drivers/pinctrl/sh-pfc/pfc-r8a7795.c

   1 /*
   2  * R8A7795 processor support - PFC hardware block.
   3  *
   4  * Copyright (C) 2015  Renesas Electronics Corporation
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  */
  10
  11 #include <linux/kernel.h>
  12
  13 #include "core.h"
  14 #include "sh_pfc.h"
  15
  16 #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
  17                    SH_PFC_PIN_CFG_PULL_UP | \
  18                    SH_PFC_PIN_CFG_PULL_DOWN)
  19
  20 #define CPU_ALL_PORT(fn, sfx)                                           \
  21         PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS),  \
  22         PORT_GP_CFG_28(1, fn, sfx, CFG_FLAGS),  \
  23         PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS),  \
  24         PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE),      \
  25         PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS),       \
  26         PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS),       \
  27         PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS),       \
  28         PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS),       \
  29         PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE),      \
  30         PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS),  \
  31         PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS),  \
  32         PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
  33 /*
  34  * F_() : just information
  35  * FM() : macro for FN_xxx / xxx_MARK
  36  */
  37
  38 /* GPSR0 */
  39 #define GPSR0_15        F_(D15,                 IP7_11_8)
  40 #define GPSR0_14        F_(D14,                 IP7_7_4)
  41 #define GPSR0_13        F_(D13,                 IP7_3_0)
  42 #define GPSR0_12        F_(D12,                 IP6_31_28)
  43 #define GPSR0_11        F_(D11,                 IP6_27_24)
  44 #define GPSR0_10        F_(D10,                 IP6_23_20)
  45 #define GPSR0_9         F_(D9,                  IP6_19_16)
  46 #define GPSR0_8         F_(D8,                  IP6_15_12)
  47 #define GPSR0_7         F_(D7,                  IP6_11_8)
  48 #define GPSR0_6         F_(D6,                  IP6_7_4)
  49 #define GPSR0_5         F_(D5,                  IP6_3_0)
  50 #define GPSR0_4         F_(D4,                  IP5_31_28)
  51 #define GPSR0_3         F_(D3,                  IP5_27_24)
  52 #define GPSR0_2         F_(D2,                  IP5_23_20)
  53 #define GPSR0_1         F_(D1,                  IP5_19_16)
  54 #define GPSR0_0         F_(D0,                  IP5_15_12)
  55
  56 /* GPSR1 */
  57 #define GPSR1_27        F_(EX_WAIT0_A,          IP5_11_8)
  58 #define GPSR1_26        F_(WE1_N,               IP5_7_4)
  59 #define GPSR1_25        F_(WE0_N,               IP5_3_0)
  60 #define GPSR1_24        F_(RD_WR_N,             IP4_31_28)
  61 #define GPSR1_23        F_(RD_N,                IP4_27_24)
  62 #define GPSR1_22        F_(BS_N,                IP4_23_20)
  63 #define GPSR1_21        F_(CS1_N_A26,           IP4_19_16)
  64 #define GPSR1_20        F_(CS0_N,               IP4_15_12)
  65 #define GPSR1_19        F_(A19,                 IP4_11_8)
  66 #define GPSR1_18        F_(A18,                 IP4_7_4)
  67 #define GPSR1_17        F_(A17,                 IP4_3_0)
  68 #define GPSR1_16        F_(A16,                 IP3_31_28)
  69 #define GPSR1_15        F_(A15,                 IP3_27_24)
  70 #define GPSR1_14        F_(A14,                 IP3_23_20)
  71 #define GPSR1_13        F_(A13,                 IP3_19_16)
  72 #define GPSR1_12        F_(A12,                 IP3_15_12)
  73 #define GPSR1_11        F_(A11,                 IP3_11_8)
  74 #define GPSR1_10        F_(A10,                 IP3_7_4)
  75 #define GPSR1_9         F_(A9,                  IP3_3_0)
  76 #define GPSR1_8         F_(A8,                  IP2_31_28)
  77 #define GPSR1_7         F_(A7,                  IP2_27_24)
  78 #define GPSR1_6         F_(A6,                  IP2_23_20)
  79 #define GPSR1_5         F_(A5,                  IP2_19_16)
  80 #define GPSR1_4         F_(A4,                  IP2_15_12)
  81 #define GPSR1_3         F_(A3,                  IP2_11_8)
  82 #define GPSR1_2         F_(A2,                  IP2_7_4)
  83 #define GPSR1_1         F_(A1,                  IP2_3_0)
  84 #define GPSR1_0         F_(A0,                  IP1_31_28)
  85
  86 /* GPSR2 */
  87 #define GPSR2_14        F_(AVB_AVTP_CAPTURE_A,  IP0_23_20)
  88 #define GPSR2_13        F_(AVB_AVTP_MATCH_A,    IP0_19_16)
  89 #define GPSR2_12        F_(AVB_LINK,            IP0_15_12)
  90 #define GPSR2_11        F_(AVB_PHY_INT,         IP0_11_8)
  91 #define GPSR2_10        F_(AVB_MAGIC,           IP0_7_4)
  92 #define GPSR2_9         F_(AVB_MDC,             IP0_3_0)
  93 #define GPSR2_8         F_(PWM2_A,              IP1_27_24)
  94 #define GPSR2_7         F_(PWM1_A,              IP1_23_20)
  95 #define GPSR2_6         F_(PWM0,                IP1_19_16)
  96 #define GPSR2_5         F_(IRQ5,                IP1_15_12)
  97 #define GPSR2_4         F_(IRQ4,                IP1_11_8)
  98 #define GPSR2_3         F_(IRQ3,                IP1_7_4)
  99 #define GPSR2_2         F_(IRQ2,                IP1_3_0)
 100 #define GPSR2_1         F_(IRQ1,                IP0_31_28)
 101 #define GPSR2_0         F_(IRQ0,                IP0_27_24)
 102
 103 /* GPSR3 */
 104 #define GPSR3_15        F_(SD1_WP,              IP10_23_20)
 105 #define GPSR3_14        F_(SD1_CD,              IP10_19_16)
 106 #define GPSR3_13        F_(SD0_WP,              IP10_15_12)
 107 #define GPSR3_12        F_(SD0_CD,              IP10_11_8)
 108 #define GPSR3_11        F_(SD1_DAT3,            IP8_31_28)
 109 #define GPSR3_10        F_(SD1_DAT2,            IP8_27_24)
 110 #define GPSR3_9         F_(SD1_DAT1,            IP8_23_20)
 111 #define GPSR3_8         F_(SD1_DAT0,            IP8_19_16)
 112 #define GPSR3_7         F_(SD1_CMD,             IP8_15_12)
 113 #define GPSR3_6         F_(SD1_CLK,             IP8_11_8)
 114 #define GPSR3_5         F_(SD0_DAT3,            IP8_7_4)
 115 #define GPSR3_4         F_(SD0_DAT2,            IP8_3_0)
 116 #define GPSR3_3         F_(SD0_DAT1,            IP7_31_28)
 117 #define GPSR3_2         F_(SD0_DAT0,            IP7_27_24)
 118 #define GPSR3_1         F_(SD0_CMD,             IP7_23_20)
 119 #define GPSR3_0         F_(SD0_CLK,             IP7_19_16)
 120
 121 /* GPSR4 */
 122 #define GPSR4_17        FM(SD3_DS)
 123 #define GPSR4_16        F_(SD3_DAT7,            IP10_7_4)
 124 #define GPSR4_15        F_(SD3_DAT6,            IP10_3_0)
 125 #define GPSR4_14        F_(SD3_DAT5,            IP9_31_28)
 126 #define GPSR4_13        F_(SD3_DAT4,            IP9_27_24)
 127 #define GPSR4_12        FM(SD3_DAT3)
 128 #define GPSR4_11        FM(SD3_DAT2)
 129 #define GPSR4_10        FM(SD3_DAT1)
 130 #define GPSR4_9         FM(SD3_DAT0)
 131 #define GPSR4_8         FM(SD3_CMD)
 132 #define GPSR4_7         FM(SD3_CLK)
 133 #define GPSR4_6         F_(SD2_DS,              IP9_23_20)
 134 #define GPSR4_5         F_(SD2_DAT3,            IP9_19_16)
 135 #define GPSR4_4         F_(SD2_DAT2,            IP9_15_12)
 136 #define GPSR4_3         F_(SD2_DAT1,            IP9_11_8)
 137 #define GPSR4_2         F_(SD2_DAT0,            IP9_7_4)
 138 #define GPSR4_1         FM(SD2_CMD)
 139 #define GPSR4_0         F_(SD2_CLK,             IP9_3_0)
 140
 141 /* GPSR5 */
 142 #define GPSR5_25        F_(MLB_DAT,             IP13_19_16)
 143 #define GPSR5_24        F_(MLB_SIG,             IP13_15_12)
 144 #define GPSR5_23        F_(MLB_CLK,             IP13_11_8)
 145 #define GPSR5_22        FM(MSIOF0_RXD)
 146 #define GPSR5_21        F_(MSIOF0_SS2,          IP13_7_4)
 147 #define GPSR5_20        FM(MSIOF0_TXD)
 148 #define GPSR5_19        F_(MSIOF0_SS1,          IP13_3_0)
 149 #define GPSR5_18        F_(MSIOF0_SYNC,         IP12_31_28)
 150 #define GPSR5_17        FM(MSIOF0_SCK)
 151 #define GPSR5_16        F_(HRTS0_N,             IP12_27_24)
 152 #define GPSR5_15        F_(HCTS0_N,             IP12_23_20)
 153 #define GPSR5_14        F_(HTX0,                IP12_19_16)
 154 #define GPSR5_13        F_(HRX0,                IP12_15_12)
 155 #define GPSR5_12        F_(HSCK0,               IP12_11_8)
 156 #define GPSR5_11        F_(RX2_A,               IP12_7_4)
 157 #define GPSR5_10        F_(TX2_A,               IP12_3_0)
 158 #define GPSR5_9         F_(SCK2,                IP11_31_28)
 159 #define GPSR5_8         F_(RTS1_N_TANS,         IP11_27_24)
 160 #define GPSR5_7         F_(CTS1_N,              IP11_23_20)
 161 #define GPSR5_6         F_(TX1_A,               IP11_19_16)
 162 #define GPSR5_5         F_(RX1_A,               IP11_15_12)
 163 #define GPSR5_4         F_(RTS0_N_TANS,         IP11_11_8)
 164 #define GPSR5_3         F_(CTS0_N,              IP11_7_4)
 165 #define GPSR5_2         F_(TX0,                 IP11_3_0)
 166 #define GPSR5_1         F_(RX0,                 IP10_31_28)
 167 #define GPSR5_0         F_(SCK0,                IP10_27_24)
 168
 169 /* GPSR6 */
 170 #define GPSR6_31        F_(USB31_OVC,           IP17_7_4)
 171 #define GPSR6_30        F_(USB31_PWEN,          IP17_3_0)
 172 #define GPSR6_29        F_(USB30_OVC,           IP16_31_28)
 173 #define GPSR6_28        F_(USB30_PWEN,          IP16_27_24)
 174 #define GPSR6_27        F_(USB1_OVC,            IP16_23_20)
 175 #define GPSR6_26        F_(USB1_PWEN,           IP16_19_16)
 176 #define GPSR6_25        F_(USB0_OVC,            IP16_15_12)
 177 #define GPSR6_24        F_(USB0_PWEN,           IP16_11_8)
 178 #define GPSR6_23        F_(AUDIO_CLKB_B,        IP16_7_4)
 179 #define GPSR6_22        F_(AUDIO_CLKA_A,        IP16_3_0)
 180 #define GPSR6_21        F_(SSI_SDATA9_A,        IP15_31_28)
 181 #define GPSR6_20        F_(SSI_SDATA8,          IP15_27_24)
 182 #define GPSR6_19        F_(SSI_SDATA7,          IP15_23_20)
 183 #define GPSR6_18        F_(SSI_WS78,            IP15_19_16)
 184 #define GPSR6_17        F_(SSI_SCK78,           IP15_15_12)
 185 #define GPSR6_16        F_(SSI_SDATA6,          IP15_11_8)
 186 #define GPSR6_15        F_(SSI_WS6,             IP15_7_4)
 187 #define GPSR6_14        F_(SSI_SCK6,            IP15_3_0)
 188 #define GPSR6_13        FM(SSI_SDATA5)
 189 #define GPSR6_12        FM(SSI_WS5)
 190 #define GPSR6_11        FM(SSI_SCK5)
 191 #define GPSR6_10        F_(SSI_SDATA4,          IP14_31_28)
 192 #define GPSR6_9         F_(SSI_WS4,             IP14_27_24)
 193 #define GPSR6_8         F_(SSI_SCK4,            IP14_23_20)
 194 #define GPSR6_7         F_(SSI_SDATA3,          IP14_19_16)
 195 #define GPSR6_6         F_(SSI_WS34,            IP14_15_12)
 196 #define GPSR6_5         F_(SSI_SCK34,           IP14_11_8)
 197 #define GPSR6_4         F_(SSI_SDATA2_A,        IP14_7_4)
 198 #define GPSR6_3         F_(SSI_SDATA1_A,        IP14_3_0)
 199 #define GPSR6_2         F_(SSI_SDATA0,          IP13_31_28)
 200 #define GPSR6_1         F_(SSI_WS01239,         IP13_27_24)
 201 #define GPSR6_0         F_(SSI_SCK01239,        IP13_23_20)
 202
 203 /* GPSR7 */
 204 #define GPSR7_3         FM(HDMI1_CEC)
 205 #define GPSR7_2         FM(HDMI0_CEC)
 206 #define GPSR7_1         FM(AVS2)
 207 #define GPSR7_0         FM(AVS1)
 208
 209
 210 /* IPSRx */             /* 0 */                 /* 1 */         /* 2 */                 /* 3 */                         /* 4 */         /* 5 */         /* 6 */                 /* 7 */         /* 8 */                 /* 9 */         /* A */         /* B */         /* C - F */
 211 #define IP0_3_0         FM(AVB_MDC)             F_(0, 0)        FM(MSIOF2_SS2_C)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 212 #define IP0_7_4         FM(AVB_MAGIC)           F_(0, 0)        FM(MSIOF2_SS1_C)        FM(SCK4_A)                      F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 213 #define IP0_11_8        FM(AVB_PHY_INT)         F_(0, 0)        FM(MSIOF2_SYNC_C)       FM(RX4_A)                       F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 214 #define IP0_15_12       FM(AVB_LINK)            F_(0, 0)        FM(MSIOF2_SCK_C)        FM(TX4_A)                       F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 215 #define IP0_19_16       FM(AVB_AVTP_MATCH_A)    F_(0, 0)        FM(MSIOF2_RXD_C)        FM(CTS4_N_A)                    F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 216 #define IP0_23_20       FM(AVB_AVTP_CAPTURE_A)  F_(0, 0)        FM(MSIOF2_TXD_C)        FM(RTS4_N_TANS_A)               F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 217 #define IP0_27_24       FM(IRQ0)                FM(QPOLB)       F_(0, 0)                FM(DU_CDE)                      FM(VI4_DATA0_B) FM(CAN0_TX_B)   FM(CANFD0_TX_B)         F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 218 #define IP0_31_28       FM(IRQ1)                FM(QPOLA)       F_(0, 0)                FM(DU_DISP)                     FM(VI4_DATA1_B) FM(CAN0_RX_B)   FM(CANFD0_RX_B)         F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 219 #define IP1_3_0         FM(IRQ2)                FM(QCPV_QDE)    F_(0, 0)                FM(DU_EXODDF_DU_ODDF_DISP_CDE)  FM(VI4_DATA2_B) F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                FM(PWM3_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 220 #define IP1_7_4         FM(IRQ3)                FM(QSTVB_QVE)   FM(A25)                 FM(DU_DOTCLKOUT1)               FM(VI4_DATA3_B) F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                FM(PWM4_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 221 #define IP1_11_8        FM(IRQ4)                FM(QSTH_QHS)    FM(A24)                 FM(DU_EXHSYNC_DU_HSYNC)         FM(VI4_DATA4_B) F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                FM(PWM5_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 222 #define IP1_15_12       FM(IRQ5)                FM(QSTB_QHE)    FM(A23)                 FM(DU_EXVSYNC_DU_VSYNC)         FM(VI4_DATA5_B) F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                FM(PWM6_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 223 #define IP1_19_16       FM(PWM0)                FM(AVB_AVTP_PPS)FM(A22)                 F_(0, 0)                        FM(VI4_DATA6_B) F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                FM(IECLK_B)     F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 224 #define IP1_23_20       FM(PWM1_A)              F_(0, 0)        FM(A21)                 FM(HRX3_D)                      FM(VI4_DATA7_B) F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                FM(IERX_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 225 #define IP1_27_24       FM(PWM2_A)              F_(0, 0)        FM(A20)                 FM(HTX3_D)                      F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                FM(IETX_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 226 #define IP1_31_28       FM(A0)                  FM(LCDOUT16)    FM(MSIOF3_SYNC_B)       F_(0, 0)                        FM(VI4_DATA8)   F_(0, 0)        FM(DU_DB0)              F_(0, 0)        F_(0, 0)                FM(PWM3_A)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 227 #define IP2_3_0         FM(A1)                  FM(LCDOUT17)    FM(MSIOF3_TXD_B)        F_(0, 0)                        FM(VI4_DATA9)   F_(0, 0)        FM(DU_DB1)              F_(0, 0)        F_(0, 0)                FM(PWM4_A)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 228 #define IP2_7_4         FM(A2)                  FM(LCDOUT18)    FM(MSIOF3_SCK_B)        F_(0, 0)                        FM(VI4_DATA10)  F_(0, 0)        FM(DU_DB2)              F_(0, 0)        F_(0, 0)                FM(PWM5_A)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 229 #define IP2_11_8        FM(A3)                  FM(LCDOUT19)    FM(MSIOF3_RXD_B)        F_(0, 0)                        FM(VI4_DATA11)  F_(0, 0)        FM(DU_DB3)              F_(0, 0)        F_(0, 0)                FM(PWM6_A)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 230
 231 /* IPSRx */             /* 0 */                 /* 1 */         /* 2 */                 /* 3 */                         /* 4 */         /* 5 */         /* 6 */                 /* 7 */         /* 8 */                 /* 9 */         /* A */         /* B */         /* C - F */
 232 #define IP2_15_12       FM(A4)                  FM(LCDOUT20)    FM(MSIOF3_SS1_B)        F_(0, 0)                        FM(VI4_DATA12)  FM(VI5_DATA12)  FM(DU_DB4)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 233 #define IP2_19_16       FM(A5)                  FM(LCDOUT21)    FM(MSIOF3_SS2_B)        FM(SCK4_B)                      FM(VI4_DATA13)  FM(VI5_DATA13)  FM(DU_DB5)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 234 #define IP2_23_20       FM(A6)                  FM(LCDOUT22)    FM(MSIOF2_SS1_A)        FM(RX4_B)                       FM(VI4_DATA14)  FM(VI5_DATA14)  FM(DU_DB6)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 235 #define IP2_27_24       FM(A7)                  FM(LCDOUT23)    FM(MSIOF2_SS2_A)        FM(TX4_B)                       FM(VI4_DATA15)  FM(VI5_DATA15)  FM(DU_DB7)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 236 #define IP2_31_28       FM(A8)                  FM(RX3_B)       FM(MSIOF2_SYNC_A)       FM(HRX4_B)                      F_(0, 0)        F_(0, 0)        F_(0, 0)                FM(SDA6_A)      FM(AVB_AVTP_MATCH_B)    FM(PWM1_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 237 #define IP3_3_0         FM(A9)                  F_(0, 0)        FM(MSIOF2_SCK_A)        FM(CTS4_N_B)                    F_(0, 0)        FM(VI5_VSYNC_N) F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 238 #define IP3_7_4         FM(A10)                 F_(0, 0)        FM(MSIOF2_RXD_A)        FM(RTS4_N_TANS_B)               F_(0, 0)        FM(VI5_HSYNC_N) F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 239 #define IP3_11_8        FM(A11)                 FM(TX3_B)       FM(MSIOF2_TXD_A)        FM(HTX4_B)                      FM(HSCK4)       FM(VI5_FIELD)   F_(0, 0)                FM(SCL6_A)      FM(AVB_AVTP_CAPTURE_B)  FM(PWM2_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 240 #define IP3_15_12       FM(A12)                 FM(LCDOUT12)    FM(MSIOF3_SCK_C)        F_(0, 0)                        FM(HRX4_A)      FM(VI5_DATA8)   FM(DU_DG4)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 241 #define IP3_19_16       FM(A13)                 FM(LCDOUT13)    FM(MSIOF3_SYNC_C)       F_(0, 0)                        FM(HTX4_A)      FM(VI5_DATA9)   FM(DU_DG5)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 242 #define IP3_23_20       FM(A14)                 FM(LCDOUT14)    FM(MSIOF3_RXD_C)        F_(0, 0)                        FM(HCTS4_N)     FM(VI5_DATA10)  FM(DU_DG6)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 243 #define IP3_27_24       FM(A15)                 FM(LCDOUT15)    FM(MSIOF3_TXD_C)        F_(0, 0)                        FM(HRTS4_N)     FM(VI5_DATA11)  FM(DU_DG7)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 244 #define IP3_31_28       FM(A16)                 FM(LCDOUT8)     F_(0, 0)                F_(0, 0)                        FM(VI4_FIELD)   F_(0, 0)        FM(DU_DG0)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 245 #define IP4_3_0         FM(A17)                 FM(LCDOUT9)     F_(0, 0)                F_(0, 0)                        FM(VI4_VSYNC_N) F_(0, 0)        FM(DU_DG1)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 246 #define IP4_7_4         FM(A18)                 FM(LCDOUT10)    F_(0, 0)                F_(0, 0)                        FM(VI4_HSYNC_N) F_(0, 0)        FM(DU_DG2)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 247 #define IP4_11_8        FM(A19)                 FM(LCDOUT11)    F_(0, 0)                F_(0, 0)                        FM(VI4_CLKENB)  F_(0, 0)        FM(DU_DG3)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 248 #define IP4_15_12       FM(CS0_N)               F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(VI5_CLKENB)  F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 249 #define IP4_19_16       FM(CS1_N_A26)           F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(VI5_CLK)     F_(0, 0)                FM(EX_WAIT0_B)  F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 250 #define IP4_23_20       FM(BS_N)                FM(QSTVA_QVS)   FM(MSIOF3_SCK_D)        FM(SCK3)                        FM(HSCK3)       F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(CAN1_TX)             FM(CANFD1_TX)   FM(IETX_A)      F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 251 #define IP4_27_24       FM(RD_N)                F_(0, 0)        FM(MSIOF3_SYNC_D)       FM(RX3_A)                       FM(HRX3_A)      F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(CAN0_TX_A)           FM(CANFD0_TX_A) F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 252 #define IP4_31_28       FM(RD_WR_N)             F_(0, 0)        FM(MSIOF3_RXD_D)        FM(TX3_A)                       FM(HTX3_A)      F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(CAN0_RX_A)           FM(CANFD0_RX_A) F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 253 #define IP5_3_0         FM(WE0_N)               F_(0, 0)        FM(MSIOF3_TXD_D)        FM(CTS3_N)                      FM(HCTS3_N)     F_(0, 0)        F_(0, 0)                FM(SCL6_B)      FM(CAN_CLK)             F_(0, 0)        FM(IECLK_A)     F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 254 #define IP5_7_4         FM(WE1_N)               F_(0, 0)        FM(MSIOF3_SS1_D)        FM(RTS3_N_TANS)                 FM(HRTS3_N)     F_(0, 0)        F_(0, 0)                FM(SDA6_B)      FM(CAN1_RX)             FM(CANFD1_RX)   FM(IERX_A)      F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 255 #define IP5_11_8        FM(EX_WAIT0_A)          FM(QCLK)        F_(0, 0)                F_(0, 0)                        FM(VI4_CLK)     F_(0, 0)        FM(DU_DOTCLKOUT0)       F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 256 #define IP5_15_12       FM(D0)                  FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A)        F_(0, 0)                        FM(VI4_DATA16)  FM(VI5_DATA0)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 257 #define IP5_19_16       FM(D1)                  FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A)       F_(0, 0)                        FM(VI4_DATA17)  FM(VI5_DATA1)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 258 #define IP5_23_20       FM(D2)                  F_(0, 0)        FM(MSIOF3_RXD_A)        F_(0, 0)                        FM(VI4_DATA18)  FM(VI5_DATA2)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 259 #define IP5_27_24       FM(D3)                  F_(0, 0)        FM(MSIOF3_TXD_A)        F_(0, 0)                        FM(VI4_DATA19)  FM(VI5_DATA3)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 260 #define IP5_31_28       FM(D4)                  FM(MSIOF2_SCK_B)F_(0, 0)                F_(0, 0)                        FM(VI4_DATA20)  FM(VI5_DATA4)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 261 #define IP6_3_0         FM(D5)                  FM(MSIOF2_SYNC_B)F_(0, 0)               F_(0, 0)                        FM(VI4_DATA21)  FM(VI5_DATA5)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 262 #define IP6_7_4         FM(D6)                  FM(MSIOF2_RXD_B)F_(0, 0)                F_(0, 0)                        FM(VI4_DATA22)  FM(VI5_DATA6)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 263 #define IP6_11_8        FM(D7)                  FM(MSIOF2_TXD_B)F_(0, 0)                F_(0, 0)                        FM(VI4_DATA23)  FM(VI5_DATA7)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 264 #define IP6_15_12       FM(D8)                  FM(LCDOUT0)     FM(MSIOF2_SCK_D)        FM(SCK4_C)                      FM(VI4_DATA0_A) F_(0, 0)        FM(DU_DR0)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 265 #define IP6_19_16       FM(D9)                  FM(LCDOUT1)     FM(MSIOF2_SYNC_D)       F_(0, 0)                        FM(VI4_DATA1_A) F_(0, 0)        FM(DU_DR1)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 266 #define IP6_23_20       FM(D10)                 FM(LCDOUT2)     FM(MSIOF2_RXD_D)        FM(HRX3_B)                      FM(VI4_DATA2_A) FM(CTS4_N_C)    FM(DU_DR2)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 267 #define IP6_27_24       FM(D11)                 FM(LCDOUT3)     FM(MSIOF2_TXD_D)        FM(HTX3_B)                      FM(VI4_DATA3_A) FM(RTS4_N_TANS_C)FM(DU_DR3)             F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 268 #define IP6_31_28       FM(D12)                 FM(LCDOUT4)     FM(MSIOF2_SS1_D)        FM(RX4_C)                       FM(VI4_DATA4_A) F_(0, 0)        FM(DU_DR4)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 269 #define IP7_3_0         FM(D13)                 FM(LCDOUT5)     FM(MSIOF2_SS2_D)        FM(TX4_C)                       FM(VI4_DATA5_A) F_(0, 0)        FM(DU_DR5)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 270 #define IP7_7_4         FM(D14)                 FM(LCDOUT6)     FM(MSIOF3_SS1_A)        FM(HRX3_C)                      FM(VI4_DATA6_A) F_(0, 0)        FM(DU_DR6)              FM(SCL6_C)      F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 271 #define IP7_11_8        FM(D15)                 FM(LCDOUT7)     FM(MSIOF3_SS2_A)        FM(HTX3_C)                      FM(VI4_DATA7_A) F_(0, 0)        FM(DU_DR7)              FM(SDA6_C)      F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 272 #define IP7_15_12       FM(FSCLKST)             F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 273 #define IP7_19_16       FM(SD0_CLK)             F_(0, 0)        FM(MSIOF1_SCK_E)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_OPWM_0_B)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 274
 275 /* IPSRx */             /* 0 */                 /* 1 */         /* 2 */                 /* 3 */                         /* 4 */         /* 5 */         /* 6 */                 /* 7 */         /* 8 */                 /* 9 */         /* A */         /* B */         /* C - F */
 276 #define IP7_23_20       FM(SD0_CMD)             F_(0, 0)        FM(MSIOF1_SYNC_E)       F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_IVCXO27_0_B)     F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 277 #define IP7_27_24       FM(SD0_DAT0)            F_(0, 0)        FM(MSIOF1_RXD_E)        F_(0, 0)                        F_(0, 0)        FM(TS_SCK0_B)   FM(STP_ISCLK_0_B)       F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 278 #define IP7_31_28       FM(SD0_DAT1)            F_(0, 0)        FM(MSIOF1_TXD_E)        F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 279 #define IP8_3_0         FM(SD0_DAT2)            F_(0, 0)        FM(MSIOF1_SS1_E)        F_(0, 0)                        F_(0, 0)        FM(TS_SDAT0_B)  FM(STP_ISD_0_B)         F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 280 #define IP8_7_4         FM(SD0_DAT3)            F_(0, 0)        FM(MSIOF1_SS2_E)        F_(0, 0)                        F_(0, 0)        FM(TS_SDEN0_B)  FM(STP_ISEN_0_B)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 281 #define IP8_11_8        FM(SD1_CLK)             F_(0, 0)        FM(MSIOF1_SCK_G)        F_(0, 0)                        F_(0, 0)        FM(SIM0_CLK_A)  F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 282 #define IP8_15_12       FM(SD1_CMD)             F_(0, 0)        FM(MSIOF1_SYNC_G)       F_(0, 0)                        F_(0, 0)        FM(SIM0_D_A)    FM(STP_IVCXO27_1_B)     F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 283 #define IP8_19_16       FM(SD1_DAT0)            FM(SD2_DAT4)    FM(MSIOF1_RXD_G)        F_(0, 0)                        F_(0, 0)        FM(TS_SCK1_B)   FM(STP_ISCLK_1_B)       F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 284 #define IP8_23_20       FM(SD1_DAT1)            FM(SD2_DAT5)    FM(MSIOF1_TXD_G)        F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 285 #define IP8_27_24       FM(SD1_DAT2)            FM(SD2_DAT6)    FM(MSIOF1_SS1_G)        F_(0, 0)                        F_(0, 0)        FM(TS_SDAT1_B)  FM(STP_ISD_1_B)         F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 286 #define IP8_31_28       FM(SD1_DAT3)            FM(SD2_DAT7)    FM(MSIOF1_SS2_G)        F_(0, 0)                        F_(0, 0)        FM(TS_SDEN1_B)  FM(STP_ISEN_1_B)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 287 #define IP9_3_0         FM(SD2_CLK)             F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 288 #define IP9_7_4         FM(SD2_DAT0)            F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 289 #define IP9_11_8        FM(SD2_DAT1)            F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 290 #define IP9_15_12       FM(SD2_DAT2)            F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 291 #define IP9_19_16       FM(SD2_DAT3)            F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 292 #define IP9_23_20       FM(SD2_DS)              F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(SATA_DEVSLP_B)       F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 293 #define IP9_27_24       FM(SD3_DAT4)            FM(SD2_CD_A)    F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 294 #define IP9_31_28       FM(SD3_DAT5)            FM(SD2_WP_A)    F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 295 #define IP10_3_0        FM(SD3_DAT6)            FM(SD3_CD)      F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 296 #define IP10_7_4        FM(SD3_DAT7)            FM(SD3_WP)      F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 297 #define IP10_11_8       FM(SD0_CD)              F_(0, 0)        F_(0, 0)                F_(0, 0)                        FM(SCL2_B)      FM(SIM0_RST_A)  F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 298 #define IP10_15_12      FM(SD0_WP)              F_(0, 0)        F_(0, 0)                F_(0, 0)                        FM(SDA2_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 299 #define IP10_19_16      FM(SD1_CD)              F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(SIM0_CLK_B)  F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 300 #define IP10_23_20      FM(SD1_WP)              F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(SIM0_D_B)    F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 301 #define IP10_27_24      FM(SCK0)                FM(HSCK1_B)     FM(MSIOF1_SS2_B)        FM(AUDIO_CLKC_B)                FM(SDA2_A)      FM(SIM0_RST_B)  FM(STP_OPWM_0_C)        FM(RIF0_CLK_B)  F_(0, 0)                FM(ADICHS2)     F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 302 #define IP10_31_28      FM(RX0)                 FM(HRX1_B)      F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(TS_SCK0_C)   FM(STP_ISCLK_0_C)       FM(RIF0_D0_B)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 303 #define IP11_3_0        FM(TX0)                 FM(HTX1_B)      F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C)      FM(RIF0_D1_B)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 304 #define IP11_7_4        FM(CTS0_N)              FM(HCTS1_N_B)   FM(MSIOF1_SYNC_B)       F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C)      FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C)      FM(ADICS_SAMP)  F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 305 #define IP11_11_8       FM(RTS0_N_TANS)         FM(HRTS1_N_B)   FM(MSIOF1_SS1_B)        FM(AUDIO_CLKA_B)                FM(SCL2_A)      F_(0, 0)        FM(STP_IVCXO27_1_C)     FM(RIF0_SYNC_B) F_(0, 0)                FM(ADICHS1)     F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 306 #define IP11_15_12      FM(RX1_A)               FM(HRX1_A)      F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(TS_SDAT0_C)  FM(STP_ISD_0_C)         FM(RIF1_CLK_C)  F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 307 #define IP11_19_16      FM(TX1_A)               FM(HTX1_A)      F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(TS_SDEN0_C)  FM(STP_ISEN_0_C)        FM(RIF1_D0_C)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 308 #define IP11_23_20      FM(CTS1_N)              FM(HCTS1_N_A)   FM(MSIOF1_RXD_B)        F_(0, 0)                        F_(0, 0)        FM(TS_SDEN1_C)  FM(STP_ISEN_1_C)        FM(RIF1_D0_B)   F_(0, 0)                FM(ADIDATA)     F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 309 #define IP11_27_24      FM(RTS1_N_TANS)         FM(HRTS1_N_A)   FM(MSIOF1_TXD_B)        F_(0, 0)                        F_(0, 0)        FM(TS_SDAT1_C)  FM(STP_ISD_1_C)         FM(RIF1_D1_B)   F_(0, 0)                FM(ADICHS0)     F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 310 #define IP11_31_28      FM(SCK2)                FM(SCIF_CLK_B)  FM(MSIOF1_SCK_B)        F_(0, 0)                        F_(0, 0)        FM(TS_SCK1_C)   FM(STP_ISCLK_1_C)       FM(RIF1_CLK_B)  F_(0, 0)                FM(ADICLK)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 311 #define IP12_3_0        FM(TX2_A)               F_(0, 0)        F_(0, 0)                FM(SD2_CD_B)                    FM(SCL1_A)      F_(0, 0)        FM(FMCLK_A)             FM(RIF1_D1_C)   F_(0, 0)                FM(FSO_CFE_0_B) F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 312 #define IP12_7_4        FM(RX2_A)               F_(0, 0)        F_(0, 0)                FM(SD2_WP_B)                    FM(SDA1_A)      F_(0, 0)        FM(FMIN_A)              FM(RIF1_SYNC_C) F_(0, 0)                FM(FSO_CFE_1_B) F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 313 #define IP12_11_8       FM(HSCK0)               F_(0, 0)        FM(MSIOF1_SCK_D)        FM(AUDIO_CLKB_A)                FM(SSI_SDATA1_B)FM(TS_SCK0_D)   FM(STP_ISCLK_0_D)       FM(RIF0_CLK_C)  F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 314 #define IP12_15_12      FM(HRX0)                F_(0, 0)        FM(MSIOF1_RXD_D)        F_(0, 0)                        FM(SSI_SDATA2_B)FM(TS_SDEN0_D)  FM(STP_ISEN_0_D)        FM(RIF0_D0_C)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 315 #define IP12_19_16      FM(HTX0)                F_(0, 0)        FM(MSIOF1_TXD_D)        F_(0, 0)                        FM(SSI_SDATA9_B)FM(TS_SDAT0_D)  FM(STP_ISD_0_D)         FM(RIF0_D1_C)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 316 #define IP12_23_20      FM(HCTS0_N)             FM(RX2_B)       FM(MSIOF1_SYNC_D)       F_(0, 0)                        FM(SSI_SCK9_A)  FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D)      FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A)     F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 317 #define IP12_27_24      FM(HRTS0_N)             FM(TX2_B)       FM(MSIOF1_SS1_D)        F_(0, 0)                        FM(SSI_WS9_A)   F_(0, 0)        FM(STP_IVCXO27_0_D)     FM(BPFCLK_A)    FM(AUDIO_CLKOUT2_A)     F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 318
 319 /* IPSRx */             /* 0 */                 /* 1 */         /* 2 */                 /* 3 */                         /* 4 */         /* 5 */         /* 6 */                 /* 7 */         /* 8 */                 /* 9 */         /* A */         /* B */         /* C - F */
 320 #define IP12_31_28      FM(MSIOF0_SYNC)         F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(AUDIO_CLKOUT_A)      F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 321 #define IP13_3_0        FM(MSIOF0_SS1)          FM(RX5)         F_(0, 0)                FM(AUDIO_CLKA_C)                FM(SSI_SCK2_A)  F_(0, 0)        FM(STP_IVCXO27_0_C)     F_(0, 0)        FM(AUDIO_CLKOUT3_A)     F_(0, 0)        FM(TCLK1_B)     F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 322 #define IP13_7_4        FM(MSIOF0_SS2)          FM(TX5)         FM(MSIOF1_SS2_D)        FM(AUDIO_CLKC_A)                FM(SSI_WS2_A)   F_(0, 0)        FM(STP_OPWM_0_D)        F_(0, 0)        FM(AUDIO_CLKOUT_D)      F_(0, 0)        FM(SPEEDIN_B)   F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 323 #define IP13_11_8       FM(MLB_CLK)             F_(0, 0)        FM(MSIOF1_SCK_F)        F_(0, 0)                        FM(SCL1_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 324 #define IP13_15_12      FM(MLB_SIG)             FM(RX1_B)       FM(MSIOF1_SYNC_F)       F_(0, 0)                        FM(SDA1_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 325 #define IP13_19_16      FM(MLB_DAT)             FM(TX1_B)       FM(MSIOF1_RXD_F)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 326 #define IP13_23_20      FM(SSI_SCK01239)        F_(0, 0)        FM(MSIOF1_TXD_F)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 327 #define IP13_27_24      FM(SSI_WS01239)         F_(0, 0)        FM(MSIOF1_SS1_F)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 328 #define IP13_31_28      FM(SSI_SDATA0)          F_(0, 0)        FM(MSIOF1_SS2_F)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 329 #define IP14_3_0        FM(SSI_SDATA1_A)        F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 330 #define IP14_7_4        FM(SSI_SDATA2_A)        F_(0, 0)        F_(0, 0)                F_(0, 0)                        FM(SSI_SCK1_B)  F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 331 #define IP14_11_8       FM(SSI_SCK34)           F_(0, 0)        FM(MSIOF1_SS1_A)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_OPWM_0_A)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 332 #define IP14_15_12      FM(SSI_WS34)            FM(HCTS2_N_A)   FM(MSIOF1_SS2_A)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_IVCXO27_0_A)     F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 333 #define IP14_19_16      FM(SSI_SDATA3)          FM(HRTS2_N_A)   FM(MSIOF1_TXD_A)        F_(0, 0)                        F_(0, 0)        FM(TS_SCK0_A)   FM(STP_ISCLK_0_A)       FM(RIF0_D1_A)   FM(RIF2_D0_A)           F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 334 #define IP14_23_20      FM(SSI_SCK4)            FM(HRX2_A)      FM(MSIOF1_SCK_A)        F_(0, 0)                        F_(0, 0)        FM(TS_SDAT0_A)  FM(STP_ISD_0_A)         FM(RIF0_CLK_A)  FM(RIF2_CLK_A)          F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 335 #define IP14_27_24      FM(SSI_WS4)             FM(HTX2_A)      FM(MSIOF1_SYNC_A)       F_(0, 0)                        F_(0, 0)        FM(TS_SDEN0_A)  FM(STP_ISEN_0_A)        FM(RIF0_SYNC_A) FM(RIF2_SYNC_A)         F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 336 #define IP14_31_28      FM(SSI_SDATA4)          FM(HSCK2_A)     FM(MSIOF1_RXD_A)        F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A)      FM(RIF0_D0_A)   FM(RIF2_D1_A)           F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 337 #define IP15_3_0        FM(SSI_SCK6)            FM(USB2_PWEN)   F_(0, 0)                FM(SIM0_RST_D)                  F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 338 #define IP15_7_4        FM(SSI_WS6)             FM(USB2_OVC)    F_(0, 0)                FM(SIM0_D_D)                    F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 339 #define IP15_11_8       FM(SSI_SDATA6)          F_(0, 0)        F_(0, 0)                FM(SIM0_CLK_D)                  F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(SATA_DEVSLP_A)       F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 340 #define IP15_15_12      FM(SSI_SCK78)           FM(HRX2_B)      FM(MSIOF1_SCK_C)        F_(0, 0)                        F_(0, 0)        FM(TS_SCK1_A)   FM(STP_ISCLK_1_A)       FM(RIF1_CLK_A)  FM(RIF3_CLK_A)          F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 341 #define IP15_19_16      FM(SSI_WS78)            FM(HTX2_B)      FM(MSIOF1_SYNC_C)       F_(0, 0)                        F_(0, 0)        FM(TS_SDAT1_A)  FM(STP_ISD_1_A)         FM(RIF1_SYNC_A) FM(RIF3_SYNC_A)         F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 342 #define IP15_23_20      FM(SSI_SDATA7)          FM(HCTS2_N_B)   FM(MSIOF1_RXD_C)        F_(0, 0)                        F_(0, 0)        FM(TS_SDEN1_A)  FM(STP_ISEN_1_A)        FM(RIF1_D0_A)   FM(RIF3_D0_A)           F_(0, 0)        FM(TCLK2_A)     F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 343 #define IP15_27_24      FM(SSI_SDATA8)          FM(HRTS2_N_B)   FM(MSIOF1_TXD_C)        F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A)      FM(RIF1_D1_A)   FM(RIF3_D1_A)           F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 344 #define IP15_31_28      FM(SSI_SDATA9_A)        FM(HSCK2_B)     FM(MSIOF1_SS1_C)        FM(HSCK1_A)                     FM(SSI_WS1_B)   FM(SCK1)        FM(STP_IVCXO27_1_A)     FM(SCK5)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 345 #define IP16_3_0        FM(AUDIO_CLKA_A)        F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        FM(CC5_OSCOUT)  F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 346 #define IP16_7_4        FM(AUDIO_CLKB_B)        FM(SCIF_CLK_A)  F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_IVCXO27_1_D)     FM(REMOCON_A)   F_(0, 0)                F_(0, 0)        FM(TCLK1_A)     F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 347 #define IP16_11_8       FM(USB0_PWEN)           F_(0, 0)        F_(0, 0)                FM(SIM0_RST_C)                  F_(0, 0)        FM(TS_SCK1_D)   FM(STP_ISCLK_1_D)       FM(BPFCLK_B)    FM(RIF3_CLK_B)          F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 348 #define IP16_15_12      FM(USB0_OVC)            F_(0, 0)        F_(0, 0)                FM(SIM0_D_C)                    F_(0, 0)        FM(TS_SDAT1_D)  FM(STP_ISD_1_D)         F_(0, 0)        FM(RIF3_SYNC_B)         F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 349 #define IP16_19_16      FM(USB1_PWEN)           F_(0, 0)        F_(0, 0)                FM(SIM0_CLK_C)                  FM(SSI_SCK1_A)  FM(TS_SCK0_E)   FM(STP_ISCLK_0_E)       FM(FMCLK_B)     FM(RIF2_CLK_B)          F_(0, 0)        FM(SPEEDIN_A)   F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 350 #define IP16_23_20      FM(USB1_OVC)            F_(0, 0)        FM(MSIOF1_SS2_C)        F_(0, 0)                        FM(SSI_WS1_A)   FM(TS_SDAT0_E)  FM(STP_ISD_0_E)         FM(FMIN_B)      FM(RIF2_SYNC_B)         F_(0, 0)        FM(REMOCON_B)   F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 351 #define IP16_27_24      FM(USB30_PWEN)          F_(0, 0)        F_(0, 0)                FM(AUDIO_CLKOUT_B)              FM(SSI_SCK2_B)  FM(TS_SDEN1_D)  FM(STP_ISEN_1_D)        FM(STP_OPWM_0_E)FM(RIF3_D0_B)           F_(0, 0)        FM(TCLK2_B)     FM(TPU0TO0)     F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 352 #define IP16_31_28      FM(USB30_OVC)           F_(0, 0)        F_(0, 0)                FM(AUDIO_CLKOUT1_B)             FM(SSI_WS2_B)   FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D)      FM(STP_IVCXO27_0_E)FM(RIF3_D1_B)        F_(0, 0)        FM(FSO_TOE_B)   FM(TPU0TO1)     F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 353 #define IP17_3_0        FM(USB31_PWEN)          F_(0, 0)        F_(0, 0)                FM(AUDIO_CLKOUT2_B)             FM(SSI_SCK9_B)  FM(TS_SDEN0_E)  FM(STP_ISEN_0_E)        F_(0, 0)        FM(RIF2_D0_B)           F_(0, 0)        F_(0, 0)        FM(TPU0TO2)     F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 354 #define IP17_7_4        FM(USB31_OVC)           F_(0, 0)        F_(0, 0)                FM(AUDIO_CLKOUT3_B)             FM(SSI_WS9_B)   FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E)      F_(0, 0)        FM(RIF2_D1_B)           F_(0, 0)        F_(0, 0)        FM(TPU0TO3)     F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 355
 356 #define PINMUX_GPSR     \
 357 \
 358                                                                                                 GPSR6_31 \
 359                                                                                                 GPSR6_30 \
 360                                                                                                 GPSR6_29 \
 361                                                                                                 GPSR6_28 \
 362                 GPSR1_27                                                                        GPSR6_27 \
 363                 GPSR1_26                                                                        GPSR6_26 \
 364                 GPSR1_25                                                        GPSR5_25        GPSR6_25 \
 365                 GPSR1_24                                                        GPSR5_24        GPSR6_24 \
 366                 GPSR1_23                                                        GPSR5_23        GPSR6_23 \
 367                 GPSR1_22                                                        GPSR5_22        GPSR6_22 \
 368                 GPSR1_21                                                        GPSR5_21        GPSR6_21 \
 369                 GPSR1_20                                                        GPSR5_20        GPSR6_20 \
 370                 GPSR1_19                                                        GPSR5_19        GPSR6_19 \
 371                 GPSR1_18                                                        GPSR5_18        GPSR6_18 \
 372                 GPSR1_17                                        GPSR4_17        GPSR5_17        GPSR6_17 \
 373                 GPSR1_16                                        GPSR4_16        GPSR5_16        GPSR6_16 \
 374 GPSR0_15        GPSR1_15                        GPSR3_15        GPSR4_15        GPSR5_15        GPSR6_15 \
 375 GPSR0_14        GPSR1_14        GPSR2_14        GPSR3_14        GPSR4_14        GPSR5_14        GPSR6_14 \
 376 GPSR0_13        GPSR1_13        GPSR2_13        GPSR3_13        GPSR4_13        GPSR5_13        GPSR6_13 \
 377 GPSR0_12        GPSR1_12        GPSR2_12        GPSR3_12        GPSR4_12        GPSR5_12        GPSR6_12 \
 378 GPSR0_11        GPSR1_11        GPSR2_11        GPSR3_11        GPSR4_11        GPSR5_11        GPSR6_11 \
 379 GPSR0_10        GPSR1_10        GPSR2_10        GPSR3_10        GPSR4_10        GPSR5_10        GPSR6_10 \
 380 GPSR0_9         GPSR1_9         GPSR2_9         GPSR3_9         GPSR4_9         GPSR5_9         GPSR6_9 \
 381 GPSR0_8         GPSR1_8         GPSR2_8         GPSR3_8         GPSR4_8         GPSR5_8         GPSR6_8 \
 382 GPSR0_7         GPSR1_7         GPSR2_7         GPSR3_7         GPSR4_7         GPSR5_7         GPSR6_7 \
 383 GPSR0_6         GPSR1_6         GPSR2_6         GPSR3_6         GPSR4_6         GPSR5_6         GPSR6_6 \
 384 GPSR0_5         GPSR1_5         GPSR2_5         GPSR3_5         GPSR4_5         GPSR5_5         GPSR6_5 \
 385 GPSR0_4         GPSR1_4         GPSR2_4         GPSR3_4         GPSR4_4         GPSR5_4         GPSR6_4 \
 386 GPSR0_3         GPSR1_3         GPSR2_3         GPSR3_3         GPSR4_3         GPSR5_3         GPSR6_3         GPSR7_3 \
 387 GPSR0_2         GPSR1_2         GPSR2_2         GPSR3_2         GPSR4_2         GPSR5_2         GPSR6_2         GPSR7_2 \
 388 GPSR0_1         GPSR1_1         GPSR2_1         GPSR3_1         GPSR4_1         GPSR5_1         GPSR6_1         GPSR7_1 \
 389 GPSR0_0         GPSR1_0         GPSR2_0         GPSR3_0         GPSR4_0         GPSR5_0         GPSR6_0         GPSR7_0
 390
 391 #define PINMUX_IPSR                             \
 392 \
 393 FM(IP0_3_0)     IP0_3_0         FM(IP1_3_0)     IP1_3_0         FM(IP2_3_0)     IP2_3_0         FM(IP3_3_0)     IP3_3_0 \
 394 FM(IP0_7_4)     IP0_7_4         FM(IP1_7_4)     IP1_7_4         FM(IP2_7_4)     IP2_7_4         FM(IP3_7_4)     IP3_7_4 \
 395 FM(IP0_11_8)    IP0_11_8        FM(IP1_11_8)    IP1_11_8        FM(IP2_11_8)    IP2_11_8        FM(IP3_11_8)    IP3_11_8 \
 396 FM(IP0_15_12)   IP0_15_12       FM(IP1_15_12)   IP1_15_12       FM(IP2_15_12)   IP2_15_12       FM(IP3_15_12)   IP3_15_12 \
 397 FM(IP0_19_16)   IP0_19_16       FM(IP1_19_16)   IP1_19_16       FM(IP2_19_16)   IP2_19_16       FM(IP3_19_16)   IP3_19_16 \
 398 FM(IP0_23_20)   IP0_23_20       FM(IP1_23_20)   IP1_23_20       FM(IP2_23_20)   IP2_23_20       FM(IP3_23_20)   IP3_23_20 \
 399 FM(IP0_27_24)   IP0_27_24       FM(IP1_27_24)   IP1_27_24       FM(IP2_27_24)   IP2_27_24       FM(IP3_27_24)   IP3_27_24 \
 400 FM(IP0_31_28)   IP0_31_28       FM(IP1_31_28)   IP1_31_28       FM(IP2_31_28)   IP2_31_28       FM(IP3_31_28)   IP3_31_28 \
 401 \
 402 FM(IP4_3_0)     IP4_3_0         FM(IP5_3_0)     IP5_3_0         FM(IP6_3_0)     IP6_3_0         FM(IP7_3_0)     IP7_3_0 \
 403 FM(IP4_7_4)     IP4_7_4         FM(IP5_7_4)     IP5_7_4         FM(IP6_7_4)     IP6_7_4         FM(IP7_7_4)     IP7_7_4 \
 404 FM(IP4_11_8)    IP4_11_8        FM(IP5_11_8)    IP5_11_8        FM(IP6_11_8)    IP6_11_8        FM(IP7_11_8)    IP7_11_8 \
 405 FM(IP4_15_12)   IP4_15_12       FM(IP5_15_12)   IP5_15_12       FM(IP6_15_12)   IP6_15_12       FM(IP7_15_12)   IP7_15_12 \
 406 FM(IP4_19_16)   IP4_19_16       FM(IP5_19_16)   IP5_19_16       FM(IP6_19_16)   IP6_19_16       FM(IP7_19_16)   IP7_19_16 \
 407 FM(IP4_23_20)   IP4_23_20       FM(IP5_23_20)   IP5_23_20       FM(IP6_23_20)   IP6_23_20       FM(IP7_23_20)   IP7_23_20 \
 408 FM(IP4_27_24)   IP4_27_24       FM(IP5_27_24)   IP5_27_24       FM(IP6_27_24)   IP6_27_24       FM(IP7_27_24)   IP7_27_24 \
 409 FM(IP4_31_28)   IP4_31_28       FM(IP5_31_28)   IP5_31_28       FM(IP6_31_28)   IP6_31_28       FM(IP7_31_28)   IP7_31_28 \
 410 \
 411 FM(IP8_3_0)     IP8_3_0         FM(IP9_3_0)     IP9_3_0         FM(IP10_3_0)    IP10_3_0        FM(IP11_3_0)    IP11_3_0 \
 412 FM(IP8_7_4)     IP8_7_4         FM(IP9_7_4)     IP9_7_4         FM(IP10_7_4)    IP10_7_4        FM(IP11_7_4)    IP11_7_4 \
 413 FM(IP8_11_8)    IP8_11_8        FM(IP9_11_8)    IP9_11_8        FM(IP10_11_8)   IP10_11_8       FM(IP11_11_8)   IP11_11_8 \
 414 FM(IP8_15_12)   IP8_15_12       FM(IP9_15_12)   IP9_15_12       FM(IP10_15_12)  IP10_15_12      FM(IP11_15_12)  IP11_15_12 \
 415 FM(IP8_19_16)   IP8_19_16       FM(IP9_19_16)   IP9_19_16       FM(IP10_19_16)  IP10_19_16      FM(IP11_19_16)  IP11_19_16 \
 416 FM(IP8_23_20)   IP8_23_20       FM(IP9_23_20)   IP9_23_20       FM(IP10_23_20)  IP10_23_20      FM(IP11_23_20)  IP11_23_20 \
 417 FM(IP8_27_24)   IP8_27_24       FM(IP9_27_24)   IP9_27_24       FM(IP10_27_24)  IP10_27_24      FM(IP11_27_24)  IP11_27_24 \
 418 FM(IP8_31_28)   IP8_31_28       FM(IP9_31_28)   IP9_31_28       FM(IP10_31_28)  IP10_31_28      FM(IP11_31_28)  IP11_31_28 \
 419 \
 420 FM(IP12_3_0)    IP12_3_0        FM(IP13_3_0)    IP13_3_0        FM(IP14_3_0)    IP14_3_0        FM(IP15_3_0)    IP15_3_0 \
 421 FM(IP12_7_4)    IP12_7_4        FM(IP13_7_4)    IP13_7_4        FM(IP14_7_4)    IP14_7_4        FM(IP15_7_4)    IP15_7_4 \
 422 FM(IP12_11_8)   IP12_11_8       FM(IP13_11_8)   IP13_11_8       FM(IP14_11_8)   IP14_11_8       FM(IP15_11_8)   IP15_11_8 \
 423 FM(IP12_15_12)  IP12_15_12      FM(IP13_15_12)  IP13_15_12      FM(IP14_15_12)  IP14_15_12      FM(IP15_15_12)  IP15_15_12 \
 424 FM(IP12_19_16)  IP12_19_16      FM(IP13_19_16)  IP13_19_16      FM(IP14_19_16)  IP14_19_16      FM(IP15_19_16)  IP15_19_16 \
 425 FM(IP12_23_20)  IP12_23_20      FM(IP13_23_20)  IP13_23_20      FM(IP14_23_20)  IP14_23_20      FM(IP15_23_20)  IP15_23_20 \
 426 FM(IP12_27_24)  IP12_27_24      FM(IP13_27_24)  IP13_27_24      FM(IP14_27_24)  IP14_27_24      FM(IP15_27_24)  IP15_27_24 \
 427 FM(IP12_31_28)  IP12_31_28      FM(IP13_31_28)  IP13_31_28      FM(IP14_31_28)  IP14_31_28      FM(IP15_31_28)  IP15_31_28 \
 428 \
 429 FM(IP16_3_0)    IP16_3_0        FM(IP17_3_0)    IP17_3_0 \
 430 FM(IP16_7_4)    IP16_7_4        FM(IP17_7_4)    IP17_7_4 \
 431 FM(IP16_11_8)   IP16_11_8 \
 432 FM(IP16_15_12)  IP16_15_12 \
 433 FM(IP16_19_16)  IP16_19_16 \
 434 FM(IP16_23_20)  IP16_23_20 \
 435 FM(IP16_27_24)  IP16_27_24 \
 436 FM(IP16_31_28)  IP16_31_28
 437
 438 /* MOD_SEL0 */                  /* 0 */                 /* 1 */                 /* 2 */                 /* 3 */                 /* 4 */                 /* 5 */                 /* 6 */                 /* 7 */
 439 #define MOD_SEL0_30_29          FM(SEL_MSIOF3_0)        FM(SEL_MSIOF3_1)        FM(SEL_MSIOF3_2)        FM(SEL_MSIOF3_3)
 440 #define MOD_SEL0_28_27          FM(SEL_MSIOF2_0)        FM(SEL_MSIOF2_1)        FM(SEL_MSIOF2_2)        FM(SEL_MSIOF2_3)
 441 #define MOD_SEL0_26_25_24       FM(SEL_MSIOF1_0)        FM(SEL_MSIOF1_1)        FM(SEL_MSIOF1_2)        FM(SEL_MSIOF1_3)        FM(SEL_MSIOF1_4)        FM(SEL_MSIOF1_5)        FM(SEL_MSIOF1_6)        F_(0, 0)
 442 #define MOD_SEL0_23             FM(SEL_LBSC_0)          FM(SEL_LBSC_1)
 443 #define MOD_SEL0_22             FM(SEL_IEBUS_0)         FM(SEL_IEBUS_1)
 444 #define MOD_SEL0_21_20          FM(SEL_I2C6_0)          FM(SEL_I2C6_1)          FM(SEL_I2C6_2)          F_(0, 0)
 445 #define MOD_SEL0_19             FM(SEL_I2C2_0)          FM(SEL_I2C2_1)
 446 #define MOD_SEL0_18             FM(SEL_I2C1_0)          FM(SEL_I2C1_1)
 447 #define MOD_SEL0_17             FM(SEL_HSCIF4_0)        FM(SEL_HSCIF4_1)
 448 #define MOD_SEL0_16_15          FM(SEL_HSCIF3_0)        FM(SEL_HSCIF3_1)        FM(SEL_HSCIF3_2)        FM(SEL_HSCIF3_3)
 449 #define MOD_SEL0_14             FM(SEL_HSCIF2_0)        FM(SEL_HSCIF2_1)
 450 #define MOD_SEL0_13             FM(SEL_HSCIF1_0)        FM(SEL_HSCIF1_1)
 451 #define MOD_SEL0_12             FM(SEL_FSO_0)           FM(SEL_FSO_1)
 452 #define MOD_SEL0_11             FM(SEL_FM_0)            FM(SEL_FM_1)
 453 #define MOD_SEL0_10             FM(SEL_ETHERAVB_0)      FM(SEL_ETHERAVB_1)
 454 #define MOD_SEL0_9              FM(SEL_DRIF3_0)         FM(SEL_DRIF3_1)
 455 #define MOD_SEL0_8              FM(SEL_DRIF2_0)         FM(SEL_DRIF2_1)
 456 #define MOD_SEL0_7_6            FM(SEL_DRIF1_0)         FM(SEL_DRIF1_1)         FM(SEL_DRIF1_2)         F_(0, 0)
 457 #define MOD_SEL0_5_4            FM(SEL_DRIF0_0)         FM(SEL_DRIF0_1)         FM(SEL_DRIF0_2)         F_(0, 0)
 458 #define MOD_SEL0_3              FM(SEL_CANFD0_0)        FM(SEL_CANFD0_1)
 459 #define MOD_SEL0_2_1            FM(SEL_ADG_0)           FM(SEL_ADG_1)           FM(SEL_ADG_2)           FM(SEL_ADG_3)
 460
 461 /* MOD_SEL1 */                  /* 0 */                 /* 1 */                 /* 2 */                 /* 3 */                 /* 4 */                 /* 5 */                 /* 6 */                 /* 7 */
 462 #define MOD_SEL1_31_30          FM(SEL_TSIF1_0)         FM(SEL_TSIF1_1)         FM(SEL_TSIF1_2)         FM(SEL_TSIF1_3)
 463 #define MOD_SEL1_29_28_27       FM(SEL_TSIF0_0)         FM(SEL_TSIF0_1)         FM(SEL_TSIF0_2)         FM(SEL_TSIF0_3)         FM(SEL_TSIF0_4)         F_(0, 0)                F_(0, 0)                F_(0, 0)
 464 #define MOD_SEL1_26             FM(SEL_TIMER_TMU_0)     FM(SEL_TIMER_TMU_1)
 465 #define MOD_SEL1_25_24          FM(SEL_SSP1_1_0)        FM(SEL_SSP1_1_1)        FM(SEL_SSP1_1_2)        FM(SEL_SSP1_1_3)
 466 #define MOD_SEL1_23_22_21       FM(SEL_SSP1_0_0)        FM(SEL_SSP1_0_1)        FM(SEL_SSP1_0_2)        FM(SEL_SSP1_0_3)        FM(SEL_SSP1_0_4)        F_(0, 0)                F_(0, 0)                F_(0, 0)
 467 #define MOD_SEL1_20             FM(SEL_SSI_0)           FM(SEL_SSI_1)
 468 #define MOD_SEL1_19             FM(SEL_SPEED_PULSE_0)   FM(SEL_SPEED_PULSE_1)
 469 #define MOD_SEL1_18_17          FM(SEL_SIMCARD_0)       FM(SEL_SIMCARD_1)       FM(SEL_SIMCARD_2)       FM(SEL_SIMCARD_3)
 470 #define MOD_SEL1_16             FM(SEL_SDHI2_0)         FM(SEL_SDHI2_1)
 471 #define MOD_SEL1_15_14          FM(SEL_SCIF4_0)         FM(SEL_SCIF4_1)         FM(SEL_SCIF4_2)         F_(0, 0)
 472 #define MOD_SEL1_13             FM(SEL_SCIF3_0)         FM(SEL_SCIF3_1)
 473 #define MOD_SEL1_12             FM(SEL_SCIF2_0)         FM(SEL_SCIF2_1)
 474 #define MOD_SEL1_11             FM(SEL_SCIF1_0)         FM(SEL_SCIF1_1)
 475 #define MOD_SEL1_10             FM(SEL_SATA_0)          FM(SEL_SATA_1)
 476 #define MOD_SEL1_9              FM(SEL_REMOCON_0)       FM(SEL_REMOCON_1)
 477 #define MOD_SEL1_6              FM(SEL_RCAN0_0)         FM(SEL_RCAN0_1)
 478 #define MOD_SEL1_5              FM(SEL_PWM6_0)          FM(SEL_PWM6_1)
 479 #define MOD_SEL1_4              FM(SEL_PWM5_0)          FM(SEL_PWM5_1)
 480 #define MOD_SEL1_3              FM(SEL_PWM4_0)          FM(SEL_PWM4_1)
 481 #define MOD_SEL1_2              FM(SEL_PWM3_0)          FM(SEL_PWM3_1)
 482 #define MOD_SEL1_1              FM(SEL_PWM2_0)          FM(SEL_PWM2_1)
 483 #define MOD_SEL1_0              FM(SEL_PWM1_0)          FM(SEL_PWM1_1)
 484
 485 /* MOD_SEL2 */                  /* 0 */                 /* 1 */                 /* 2 */                 /* 3 */
 486 #define MOD_SEL2_31             FM(I2C_SEL_5_0)         FM(I2C_SEL_5_1)
 487 #define MOD_SEL2_30             FM(I2C_SEL_3_0)         FM(I2C_SEL_3_1)
 488 #define MOD_SEL2_29             FM(I2C_SEL_0_0)         FM(I2C_SEL_0_1)
 489 #define MOD_SEL2_0              FM(SEL_VIN4_0)          FM(SEL_VIN4_1)
 490
 491 #define PINMUX_MOD_SELS\
 492 \
 493                         MOD_SEL1_31_30          MOD_SEL2_31 \
 494 MOD_SEL0_30_29                                  MOD_SEL2_30 \
 495                         MOD_SEL1_29_28_27       MOD_SEL2_29 \
 496 MOD_SEL0_28_27 \
 497 \
 498 MOD_SEL0_26_25_24       MOD_SEL1_26 \
 499                         MOD_SEL1_25_24 \
 500 \
 501 MOD_SEL0_23             MOD_SEL1_23_22_21 \
 502 MOD_SEL0_22 \
 503 MOD_SEL0_21_20 \
 504                         MOD_SEL1_20 \
 505 MOD_SEL0_19             MOD_SEL1_19 \
 506 MOD_SEL0_18             MOD_SEL1_18_17 \
 507 MOD_SEL0_17 \
 508 MOD_SEL0_16_15          MOD_SEL1_16 \
 509                         MOD_SEL1_15_14 \
 510 MOD_SEL0_14 \
 511 MOD_SEL0_13             MOD_SEL1_13 \
 512 MOD_SEL0_12             MOD_SEL1_12 \
 513 MOD_SEL0_11             MOD_SEL1_11 \
 514 MOD_SEL0_10             MOD_SEL1_10 \
 515 MOD_SEL0_9              MOD_SEL1_9 \
 516 MOD_SEL0_8 \
 517 MOD_SEL0_7_6 \
 518                         MOD_SEL1_6 \
 519 MOD_SEL0_5_4            MOD_SEL1_5 \
 520                         MOD_SEL1_4 \
 521 MOD_SEL0_3              MOD_SEL1_3 \
 522 MOD_SEL0_2_1            MOD_SEL1_2 \
 523                         MOD_SEL1_1 \
 524                         MOD_SEL1_0              MOD_SEL2_0
 525
 526 /*
 527  * These pins are not able to be muxed but have other properties
 528  * that can be set, such as drive-strength or pull-up/pull-down enable.
 529  */
 530 #define PINMUX_STATIC \
 531         FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
 532         FM(QSPI0_IO2) FM(QSPI0_IO3) \
 533         FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
 534         FM(QSPI1_IO2) FM(QSPI1_IO3) \
 535         FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
 536         FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
 537         FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
 538         FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
 539         FM(CLKOUT) FM(PRESETOUT) \
 540         FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \
 541         FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
 542
 543 enum {
 544         PINMUX_RESERVED = 0,
 545
 546         PINMUX_DATA_BEGIN,
 547         GP_ALL(DATA),
 548         PINMUX_DATA_END,
 549
 550 #define F_(x, y)
 551 #define FM(x)   FN_##x,
 552         PINMUX_FUNCTION_BEGIN,
 553         GP_ALL(FN),
 554         PINMUX_GPSR
 555         PINMUX_IPSR
 556         PINMUX_MOD_SELS
 557         PINMUX_FUNCTION_END,
 558 #undef F_
 559 #undef FM
 560
 561 #define F_(x, y)
 562 #define FM(x)   x##_MARK,
 563         PINMUX_MARK_BEGIN,
 564         PINMUX_GPSR
 565         PINMUX_IPSR
 566         PINMUX_MOD_SELS
 567         PINMUX_STATIC
 568         PINMUX_MARK_END,
 569 #undef F_
 570 #undef FM
 571 };
 572
 573 static const u16 pinmux_data[] = {
 574         PINMUX_DATA_GP_ALL(),
 575
 576         PINMUX_SINGLE(AVS1),
 577         PINMUX_SINGLE(AVS2),
 578         PINMUX_SINGLE(HDMI0_CEC),
 579         PINMUX_SINGLE(HDMI1_CEC),
 580         PINMUX_SINGLE(I2C_SEL_0_1),
 581         PINMUX_SINGLE(I2C_SEL_3_1),
 582         PINMUX_SINGLE(I2C_SEL_5_1),
 583         PINMUX_SINGLE(MSIOF0_RXD),
 584         PINMUX_SINGLE(MSIOF0_SCK),
 585         PINMUX_SINGLE(MSIOF0_TXD),
 586         PINMUX_SINGLE(SD2_CMD),
 587         PINMUX_SINGLE(SD3_CLK),
 588         PINMUX_SINGLE(SD3_CMD),
 589         PINMUX_SINGLE(SD3_DAT0),
 590         PINMUX_SINGLE(SD3_DAT1),
 591         PINMUX_SINGLE(SD3_DAT2),
 592         PINMUX_SINGLE(SD3_DAT3),
 593         PINMUX_SINGLE(SD3_DS),
 594         PINMUX_SINGLE(SSI_SCK5),
 595         PINMUX_SINGLE(SSI_SDATA5),
 596         PINMUX_SINGLE(SSI_WS5),
 597
 598         /* IPSR0 */
 599         PINMUX_IPSR_GPSR(IP0_3_0,       AVB_MDC),
 600         PINMUX_IPSR_MSEL(IP0_3_0,       MSIOF2_SS2_C,           SEL_MSIOF2_2),
 601
 602         PINMUX_IPSR_GPSR(IP0_7_4,       AVB_MAGIC),
 603         PINMUX_IPSR_MSEL(IP0_7_4,       MSIOF2_SS1_C,           SEL_MSIOF2_2),
 604         PINMUX_IPSR_MSEL(IP0_7_4,       SCK4_A,                 SEL_SCIF4_0),
 605
 606         PINMUX_IPSR_GPSR(IP0_11_8,      AVB_PHY_INT),
 607         PINMUX_IPSR_MSEL(IP0_11_8,      MSIOF2_SYNC_C,          SEL_MSIOF2_2),
 608         PINMUX_IPSR_MSEL(IP0_11_8,      RX4_A,                  SEL_SCIF4_0),
 609
 610         PINMUX_IPSR_GPSR(IP0_15_12,     AVB_LINK),
 611         PINMUX_IPSR_MSEL(IP0_15_12,     MSIOF2_SCK_C,           SEL_MSIOF2_2),
 612         PINMUX_IPSR_MSEL(IP0_15_12,     TX4_A,                  SEL_SCIF4_0),
 613
 614         PINMUX_IPSR_MSEL(IP0_19_16,     AVB_AVTP_MATCH_A,       SEL_ETHERAVB_0),
 615         PINMUX_IPSR_MSEL(IP0_19_16,     MSIOF2_RXD_C,           SEL_MSIOF2_2),
 616         PINMUX_IPSR_MSEL(IP0_19_16,     CTS4_N_A,               SEL_SCIF4_0),
 617
 618         PINMUX_IPSR_MSEL(IP0_23_20,     AVB_AVTP_CAPTURE_A,     SEL_ETHERAVB_0),
 619         PINMUX_IPSR_MSEL(IP0_23_20,     MSIOF2_TXD_C,           SEL_MSIOF2_2),
 620         PINMUX_IPSR_MSEL(IP0_23_20,     RTS4_N_TANS_A,          SEL_SCIF4_0),
 621
 622         PINMUX_IPSR_GPSR(IP0_27_24,     IRQ0),
 623         PINMUX_IPSR_GPSR(IP0_27_24,     QPOLB),
 624         PINMUX_IPSR_GPSR(IP0_27_24,     DU_CDE),
 625         PINMUX_IPSR_MSEL(IP0_27_24,     VI4_DATA0_B,            SEL_VIN4_1),
 626         PINMUX_IPSR_MSEL(IP0_27_24,     CAN0_TX_B,              SEL_RCAN0_1),
 627         PINMUX_IPSR_MSEL(IP0_27_24,     CANFD0_TX_B,            SEL_CANFD0_1),
 628
 629         PINMUX_IPSR_GPSR(IP0_31_28,     IRQ1),
 630         PINMUX_IPSR_GPSR(IP0_31_28,     QPOLA),
 631         PINMUX_IPSR_GPSR(IP0_31_28,     DU_DISP),
 632         PINMUX_IPSR_MSEL(IP0_31_28,     VI4_DATA1_B,            SEL_VIN4_1),
 633         PINMUX_IPSR_MSEL(IP0_31_28,     CAN0_RX_B,              SEL_RCAN0_1),
 634         PINMUX_IPSR_MSEL(IP0_31_28,     CANFD0_RX_B,            SEL_CANFD0_1),
 635
 636         /* IPSR1 */
 637         PINMUX_IPSR_GPSR(IP1_3_0,       IRQ2),
 638         PINMUX_IPSR_GPSR(IP1_3_0,       QCPV_QDE),
 639         PINMUX_IPSR_GPSR(IP1_3_0,       DU_EXODDF_DU_ODDF_DISP_CDE),
 640         PINMUX_IPSR_MSEL(IP1_3_0,       VI4_DATA2_B,            SEL_VIN4_1),
 641         PINMUX_IPSR_MSEL(IP1_3_0,       PWM3_B,                 SEL_PWM3_1),
 642
 643         PINMUX_IPSR_GPSR(IP1_7_4,       IRQ3),
 644         PINMUX_IPSR_GPSR(IP1_7_4,       QSTVB_QVE),
 645         PINMUX_IPSR_GPSR(IP1_7_4,       A25),
 646         PINMUX_IPSR_GPSR(IP1_7_4,       DU_DOTCLKOUT1),
 647         PINMUX_IPSR_MSEL(IP1_7_4,       VI4_DATA3_B,            SEL_VIN4_1),
 648         PINMUX_IPSR_MSEL(IP1_7_4,       PWM4_B,                 SEL_PWM4_1),
 649
 650         PINMUX_IPSR_GPSR(IP1_11_8,      IRQ4),
 651         PINMUX_IPSR_GPSR(IP1_11_8,      QSTH_QHS),
 652         PINMUX_IPSR_GPSR(IP1_11_8,      A24),
 653         PINMUX_IPSR_GPSR(IP1_11_8,      DU_EXHSYNC_DU_HSYNC),
 654         PINMUX_IPSR_MSEL(IP1_11_8,      VI4_DATA4_B,            SEL_VIN4_1),
 655         PINMUX_IPSR_MSEL(IP1_11_8,      PWM5_B,                 SEL_PWM5_1),
 656
 657         PINMUX_IPSR_GPSR(IP1_15_12,     IRQ5),
 658         PINMUX_IPSR_GPSR(IP1_15_12,     QSTB_QHE),
 659         PINMUX_IPSR_GPSR(IP1_15_12,     A23),
 660         PINMUX_IPSR_GPSR(IP1_15_12,     DU_EXVSYNC_DU_VSYNC),
 661         PINMUX_IPSR_MSEL(IP1_15_12,     VI4_DATA5_B,            SEL_VIN4_1),
 662         PINMUX_IPSR_MSEL(IP1_15_12,     PWM6_B,                 SEL_PWM6_1),
 663
 664         PINMUX_IPSR_GPSR(IP1_19_16,     PWM0),
 665         PINMUX_IPSR_GPSR(IP1_19_16,     AVB_AVTP_PPS),
 666         PINMUX_IPSR_GPSR(IP1_19_16,     A22),
 667         PINMUX_IPSR_MSEL(IP1_19_16,     VI4_DATA6_B,            SEL_VIN4_1),
 668         PINMUX_IPSR_MSEL(IP1_19_16,     IECLK_B,                SEL_IEBUS_1),
 669
 670         PINMUX_IPSR_MSEL(IP1_23_20,     PWM1_A,                 SEL_PWM1_0),
 671         PINMUX_IPSR_GPSR(IP1_23_20,     A21),
 672         PINMUX_IPSR_MSEL(IP1_23_20,     HRX3_D,                 SEL_HSCIF3_3),
 673         PINMUX_IPSR_MSEL(IP1_23_20,     VI4_DATA7_B,            SEL_VIN4_1),
 674         PINMUX_IPSR_MSEL(IP1_23_20,     IERX_B,                 SEL_IEBUS_1),
 675
 676         PINMUX_IPSR_MSEL(IP1_27_24,     PWM2_A,                 SEL_PWM2_0),
 677         PINMUX_IPSR_GPSR(IP1_27_24,     A20),
 678         PINMUX_IPSR_MSEL(IP1_27_24,     HTX3_D,                 SEL_HSCIF3_3),
 679         PINMUX_IPSR_MSEL(IP1_27_24,     IETX_B,                 SEL_IEBUS_1),
 680
 681         PINMUX_IPSR_GPSR(IP1_31_28,     A0),
 682         PINMUX_IPSR_GPSR(IP1_31_28,     LCDOUT16),
 683         PINMUX_IPSR_MSEL(IP1_31_28,     MSIOF3_SYNC_B,          SEL_MSIOF3_1),
 684         PINMUX_IPSR_GPSR(IP1_31_28,     VI4_DATA8),
 685         PINMUX_IPSR_GPSR(IP1_31_28,     DU_DB0),
 686         PINMUX_IPSR_MSEL(IP1_31_28,     PWM3_A,                 SEL_PWM3_0),
 687
 688         /* IPSR2 */
 689         PINMUX_IPSR_GPSR(IP2_3_0,       A1),
 690         PINMUX_IPSR_GPSR(IP2_3_0,       LCDOUT17),
 691         PINMUX_IPSR_MSEL(IP2_3_0,       MSIOF3_TXD_B,           SEL_MSIOF3_1),
 692         PINMUX_IPSR_GPSR(IP2_3_0,       VI4_DATA9),
 693         PINMUX_IPSR_GPSR(IP2_3_0,       DU_DB1),
 694         PINMUX_IPSR_MSEL(IP2_3_0,       PWM4_A,                 SEL_PWM4_0),
 695
 696         PINMUX_IPSR_GPSR(IP2_7_4,       A2),
 697         PINMUX_IPSR_GPSR(IP2_7_4,       LCDOUT18),
 698         PINMUX_IPSR_MSEL(IP2_7_4,       MSIOF3_SCK_B,           SEL_MSIOF3_1),
 699         PINMUX_IPSR_GPSR(IP2_7_4,       VI4_DATA10),
 700         PINMUX_IPSR_GPSR(IP2_7_4,       DU_DB2),
 701         PINMUX_IPSR_MSEL(IP2_7_4,       PWM5_A,                 SEL_PWM5_0),
 702
 703         PINMUX_IPSR_GPSR(IP2_11_8,      A3),
 704         PINMUX_IPSR_GPSR(IP2_11_8,      LCDOUT19),
 705         PINMUX_IPSR_MSEL(IP2_11_8,      MSIOF3_RXD_B,           SEL_MSIOF3_1),
 706         PINMUX_IPSR_GPSR(IP2_11_8,      VI4_DATA11),
 707         PINMUX_IPSR_GPSR(IP2_11_8,      DU_DB3),
 708         PINMUX_IPSR_MSEL(IP2_11_8,      PWM6_A,                 SEL_PWM6_0),
 709
 710         PINMUX_IPSR_GPSR(IP2_15_12,     A4),
 711         PINMUX_IPSR_GPSR(IP2_15_12,     LCDOUT20),
 712         PINMUX_IPSR_MSEL(IP2_15_12,     MSIOF3_SS1_B,           SEL_MSIOF3_1),
 713         PINMUX_IPSR_GPSR(IP2_15_12,     VI4_DATA12),
 714         PINMUX_IPSR_GPSR(IP2_15_12,     VI5_DATA12),
 715         PINMUX_IPSR_GPSR(IP2_15_12,     DU_DB4),
 716
 717         PINMUX_IPSR_GPSR(IP2_19_16,     A5),
 718         PINMUX_IPSR_GPSR(IP2_19_16,     LCDOUT21),
 719         PINMUX_IPSR_MSEL(IP2_19_16,     MSIOF3_SS2_B,           SEL_MSIOF3_1),
 720         PINMUX_IPSR_MSEL(IP2_19_16,     SCK4_B,                 SEL_SCIF4_1),
 721         PINMUX_IPSR_GPSR(IP2_19_16,     VI4_DATA13),
 722         PINMUX_IPSR_GPSR(IP2_19_16,     VI5_DATA13),
 723         PINMUX_IPSR_GPSR(IP2_19_16,     DU_DB5),
 724
 725         PINMUX_IPSR_GPSR(IP2_23_20,     A6),
 726         PINMUX_IPSR_GPSR(IP2_23_20,     LCDOUT22),
 727         PINMUX_IPSR_MSEL(IP2_23_20,     MSIOF2_SS1_A,           SEL_MSIOF2_0),
 728         PINMUX_IPSR_MSEL(IP2_23_20,     RX4_B,                  SEL_SCIF4_1),
 729         PINMUX_IPSR_GPSR(IP2_23_20,     VI4_DATA14),
 730         PINMUX_IPSR_GPSR(IP2_23_20,     VI5_DATA14),
 731         PINMUX_IPSR_GPSR(IP2_23_20,     DU_DB6),
 732
 733         PINMUX_IPSR_GPSR(IP2_27_24,     A7),
 734         PINMUX_IPSR_GPSR(IP2_27_24,     LCDOUT23),
 735         PINMUX_IPSR_MSEL(IP2_27_24,     MSIOF2_SS2_A,           SEL_MSIOF2_0),
 736         PINMUX_IPSR_MSEL(IP2_27_24,     TX4_B,                  SEL_SCIF4_1),
 737         PINMUX_IPSR_GPSR(IP2_27_24,     VI4_DATA15),
 738         PINMUX_IPSR_GPSR(IP2_27_24,     VI5_DATA15),
 739         PINMUX_IPSR_GPSR(IP2_27_24,     DU_DB7),
 740
 741         PINMUX_IPSR_GPSR(IP2_31_28,     A8),
 742         PINMUX_IPSR_MSEL(IP2_31_28,     RX3_B,                  SEL_SCIF3_1),
 743         PINMUX_IPSR_MSEL(IP2_31_28,     MSIOF2_SYNC_A,          SEL_MSIOF2_0),
 744         PINMUX_IPSR_MSEL(IP2_31_28,     HRX4_B,                 SEL_HSCIF4_1),
 745         PINMUX_IPSR_MSEL(IP2_31_28,     SDA6_A,                 SEL_I2C6_0),
 746         PINMUX_IPSR_MSEL(IP2_31_28,     AVB_AVTP_MATCH_B,       SEL_ETHERAVB_1),
 747         PINMUX_IPSR_MSEL(IP2_31_28,     PWM1_B,                 SEL_PWM1_1),
 748
 749         /* IPSR3 */
 750         PINMUX_IPSR_GPSR(IP3_3_0,       A9),
 751         PINMUX_IPSR_MSEL(IP3_3_0,       MSIOF2_SCK_A,           SEL_MSIOF2_0),
 752         PINMUX_IPSR_MSEL(IP3_3_0,       CTS4_N_B,               SEL_SCIF4_1),
 753         PINMUX_IPSR_GPSR(IP3_3_0,       VI5_VSYNC_N),
 754
 755         PINMUX_IPSR_GPSR(IP3_7_4,       A10),
 756         PINMUX_IPSR_MSEL(IP3_7_4,       MSIOF2_RXD_A,           SEL_MSIOF2_0),
 757         PINMUX_IPSR_MSEL(IP3_7_4,       RTS4_N_TANS_B,          SEL_SCIF4_1),
 758         PINMUX_IPSR_GPSR(IP3_7_4,       VI5_HSYNC_N),
 759
 760         PINMUX_IPSR_GPSR(IP3_11_8,      A11),
 761         PINMUX_IPSR_MSEL(IP3_11_8,      TX3_B,                  SEL_SCIF3_1),
 762         PINMUX_IPSR_MSEL(IP3_11_8,      MSIOF2_TXD_A,           SEL_MSIOF2_0),
 763         PINMUX_IPSR_MSEL(IP3_11_8,      HTX4_B,                 SEL_HSCIF4_1),
 764         PINMUX_IPSR_GPSR(IP3_11_8,      HSCK4),
 765         PINMUX_IPSR_GPSR(IP3_11_8,      VI5_FIELD),
 766         PINMUX_IPSR_MSEL(IP3_11_8,      SCL6_A,                 SEL_I2C6_0),
 767         PINMUX_IPSR_MSEL(IP3_11_8,      AVB_AVTP_CAPTURE_B,     SEL_ETHERAVB_1),
 768         PINMUX_IPSR_MSEL(IP3_11_8,      PWM2_B,                 SEL_PWM2_1),
 769
 770         PINMUX_IPSR_GPSR(IP3_15_12,     A12),
 771         PINMUX_IPSR_GPSR(IP3_15_12,     LCDOUT12),
 772         PINMUX_IPSR_MSEL(IP3_15_12,     MSIOF3_SCK_C,           SEL_MSIOF3_2),
 773         PINMUX_IPSR_MSEL(IP3_15_12,     HRX4_A,                 SEL_HSCIF4_0),
 774         PINMUX_IPSR_GPSR(IP3_15_12,     VI5_DATA8),
 775         PINMUX_IPSR_GPSR(IP3_15_12,     DU_DG4),
 776
 777         PINMUX_IPSR_GPSR(IP3_19_16,     A13),
 778         PINMUX_IPSR_GPSR(IP3_19_16,     LCDOUT13),
 779         PINMUX_IPSR_MSEL(IP3_19_16,     MSIOF3_SYNC_C,          SEL_MSIOF3_2),
 780         PINMUX_IPSR_MSEL(IP3_19_16,     HTX4_A,                 SEL_HSCIF4_0),
 781         PINMUX_IPSR_GPSR(IP3_19_16,     VI5_DATA9),
 782         PINMUX_IPSR_GPSR(IP3_19_16,     DU_DG5),
 783
 784         PINMUX_IPSR_GPSR(IP3_23_20,     A14),
 785         PINMUX_IPSR_GPSR(IP3_23_20,     LCDOUT14),
 786         PINMUX_IPSR_MSEL(IP3_23_20,     MSIOF3_RXD_C,           SEL_MSIOF3_2),
 787         PINMUX_IPSR_GPSR(IP3_23_20,     HCTS4_N),
 788         PINMUX_IPSR_GPSR(IP3_23_20,     VI5_DATA10),
 789         PINMUX_IPSR_GPSR(IP3_23_20,     DU_DG6),
 790
 791         PINMUX_IPSR_GPSR(IP3_27_24,     A15),
 792         PINMUX_IPSR_GPSR(IP3_27_24,     LCDOUT15),
 793         PINMUX_IPSR_MSEL(IP3_27_24,     MSIOF3_TXD_C,           SEL_MSIOF3_2),
 794         PINMUX_IPSR_GPSR(IP3_27_24,     HRTS4_N),
 795         PINMUX_IPSR_GPSR(IP3_27_24,     VI5_DATA11),
 796         PINMUX_IPSR_GPSR(IP3_27_24,     DU_DG7),
 797
 798         PINMUX_IPSR_GPSR(IP3_31_28,     A16),
 799         PINMUX_IPSR_GPSR(IP3_31_28,     LCDOUT8),
 800         PINMUX_IPSR_GPSR(IP3_31_28,     VI4_FIELD),
 801         PINMUX_IPSR_GPSR(IP3_31_28,     DU_DG0),
 802
 803         /* IPSR4 */
 804         PINMUX_IPSR_GPSR(IP4_3_0,       A17),
 805         PINMUX_IPSR_GPSR(IP4_3_0,       LCDOUT9),
 806         PINMUX_IPSR_GPSR(IP4_3_0,       VI4_VSYNC_N),
 807         PINMUX_IPSR_GPSR(IP4_3_0,       DU_DG1),
 808
 809         PINMUX_IPSR_GPSR(IP4_7_4,       A18),
 810         PINMUX_IPSR_GPSR(IP4_7_4,       LCDOUT10),
 811         PINMUX_IPSR_GPSR(IP4_7_4,       VI4_HSYNC_N),
 812         PINMUX_IPSR_GPSR(IP4_7_4,       DU_DG2),
 813
 814         PINMUX_IPSR_GPSR(IP4_11_8,      A19),
 815         PINMUX_IPSR_GPSR(IP4_11_8,      LCDOUT11),
 816         PINMUX_IPSR_GPSR(IP4_11_8,      VI4_CLKENB),
 817         PINMUX_IPSR_GPSR(IP4_11_8,      DU_DG3),
 818
 819         PINMUX_IPSR_GPSR(IP4_15_12,     CS0_N),
 820         PINMUX_IPSR_GPSR(IP4_15_12,     VI5_CLKENB),
 821
 822         PINMUX_IPSR_GPSR(IP4_19_16,     CS1_N_A26),
 823         PINMUX_IPSR_GPSR(IP4_19_16,     VI5_CLK),
 824         PINMUX_IPSR_MSEL(IP4_19_16,     EX_WAIT0_B,             SEL_LBSC_1),
 825
 826         PINMUX_IPSR_GPSR(IP4_23_20,     BS_N),
 827         PINMUX_IPSR_GPSR(IP4_23_20,     QSTVA_QVS),
 828         PINMUX_IPSR_MSEL(IP4_23_20,     MSIOF3_SCK_D,           SEL_MSIOF3_3),
 829         PINMUX_IPSR_GPSR(IP4_23_20,     SCK3),
 830         PINMUX_IPSR_GPSR(IP4_23_20,     HSCK3),
 831         PINMUX_IPSR_GPSR(IP4_23_20,     CAN1_TX),
 832         PINMUX_IPSR_GPSR(IP4_23_20,     CANFD1_TX),
 833         PINMUX_IPSR_MSEL(IP4_23_20,     IETX_A,                 SEL_IEBUS_0),
 834
 835         PINMUX_IPSR_GPSR(IP4_27_24,     RD_N),
 836         PINMUX_IPSR_MSEL(IP4_27_24,     MSIOF3_SYNC_D,          SEL_MSIOF3_3),
 837         PINMUX_IPSR_MSEL(IP4_27_24,     RX3_A,                  SEL_SCIF3_0),
 838         PINMUX_IPSR_MSEL(IP4_27_24,     HRX3_A,                 SEL_HSCIF3_0),
 839         PINMUX_IPSR_MSEL(IP4_27_24,     CAN0_TX_A,              SEL_RCAN0_0),
 840         PINMUX_IPSR_MSEL(IP4_27_24,     CANFD0_TX_A,            SEL_CANFD0_0),
 841
 842         PINMUX_IPSR_GPSR(IP4_31_28,     RD_WR_N),
 843         PINMUX_IPSR_MSEL(IP4_31_28,     MSIOF3_RXD_D,           SEL_MSIOF3_3),
 844         PINMUX_IPSR_MSEL(IP4_31_28,     TX3_A,                  SEL_SCIF3_0),
 845         PINMUX_IPSR_MSEL(IP4_31_28,     HTX3_A,                 SEL_HSCIF3_0),
 846         PINMUX_IPSR_MSEL(IP4_31_28,     CAN0_RX_A,              SEL_RCAN0_0),
 847         PINMUX_IPSR_MSEL(IP4_31_28,     CANFD0_RX_A,            SEL_CANFD0_0),
 848
 849         /* IPSR5 */
 850         PINMUX_IPSR_GPSR(IP5_3_0,       WE0_N),
 851         PINMUX_IPSR_MSEL(IP5_3_0,       MSIOF3_TXD_D,           SEL_MSIOF3_3),
 852         PINMUX_IPSR_GPSR(IP5_3_0,       CTS3_N),
 853         PINMUX_IPSR_GPSR(IP5_3_0,       HCTS3_N),
 854         PINMUX_IPSR_MSEL(IP5_3_0,       SCL6_B,                 SEL_I2C6_1),
 855         PINMUX_IPSR_GPSR(IP5_3_0,       CAN_CLK),
 856         PINMUX_IPSR_MSEL(IP5_3_0,       IECLK_A,                SEL_IEBUS_0),
 857
 858         PINMUX_IPSR_GPSR(IP5_7_4,       WE1_N),
 859         PINMUX_IPSR_MSEL(IP5_7_4,       MSIOF3_SS1_D,           SEL_MSIOF3_3),
 860         PINMUX_IPSR_GPSR(IP5_7_4,       RTS3_N_TANS),
 861         PINMUX_IPSR_GPSR(IP5_7_4,       HRTS3_N),
 862         PINMUX_IPSR_MSEL(IP5_7_4,       SDA6_B,                 SEL_I2C6_1),
 863         PINMUX_IPSR_GPSR(IP5_7_4,       CAN1_RX),
 864         PINMUX_IPSR_GPSR(IP5_7_4,       CANFD1_RX),
 865         PINMUX_IPSR_MSEL(IP5_7_4,       IERX_A,                 SEL_IEBUS_0),
 866
 867         PINMUX_IPSR_MSEL(IP5_11_8,      EX_WAIT0_A,             SEL_LBSC_0),
 868         PINMUX_IPSR_GPSR(IP5_11_8,      QCLK),
 869         PINMUX_IPSR_GPSR(IP5_11_8,      VI4_CLK),
 870         PINMUX_IPSR_GPSR(IP5_11_8,      DU_DOTCLKOUT0),
 871
 872         PINMUX_IPSR_GPSR(IP5_15_12,     D0),
 873         PINMUX_IPSR_MSEL(IP5_15_12,     MSIOF2_SS1_B,           SEL_MSIOF2_1),
 874         PINMUX_IPSR_MSEL(IP5_15_12,     MSIOF3_SCK_A,           SEL_MSIOF3_0),
 875         PINMUX_IPSR_GPSR(IP5_15_12,     VI4_DATA16),
 876         PINMUX_IPSR_GPSR(IP5_15_12,     VI5_DATA0),
 877
 878         PINMUX_IPSR_GPSR(IP5_19_16,     D1),
 879         PINMUX_IPSR_MSEL(IP5_19_16,     MSIOF2_SS2_B,           SEL_MSIOF2_1),
 880         PINMUX_IPSR_MSEL(IP5_19_16,     MSIOF3_SYNC_A,          SEL_MSIOF3_0),
 881         PINMUX_IPSR_GPSR(IP5_19_16,     VI4_DATA17),
 882         PINMUX_IPSR_GPSR(IP5_19_16,     VI5_DATA1),
 883
 884         PINMUX_IPSR_GPSR(IP5_23_20,     D2),
 885         PINMUX_IPSR_MSEL(IP5_23_20,     MSIOF3_RXD_A,           SEL_MSIOF3_0),
 886         PINMUX_IPSR_GPSR(IP5_23_20,     VI4_DATA18),
 887         PINMUX_IPSR_GPSR(IP5_23_20,     VI5_DATA2),
 888
 889         PINMUX_IPSR_GPSR(IP5_27_24,     D3),
 890         PINMUX_IPSR_MSEL(IP5_27_24,     MSIOF3_TXD_A,           SEL_MSIOF3_0),
 891         PINMUX_IPSR_GPSR(IP5_27_24,     VI4_DATA19),
 892         PINMUX_IPSR_GPSR(IP5_27_24,     VI5_DATA3),
 893
 894         PINMUX_IPSR_GPSR(IP5_31_28,     D4),
 895         PINMUX_IPSR_MSEL(IP5_31_28,     MSIOF2_SCK_B,           SEL_MSIOF2_1),
 896         PINMUX_IPSR_GPSR(IP5_31_28,     VI4_DATA20),
 897         PINMUX_IPSR_GPSR(IP5_31_28,     VI5_DATA4),
 898
 899         /* IPSR6 */
 900         PINMUX_IPSR_GPSR(IP6_3_0,       D5),
 901         PINMUX_IPSR_MSEL(IP6_3_0,       MSIOF2_SYNC_B,          SEL_MSIOF2_1),
 902         PINMUX_IPSR_GPSR(IP6_3_0,       VI4_DATA21),
 903         PINMUX_IPSR_GPSR(IP6_3_0,       VI5_DATA5),
 904
 905         PINMUX_IPSR_GPSR(IP6_7_4,       D6),
 906         PINMUX_IPSR_MSEL(IP6_7_4,       MSIOF2_RXD_B,           SEL_MSIOF2_1),
 907         PINMUX_IPSR_GPSR(IP6_7_4,       VI4_DATA22),
 908         PINMUX_IPSR_GPSR(IP6_7_4,       VI5_DATA6),
 909
 910         PINMUX_IPSR_GPSR(IP6_11_8,      D7),
 911         PINMUX_IPSR_MSEL(IP6_11_8,      MSIOF2_TXD_B,           SEL_MSIOF2_1),
 912         PINMUX_IPSR_GPSR(IP6_11_8,      VI4_DATA23),
 913         PINMUX_IPSR_GPSR(IP6_11_8,      VI5_DATA7),
 914
 915         PINMUX_IPSR_GPSR(IP6_15_12,     D8),
 916         PINMUX_IPSR_GPSR(IP6_15_12,     LCDOUT0),
 917         PINMUX_IPSR_MSEL(IP6_15_12,     MSIOF2_SCK_D,           SEL_MSIOF2_3),
 918         PINMUX_IPSR_MSEL(IP6_15_12,     SCK4_C,                 SEL_SCIF4_2),
 919         PINMUX_IPSR_MSEL(IP6_15_12,     VI4_DATA0_A,            SEL_VIN4_0),
 920         PINMUX_IPSR_GPSR(IP6_15_12,     DU_DR0),
 921
 922         PINMUX_IPSR_GPSR(IP6_19_16,     D9),
 923         PINMUX_IPSR_GPSR(IP6_19_16,     LCDOUT1),
 924         PINMUX_IPSR_MSEL(IP6_19_16,     MSIOF2_SYNC_D,          SEL_MSIOF2_3),
 925         PINMUX_IPSR_MSEL(IP6_19_16,     VI4_DATA1_A,            SEL_VIN4_0),
 926         PINMUX_IPSR_GPSR(IP6_19_16,     DU_DR1),
 927
 928         PINMUX_IPSR_GPSR(IP6_23_20,     D10),
 929         PINMUX_IPSR_GPSR(IP6_23_20,     LCDOUT2),
 930         PINMUX_IPSR_MSEL(IP6_23_20,     MSIOF2_RXD_D,           SEL_MSIOF2_3),
 931         PINMUX_IPSR_MSEL(IP6_23_20,     HRX3_B,                 SEL_HSCIF3_1),
 932         PINMUX_IPSR_MSEL(IP6_23_20,     VI4_DATA2_A,            SEL_VIN4_0),
 933         PINMUX_IPSR_MSEL(IP6_23_20,     CTS4_N_C,               SEL_SCIF4_2),
 934         PINMUX_IPSR_GPSR(IP6_23_20,     DU_DR2),
 935
 936         PINMUX_IPSR_GPSR(IP6_27_24,     D11),
 937         PINMUX_IPSR_GPSR(IP6_27_24,     LCDOUT3),
 938         PINMUX_IPSR_MSEL(IP6_27_24,     MSIOF2_TXD_D,           SEL_MSIOF2_3),
 939         PINMUX_IPSR_MSEL(IP6_27_24,     HTX3_B,                 SEL_HSCIF3_1),
 940         PINMUX_IPSR_MSEL(IP6_27_24,     VI4_DATA3_A,            SEL_VIN4_0),
 941         PINMUX_IPSR_MSEL(IP6_27_24,     RTS4_N_TANS_C,          SEL_SCIF4_2),
 942         PINMUX_IPSR_GPSR(IP6_27_24,     DU_DR3),
 943
 944         PINMUX_IPSR_GPSR(IP6_31_28,     D12),
 945         PINMUX_IPSR_GPSR(IP6_31_28,     LCDOUT4),
 946         PINMUX_IPSR_MSEL(IP6_31_28,     MSIOF2_SS1_D,           SEL_MSIOF2_3),
 947         PINMUX_IPSR_MSEL(IP6_31_28,     RX4_C,                  SEL_SCIF4_2),
 948         PINMUX_IPSR_MSEL(IP6_31_28,     VI4_DATA4_A,            SEL_VIN4_0),
 949         PINMUX_IPSR_GPSR(IP6_31_28,     DU_DR4),
 950
 951         /* IPSR7 */
 952         PINMUX_IPSR_GPSR(IP7_3_0,       D13),
 953         PINMUX_IPSR_GPSR(IP7_3_0,       LCDOUT5),
 954         PINMUX_IPSR_MSEL(IP7_3_0,       MSIOF2_SS2_D,           SEL_MSIOF2_3),
 955         PINMUX_IPSR_MSEL(IP7_3_0,       TX4_C,                  SEL_SCIF4_2),
 956         PINMUX_IPSR_MSEL(IP7_3_0,       VI4_DATA5_A,            SEL_VIN4_0),
 957         PINMUX_IPSR_GPSR(IP7_3_0,       DU_DR5),
 958
 959         PINMUX_IPSR_GPSR(IP7_7_4,       D14),
 960         PINMUX_IPSR_GPSR(IP7_7_4,       LCDOUT6),
 961         PINMUX_IPSR_MSEL(IP7_7_4,       MSIOF3_SS1_A,           SEL_MSIOF3_0),
 962         PINMUX_IPSR_MSEL(IP7_7_4,       HRX3_C,                 SEL_HSCIF3_2),
 963         PINMUX_IPSR_MSEL(IP7_7_4,       VI4_DATA6_A,            SEL_VIN4_0),
 964         PINMUX_IPSR_GPSR(IP7_7_4,       DU_DR6),
 965         PINMUX_IPSR_MSEL(IP7_7_4,       SCL6_C,                 SEL_I2C6_2),
 966
 967         PINMUX_IPSR_GPSR(IP7_11_8,      D15),
 968         PINMUX_IPSR_GPSR(IP7_11_8,      LCDOUT7),
 969         PINMUX_IPSR_MSEL(IP7_11_8,      MSIOF3_SS2_A,           SEL_MSIOF3_0),
 970         PINMUX_IPSR_MSEL(IP7_11_8,      HTX3_C,                 SEL_HSCIF3_2),
 971         PINMUX_IPSR_MSEL(IP7_11_8,      VI4_DATA7_A,            SEL_VIN4_0),
 972         PINMUX_IPSR_GPSR(IP7_11_8,      DU_DR7),
 973         PINMUX_IPSR_MSEL(IP7_11_8,      SDA6_C,                 SEL_I2C6_2),
 974
 975         PINMUX_IPSR_GPSR(IP7_15_12,     FSCLKST),
 976
 977         PINMUX_IPSR_GPSR(IP7_19_16,     SD0_CLK),
 978         PINMUX_IPSR_MSEL(IP7_19_16,     MSIOF1_SCK_E,           SEL_MSIOF1_4),
 979         PINMUX_IPSR_MSEL(IP7_19_16,     STP_OPWM_0_B,           SEL_SSP1_0_1),
 980
 981         PINMUX_IPSR_GPSR(IP7_23_20,     SD0_CMD),
 982         PINMUX_IPSR_MSEL(IP7_23_20,     MSIOF1_SYNC_E,          SEL_MSIOF1_4),
 983         PINMUX_IPSR_MSEL(IP7_23_20,     STP_IVCXO27_0_B,        SEL_SSP1_0_1),
 984
 985         PINMUX_IPSR_GPSR(IP7_27_24,     SD0_DAT0),
 986         PINMUX_IPSR_MSEL(IP7_27_24,     MSIOF1_RXD_E,           SEL_MSIOF1_4),
 987         PINMUX_IPSR_MSEL(IP7_27_24,     TS_SCK0_B,              SEL_TSIF0_1),
 988         PINMUX_IPSR_MSEL(IP7_27_24,     STP_ISCLK_0_B,          SEL_SSP1_0_1),
 989
 990         PINMUX_IPSR_GPSR(IP7_31_28,     SD0_DAT1),
 991         PINMUX_IPSR_MSEL(IP7_31_28,     MSIOF1_TXD_E,           SEL_MSIOF1_4),
 992         PINMUX_IPSR_MSEL(IP7_31_28,     TS_SPSYNC0_B,           SEL_TSIF0_1),
 993         PINMUX_IPSR_MSEL(IP7_31_28,     STP_ISSYNC_0_B,         SEL_SSP1_0_1),
 994
 995         /* IPSR8 */
 996         PINMUX_IPSR_GPSR(IP8_3_0,       SD0_DAT2),
 997         PINMUX_IPSR_MSEL(IP8_3_0,       MSIOF1_SS1_E,           SEL_MSIOF1_4),
 998         PINMUX_IPSR_MSEL(IP8_3_0,       TS_SDAT0_B,             SEL_TSIF0_1),
 999         PINMUX_IPSR_MSEL(IP8_3_0,       STP_ISD_0_B,            SEL_SSP1_0_1),
1000
1001         PINMUX_IPSR_GPSR(IP8_7_4,       SD0_DAT3),
1002         PINMUX_IPSR_MSEL(IP8_7_4,       MSIOF1_SS2_E,           SEL_MSIOF1_4),
1003         PINMUX_IPSR_MSEL(IP8_7_4,       TS_SDEN0_B,             SEL_TSIF0_1),
1004         PINMUX_IPSR_MSEL(IP8_7_4,       STP_ISEN_0_B,           SEL_SSP1_0_1),
1005
1006         PINMUX_IPSR_GPSR(IP8_11_8,      SD1_CLK),
1007         PINMUX_IPSR_MSEL(IP8_11_8,      MSIOF1_SCK_G,           SEL_MSIOF1_6),
1008         PINMUX_IPSR_MSEL(IP8_11_8,      SIM0_CLK_A,             SEL_SIMCARD_0),
1009
1010         PINMUX_IPSR_GPSR(IP8_15_12,     SD1_CMD),
1011         PINMUX_IPSR_MSEL(IP8_15_12,     MSIOF1_SYNC_G,          SEL_MSIOF1_6),
1012         PINMUX_IPSR_MSEL(IP8_15_12,     SIM0_D_A,               SEL_SIMCARD_0),
1013         PINMUX_IPSR_MSEL(IP8_15_12,     STP_IVCXO27_1_B,        SEL_SSP1_1_1),
1014
1015         PINMUX_IPSR_GPSR(IP8_19_16,     SD1_DAT0),
1016         PINMUX_IPSR_GPSR(IP8_19_16,     SD2_DAT4),
1017         PINMUX_IPSR_MSEL(IP8_19_16,     MSIOF1_RXD_G,           SEL_MSIOF1_6),
1018         PINMUX_IPSR_MSEL(IP8_19_16,     TS_SCK1_B,              SEL_TSIF1_1),
1019         PINMUX_IPSR_MSEL(IP8_19_16,     STP_ISCLK_1_B,          SEL_SSP1_1_1),
1020
1021         PINMUX_IPSR_GPSR(IP8_23_20,     SD1_DAT1),
1022         PINMUX_IPSR_GPSR(IP8_23_20,     SD2_DAT5),
1023         PINMUX_IPSR_MSEL(IP8_23_20,     MSIOF1_TXD_G,           SEL_MSIOF1_6),
1024         PINMUX_IPSR_MSEL(IP8_23_20,     TS_SPSYNC1_B,           SEL_TSIF1_1),
1025         PINMUX_IPSR_MSEL(IP8_23_20,     STP_ISSYNC_1_B,         SEL_SSP1_1_1),
1026
1027         PINMUX_IPSR_GPSR(IP8_27_24,     SD1_DAT2),
1028         PINMUX_IPSR_GPSR(IP8_27_24,     SD2_DAT6),
1029         PINMUX_IPSR_MSEL(IP8_27_24,     MSIOF1_SS1_G,           SEL_MSIOF1_6),
1030         PINMUX_IPSR_MSEL(IP8_27_24,     TS_SDAT1_B,             SEL_TSIF1_1),
1031         PINMUX_IPSR_MSEL(IP8_27_24,     STP_ISD_1_B,            SEL_SSP1_1_1),
1032
1033         PINMUX_IPSR_GPSR(IP8_31_28,     SD1_DAT3),
1034         PINMUX_IPSR_GPSR(IP8_31_28,     SD2_DAT7),
1035         PINMUX_IPSR_MSEL(IP8_31_28,     MSIOF1_SS2_G,           SEL_MSIOF1_6),
1036         PINMUX_IPSR_MSEL(IP8_31_28,     TS_SDEN1_B,             SEL_TSIF1_1),
1037         PINMUX_IPSR_MSEL(IP8_31_28,     STP_ISEN_1_B,           SEL_SSP1_1_1),
1038
1039         /* IPSR9 */
1040         PINMUX_IPSR_GPSR(IP9_3_0,       SD2_CLK),
1041
1042         PINMUX_IPSR_GPSR(IP9_7_4,       SD2_DAT0),
1043
1044         PINMUX_IPSR_GPSR(IP9_11_8,      SD2_DAT1),
1045
1046         PINMUX_IPSR_GPSR(IP9_15_12,     SD2_DAT2),
1047
1048         PINMUX_IPSR_GPSR(IP9_19_16,     SD2_DAT3),
1049
1050         PINMUX_IPSR_GPSR(IP9_23_20,     SD2_DS),
1051         PINMUX_IPSR_MSEL(IP9_23_20,     SATA_DEVSLP_B,          SEL_SATA_1),
1052
1053         PINMUX_IPSR_GPSR(IP9_27_24,     SD3_DAT4),
1054         PINMUX_IPSR_MSEL(IP9_27_24,     SD2_CD_A,               SEL_SDHI2_0),
1055
1056         PINMUX_IPSR_GPSR(IP9_31_28,     SD3_DAT5),
1057         PINMUX_IPSR_MSEL(IP9_31_28,     SD2_WP_A,               SEL_SDHI2_0),
1058
1059         /* IPSR10 */
1060         PINMUX_IPSR_GPSR(IP10_3_0,      SD3_DAT6),
1061         PINMUX_IPSR_GPSR(IP10_3_0,      SD3_CD),
1062
1063         PINMUX_IPSR_GPSR(IP10_7_4,      SD3_DAT7),
1064         PINMUX_IPSR_GPSR(IP10_7_4,      SD3_WP),
1065
1066         PINMUX_IPSR_GPSR(IP10_11_8,     SD0_CD),
1067         PINMUX_IPSR_MSEL(IP10_11_8,     SCL2_B,                 SEL_I2C2_1),
1068         PINMUX_IPSR_MSEL(IP10_11_8,     SIM0_RST_A,             SEL_SIMCARD_0),
1069
1070         PINMUX_IPSR_GPSR(IP10_15_12,    SD0_WP),
1071         PINMUX_IPSR_MSEL(IP10_15_12,    SDA2_B,                 SEL_I2C2_1),
1072
1073         PINMUX_IPSR_GPSR(IP10_19_16,    SD1_CD),
1074         PINMUX_IPSR_MSEL(IP10_19_16,    SIM0_CLK_B,             SEL_SIMCARD_1),
1075
1076         PINMUX_IPSR_GPSR(IP10_23_20,    SD1_WP),
1077         PINMUX_IPSR_MSEL(IP10_23_20,    SIM0_D_B,               SEL_SIMCARD_1),
1078
1079         PINMUX_IPSR_GPSR(IP10_27_24,    SCK0),
1080         PINMUX_IPSR_MSEL(IP10_27_24,    HSCK1_B,                SEL_HSCIF1_1),
1081         PINMUX_IPSR_MSEL(IP10_27_24,    MSIOF1_SS2_B,           SEL_MSIOF1_1),
1082         PINMUX_IPSR_MSEL(IP10_27_24,    AUDIO_CLKC_B,           SEL_ADG_1),
1083         PINMUX_IPSR_MSEL(IP10_27_24,    SDA2_A,                 SEL_I2C2_0),
1084         PINMUX_IPSR_MSEL(IP10_27_24,    SIM0_RST_B,             SEL_SIMCARD_1),
1085         PINMUX_IPSR_MSEL(IP10_27_24,    STP_OPWM_0_C,           SEL_SSP1_0_2),
1086         PINMUX_IPSR_MSEL(IP10_27_24,    RIF0_CLK_B,             SEL_DRIF0_1),
1087         PINMUX_IPSR_GPSR(IP10_27_24,    ADICHS2),
1088
1089         PINMUX_IPSR_GPSR(IP10_31_28,    RX0),
1090         PINMUX_IPSR_MSEL(IP10_31_28,    HRX1_B,                 SEL_HSCIF1_1),
1091         PINMUX_IPSR_MSEL(IP10_31_28,    TS_SCK0_C,              SEL_TSIF0_2),
1092         PINMUX_IPSR_MSEL(IP10_31_28,    STP_ISCLK_0_C,          SEL_SSP1_0_2),
1093         PINMUX_IPSR_MSEL(IP10_31_28,    RIF0_D0_B,              SEL_DRIF0_1),
1094
1095         /* IPSR11 */
1096         PINMUX_IPSR_GPSR(IP11_3_0,      TX0),
1097         PINMUX_IPSR_MSEL(IP11_3_0,      HTX1_B,                 SEL_HSCIF1_1),
1098         PINMUX_IPSR_MSEL(IP11_3_0,      TS_SPSYNC0_C,           SEL_TSIF0_2),
1099         PINMUX_IPSR_MSEL(IP11_3_0,      STP_ISSYNC_0_C,         SEL_SSP1_0_2),
1100         PINMUX_IPSR_MSEL(IP11_3_0,      RIF0_D1_B,              SEL_DRIF0_1),
1101
1102         PINMUX_IPSR_GPSR(IP11_7_4,      CTS0_N),
1103         PINMUX_IPSR_MSEL(IP11_7_4,      HCTS1_N_B,              SEL_HSCIF1_1),
1104         PINMUX_IPSR_MSEL(IP11_7_4,      MSIOF1_SYNC_B,          SEL_MSIOF1_1),
1105         PINMUX_IPSR_MSEL(IP11_7_4,      TS_SPSYNC1_C,           SEL_TSIF1_2),
1106         PINMUX_IPSR_MSEL(IP11_7_4,      STP_ISSYNC_1_C,         SEL_SSP1_1_2),
1107         PINMUX_IPSR_MSEL(IP11_7_4,      RIF1_SYNC_B,            SEL_DRIF1_1),
1108         PINMUX_IPSR_MSEL(IP11_7_4,      AUDIO_CLKOUT_C,         SEL_ADG_2),
1109         PINMUX_IPSR_GPSR(IP11_7_4,      ADICS_SAMP),
1110
1111         PINMUX_IPSR_GPSR(IP11_11_8,     RTS0_N_TANS),
1112         PINMUX_IPSR_MSEL(IP11_11_8,     HRTS1_N_B,              SEL_HSCIF1_1),
1113         PINMUX_IPSR_MSEL(IP11_11_8,     MSIOF1_SS1_B,           SEL_MSIOF1_1),
1114         PINMUX_IPSR_MSEL(IP11_11_8,     AUDIO_CLKA_B,           SEL_ADG_1),
1115         PINMUX_IPSR_MSEL(IP11_11_8,     SCL2_A,                 SEL_I2C2_0),
1116         PINMUX_IPSR_MSEL(IP11_11_8,     STP_IVCXO27_1_C,        SEL_SSP1_1_2),
1117         PINMUX_IPSR_MSEL(IP11_11_8,     RIF0_SYNC_B,            SEL_DRIF0_1),
1118         PINMUX_IPSR_GPSR(IP11_11_8,     ADICHS1),
1119
1120         PINMUX_IPSR_MSEL(IP11_15_12,    RX1_A,                  SEL_SCIF1_0),
1121         PINMUX_IPSR_MSEL(IP11_15_12,    HRX1_A,                 SEL_HSCIF1_0),
1122         PINMUX_IPSR_MSEL(IP11_15_12,    TS_SDAT0_C,             SEL_TSIF0_2),
1123         PINMUX_IPSR_MSEL(IP11_15_12,    STP_ISD_0_C,            SEL_SSP1_0_2),
1124         PINMUX_IPSR_MSEL(IP11_15_12,    RIF1_CLK_C,             SEL_DRIF1_2),
1125
1126         PINMUX_IPSR_MSEL(IP11_19_16,    TX1_A,                  SEL_SCIF1_0),
1127         PINMUX_IPSR_MSEL(IP11_19_16,    HTX1_A,                 SEL_HSCIF1_0),
1128         PINMUX_IPSR_MSEL(IP11_19_16,    TS_SDEN0_C,             SEL_TSIF0_2),
1129         PINMUX_IPSR_MSEL(IP11_19_16,    STP_ISEN_0_C,           SEL_SSP1_0_2),
1130         PINMUX_IPSR_MSEL(IP11_19_16,    RIF1_D0_C,              SEL_DRIF1_2),
1131
1132         PINMUX_IPSR_GPSR(IP11_23_20,    CTS1_N),
1133         PINMUX_IPSR_MSEL(IP11_23_20,    HCTS1_N_A,              SEL_HSCIF1_0),
1134         PINMUX_IPSR_MSEL(IP11_23_20,    MSIOF1_RXD_B,           SEL_MSIOF1_1),
1135         PINMUX_IPSR_MSEL(IP11_23_20,    TS_SDEN1_C,             SEL_TSIF1_2),
1136         PINMUX_IPSR_MSEL(IP11_23_20,    STP_ISEN_1_C,           SEL_SSP1_1_2),
1137         PINMUX_IPSR_MSEL(IP11_23_20,    RIF1_D0_B,              SEL_DRIF1_1),
1138         PINMUX_IPSR_GPSR(IP11_23_20,    ADIDATA),
1139
1140         PINMUX_IPSR_GPSR(IP11_27_24,    RTS1_N_TANS),
1141         PINMUX_IPSR_MSEL(IP11_27_24,    HRTS1_N_A,              SEL_HSCIF1_0),
1142         PINMUX_IPSR_MSEL(IP11_27_24,    MSIOF1_TXD_B,           SEL_MSIOF1_1),
1143         PINMUX_IPSR_MSEL(IP11_27_24,    TS_SDAT1_C,             SEL_TSIF1_2),
1144         PINMUX_IPSR_MSEL(IP11_27_24,    STP_ISD_1_C,            SEL_SSP1_1_2),
1145         PINMUX_IPSR_MSEL(IP11_27_24,    RIF1_D1_B,              SEL_DRIF1_1),
1146         PINMUX_IPSR_GPSR(IP11_27_24,    ADICHS0),
1147
1148         PINMUX_IPSR_GPSR(IP11_31_28,    SCK2),
1149         PINMUX_IPSR_MSEL(IP11_31_28,    SCIF_CLK_B,             SEL_SCIF1_1),
1150         PINMUX_IPSR_MSEL(IP11_31_28,    MSIOF1_SCK_B,           SEL_MSIOF1_1),
1151         PINMUX_IPSR_MSEL(IP11_31_28,    TS_SCK1_C,              SEL_TSIF1_2),
1152         PINMUX_IPSR_MSEL(IP11_31_28,    STP_ISCLK_1_C,          SEL_SSP1_1_2),
1153         PINMUX_IPSR_MSEL(IP11_31_28,    RIF1_CLK_B,             SEL_DRIF1_1),
1154         PINMUX_IPSR_GPSR(IP11_31_28,    ADICLK),
1155
1156         /* IPSR12 */
1157         PINMUX_IPSR_MSEL(IP12_3_0,      TX2_A,                  SEL_SCIF2_0),
1158         PINMUX_IPSR_MSEL(IP12_3_0,      SD2_CD_B,               SEL_SDHI2_1),
1159         PINMUX_IPSR_MSEL(IP12_3_0,      SCL1_A,                 SEL_I2C1_0),
1160         PINMUX_IPSR_MSEL(IP12_3_0,      FMCLK_A,                SEL_FM_0),
1161         PINMUX_IPSR_MSEL(IP12_3_0,      RIF1_D1_C,              SEL_DRIF1_2),
1162         PINMUX_IPSR_MSEL(IP12_3_0,      FSO_CFE_0_B,            SEL_FSO_1),
1163
1164         PINMUX_IPSR_MSEL(IP12_7_4,      RX2_A,                  SEL_SCIF2_0),
1165         PINMUX_IPSR_MSEL(IP12_7_4,      SD2_WP_B,               SEL_SDHI2_1),
1166         PINMUX_IPSR_MSEL(IP12_7_4,      SDA1_A,                 SEL_I2C1_0),
1167         PINMUX_IPSR_MSEL(IP12_7_4,      FMIN_A,                 SEL_FM_0),
1168         PINMUX_IPSR_MSEL(IP12_7_4,      RIF1_SYNC_C,            SEL_DRIF1_2),
1169         PINMUX_IPSR_MSEL(IP12_7_4,      FSO_CFE_1_B,            SEL_FSO_1),
1170
1171         PINMUX_IPSR_GPSR(IP12_11_8,     HSCK0),
1172         PINMUX_IPSR_MSEL(IP12_11_8,     MSIOF1_SCK_D,           SEL_MSIOF1_3),
1173         PINMUX_IPSR_MSEL(IP12_11_8,     AUDIO_CLKB_A,           SEL_ADG_0),
1174         PINMUX_IPSR_MSEL(IP12_11_8,     SSI_SDATA1_B,           SEL_SSI_1),
1175         PINMUX_IPSR_MSEL(IP12_11_8,     TS_SCK0_D,              SEL_TSIF0_3),
1176         PINMUX_IPSR_MSEL(IP12_11_8,     STP_ISCLK_0_D,          SEL_SSP1_0_3),
1177         PINMUX_IPSR_MSEL(IP12_11_8,     RIF0_CLK_C,             SEL_DRIF0_2),
1178
1179         PINMUX_IPSR_GPSR(IP12_15_12,    HRX0),
1180         PINMUX_IPSR_MSEL(IP12_15_12,    MSIOF1_RXD_D,           SEL_MSIOF1_3),
1181         PINMUX_IPSR_MSEL(IP12_15_12,    SSI_SDATA2_B,           SEL_SSI_1),
1182         PINMUX_IPSR_MSEL(IP12_15_12,    TS_SDEN0_D,             SEL_TSIF0_3),
1183         PINMUX_IPSR_MSEL(IP12_15_12,    STP_ISEN_0_D,           SEL_SSP1_0_3),
1184         PINMUX_IPSR_MSEL(IP12_15_12,    RIF0_D0_C,              SEL_DRIF0_2),
1185
1186         PINMUX_IPSR_GPSR(IP12_19_16,    HTX0),
1187         PINMUX_IPSR_MSEL(IP12_19_16,    MSIOF1_TXD_D,           SEL_MSIOF1_3),
1188         PINMUX_IPSR_MSEL(IP12_19_16,    SSI_SDATA9_B,           SEL_SSI_1),
1189         PINMUX_IPSR_MSEL(IP12_19_16,    TS_SDAT0_D,             SEL_TSIF0_3),
1190         PINMUX_IPSR_MSEL(IP12_19_16,    STP_ISD_0_D,            SEL_SSP1_0_3),
1191         PINMUX_IPSR_MSEL(IP12_19_16,    RIF0_D1_C,              SEL_DRIF0_2),
1192
1193         PINMUX_IPSR_GPSR(IP12_23_20,    HCTS0_N),
1194         PINMUX_IPSR_MSEL(IP12_23_20,    RX2_B,                  SEL_SCIF2_1),
1195         PINMUX_IPSR_MSEL(IP12_23_20,    MSIOF1_SYNC_D,          SEL_MSIOF1_3),
1196         PINMUX_IPSR_MSEL(IP12_23_20,    SSI_SCK9_A,             SEL_SSI_0),
1197         PINMUX_IPSR_MSEL(IP12_23_20,    TS_SPSYNC0_D,           SEL_TSIF0_3),
1198         PINMUX_IPSR_MSEL(IP12_23_20,    STP_ISSYNC_0_D,         SEL_SSP1_0_3),
1199         PINMUX_IPSR_MSEL(IP12_23_20,    RIF0_SYNC_C,            SEL_DRIF0_2),
1200         PINMUX_IPSR_MSEL(IP12_23_20,    AUDIO_CLKOUT1_A,        SEL_ADG_0),
1201
1202         PINMUX_IPSR_GPSR(IP12_27_24,    HRTS0_N),
1203         PINMUX_IPSR_MSEL(IP12_27_24,    TX2_B,                  SEL_SCIF2_1),
1204         PINMUX_IPSR_MSEL(IP12_27_24,    MSIOF1_SS1_D,           SEL_MSIOF1_3),
1205         PINMUX_IPSR_MSEL(IP12_27_24,    SSI_WS9_A,              SEL_SSI_0),
1206         PINMUX_IPSR_MSEL(IP12_27_24,    STP_IVCXO27_0_D,        SEL_SSP1_0_3),
1207         PINMUX_IPSR_MSEL(IP12_27_24,    BPFCLK_A,               SEL_FM_0),
1208         PINMUX_IPSR_MSEL(IP12_27_24,    AUDIO_CLKOUT2_A,        SEL_ADG_0),
1209
1210         PINMUX_IPSR_GPSR(IP12_31_28,    MSIOF0_SYNC),
1211         PINMUX_IPSR_MSEL(IP12_31_28,    AUDIO_CLKOUT_A,         SEL_ADG_0),
1212
1213         /* IPSR13 */
1214         PINMUX_IPSR_GPSR(IP13_3_0,      MSIOF0_SS1),
1215         PINMUX_IPSR_GPSR(IP13_3_0,      RX5),
1216         PINMUX_IPSR_MSEL(IP13_3_0,      AUDIO_CLKA_C,           SEL_ADG_2),
1217         PINMUX_IPSR_MSEL(IP13_3_0,      SSI_SCK2_A,             SEL_SSI_0),
1218         PINMUX_IPSR_MSEL(IP13_3_0,      STP_IVCXO27_0_C,        SEL_SSP1_0_2),
1219         PINMUX_IPSR_MSEL(IP13_3_0,      AUDIO_CLKOUT3_A,        SEL_ADG_0),
1220         PINMUX_IPSR_MSEL(IP13_3_0,      TCLK1_B,                SEL_TIMER_TMU_1),
1221
1222         PINMUX_IPSR_GPSR(IP13_7_4,      MSIOF0_SS2),
1223         PINMUX_IPSR_GPSR(IP13_7_4,      TX5),
1224         PINMUX_IPSR_MSEL(IP13_7_4,      MSIOF1_SS2_D,           SEL_MSIOF1_3),
1225         PINMUX_IPSR_MSEL(IP13_7_4,      AUDIO_CLKC_A,           SEL_ADG_0),
1226         PINMUX_IPSR_MSEL(IP13_7_4,      SSI_WS2_A,              SEL_SSI_0),
1227         PINMUX_IPSR_MSEL(IP13_7_4,      STP_OPWM_0_D,           SEL_SSP1_0_3),
1228         PINMUX_IPSR_MSEL(IP13_7_4,      AUDIO_CLKOUT_D,         SEL_ADG_3),
1229         PINMUX_IPSR_MSEL(IP13_7_4,      SPEEDIN_B,              SEL_SPEED_PULSE_1),
1230
1231         PINMUX_IPSR_GPSR(IP13_11_8,     MLB_CLK),
1232         PINMUX_IPSR_MSEL(IP13_11_8,     MSIOF1_SCK_F,           SEL_MSIOF1_5),
1233         PINMUX_IPSR_MSEL(IP13_11_8,     SCL1_B,                 SEL_I2C1_1),
1234
1235         PINMUX_IPSR_GPSR(IP13_15_12,    MLB_SIG),
1236         PINMUX_IPSR_MSEL(IP13_15_12,    RX1_B,                  SEL_SCIF1_1),
1237         PINMUX_IPSR_MSEL(IP13_15_12,    MSIOF1_SYNC_F,          SEL_MSIOF1_5),
1238         PINMUX_IPSR_MSEL(IP13_15_12,    SDA1_B,                 SEL_I2C1_1),
1239
1240         PINMUX_IPSR_GPSR(IP13_19_16,    MLB_DAT),
1241         PINMUX_IPSR_MSEL(IP13_19_16,    TX1_B,                  SEL_SCIF1_1),
1242         PINMUX_IPSR_MSEL(IP13_19_16,    MSIOF1_RXD_F,           SEL_MSIOF1_5),
1243
1244         PINMUX_IPSR_GPSR(IP13_23_20,    SSI_SCK01239),
1245         PINMUX_IPSR_MSEL(IP13_23_20,    MSIOF1_TXD_F,           SEL_MSIOF1_5),
1246
1247         PINMUX_IPSR_GPSR(IP13_27_24,    SSI_WS01239),
1248         PINMUX_IPSR_MSEL(IP13_27_24,    MSIOF1_SS1_F,           SEL_MSIOF1_5),
1249
1250         PINMUX_IPSR_GPSR(IP13_31_28,    SSI_SDATA0),
1251         PINMUX_IPSR_MSEL(IP13_31_28,    MSIOF1_SS2_F,           SEL_MSIOF1_5),
1252
1253         /* IPSR14 */
1254         PINMUX_IPSR_MSEL(IP14_3_0,      SSI_SDATA1_A,           SEL_SSI_0),
1255
1256         PINMUX_IPSR_MSEL(IP14_7_4,      SSI_SDATA2_A,           SEL_SSI_0),
1257         PINMUX_IPSR_MSEL(IP14_7_4,      SSI_SCK1_B,             SEL_SSI_1),
1258
1259         PINMUX_IPSR_GPSR(IP14_11_8,     SSI_SCK34),
1260         PINMUX_IPSR_MSEL(IP14_11_8,     MSIOF1_SS1_A,           SEL_MSIOF1_0),
1261         PINMUX_IPSR_MSEL(IP14_11_8,     STP_OPWM_0_A,           SEL_SSP1_0_0),
1262
1263         PINMUX_IPSR_GPSR(IP14_15_12,    SSI_WS34),
1264         PINMUX_IPSR_MSEL(IP14_15_12,    HCTS2_N_A,              SEL_HSCIF2_0),
1265         PINMUX_IPSR_MSEL(IP14_15_12,    MSIOF1_SS2_A,           SEL_MSIOF1_0),
1266         PINMUX_IPSR_MSEL(IP14_15_12,    STP_IVCXO27_0_A,        SEL_SSP1_0_0),
1267
1268         PINMUX_IPSR_GPSR(IP14_19_16,    SSI_SDATA3),
1269         PINMUX_IPSR_MSEL(IP14_19_16,    HRTS2_N_A,              SEL_HSCIF2_0),
1270         PINMUX_IPSR_MSEL(IP14_19_16,    MSIOF1_TXD_A,           SEL_MSIOF1_0),
1271         PINMUX_IPSR_MSEL(IP14_19_16,    TS_SCK0_A,              SEL_TSIF0_0),
1272         PINMUX_IPSR_MSEL(IP14_19_16,    STP_ISCLK_0_A,          SEL_SSP1_0_0),
1273         PINMUX_IPSR_MSEL(IP14_19_16,    RIF0_D1_A,              SEL_DRIF0_0),
1274         PINMUX_IPSR_MSEL(IP14_19_16,    RIF2_D0_A,              SEL_DRIF2_0),
1275
1276         PINMUX_IPSR_GPSR(IP14_23_20,    SSI_SCK4),
1277         PINMUX_IPSR_MSEL(IP14_23_20,    HRX2_A,                 SEL_HSCIF2_0),
1278         PINMUX_IPSR_MSEL(IP14_23_20,    MSIOF1_SCK_A,           SEL_MSIOF1_0),
1279         PINMUX_IPSR_MSEL(IP14_23_20,    TS_SDAT0_A,             SEL_TSIF0_0),
1280         PINMUX_IPSR_MSEL(IP14_23_20,    STP_ISD_0_A,            SEL_SSP1_0_0),
1281         PINMUX_IPSR_MSEL(IP14_23_20,    RIF0_CLK_A,             SEL_DRIF0_0),
1282         PINMUX_IPSR_MSEL(IP14_23_20,    RIF2_CLK_A,             SEL_DRIF2_0),
1283
1284         PINMUX_IPSR_GPSR(IP14_27_24,    SSI_WS4),
1285         PINMUX_IPSR_MSEL(IP14_27_24,    HTX2_A,                 SEL_HSCIF2_0),
1286         PINMUX_IPSR_MSEL(IP14_27_24,    MSIOF1_SYNC_A,          SEL_MSIOF1_0),
1287         PINMUX_IPSR_MSEL(IP14_27_24,    TS_SDEN0_A,             SEL_TSIF0_0),
1288         PINMUX_IPSR_MSEL(IP14_27_24,    STP_ISEN_0_A,           SEL_SSP1_0_0),
1289         PINMUX_IPSR_MSEL(IP14_27_24,    RIF0_SYNC_A,            SEL_DRIF0_0),
1290         PINMUX_IPSR_MSEL(IP14_27_24,    RIF2_SYNC_A,            SEL_DRIF2_0),
1291
1292         PINMUX_IPSR_GPSR(IP14_31_28,    SSI_SDATA4),
1293         PINMUX_IPSR_MSEL(IP14_31_28,    HSCK2_A,                SEL_HSCIF2_0),
1294         PINMUX_IPSR_MSEL(IP14_31_28,    MSIOF1_RXD_A,           SEL_MSIOF1_0),
1295         PINMUX_IPSR_MSEL(IP14_31_28,    TS_SPSYNC0_A,           SEL_TSIF0_0),
1296         PINMUX_IPSR_MSEL(IP14_31_28,    STP_ISSYNC_0_A,         SEL_SSP1_0_0),
1297         PINMUX_IPSR_MSEL(IP14_31_28,    RIF0_D0_A,              SEL_DRIF0_0),
1298         PINMUX_IPSR_MSEL(IP14_31_28,    RIF2_D1_A,              SEL_DRIF2_0),
1299
1300         /* IPSR15 */
1301         PINMUX_IPSR_GPSR(IP15_3_0,      SSI_SCK6),
1302         PINMUX_IPSR_GPSR(IP15_3_0,      USB2_PWEN),
1303         PINMUX_IPSR_MSEL(IP15_3_0,      SIM0_RST_D,             SEL_SIMCARD_3),
1304
1305         PINMUX_IPSR_GPSR(IP15_7_4,      SSI_WS6),
1306         PINMUX_IPSR_GPSR(IP15_7_4,      USB2_OVC),
1307         PINMUX_IPSR_MSEL(IP15_7_4,      SIM0_D_D,               SEL_SIMCARD_3),
1308
1309         PINMUX_IPSR_GPSR(IP15_11_8,     SSI_SDATA6),
1310         PINMUX_IPSR_MSEL(IP15_11_8,     SIM0_CLK_D,             SEL_SIMCARD_3),
1311         PINMUX_IPSR_MSEL(IP15_11_8,     SATA_DEVSLP_A,          SEL_SATA_0),
1312
1313         PINMUX_IPSR_GPSR(IP15_15_12,    SSI_SCK78),
1314         PINMUX_IPSR_MSEL(IP15_15_12,    HRX2_B,                 SEL_HSCIF2_1),
1315         PINMUX_IPSR_MSEL(IP15_15_12,    MSIOF1_SCK_C,           SEL_MSIOF1_2),
1316         PINMUX_IPSR_MSEL(IP15_15_12,    TS_SCK1_A,              SEL_TSIF1_0),
1317         PINMUX_IPSR_MSEL(IP15_15_12,    STP_ISCLK_1_A,          SEL_SSP1_1_0),
1318         PINMUX_IPSR_MSEL(IP15_15_12,    RIF1_CLK_A,             SEL_DRIF1_0),
1319         PINMUX_IPSR_MSEL(IP15_15_12,    RIF3_CLK_A,             SEL_DRIF3_0),
1320
1321         PINMUX_IPSR_GPSR(IP15_19_16,    SSI_WS78),
1322         PINMUX_IPSR_MSEL(IP15_19_16,    HTX2_B,                 SEL_HSCIF2_1),
1323         PINMUX_IPSR_MSEL(IP15_19_16,    MSIOF1_SYNC_C,          SEL_MSIOF1_2),
1324         PINMUX_IPSR_MSEL(IP15_19_16,    TS_SDAT1_A,             SEL_TSIF1_0),
1325         PINMUX_IPSR_MSEL(IP15_19_16,    STP_ISD_1_A,            SEL_SSP1_1_0),
1326         PINMUX_IPSR_MSEL(IP15_19_16,    RIF1_SYNC_A,            SEL_DRIF1_0),
1327         PINMUX_IPSR_MSEL(IP15_19_16,    RIF3_SYNC_A,            SEL_DRIF3_0),
1328
1329         PINMUX_IPSR_GPSR(IP15_23_20,    SSI_SDATA7),
1330         PINMUX_IPSR_MSEL(IP15_23_20,    HCTS2_N_B,              SEL_HSCIF2_1),
1331         PINMUX_IPSR_MSEL(IP15_23_20,    MSIOF1_RXD_C,           SEL_MSIOF1_2),
1332         PINMUX_IPSR_MSEL(IP15_23_20,    TS_SDEN1_A,             SEL_TSIF1_0),
1333         PINMUX_IPSR_MSEL(IP15_23_20,    STP_ISEN_1_A,           SEL_SSP1_1_0),
1334         PINMUX_IPSR_MSEL(IP15_23_20,    RIF1_D0_A,              SEL_DRIF1_0),
1335         PINMUX_IPSR_MSEL(IP15_23_20,    RIF3_D0_A,              SEL_DRIF3_0),
1336         PINMUX_IPSR_MSEL(IP15_23_20,    TCLK2_A,                SEL_TIMER_TMU_0),
1337
1338         PINMUX_IPSR_GPSR(IP15_27_24,    SSI_SDATA8),
1339         PINMUX_IPSR_MSEL(IP15_27_24,    HRTS2_N_B,              SEL_HSCIF2_1),
1340         PINMUX_IPSR_MSEL(IP15_27_24,    MSIOF1_TXD_C,           SEL_MSIOF1_2),
1341         PINMUX_IPSR_MSEL(IP15_27_24,    TS_SPSYNC1_A,           SEL_TSIF1_0),
1342         PINMUX_IPSR_MSEL(IP15_27_24,    STP_ISSYNC_1_A,         SEL_SSP1_1_0),
1343         PINMUX_IPSR_MSEL(IP15_27_24,    RIF1_D1_A,              SEL_DRIF1_0),
1344         PINMUX_IPSR_MSEL(IP15_27_24,    RIF3_D1_A,              SEL_DRIF3_0),
1345
1346         PINMUX_IPSR_MSEL(IP15_31_28,    SSI_SDATA9_A,           SEL_SSI_0),
1347         PINMUX_IPSR_MSEL(IP15_31_28,    HSCK2_B,                SEL_HSCIF2_1),
1348         PINMUX_IPSR_MSEL(IP15_31_28,    MSIOF1_SS1_C,           SEL_MSIOF1_2),
1349         PINMUX_IPSR_MSEL(IP15_31_28,    HSCK1_A,                SEL_HSCIF1_0),
1350         PINMUX_IPSR_MSEL(IP15_31_28,    SSI_WS1_B,              SEL_SSI_1),
1351         PINMUX_IPSR_GPSR(IP15_31_28,    SCK1),
1352         PINMUX_IPSR_MSEL(IP15_31_28,    STP_IVCXO27_1_A,        SEL_SSP1_1_0),
1353         PINMUX_IPSR_GPSR(IP15_31_28,    SCK5),
1354
1355         /* IPSR16 */
1356         PINMUX_IPSR_MSEL(IP16_3_0,      AUDIO_CLKA_A,           SEL_ADG_0),
1357         PINMUX_IPSR_GPSR(IP16_3_0,      CC5_OSCOUT),
1358
1359         PINMUX_IPSR_MSEL(IP16_7_4,      AUDIO_CLKB_B,           SEL_ADG_1),
1360         PINMUX_IPSR_MSEL(IP16_7_4,      SCIF_CLK_A,             SEL_SCIF1_0),
1361         PINMUX_IPSR_MSEL(IP16_7_4,      STP_IVCXO27_1_D,        SEL_SSP1_1_3),
1362         PINMUX_IPSR_MSEL(IP16_7_4,      REMOCON_A,              SEL_REMOCON_0),
1363         PINMUX_IPSR_MSEL(IP16_7_4,      TCLK1_A,                SEL_TIMER_TMU_0),
1364
1365         PINMUX_IPSR_GPSR(IP16_11_8,     USB0_PWEN),
1366         PINMUX_IPSR_MSEL(IP16_11_8,     SIM0_RST_C,             SEL_SIMCARD_2),
1367         PINMUX_IPSR_MSEL(IP16_11_8,     TS_SCK1_D,              SEL_TSIF1_3),
1368         PINMUX_IPSR_MSEL(IP16_11_8,     STP_ISCLK_1_D,          SEL_SSP1_1_3),
1369         PINMUX_IPSR_MSEL(IP16_11_8,     BPFCLK_B,               SEL_FM_1),
1370         PINMUX_IPSR_MSEL(IP16_11_8,     RIF3_CLK_B,             SEL_DRIF3_1),
1371
1372         PINMUX_IPSR_GPSR(IP16_15_12,    USB0_OVC),
1373         PINMUX_IPSR_MSEL(IP16_11_8,     SIM0_D_C,               SEL_SIMCARD_2),
1374         PINMUX_IPSR_MSEL(IP16_11_8,     TS_SDAT1_D,             SEL_TSIF1_3),
1375         PINMUX_IPSR_MSEL(IP16_11_8,     STP_ISD_1_D,            SEL_SSP1_1_3),
1376         PINMUX_IPSR_MSEL(IP16_11_8,     RIF3_SYNC_B,            SEL_DRIF3_1),
1377
1378         PINMUX_IPSR_GPSR(IP16_19_16,    USB1_PWEN),
1379         PINMUX_IPSR_MSEL(IP16_19_16,    SIM0_CLK_C,             SEL_SIMCARD_2),
1380         PINMUX_IPSR_MSEL(IP16_19_16,    SSI_SCK1_A,             SEL_SSI_0),
1381         PINMUX_IPSR_MSEL(IP16_19_16,    TS_SCK0_E,              SEL_TSIF0_4),
1382         PINMUX_IPSR_MSEL(IP16_19_16,    STP_ISCLK_0_E,          SEL_SSP1_0_4),
1383         PINMUX_IPSR_MSEL(IP16_19_16,    FMCLK_B,                SEL_FM_1),
1384         PINMUX_IPSR_MSEL(IP16_19_16,    RIF2_CLK_B,             SEL_DRIF2_1),
1385         PINMUX_IPSR_MSEL(IP16_19_16,    SPEEDIN_A,              SEL_SPEED_PULSE_0),
1386
1387         PINMUX_IPSR_GPSR(IP16_23_20,    USB1_OVC),
1388         PINMUX_IPSR_MSEL(IP16_23_20,    MSIOF1_SS2_C,           SEL_MSIOF1_2),
1389         PINMUX_IPSR_MSEL(IP16_23_20,    SSI_WS1_A,              SEL_SSI_0),
1390         PINMUX_IPSR_MSEL(IP16_23_20,    TS_SDAT0_E,             SEL_TSIF0_4),
1391         PINMUX_IPSR_MSEL(IP16_23_20,    STP_ISD_0_E,            SEL_SSP1_0_4),
1392         PINMUX_IPSR_MSEL(IP16_23_20,    FMIN_B,                 SEL_FM_1),
1393         PINMUX_IPSR_MSEL(IP16_23_20,    RIF2_SYNC_B,            SEL_DRIF2_1),
1394         PINMUX_IPSR_MSEL(IP16_23_20,    REMOCON_B,              SEL_REMOCON_1),
1395
1396         PINMUX_IPSR_GPSR(IP16_27_24,    USB30_PWEN),
1397         PINMUX_IPSR_MSEL(IP16_27_24,    AUDIO_CLKOUT_B,         SEL_ADG_1),
1398         PINMUX_IPSR_MSEL(IP16_27_24,    SSI_SCK2_B,             SEL_SSI_1),
1399         PINMUX_IPSR_MSEL(IP16_27_24,    TS_SDEN1_D,             SEL_TSIF1_3),
1400         PINMUX_IPSR_MSEL(IP16_27_24,    STP_ISEN_1_D,           SEL_SSP1_1_2),
1401         PINMUX_IPSR_MSEL(IP16_27_24,    STP_OPWM_0_E,           SEL_SSP1_0_4),
1402         PINMUX_IPSR_MSEL(IP16_27_24,    RIF3_D0_B,              SEL_DRIF3_1),
1403         PINMUX_IPSR_MSEL(IP16_27_24,    TCLK2_B,                SEL_TIMER_TMU_1),
1404         PINMUX_IPSR_GPSR(IP16_27_24,    TPU0TO0),
1405
1406         PINMUX_IPSR_GPSR(IP16_31_28,    USB30_OVC),
1407         PINMUX_IPSR_MSEL(IP16_31_28,    AUDIO_CLKOUT1_B,        SEL_ADG_1),
1408         PINMUX_IPSR_MSEL(IP16_31_28,    SSI_WS2_B,              SEL_SSI_1),
1409         PINMUX_IPSR_MSEL(IP16_31_28,    TS_SPSYNC1_D,           SEL_TSIF1_3),
1410         PINMUX_IPSR_MSEL(IP16_31_28,    STP_ISSYNC_1_D,         SEL_SSP1_1_3),
1411         PINMUX_IPSR_MSEL(IP16_31_28,    STP_IVCXO27_0_E,        SEL_SSP1_0_4),
1412         PINMUX_IPSR_MSEL(IP16_31_28,    RIF3_D1_B,              SEL_DRIF3_1),
1413         PINMUX_IPSR_MSEL(IP16_31_28,    FSO_TOE_B,              SEL_FSO_1),
1414         PINMUX_IPSR_GPSR(IP16_31_28,    TPU0TO1),
1415
1416         /* IPSR17 */
1417         PINMUX_IPSR_GPSR(IP17_3_0,      USB31_PWEN),
1418         PINMUX_IPSR_MSEL(IP17_3_0,      AUDIO_CLKOUT2_B,        SEL_ADG_1),
1419         PINMUX_IPSR_MSEL(IP17_3_0,      SSI_SCK9_B,             SEL_SSI_1),
1420         PINMUX_IPSR_MSEL(IP17_3_0,      TS_SDEN0_E,             SEL_TSIF0_4),
1421         PINMUX_IPSR_MSEL(IP17_3_0,      STP_ISEN_0_E,           SEL_SSP1_0_4),
1422         PINMUX_IPSR_MSEL(IP17_3_0,      RIF2_D0_B,              SEL_DRIF2_1),
1423         PINMUX_IPSR_GPSR(IP17_3_0,      TPU0TO2),
1424
1425         PINMUX_IPSR_GPSR(IP17_7_4,      USB31_OVC),
1426         PINMUX_IPSR_MSEL(IP17_7_4,      AUDIO_CLKOUT3_B,        SEL_ADG_1),
1427         PINMUX_IPSR_MSEL(IP17_7_4,      SSI_WS9_B,              SEL_SSI_1),
1428         PINMUX_IPSR_MSEL(IP17_7_4,      TS_SPSYNC0_E,           SEL_TSIF0_4),
1429         PINMUX_IPSR_MSEL(IP17_7_4,      STP_ISSYNC_0_E,         SEL_SSP1_0_4),
1430         PINMUX_IPSR_MSEL(IP17_7_4,      RIF2_D1_B,              SEL_DRIF2_1),
1431         PINMUX_IPSR_GPSR(IP17_7_4,      TPU0TO3),
1432
1433 /*
1434  * Static pins can not be muxed between different functions but
1435  * still needs a mark entry in the pinmux list. Add each static
1436  * pin to the list without an associated function. The sh-pfc
1437  * core will do the right thing and skip trying to mux then pin
1438  * while still applying configuration to it
1439  */
1440 #define FM(x)   PINMUX_DATA(x##_MARK, 0),
1441         PINMUX_STATIC
1442 #undef FM
1443 };
1444
1445 /*
1446  * R8A7795 has 8 banks with 32 PGIOS in each => 256 GPIOs.
1447  * Physical layout rows: A - AW, cols: 1 - 39.
1448  */
1449 #define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
1450 #define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
1451 #define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
1452
1453 static const struct sh_pfc_pin pinmux_pins[] = {
1454         PINMUX_GPIO_GP_ALL(),
1455
1456         /*
1457          * Pins not associated with a GPIO port.
1458          *
1459          * The pin positions are different between different r8a7795
1460          * packages, all that is needed for the pfc driver is a unique
1461          * number for each pin. To this end use the pin layout from
1462          * R-Car H3SiP to calculate a unique number for each pin.
1463          */
1464         SH_PFC_PIN_NAMED_CFG('A',  8, AVB_TX_CTL, CFG_FLAGS),
1465         SH_PFC_PIN_NAMED_CFG('A',  9, AVB_MDIO, CFG_FLAGS),
1466         SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS),
1467         SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS),
1468         SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS),
1469         SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS),
1470         SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS),
1471         SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS),
1472         SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS),
1473         SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS),
1474         SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS),
1475         SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS),
1476         SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS),
1477         SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS),
1478         SH_PFC_PIN_NAMED_CFG('C',  1, PRESETOUT#, CFG_FLAGS),
1479         SH_PFC_PIN_NAMED_CFG('F',  1, CLKOUT, CFG_FLAGS),
1480         SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS),
1481         SH_PFC_PIN_NAMED_CFG('V',  3, QSPI1_SPCLK, CFG_FLAGS),
1482         SH_PFC_PIN_NAMED_CFG('V',  5, QSPI1_SSL, CFG_FLAGS),
1483         SH_PFC_PIN_NAMED_CFG('V',  6, RPC_WP#, CFG_FLAGS),
1484         SH_PFC_PIN_NAMED_CFG('V',  7, RPC_RESET#, CFG_FLAGS),
1485         SH_PFC_PIN_NAMED_CFG('W',  3, QSPI0_SPCLK, CFG_FLAGS),
1486         SH_PFC_PIN_NAMED_CFG('Y',  3, QSPI0_SSL, CFG_FLAGS),
1487         SH_PFC_PIN_NAMED_CFG('Y',  6, QSPI0_IO2, CFG_FLAGS),
1488         SH_PFC_PIN_NAMED_CFG('Y',  7, RPC_INT#, CFG_FLAGS),
1489         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'),  4, QSPI0_MISO_IO1, CFG_FLAGS),
1490         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'),  6, QSPI0_IO3, CFG_FLAGS),
1491         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'),  3, QSPI1_IO3, CFG_FLAGS),
1492         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'),  5, QSPI0_MOSI_IO0, CFG_FLAGS),
1493         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'),  7, QSPI1_MOSI_IO0, CFG_FLAGS),
1494         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST#, CFG_FLAGS),
1495         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1496         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'),  4, QSPI1_IO2, CFG_FLAGS),
1497         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'),  5, QSPI1_MISO_IO1, CFG_FLAGS),
1498         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'),  7, DU_DOTCLKIN0, CFG_FLAGS),
1499         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'),  8, DU_DOTCLKIN1, CFG_FLAGS),
1500         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'),  7, DU_DOTCLKIN2, CFG_FLAGS),
1501         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'),  8, DU_DOTCLKIN3, CFG_FLAGS),
1502         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1503         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1504         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS),
1505         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1506         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1507         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
1508 };
1509
1510 /* - AUDIO CLOCK ------------------------------------------------------------ */
1511 static const unsigned int audio_clk_a_a_pins[] = {
1512         /* CLK A */
1513         RCAR_GP_PIN(6, 22),
1514 };
1515 static const unsigned int audio_clk_a_a_mux[] = {
1516         AUDIO_CLKA_A_MARK,
1517 };
1518 static const unsigned int audio_clk_a_b_pins[] = {
1519         /* CLK A */
1520         RCAR_GP_PIN(5, 4),
1521 };
1522 static const unsigned int audio_clk_a_b_mux[] = {
1523         AUDIO_CLKA_B_MARK,
1524 };
1525 static const unsigned int audio_clk_a_c_pins[] = {
1526         /* CLK A */
1527         RCAR_GP_PIN(5, 19),
1528 };
1529 static const unsigned int audio_clk_a_c_mux[] = {
1530         AUDIO_CLKA_C_MARK,
1531 };
1532 static const unsigned int audio_clk_b_a_pins[] = {
1533         /* CLK B */
1534         RCAR_GP_PIN(5, 12),
1535 };
1536 static const unsigned int audio_clk_b_a_mux[] = {
1537         AUDIO_CLKB_A_MARK,
1538 };
1539 static const unsigned int audio_clk_b_b_pins[] = {
1540         /* CLK B */
1541         RCAR_GP_PIN(6, 23),
1542 };
1543 static const unsigned int audio_clk_b_b_mux[] = {
1544         AUDIO_CLKB_B_MARK,
1545 };
1546 static const unsigned int audio_clk_c_a_pins[] = {
1547         /* CLK C */
1548         RCAR_GP_PIN(5, 21),
1549 };
1550 static const unsigned int audio_clk_c_a_mux[] = {
1551         AUDIO_CLKC_A_MARK,
1552 };
1553 static const unsigned int audio_clk_c_b_pins[] = {
1554         /* CLK C */
1555         RCAR_GP_PIN(5, 0),
1556 };
1557 static const unsigned int audio_clk_c_b_mux[] = {
1558         AUDIO_CLKC_B_MARK,
1559 };
1560 static const unsigned int audio_clkout_a_pins[] = {
1561         /* CLKOUT */
1562         RCAR_GP_PIN(5, 18),
1563 };
1564 static const unsigned int audio_clkout_a_mux[] = {
1565         AUDIO_CLKOUT_A_MARK,
1566 };
1567 static const unsigned int audio_clkout_b_pins[] = {
1568         /* CLKOUT */
1569         RCAR_GP_PIN(6, 28),
1570 };
1571 static const unsigned int audio_clkout_b_mux[] = {
1572         AUDIO_CLKOUT_B_MARK,
1573 };
1574 static const unsigned int audio_clkout_c_pins[] = {
1575         /* CLKOUT */
1576         RCAR_GP_PIN(5, 3),
1577 };
1578 static const unsigned int audio_clkout_c_mux[] = {
1579         AUDIO_CLKOUT_C_MARK,
1580 };
1581 static const unsigned int audio_clkout_d_pins[] = {
1582         /* CLKOUT */
1583         RCAR_GP_PIN(5, 21),
1584 };
1585 static const unsigned int audio_clkout_d_mux[] = {
1586         AUDIO_CLKOUT_D_MARK,
1587 };
1588 static const unsigned int audio_clkout1_a_pins[] = {
1589         /* CLKOUT1 */
1590         RCAR_GP_PIN(5, 15),
1591 };
1592 static const unsigned int audio_clkout1_a_mux[] = {
1593         AUDIO_CLKOUT1_A_MARK,
1594 };
1595 static const unsigned int audio_clkout1_b_pins[] = {
1596         /* CLKOUT1 */
1597         RCAR_GP_PIN(6, 29),
1598 };
1599 static const unsigned int audio_clkout1_b_mux[] = {
1600         AUDIO_CLKOUT1_B_MARK,
1601 };
1602 static const unsigned int audio_clkout2_a_pins[] = {
1603         /* CLKOUT2 */
1604         RCAR_GP_PIN(5, 16),
1605 };
1606 static const unsigned int audio_clkout2_a_mux[] = {
1607         AUDIO_CLKOUT2_A_MARK,
1608 };
1609 static const unsigned int audio_clkout2_b_pins[] = {
1610         /* CLKOUT2 */
1611         RCAR_GP_PIN(6, 30),
1612 };
1613 static const unsigned int audio_clkout2_b_mux[] = {
1614         AUDIO_CLKOUT2_B_MARK,
1615 };
1616
1617 static const unsigned int audio_clkout3_a_pins[] = {
1618         /* CLKOUT3 */
1619         RCAR_GP_PIN(5, 19),
1620 };
1621 static const unsigned int audio_clkout3_a_mux[] = {
1622         AUDIO_CLKOUT3_A_MARK,
1623 };
1624 static const unsigned int audio_clkout3_b_pins[] = {
1625         /* CLKOUT3 */
1626         RCAR_GP_PIN(6, 31),
1627 };
1628 static const unsigned int audio_clkout3_b_mux[] = {
1629         AUDIO_CLKOUT3_B_MARK,
1630 };
1631
1632 /* - EtherAVB --------------------------------------------------------------- */
1633 static const unsigned int avb_link_pins[] = {
1634         /* AVB_LINK */
1635         RCAR_GP_PIN(2, 12),
1636 };
1637 static const unsigned int avb_link_mux[] = {
1638         AVB_LINK_MARK,
1639 };
1640 static const unsigned int avb_magic_pins[] = {
1641         /* AVB_MAGIC_ */
1642         RCAR_GP_PIN(2, 10),
1643 };
1644 static const unsigned int avb_magic_mux[] = {
1645         AVB_MAGIC_MARK,
1646 };
1647 static const unsigned int avb_phy_int_pins[] = {
1648         /* AVB_PHY_INT */
1649         RCAR_GP_PIN(2, 11),
1650 };
1651 static const unsigned int avb_phy_int_mux[] = {
1652         AVB_PHY_INT_MARK,
1653 };
1654 static const unsigned int avb_mdc_pins[] = {
1655         /* AVB_MDC, AVB_MDIO */
1656         RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
1657 };
1658 static const unsigned int avb_mdc_mux[] = {
1659         AVB_MDC_MARK, AVB_MDIO_MARK,
1660 };
1661 static const unsigned int avb_mii_pins[] = {
1662         /*
1663          * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1664          * AVB_TD1, AVB_TD2, AVB_TD3,
1665          * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1666          * AVB_RD1, AVB_RD2, AVB_RD3,
1667          * AVB_TXCREFCLK
1668          */
1669         PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18),
1670         PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17),
1671         PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13),
1672         PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14),
1673         PIN_NUMBER('A', 12),
1674
1675 };
1676 static const unsigned int avb_mii_mux[] = {
1677         AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
1678         AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
1679         AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1680         AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1681         AVB_TXCREFCLK_MARK,
1682 };
1683 static const unsigned int avb_avtp_pps_pins[] = {
1684         /* AVB_AVTP_PPS */
1685         RCAR_GP_PIN(2, 6),
1686 };
1687 static const unsigned int avb_avtp_pps_mux[] = {
1688         AVB_AVTP_PPS_MARK,
1689 };
1690 static const unsigned int avb_avtp_match_a_pins[] = {
1691         /* AVB_AVTP_MATCH_A */
1692         RCAR_GP_PIN(2, 13),
1693 };
1694 static const unsigned int avb_avtp_match_a_mux[] = {
1695         AVB_AVTP_MATCH_A_MARK,
1696 };
1697 static const unsigned int avb_avtp_capture_a_pins[] = {
1698         /* AVB_AVTP_CAPTURE_A */
1699         RCAR_GP_PIN(2, 14),
1700 };
1701 static const unsigned int avb_avtp_capture_a_mux[] = {
1702         AVB_AVTP_CAPTURE_A_MARK,
1703 };
1704 static const unsigned int avb_avtp_match_b_pins[] = {
1705         /*  AVB_AVTP_MATCH_B */
1706         RCAR_GP_PIN(1, 8),
1707 };
1708 static const unsigned int avb_avtp_match_b_mux[] = {
1709         AVB_AVTP_MATCH_B_MARK,
1710 };
1711 static const unsigned int avb_avtp_capture_b_pins[] = {
1712         /* AVB_AVTP_CAPTURE_B */
1713         RCAR_GP_PIN(1, 11),
1714 };
1715 static const unsigned int avb_avtp_capture_b_mux[] = {
1716         AVB_AVTP_CAPTURE_B_MARK,
1717 };
1718
1719 /* - CAN ------------------------------------------------------------------ */
1720 static const unsigned int can0_data_a_pins[] = {
1721         /* TX, RX */
1722         RCAR_GP_PIN(1, 23),     RCAR_GP_PIN(1, 24),
1723 };
1724 static const unsigned int can0_data_a_mux[] = {
1725         CAN0_TX_A_MARK,         CAN0_RX_A_MARK,
1726 };
1727 static const unsigned int can0_data_b_pins[] = {
1728         /* TX, RX */
1729         RCAR_GP_PIN(2, 0),      RCAR_GP_PIN(2, 1),
1730 };
1731 static const unsigned int can0_data_b_mux[] = {
1732         CAN0_TX_B_MARK,         CAN0_RX_B_MARK,
1733 };
1734 static const unsigned int can1_data_pins[] = {
1735         /* TX, RX */
1736         RCAR_GP_PIN(1, 22),     RCAR_GP_PIN(1, 26),
1737 };
1738 static const unsigned int can1_data_mux[] = {
1739         CAN1_TX_MARK,           CAN1_RX_MARK,
1740 };
1741
1742 /* - CAN Clock -------------------------------------------------------------- */
1743 static const unsigned int can_clk_pins[] = {
1744         /* CLK */
1745         RCAR_GP_PIN(1, 25),
1746 };
1747 static const unsigned int can_clk_mux[] = {
1748         CAN_CLK_MARK,
1749 };
1750
1751 /* - CAN FD --------------------------------------------------------------- */
1752 static const unsigned int canfd0_data_a_pins[] = {
1753         /* TX, RX */
1754         RCAR_GP_PIN(1, 23),     RCAR_GP_PIN(1, 24),
1755 };
1756 static const unsigned int canfd0_data_a_mux[] = {
1757         CANFD0_TX_A_MARK,       CANFD0_RX_A_MARK,
1758 };
1759 static const unsigned int canfd0_data_b_pins[] = {
1760         /* TX, RX */
1761         RCAR_GP_PIN(2, 0),      RCAR_GP_PIN(2, 1),
1762 };
1763 static const unsigned int canfd0_data_b_mux[] = {
1764         CANFD0_TX_B_MARK,       CANFD0_RX_B_MARK,
1765 };
1766 static const unsigned int canfd1_data_pins[] = {
1767         /* TX, RX */
1768         RCAR_GP_PIN(1, 22),     RCAR_GP_PIN(1, 26),
1769 };
1770 static const unsigned int canfd1_data_mux[] = {
1771         CANFD1_TX_MARK,         CANFD1_RX_MARK,
1772 };
1773
1774 /* - DRIF0 --------------------------------------------------------------- */
1775 static const unsigned int drif0_ctrl_a_pins[] = {
1776         /* CLK, SYNC */
1777         RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1778 };
1779 static const unsigned int drif0_ctrl_a_mux[] = {
1780         RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
1781 };
1782 static const unsigned int drif0_data0_a_pins[] = {
1783         /* D0 */
1784         RCAR_GP_PIN(6, 10),
1785 };
1786 static const unsigned int drif0_data0_a_mux[] = {
1787         RIF0_D0_A_MARK,
1788 };
1789 static const unsigned int drif0_data1_a_pins[] = {
1790         /* D1 */
1791         RCAR_GP_PIN(6, 7),
1792 };
1793 static const unsigned int drif0_data1_a_mux[] = {
1794         RIF0_D1_A_MARK,
1795 };
1796 static const unsigned int drif0_ctrl_b_pins[] = {
1797         /* CLK, SYNC */
1798         RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
1799 };
1800 static const unsigned int drif0_ctrl_b_mux[] = {
1801         RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
1802 };
1803 static const unsigned int drif0_data0_b_pins[] = {
1804         /* D0 */
1805         RCAR_GP_PIN(5, 1),
1806 };
1807 static const unsigned int drif0_data0_b_mux[] = {
1808         RIF0_D0_B_MARK,
1809 };
1810 static const unsigned int drif0_data1_b_pins[] = {
1811         /* D1 */
1812         RCAR_GP_PIN(5, 2),
1813 };
1814 static const unsigned int drif0_data1_b_mux[] = {
1815         RIF0_D1_B_MARK,
1816 };
1817 static const unsigned int drif0_ctrl_c_pins[] = {
1818         /* CLK, SYNC */
1819         RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
1820 };
1821 static const unsigned int drif0_ctrl_c_mux[] = {
1822         RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
1823 };
1824 static const unsigned int drif0_data0_c_pins[] = {
1825         /* D0 */
1826         RCAR_GP_PIN(5, 13),
1827 };
1828 static const unsigned int drif0_data0_c_mux[] = {
1829         RIF0_D0_C_MARK,
1830 };
1831 static const unsigned int drif0_data1_c_pins[] = {
1832         /* D1 */
1833         RCAR_GP_PIN(5, 14),
1834 };
1835 static const unsigned int drif0_data1_c_mux[] = {
1836         RIF0_D1_C_MARK,
1837 };
1838 /* - DRIF1 --------------------------------------------------------------- */
1839 static const unsigned int drif1_ctrl_a_pins[] = {
1840         /* CLK, SYNC */
1841         RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1842 };
1843 static const unsigned int drif1_ctrl_a_mux[] = {
1844         RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
1845 };
1846 static const unsigned int drif1_data0_a_pins[] = {
1847         /* D0 */
1848         RCAR_GP_PIN(6, 19),
1849 };
1850 static const unsigned int drif1_data0_a_mux[] = {
1851         RIF1_D0_A_MARK,
1852 };
1853 static const unsigned int drif1_data1_a_pins[] = {
1854         /* D1 */
1855         RCAR_GP_PIN(6, 20),
1856 };
1857 static const unsigned int drif1_data1_a_mux[] = {
1858         RIF1_D1_A_MARK,
1859 };
1860 static const unsigned int drif1_ctrl_b_pins[] = {
1861         /* CLK, SYNC */
1862         RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
1863 };
1864 static const unsigned int drif1_ctrl_b_mux[] = {
1865         RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
1866 };
1867 static const unsigned int drif1_data0_b_pins[] = {
1868         /* D0 */
1869         RCAR_GP_PIN(5, 7),
1870 };
1871 static const unsigned int drif1_data0_b_mux[] = {
1872         RIF1_D0_B_MARK,
1873 };
1874 static const unsigned int drif1_data1_b_pins[] = {
1875         /* D1 */
1876         RCAR_GP_PIN(5, 8),
1877 };
1878 static const unsigned int drif1_data1_b_mux[] = {
1879         RIF1_D1_B_MARK,
1880 };
1881 static const unsigned int drif1_ctrl_c_pins[] = {
1882         /* CLK, SYNC */
1883         RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
1884 };
1885 static const unsigned int drif1_ctrl_c_mux[] = {
1886         RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
1887 };
1888 static const unsigned int drif1_data0_c_pins[] = {
1889         /* D0 */
1890         RCAR_GP_PIN(5, 6),
1891 };
1892 static const unsigned int drif1_data0_c_mux[] = {
1893         RIF1_D0_C_MARK,
1894 };
1895 static const unsigned int drif1_data1_c_pins[] = {
1896         /* D1 */
1897         RCAR_GP_PIN(5, 10),
1898 };
1899 static const unsigned int drif1_data1_c_mux[] = {
1900         RIF1_D1_C_MARK,
1901 };
1902 /* - DRIF2 --------------------------------------------------------------- */
1903 static const unsigned int drif2_ctrl_a_pins[] = {
1904         /* CLK, SYNC */
1905         RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1906 };
1907 static const unsigned int drif2_ctrl_a_mux[] = {
1908         RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
1909 };
1910 static const unsigned int drif2_data0_a_pins[] = {
1911         /* D0 */
1912         RCAR_GP_PIN(6, 7),
1913 };
1914 static const unsigned int drif2_data0_a_mux[] = {
1915         RIF2_D0_A_MARK,
1916 };
1917 static const unsigned int drif2_data1_a_pins[] = {
1918         /* D1 */
1919         RCAR_GP_PIN(6, 10),
1920 };
1921 static const unsigned int drif2_data1_a_mux[] = {
1922         RIF2_D1_A_MARK,
1923 };
1924 static const unsigned int drif2_ctrl_b_pins[] = {
1925         /* CLK, SYNC */
1926         RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
1927 };
1928 static const unsigned int drif2_ctrl_b_mux[] = {
1929         RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
1930 };
1931 static const unsigned int drif2_data0_b_pins[] = {
1932         /* D0 */
1933         RCAR_GP_PIN(6, 30),
1934 };
1935 static const unsigned int drif2_data0_b_mux[] = {
1936         RIF2_D0_B_MARK,
1937 };
1938 static const unsigned int drif2_data1_b_pins[] = {
1939         /* D1 */
1940         RCAR_GP_PIN(6, 31),
1941 };
1942 static const unsigned int drif2_data1_b_mux[] = {
1943         RIF2_D1_B_MARK,
1944 };
1945 /* - DRIF3 --------------------------------------------------------------- */
1946 static const unsigned int drif3_ctrl_a_pins[] = {
1947         /* CLK, SYNC */
1948         RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1949 };
1950 static const unsigned int drif3_ctrl_a_mux[] = {
1951         RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
1952 };
1953 static const unsigned int drif3_data0_a_pins[] = {
1954         /* D0 */
1955         RCAR_GP_PIN(6, 19),
1956 };
1957 static const unsigned int drif3_data0_a_mux[] = {
1958         RIF3_D0_A_MARK,
1959 };
1960 static const unsigned int drif3_data1_a_pins[] = {
1961         /* D1 */
1962         RCAR_GP_PIN(6, 20),
1963 };
1964 static const unsigned int drif3_data1_a_mux[] = {
1965         RIF3_D1_A_MARK,
1966 };
1967 static const unsigned int drif3_ctrl_b_pins[] = {
1968         /* CLK, SYNC */
1969         RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
1970 };
1971 static const unsigned int drif3_ctrl_b_mux[] = {
1972         RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
1973 };
1974 static const unsigned int drif3_data0_b_pins[] = {
1975         /* D0 */
1976         RCAR_GP_PIN(6, 28),
1977 };
1978 static const unsigned int drif3_data0_b_mux[] = {
1979         RIF3_D0_B_MARK,
1980 };
1981 static const unsigned int drif3_data1_b_pins[] = {
1982         /* D1 */
1983         RCAR_GP_PIN(6, 29),
1984 };
1985 static const unsigned int drif3_data1_b_mux[] = {
1986         RIF3_D1_B_MARK,
1987 };
1988
1989 /* - DU --------------------------------------------------------------------- */
1990 static const unsigned int du_rgb666_pins[] = {
1991         /* R[7:2], G[7:2], B[7:2] */
1992         RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
1993         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
1994         RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
1995         RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
1996         RCAR_GP_PIN(1, 7),  RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),
1997         RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),
1998 };
1999 static const unsigned int du_rgb666_mux[] = {
2000         DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2001         DU_DR3_MARK, DU_DR2_MARK,
2002         DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2003         DU_DG3_MARK, DU_DG2_MARK,
2004         DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2005         DU_DB3_MARK, DU_DB2_MARK,
2006 };
2007 static const unsigned int du_rgb888_pins[] = {
2008         /* R[7:0], G[7:0], B[7:0] */
2009         RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2010         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2011         RCAR_GP_PIN(0, 9),  RCAR_GP_PIN(0, 8),
2012         RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2013         RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2014         RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
2015         RCAR_GP_PIN(1, 7),  RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),
2016         RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),
2017         RCAR_GP_PIN(1, 1),  RCAR_GP_PIN(1, 0),
2018 };
2019 static const unsigned int du_rgb888_mux[] = {
2020         DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2021         DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
2022         DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2023         DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
2024         DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2025         DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
2026 };
2027 static const unsigned int du_clk_out_0_pins[] = {
2028         /* CLKOUT */
2029         RCAR_GP_PIN(1, 27),
2030 };
2031 static const unsigned int du_clk_out_0_mux[] = {
2032         DU_DOTCLKOUT0_MARK
2033 };
2034 static const unsigned int du_clk_out_1_pins[] = {
2035         /* CLKOUT */
2036         RCAR_GP_PIN(2, 3),
2037 };
2038 static const unsigned int du_clk_out_1_mux[] = {
2039         DU_DOTCLKOUT1_MARK
2040 };
2041 static const unsigned int du_sync_pins[] = {
2042         /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
2043         RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
2044 };
2045 static const unsigned int du_sync_mux[] = {
2046         DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
2047 };
2048 static const unsigned int du_oddf_pins[] = {
2049         /* EXDISP/EXODDF/EXCDE */
2050         RCAR_GP_PIN(2, 2),
2051 };
2052 static const unsigned int du_oddf_mux[] = {
2053         DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
2054 };
2055 static const unsigned int du_cde_pins[] = {
2056         /* CDE */
2057         RCAR_GP_PIN(2, 0),
2058 };
2059 static const unsigned int du_cde_mux[] = {
2060         DU_CDE_MARK,
2061 };
2062 static const unsigned int du_disp_pins[] = {
2063         /* DISP */
2064         RCAR_GP_PIN(2, 1),
2065 };
2066 static const unsigned int du_disp_mux[] = {
2067         DU_DISP_MARK,
2068 };
2069 /* - HSCIF0 ----------------------------------------------------------------- */
2070 static const unsigned int hscif0_data_pins[] = {
2071         /* RX, TX */
2072         RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2073 };
2074 static const unsigned int hscif0_data_mux[] = {
2075         HRX0_MARK, HTX0_MARK,
2076 };
2077 static const unsigned int hscif0_clk_pins[] = {
2078         /* SCK */
2079         RCAR_GP_PIN(5, 12),
2080 };
2081 static const unsigned int hscif0_clk_mux[] = {
2082         HSCK0_MARK,
2083 };
2084 static const unsigned int hscif0_ctrl_pins[] = {
2085         /* RTS, CTS */
2086         RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
2087 };
2088 static const unsigned int hscif0_ctrl_mux[] = {
2089         HRTS0_N_MARK, HCTS0_N_MARK,
2090 };
2091 /* - HSCIF1 ----------------------------------------------------------------- */
2092 static const unsigned int hscif1_data_a_pins[] = {
2093         /* RX, TX */
2094         RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2095 };
2096 static const unsigned int hscif1_data_a_mux[] = {
2097         HRX1_A_MARK, HTX1_A_MARK,
2098 };
2099 static const unsigned int hscif1_clk_a_pins[] = {
2100         /* SCK */
2101         RCAR_GP_PIN(6, 21),
2102 };
2103 static const unsigned int hscif1_clk_a_mux[] = {
2104         HSCK1_A_MARK,
2105 };
2106 static const unsigned int hscif1_ctrl_a_pins[] = {
2107         /* RTS, CTS */
2108         RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
2109 };
2110 static const unsigned int hscif1_ctrl_a_mux[] = {
2111         HRTS1_N_A_MARK, HCTS1_N_A_MARK,
2112 };
2113
2114 static const unsigned int hscif1_data_b_pins[] = {
2115         /* RX, TX */
2116         RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2117 };
2118 static const unsigned int hscif1_data_b_mux[] = {
2119         HRX1_B_MARK, HTX1_B_MARK,
2120 };
2121 static const unsigned int hscif1_clk_b_pins[] = {
2122         /* SCK */
2123         RCAR_GP_PIN(5, 0),
2124 };
2125 static const unsigned int hscif1_clk_b_mux[] = {
2126         HSCK1_B_MARK,
2127 };
2128 static const unsigned int hscif1_ctrl_b_pins[] = {
2129         /* RTS, CTS */
2130         RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2131 };
2132 static const unsigned int hscif1_ctrl_b_mux[] = {
2133         HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2134 };
2135 /* - HSCIF2 ----------------------------------------------------------------- */
2136 static const unsigned int hscif2_data_a_pins[] = {
2137         /* RX, TX */
2138         RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2139 };
2140 static const unsigned int hscif2_data_a_mux[] = {
2141         HRX2_A_MARK, HTX2_A_MARK,
2142 };
2143 static const unsigned int hscif2_clk_a_pins[] = {
2144         /* SCK */
2145         RCAR_GP_PIN(6, 10),
2146 };
2147 static const unsigned int hscif2_clk_a_mux[] = {
2148         HSCK2_A_MARK,
2149 };
2150 static const unsigned int hscif2_ctrl_a_pins[] = {
2151         /* RTS, CTS */
2152         RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2153 };
2154 static const unsigned int hscif2_ctrl_a_mux[] = {
2155         HRTS2_N_A_MARK, HCTS2_N_A_MARK,
2156 };
2157
2158 static const unsigned int hscif2_data_b_pins[] = {
2159         /* RX, TX */
2160         RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2161 };
2162 static const unsigned int hscif2_data_b_mux[] = {
2163         HRX2_B_MARK, HTX2_B_MARK,
2164 };
2165 static const unsigned int hscif2_clk_b_pins[] = {
2166         /* SCK */
2167         RCAR_GP_PIN(6, 21),
2168 };
2169 static const unsigned int hscif2_clk_b_mux[] = {
2170         HSCK2_B_MARK,
2171 };
2172 static const unsigned int hscif2_ctrl_b_pins[] = {
2173         /* RTS, CTS */
2174         RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
2175 };
2176 static const unsigned int hscif2_ctrl_b_mux[] = {
2177         HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2178 };
2179 /* - HSCIF3 ----------------------------------------------------------------- */
2180 static const unsigned int hscif3_data_a_pins[] = {
2181         /* RX, TX */
2182         RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
2183 };
2184 static const unsigned int hscif3_data_a_mux[] = {
2185         HRX3_A_MARK, HTX3_A_MARK,
2186 };
2187 static const unsigned int hscif3_clk_pins[] = {
2188         /* SCK */
2189         RCAR_GP_PIN(1, 22),
2190 };
2191 static const unsigned int hscif3_clk_mux[] = {
2192         HSCK3_MARK,
2193 };
2194 static const unsigned int hscif3_ctrl_pins[] = {
2195         /* RTS, CTS */
2196         RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2197 };
2198 static const unsigned int hscif3_ctrl_mux[] = {
2199         HRTS3_N_MARK, HCTS3_N_MARK,
2200 };
2201
2202 static const unsigned int hscif3_data_b_pins[] = {
2203         /* RX, TX */
2204         RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
2205 };
2206 static const unsigned int hscif3_data_b_mux[] = {
2207         HRX3_B_MARK, HTX3_B_MARK,
2208 };
2209 static const unsigned int hscif3_data_c_pins[] = {
2210         /* RX, TX */
2211         RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2212 };
2213 static const unsigned int hscif3_data_c_mux[] = {
2214         HRX3_C_MARK, HTX3_C_MARK,
2215 };
2216 static const unsigned int hscif3_data_d_pins[] = {
2217         /* RX, TX */
2218         RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2219 };
2220 static const unsigned int hscif3_data_d_mux[] = {
2221         HRX3_D_MARK, HTX3_D_MARK,
2222 };
2223 /* - HSCIF4 ----------------------------------------------------------------- */
2224 static const unsigned int hscif4_data_a_pins[] = {
2225         /* RX, TX */
2226         RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
2227 };
2228 static const unsigned int hscif4_data_a_mux[] = {
2229         HRX4_A_MARK, HTX4_A_MARK,
2230 };
2231 static const unsigned int hscif4_clk_pins[] = {
2232         /* SCK */
2233         RCAR_GP_PIN(1, 11),
2234 };
2235 static const unsigned int hscif4_clk_mux[] = {
2236         HSCK4_MARK,
2237 };
2238 static const unsigned int hscif4_ctrl_pins[] = {
2239         /* RTS, CTS */
2240         RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
2241 };
2242 static const unsigned int hscif4_ctrl_mux[] = {
2243         HRTS4_N_MARK, HCTS4_N_MARK,
2244 };
2245
2246 static const unsigned int hscif4_data_b_pins[] = {
2247         /* RX, TX */
2248         RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2249 };
2250 static const unsigned int hscif4_data_b_mux[] = {
2251         HRX4_B_MARK, HTX4_B_MARK,
2252 };
2253
2254 /* - I2C -------------------------------------------------------------------- */
2255 static const unsigned int i2c1_a_pins[] = {
2256         /* SDA, SCL */
2257         RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2258 };
2259 static const unsigned int i2c1_a_mux[] = {
2260         SDA1_A_MARK, SCL1_A_MARK,
2261 };
2262 static const unsigned int i2c1_b_pins[] = {
2263         /* SDA, SCL */
2264         RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
2265 };
2266 static const unsigned int i2c1_b_mux[] = {
2267         SDA1_B_MARK, SCL1_B_MARK,
2268 };
2269 static const unsigned int i2c2_a_pins[] = {
2270         /* SDA, SCL */
2271         RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
2272 };
2273 static const unsigned int i2c2_a_mux[] = {
2274         SDA2_A_MARK, SCL2_A_MARK,
2275 };
2276 static const unsigned int i2c2_b_pins[] = {
2277         /* SDA, SCL */
2278         RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
2279 };
2280 static const unsigned int i2c2_b_mux[] = {
2281         SDA2_B_MARK, SCL2_B_MARK,
2282 };
2283 static const unsigned int i2c6_a_pins[] = {
2284         /* SDA, SCL */
2285         RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2286 };
2287 static const unsigned int i2c6_a_mux[] = {
2288         SDA6_A_MARK, SCL6_A_MARK,
2289 };
2290 static const unsigned int i2c6_b_pins[] = {
2291         /* SDA, SCL */
2292         RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2293 };
2294 static const unsigned int i2c6_b_mux[] = {
2295         SDA6_B_MARK, SCL6_B_MARK,
2296 };
2297 static const unsigned int i2c6_c_pins[] = {
2298         /* SDA, SCL */
2299         RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2300 };
2301 static const unsigned int i2c6_c_mux[] = {
2302         SDA6_C_MARK, SCL6_C_MARK,
2303 };
2304
2305 /* - INTC-EX ---------------------------------------------------------------- */
2306 static const unsigned int intc_ex_irq0_pins[] = {
2307         /* IRQ0 */
2308         RCAR_GP_PIN(2, 0),
2309 };
2310 static const unsigned int intc_ex_irq0_mux[] = {
2311         IRQ0_MARK,
2312 };
2313 static const unsigned int intc_ex_irq1_pins[] = {
2314         /* IRQ1 */
2315         RCAR_GP_PIN(2, 1),
2316 };
2317 static const unsigned int intc_ex_irq1_mux[] = {
2318         IRQ1_MARK,
2319 };
2320 static const unsigned int intc_ex_irq2_pins[] = {
2321         /* IRQ2 */
2322         RCAR_GP_PIN(2, 2),
2323 };
2324 static const unsigned int intc_ex_irq2_mux[] = {
2325         IRQ2_MARK,
2326 };
2327 static const unsigned int intc_ex_irq3_pins[] = {
2328         /* IRQ3 */
2329         RCAR_GP_PIN(2, 3),
2330 };
2331 static const unsigned int intc_ex_irq3_mux[] = {
2332         IRQ3_MARK,
2333 };
2334 static const unsigned int intc_ex_irq4_pins[] = {
2335         /* IRQ4 */
2336         RCAR_GP_PIN(2, 4),
2337 };
2338 static const unsigned int intc_ex_irq4_mux[] = {
2339         IRQ4_MARK,
2340 };
2341 static const unsigned int intc_ex_irq5_pins[] = {
2342         /* IRQ5 */
2343         RCAR_GP_PIN(2, 5),
2344 };
2345 static const unsigned int intc_ex_irq5_mux[] = {
2346         IRQ5_MARK,
2347 };
2348
2349 /* - MSIOF0 ----------------------------------------------------------------- */
2350 static const unsigned int msiof0_clk_pins[] = {
2351         /* SCK */
2352         RCAR_GP_PIN(5, 17),
2353 };
2354 static const unsigned int msiof0_clk_mux[] = {
2355         MSIOF0_SCK_MARK,
2356 };
2357 static const unsigned int msiof0_sync_pins[] = {
2358         /* SYNC */
2359         RCAR_GP_PIN(5, 18),
2360 };
2361 static const unsigned int msiof0_sync_mux[] = {
2362         MSIOF0_SYNC_MARK,
2363 };
2364 static const unsigned int msiof0_ss1_pins[] = {
2365         /* SS1 */
2366         RCAR_GP_PIN(5, 19),
2367 };
2368 static const unsigned int msiof0_ss1_mux[] = {
2369         MSIOF0_SS1_MARK,
2370 };
2371 static const unsigned int msiof0_ss2_pins[] = {
2372         /* SS2 */
2373         RCAR_GP_PIN(5, 21),
2374 };
2375 static const unsigned int msiof0_ss2_mux[] = {
2376         MSIOF0_SS2_MARK,
2377 };
2378 static const unsigned int msiof0_txd_pins[] = {
2379         /* TXD */
2380         RCAR_GP_PIN(5, 20),
2381 };
2382 static const unsigned int msiof0_txd_mux[] = {
2383         MSIOF0_TXD_MARK,
2384 };
2385 static const unsigned int msiof0_rxd_pins[] = {
2386         /* RXD */
2387         RCAR_GP_PIN(5, 22),
2388 };
2389 static const unsigned int msiof0_rxd_mux[] = {
2390         MSIOF0_RXD_MARK,
2391 };
2392 /* - MSIOF1 ----------------------------------------------------------------- */
2393 static const unsigned int msiof1_clk_a_pins[] = {
2394         /* SCK */
2395         RCAR_GP_PIN(6, 8),
2396 };
2397 static const unsigned int msiof1_clk_a_mux[] = {
2398         MSIOF1_SCK_A_MARK,
2399 };
2400 static const unsigned int msiof1_sync_a_pins[] = {
2401         /* SYNC */
2402         RCAR_GP_PIN(6, 9),
2403 };
2404 static const unsigned int msiof1_sync_a_mux[] = {
2405         MSIOF1_SYNC_A_MARK,
2406 };
2407 static const unsigned int msiof1_ss1_a_pins[] = {
2408         /* SS1 */
2409         RCAR_GP_PIN(6, 5),
2410 };
2411 static const unsigned int msiof1_ss1_a_mux[] = {
2412         MSIOF1_SS1_A_MARK,
2413 };
2414 static const unsigned int msiof1_ss2_a_pins[] = {
2415         /* SS2 */
2416         RCAR_GP_PIN(6, 6),
2417 };
2418 static const unsigned int msiof1_ss2_a_mux[] = {
2419         MSIOF1_SS2_A_MARK,
2420 };
2421 static const unsigned int msiof1_txd_a_pins[] = {
2422         /* TXD */
2423         RCAR_GP_PIN(6, 7),
2424 };
2425 static const unsigned int msiof1_txd_a_mux[] = {
2426         MSIOF1_TXD_A_MARK,
2427 };
2428 static const unsigned int msiof1_rxd_a_pins[] = {
2429         /* RXD */
2430         RCAR_GP_PIN(6, 10),
2431 };
2432 static const unsigned int msiof1_rxd_a_mux[] = {
2433         MSIOF1_RXD_A_MARK,
2434 };
2435 static const unsigned int msiof1_clk_b_pins[] = {
2436         /* SCK */
2437         RCAR_GP_PIN(5, 9),
2438 };
2439 static const unsigned int msiof1_clk_b_mux[] = {
2440         MSIOF1_SCK_B_MARK,
2441 };
2442 static const unsigned int msiof1_sync_b_pins[] = {
2443         /* SYNC */
2444         RCAR_GP_PIN(5, 3),
2445 };
2446 static const unsigned int msiof1_sync_b_mux[] = {
2447         MSIOF1_SYNC_B_MARK,
2448 };
2449 static const unsigned int msiof1_ss1_b_pins[] = {
2450         /* SS1 */
2451         RCAR_GP_PIN(5, 4),
2452 };
2453 static const unsigned int msiof1_ss1_b_mux[] = {
2454         MSIOF1_SS1_B_MARK,
2455 };
2456 static const unsigned int msiof1_ss2_b_pins[] = {
2457         /* SS2 */
2458         RCAR_GP_PIN(5, 0),
2459 };
2460 static const unsigned int msiof1_ss2_b_mux[] = {
2461         MSIOF1_SS2_B_MARK,
2462 };
2463 static const unsigned int msiof1_txd_b_pins[] = {
2464         /* TXD */
2465         RCAR_GP_PIN(5, 8),
2466 };
2467 static const unsigned int msiof1_txd_b_mux[] = {
2468         MSIOF1_TXD_B_MARK,
2469 };
2470 static const unsigned int msiof1_rxd_b_pins[] = {
2471         /* RXD */
2472         RCAR_GP_PIN(5, 7),
2473 };
2474 static const unsigned int msiof1_rxd_b_mux[] = {
2475         MSIOF1_RXD_B_MARK,
2476 };
2477 static const unsigned int msiof1_clk_c_pins[] = {
2478         /* SCK */
2479         RCAR_GP_PIN(6, 17),
2480 };
2481 static const unsigned int msiof1_clk_c_mux[] = {
2482         MSIOF1_SCK_C_MARK,
2483 };
2484 static const unsigned int msiof1_sync_c_pins[] = {
2485         /* SYNC */
2486         RCAR_GP_PIN(6, 18),
2487 };
2488 static const unsigned int msiof1_sync_c_mux[] = {
2489         MSIOF1_SYNC_C_MARK,
2490 };
2491 static const unsigned int msiof1_ss1_c_pins[] = {
2492         /* SS1 */
2493         RCAR_GP_PIN(6, 21),
2494 };
2495 static const unsigned int msiof1_ss1_c_mux[] = {
2496         MSIOF1_SS1_C_MARK,
2497 };
2498 static const unsigned int msiof1_ss2_c_pins[] = {
2499         /* SS2 */
2500         RCAR_GP_PIN(6, 27),
2501 };
2502 static const unsigned int msiof1_ss2_c_mux[] = {
2503         MSIOF1_SS2_C_MARK,
2504 };
2505 static const unsigned int msiof1_txd_c_pins[] = {
2506         /* TXD */
2507         RCAR_GP_PIN(6, 20),
2508 };
2509 static const unsigned int msiof1_txd_c_mux[] = {
2510         MSIOF1_TXD_C_MARK,
2511 };
2512 static const unsigned int msiof1_rxd_c_pins[] = {
2513         /* RXD */
2514         RCAR_GP_PIN(6, 19),
2515 };
2516 static const unsigned int msiof1_rxd_c_mux[] = {
2517         MSIOF1_RXD_C_MARK,
2518 };
2519 static const unsigned int msiof1_clk_d_pins[] = {
2520         /* SCK */
2521         RCAR_GP_PIN(5, 12),
2522 };
2523 static const unsigned int msiof1_clk_d_mux[] = {
2524         MSIOF1_SCK_D_MARK,
2525 };
2526 static const unsigned int msiof1_sync_d_pins[] = {
2527         /* SYNC */
2528         RCAR_GP_PIN(5, 15),
2529 };
2530 static const unsigned int msiof1_sync_d_mux[] = {
2531         MSIOF1_SYNC_D_MARK,
2532 };
2533 static const unsigned int msiof1_ss1_d_pins[] = {
2534         /* SS1 */
2535         RCAR_GP_PIN(5, 16),
2536 };
2537 static const unsigned int msiof1_ss1_d_mux[] = {
2538         MSIOF1_SS1_D_MARK,
2539 };
2540 static const unsigned int msiof1_ss2_d_pins[] = {
2541         /* SS2 */
2542         RCAR_GP_PIN(5, 21),
2543 };
2544 static const unsigned int msiof1_ss2_d_mux[] = {
2545         MSIOF1_SS2_D_MARK,
2546 };
2547 static const unsigned int msiof1_txd_d_pins[] = {
2548         /* TXD */
2549         RCAR_GP_PIN(5, 14),
2550 };
2551 static const unsigned int msiof1_txd_d_mux[] = {
2552         MSIOF1_TXD_D_MARK,
2553 };
2554 static const unsigned int msiof1_rxd_d_pins[] = {
2555         /* RXD */
2556         RCAR_GP_PIN(5, 13),
2557 };
2558 static const unsigned int msiof1_rxd_d_mux[] = {
2559         MSIOF1_RXD_D_MARK,
2560 };
2561 static const unsigned int msiof1_clk_e_pins[] = {
2562         /* SCK */
2563         RCAR_GP_PIN(3, 0),
2564 };
2565 static const unsigned int msiof1_clk_e_mux[] = {
2566         MSIOF1_SCK_E_MARK,
2567 };
2568 static const unsigned int msiof1_sync_e_pins[] = {
2569         /* SYNC */
2570         RCAR_GP_PIN(3, 1),
2571 };
2572 static const unsigned int msiof1_sync_e_mux[] = {
2573         MSIOF1_SYNC_E_MARK,
2574 };
2575 static const unsigned int msiof1_ss1_e_pins[] = {
2576         /* SS1 */
2577         RCAR_GP_PIN(3, 4),
2578 };
2579 static const unsigned int msiof1_ss1_e_mux[] = {
2580         MSIOF1_SS1_E_MARK,
2581 };
2582 static const unsigned int msiof1_ss2_e_pins[] = {
2583         /* SS2 */
2584         RCAR_GP_PIN(3, 5),
2585 };
2586 static const unsigned int msiof1_ss2_e_mux[] = {
2587         MSIOF1_SS2_E_MARK,
2588 };
2589 static const unsigned int msiof1_txd_e_pins[] = {
2590         /* TXD */
2591         RCAR_GP_PIN(3, 3),
2592 };
2593 static const unsigned int msiof1_txd_e_mux[] = {
2594         MSIOF1_TXD_E_MARK,
2595 };
2596 static const unsigned int msiof1_rxd_e_pins[] = {
2597         /* RXD */
2598         RCAR_GP_PIN(3, 2),
2599 };
2600 static const unsigned int msiof1_rxd_e_mux[] = {
2601         MSIOF1_RXD_E_MARK,
2602 };
2603 static const unsigned int msiof1_clk_f_pins[] = {
2604         /* SCK */
2605         RCAR_GP_PIN(5, 23),
2606 };
2607 static const unsigned int msiof1_clk_f_mux[] = {
2608         MSIOF1_SCK_F_MARK,
2609 };
2610 static const unsigned int msiof1_sync_f_pins[] = {
2611         /* SYNC */
2612         RCAR_GP_PIN(5, 24),
2613 };
2614 static const unsigned int msiof1_sync_f_mux[] = {
2615         MSIOF1_SYNC_F_MARK,
2616 };
2617 static const unsigned int msiof1_ss1_f_pins[] = {
2618         /* SS1 */
2619         RCAR_GP_PIN(6, 1),
2620 };
2621 static const unsigned int msiof1_ss1_f_mux[] = {
2622         MSIOF1_SS1_F_MARK,
2623 };
2624 static const unsigned int msiof1_ss2_f_pins[] = {
2625         /* SS2 */
2626         RCAR_GP_PIN(6, 2),
2627 };
2628 static const unsigned int msiof1_ss2_f_mux[] = {
2629         MSIOF1_SS2_F_MARK,
2630 };
2631 static const unsigned int msiof1_txd_f_pins[] = {
2632         /* TXD */
2633         RCAR_GP_PIN(6, 0),
2634 };
2635 static const unsigned int msiof1_txd_f_mux[] = {
2636         MSIOF1_TXD_F_MARK,
2637 };
2638 static const unsigned int msiof1_rxd_f_pins[] = {
2639         /* RXD */
2640         RCAR_GP_PIN(5, 25),
2641 };
2642 static const unsigned int msiof1_rxd_f_mux[] = {
2643         MSIOF1_RXD_F_MARK,
2644 };
2645 static const unsigned int msiof1_clk_g_pins[] = {
2646         /* SCK */
2647         RCAR_GP_PIN(3, 6),
2648 };
2649 static const unsigned int msiof1_clk_g_mux[] = {
2650         MSIOF1_SCK_G_MARK,
2651 };
2652 static const unsigned int msiof1_sync_g_pins[] = {
2653         /* SYNC */
2654         RCAR_GP_PIN(3, 7),
2655 };
2656 static const unsigned int msiof1_sync_g_mux[] = {
2657         MSIOF1_SYNC_G_MARK,
2658 };
2659 static const unsigned int msiof1_ss1_g_pins[] = {
2660         /* SS1 */
2661         RCAR_GP_PIN(3, 10),
2662 };
2663 static const unsigned int msiof1_ss1_g_mux[] = {
2664         MSIOF1_SS1_G_MARK,
2665 };
2666 static const unsigned int msiof1_ss2_g_pins[] = {
2667         /* SS2 */
2668         RCAR_GP_PIN(3, 11),
2669 };
2670 static const unsigned int msiof1_ss2_g_mux[] = {
2671         MSIOF1_SS2_G_MARK,
2672 };
2673 static const unsigned int msiof1_txd_g_pins[] = {
2674         /* TXD */
2675         RCAR_GP_PIN(3, 9),
2676 };
2677 static const unsigned int msiof1_txd_g_mux[] = {
2678         MSIOF1_TXD_G_MARK,
2679 };
2680 static const unsigned int msiof1_rxd_g_pins[] = {
2681         /* RXD */
2682         RCAR_GP_PIN(3, 8),
2683 };
2684 static const unsigned int msiof1_rxd_g_mux[] = {
2685         MSIOF1_RXD_G_MARK,
2686 };
2687 /* - MSIOF2 ----------------------------------------------------------------- */
2688 static const unsigned int msiof2_clk_a_pins[] = {
2689         /* SCK */
2690         RCAR_GP_PIN(1, 9),
2691 };
2692 static const unsigned int msiof2_clk_a_mux[] = {
2693         MSIOF2_SCK_A_MARK,
2694 };
2695 static const unsigned int msiof2_sync_a_pins[] = {
2696         /* SYNC */
2697         RCAR_GP_PIN(1, 8),
2698 };
2699 static const unsigned int msiof2_sync_a_mux[] = {
2700         MSIOF2_SYNC_A_MARK,
2701 };
2702 static const unsigned int msiof2_ss1_a_pins[] = {
2703         /* SS1 */
2704         RCAR_GP_PIN(1, 6),
2705 };
2706 static const unsigned int msiof2_ss1_a_mux[] = {
2707         MSIOF2_SS1_A_MARK,
2708 };
2709 static const unsigned int msiof2_ss2_a_pins[] = {
2710         /* SS2 */
2711         RCAR_GP_PIN(1, 7),
2712 };
2713 static const unsigned int msiof2_ss2_a_mux[] = {
2714         MSIOF2_SS2_A_MARK,
2715 };
2716 static const unsigned int msiof2_txd_a_pins[] = {
2717         /* TXD */
2718         RCAR_GP_PIN(1, 11),
2719 };
2720 static const unsigned int msiof2_txd_a_mux[] = {
2721         MSIOF2_TXD_A_MARK,
2722 };
2723 static const unsigned int msiof2_rxd_a_pins[] = {
2724         /* RXD */
2725         RCAR_GP_PIN(1, 10),
2726 };
2727 static const unsigned int msiof2_rxd_a_mux[] = {
2728         MSIOF2_RXD_A_MARK,
2729 };
2730 static const unsigned int msiof2_clk_b_pins[] = {
2731         /* SCK */
2732         RCAR_GP_PIN(0, 4),
2733 };
2734 static const unsigned int msiof2_clk_b_mux[] = {
2735         MSIOF2_SCK_B_MARK,
2736 };
2737 static const unsigned int msiof2_sync_b_pins[] = {
2738         /* SYNC */
2739         RCAR_GP_PIN(0, 5),
2740 };
2741 static const unsigned int msiof2_sync_b_mux[] = {
2742         MSIOF2_SYNC_B_MARK,
2743 };
2744 static const unsigned int msiof2_ss1_b_pins[] = {
2745         /* SS1 */
2746         RCAR_GP_PIN(0, 0),
2747 };
2748 static const unsigned int msiof2_ss1_b_mux[] = {
2749         MSIOF2_SS1_B_MARK,
2750 };
2751 static const unsigned int msiof2_ss2_b_pins[] = {
2752         /* SS2 */
2753         RCAR_GP_PIN(0, 1),
2754 };
2755 static const unsigned int msiof2_ss2_b_mux[] = {
2756         MSIOF2_SS2_B_MARK,
2757 };
2758 static const unsigned int msiof2_txd_b_pins[] = {
2759         /* TXD */
2760         RCAR_GP_PIN(0, 7),
2761 };
2762 static const unsigned int msiof2_txd_b_mux[] = {
2763         MSIOF2_TXD_B_MARK,
2764 };
2765 static const unsigned int msiof2_rxd_b_pins[] = {
2766         /* RXD */
2767         RCAR_GP_PIN(0, 6),
2768 };
2769 static const unsigned int msiof2_rxd_b_mux[] = {
2770         MSIOF2_RXD_B_MARK,
2771 };
2772 static const unsigned int msiof2_clk_c_pins[] = {
2773         /* SCK */
2774         RCAR_GP_PIN(2, 12),
2775 };
2776 static const unsigned int msiof2_clk_c_mux[] = {
2777         MSIOF2_SCK_C_MARK,
2778 };
2779 static const unsigned int msiof2_sync_c_pins[] = {
2780         /* SYNC */
2781         RCAR_GP_PIN(2, 11),
2782 };
2783 static const unsigned int msiof2_sync_c_mux[] = {
2784         MSIOF2_SYNC_C_MARK,
2785 };
2786 static const unsigned int msiof2_ss1_c_pins[] = {
2787         /* SS1 */
2788         RCAR_GP_PIN(2, 10),
2789 };
2790 static const unsigned int msiof2_ss1_c_mux[] = {
2791         MSIOF2_SS1_C_MARK,
2792 };
2793 static const unsigned int msiof2_ss2_c_pins[] = {
2794         /* SS2 */
2795         RCAR_GP_PIN(2, 9),
2796 };
2797 static const unsigned int msiof2_ss2_c_mux[] = {
2798         MSIOF2_SS2_C_MARK,
2799 };
2800 static const unsigned int msiof2_txd_c_pins[] = {
2801         /* TXD */
2802         RCAR_GP_PIN(2, 14),
2803 };
2804 static const unsigned int msiof2_txd_c_mux[] = {
2805         MSIOF2_TXD_C_MARK,
2806 };
2807 static const unsigned int msiof2_rxd_c_pins[] = {
2808         /* RXD */
2809         RCAR_GP_PIN(2, 13),
2810 };
2811 static const unsigned int msiof2_rxd_c_mux[] = {
2812         MSIOF2_RXD_C_MARK,
2813 };
2814 static const unsigned int msiof2_clk_d_pins[] = {
2815         /* SCK */
2816         RCAR_GP_PIN(0, 8),
2817 };
2818 static const unsigned int msiof2_clk_d_mux[] = {
2819         MSIOF2_SCK_D_MARK,
2820 };
2821 static const unsigned int msiof2_sync_d_pins[] = {
2822         /* SYNC */
2823         RCAR_GP_PIN(0, 9),
2824 };
2825 static const unsigned int msiof2_sync_d_mux[] = {
2826         MSIOF2_SYNC_D_MARK,
2827 };
2828 static const unsigned int msiof2_ss1_d_pins[] = {
2829         /* SS1 */
2830         RCAR_GP_PIN(0, 12),
2831 };
2832 static const unsigned int msiof2_ss1_d_mux[] = {
2833         MSIOF2_SS1_D_MARK,
2834 };
2835 static const unsigned int msiof2_ss2_d_pins[] = {
2836         /* SS2 */
2837         RCAR_GP_PIN(0, 13),
2838 };
2839 static const unsigned int msiof2_ss2_d_mux[] = {
2840         MSIOF2_SS2_D_MARK,
2841 };
2842 static const unsigned int msiof2_txd_d_pins[] = {
2843         /* TXD */
2844         RCAR_GP_PIN(0, 11),
2845 };
2846 static const unsigned int msiof2_txd_d_mux[] = {
2847         MSIOF2_TXD_D_MARK,
2848 };
2849 static const unsigned int msiof2_rxd_d_pins[] = {
2850         /* RXD */
2851         RCAR_GP_PIN(0, 10),
2852 };
2853 static const unsigned int msiof2_rxd_d_mux[] = {
2854         MSIOF2_RXD_D_MARK,
2855 };
2856 /* - MSIOF3 ----------------------------------------------------------------- */
2857 static const unsigned int msiof3_clk_a_pins[] = {
2858         /* SCK */
2859         RCAR_GP_PIN(0, 0),
2860 };
2861 static const unsigned int msiof3_clk_a_mux[] = {
2862         MSIOF3_SCK_A_MARK,
2863 };
2864 static const unsigned int msiof3_sync_a_pins[] = {
2865         /* SYNC */
2866         RCAR_GP_PIN(0, 1),
2867 };
2868 static const unsigned int msiof3_sync_a_mux[] = {
2869         MSIOF3_SYNC_A_MARK,
2870 };
2871 static const unsigned int msiof3_ss1_a_pins[] = {
2872         /* SS1 */
2873         RCAR_GP_PIN(0, 14),
2874 };
2875 static const unsigned int msiof3_ss1_a_mux[] = {
2876         MSIOF3_SS1_A_MARK,
2877 };
2878 static const unsigned int msiof3_ss2_a_pins[] = {
2879         /* SS2 */
2880         RCAR_GP_PIN(0, 15),
2881 };
2882 static const unsigned int msiof3_ss2_a_mux[] = {
2883         MSIOF3_SS2_A_MARK,
2884 };
2885 static const unsigned int msiof3_txd_a_pins[] = {
2886         /* TXD */
2887         RCAR_GP_PIN(0, 3),
2888 };
2889 static const unsigned int msiof3_txd_a_mux[] = {
2890         MSIOF3_TXD_A_MARK,
2891 };
2892 static const unsigned int msiof3_rxd_a_pins[] = {
2893         /* RXD */
2894         RCAR_GP_PIN(0, 2),
2895 };
2896 static const unsigned int msiof3_rxd_a_mux[] = {
2897         MSIOF3_RXD_A_MARK,
2898 };
2899 static const unsigned int msiof3_clk_b_pins[] = {
2900         /* SCK */
2901         RCAR_GP_PIN(1, 2),
2902 };
2903 static const unsigned int msiof3_clk_b_mux[] = {
2904         MSIOF3_SCK_B_MARK,
2905 };
2906 static const unsigned int msiof3_sync_b_pins[] = {
2907         /* SYNC */
2908         RCAR_GP_PIN(1, 0),
2909 };
2910 static const unsigned int msiof3_sync_b_mux[] = {
2911         MSIOF3_SYNC_B_MARK,
2912 };
2913 static const unsigned int msiof3_ss1_b_pins[] = {
2914         /* SS1 */
2915         RCAR_GP_PIN(1, 4),
2916 };
2917 static const unsigned int msiof3_ss1_b_mux[] = {
2918         MSIOF3_SS1_B_MARK,
2919 };
2920 static const unsigned int msiof3_ss2_b_pins[] = {
2921         /* SS2 */
2922         RCAR_GP_PIN(1, 5),
2923 };
2924 static const unsigned int msiof3_ss2_b_mux[] = {
2925         MSIOF3_SS2_B_MARK,
2926 };
2927 static const unsigned int msiof3_txd_b_pins[] = {
2928         /* TXD */
2929         RCAR_GP_PIN(1, 1),
2930 };
2931 static const unsigned int msiof3_txd_b_mux[] = {
2932         MSIOF3_TXD_B_MARK,
2933 };
2934 static const unsigned int msiof3_rxd_b_pins[] = {
2935         /* RXD */
2936         RCAR_GP_PIN(1, 3),
2937 };
2938 static const unsigned int msiof3_rxd_b_mux[] = {
2939         MSIOF3_RXD_B_MARK,
2940 };
2941 static const unsigned int msiof3_clk_c_pins[] = {
2942         /* SCK */
2943         RCAR_GP_PIN(1, 12),
2944 };
2945 static const unsigned int msiof3_clk_c_mux[] = {
2946         MSIOF3_SCK_C_MARK,
2947 };
2948 static const unsigned int msiof3_sync_c_pins[] = {
2949         /* SYNC */
2950         RCAR_GP_PIN(1, 13),
2951 };
2952 static const unsigned int msiof3_sync_c_mux[] = {
2953         MSIOF3_SYNC_C_MARK,
2954 };
2955 static const unsigned int msiof3_txd_c_pins[] = {
2956         /* TXD */
2957         RCAR_GP_PIN(1, 15),
2958 };
2959 static const unsigned int msiof3_txd_c_mux[] = {
2960         MSIOF3_TXD_C_MARK,
2961 };
2962 static const unsigned int msiof3_rxd_c_pins[] = {
2963         /* RXD */
2964         RCAR_GP_PIN(1, 14),
2965 };
2966 static const unsigned int msiof3_rxd_c_mux[] = {
2967         MSIOF3_RXD_C_MARK,
2968 };
2969 static const unsigned int msiof3_clk_d_pins[] = {
2970         /* SCK */
2971         RCAR_GP_PIN(1, 22),
2972 };
2973 static const unsigned int msiof3_clk_d_mux[] = {
2974         MSIOF3_SCK_D_MARK,
2975 };
2976 static const unsigned int msiof3_sync_d_pins[] = {
2977         /* SYNC */
2978         RCAR_GP_PIN(1, 23),
2979 };
2980 static const unsigned int msiof3_sync_d_mux[] = {
2981         MSIOF3_SYNC_D_MARK,
2982 };
2983 static const unsigned int msiof3_ss1_d_pins[] = {
2984         /* SS1 */
2985         RCAR_GP_PIN(1, 26),
2986 };
2987 static const unsigned int msiof3_ss1_d_mux[] = {
2988         MSIOF3_SS1_D_MARK,
2989 };
2990 static const unsigned int msiof3_txd_d_pins[] = {
2991         /* TXD */
2992         RCAR_GP_PIN(1, 25),
2993 };
2994 static const unsigned int msiof3_txd_d_mux[] = {
2995         MSIOF3_TXD_D_MARK,
2996 };
2997 static const unsigned int msiof3_rxd_d_pins[] = {
2998         /* RXD */
2999         RCAR_GP_PIN(1, 24),
3000 };
3001 static const unsigned int msiof3_rxd_d_mux[] = {
3002         MSIOF3_RXD_D_MARK,
3003 };
3004
3005 /* - PWM0 --------------------------------------------------------------------*/
3006 static const unsigned int pwm0_pins[] = {
3007         /* PWM */
3008         RCAR_GP_PIN(2, 6),
3009 };
3010 static const unsigned int pwm0_mux[] = {
3011         PWM0_MARK,
3012 };
3013 /* - PWM1 --------------------------------------------------------------------*/
3014 static const unsigned int pwm1_a_pins[] = {
3015         /* PWM */
3016         RCAR_GP_PIN(2, 7),
3017 };
3018 static const unsigned int pwm1_a_mux[] = {
3019         PWM1_A_MARK,
3020 };
3021 static const unsigned int pwm1_b_pins[] = {
3022         /* PWM */
3023         RCAR_GP_PIN(1, 8),
3024 };
3025 static const unsigned int pwm1_b_mux[] = {
3026         PWM1_B_MARK,
3027 };
3028 /* - PWM2 --------------------------------------------------------------------*/
3029 static const unsigned int pwm2_a_pins[] = {
3030         /* PWM */
3031         RCAR_GP_PIN(2, 8),
3032 };
3033 static const unsigned int pwm2_a_mux[] = {
3034         PWM2_A_MARK,
3035 };
3036 static const unsigned int pwm2_b_pins[] = {
3037         /* PWM */
3038         RCAR_GP_PIN(1, 11),
3039 };
3040 static const unsigned int pwm2_b_mux[] = {
3041         PWM2_B_MARK,
3042 };
3043 /* - PWM3 --------------------------------------------------------------------*/
3044 static const unsigned int pwm3_a_pins[] = {
3045         /* PWM */
3046         RCAR_GP_PIN(1, 0),
3047 };
3048 static const unsigned int pwm3_a_mux[] = {
3049         PWM3_A_MARK,
3050 };
3051 static const unsigned int pwm3_b_pins[] = {
3052         /* PWM */
3053         RCAR_GP_PIN(2, 2),
3054 };
3055 static const unsigned int pwm3_b_mux[] = {
3056         PWM3_B_MARK,
3057 };
3058 /* - PWM4 --------------------------------------------------------------------*/
3059 static const unsigned int pwm4_a_pins[] = {
3060         /* PWM */
3061         RCAR_GP_PIN(1, 1),
3062 };
3063 static const unsigned int pwm4_a_mux[] = {
3064         PWM4_A_MARK,
3065 };
3066 static const unsigned int pwm4_b_pins[] = {
3067         /* PWM */
3068         RCAR_GP_PIN(2, 3),
3069 };
3070 static const unsigned int pwm4_b_mux[] = {
3071         PWM4_B_MARK,
3072 };
3073 /* - PWM5 --------------------------------------------------------------------*/
3074 static const unsigned int pwm5_a_pins[] = {
3075         /* PWM */
3076         RCAR_GP_PIN(1, 2),
3077 };
3078 static const unsigned int pwm5_a_mux[] = {
3079         PWM5_A_MARK,
3080 };
3081 static const unsigned int pwm5_b_pins[] = {
3082         /* PWM */
3083         RCAR_GP_PIN(2, 4),
3084 };
3085 static const unsigned int pwm5_b_mux[] = {
3086         PWM5_B_MARK,
3087 };
3088 /* - PWM6 --------------------------------------------------------------------*/
3089 static const unsigned int pwm6_a_pins[] = {
3090         /* PWM */
3091         RCAR_GP_PIN(1, 3),
3092 };
3093 static const unsigned int pwm6_a_mux[] = {
3094         PWM6_A_MARK,
3095 };
3096 static const unsigned int pwm6_b_pins[] = {
3097         /* PWM */
3098         RCAR_GP_PIN(2, 5),
3099 };
3100 static const unsigned int pwm6_b_mux[] = {
3101         PWM6_B_MARK,
3102 };
3103
3104 /* - QSPI0 ------------------------------------------------------------------ */
3105 static const unsigned int qspi0_ctrl_pins[] = {
3106         /* QSPI0_SPCLK, QSPI0_SSL */
3107         PIN_NUMBER('W', 3), PIN_NUMBER('Y', 3),
3108 };
3109 static const unsigned int qspi0_ctrl_mux[] = {
3110         QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
3111 };
3112 static const unsigned int qspi0_data2_pins[] = {
3113         /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
3114         PIN_A_NUMBER('C', 5), PIN_A_NUMBER('B', 4),
3115 };
3116 static const unsigned int qspi0_data2_mux[] = {
3117         QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
3118 };
3119 static const unsigned int qspi0_data4_pins[] = {
3120         /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1, QSPI0_IO2, QSPI0_IO3 */
3121         PIN_A_NUMBER('C', 5), PIN_A_NUMBER('B', 4),
3122         PIN_NUMBER('Y', 6), PIN_A_NUMBER('B', 6),
3123 };
3124 static const unsigned int qspi0_data4_mux[] = {
3125         QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
3126         QSPI0_IO2_MARK, QSPI0_IO3_MARK,
3127 };
3128 /* - QSPI1 ------------------------------------------------------------------ */
3129 static const unsigned int qspi1_ctrl_pins[] = {
3130         /* QSPI1_SPCLK, QSPI1_SSL */
3131         PIN_NUMBER('V', 3), PIN_NUMBER('V', 5),
3132 };
3133 static const unsigned int qspi1_ctrl_mux[] = {
3134         QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
3135 };
3136 static const unsigned int qspi1_data2_pins[] = {
3137         /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
3138         PIN_A_NUMBER('C', 7), PIN_A_NUMBER('E', 5),
3139 };
3140 static const unsigned int qspi1_data2_mux[] = {
3141         QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
3142 };
3143 static const unsigned int qspi1_data4_pins[] = {
3144         /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1, QSPI1_IO2, QSPI1_IO3 */
3145         PIN_A_NUMBER('C', 7), PIN_A_NUMBER('E', 5),
3146         PIN_A_NUMBER('E', 4), PIN_A_NUMBER('C', 3),
3147 };
3148 static const unsigned int qspi1_data4_mux[] = {
3149         QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
3150         QSPI1_IO2_MARK, QSPI1_IO3_MARK,
3151 };
3152
3153 /* - SATA --------------------------------------------------------------------*/
3154 static const unsigned int sata0_devslp_a_pins[] = {
3155         /* DEVSLP */
3156         RCAR_GP_PIN(6, 16),
3157 };
3158 static const unsigned int sata0_devslp_a_mux[] = {
3159         SATA_DEVSLP_A_MARK,
3160 };
3161 static const unsigned int sata0_devslp_b_pins[] = {
3162         /* DEVSLP */
3163         RCAR_GP_PIN(4, 6),
3164 };
3165 static const unsigned int sata0_devslp_b_mux[] = {
3166         SATA_DEVSLP_B_MARK,
3167 };
3168
3169 /* - SCIF0 ------------------------------------------------------------------ */
3170 static const unsigned int scif0_data_pins[] = {
3171         /* RX, TX */
3172         RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3173 };
3174 static const unsigned int scif0_data_mux[] = {
3175         RX0_MARK, TX0_MARK,
3176 };
3177 static const unsigned int scif0_clk_pins[] = {
3178         /* SCK */
3179         RCAR_GP_PIN(5, 0),
3180 };
3181 static const unsigned int scif0_clk_mux[] = {
3182         SCK0_MARK,
3183 };
3184 static const unsigned int scif0_ctrl_pins[] = {
3185         /* RTS, CTS */
3186         RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
3187 };
3188 static const unsigned int scif0_ctrl_mux[] = {
3189         RTS0_N_TANS_MARK, CTS0_N_MARK,
3190 };
3191 /* - SCIF1 ------------------------------------------------------------------ */
3192 static const unsigned int scif1_data_a_pins[] = {
3193         /* RX, TX */
3194         RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3195 };
3196 static const unsigned int scif1_data_a_mux[] = {
3197         RX1_A_MARK, TX1_A_MARK,
3198 };
3199 static const unsigned int scif1_clk_pins[] = {
3200         /* SCK */
3201         RCAR_GP_PIN(6, 21),
3202 };
3203 static const unsigned int scif1_clk_mux[] = {
3204         SCK1_MARK,
3205 };
3206 static const unsigned int scif1_ctrl_pins[] = {
3207         /* RTS, CTS */
3208         RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
3209 };
3210 static const unsigned int scif1_ctrl_mux[] = {
3211         RTS1_N_TANS_MARK, CTS1_N_MARK,
3212 };
3213
3214 static const unsigned int scif1_data_b_pins[] = {
3215         /* RX, TX */
3216         RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
3217 };
3218 static const unsigned int scif1_data_b_mux[] = {
3219         RX1_B_MARK, TX1_B_MARK,
3220 };
3221 /* - SCIF2 ------------------------------------------------------------------ */
3222 static const unsigned int scif2_data_a_pins[] = {
3223         /* RX, TX */
3224         RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
3225 };
3226 static const unsigned int scif2_data_a_mux[] = {
3227         RX2_A_MARK, TX2_A_MARK,
3228 };
3229 static const unsigned int scif2_clk_pins[] = {
3230         /* SCK */
3231         RCAR_GP_PIN(5, 9),
3232 };
3233 static const unsigned int scif2_clk_mux[] = {
3234         SCK2_MARK,
3235 };
3236 static const unsigned int scif2_data_b_pins[] = {
3237         /* RX, TX */
3238         RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3239 };
3240 static const unsigned int scif2_data_b_mux[] = {
3241         RX2_B_MARK, TX2_B_MARK,
3242 };
3243 /* - SCIF3 ------------------------------------------------------------------ */
3244 static const unsigned int scif3_data_a_pins[] = {
3245         /* RX, TX */
3246         RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
3247 };
3248 static const unsigned int scif3_data_a_mux[] = {
3249         RX3_A_MARK, TX3_A_MARK,
3250 };
3251 static const unsigned int scif3_clk_pins[] = {
3252         /* SCK */
3253         RCAR_GP_PIN(1, 22),
3254 };
3255 static const unsigned int scif3_clk_mux[] = {
3256         SCK3_MARK,
3257 };
3258 static const unsigned int scif3_ctrl_pins[] = {
3259         /* RTS, CTS */
3260         RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
3261 };
3262 static const unsigned int scif3_ctrl_mux[] = {
3263         RTS3_N_TANS_MARK, CTS3_N_MARK,
3264 };
3265 static const unsigned int scif3_data_b_pins[] = {
3266         /* RX, TX */
3267         RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3268 };
3269 static const unsigned int scif3_data_b_mux[] = {
3270         RX3_B_MARK, TX3_B_MARK,
3271 };
3272 /* - SCIF4 ------------------------------------------------------------------ */
3273 static const unsigned int scif4_data_a_pins[] = {
3274         /* RX, TX */
3275         RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
3276 };
3277 static const unsigned int scif4_data_a_mux[] = {
3278         RX4_A_MARK, TX4_A_MARK,
3279 };
3280 static const unsigned int scif4_clk_a_pins[] = {
3281         /* SCK */
3282         RCAR_GP_PIN(2, 10),
3283 };
3284 static const unsigned int scif4_clk_a_mux[] = {
3285         SCK4_A_MARK,
3286 };
3287 static const unsigned int scif4_ctrl_a_pins[] = {
3288         /* RTS, CTS */
3289         RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
3290 };
3291 static const unsigned int scif4_ctrl_a_mux[] = {
3292         RTS4_N_TANS_A_MARK, CTS4_N_A_MARK,
3293 };
3294 static const unsigned int scif4_data_b_pins[] = {
3295         /* RX, TX */
3296         RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3297 };
3298 static const unsigned int scif4_data_b_mux[] = {
3299         RX4_B_MARK, TX4_B_MARK,
3300 };
3301 static const unsigned int scif4_clk_b_pins[] = {
3302         /* SCK */
3303         RCAR_GP_PIN(1, 5),
3304 };
3305 static const unsigned int scif4_clk_b_mux[] = {
3306         SCK4_B_MARK,
3307 };
3308 static const unsigned int scif4_ctrl_b_pins[] = {
3309         /* RTS, CTS */
3310         RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
3311 };
3312 static const unsigned int scif4_ctrl_b_mux[] = {
3313         RTS4_N_TANS_B_MARK, CTS4_N_B_MARK,
3314 };
3315 static const unsigned int scif4_data_c_pins[] = {
3316         /* RX, TX */
3317         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3318 };
3319 static const unsigned int scif4_data_c_mux[] = {
3320         RX4_C_MARK, TX4_C_MARK,
3321 };
3322 static const unsigned int scif4_clk_c_pins[] = {
3323         /* SCK */
3324         RCAR_GP_PIN(0, 8),
3325 };
3326 static const unsigned int scif4_clk_c_mux[] = {
3327         SCK4_C_MARK,
3328 };
3329 static const unsigned int scif4_ctrl_c_pins[] = {
3330         /* RTS, CTS */
3331         RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
3332 };
3333 static const unsigned int scif4_ctrl_c_mux[] = {
3334         RTS4_N_TANS_C_MARK, CTS4_N_C_MARK,
3335 };
3336 /* - SCIF5 ------------------------------------------------------------------ */
3337 static const unsigned int scif5_data_pins[] = {
3338         /* RX, TX */
3339         RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3340 };
3341 static const unsigned int scif5_data_mux[] = {
3342         RX5_MARK, TX5_MARK,
3343 };
3344 static const unsigned int scif5_clk_pins[] = {
3345         /* SCK */
3346         RCAR_GP_PIN(6, 21),
3347 };
3348 static const unsigned int scif5_clk_mux[] = {
3349         SCK5_MARK,
3350 };
3351
3352 /* - SCIF Clock ------------------------------------------------------------- */
3353 static const unsigned int scif_clk_a_pins[] = {
3354         /* SCIF_CLK */
3355         RCAR_GP_PIN(6, 23),
3356 };
3357 static const unsigned int scif_clk_a_mux[] = {
3358         SCIF_CLK_A_MARK,
3359 };
3360 static const unsigned int scif_clk_b_pins[] = {
3361         /* SCIF_CLK */
3362         RCAR_GP_PIN(5, 9),
3363 };
3364 static const unsigned int scif_clk_b_mux[] = {
3365         SCIF_CLK_B_MARK,
3366 };
3367
3368 /* - SDHI0 ------------------------------------------------------------------ */
3369 static const unsigned int sdhi0_data1_pins[] = {
3370         /* D0 */
3371         RCAR_GP_PIN(3, 2),
3372 };
3373 static const unsigned int sdhi0_data1_mux[] = {
3374         SD0_DAT0_MARK,
3375 };
3376 static const unsigned int sdhi0_data4_pins[] = {
3377         /* D[0:3] */
3378         RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3379         RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3380 };
3381 static const unsigned int sdhi0_data4_mux[] = {
3382         SD0_DAT0_MARK, SD0_DAT1_MARK,
3383         SD0_DAT2_MARK, SD0_DAT3_MARK,
3384 };
3385 static const unsigned int sdhi0_ctrl_pins[] = {
3386         /* CLK, CMD */
3387         RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3388 };
3389 static const unsigned int sdhi0_ctrl_mux[] = {
3390         SD0_CLK_MARK, SD0_CMD_MARK,
3391 };
3392 static const unsigned int sdhi0_cd_pins[] = {
3393         /* CD */
3394         RCAR_GP_PIN(3, 12),
3395 };
3396 static const unsigned int sdhi0_cd_mux[] = {
3397         SD0_CD_MARK,
3398 };
3399 static const unsigned int sdhi0_wp_pins[] = {
3400         /* WP */
3401         RCAR_GP_PIN(3, 13),
3402 };
3403 static const unsigned int sdhi0_wp_mux[] = {
3404         SD0_WP_MARK,
3405 };
3406 /* - SDHI1 ------------------------------------------------------------------ */
3407 static const unsigned int sdhi1_data1_pins[] = {
3408         /* D0 */
3409         RCAR_GP_PIN(3, 8),
3410 };
3411 static const unsigned int sdhi1_data1_mux[] = {
3412         SD1_DAT0_MARK,
3413 };
3414 static const unsigned int sdhi1_data4_pins[] = {
3415         /* D[0:3] */
3416         RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
3417         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3418 };
3419 static const unsigned int sdhi1_data4_mux[] = {
3420         SD1_DAT0_MARK, SD1_DAT1_MARK,
3421         SD1_DAT2_MARK, SD1_DAT3_MARK,
3422 };
3423 static const unsigned int sdhi1_ctrl_pins[] = {
3424         /* CLK, CMD */
3425         RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3426 };
3427 static const unsigned int sdhi1_ctrl_mux[] = {
3428         SD1_CLK_MARK, SD1_CMD_MARK,
3429 };
3430 static const unsigned int sdhi1_cd_pins[] = {
3431         /* CD */
3432         RCAR_GP_PIN(3, 14),
3433 };
3434 static const unsigned int sdhi1_cd_mux[] = {
3435         SD1_CD_MARK,
3436 };
3437 static const unsigned int sdhi1_wp_pins[] = {
3438         /* WP */
3439         RCAR_GP_PIN(3, 15),
3440 };
3441 static const unsigned int sdhi1_wp_mux[] = {
3442         SD1_WP_MARK,
3443 };
3444 /* - SDHI2 ------------------------------------------------------------------ */
3445 static const unsigned int sdhi2_data1_pins[] = {
3446         /* D0 */
3447         RCAR_GP_PIN(4, 2),
3448 };
3449 static const unsigned int sdhi2_data1_mux[] = {
3450         SD2_DAT0_MARK,
3451 };
3452 static const unsigned int sdhi2_data4_pins[] = {
3453         /* D[0:3] */
3454         RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3455         RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3456 };
3457 static const unsigned int sdhi2_data4_mux[] = {
3458         SD2_DAT0_MARK, SD2_DAT1_MARK,
3459         SD2_DAT2_MARK, SD2_DAT3_MARK,
3460 };
3461 static const unsigned int sdhi2_data8_pins[] = {
3462         /* D[0:7] */
3463         RCAR_GP_PIN(4, 2),  RCAR_GP_PIN(4, 3),
3464         RCAR_GP_PIN(4, 4),  RCAR_GP_PIN(4, 5),
3465         RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
3466         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3467 };
3468 static const unsigned int sdhi2_data8_mux[] = {
3469         SD2_DAT0_MARK, SD2_DAT1_MARK,
3470         SD2_DAT2_MARK, SD2_DAT3_MARK,
3471         SD2_DAT4_MARK, SD2_DAT5_MARK,
3472         SD2_DAT6_MARK, SD2_DAT7_MARK,
3473 };
3474 static const unsigned int sdhi2_ctrl_pins[] = {
3475         /* CLK, CMD */
3476         RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3477 };
3478 static const unsigned int sdhi2_ctrl_mux[] = {
3479         SD2_CLK_MARK, SD2_CMD_MARK,
3480 };
3481 static const unsigned int sdhi2_cd_a_pins[] = {
3482         /* CD */
3483         RCAR_GP_PIN(4, 13),
3484 };
3485 static const unsigned int sdhi2_cd_a_mux[] = {
3486         SD2_CD_A_MARK,
3487 };
3488 static const unsigned int sdhi2_cd_b_pins[] = {
3489         /* CD */
3490         RCAR_GP_PIN(5, 10),
3491 };
3492 static const unsigned int sdhi2_cd_b_mux[] = {
3493         SD2_CD_B_MARK,
3494 };
3495 static const unsigned int sdhi2_wp_a_pins[] = {
3496         /* WP */
3497         RCAR_GP_PIN(4, 14),
3498 };
3499 static const unsigned int sdhi2_wp_a_mux[] = {
3500         SD2_WP_A_MARK,
3501 };
3502 static const unsigned int sdhi2_wp_b_pins[] = {
3503         /* WP */
3504         RCAR_GP_PIN(5, 11),
3505 };
3506 static const unsigned int sdhi2_wp_b_mux[] = {
3507         SD2_WP_B_MARK,
3508 };
3509 static const unsigned int sdhi2_ds_pins[] = {
3510         /* DS */
3511         RCAR_GP_PIN(4, 6),
3512 };
3513 static const unsigned int sdhi2_ds_mux[] = {
3514         SD2_DS_MARK,
3515 };
3516 /* - SDHI3 ------------------------------------------------------------------ */
3517 static const unsigned int sdhi3_data1_pins[] = {
3518         /* D0 */
3519         RCAR_GP_PIN(4, 9),
3520 };
3521 static const unsigned int sdhi3_data1_mux[] = {
3522         SD3_DAT0_MARK,
3523 };
3524 static const unsigned int sdhi3_data4_pins[] = {
3525         /* D[0:3] */
3526         RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 10),
3527         RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3528 };
3529 static const unsigned int sdhi3_data4_mux[] = {
3530         SD3_DAT0_MARK, SD3_DAT1_MARK,
3531         SD3_DAT2_MARK, SD3_DAT3_MARK,
3532 };
3533 static const unsigned int sdhi3_data8_pins[] = {
3534         /* D[0:7] */
3535         RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 10),
3536         RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3537         RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3538         RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3539 };
3540 static const unsigned int sdhi3_data8_mux[] = {
3541         SD3_DAT0_MARK, SD3_DAT1_MARK,
3542         SD3_DAT2_MARK, SD3_DAT3_MARK,
3543         SD3_DAT4_MARK, SD3_DAT5_MARK,
3544         SD3_DAT6_MARK, SD3_DAT7_MARK,
3545 };
3546 static const unsigned int sdhi3_ctrl_pins[] = {
3547         /* CLK, CMD */
3548         RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3549 };
3550 static const unsigned int sdhi3_ctrl_mux[] = {
3551         SD3_CLK_MARK, SD3_CMD_MARK,
3552 };
3553 static const unsigned int sdhi3_cd_pins[] = {
3554         /* CD */
3555         RCAR_GP_PIN(4, 15),
3556 };
3557 static const unsigned int sdhi3_cd_mux[] = {
3558         SD3_CD_MARK,
3559 };
3560 static const unsigned int sdhi3_wp_pins[] = {
3561         /* WP */
3562         RCAR_GP_PIN(4, 16),
3563 };
3564 static const unsigned int sdhi3_wp_mux[] = {
3565         SD3_WP_MARK,
3566 };
3567 static const unsigned int sdhi3_ds_pins[] = {
3568         /* DS */
3569         RCAR_GP_PIN(4, 17),
3570 };
3571 static const unsigned int sdhi3_ds_mux[] = {
3572         SD3_DS_MARK,
3573 };
3574
3575 /* - SSI -------------------------------------------------------------------- */
3576 static const unsigned int ssi0_data_pins[] = {
3577         /* SDATA */
3578         RCAR_GP_PIN(6, 2),
3579 };
3580 static const unsigned int ssi0_data_mux[] = {
3581         SSI_SDATA0_MARK,
3582 };
3583 static const unsigned int ssi01239_ctrl_pins[] = {
3584         /* SCK, WS */
3585         RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3586 };
3587 static const unsigned int ssi01239_ctrl_mux[] = {
3588         SSI_SCK01239_MARK, SSI_WS01239_MARK,
3589 };
3590 static const unsigned int ssi1_data_a_pins[] = {
3591         /* SDATA */
3592         RCAR_GP_PIN(6, 3),
3593 };
3594 static const unsigned int ssi1_data_a_mux[] = {
3595         SSI_SDATA1_A_MARK,
3596 };
3597 static const unsigned int ssi1_data_b_pins[] = {
3598         /* SDATA */
3599         RCAR_GP_PIN(5, 12),
3600 };
3601 static const unsigned int ssi1_data_b_mux[] = {
3602         SSI_SDATA1_B_MARK,
3603 };
3604 static const unsigned int ssi1_ctrl_a_pins[] = {
3605         /* SCK, WS */
3606         RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3607 };
3608 static const unsigned int ssi1_ctrl_a_mux[] = {
3609         SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
3610 };
3611 static const unsigned int ssi1_ctrl_b_pins[] = {
3612         /* SCK, WS */
3613         RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
3614 };
3615 static const unsigned int ssi1_ctrl_b_mux[] = {
3616         SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3617 };
3618 static const unsigned int ssi2_data_a_pins[] = {
3619         /* SDATA */
3620         RCAR_GP_PIN(6, 4),
3621 };
3622 static const unsigned int ssi2_data_a_mux[] = {
3623         SSI_SDATA2_A_MARK,
3624 };
3625 static const unsigned int ssi2_data_b_pins[] = {
3626         /* SDATA */
3627         RCAR_GP_PIN(5, 13),
3628 };
3629 static const unsigned int ssi2_data_b_mux[] = {
3630         SSI_SDATA2_B_MARK,
3631 };
3632 static const unsigned int ssi2_ctrl_a_pins[] = {
3633         /* SCK, WS */
3634         RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3635 };
3636 static const unsigned int ssi2_ctrl_a_mux[] = {
3637         SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
3638 };
3639 static const unsigned int ssi2_ctrl_b_pins[] = {
3640         /* SCK, WS */
3641         RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3642 };
3643 static const unsigned int ssi2_ctrl_b_mux[] = {
3644         SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3645 };
3646 static const unsigned int ssi3_data_pins[] = {
3647         /* SDATA */
3648         RCAR_GP_PIN(6, 7),
3649 };
3650 static const unsigned int ssi3_data_mux[] = {
3651         SSI_SDATA3_MARK,
3652 };
3653 static const unsigned int ssi34_ctrl_pins[] = {
3654         /* SCK, WS */
3655         RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
3656 };
3657 static const unsigned int ssi34_ctrl_mux[] = {
3658         SSI_SCK34_MARK, SSI_WS34_MARK,
3659 };
3660 static const unsigned int ssi4_data_pins[] = {
3661         /* SDATA */
3662         RCAR_GP_PIN(6, 10),
3663 };
3664 static const unsigned int ssi4_data_mux[] = {
3665         SSI_SDATA4_MARK,
3666 };
3667 static const unsigned int ssi4_ctrl_pins[] = {
3668         /* SCK, WS */
3669         RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3670 };
3671 static const unsigned int ssi4_ctrl_mux[] = {
3672         SSI_SCK4_MARK, SSI_WS4_MARK,
3673 };
3674 static const unsigned int ssi5_data_pins[] = {
3675         /* SDATA */
3676         RCAR_GP_PIN(6, 13),
3677 };
3678 static const unsigned int ssi5_data_mux[] = {
3679         SSI_SDATA5_MARK,
3680 };
3681 static const unsigned int ssi5_ctrl_pins[] = {
3682         /* SCK, WS */
3683         RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3684 };
3685 static const unsigned int ssi5_ctrl_mux[] = {
3686         SSI_SCK5_MARK, SSI_WS5_MARK,
3687 };
3688 static const unsigned int ssi6_data_pins[] = {
3689         /* SDATA */
3690         RCAR_GP_PIN(6, 16),
3691 };
3692 static const unsigned int ssi6_data_mux[] = {
3693         SSI_SDATA6_MARK,
3694 };
3695 static const unsigned int ssi6_ctrl_pins[] = {
3696         /* SCK, WS */
3697         RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3698 };
3699 static const unsigned int ssi6_ctrl_mux[] = {
3700         SSI_SCK6_MARK, SSI_WS6_MARK,
3701 };
3702 static const unsigned int ssi7_data_pins[] = {
3703         /* SDATA */
3704         RCAR_GP_PIN(6, 19),
3705 };
3706 static const unsigned int ssi7_data_mux[] = {
3707         SSI_SDATA7_MARK,
3708 };
3709 static const unsigned int ssi78_ctrl_pins[] = {
3710         /* SCK, WS */
3711         RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
3712 };
3713 static const unsigned int ssi78_ctrl_mux[] = {
3714         SSI_SCK78_MARK, SSI_WS78_MARK,
3715 };
3716 static const unsigned int ssi8_data_pins[] = {
3717         /* SDATA */
3718         RCAR_GP_PIN(6, 20),
3719 };
3720 static const unsigned int ssi8_data_mux[] = {
3721         SSI_SDATA8_MARK,
3722 };
3723 static const unsigned int ssi9_data_a_pins[] = {
3724         /* SDATA */
3725         RCAR_GP_PIN(6, 21),
3726 };
3727 static const unsigned int ssi9_data_a_mux[] = {
3728         SSI_SDATA9_A_MARK,
3729 };
3730 static const unsigned int ssi9_data_b_pins[] = {
3731         /* SDATA */
3732         RCAR_GP_PIN(5, 14),
3733 };
3734 static const unsigned int ssi9_data_b_mux[] = {
3735         SSI_SDATA9_B_MARK,
3736 };
3737 static const unsigned int ssi9_ctrl_a_pins[] = {
3738         /* SCK, WS */
3739         RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3740 };
3741 static const unsigned int ssi9_ctrl_a_mux[] = {
3742         SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
3743 };
3744 static const unsigned int ssi9_ctrl_b_pins[] = {
3745         /* SCK, WS */
3746         RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3747 };
3748 static const unsigned int ssi9_ctrl_b_mux[] = {
3749         SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3750 };
3751
3752 /* - USB0 ------------------------------------------------------------------- */
3753 static const unsigned int usb0_pins[] = {
3754         /* PWEN, OVC */
3755         RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
3756 };
3757 static const unsigned int usb0_mux[] = {
3758         USB0_PWEN_MARK, USB0_OVC_MARK,
3759 };
3760 /* - USB1 ------------------------------------------------------------------- */
3761 static const unsigned int usb1_pins[] = {
3762         /* PWEN, OVC */
3763         RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3764 };
3765 static const unsigned int usb1_mux[] = {
3766         USB1_PWEN_MARK, USB1_OVC_MARK,
3767 };
3768 /* - USB2 ------------------------------------------------------------------- */
3769 static const unsigned int usb2_pins[] = {
3770         /* PWEN, OVC */
3771         RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3772 };
3773 static const unsigned int usb2_mux[] = {
3774         USB2_PWEN_MARK, USB2_OVC_MARK,
3775 };
3776
3777 static const struct sh_pfc_pin_group pinmux_groups[] = {
3778         SH_PFC_PIN_GROUP(audio_clk_a_a),
3779         SH_PFC_PIN_GROUP(audio_clk_a_b),
3780         SH_PFC_PIN_GROUP(audio_clk_a_c),
3781         SH_PFC_PIN_GROUP(audio_clk_b_a),
3782         SH_PFC_PIN_GROUP(audio_clk_b_b),
3783         SH_PFC_PIN_GROUP(audio_clk_c_a),
3784         SH_PFC_PIN_GROUP(audio_clk_c_b),
3785         SH_PFC_PIN_GROUP(audio_clkout_a),
3786         SH_PFC_PIN_GROUP(audio_clkout_b),
3787         SH_PFC_PIN_GROUP(audio_clkout_c),
3788         SH_PFC_PIN_GROUP(audio_clkout_d),
3789         SH_PFC_PIN_GROUP(audio_clkout1_a),
3790         SH_PFC_PIN_GROUP(audio_clkout1_b),
3791         SH_PFC_PIN_GROUP(audio_clkout2_a),
3792         SH_PFC_PIN_GROUP(audio_clkout2_b),
3793         SH_PFC_PIN_GROUP(audio_clkout3_a),
3794         SH_PFC_PIN_GROUP(audio_clkout3_b),
3795         SH_PFC_PIN_GROUP(avb_link),
3796         SH_PFC_PIN_GROUP(avb_magic),
3797         SH_PFC_PIN_GROUP(avb_phy_int),
3798         SH_PFC_PIN_GROUP(avb_mdc),
3799         SH_PFC_PIN_GROUP(avb_mii),
3800         SH_PFC_PIN_GROUP(avb_avtp_pps),
3801         SH_PFC_PIN_GROUP(avb_avtp_match_a),
3802         SH_PFC_PIN_GROUP(avb_avtp_capture_a),
3803         SH_PFC_PIN_GROUP(avb_avtp_match_b),
3804         SH_PFC_PIN_GROUP(avb_avtp_capture_b),
3805         SH_PFC_PIN_GROUP(can0_data_a),
3806         SH_PFC_PIN_GROUP(can0_data_b),
3807         SH_PFC_PIN_GROUP(can1_data),
3808         SH_PFC_PIN_GROUP(can_clk),
3809         SH_PFC_PIN_GROUP(canfd0_data_a),
3810         SH_PFC_PIN_GROUP(canfd0_data_b),
3811         SH_PFC_PIN_GROUP(canfd1_data),
3812         SH_PFC_PIN_GROUP(drif0_ctrl_a),
3813         SH_PFC_PIN_GROUP(drif0_data0_a),
3814         SH_PFC_PIN_GROUP(drif0_data1_a),
3815         SH_PFC_PIN_GROUP(drif0_ctrl_b),
3816         SH_PFC_PIN_GROUP(drif0_data0_b),
3817         SH_PFC_PIN_GROUP(drif0_data1_b),
3818         SH_PFC_PIN_GROUP(drif0_ctrl_c),
3819         SH_PFC_PIN_GROUP(drif0_data0_c),
3820         SH_PFC_PIN_GROUP(drif0_data1_c),
3821         SH_PFC_PIN_GROUP(drif1_ctrl_a),
3822         SH_PFC_PIN_GROUP(drif1_data0_a),
3823         SH_PFC_PIN_GROUP(drif1_data1_a),
3824         SH_PFC_PIN_GROUP(drif1_ctrl_b),
3825         SH_PFC_PIN_GROUP(drif1_data0_b),
3826         SH_PFC_PIN_GROUP(drif1_data1_b),
3827         SH_PFC_PIN_GROUP(drif1_ctrl_c),
3828         SH_PFC_PIN_GROUP(drif1_data0_c),
3829         SH_PFC_PIN_GROUP(drif1_data1_c),
3830         SH_PFC_PIN_GROUP(drif2_ctrl_a),
3831         SH_PFC_PIN_GROUP(drif2_data0_a),
3832         SH_PFC_PIN_GROUP(drif2_data1_a),
3833         SH_PFC_PIN_GROUP(drif2_ctrl_b),
3834         SH_PFC_PIN_GROUP(drif2_data0_b),
3835         SH_PFC_PIN_GROUP(drif2_data1_b),
3836         SH_PFC_PIN_GROUP(drif3_ctrl_a),
3837         SH_PFC_PIN_GROUP(drif3_data0_a),
3838         SH_PFC_PIN_GROUP(drif3_data1_a),
3839         SH_PFC_PIN_GROUP(drif3_ctrl_b),
3840         SH_PFC_PIN_GROUP(drif3_data0_b),
3841         SH_PFC_PIN_GROUP(drif3_data1_b),
3842         SH_PFC_PIN_GROUP(du_rgb666),
3843         SH_PFC_PIN_GROUP(du_rgb888),
3844         SH_PFC_PIN_GROUP(du_clk_out_0),
3845         SH_PFC_PIN_GROUP(du_clk_out_1),
3846         SH_PFC_PIN_GROUP(du_sync),
3847         SH_PFC_PIN_GROUP(du_oddf),
3848         SH_PFC_PIN_GROUP(du_cde),
3849         SH_PFC_PIN_GROUP(du_disp),
3850         SH_PFC_PIN_GROUP(hscif0_data),
3851         SH_PFC_PIN_GROUP(hscif0_clk),
3852         SH_PFC_PIN_GROUP(hscif0_ctrl),
3853         SH_PFC_PIN_GROUP(hscif1_data_a),
3854         SH_PFC_PIN_GROUP(hscif1_clk_a),
3855         SH_PFC_PIN_GROUP(hscif1_ctrl_a),
3856         SH_PFC_PIN_GROUP(hscif1_data_b),
3857         SH_PFC_PIN_GROUP(hscif1_clk_b),
3858         SH_PFC_PIN_GROUP(hscif1_ctrl_b),
3859         SH_PFC_PIN_GROUP(hscif2_data_a),
3860         SH_PFC_PIN_GROUP(hscif2_clk_a),
3861         SH_PFC_PIN_GROUP(hscif2_ctrl_a),
3862         SH_PFC_PIN_GROUP(hscif2_data_b),
3863         SH_PFC_PIN_GROUP(hscif2_clk_b),
3864         SH_PFC_PIN_GROUP(hscif2_ctrl_b),
3865         SH_PFC_PIN_GROUP(hscif3_data_a),
3866         SH_PFC_PIN_GROUP(hscif3_clk),
3867         SH_PFC_PIN_GROUP(hscif3_ctrl),
3868         SH_PFC_PIN_GROUP(hscif3_data_b),
3869         SH_PFC_PIN_GROUP(hscif3_data_c),
3870         SH_PFC_PIN_GROUP(hscif3_data_d),
3871         SH_PFC_PIN_GROUP(hscif4_data_a),
3872         SH_PFC_PIN_GROUP(hscif4_clk),
3873         SH_PFC_PIN_GROUP(hscif4_ctrl),
3874         SH_PFC_PIN_GROUP(hscif4_data_b),
3875         SH_PFC_PIN_GROUP(i2c1_a),
3876         SH_PFC_PIN_GROUP(i2c1_b),
3877         SH_PFC_PIN_GROUP(i2c2_a),
3878         SH_PFC_PIN_GROUP(i2c2_b),
3879         SH_PFC_PIN_GROUP(i2c6_a),
3880         SH_PFC_PIN_GROUP(i2c6_b),
3881         SH_PFC_PIN_GROUP(i2c6_c),
3882         SH_PFC_PIN_GROUP(intc_ex_irq0),
3883         SH_PFC_PIN_GROUP(intc_ex_irq1),
3884         SH_PFC_PIN_GROUP(intc_ex_irq2),
3885         SH_PFC_PIN_GROUP(intc_ex_irq3),
3886         SH_PFC_PIN_GROUP(intc_ex_irq4),
3887         SH_PFC_PIN_GROUP(intc_ex_irq5),
3888         SH_PFC_PIN_GROUP(msiof0_clk),
3889         SH_PFC_PIN_GROUP(msiof0_sync),
3890         SH_PFC_PIN_GROUP(msiof0_ss1),
3891         SH_PFC_PIN_GROUP(msiof0_ss2),
3892         SH_PFC_PIN_GROUP(msiof0_txd),
3893         SH_PFC_PIN_GROUP(msiof0_rxd),
3894         SH_PFC_PIN_GROUP(msiof1_clk_a),
3895         SH_PFC_PIN_GROUP(msiof1_sync_a),
3896         SH_PFC_PIN_GROUP(msiof1_ss1_a),
3897         SH_PFC_PIN_GROUP(msiof1_ss2_a),
3898         SH_PFC_PIN_GROUP(msiof1_txd_a),
3899         SH_PFC_PIN_GROUP(msiof1_rxd_a),
3900         SH_PFC_PIN_GROUP(msiof1_clk_b),
3901         SH_PFC_PIN_GROUP(msiof1_sync_b),
3902         SH_PFC_PIN_GROUP(msiof1_ss1_b),
3903         SH_PFC_PIN_GROUP(msiof1_ss2_b),
3904         SH_PFC_PIN_GROUP(msiof1_txd_b),
3905         SH_PFC_PIN_GROUP(msiof1_rxd_b),
3906         SH_PFC_PIN_GROUP(msiof1_clk_c),
3907         SH_PFC_PIN_GROUP(msiof1_sync_c),
3908         SH_PFC_PIN_GROUP(msiof1_ss1_c),
3909         SH_PFC_PIN_GROUP(msiof1_ss2_c),
3910         SH_PFC_PIN_GROUP(msiof1_txd_c),
3911         SH_PFC_PIN_GROUP(msiof1_rxd_c),
3912         SH_PFC_PIN_GROUP(msiof1_clk_d),
3913         SH_PFC_PIN_GROUP(msiof1_sync_d),
3914         SH_PFC_PIN_GROUP(msiof1_ss1_d),
3915         SH_PFC_PIN_GROUP(msiof1_ss2_d),
3916         SH_PFC_PIN_GROUP(msiof1_txd_d),
3917         SH_PFC_PIN_GROUP(msiof1_rxd_d),
3918         SH_PFC_PIN_GROUP(msiof1_clk_e),
3919         SH_PFC_PIN_GROUP(msiof1_sync_e),
3920         SH_PFC_PIN_GROUP(msiof1_ss1_e),
3921         SH_PFC_PIN_GROUP(msiof1_ss2_e),
3922         SH_PFC_PIN_GROUP(msiof1_txd_e),
3923         SH_PFC_PIN_GROUP(msiof1_rxd_e),
3924         SH_PFC_PIN_GROUP(msiof1_clk_f),
3925         SH_PFC_PIN_GROUP(msiof1_sync_f),
3926         SH_PFC_PIN_GROUP(msiof1_ss1_f),
3927         SH_PFC_PIN_GROUP(msiof1_ss2_f),
3928         SH_PFC_PIN_GROUP(msiof1_txd_f),
3929         SH_PFC_PIN_GROUP(msiof1_rxd_f),
3930         SH_PFC_PIN_GROUP(msiof1_clk_g),
3931         SH_PFC_PIN_GROUP(msiof1_sync_g),
3932         SH_PFC_PIN_GROUP(msiof1_ss1_g),
3933         SH_PFC_PIN_GROUP(msiof1_ss2_g),
3934         SH_PFC_PIN_GROUP(msiof1_txd_g),
3935         SH_PFC_PIN_GROUP(msiof1_rxd_g),
3936         SH_PFC_PIN_GROUP(msiof2_clk_a),
3937         SH_PFC_PIN_GROUP(msiof2_sync_a),
3938         SH_PFC_PIN_GROUP(msiof2_ss1_a),
3939         SH_PFC_PIN_GROUP(msiof2_ss2_a),
3940         SH_PFC_PIN_GROUP(msiof2_txd_a),
3941         SH_PFC_PIN_GROUP(msiof2_rxd_a),
3942         SH_PFC_PIN_GROUP(msiof2_clk_b),
3943         SH_PFC_PIN_GROUP(msiof2_sync_b),
3944         SH_PFC_PIN_GROUP(msiof2_ss1_b),
3945         SH_PFC_PIN_GROUP(msiof2_ss2_b),
3946         SH_PFC_PIN_GROUP(msiof2_txd_b),
3947         SH_PFC_PIN_GROUP(msiof2_rxd_b),
3948         SH_PFC_PIN_GROUP(msiof2_clk_c),
3949         SH_PFC_PIN_GROUP(msiof2_sync_c),
3950         SH_PFC_PIN_GROUP(msiof2_ss1_c),
3951         SH_PFC_PIN_GROUP(msiof2_ss2_c),
3952         SH_PFC_PIN_GROUP(msiof2_txd_c),
3953         SH_PFC_PIN_GROUP(msiof2_rxd_c),
3954         SH_PFC_PIN_GROUP(msiof2_clk_d),
3955         SH_PFC_PIN_GROUP(msiof2_sync_d),
3956         SH_PFC_PIN_GROUP(msiof2_ss1_d),
3957         SH_PFC_PIN_GROUP(msiof2_ss2_d),
3958         SH_PFC_PIN_GROUP(msiof2_txd_d),
3959         SH_PFC_PIN_GROUP(msiof2_rxd_d),
3960         SH_PFC_PIN_GROUP(msiof3_clk_a),
3961         SH_PFC_PIN_GROUP(msiof3_sync_a),
3962         SH_PFC_PIN_GROUP(msiof3_ss1_a),
3963         SH_PFC_PIN_GROUP(msiof3_ss2_a),
3964         SH_PFC_PIN_GROUP(msiof3_txd_a),
3965         SH_PFC_PIN_GROUP(msiof3_rxd_a),
3966         SH_PFC_PIN_GROUP(msiof3_clk_b),
3967         SH_PFC_PIN_GROUP(msiof3_sync_b),
3968         SH_PFC_PIN_GROUP(msiof3_ss1_b),
3969         SH_PFC_PIN_GROUP(msiof3_ss2_b),
3970         SH_PFC_PIN_GROUP(msiof3_txd_b),
3971         SH_PFC_PIN_GROUP(msiof3_rxd_b),
3972         SH_PFC_PIN_GROUP(msiof3_clk_c),
3973         SH_PFC_PIN_GROUP(msiof3_sync_c),
3974         SH_PFC_PIN_GROUP(msiof3_txd_c),
3975         SH_PFC_PIN_GROUP(msiof3_rxd_c),
3976         SH_PFC_PIN_GROUP(msiof3_clk_d),
3977         SH_PFC_PIN_GROUP(msiof3_sync_d),
3978         SH_PFC_PIN_GROUP(msiof3_ss1_d),
3979         SH_PFC_PIN_GROUP(msiof3_txd_d),
3980         SH_PFC_PIN_GROUP(msiof3_rxd_d),
3981         SH_PFC_PIN_GROUP(pwm0),
3982         SH_PFC_PIN_GROUP(pwm1_a),
3983         SH_PFC_PIN_GROUP(pwm1_b),
3984         SH_PFC_PIN_GROUP(pwm2_a),
3985         SH_PFC_PIN_GROUP(pwm2_b),
3986         SH_PFC_PIN_GROUP(pwm3_a),
3987         SH_PFC_PIN_GROUP(pwm3_b),
3988         SH_PFC_PIN_GROUP(pwm4_a),
3989         SH_PFC_PIN_GROUP(pwm4_b),
3990         SH_PFC_PIN_GROUP(pwm5_a),
3991         SH_PFC_PIN_GROUP(pwm5_b),
3992         SH_PFC_PIN_GROUP(pwm6_a),
3993         SH_PFC_PIN_GROUP(pwm6_b),
3994         SH_PFC_PIN_GROUP(qspi0_ctrl),
3995         SH_PFC_PIN_GROUP(qspi0_data2),
3996         SH_PFC_PIN_GROUP(qspi0_data4),
3997         SH_PFC_PIN_GROUP(qspi1_ctrl),
3998         SH_PFC_PIN_GROUP(qspi1_data2),
3999         SH_PFC_PIN_GROUP(qspi1_data4),
4000         SH_PFC_PIN_GROUP(sata0_devslp_a),
4001         SH_PFC_PIN_GROUP(sata0_devslp_b),
4002         SH_PFC_PIN_GROUP(scif0_data),
4003         SH_PFC_PIN_GROUP(scif0_clk),
4004         SH_PFC_PIN_GROUP(scif0_ctrl),
4005         SH_PFC_PIN_GROUP(scif1_data_a),
4006         SH_PFC_PIN_GROUP(scif1_clk),
4007         SH_PFC_PIN_GROUP(scif1_ctrl),
4008         SH_PFC_PIN_GROUP(scif1_data_b),
4009         SH_PFC_PIN_GROUP(scif2_data_a),
4010         SH_PFC_PIN_GROUP(scif2_clk),
4011         SH_PFC_PIN_GROUP(scif2_data_b),
4012         SH_PFC_PIN_GROUP(scif3_data_a),
4013         SH_PFC_PIN_GROUP(scif3_clk),
4014         SH_PFC_PIN_GROUP(scif3_ctrl),
4015         SH_PFC_PIN_GROUP(scif3_data_b),
4016         SH_PFC_PIN_GROUP(scif4_data_a),
4017         SH_PFC_PIN_GROUP(scif4_clk_a),
4018         SH_PFC_PIN_GROUP(scif4_ctrl_a),
4019         SH_PFC_PIN_GROUP(scif4_data_b),
4020         SH_PFC_PIN_GROUP(scif4_clk_b),
4021         SH_PFC_PIN_GROUP(scif4_ctrl_b),
4022         SH_PFC_PIN_GROUP(scif4_data_c),
4023         SH_PFC_PIN_GROUP(scif4_clk_c),
4024         SH_PFC_PIN_GROUP(scif4_ctrl_c),
4025         SH_PFC_PIN_GROUP(scif5_data),
4026         SH_PFC_PIN_GROUP(scif5_clk),
4027         SH_PFC_PIN_GROUP(scif_clk_a),
4028         SH_PFC_PIN_GROUP(scif_clk_b),
4029         SH_PFC_PIN_GROUP(sdhi0_data1),
4030         SH_PFC_PIN_GROUP(sdhi0_data4),
4031         SH_PFC_PIN_GROUP(sdhi0_ctrl),
4032         SH_PFC_PIN_GROUP(sdhi0_cd),
4033         SH_PFC_PIN_GROUP(sdhi0_wp),
4034         SH_PFC_PIN_GROUP(sdhi1_data1),
4035         SH_PFC_PIN_GROUP(sdhi1_data4),
4036         SH_PFC_PIN_GROUP(sdhi1_ctrl),
4037         SH_PFC_PIN_GROUP(sdhi1_cd),
4038         SH_PFC_PIN_GROUP(sdhi1_wp),
4039         SH_PFC_PIN_GROUP(sdhi2_data1),
4040         SH_PFC_PIN_GROUP(sdhi2_data4),
4041         SH_PFC_PIN_GROUP(sdhi2_data8),
4042         SH_PFC_PIN_GROUP(sdhi2_ctrl),
4043         SH_PFC_PIN_GROUP(sdhi2_cd_a),
4044         SH_PFC_PIN_GROUP(sdhi2_wp_a),
4045         SH_PFC_PIN_GROUP(sdhi2_cd_b),
4046         SH_PFC_PIN_GROUP(sdhi2_wp_b),
4047         SH_PFC_PIN_GROUP(sdhi2_ds),
4048         SH_PFC_PIN_GROUP(sdhi3_data1),
4049         SH_PFC_PIN_GROUP(sdhi3_data4),
4050         SH_PFC_PIN_GROUP(sdhi3_data8),
4051         SH_PFC_PIN_GROUP(sdhi3_ctrl),
4052         SH_PFC_PIN_GROUP(sdhi3_cd),
4053         SH_PFC_PIN_GROUP(sdhi3_wp),
4054         SH_PFC_PIN_GROUP(sdhi3_ds),
4055         SH_PFC_PIN_GROUP(ssi0_data),
4056         SH_PFC_PIN_GROUP(ssi01239_ctrl),
4057         SH_PFC_PIN_GROUP(ssi1_data_a),
4058         SH_PFC_PIN_GROUP(ssi1_data_b),
4059         SH_PFC_PIN_GROUP(ssi1_ctrl_a),
4060         SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4061         SH_PFC_PIN_GROUP(ssi2_data_a),
4062         SH_PFC_PIN_GROUP(ssi2_data_b),
4063         SH_PFC_PIN_GROUP(ssi2_ctrl_a),
4064         SH_PFC_PIN_GROUP(ssi2_ctrl_b),
4065         SH_PFC_PIN_GROUP(ssi3_data),
4066         SH_PFC_PIN_GROUP(ssi34_ctrl),
4067         SH_PFC_PIN_GROUP(ssi4_data),
4068         SH_PFC_PIN_GROUP(ssi4_ctrl),
4069         SH_PFC_PIN_GROUP(ssi5_data),
4070         SH_PFC_PIN_GROUP(ssi5_ctrl),
4071         SH_PFC_PIN_GROUP(ssi6_data),
4072         SH_PFC_PIN_GROUP(ssi6_ctrl),
4073         SH_PFC_PIN_GROUP(ssi7_data),
4074         SH_PFC_PIN_GROUP(ssi78_ctrl),
4075         SH_PFC_PIN_GROUP(ssi8_data),
4076         SH_PFC_PIN_GROUP(ssi9_data_a),
4077         SH_PFC_PIN_GROUP(ssi9_data_b),
4078         SH_PFC_PIN_GROUP(ssi9_ctrl_a),
4079         SH_PFC_PIN_GROUP(ssi9_ctrl_b),
4080         SH_PFC_PIN_GROUP(usb0),
4081         SH_PFC_PIN_GROUP(usb1),
4082         SH_PFC_PIN_GROUP(usb2),
4083 };
4084
4085 static const char * const audio_clk_groups[] = {
4086         "audio_clk_a_a",
4087         "audio_clk_a_b",
4088         "audio_clk_a_c",
4089         "audio_clk_b_a",
4090         "audio_clk_b_b",
4091         "audio_clk_c_a",
4092         "audio_clk_c_b",
4093         "audio_clkout_a",
4094         "audio_clkout_b",
4095         "audio_clkout_c",
4096         "audio_clkout_d",
4097         "audio_clkout1_a",
4098         "audio_clkout1_b",
4099         "audio_clkout2_a",
4100         "audio_clkout2_b",
4101         "audio_clkout3_a",
4102         "audio_clkout3_b",
4103 };
4104
4105 static const char * const avb_groups[] = {
4106         "avb_link",
4107         "avb_magic",
4108         "avb_phy_int",
4109         "avb_mdc",
4110         "avb_mii",
4111         "avb_avtp_pps",
4112         "avb_avtp_match_a",
4113         "avb_avtp_capture_a",
4114         "avb_avtp_match_b",
4115         "avb_avtp_capture_b",
4116 };
4117
4118 static const char * const can0_groups[] = {
4119         "can0_data_a",
4120         "can0_data_b",
4121 };
4122
4123 static const char * const can1_groups[] = {
4124         "can1_data",
4125 };
4126
4127 static const char * const can_clk_groups[] = {
4128         "can_clk",
4129 };
4130
4131 static const char * const canfd0_groups[] = {
4132         "canfd0_data_a",
4133         "canfd0_data_b",
4134 };
4135
4136 static const char * const canfd1_groups[] = {
4137         "canfd1_data",
4138 };
4139
4140 static const char * const drif0_groups[] = {
4141         "drif0_ctrl_a",
4142         "drif0_data0_a",
4143         "drif0_data1_a",
4144         "drif0_ctrl_b",
4145         "drif0_data0_b",
4146         "drif0_data1_b",
4147         "drif0_ctrl_c",
4148         "drif0_data0_c",
4149         "drif0_data1_c",
4150 };
4151
4152 static const char * const drif1_groups[] = {
4153         "drif1_ctrl_a",
4154         "drif1_data0_a",
4155         "drif1_data1_a",
4156         "drif1_ctrl_b",
4157         "drif1_data0_b",
4158         "drif1_data1_b",
4159         "drif1_ctrl_c",
4160         "drif1_data0_c",
4161         "drif1_data1_c",
4162 };
4163
4164 static const char * const drif2_groups[] = {
4165         "drif2_ctrl_a",
4166         "drif2_data0_a",
4167         "drif2_data1_a",
4168         "drif2_ctrl_b",
4169         "drif2_data0_b",
4170         "drif2_data1_b",
4171 };
4172
4173 static const char * const drif3_groups[] = {
4174         "drif3_ctrl_a",
4175         "drif3_data0_a",
4176         "drif3_data1_a",
4177         "drif3_ctrl_b",
4178         "drif3_data0_b",
4179         "drif3_data1_b",
4180 };
4181
4182 static const char * const du_groups[] = {
4183         "du_rgb666",
4184         "du_rgb888",
4185         "du_clk_out_0",
4186         "du_clk_out_1",
4187         "du_sync",
4188         "du_oddf",
4189         "du_cde",
4190         "du_disp",
4191 };
4192
4193 static const char * const hscif0_groups[] = {
4194         "hscif0_data",
4195         "hscif0_clk",
4196         "hscif0_ctrl",
4197 };
4198
4199 static const char * const hscif1_groups[] = {
4200         "hscif1_data_a",
4201         "hscif1_clk_a",
4202         "hscif1_ctrl_a",
4203         "hscif1_data_b",
4204         "hscif1_clk_b",
4205         "hscif1_ctrl_b",
4206 };
4207
4208 static const char * const hscif2_groups[] = {
4209         "hscif2_data_a",
4210         "hscif2_clk_a",
4211         "hscif2_ctrl_a",
4212         "hscif2_data_b",
4213         "hscif2_clk_b",
4214         "hscif2_ctrl_b",
4215 };
4216
4217 static const char * const hscif3_groups[] = {
4218         "hscif3_data_a",
4219         "hscif3_clk",
4220         "hscif3_ctrl",
4221         "hscif3_data_b",
4222         "hscif3_data_c",
4223         "hscif3_data_d",
4224 };
4225
4226 static const char * const hscif4_groups[] = {
4227         "hscif4_data_a",
4228         "hscif4_clk",
4229         "hscif4_ctrl",
4230         "hscif4_data_b",
4231 };
4232
4233 static const char * const i2c1_groups[] = {
4234         "i2c1_a",
4235         "i2c1_b",
4236 };
4237
4238 static const char * const i2c2_groups[] = {
4239         "i2c2_a",
4240         "i2c2_b",
4241 };
4242
4243 static const char * const i2c6_groups[] = {
4244         "i2c6_a",
4245         "i2c6_b",
4246         "i2c6_c",
4247 };
4248
4249 static const char * const intc_ex_groups[] = {
4250         "intc_ex_irq0",
4251         "intc_ex_irq1",
4252         "intc_ex_irq2",
4253         "intc_ex_irq3",
4254         "intc_ex_irq4",
4255         "intc_ex_irq5",
4256 };
4257
4258 static const char * const msiof0_groups[] = {
4259         "msiof0_clk",
4260         "msiof0_sync",
4261         "msiof0_ss1",
4262         "msiof0_ss2",
4263         "msiof0_txd",
4264         "msiof0_rxd",
4265 };
4266
4267 static const char * const msiof1_groups[] = {
4268         "msiof1_clk_a",
4269         "msiof1_sync_a",
4270         "msiof1_ss1_a",
4271         "msiof1_ss2_a",
4272         "msiof1_txd_a",
4273         "msiof1_rxd_a",
4274         "msiof1_clk_b",
4275         "msiof1_sync_b",
4276         "msiof1_ss1_b",
4277         "msiof1_ss2_b",
4278         "msiof1_txd_b",
4279         "msiof1_rxd_b",
4280         "msiof1_clk_c",
4281         "msiof1_sync_c",
4282         "msiof1_ss1_c",
4283         "msiof1_ss2_c",
4284         "msiof1_txd_c",
4285         "msiof1_rxd_c",
4286         "msiof1_clk_d",
4287         "msiof1_sync_d",
4288         "msiof1_ss1_d",
4289         "msiof1_ss2_d",
4290         "msiof1_txd_d",
4291         "msiof1_rxd_d",
4292         "msiof1_clk_e",
4293         "msiof1_sync_e",
4294         "msiof1_ss1_e",
4295         "msiof1_ss2_e",
4296         "msiof1_txd_e",
4297         "msiof1_rxd_e",
4298         "msiof1_clk_f",
4299         "msiof1_sync_f",
4300         "msiof1_ss1_f",
4301         "msiof1_ss2_f",
4302         "msiof1_txd_f",
4303         "msiof1_rxd_f",
4304         "msiof1_clk_g",
4305         "msiof1_sync_g",
4306         "msiof1_ss1_g",
4307         "msiof1_ss2_g",
4308         "msiof1_txd_g",
4309         "msiof1_rxd_g",
4310 };
4311
4312 static const char * const msiof2_groups[] = {
4313         "msiof2_clk_a",
4314         "msiof2_sync_a",
4315         "msiof2_ss1_a",
4316         "msiof2_ss2_a",
4317         "msiof2_txd_a",
4318         "msiof2_rxd_a",
4319         "msiof2_clk_b",
4320         "msiof2_sync_b",
4321         "msiof2_ss1_b",
4322         "msiof2_ss2_b",
4323         "msiof2_txd_b",
4324         "msiof2_rxd_b",
4325         "msiof2_clk_c",
4326         "msiof2_sync_c",
4327         "msiof2_ss1_c",
4328         "msiof2_ss2_c",
4329         "msiof2_txd_c",
4330         "msiof2_rxd_c",
4331         "msiof2_clk_d",
4332         "msiof2_sync_d",
4333         "msiof2_ss1_d",
4334         "msiof2_ss2_d",
4335         "msiof2_txd_d",
4336         "msiof2_rxd_d",
4337 };
4338
4339 static const char * const msiof3_groups[] = {
4340         "msiof3_clk_a",
4341         "msiof3_sync_a",
4342         "msiof3_ss1_a",
4343         "msiof3_ss2_a",
4344         "msiof3_txd_a",
4345         "msiof3_rxd_a",
4346         "msiof3_clk_b",
4347         "msiof3_sync_b",
4348         "msiof3_ss1_b",
4349         "msiof3_ss2_b",
4350         "msiof3_txd_b",
4351         "msiof3_rxd_b",
4352         "msiof3_clk_c",
4353         "msiof3_sync_c",
4354         "msiof3_txd_c",
4355         "msiof3_rxd_c",
4356         "msiof3_clk_d",
4357         "msiof3_sync_d",
4358         "msiof3_ss1_d",
4359         "msiof3_txd_d",
4360         "msiof3_rxd_d",
4361 };
4362
4363 static const char * const pwm0_groups[] = {
4364         "pwm0",
4365 };
4366
4367 static const char * const pwm1_groups[] = {
4368         "pwm1_a",
4369         "pwm1_b",
4370 };
4371
4372 static const char * const pwm2_groups[] = {
4373         "pwm2_a",
4374         "pwm2_b",
4375 };
4376
4377 static const char * const pwm3_groups[] = {
4378         "pwm3_a",
4379         "pwm3_b",
4380 };
4381
4382 static const char * const pwm4_groups[] = {
4383         "pwm4_a",
4384         "pwm4_b",
4385 };
4386
4387 static const char * const pwm5_groups[] = {
4388         "pwm5_a",
4389         "pwm5_b",
4390 };
4391
4392 static const char * const pwm6_groups[] = {
4393         "pwm6_a",
4394         "pwm6_b",
4395 };
4396
4397 static const char * const qspi0_groups[] = {
4398         "qspi0_ctrl",
4399         "qspi0_data2",
4400         "qspi0_data4",
4401 };
4402
4403 static const char * const qspi1_groups[] = {
4404         "qspi1_ctrl",
4405         "qspi1_data2",
4406         "qspi1_data4",
4407 };
4408
4409 static const char * const sata0_groups[] = {
4410         "sata0_devslp_a",
4411         "sata0_devslp_b",
4412 };
4413
4414 static const char * const scif0_groups[] = {
4415         "scif0_data",
4416         "scif0_clk",
4417         "scif0_ctrl",
4418 };
4419
4420 static const char * const scif1_groups[] = {
4421         "scif1_data_a",
4422         "scif1_clk",
4423         "scif1_ctrl",
4424         "scif1_data_b",
4425 };
4426
4427 static const char * const scif2_groups[] = {
4428         "scif2_data_a",
4429         "scif2_clk",
4430         "scif2_data_b",
4431 };
4432
4433 static const char * const scif3_groups[] = {
4434         "scif3_data_a",
4435         "scif3_clk",
4436         "scif3_ctrl",
4437         "scif3_data_b",
4438 };
4439
4440 static const char * const scif4_groups[] = {
4441         "scif4_data_a",
4442         "scif4_clk_a",
4443         "scif4_ctrl_a",
4444         "scif4_data_b",
4445         "scif4_clk_b",
4446         "scif4_ctrl_b",
4447         "scif4_data_c",
4448         "scif4_clk_c",
4449         "scif4_ctrl_c",
4450 };
4451
4452 static const char * const scif5_groups[] = {
4453         "scif5_data",
4454         "scif5_clk",
4455 };
4456
4457 static const char * const scif_clk_groups[] = {
4458         "scif_clk_a",
4459         "scif_clk_b",
4460 };
4461
4462 static const char * const sdhi0_groups[] = {
4463         "sdhi0_data1",
4464         "sdhi0_data4",
4465         "sdhi0_ctrl",
4466         "sdhi0_cd",
4467         "sdhi0_wp",
4468 };
4469
4470 static const char * const sdhi1_groups[] = {
4471         "sdhi1_data1",
4472         "sdhi1_data4",
4473         "sdhi1_ctrl",
4474         "sdhi1_cd",
4475         "sdhi1_wp",
4476 };
4477
4478 static const char * const sdhi2_groups[] = {
4479         "sdhi2_data1",
4480         "sdhi2_data4",
4481         "sdhi2_data8",
4482         "sdhi2_ctrl",
4483         "sdhi2_cd_a",
4484         "sdhi2_wp_a",
4485         "sdhi2_cd_b",
4486         "sdhi2_wp_b",
4487         "sdhi2_ds",
4488 };
4489
4490 static const char * const sdhi3_groups[] = {
4491         "sdhi3_data1",
4492         "sdhi3_data4",
4493         "sdhi3_data8",
4494         "sdhi3_ctrl",
4495         "sdhi3_cd",
4496         "sdhi3_wp",
4497         "sdhi3_ds",
4498 };
4499
4500 static const char * const ssi_groups[] = {
4501         "ssi0_data",
4502         "ssi01239_ctrl",
4503         "ssi1_data_a",
4504         "ssi1_data_b",
4505         "ssi1_ctrl_a",
4506         "ssi1_ctrl_b",
4507         "ssi2_data_a",
4508         "ssi2_data_b",
4509         "ssi2_ctrl_a",
4510         "ssi2_ctrl_b",
4511         "ssi3_data",
4512         "ssi34_ctrl",
4513         "ssi4_data",
4514         "ssi4_ctrl",
4515         "ssi5_data",
4516         "ssi5_ctrl",
4517         "ssi6_data",
4518         "ssi6_ctrl",
4519         "ssi7_data",
4520         "ssi78_ctrl",
4521         "ssi8_data",
4522         "ssi9_data_a",
4523         "ssi9_data_b",
4524         "ssi9_ctrl_a",
4525         "ssi9_ctrl_b",
4526 };
4527
4528 static const char * const usb0_groups[] = {
4529         "usb0",
4530 };
4531
4532 static const char * const usb1_groups[] = {
4533         "usb1",
4534 };
4535
4536 static const char * const usb2_groups[] = {
4537         "usb2",
4538 };
4539
4540 static const struct sh_pfc_function pinmux_functions[] = {
4541         SH_PFC_FUNCTION(audio_clk),
4542         SH_PFC_FUNCTION(avb),
4543         SH_PFC_FUNCTION(can0),
4544         SH_PFC_FUNCTION(can1),
4545         SH_PFC_FUNCTION(can_clk),
4546         SH_PFC_FUNCTION(canfd0),
4547         SH_PFC_FUNCTION(canfd1),
4548         SH_PFC_FUNCTION(drif0),
4549         SH_PFC_FUNCTION(drif1),
4550         SH_PFC_FUNCTION(drif2),
4551         SH_PFC_FUNCTION(drif3),
4552         SH_PFC_FUNCTION(du),
4553         SH_PFC_FUNCTION(hscif0),
4554         SH_PFC_FUNCTION(hscif1),
4555         SH_PFC_FUNCTION(hscif2),
4556         SH_PFC_FUNCTION(hscif3),
4557         SH_PFC_FUNCTION(hscif4),
4558         SH_PFC_FUNCTION(i2c1),
4559         SH_PFC_FUNCTION(i2c2),
4560         SH_PFC_FUNCTION(i2c6),
4561         SH_PFC_FUNCTION(intc_ex),
4562         SH_PFC_FUNCTION(msiof0),
4563         SH_PFC_FUNCTION(msiof1),
4564         SH_PFC_FUNCTION(msiof2),
4565         SH_PFC_FUNCTION(msiof3),
4566         SH_PFC_FUNCTION(pwm0),
4567         SH_PFC_FUNCTION(pwm1),
4568         SH_PFC_FUNCTION(pwm2),
4569         SH_PFC_FUNCTION(pwm3),
4570         SH_PFC_FUNCTION(pwm4),
4571         SH_PFC_FUNCTION(pwm5),
4572         SH_PFC_FUNCTION(pwm6),
4573         SH_PFC_FUNCTION(qspi0),
4574         SH_PFC_FUNCTION(qspi1),
4575         SH_PFC_FUNCTION(sata0),
4576         SH_PFC_FUNCTION(scif0),
4577         SH_PFC_FUNCTION(scif1),
4578         SH_PFC_FUNCTION(scif2),
4579         SH_PFC_FUNCTION(scif3),
4580         SH_PFC_FUNCTION(scif4),
4581         SH_PFC_FUNCTION(scif5),
4582         SH_PFC_FUNCTION(scif_clk),
4583         SH_PFC_FUNCTION(sdhi0),
4584         SH_PFC_FUNCTION(sdhi1),
4585         SH_PFC_FUNCTION(sdhi2),
4586         SH_PFC_FUNCTION(sdhi3),
4587         SH_PFC_FUNCTION(ssi),
4588         SH_PFC_FUNCTION(usb0),
4589         SH_PFC_FUNCTION(usb1),
4590         SH_PFC_FUNCTION(usb2),
4591 };
4592
4593 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4594 #define F_(x, y)        FN_##y
4595 #define FM(x)           FN_##x
4596         { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
4597                 0, 0,
4598                 0, 0,
4599                 0, 0,
4600                 0, 0,
4601                 0, 0,
4602                 0, 0,
4603                 0, 0,
4604                 0, 0,
4605                 0, 0,
4606                 0, 0,
4607                 0, 0,
4608                 0, 0,
4609                 0, 0,
4610                 0, 0,
4611                 0, 0,
4612                 0, 0,
4613                 GP_0_15_FN,     GPSR0_15,
4614                 GP_0_14_FN,     GPSR0_14,
4615                 GP_0_13_FN,     GPSR0_13,
4616                 GP_0_12_FN,     GPSR0_12,
4617                 GP_0_11_FN,     GPSR0_11,
4618                 GP_0_10_FN,     GPSR0_10,
4619                 GP_0_9_FN,      GPSR0_9,
4620                 GP_0_8_FN,      GPSR0_8,
4621                 GP_0_7_FN,      GPSR0_7,
4622                 GP_0_6_FN,      GPSR0_6,
4623                 GP_0_5_FN,      GPSR0_5,
4624                 GP_0_4_FN,      GPSR0_4,
4625                 GP_0_3_FN,      GPSR0_3,
4626                 GP_0_2_FN,      GPSR0_2,
4627                 GP_0_1_FN,      GPSR0_1,
4628                 GP_0_0_FN,      GPSR0_0, }
4629         },
4630         { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
4631                 0, 0,
4632                 0, 0,
4633                 0, 0,
4634                 0, 0,
4635                 GP_1_27_FN,     GPSR1_27,
4636                 GP_1_26_FN,     GPSR1_26,
4637                 GP_1_25_FN,     GPSR1_25,
4638                 GP_1_24_FN,     GPSR1_24,
4639                 GP_1_23_FN,     GPSR1_23,
4640                 GP_1_22_FN,     GPSR1_22,
4641                 GP_1_21_FN,     GPSR1_21,
4642                 GP_1_20_FN,     GPSR1_20,
4643                 GP_1_19_FN,     GPSR1_19,
4644                 GP_1_18_FN,     GPSR1_18,
4645                 GP_1_17_FN,     GPSR1_17,
4646                 GP_1_16_FN,     GPSR1_16,
4647                 GP_1_15_FN,     GPSR1_15,
4648                 GP_1_14_FN,     GPSR1_14,
4649                 GP_1_13_FN,     GPSR1_13,
4650                 GP_1_12_FN,     GPSR1_12,
4651                 GP_1_11_FN,     GPSR1_11,
4652                 GP_1_10_FN,     GPSR1_10,
4653                 GP_1_9_FN,      GPSR1_9,
4654                 GP_1_8_FN,      GPSR1_8,
4655                 GP_1_7_FN,      GPSR1_7,
4656                 GP_1_6_FN,      GPSR1_6,
4657                 GP_1_5_FN,      GPSR1_5,
4658                 GP_1_4_FN,      GPSR1_4,
4659                 GP_1_3_FN,      GPSR1_3,
4660                 GP_1_2_FN,      GPSR1_2,
4661                 GP_1_1_FN,      GPSR1_1,
4662                 GP_1_0_FN,      GPSR1_0, }
4663         },
4664         { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
4665                 0, 0,
4666                 0, 0,
4667                 0, 0,
4668                 0, 0,
4669                 0, 0,
4670                 0, 0,
4671                 0, 0,
4672                 0, 0,
4673                 0, 0,
4674                 0, 0,
4675                 0, 0,
4676                 0, 0,
4677                 0, 0,
4678                 0, 0,
4679                 0, 0,
4680                 0, 0,
4681                 0, 0,
4682                 GP_2_14_FN,     GPSR2_14,
4683                 GP_2_13_FN,     GPSR2_13,
4684                 GP_2_12_FN,     GPSR2_12,
4685                 GP_2_11_FN,     GPSR2_11,
4686                 GP_2_10_FN,     GPSR2_10,
4687                 GP_2_9_FN,      GPSR2_9,
4688                 GP_2_8_FN,      GPSR2_8,
4689                 GP_2_7_FN,      GPSR2_7,
4690                 GP_2_6_FN,      GPSR2_6,
4691                 GP_2_5_FN,      GPSR2_5,
4692                 GP_2_4_FN,      GPSR2_4,
4693                 GP_2_3_FN,      GPSR2_3,
4694                 GP_2_2_FN,      GPSR2_2,
4695                 GP_2_1_FN,      GPSR2_1,
4696                 GP_2_0_FN,      GPSR2_0, }
4697         },
4698         { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
4699                 0, 0,
4700                 0, 0,
4701                 0, 0,
4702                 0, 0,
4703                 0, 0,
4704                 0, 0,
4705                 0, 0,
4706                 0, 0,
4707                 0, 0,
4708                 0, 0,
4709                 0, 0,
4710                 0, 0,
4711                 0, 0,
4712                 0, 0,
4713                 0, 0,
4714                 0, 0,
4715                 GP_3_15_FN,     GPSR3_15,
4716                 GP_3_14_FN,     GPSR3_14,
4717                 GP_3_13_FN,     GPSR3_13,
4718                 GP_3_12_FN,     GPSR3_12,
4719                 GP_3_11_FN,     GPSR3_11,
4720                 GP_3_10_FN,     GPSR3_10,
4721                 GP_3_9_FN,      GPSR3_9,
4722                 GP_3_8_FN,      GPSR3_8,
4723                 GP_3_7_FN,      GPSR3_7,
4724                 GP_3_6_FN,      GPSR3_6,
4725                 GP_3_5_FN,      GPSR3_5,
4726                 GP_3_4_FN,      GPSR3_4,
4727                 GP_3_3_FN,      GPSR3_3,
4728                 GP_3_2_FN,      GPSR3_2,
4729                 GP_3_1_FN,      GPSR3_1,
4730                 GP_3_0_FN,      GPSR3_0, }
4731         },
4732         { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
4733                 0, 0,
4734                 0, 0,
4735                 0, 0,
4736                 0, 0,
4737                 0, 0,
4738                 0, 0,
4739                 0, 0,
4740                 0, 0,
4741                 0, 0,
4742                 0, 0,
4743                 0, 0,
4744                 0, 0,
4745                 0, 0,
4746                 0, 0,
4747                 GP_4_17_FN,     GPSR4_17,
4748                 GP_4_16_FN,     GPSR4_16,
4749                 GP_4_15_FN,     GPSR4_15,
4750                 GP_4_14_FN,     GPSR4_14,
4751                 GP_4_13_FN,     GPSR4_13,
4752                 GP_4_12_FN,     GPSR4_12,
4753                 GP_4_11_FN,     GPSR4_11,
4754                 GP_4_10_FN,     GPSR4_10,
4755                 GP_4_9_FN,      GPSR4_9,
4756                 GP_4_8_FN,      GPSR4_8,
4757                 GP_4_7_FN,      GPSR4_7,
4758                 GP_4_6_FN,      GPSR4_6,
4759                 GP_4_5_FN,      GPSR4_5,
4760                 GP_4_4_FN,      GPSR4_4,
4761                 GP_4_3_FN,      GPSR4_3,
4762                 GP_4_2_FN,      GPSR4_2,
4763                 GP_4_1_FN,      GPSR4_1,
4764                 GP_4_0_FN,      GPSR4_0, }
4765         },
4766         { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
4767                 0, 0,
4768                 0, 0,
4769                 0, 0,
4770                 0, 0,
4771                 0, 0,
4772                 0, 0,
4773                 GP_5_25_FN,     GPSR5_25,
4774                 GP_5_24_FN,     GPSR5_24,
4775                 GP_5_23_FN,     GPSR5_23,
4776                 GP_5_22_FN,     GPSR5_22,
4777                 GP_5_21_FN,     GPSR5_21,
4778                 GP_5_20_FN,     GPSR5_20,
4779                 GP_5_19_FN,     GPSR5_19,
4780                 GP_5_18_FN,     GPSR5_18,
4781                 GP_5_17_FN,     GPSR5_17,
4782                 GP_5_16_FN,     GPSR5_16,
4783                 GP_5_15_FN,     GPSR5_15,
4784                 GP_5_14_FN,     GPSR5_14,
4785                 GP_5_13_FN,     GPSR5_13,
4786                 GP_5_12_FN,     GPSR5_12,
4787                 GP_5_11_FN,     GPSR5_11,
4788                 GP_5_10_FN,     GPSR5_10,
4789                 GP_5_9_FN,      GPSR5_9,
4790                 GP_5_8_FN,      GPSR5_8,
4791                 GP_5_7_FN,      GPSR5_7,
4792                 GP_5_6_FN,      GPSR5_6,
4793                 GP_5_5_FN,      GPSR5_5,
4794                 GP_5_4_FN,      GPSR5_4,
4795                 GP_5_3_FN,      GPSR5_3,
4796                 GP_5_2_FN,      GPSR5_2,
4797                 GP_5_1_FN,      GPSR5_1,
4798                 GP_5_0_FN,      GPSR5_0, }
4799         },
4800         { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
4801                 GP_6_31_FN,     GPSR6_31,
4802                 GP_6_30_FN,     GPSR6_30,
4803                 GP_6_29_FN,     GPSR6_29,
4804                 GP_6_28_FN,     GPSR6_28,
4805                 GP_6_27_FN,     GPSR6_27,
4806                 GP_6_26_FN,     GPSR6_26,
4807                 GP_6_25_FN,     GPSR6_25,
4808                 GP_6_24_FN,     GPSR6_24,
4809                 GP_6_23_FN,     GPSR6_23,
4810                 GP_6_22_FN,     GPSR6_22,
4811                 GP_6_21_FN,     GPSR6_21,
4812                 GP_6_20_FN,     GPSR6_20,
4813                 GP_6_19_FN,     GPSR6_19,
4814                 GP_6_18_FN,     GPSR6_18,
4815                 GP_6_17_FN,     GPSR6_17,
4816                 GP_6_16_FN,     GPSR6_16,
4817                 GP_6_15_FN,     GPSR6_15,
4818                 GP_6_14_FN,     GPSR6_14,
4819                 GP_6_13_FN,     GPSR6_13,
4820                 GP_6_12_FN,     GPSR6_12,
4821                 GP_6_11_FN,     GPSR6_11,
4822                 GP_6_10_FN,     GPSR6_10,
4823                 GP_6_9_FN,      GPSR6_9,
4824                 GP_6_8_FN,      GPSR6_8,
4825                 GP_6_7_FN,      GPSR6_7,
4826                 GP_6_6_FN,      GPSR6_6,
4827                 GP_6_5_FN,      GPSR6_5,
4828                 GP_6_4_FN,      GPSR6_4,
4829                 GP_6_3_FN,      GPSR6_3,
4830                 GP_6_2_FN,      GPSR6_2,
4831                 GP_6_1_FN,      GPSR6_1,
4832                 GP_6_0_FN,      GPSR6_0, }
4833         },
4834         { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) {
4835                 0, 0,
4836                 0, 0,
4837                 0, 0,
4838                 0, 0,
4839                 0, 0,
4840                 0, 0,
4841                 0, 0,
4842                 0, 0,
4843                 0, 0,
4844                 0, 0,
4845                 0, 0,
4846                 0, 0,
4847                 0, 0,
4848                 0, 0,
4849                 0, 0,
4850                 0, 0,
4851                 0, 0,
4852                 0, 0,
4853                 0, 0,
4854                 0, 0,
4855                 0, 0,
4856                 0, 0,
4857                 0, 0,
4858                 0, 0,
4859                 0, 0,
4860                 0, 0,
4861                 0, 0,
4862                 0, 0,
4863                 GP_7_3_FN, GPSR7_3,
4864                 GP_7_2_FN, GPSR7_2,
4865                 GP_7_1_FN, GPSR7_1,
4866                 GP_7_0_FN, GPSR7_0, }
4867         },
4868 #undef F_
4869 #undef FM
4870
4871 #define F_(x, y)        x,
4872 #define FM(x)           FN_##x,
4873         { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
4874                 IP0_31_28
4875                 IP0_27_24
4876                 IP0_23_20
4877                 IP0_19_16
4878                 IP0_15_12
4879                 IP0_11_8
4880                 IP0_7_4
4881                 IP0_3_0 }
4882         },
4883         { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
4884                 IP1_31_28
4885                 IP1_27_24
4886                 IP1_23_20
4887                 IP1_19_16
4888                 IP1_15_12
4889                 IP1_11_8
4890                 IP1_7_4
4891                 IP1_3_0 }
4892         },
4893         { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
4894                 IP2_31_28
4895                 IP2_27_24
4896                 IP2_23_20
4897                 IP2_19_16
4898                 IP2_15_12
4899                 IP2_11_8
4900                 IP2_7_4
4901                 IP2_3_0 }
4902         },
4903         { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
4904                 IP3_31_28
4905                 IP3_27_24
4906                 IP3_23_20
4907                 IP3_19_16
4908                 IP3_15_12
4909                 IP3_11_8
4910                 IP3_7_4
4911                 IP3_3_0 }
4912         },
4913         { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
4914                 IP4_31_28
4915                 IP4_27_24
4916                 IP4_23_20
4917                 IP4_19_16
4918                 IP4_15_12
4919                 IP4_11_8
4920                 IP4_7_4
4921                 IP4_3_0 }
4922         },
4923         { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
4924                 IP5_31_28
4925                 IP5_27_24
4926                 IP5_23_20
4927                 IP5_19_16
4928                 IP5_15_12
4929                 IP5_11_8
4930                 IP5_7_4
4931                 IP5_3_0 }
4932         },
4933         { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
4934                 IP6_31_28
4935                 IP6_27_24
4936                 IP6_23_20
4937                 IP6_19_16
4938                 IP6_15_12
4939                 IP6_11_8
4940                 IP6_7_4
4941                 IP6_3_0 }
4942         },
4943         { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
4944                 IP7_31_28
4945                 IP7_27_24
4946                 IP7_23_20
4947                 IP7_19_16
4948                 IP7_15_12
4949                 IP7_11_8
4950                 IP7_7_4
4951                 IP7_3_0 }
4952         },
4953         { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
4954                 IP8_31_28
4955                 IP8_27_24
4956                 IP8_23_20
4957                 IP8_19_16
4958                 IP8_15_12
4959                 IP8_11_8
4960                 IP8_7_4
4961                 IP8_3_0 }
4962         },
4963         { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
4964                 IP9_31_28
4965                 IP9_27_24
4966                 IP9_23_20
4967                 IP9_19_16
4968                 IP9_15_12
4969                 IP9_11_8
4970                 IP9_7_4
4971                 IP9_3_0 }
4972         },
4973         { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
4974                 IP10_31_28
4975                 IP10_27_24
4976                 IP10_23_20
4977                 IP10_19_16
4978                 IP10_15_12
4979                 IP10_11_8
4980                 IP10_7_4
4981                 IP10_3_0 }
4982         },
4983         { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
4984                 IP11_31_28
4985                 IP11_27_24
4986                 IP11_23_20
4987                 IP11_19_16
4988                 IP11_15_12
4989                 IP11_11_8
4990                 IP11_7_4
4991                 IP11_3_0 }
4992         },
4993         { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
4994                 IP12_31_28
4995                 IP12_27_24
4996                 IP12_23_20
4997                 IP12_19_16
4998                 IP12_15_12
4999                 IP12_11_8
5000                 IP12_7_4
5001                 IP12_3_0 }
5002         },
5003         { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
5004                 IP13_31_28
5005                 IP13_27_24
5006                 IP13_23_20
5007                 IP13_19_16
5008                 IP13_15_12
5009                 IP13_11_8
5010                 IP13_7_4
5011                 IP13_3_0 }
5012         },
5013         { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) {
5014                 IP14_31_28
5015                 IP14_27_24
5016                 IP14_23_20
5017                 IP14_19_16
5018                 IP14_15_12
5019                 IP14_11_8
5020                 IP14_7_4
5021                 IP14_3_0 }
5022         },
5023         { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) {
5024                 IP15_31_28
5025                 IP15_27_24
5026                 IP15_23_20
5027                 IP15_19_16
5028                 IP15_15_12
5029                 IP15_11_8
5030                 IP15_7_4
5031                 IP15_3_0 }
5032         },
5033         { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) {
5034                 IP16_31_28
5035                 IP16_27_24
5036                 IP16_23_20
5037                 IP16_19_16
5038                 IP16_15_12
5039                 IP16_11_8
5040                 IP16_7_4
5041                 IP16_3_0 }
5042         },
5043         { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) {
5044                 /* IP17_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5045                 /* IP17_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5046                 /* IP17_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5047                 /* IP17_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5048                 /* IP17_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5049                 /* IP17_11_8  */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5050                 IP17_7_4
5051                 IP17_3_0 }
5052         },
5053 #undef F_
5054 #undef FM
5055
5056 #define F_(x, y)        x,
5057 #define FM(x)           FN_##x,
5058         { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
5059                              1, 2, 2, 3, 1, 1, 2, 1, 1, 1,
5060                              2, 1, 1, 1, 1, 1, 1, 1, 2, 2, 1, 2, 1) {
5061                 0, 0, /* RESERVED 31 */
5062                 MOD_SEL0_30_29
5063                 MOD_SEL0_28_27
5064                 MOD_SEL0_26_25_24
5065                 MOD_SEL0_23
5066                 MOD_SEL0_22
5067                 MOD_SEL0_21_20
5068                 MOD_SEL0_19
5069                 MOD_SEL0_18
5070                 MOD_SEL0_17
5071                 MOD_SEL0_16_15
5072                 MOD_SEL0_14
5073                 MOD_SEL0_13
5074                 MOD_SEL0_12
5075                 MOD_SEL0_11
5076                 MOD_SEL0_10
5077                 MOD_SEL0_9
5078                 MOD_SEL0_8
5079                 MOD_SEL0_7_6
5080                 MOD_SEL0_5_4
5081                 MOD_SEL0_3
5082                 MOD_SEL0_2_1
5083                 0, 0, /* RESERVED 0 */ }
5084         },
5085         { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
5086                              2, 3, 1, 2, 3, 1, 1, 2, 1,
5087                              2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {
5088                 MOD_SEL1_31_30
5089                 MOD_SEL1_29_28_27
5090                 MOD_SEL1_26
5091                 MOD_SEL1_25_24
5092                 MOD_SEL1_23_22_21
5093                 MOD_SEL1_20
5094                 MOD_SEL1_19
5095                 MOD_SEL1_18_17
5096                 MOD_SEL1_16
5097                 MOD_SEL1_15_14
5098                 MOD_SEL1_13
5099                 MOD_SEL1_12
5100                 MOD_SEL1_11
5101                 MOD_SEL1_10
5102                 MOD_SEL1_9
5103                 0, 0, 0, 0, /* RESERVED 8, 7 */
5104                 MOD_SEL1_6
5105                 MOD_SEL1_5
5106                 MOD_SEL1_4
5107                 MOD_SEL1_3
5108                 MOD_SEL1_2
5109                 MOD_SEL1_1
5110                 MOD_SEL1_0 }
5111         },
5112         { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
5113                              1, 1, 1, 1, 4, 4, 4,
5114                              4, 4, 4, 1, 2, 1) {
5115                 MOD_SEL2_31
5116                 MOD_SEL2_30
5117                 MOD_SEL2_29
5118                 /* RESERVED 28 */
5119                 0, 0,
5120                 /* RESERVED 27, 26, 25, 24 */
5121                 0, 0, 0, 0, 0, 0, 0, 0,
5122                 0, 0, 0, 0, 0, 0, 0, 0,
5123                 /* RESERVED 23, 22, 21, 20 */
5124                 0, 0, 0, 0, 0, 0, 0, 0,
5125                 0, 0, 0, 0, 0, 0, 0, 0,
5126                 /* RESERVED 19, 18, 17, 16 */
5127                 0, 0, 0, 0, 0, 0, 0, 0,
5128                 0, 0, 0, 0, 0, 0, 0, 0,
5129                 /* RESERVED 15, 14, 13, 12 */
5130                 0, 0, 0, 0, 0, 0, 0, 0,
5131                 0, 0, 0, 0, 0, 0, 0, 0,
5132                 /* RESERVED 11, 10, 9, 8 */
5133                 0, 0, 0, 0, 0, 0, 0, 0,
5134                 0, 0, 0, 0, 0, 0, 0, 0,
5135                 /* RESERVED 7, 6, 5, 4 */
5136                 0, 0, 0, 0, 0, 0, 0, 0,
5137                 0, 0, 0, 0, 0, 0, 0, 0,
5138                 /* RESERVED 3 */
5139                 0, 0,
5140                 /* RESERVED 2, 1 */
5141                 0, 0, 0, 0,
5142                 MOD_SEL2_0 }
5143         },
5144         { },
5145 };
5146
5147 static const struct pinmux_drive_reg pinmux_drive_regs[] = {
5148         { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
5149                 { PIN_NUMBER('W', 3),   28, 2 },        /* QSPI0_SPCLK */
5150                 { PIN_A_NUMBER('C', 5), 24, 2 },        /* QSPI0_MOSI_IO0 */
5151                 { PIN_A_NUMBER('B', 4), 20, 2 },        /* QSPI0_MISO_IO1 */
5152                 { PIN_NUMBER('Y', 6),   16, 2 },        /* QSPI0_IO2 */
5153                 { PIN_A_NUMBER('B', 6), 12, 2 },        /* QSPI0_IO3 */
5154                 { PIN_NUMBER('Y', 3),    8, 2 },        /* QSPI0_SSL */
5155                 { PIN_NUMBER('V', 3),    4, 2 },        /* QSPI1_SPCLK */
5156                 { PIN_A_NUMBER('C', 7),  0, 2 },        /* QSPI1_MOSI_IO0 */
5157         } },
5158         { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
5159                 { PIN_A_NUMBER('E', 5), 28, 2 },        /* QSPI1_MISO_IO1 */
5160                 { PIN_A_NUMBER('E', 4), 24, 2 },        /* QSPI1_IO2 */
5161                 { PIN_A_NUMBER('C', 3), 20, 2 },        /* QSPI1_IO3 */
5162                 { PIN_NUMBER('V', 5),   16, 2 },        /* QSPI1_SSL */
5163                 { PIN_NUMBER('Y', 7),   12, 2 },        /* RPC_INT# */
5164                 { PIN_NUMBER('V', 6),    8, 2 },        /* RPC_WP# */
5165                 { PIN_NUMBER('V', 7),    4, 2 },        /* RPC_RESET# */
5166                 { PIN_NUMBER('A', 16),   0, 3 },        /* AVB_RX_CTL */
5167         } },
5168         { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
5169                 { PIN_NUMBER('B', 19),  28, 3 },        /* AVB_RXC */
5170                 { PIN_NUMBER('A', 13),  24, 3 },        /* AVB_RD0 */
5171                 { PIN_NUMBER('B', 13),  20, 3 },        /* AVB_RD1 */
5172                 { PIN_NUMBER('A', 14),  16, 3 },        /* AVB_RD2 */
5173                 { PIN_NUMBER('B', 14),  12, 3 },        /* AVB_RD3 */
5174                 { PIN_NUMBER('A', 8),    8, 3 },        /* AVB_TX_CTL */
5175                 { PIN_NUMBER('A', 19),   4, 3 },        /* AVB_TXC */
5176                 { PIN_NUMBER('A', 18),   0, 3 },        /* AVB_TD0 */
5177         } },
5178         { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
5179                 { PIN_NUMBER('B', 18),  28, 3 },        /* AVB_TD1 */
5180                 { PIN_NUMBER('A', 17),  24, 3 },        /* AVB_TD2 */
5181                 { PIN_NUMBER('B', 17),  20, 3 },        /* AVB_TD3 */
5182                 { PIN_NUMBER('A', 12),  16, 3 },        /* AVB_TXCREFCLK */
5183                 { PIN_NUMBER('A', 9),   12, 3 },        /* AVB_MDIO */
5184                 { RCAR_GP_PIN(2,  9),    8, 3 },        /* AVB_MDC */
5185                 { RCAR_GP_PIN(2, 10),    4, 3 },        /* AVB_MAGIC */
5186                 { RCAR_GP_PIN(2, 11),    0, 3 },        /* AVB_PHY_INT */
5187         } },
5188         { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
5189                 { RCAR_GP_PIN(2, 12), 28, 3 },  /* AVB_LINK */
5190                 { RCAR_GP_PIN(2, 13), 24, 3 },  /* AVB_AVTP_MATCH */
5191                 { RCAR_GP_PIN(2, 14), 20, 3 },  /* AVB_AVTP_CAPTURE */
5192                 { RCAR_GP_PIN(2,  0), 16, 3 },  /* IRQ0 */
5193                 { RCAR_GP_PIN(2,  1), 12, 3 },  /* IRQ1 */
5194                 { RCAR_GP_PIN(2,  2),  8, 3 },  /* IRQ2 */
5195                 { RCAR_GP_PIN(2,  3),  4, 3 },  /* IRQ3 */
5196                 { RCAR_GP_PIN(2,  4),  0, 3 },  /* IRQ4 */
5197         } },
5198         { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
5199                 { RCAR_GP_PIN(2,  5), 28, 3 },  /* IRQ5 */
5200                 { RCAR_GP_PIN(2,  6), 24, 3 },  /* PWM0 */
5201                 { RCAR_GP_PIN(2,  7), 20, 3 },  /* PWM1 */
5202                 { RCAR_GP_PIN(2,  8), 16, 3 },  /* PWM2 */
5203                 { RCAR_GP_PIN(1,  0), 12, 3 },  /* A0 */
5204                 { RCAR_GP_PIN(1,  1),  8, 3 },  /* A1 */
5205                 { RCAR_GP_PIN(1,  2),  4, 3 },  /* A2 */
5206                 { RCAR_GP_PIN(1,  3),  0, 3 },  /* A3 */
5207         } },
5208         { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
5209                 { RCAR_GP_PIN(1,  4), 28, 3 },  /* A4 */
5210                 { RCAR_GP_PIN(1,  5), 24, 3 },  /* A5 */
5211                 { RCAR_GP_PIN(1,  6), 20, 3 },  /* A6 */
5212                 { RCAR_GP_PIN(1,  7), 16, 3 },  /* A7 */
5213                 { RCAR_GP_PIN(1,  8), 12, 3 },  /* A8 */
5214                 { RCAR_GP_PIN(1,  9),  8, 3 },  /* A9 */
5215                 { RCAR_GP_PIN(1, 10),  4, 3 },  /* A10 */
5216                 { RCAR_GP_PIN(1, 11),  0, 3 },  /* A11 */
5217         } },
5218         { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
5219                 { RCAR_GP_PIN(1, 12), 28, 3 },  /* A12 */
5220                 { RCAR_GP_PIN(1, 13), 24, 3 },  /* A13 */
5221                 { RCAR_GP_PIN(1, 14), 20, 3 },  /* A14 */
5222                 { RCAR_GP_PIN(1, 15), 16, 3 },  /* A15 */
5223                 { RCAR_GP_PIN(1, 16), 12, 3 },  /* A16 */
5224                 { RCAR_GP_PIN(1, 17),  8, 3 },  /* A17 */
5225                 { RCAR_GP_PIN(1, 18),  4, 3 },  /* A18 */
5226                 { RCAR_GP_PIN(1, 19),  0, 3 },  /* A19 */
5227         } },
5228         { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
5229                 { PIN_NUMBER('F', 1), 28, 3 },  /* CLKOUT */
5230                 { RCAR_GP_PIN(1, 20), 24, 3 },  /* CS0 */
5231                 { RCAR_GP_PIN(1, 21), 20, 3 },  /* CS1_A26 */
5232                 { RCAR_GP_PIN(1, 22), 16, 3 },  /* BS */
5233                 { RCAR_GP_PIN(1, 23), 12, 3 },  /* RD */
5234                 { RCAR_GP_PIN(1, 24),  8, 3 },  /* RD_WR */
5235                 { RCAR_GP_PIN(1, 25),  4, 3 },  /* WE0 */
5236                 { RCAR_GP_PIN(1, 26),  0, 3 },  /* WE1 */
5237         } },
5238         { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
5239                 { RCAR_GP_PIN(1, 27), 28, 3 },  /* EX_WAIT0 */
5240                 { PIN_NUMBER('C', 1), 24, 3 },  /* PRESETOUT# */
5241                 { RCAR_GP_PIN(0,  0), 20, 3 },  /* D0 */
5242                 { RCAR_GP_PIN(0,  1), 16, 3 },  /* D1 */
5243                 { RCAR_GP_PIN(0,  2), 12, 3 },  /* D2 */
5244                 { RCAR_GP_PIN(0,  3),  8, 3 },  /* D3 */
5245                 { RCAR_GP_PIN(0,  4),  4, 3 },  /* D4 */
5246                 { RCAR_GP_PIN(0,  5),  0, 3 },  /* D5 */
5247         } },
5248         { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
5249                 { RCAR_GP_PIN(0,  6), 28, 3 },  /* D6 */
5250                 { RCAR_GP_PIN(0,  7), 24, 3 },  /* D7 */
5251                 { RCAR_GP_PIN(0,  8), 20, 3 },  /* D8 */
5252                 { RCAR_GP_PIN(0,  9), 16, 3 },  /* D9 */
5253                 { RCAR_GP_PIN(0, 10), 12, 3 },  /* D10 */
5254                 { RCAR_GP_PIN(0, 11),  8, 3 },  /* D11 */
5255                 { RCAR_GP_PIN(0, 12),  4, 3 },  /* D12 */
5256                 { RCAR_GP_PIN(0, 13),  0, 3 },  /* D13 */
5257         } },
5258         { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
5259                 { RCAR_GP_PIN(0, 14),   28, 3 },        /* D14 */
5260                 { RCAR_GP_PIN(0, 15),   24, 3 },        /* D15 */
5261                 { RCAR_GP_PIN(7,  0),   20, 3 },        /* AVS1 */
5262                 { RCAR_GP_PIN(7,  1),   16, 3 },        /* AVS2 */
5263                 { RCAR_GP_PIN(7,  2),   12, 3 },        /* HDMI0_CEC */
5264                 { RCAR_GP_PIN(7,  3),    8, 3 },        /* HDMI1_CEC */
5265                 { PIN_A_NUMBER('P', 7),  4, 2 },        /* DU_DOTCLKIN0 */
5266                 { PIN_A_NUMBER('P', 8),  0, 2 },        /* DU_DOTCLKIN1 */
5267         } },
5268         { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
5269                 { PIN_A_NUMBER('R', 7),  28, 2 },       /* DU_DOTCLKIN2 */
5270                 { PIN_A_NUMBER('R', 8),  24, 2 },       /* DU_DOTCLKIN3 */
5271                 { PIN_A_NUMBER('D', 38), 20, 2 },       /* FSCLKST# */
5272                 { PIN_A_NUMBER('R', 30),  4, 2 },       /* TMS */
5273         } },
5274         { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
5275                 { PIN_A_NUMBER('T', 28), 28, 2 },       /* TDO */
5276                 { PIN_A_NUMBER('T', 30), 24, 2 },       /* ASEBRK */
5277                 { RCAR_GP_PIN(3,  0),    20, 3 },       /* SD0_CLK */
5278                 { RCAR_GP_PIN(3,  1),    16, 3 },       /* SD0_CMD */
5279                 { RCAR_GP_PIN(3,  2),    12, 3 },       /* SD0_DAT0 */
5280                 { RCAR_GP_PIN(3,  3),     8, 3 },       /* SD0_DAT1 */
5281                 { RCAR_GP_PIN(3,  4),     4, 3 },       /* SD0_DAT2 */
5282                 { RCAR_GP_PIN(3,  5),     0, 3 },       /* SD0_DAT3 */
5283         } },
5284         { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
5285                 { RCAR_GP_PIN(3,  6), 28, 3 },  /* SD1_CLK */
5286                 { RCAR_GP_PIN(3,  7), 24, 3 },  /* SD1_CMD */
5287                 { RCAR_GP_PIN(3,  8), 20, 3 },  /* SD1_DAT0 */
5288                 { RCAR_GP_PIN(3,  9), 16, 3 },  /* SD1_DAT1 */
5289                 { RCAR_GP_PIN(3, 10), 12, 3 },  /* SD1_DAT2 */
5290                 { RCAR_GP_PIN(3, 11),  8, 3 },  /* SD1_DAT3 */
5291                 { RCAR_GP_PIN(4,  0),  4, 3 },  /* SD2_CLK */
5292                 { RCAR_GP_PIN(4,  1),  0, 3 },  /* SD2_CMD */
5293         } },
5294         { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
5295                 { RCAR_GP_PIN(4,  2), 28, 3 },  /* SD2_DAT0 */
5296                 { RCAR_GP_PIN(4,  3), 24, 3 },  /* SD2_DAT1 */
5297                 { RCAR_GP_PIN(4,  4), 20, 3 },  /* SD2_DAT2 */
5298                 { RCAR_GP_PIN(4,  5), 16, 3 },  /* SD2_DAT3 */
5299                 { RCAR_GP_PIN(4,  6), 12, 3 },  /* SD2_DS */
5300                 { RCAR_GP_PIN(4,  7),  8, 3 },  /* SD3_CLK */
5301                 { RCAR_GP_PIN(4,  8),  4, 3 },  /* SD3_CMD */
5302                 { RCAR_GP_PIN(4,  9),  0, 3 },  /* SD3_DAT0 */
5303         } },
5304         { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
5305                 { RCAR_GP_PIN(4, 10), 28, 3 },  /* SD3_DAT1 */
5306                 { RCAR_GP_PIN(4, 11), 24, 3 },  /* SD3_DAT2 */
5307                 { RCAR_GP_PIN(4, 12), 20, 3 },  /* SD3_DAT3 */
5308                 { RCAR_GP_PIN(4, 13), 16, 3 },  /* SD3_DAT4 */
5309                 { RCAR_GP_PIN(4, 14), 12, 3 },  /* SD3_DAT5 */
5310                 { RCAR_GP_PIN(4, 15),  8, 3 },  /* SD3_DAT6 */
5311                 { RCAR_GP_PIN(4, 16),  4, 3 },  /* SD3_DAT7 */
5312                 { RCAR_GP_PIN(4, 17),  0, 3 },  /* SD3_DS */
5313         } },
5314         { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
5315                 { RCAR_GP_PIN(3, 12), 28, 3 },  /* SD0_CD */
5316                 { RCAR_GP_PIN(3, 13), 24, 3 },  /* SD0_WP */
5317                 { RCAR_GP_PIN(3, 14), 20, 3 },  /* SD1_CD */
5318                 { RCAR_GP_PIN(3, 15), 16, 3 },  /* SD1_WP */
5319                 { RCAR_GP_PIN(5,  0), 12, 3 },  /* SCK0 */
5320                 { RCAR_GP_PIN(5,  1),  8, 3 },  /* RX0 */
5321                 { RCAR_GP_PIN(5,  2),  4, 3 },  /* TX0 */
5322                 { RCAR_GP_PIN(5,  3),  0, 3 },  /* CTS0 */
5323         } },
5324         { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
5325                 { RCAR_GP_PIN(5,  4), 28, 3 },  /* RTS0_TANS */
5326                 { RCAR_GP_PIN(5,  5), 24, 3 },  /* RX1 */
5327                 { RCAR_GP_PIN(5,  6), 20, 3 },  /* TX1 */
5328                 { RCAR_GP_PIN(5,  7), 16, 3 },  /* CTS1 */
5329                 { RCAR_GP_PIN(5,  8), 12, 3 },  /* RTS1_TANS */
5330                 { RCAR_GP_PIN(5,  9),  8, 3 },  /* SCK2 */
5331                 { RCAR_GP_PIN(5, 10),  4, 3 },  /* TX2 */
5332                 { RCAR_GP_PIN(5, 11),  0, 3 },  /* RX2 */
5333         } },
5334         { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
5335                 { RCAR_GP_PIN(5, 12), 28, 3 },  /* HSCK0 */
5336                 { RCAR_GP_PIN(5, 13), 24, 3 },  /* HRX0 */
5337                 { RCAR_GP_PIN(5, 14), 20, 3 },  /* HTX0 */
5338                 { RCAR_GP_PIN(5, 15), 16, 3 },  /* HCTS0 */
5339                 { RCAR_GP_PIN(5, 16), 12, 3 },  /* HRTS0 */
5340                 { RCAR_GP_PIN(5, 17),  8, 3 },  /* MSIOF0_SCK */
5341                 { RCAR_GP_PIN(5, 18),  4, 3 },  /* MSIOF0_SYNC */
5342                 { RCAR_GP_PIN(5, 19),  0, 3 },  /* MSIOF0_SS1 */
5343         } },
5344         { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
5345                 { RCAR_GP_PIN(5, 20), 28, 3 },  /* MSIOF0_TXD */
5346                 { RCAR_GP_PIN(5, 21), 24, 3 },  /* MSIOF0_SS2 */
5347                 { RCAR_GP_PIN(5, 22), 20, 3 },  /* MSIOF0_RXD */
5348                 { RCAR_GP_PIN(5, 23), 16, 3 },  /* MLB_CLK */
5349                 { RCAR_GP_PIN(5, 24), 12, 3 },  /* MLB_SIG */
5350                 { RCAR_GP_PIN(5, 25),  8, 3 },  /* MLB_DAT */
5351                 { PIN_NUMBER('H', 37),  4, 3 }, /* MLB_REF */
5352                 { RCAR_GP_PIN(6,  0),  0, 3 },  /* SSI_SCK01239 */
5353         } },
5354         { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
5355                 { RCAR_GP_PIN(6,  1), 28, 3 },  /* SSI_WS01239 */
5356                 { RCAR_GP_PIN(6,  2), 24, 3 },  /* SSI_SDATA0 */
5357                 { RCAR_GP_PIN(6,  3), 20, 3 },  /* SSI_SDATA1 */
5358                 { RCAR_GP_PIN(6,  4), 16, 3 },  /* SSI_SDATA2 */
5359                 { RCAR_GP_PIN(6,  5), 12, 3 },  /* SSI_SCK34 */
5360                 { RCAR_GP_PIN(6,  6),  8, 3 },  /* SSI_WS34 */
5361                 { RCAR_GP_PIN(6,  7),  4, 3 },  /* SSI_SDATA3 */
5362                 { RCAR_GP_PIN(6,  8),  0, 3 },  /* SSI_SCK4 */
5363         } },
5364         { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
5365                 { RCAR_GP_PIN(6,  9), 28, 3 },  /* SSI_WS4 */
5366                 { RCAR_GP_PIN(6, 10), 24, 3 },  /* SSI_SDATA4 */
5367                 { RCAR_GP_PIN(6, 11), 20, 3 },  /* SSI_SCK5 */
5368                 { RCAR_GP_PIN(6, 12), 16, 3 },  /* SSI_WS5 */
5369                 { RCAR_GP_PIN(6, 13), 12, 3 },  /* SSI_SDATA5 */
5370                 { RCAR_GP_PIN(6, 14),  8, 3 },  /* SSI_SCK6 */
5371                 { RCAR_GP_PIN(6, 15),  4, 3 },  /* SSI_WS6 */
5372                 { RCAR_GP_PIN(6, 16),  0, 3 },  /* SSI_SDATA6 */
5373         } },
5374         { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
5375                 { RCAR_GP_PIN(6, 17), 28, 3 },  /* SSI_SCK78 */
5376                 { RCAR_GP_PIN(6, 18), 24, 3 },  /* SSI_WS78 */
5377                 { RCAR_GP_PIN(6, 19), 20, 3 },  /* SSI_SDATA7 */
5378                 { RCAR_GP_PIN(6, 20), 16, 3 },  /* SSI_SDATA8 */
5379                 { RCAR_GP_PIN(6, 21), 12, 3 },  /* SSI_SDATA9 */
5380                 { RCAR_GP_PIN(6, 22),  8, 3 },  /* AUDIO_CLKA */
5381                 { RCAR_GP_PIN(6, 23),  4, 3 },  /* AUDIO_CLKB */
5382                 { RCAR_GP_PIN(6, 24),  0, 3 },  /* USB0_PWEN */
5383         } },
5384         { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
5385                 { RCAR_GP_PIN(6, 25), 28, 3 },  /* USB0_OVC */
5386                 { RCAR_GP_PIN(6, 26), 24, 3 },  /* USB1_PWEN */
5387                 { RCAR_GP_PIN(6, 27), 20, 3 },  /* USB1_OVC */
5388                 { RCAR_GP_PIN(6, 28), 16, 3 },  /* USB30_PWEN */
5389                 { RCAR_GP_PIN(6, 29), 12, 3 },  /* USB30_OVC */
5390                 { RCAR_GP_PIN(6, 30),  8, 3 },  /* USB31_PWEN */
5391                 { RCAR_GP_PIN(6, 31),  4, 3 },  /* USB31_OVC */
5392         } },
5393         { },
5394 };
5395
5396 static int r8a7795_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
5397 {
5398         int bit = -EINVAL;
5399
5400         *pocctrl = 0xe6060380;
5401
5402         if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
5403                 bit = pin & 0x1f;
5404
5405         if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
5406                 bit = (pin & 0x1f) + 12;
5407
5408         return bit;
5409 }
5410
5411 #define PUEN    0xe6060400
5412 #define PUD     0xe6060440
5413
5414 #define PU0     0x00
5415 #define PU1     0x04
5416 #define PU2     0x08
5417 #define PU3     0x0c
5418 #define PU4     0x10
5419 #define PU5     0x14
5420 #define PU6     0x18
5421
5422 static const struct sh_pfc_bias_info bias_info[] = {
5423         { RCAR_GP_PIN(2, 11),    PU0, 31 },     /* AVB_PHY_INT */
5424         { RCAR_GP_PIN(2, 10),    PU0, 30 },     /* AVB_MAGIC */
5425         { RCAR_GP_PIN(2,  9),    PU0, 29 },     /* AVB_MDC */
5426         { PIN_NUMBER('A', 9),    PU0, 28 },     /* AVB_MDIO */
5427         { PIN_NUMBER('A', 12),   PU0, 27 },     /* AVB_TXCREFCLK */
5428         { PIN_NUMBER('B', 17),   PU0, 26 },     /* AVB_TD3 */
5429         { PIN_NUMBER('A', 17),   PU0, 25 },     /* AVB_TD2 */
5430         { PIN_NUMBER('B', 18),   PU0, 24 },     /* AVB_TD1 */
5431         { PIN_NUMBER('A', 18),   PU0, 23 },     /* AVB_TD0 */
5432         { PIN_NUMBER('A', 19),   PU0, 22 },     /* AVB_TXC */
5433         { PIN_NUMBER('A', 8),    PU0, 21 },     /* AVB_TX_CTL */
5434         { PIN_NUMBER('B', 14),   PU0, 20 },     /* AVB_RD3 */
5435         { PIN_NUMBER('A', 14),   PU0, 19 },     /* AVB_RD2 */
5436         { PIN_NUMBER('B', 13),   PU0, 18 },     /* AVB_RD1 */
5437         { PIN_NUMBER('A', 13),   PU0, 17 },     /* AVB_RD0 */
5438         { PIN_NUMBER('B', 19),   PU0, 16 },     /* AVB_RXC */
5439         { PIN_NUMBER('A', 16),   PU0, 15 },     /* AVB_RX_CTL */
5440         { PIN_NUMBER('V', 7),    PU0, 14 },     /* RPC_RESET# */
5441         { PIN_NUMBER('V', 6),    PU0, 13 },     /* RPC_WP# */
5442         { PIN_NUMBER('Y', 7),    PU0, 12 },     /* RPC_INT# */
5443         { PIN_NUMBER('V', 5),    PU0, 11 },     /* QSPI1_SSL */
5444         { PIN_A_NUMBER('C', 3),  PU0, 10 },     /* QSPI1_IO3 */
5445         { PIN_A_NUMBER('E', 4),  PU0,  9 },     /* QSPI1_IO2 */
5446         { PIN_A_NUMBER('E', 5),  PU0,  8 },     /* QSPI1_MISO_IO1 */
5447         { PIN_A_NUMBER('C', 7),  PU0,  7 },     /* QSPI1_MOSI_IO0 */
5448         { PIN_NUMBER('V', 3),    PU0,  6 },     /* QSPI1_SPCLK */
5449         { PIN_NUMBER('Y', 3),    PU0,  5 },     /* QSPI0_SSL */
5450         { PIN_A_NUMBER('B', 6),  PU0,  4 },     /* QSPI0_IO3 */
5451         { PIN_NUMBER('Y', 6),    PU0,  3 },     /* QSPI0_IO2 */
5452         { PIN_A_NUMBER('B', 4),  PU0,  2 },     /* QSPI0_MISO_IO1 */
5453         { PIN_A_NUMBER('C', 5),  PU0,  1 },     /* QSPI0_MOSI_IO0 */
5454         { PIN_NUMBER('W', 3),    PU0,  0 },     /* QSPI0_SPCLK */
5455
5456         { RCAR_GP_PIN(1, 19),    PU1, 31 },     /* A19 */
5457         { RCAR_GP_PIN(1, 18),    PU1, 30 },     /* A18 */
5458         { RCAR_GP_PIN(1, 17),    PU1, 29 },     /* A17 */
5459         { RCAR_GP_PIN(1, 16),    PU1, 28 },     /* A16 */
5460         { RCAR_GP_PIN(1, 15),    PU1, 27 },     /* A15 */
5461         { RCAR_GP_PIN(1, 14),    PU1, 26 },     /* A14 */
5462         { RCAR_GP_PIN(1, 13),    PU1, 25 },     /* A13 */
5463         { RCAR_GP_PIN(1, 12),    PU1, 24 },     /* A12 */
5464         { RCAR_GP_PIN(1, 11),    PU1, 23 },     /* A11 */
5465         { RCAR_GP_PIN(1, 10),    PU1, 22 },     /* A10 */
5466         { RCAR_GP_PIN(1,  9),    PU1, 21 },     /* A9 */
5467         { RCAR_GP_PIN(1,  8),    PU1, 20 },     /* A8 */
5468         { RCAR_GP_PIN(1,  7),    PU1, 19 },     /* A7 */
5469         { RCAR_GP_PIN(1,  6),    PU1, 18 },     /* A6 */
5470         { RCAR_GP_PIN(1,  5),    PU1, 17 },     /* A5 */
5471         { RCAR_GP_PIN(1,  4),    PU1, 16 },     /* A4 */
5472         { RCAR_GP_PIN(1,  3),    PU1, 15 },     /* A3 */
5473         { RCAR_GP_PIN(1,  2),    PU1, 14 },     /* A2 */
5474         { RCAR_GP_PIN(1,  1),    PU1, 13 },     /* A1 */
5475         { RCAR_GP_PIN(1,  0),    PU1, 12 },     /* A0 */
5476         { RCAR_GP_PIN(2,  8),    PU1, 11 },     /* PWM2_A */
5477         { RCAR_GP_PIN(2,  7),    PU1, 10 },     /* PWM1_A */
5478         { RCAR_GP_PIN(2,  6),    PU1,  9 },     /* PWM0 */
5479         { RCAR_GP_PIN(2,  5),    PU1,  8 },     /* IRQ5 */
5480         { RCAR_GP_PIN(2,  4),    PU1,  7 },     /* IRQ4 */
5481         { RCAR_GP_PIN(2,  3),    PU1,  6 },     /* IRQ3 */
5482         { RCAR_GP_PIN(2,  2),    PU1,  5 },     /* IRQ2 */
5483         { RCAR_GP_PIN(2,  1),    PU1,  4 },     /* IRQ1 */
5484         { RCAR_GP_PIN(2,  0),    PU1,  3 },     /* IRQ0 */
5485         { RCAR_GP_PIN(2, 14),    PU1,  2 },     /* AVB_AVTP_CAPTURE_A */
5486         { RCAR_GP_PIN(2, 13),    PU1,  1 },     /* AVB_AVTP_MATCH_A */
5487         { RCAR_GP_PIN(2, 12),    PU1,  0 },     /* AVB_LINK */
5488
5489         { PIN_A_NUMBER('P', 8),  PU2, 31 },     /* DU_DOTCLKIN1 */
5490         { PIN_A_NUMBER('P', 7),  PU2, 30 },     /* DU_DOTCLKIN0 */
5491         { RCAR_GP_PIN(7,  3),    PU2, 29 },     /* HDMI1_CEC */
5492         { RCAR_GP_PIN(7,  2),    PU2, 28 },     /* HDMI0_CEC */
5493         { RCAR_GP_PIN(7,  1),    PU2, 27 },     /* AVS2 */
5494         { RCAR_GP_PIN(7,  0),    PU2, 26 },     /* AVS1 */
5495         { RCAR_GP_PIN(0, 15),    PU2, 25 },     /* D15 */
5496         { RCAR_GP_PIN(0, 14),    PU2, 24 },     /* D14 */
5497         { RCAR_GP_PIN(0, 13),    PU2, 23 },     /* D13 */
5498         { RCAR_GP_PIN(0, 12),    PU2, 22 },     /* D12 */
5499         { RCAR_GP_PIN(0, 11),    PU2, 21 },     /* D11 */
5500         { RCAR_GP_PIN(0, 10),    PU2, 20 },     /* D10 */
5501         { RCAR_GP_PIN(0,  9),    PU2, 19 },     /* D9 */
5502         { RCAR_GP_PIN(0,  8),    PU2, 18 },     /* D8 */
5503         { RCAR_GP_PIN(0,  7),    PU2, 17 },     /* D7 */
5504         { RCAR_GP_PIN(0,  6),    PU2, 16 },     /* D6 */
5505         { RCAR_GP_PIN(0,  5),    PU2, 15 },     /* D5 */
5506         { RCAR_GP_PIN(0,  4),    PU2, 14 },     /* D4 */
5507         { RCAR_GP_PIN(0,  3),    PU2, 13 },     /* D3 */
5508         { RCAR_GP_PIN(0,  2),    PU2, 12 },     /* D2 */
5509         { RCAR_GP_PIN(0,  1),    PU2, 11 },     /* D1 */
5510         { RCAR_GP_PIN(0,  0),    PU2, 10 },     /* D0 */
5511         { PIN_NUMBER('C', 1),    PU2,  9 },     /* PRESETOUT# */
5512         { RCAR_GP_PIN(1, 27),    PU2,  8 },     /* EX_WAIT0_A */
5513         { RCAR_GP_PIN(1, 26),    PU2,  7 },     /* WE1_N */
5514         { RCAR_GP_PIN(1, 25),    PU2,  6 },     /* WE0_N */
5515         { RCAR_GP_PIN(1, 24),    PU2,  5 },     /* RD_WR_N */
5516         { RCAR_GP_PIN(1, 23),    PU2,  4 },     /* RD_N */
5517         { RCAR_GP_PIN(1, 22),    PU2,  3 },     /* BS_N */
5518         { RCAR_GP_PIN(1, 21),    PU2,  2 },     /* CS1_N_A26 */
5519         { RCAR_GP_PIN(1, 20),    PU2,  1 },     /* CS0_N */
5520         { PIN_NUMBER('F', 1),    PU2,  0 },     /* CLKOUT */
5521
5522         { RCAR_GP_PIN(4,  9),    PU3, 31 },     /* SD3_DAT0 */
5523         { RCAR_GP_PIN(4,  8),    PU3, 30 },     /* SD3_CMD */
5524         { RCAR_GP_PIN(4,  7),    PU3, 29 },     /* SD3_CLK */
5525         { RCAR_GP_PIN(4,  6),    PU3, 28 },     /* SD2_DS */
5526         { RCAR_GP_PIN(4,  5),    PU3, 27 },     /* SD2_DAT3 */
5527         { RCAR_GP_PIN(4,  4),    PU3, 26 },     /* SD2_DAT2 */
5528         { RCAR_GP_PIN(4,  3),    PU3, 25 },     /* SD2_DAT1 */
5529         { RCAR_GP_PIN(4,  2),    PU3, 24 },     /* SD2_DAT0 */
5530         { RCAR_GP_PIN(4,  1),    PU3, 23 },     /* SD2_CMD */
5531         { RCAR_GP_PIN(4,  0),    PU3, 22 },     /* SD2_CLK */
5532         { RCAR_GP_PIN(3, 11),    PU3, 21 },     /* SD1_DAT3 */
5533         { RCAR_GP_PIN(3, 10),    PU3, 20 },     /* SD1_DAT2 */
5534         { RCAR_GP_PIN(3,  9),    PU3, 19 },     /* SD1_DAT1 */
5535         { RCAR_GP_PIN(3,  8),    PU3, 18 },     /* SD1_DAT0 */
5536         { RCAR_GP_PIN(3,  7),    PU3, 17 },     /* SD1_CMD */
5537         { RCAR_GP_PIN(3,  6),    PU3, 16 },     /* SD1_CLK */
5538         { RCAR_GP_PIN(3,  5),    PU3, 15 },     /* SD0_DAT3 */
5539         { RCAR_GP_PIN(3,  4),    PU3, 14 },     /* SD0_DAT2 */
5540         { RCAR_GP_PIN(3,  3),    PU3, 13 },     /* SD0_DAT1 */
5541         { RCAR_GP_PIN(3,  2),    PU3, 12 },     /* SD0_DAT0 */
5542         { RCAR_GP_PIN(3,  1),    PU3, 11 },     /* SD0_CMD */
5543         { RCAR_GP_PIN(3,  0),    PU3, 10 },     /* SD0_CLK */
5544         { PIN_A_NUMBER('T', 30), PU3,  9 },     /* ASEBRK */
5545         /* bit 8 n/a */
5546         { PIN_A_NUMBER('R', 29), PU3,  7 },     /* TDI */
5547         { PIN_A_NUMBER('R', 30), PU3,  6 },     /* TMS */
5548         { PIN_A_NUMBER('T', 27), PU3,  5 },     /* TCK */
5549         { PIN_A_NUMBER('R', 26), PU3,  4 },     /* TRST# */
5550         { PIN_A_NUMBER('D', 39), PU3,  3 },     /* EXTALR*/
5551         { PIN_A_NUMBER('D', 38), PU3,  2 },     /* FSCLKST# */
5552         { PIN_A_NUMBER('R', 8),  PU3,  1 },     /* DU_DOTCLKIN3 */
5553         { PIN_A_NUMBER('R', 7),  PU3,  0 },     /* DU_DOTCLKIN2 */
5554
5555         { RCAR_GP_PIN(5, 19),    PU4, 31 },     /* MSIOF0_SS1 */
5556         { RCAR_GP_PIN(5, 18),    PU4, 30 },     /* MSIOF0_SYNC */
5557         { RCAR_GP_PIN(5, 17),    PU4, 29 },     /* MSIOF0_SCK */
5558         { RCAR_GP_PIN(5, 16),    PU4, 28 },     /* HRTS0_N */
5559         { RCAR_GP_PIN(5, 15),    PU4, 27 },     /* HCTS0_N */
5560         { RCAR_GP_PIN(5, 14),    PU4, 26 },     /* HTX0 */
5561         { RCAR_GP_PIN(5, 13),    PU4, 25 },     /* HRX0 */
5562         { RCAR_GP_PIN(5, 12),    PU4, 24 },     /* HSCK0 */
5563         { RCAR_GP_PIN(5, 11),    PU4, 23 },     /* RX2_A */
5564         { RCAR_GP_PIN(5, 10),    PU4, 22 },     /* TX2_A */
5565         { RCAR_GP_PIN(5,  9),    PU4, 21 },     /* SCK2 */
5566         { RCAR_GP_PIN(5,  8),    PU4, 20 },     /* RTS1_N_TANS */
5567         { RCAR_GP_PIN(5,  7),    PU4, 19 },     /* CTS1_N */
5568         { RCAR_GP_PIN(5,  6),    PU4, 18 },     /* TX1_A */
5569         { RCAR_GP_PIN(5,  5),    PU4, 17 },     /* RX1_A */
5570         { RCAR_GP_PIN(5,  4),    PU4, 16 },     /* RTS0_N_TANS */
5571         { RCAR_GP_PIN(5,  3),    PU4, 15 },     /* CTS0_N */
5572         { RCAR_GP_PIN(5,  2),    PU4, 14 },     /* TX0 */
5573         { RCAR_GP_PIN(5,  1),    PU4, 13 },     /* RX0 */
5574         { RCAR_GP_PIN(5,  0),    PU4, 12 },     /* SCK0 */
5575         { RCAR_GP_PIN(3, 15),    PU4, 11 },     /* SD1_WP */
5576         { RCAR_GP_PIN(3, 14),    PU4, 10 },     /* SD1_CD */
5577         { RCAR_GP_PIN(3, 13),    PU4,  9 },     /* SD0_WP */
5578         { RCAR_GP_PIN(3, 12),    PU4,  8 },     /* SD0_CD */
5579         { RCAR_GP_PIN(4, 17),    PU4,  7 },     /* SD3_DS */
5580         { RCAR_GP_PIN(4, 16),    PU4,  6 },     /* SD3_DAT7 */
5581         { RCAR_GP_PIN(4, 15),    PU4,  5 },     /* SD3_DAT6 */
5582         { RCAR_GP_PIN(4, 14),    PU4,  4 },     /* SD3_DAT5 */
5583         { RCAR_GP_PIN(4, 13),    PU4,  3 },     /* SD3_DAT4 */
5584         { RCAR_GP_PIN(4, 12),    PU4,  2 },     /* SD3_DAT3 */
5585         { RCAR_GP_PIN(4, 11),    PU4,  1 },     /* SD3_DAT2 */
5586         { RCAR_GP_PIN(4, 10),    PU4,  0 },     /* SD3_DAT1 */
5587
5588         { RCAR_GP_PIN(6, 24),    PU5, 31 },     /* USB0_PWEN */
5589         { RCAR_GP_PIN(6, 23),    PU5, 30 },     /* AUDIO_CLKB_B */
5590         { RCAR_GP_PIN(6, 22),    PU5, 29 },     /* AUDIO_CLKA_A */
5591         { RCAR_GP_PIN(6, 21),    PU5, 28 },     /* SSI_SDATA9_A */
5592         { RCAR_GP_PIN(6, 20),    PU5, 27 },     /* SSI_SDATA8 */
5593         { RCAR_GP_PIN(6, 19),    PU5, 26 },     /* SSI_SDATA7 */
5594         { RCAR_GP_PIN(6, 18),    PU5, 25 },     /* SSI_WS78 */
5595         { RCAR_GP_PIN(6, 17),    PU5, 24 },     /* SSI_SCK78 */
5596         { RCAR_GP_PIN(6, 16),    PU5, 23 },     /* SSI_SDATA6 */
5597         { RCAR_GP_PIN(6, 15),    PU5, 22 },     /* SSI_WS6 */
5598         { RCAR_GP_PIN(6, 14),    PU5, 21 },     /* SSI_SCK6 */
5599         { RCAR_GP_PIN(6, 13),    PU5, 20 },     /* SSI_SDATA5 */
5600         { RCAR_GP_PIN(6, 12),    PU5, 19 },     /* SSI_WS5 */
5601         { RCAR_GP_PIN(6, 11),    PU5, 18 },     /* SSI_SCK5 */
5602         { RCAR_GP_PIN(6, 10),    PU5, 17 },     /* SSI_SDATA4 */
5603         { RCAR_GP_PIN(6,  9),    PU5, 16 },     /* SSI_WS4 */
5604         { RCAR_GP_PIN(6,  8),    PU5, 15 },     /* SSI_SCK4 */
5605         { RCAR_GP_PIN(6,  7),    PU5, 14 },     /* SSI_SDATA3 */
5606         { RCAR_GP_PIN(6,  6),    PU5, 13 },     /* SSI_WS34 */
5607         { RCAR_GP_PIN(6,  5),    PU5, 12 },     /* SSI_SCK34 */
5608         { RCAR_GP_PIN(6,  4),    PU5, 11 },     /* SSI_SDATA2_A */
5609         { RCAR_GP_PIN(6,  3),    PU5, 10 },     /* SSI_SDATA1_A */
5610         { RCAR_GP_PIN(6,  2),    PU5,  9 },     /* SSI_SDATA0 */
5611         { RCAR_GP_PIN(6,  1),    PU5,  8 },     /* SSI_WS01239 */
5612         { RCAR_GP_PIN(6,  0),    PU5,  7 },     /* SSI_SCK01239 */
5613         { PIN_NUMBER('H', 37),   PU5,  6 },     /* MLB_REF */
5614         { RCAR_GP_PIN(5, 25),    PU5,  5 },     /* MLB_DAT */
5615         { RCAR_GP_PIN(5, 24),    PU5,  4 },     /* MLB_SIG */
5616         { RCAR_GP_PIN(5, 23),    PU5,  3 },     /* MLB_CLK */
5617         { RCAR_GP_PIN(5, 22),    PU5,  2 },     /* MSIOF0_RXD */
5618         { RCAR_GP_PIN(5, 21),    PU5,  1 },     /* MSIOF0_SS2 */
5619         { RCAR_GP_PIN(5, 20),    PU5,  0 },     /* MSIOF0_TXD */
5620
5621         { RCAR_GP_PIN(6, 31),    PU6,  6 },     /* USB31_OVC */
5622         { RCAR_GP_PIN(6, 30),    PU6,  5 },     /* USB31_PWEN */
5623         { RCAR_GP_PIN(6, 29),    PU6,  4 },     /* USB30_OVC */
5624         { RCAR_GP_PIN(6, 28),    PU6,  3 },     /* USB30_PWEN */
5625         { RCAR_GP_PIN(6, 27),    PU6,  2 },     /* USB1_OVC */
5626         { RCAR_GP_PIN(6, 26),    PU6,  1 },     /* USB1_PWEN */
5627         { RCAR_GP_PIN(6, 25),    PU6,  0 },     /* USB0_OVC */
5628 };
5629
5630 static unsigned int r8a7795_pinmux_get_bias(struct sh_pfc *pfc,
5631                                             unsigned int pin)
5632 {
5633         const struct sh_pfc_bias_info *info;
5634         u32 reg;
5635         u32 bit;
5636
5637         info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin);
5638         if (!info)
5639                 return PIN_CONFIG_BIAS_DISABLE;
5640
5641         reg = info->reg;
5642         bit = BIT(info->bit);
5643
5644         if (!(sh_pfc_read_reg(pfc, PUEN + reg, 32) & bit))
5645                 return PIN_CONFIG_BIAS_DISABLE;
5646         else if (sh_pfc_read_reg(pfc, PUD + reg, 32) & bit)
5647                 return PIN_CONFIG_BIAS_PULL_UP;
5648         else
5649                 return PIN_CONFIG_BIAS_PULL_DOWN;
5650 }
5651
5652 static void r8a7795_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
5653                                    unsigned int bias)
5654 {
5655         const struct sh_pfc_bias_info *info;
5656         u32 enable, updown;
5657         u32 reg;
5658         u32 bit;
5659
5660         info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin);
5661         if (!info)
5662                 return;
5663
5664         reg = info->reg;
5665         bit = BIT(info->bit);
5666
5667         enable = sh_pfc_read_reg(pfc, PUEN + reg, 32) & ~bit;
5668         if (bias != PIN_CONFIG_BIAS_DISABLE)
5669                 enable |= bit;
5670
5671         updown = sh_pfc_read_reg(pfc, PUD + reg, 32) & ~bit;
5672         if (bias == PIN_CONFIG_BIAS_PULL_UP)
5673                 updown |= bit;
5674
5675         sh_pfc_write_reg(pfc, PUD + reg, 32, updown);
5676         sh_pfc_write_reg(pfc, PUEN + reg, 32, enable);
5677 }
5678
5679 static const struct sh_pfc_soc_operations r8a7795_pinmux_ops = {
5680         .pin_to_pocctrl = r8a7795_pin_to_pocctrl,
5681         .get_bias = r8a7795_pinmux_get_bias,
5682         .set_bias = r8a7795_pinmux_set_bias,
5683 };
5684
5685 const struct sh_pfc_soc_info r8a7795_pinmux_info = {
5686         .name = "r8a77950_pfc",
5687         .ops = &r8a7795_pinmux_ops,
5688         .unlock_reg = 0xe6060000, /* PMMR */
5689
5690         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
5691
5692         .pins = pinmux_pins,
5693         .nr_pins = ARRAY_SIZE(pinmux_pins),
5694         .groups = pinmux_groups,
5695         .nr_groups = ARRAY_SIZE(pinmux_groups),
5696         .functions = pinmux_functions,
5697         .nr_functions = ARRAY_SIZE(pinmux_functions),
5698
5699         .cfg_regs = pinmux_config_regs,
5700         .drive_regs = pinmux_drive_regs,
5701
5702         .pinmux_data = pinmux_data,
5703         .pinmux_data_size = ARRAY_SIZE(pinmux_data),
5704 };