2 * Copyright (C) Maxime Coquelin 2015
3 * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 * License terms: GNU General Public License (GPL), version 2
6 * Heavily based on Mediatek's pinctrl driver
9 #include <linux/gpio/driver.h>
11 #include <linux/irq.h>
12 #include <linux/mfd/syscon.h>
13 #include <linux/module.h>
15 #include <linux/of_address.h>
16 #include <linux/of_device.h>
17 #include <linux/of_irq.h>
18 #include <linux/pinctrl/consumer.h>
19 #include <linux/pinctrl/machine.h>
20 #include <linux/pinctrl/pinconf.h>
21 #include <linux/pinctrl/pinconf-generic.h>
22 #include <linux/pinctrl/pinctrl.h>
23 #include <linux/pinctrl/pinmux.h>
24 #include <linux/platform_device.h>
25 #include <linux/regmap.h>
26 #include <linux/reset.h>
27 #include <linux/slab.h>
30 #include "../pinconf.h"
31 #include "../pinctrl-utils.h"
32 #include "pinctrl-stm32.h"
34 #define STM32_GPIO_MODER 0x00
35 #define STM32_GPIO_TYPER 0x04
36 #define STM32_GPIO_SPEEDR 0x08
37 #define STM32_GPIO_PUPDR 0x0c
38 #define STM32_GPIO_IDR 0x10
39 #define STM32_GPIO_ODR 0x14
40 #define STM32_GPIO_BSRR 0x18
41 #define STM32_GPIO_LCKR 0x1c
42 #define STM32_GPIO_AFRL 0x20
43 #define STM32_GPIO_AFRH 0x24
45 #define STM32_GPIO_PINS_PER_BANK 16
46 #define STM32_GPIO_IRQ_LINE 16
48 #define gpio_range_to_bank(chip) \
49 container_of(chip, struct stm32_gpio_bank, range)
51 static const char * const stm32_gpio_functions[] = {
56 "af11", "af12", "af13",
57 "af14", "af15", "analog",
60 struct stm32_pinctrl_group {
66 struct stm32_gpio_bank {
70 struct gpio_chip gpio_chip;
71 struct pinctrl_gpio_range range;
72 struct fwnode_handle *fwnode;
73 struct irq_domain *domain;
77 struct stm32_pinctrl {
79 struct pinctrl_dev *pctl_dev;
80 struct pinctrl_desc pctl_desc;
81 struct stm32_pinctrl_group *groups;
83 const char **grp_names;
84 struct stm32_gpio_bank *banks;
86 const struct stm32_pinctrl_match_data *match_data;
87 struct irq_domain *domain;
88 struct regmap *regmap;
89 struct regmap_field *irqmux[STM32_GPIO_PINS_PER_BANK];
92 static inline int stm32_gpio_pin(int gpio)
94 return gpio % STM32_GPIO_PINS_PER_BANK;
97 static inline u32 stm32_gpio_get_mode(u32 function)
102 case STM32_PIN_AF(0) ... STM32_PIN_AF(15):
104 case STM32_PIN_ANALOG:
111 static inline u32 stm32_gpio_get_alt(u32 function)
116 case STM32_PIN_AF(0) ... STM32_PIN_AF(15):
118 case STM32_PIN_ANALOG:
127 static inline void __stm32_gpio_set(struct stm32_gpio_bank *bank,
128 unsigned offset, int value)
131 offset += STM32_GPIO_PINS_PER_BANK;
133 clk_enable(bank->clk);
135 writel_relaxed(BIT(offset), bank->base + STM32_GPIO_BSRR);
137 clk_disable(bank->clk);
140 static int stm32_gpio_request(struct gpio_chip *chip, unsigned offset)
142 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
143 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
144 struct pinctrl_gpio_range *range;
145 int pin = offset + (bank->bank_nr * STM32_GPIO_PINS_PER_BANK);
147 range = pinctrl_find_gpio_range_from_pin_nolock(pctl->pctl_dev, pin);
149 dev_err(pctl->dev, "pin %d not in range.\n", pin);
153 return pinctrl_request_gpio(chip->base + offset);
156 static void stm32_gpio_free(struct gpio_chip *chip, unsigned offset)
158 pinctrl_free_gpio(chip->base + offset);
161 static int stm32_gpio_get(struct gpio_chip *chip, unsigned offset)
163 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
166 clk_enable(bank->clk);
168 ret = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset));
170 clk_disable(bank->clk);
175 static void stm32_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
177 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
179 __stm32_gpio_set(bank, offset, value);
182 static int stm32_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
184 return pinctrl_gpio_direction_input(chip->base + offset);
187 static int stm32_gpio_direction_output(struct gpio_chip *chip,
188 unsigned offset, int value)
190 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
192 __stm32_gpio_set(bank, offset, value);
193 pinctrl_gpio_direction_output(chip->base + offset);
199 static int stm32_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
201 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
202 struct irq_fwspec fwspec;
204 fwspec.fwnode = bank->fwnode;
205 fwspec.param_count = 2;
206 fwspec.param[0] = offset;
207 fwspec.param[1] = IRQ_TYPE_NONE;
209 return irq_create_fwspec_mapping(&fwspec);
212 static const struct gpio_chip stm32_gpio_template = {
213 .request = stm32_gpio_request,
214 .free = stm32_gpio_free,
215 .get = stm32_gpio_get,
216 .set = stm32_gpio_set,
217 .direction_input = stm32_gpio_direction_input,
218 .direction_output = stm32_gpio_direction_output,
219 .to_irq = stm32_gpio_to_irq,
222 static struct irq_chip stm32_gpio_irq_chip = {
224 .irq_eoi = irq_chip_eoi_parent,
225 .irq_mask = irq_chip_mask_parent,
226 .irq_unmask = irq_chip_unmask_parent,
227 .irq_set_type = irq_chip_set_type_parent,
230 static int stm32_gpio_domain_translate(struct irq_domain *d,
231 struct irq_fwspec *fwspec,
232 unsigned long *hwirq,
235 if ((fwspec->param_count != 2) ||
236 (fwspec->param[0] >= STM32_GPIO_IRQ_LINE))
239 *hwirq = fwspec->param[0];
240 *type = fwspec->param[1];
244 static void stm32_gpio_domain_activate(struct irq_domain *d,
245 struct irq_data *irq_data)
247 struct stm32_gpio_bank *bank = d->host_data;
248 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
250 regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_nr);
251 gpiochip_lock_as_irq(&bank->gpio_chip, irq_data->hwirq);
254 static void stm32_gpio_domain_deactivate(struct irq_domain *d,
255 struct irq_data *irq_data)
257 struct stm32_gpio_bank *bank = d->host_data;
259 gpiochip_unlock_as_irq(&bank->gpio_chip, irq_data->hwirq);
262 static int stm32_gpio_domain_alloc(struct irq_domain *d,
264 unsigned int nr_irqs, void *data)
266 struct stm32_gpio_bank *bank = d->host_data;
267 struct irq_fwspec *fwspec = data;
268 struct irq_fwspec parent_fwspec;
269 irq_hw_number_t hwirq;
271 hwirq = fwspec->param[0];
272 parent_fwspec.fwnode = d->parent->fwnode;
273 parent_fwspec.param_count = 2;
274 parent_fwspec.param[0] = fwspec->param[0];
275 parent_fwspec.param[1] = fwspec->param[1];
277 irq_domain_set_hwirq_and_chip(d, virq, hwirq, &stm32_gpio_irq_chip,
280 return irq_domain_alloc_irqs_parent(d, virq, nr_irqs, &parent_fwspec);
283 static const struct irq_domain_ops stm32_gpio_domain_ops = {
284 .translate = stm32_gpio_domain_translate,
285 .alloc = stm32_gpio_domain_alloc,
286 .free = irq_domain_free_irqs_common,
287 .activate = stm32_gpio_domain_activate,
288 .deactivate = stm32_gpio_domain_deactivate,
291 /* Pinctrl functions */
292 static struct stm32_pinctrl_group *
293 stm32_pctrl_find_group_by_pin(struct stm32_pinctrl *pctl, u32 pin)
297 for (i = 0; i < pctl->ngroups; i++) {
298 struct stm32_pinctrl_group *grp = pctl->groups + i;
307 static bool stm32_pctrl_is_function_valid(struct stm32_pinctrl *pctl,
308 u32 pin_num, u32 fnum)
312 for (i = 0; i < pctl->match_data->npins; i++) {
313 const struct stm32_desc_pin *pin = pctl->match_data->pins + i;
314 const struct stm32_desc_function *func = pin->functions;
316 if (pin->pin.number != pin_num)
319 while (func && func->name) {
320 if (func->num == fnum)
331 static int stm32_pctrl_dt_node_to_map_func(struct stm32_pinctrl *pctl,
332 u32 pin, u32 fnum, struct stm32_pinctrl_group *grp,
333 struct pinctrl_map **map, unsigned *reserved_maps,
336 if (*num_maps == *reserved_maps)
339 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
340 (*map)[*num_maps].data.mux.group = grp->name;
342 if (!stm32_pctrl_is_function_valid(pctl, pin, fnum)) {
343 dev_err(pctl->dev, "invalid function %d on pin %d .\n",
348 (*map)[*num_maps].data.mux.function = stm32_gpio_functions[fnum];
354 static int stm32_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
355 struct device_node *node,
356 struct pinctrl_map **map,
357 unsigned *reserved_maps,
360 struct stm32_pinctrl *pctl;
361 struct stm32_pinctrl_group *grp;
362 struct property *pins;
363 u32 pinfunc, pin, func;
364 unsigned long *configs;
365 unsigned int num_configs;
367 unsigned reserve = 0;
368 int num_pins, num_funcs, maps_per_pin, i, err;
370 pctl = pinctrl_dev_get_drvdata(pctldev);
372 pins = of_find_property(node, "pinmux", NULL);
374 dev_err(pctl->dev, "missing pins property in node %s .\n",
379 err = pinconf_generic_parse_dt_config(node, pctldev, &configs,
387 num_pins = pins->length / sizeof(u32);
388 num_funcs = num_pins;
392 if (has_config && num_pins >= 1)
395 if (!num_pins || !maps_per_pin)
398 reserve = num_pins * maps_per_pin;
400 err = pinctrl_utils_reserve_map(pctldev, map,
401 reserved_maps, num_maps, reserve);
405 for (i = 0; i < num_pins; i++) {
406 err = of_property_read_u32_index(node, "pinmux",
411 pin = STM32_GET_PIN_NO(pinfunc);
412 func = STM32_GET_PIN_FUNC(pinfunc);
414 if (pin >= pctl->match_data->npins) {
415 dev_err(pctl->dev, "invalid pin number.\n");
419 if (!stm32_pctrl_is_function_valid(pctl, pin, func)) {
420 dev_err(pctl->dev, "invalid function.\n");
424 grp = stm32_pctrl_find_group_by_pin(pctl, pin);
426 dev_err(pctl->dev, "unable to match pin %d to group\n",
431 err = stm32_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map,
432 reserved_maps, num_maps);
437 err = pinctrl_utils_add_map_configs(pctldev, map,
438 reserved_maps, num_maps, grp->name,
439 configs, num_configs,
440 PIN_MAP_TYPE_CONFIGS_GROUP);
449 static int stm32_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
450 struct device_node *np_config,
451 struct pinctrl_map **map, unsigned *num_maps)
453 struct device_node *np;
454 unsigned reserved_maps;
461 for_each_child_of_node(np_config, np) {
462 ret = stm32_pctrl_dt_subnode_to_map(pctldev, np, map,
463 &reserved_maps, num_maps);
465 pinctrl_utils_free_map(pctldev, *map, *num_maps);
473 static int stm32_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
475 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
477 return pctl->ngroups;
480 static const char *stm32_pctrl_get_group_name(struct pinctrl_dev *pctldev,
483 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
485 return pctl->groups[group].name;
488 static int stm32_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
490 const unsigned **pins,
493 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
495 *pins = (unsigned *)&pctl->groups[group].pin;
501 static const struct pinctrl_ops stm32_pctrl_ops = {
502 .dt_node_to_map = stm32_pctrl_dt_node_to_map,
503 .dt_free_map = pinctrl_utils_free_map,
504 .get_groups_count = stm32_pctrl_get_groups_count,
505 .get_group_name = stm32_pctrl_get_group_name,
506 .get_group_pins = stm32_pctrl_get_group_pins,
510 /* Pinmux functions */
512 static int stm32_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
514 return ARRAY_SIZE(stm32_gpio_functions);
517 static const char *stm32_pmx_get_func_name(struct pinctrl_dev *pctldev,
520 return stm32_gpio_functions[selector];
523 static int stm32_pmx_get_func_groups(struct pinctrl_dev *pctldev,
525 const char * const **groups,
526 unsigned * const num_groups)
528 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
530 *groups = pctl->grp_names;
531 *num_groups = pctl->ngroups;
536 static void stm32_pmx_set_mode(struct stm32_gpio_bank *bank,
537 int pin, u32 mode, u32 alt)
540 int alt_shift = (pin % 8) * 4;
541 int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4;
544 clk_enable(bank->clk);
545 spin_lock_irqsave(&bank->lock, flags);
547 val = readl_relaxed(bank->base + alt_offset);
548 val &= ~GENMASK(alt_shift + 3, alt_shift);
549 val |= (alt << alt_shift);
550 writel_relaxed(val, bank->base + alt_offset);
552 val = readl_relaxed(bank->base + STM32_GPIO_MODER);
553 val &= ~GENMASK(pin * 2 + 1, pin * 2);
554 val |= mode << (pin * 2);
555 writel_relaxed(val, bank->base + STM32_GPIO_MODER);
557 spin_unlock_irqrestore(&bank->lock, flags);
558 clk_disable(bank->clk);
561 static void stm32_pmx_get_mode(struct stm32_gpio_bank *bank,
562 int pin, u32 *mode, u32 *alt)
565 int alt_shift = (pin % 8) * 4;
566 int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4;
569 clk_enable(bank->clk);
570 spin_lock_irqsave(&bank->lock, flags);
572 val = readl_relaxed(bank->base + alt_offset);
573 val &= GENMASK(alt_shift + 3, alt_shift);
574 *alt = val >> alt_shift;
576 val = readl_relaxed(bank->base + STM32_GPIO_MODER);
577 val &= GENMASK(pin * 2 + 1, pin * 2);
578 *mode = val >> (pin * 2);
580 spin_unlock_irqrestore(&bank->lock, flags);
581 clk_disable(bank->clk);
584 static int stm32_pmx_set_mux(struct pinctrl_dev *pctldev,
589 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
590 struct stm32_pinctrl_group *g = pctl->groups + group;
591 struct pinctrl_gpio_range *range;
592 struct stm32_gpio_bank *bank;
596 ret = stm32_pctrl_is_function_valid(pctl, g->pin, function);
598 dev_err(pctl->dev, "invalid function %d on group %d .\n",
603 range = pinctrl_find_gpio_range_from_pin(pctldev, g->pin);
604 bank = gpiochip_get_data(range->gc);
605 pin = stm32_gpio_pin(g->pin);
607 mode = stm32_gpio_get_mode(function);
608 alt = stm32_gpio_get_alt(function);
610 stm32_pmx_set_mode(bank, pin, mode, alt);
615 static int stm32_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
616 struct pinctrl_gpio_range *range, unsigned gpio,
619 struct stm32_gpio_bank *bank = gpiochip_get_data(range->gc);
620 int pin = stm32_gpio_pin(gpio);
622 stm32_pmx_set_mode(bank, pin, !input, 0);
627 static const struct pinmux_ops stm32_pmx_ops = {
628 .get_functions_count = stm32_pmx_get_funcs_cnt,
629 .get_function_name = stm32_pmx_get_func_name,
630 .get_function_groups = stm32_pmx_get_func_groups,
631 .set_mux = stm32_pmx_set_mux,
632 .gpio_set_direction = stm32_pmx_gpio_set_direction,
636 /* Pinconf functions */
638 static void stm32_pconf_set_driving(struct stm32_gpio_bank *bank,
639 unsigned offset, u32 drive)
644 clk_enable(bank->clk);
645 spin_lock_irqsave(&bank->lock, flags);
647 val = readl_relaxed(bank->base + STM32_GPIO_TYPER);
649 val |= drive << offset;
650 writel_relaxed(val, bank->base + STM32_GPIO_TYPER);
652 spin_unlock_irqrestore(&bank->lock, flags);
653 clk_disable(bank->clk);
656 static u32 stm32_pconf_get_driving(struct stm32_gpio_bank *bank,
662 clk_enable(bank->clk);
663 spin_lock_irqsave(&bank->lock, flags);
665 val = readl_relaxed(bank->base + STM32_GPIO_TYPER);
668 spin_unlock_irqrestore(&bank->lock, flags);
669 clk_disable(bank->clk);
671 return (val >> offset);
674 static void stm32_pconf_set_speed(struct stm32_gpio_bank *bank,
675 unsigned offset, u32 speed)
680 clk_enable(bank->clk);
681 spin_lock_irqsave(&bank->lock, flags);
683 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);
684 val &= ~GENMASK(offset * 2 + 1, offset * 2);
685 val |= speed << (offset * 2);
686 writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR);
688 spin_unlock_irqrestore(&bank->lock, flags);
689 clk_disable(bank->clk);
692 static u32 stm32_pconf_get_speed(struct stm32_gpio_bank *bank,
698 clk_enable(bank->clk);
699 spin_lock_irqsave(&bank->lock, flags);
701 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);
702 val &= GENMASK(offset * 2 + 1, offset * 2);
704 spin_unlock_irqrestore(&bank->lock, flags);
705 clk_disable(bank->clk);
707 return (val >> (offset * 2));
710 static void stm32_pconf_set_bias(struct stm32_gpio_bank *bank,
711 unsigned offset, u32 bias)
716 clk_enable(bank->clk);
717 spin_lock_irqsave(&bank->lock, flags);
719 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);
720 val &= ~GENMASK(offset * 2 + 1, offset * 2);
721 val |= bias << (offset * 2);
722 writel_relaxed(val, bank->base + STM32_GPIO_PUPDR);
724 spin_unlock_irqrestore(&bank->lock, flags);
725 clk_disable(bank->clk);
728 static u32 stm32_pconf_get_bias(struct stm32_gpio_bank *bank,
734 clk_enable(bank->clk);
735 spin_lock_irqsave(&bank->lock, flags);
737 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);
738 val &= GENMASK(offset * 2 + 1, offset * 2);
740 spin_unlock_irqrestore(&bank->lock, flags);
741 clk_disable(bank->clk);
743 return (val >> (offset * 2));
746 static bool stm32_pconf_get(struct stm32_gpio_bank *bank,
747 unsigned int offset, bool dir)
752 clk_enable(bank->clk);
753 spin_lock_irqsave(&bank->lock, flags);
756 val = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) &
759 val = !!(readl_relaxed(bank->base + STM32_GPIO_ODR) &
762 spin_unlock_irqrestore(&bank->lock, flags);
763 clk_disable(bank->clk);
768 static int stm32_pconf_parse_conf(struct pinctrl_dev *pctldev,
769 unsigned int pin, enum pin_config_param param,
770 enum pin_config_param arg)
772 struct pinctrl_gpio_range *range;
773 struct stm32_gpio_bank *bank;
776 range = pinctrl_find_gpio_range_from_pin(pctldev, pin);
777 bank = gpiochip_get_data(range->gc);
778 offset = stm32_gpio_pin(pin);
781 case PIN_CONFIG_DRIVE_PUSH_PULL:
782 stm32_pconf_set_driving(bank, offset, 0);
784 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
785 stm32_pconf_set_driving(bank, offset, 1);
787 case PIN_CONFIG_SLEW_RATE:
788 stm32_pconf_set_speed(bank, offset, arg);
790 case PIN_CONFIG_BIAS_DISABLE:
791 stm32_pconf_set_bias(bank, offset, 0);
793 case PIN_CONFIG_BIAS_PULL_UP:
794 stm32_pconf_set_bias(bank, offset, 1);
796 case PIN_CONFIG_BIAS_PULL_DOWN:
797 stm32_pconf_set_bias(bank, offset, 2);
799 case PIN_CONFIG_OUTPUT:
800 __stm32_gpio_set(bank, offset, arg);
801 ret = stm32_pmx_gpio_set_direction(pctldev, NULL, pin, false);
810 static int stm32_pconf_group_get(struct pinctrl_dev *pctldev,
812 unsigned long *config)
814 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
816 *config = pctl->groups[group].config;
821 static int stm32_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
822 unsigned long *configs, unsigned num_configs)
824 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
825 struct stm32_pinctrl_group *g = &pctl->groups[group];
828 for (i = 0; i < num_configs; i++) {
829 ret = stm32_pconf_parse_conf(pctldev, g->pin,
830 pinconf_to_config_param(configs[i]),
831 pinconf_to_config_argument(configs[i]));
835 g->config = configs[i];
841 static void stm32_pconf_dbg_show(struct pinctrl_dev *pctldev,
845 struct pinctrl_gpio_range *range;
846 struct stm32_gpio_bank *bank;
848 u32 mode, alt, drive, speed, bias;
849 static const char * const modes[] = {
850 "input", "output", "alternate", "analog" };
851 static const char * const speeds[] = {
852 "low", "medium", "high", "very high" };
853 static const char * const biasing[] = {
854 "floating", "pull up", "pull down", "" };
857 range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin);
858 bank = gpiochip_get_data(range->gc);
859 offset = stm32_gpio_pin(pin);
861 stm32_pmx_get_mode(bank, offset, &mode, &alt);
862 bias = stm32_pconf_get_bias(bank, offset);
864 seq_printf(s, "%s ", modes[mode]);
869 val = stm32_pconf_get(bank, offset, true);
870 seq_printf(s, "- %s - %s",
871 val ? "high" : "low",
877 drive = stm32_pconf_get_driving(bank, offset);
878 speed = stm32_pconf_get_speed(bank, offset);
879 val = stm32_pconf_get(bank, offset, false);
880 seq_printf(s, "- %s - %s - %s - %s %s",
881 val ? "high" : "low",
882 drive ? "open drain" : "push pull",
884 speeds[speed], "speed");
889 drive = stm32_pconf_get_driving(bank, offset);
890 speed = stm32_pconf_get_speed(bank, offset);
891 seq_printf(s, "%d - %s - %s - %s %s", alt,
892 drive ? "open drain" : "push pull",
894 speeds[speed], "speed");
904 static const struct pinconf_ops stm32_pconf_ops = {
905 .pin_config_group_get = stm32_pconf_group_get,
906 .pin_config_group_set = stm32_pconf_group_set,
907 .pin_config_dbg_show = stm32_pconf_dbg_show,
910 static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl,
911 struct device_node *np)
913 struct stm32_gpio_bank *bank = &pctl->banks[pctl->nbanks];
914 struct pinctrl_gpio_range *range = &bank->range;
915 struct of_phandle_args args;
916 struct device *dev = pctl->dev;
918 struct reset_control *rstc;
919 int npins = STM32_GPIO_PINS_PER_BANK;
922 rstc = of_reset_control_get(np, NULL);
924 reset_control_deassert(rstc);
926 if (of_address_to_resource(np, 0, &res))
929 bank->base = devm_ioremap_resource(dev, &res);
930 if (IS_ERR(bank->base))
931 return PTR_ERR(bank->base);
933 bank->clk = of_clk_get_by_name(np, NULL);
934 if (IS_ERR(bank->clk)) {
935 dev_err(dev, "failed to get clk (%ld)\n", PTR_ERR(bank->clk));
936 return PTR_ERR(bank->clk);
939 err = clk_prepare(bank->clk);
941 dev_err(dev, "failed to prepare clk (%d)\n", err);
945 bank->gpio_chip = stm32_gpio_template;
947 of_property_read_string(np, "st,bank-name", &bank->gpio_chip.label);
949 if (!of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args)) {
950 bank_nr = args.args[1] / STM32_GPIO_PINS_PER_BANK;
951 bank->gpio_chip.base = args.args[1];
953 bank_nr = pctl->nbanks;
954 bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK;
955 range->name = bank->gpio_chip.label;
957 range->pin_base = range->id * STM32_GPIO_PINS_PER_BANK;
958 range->base = range->id * STM32_GPIO_PINS_PER_BANK;
959 range->npins = npins;
960 range->gc = &bank->gpio_chip;
961 pinctrl_add_gpio_range(pctl->pctl_dev,
962 &pctl->banks[bank_nr].range);
964 bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK;
966 bank->gpio_chip.ngpio = npins;
967 bank->gpio_chip.of_node = np;
968 bank->gpio_chip.parent = dev;
969 bank->bank_nr = bank_nr;
970 spin_lock_init(&bank->lock);
972 /* create irq hierarchical domain */
973 bank->fwnode = of_node_to_fwnode(np);
975 bank->domain = irq_domain_create_hierarchy(pctl->domain, 0,
976 STM32_GPIO_IRQ_LINE, bank->fwnode,
977 &stm32_gpio_domain_ops, bank);
982 err = gpiochip_add_data(&bank->gpio_chip, bank);
984 dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_nr);
988 dev_info(dev, "%s bank added\n", bank->gpio_chip.label);
992 static int stm32_pctrl_dt_setup_irq(struct platform_device *pdev,
993 struct stm32_pinctrl *pctl)
995 struct device_node *np = pdev->dev.of_node, *parent;
996 struct device *dev = &pdev->dev;
1000 parent = of_irq_find_parent(np);
1004 pctl->domain = irq_find_host(parent);
1008 pctl->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
1009 if (IS_ERR(pctl->regmap))
1010 return PTR_ERR(pctl->regmap);
1014 ret = of_property_read_u32_index(np, "st,syscfg", 1, &offset);
1018 for (i = 0; i < STM32_GPIO_PINS_PER_BANK; i++) {
1019 struct reg_field mux;
1021 mux.reg = offset + (i / 4) * 4;
1022 mux.lsb = (i % 4) * 4;
1023 mux.msb = mux.lsb + 3;
1025 pctl->irqmux[i] = devm_regmap_field_alloc(dev, rm, mux);
1026 if (IS_ERR(pctl->irqmux[i]))
1027 return PTR_ERR(pctl->irqmux[i]);
1033 static int stm32_pctrl_build_state(struct platform_device *pdev)
1035 struct stm32_pinctrl *pctl = platform_get_drvdata(pdev);
1038 pctl->ngroups = pctl->match_data->npins;
1040 /* Allocate groups */
1041 pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups,
1042 sizeof(*pctl->groups), GFP_KERNEL);
1046 /* We assume that one pin is one group, use pin name as group name. */
1047 pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups,
1048 sizeof(*pctl->grp_names), GFP_KERNEL);
1049 if (!pctl->grp_names)
1052 for (i = 0; i < pctl->match_data->npins; i++) {
1053 const struct stm32_desc_pin *pin = pctl->match_data->pins + i;
1054 struct stm32_pinctrl_group *group = pctl->groups + i;
1056 group->name = pin->pin.name;
1057 group->pin = pin->pin.number;
1059 pctl->grp_names[i] = pin->pin.name;
1065 int stm32_pctl_probe(struct platform_device *pdev)
1067 struct device_node *np = pdev->dev.of_node;
1068 struct device_node *child;
1069 const struct of_device_id *match;
1070 struct device *dev = &pdev->dev;
1071 struct stm32_pinctrl *pctl;
1072 struct pinctrl_pin_desc *pins;
1073 int i, ret, banks = 0;
1078 match = of_match_device(dev->driver->of_match_table, dev);
1079 if (!match || !match->data)
1082 if (!of_find_property(np, "pins-are-numbered", NULL)) {
1083 dev_err(dev, "only support pins-are-numbered format\n");
1087 pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL);
1091 platform_set_drvdata(pdev, pctl);
1094 pctl->match_data = match->data;
1095 ret = stm32_pctrl_build_state(pdev);
1097 dev_err(dev, "build state failed: %d\n", ret);
1101 if (of_find_property(np, "interrupt-parent", NULL)) {
1102 ret = stm32_pctrl_dt_setup_irq(pdev, pctl);
1107 pins = devm_kcalloc(&pdev->dev, pctl->match_data->npins, sizeof(*pins),
1112 for (i = 0; i < pctl->match_data->npins; i++)
1113 pins[i] = pctl->match_data->pins[i].pin;
1115 pctl->pctl_desc.name = dev_name(&pdev->dev);
1116 pctl->pctl_desc.owner = THIS_MODULE;
1117 pctl->pctl_desc.pins = pins;
1118 pctl->pctl_desc.npins = pctl->match_data->npins;
1119 pctl->pctl_desc.confops = &stm32_pconf_ops;
1120 pctl->pctl_desc.pctlops = &stm32_pctrl_ops;
1121 pctl->pctl_desc.pmxops = &stm32_pmx_ops;
1122 pctl->dev = &pdev->dev;
1124 pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, &pctl->pctl_desc,
1127 if (IS_ERR(pctl->pctl_dev)) {
1128 dev_err(&pdev->dev, "Failed pinctrl registration\n");
1129 return PTR_ERR(pctl->pctl_dev);
1132 for_each_child_of_node(np, child)
1133 if (of_property_read_bool(child, "gpio-controller"))
1137 dev_err(dev, "at least one GPIO bank is required\n");
1140 pctl->banks = devm_kcalloc(dev, banks, sizeof(*pctl->banks),
1145 for_each_child_of_node(np, child) {
1146 if (of_property_read_bool(child, "gpio-controller")) {
1147 ret = stm32_gpiolib_register_bank(pctl, child);
1155 dev_info(dev, "Pinctrl STM32 initialized\n");