drivers/pinctrl/sunxi/pinctrl-sunxi.c

   1 /*
   2  * Allwinner A1X SoCs pinctrl driver.
   3  *
   4  * Copyright (C) 2012 Maxime Ripard
   5  *
   6  * Maxime Ripard <maxime.ripard@free-electrons.com>
   7  *
   8  * This file is licensed under the terms of the GNU General Public
   9  * License version 2.  This program is licensed "as is" without any
  10  * warranty of any kind, whether express or implied.
  11  */
  12
  13 #include <linux/io.h>
  14 #include <linux/clk.h>
  15 #include <linux/gpio.h>
  16 #include <linux/irqdomain.h>
  17 #include <linux/irqchip/chained_irq.h>
  18 #include <linux/module.h>
  19 #include <linux/of.h>
  20 #include <linux/of_address.h>
  21 #include <linux/of_device.h>
  22 #include <linux/of_irq.h>
  23 #include <linux/pinctrl/consumer.h>
  24 #include <linux/pinctrl/machine.h>
  25 #include <linux/pinctrl/pinctrl.h>
  26 #include <linux/pinctrl/pinconf-generic.h>
  27 #include <linux/pinctrl/pinmux.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/reset.h>
  30 #include <linux/slab.h>
  31
  32 #include "../core.h"
  33 #include "pinctrl-sunxi.h"
  34 #include "pinctrl-sunxi-pins.h"
  35
  36 static struct sunxi_pinctrl_group *
  37 sunxi_pinctrl_find_group_by_name(struct sunxi_pinctrl *pctl, const char *group)
  38 {
  39         int i;
  40
  41         for (i = 0; i < pctl->ngroups; i++) {
  42                 struct sunxi_pinctrl_group *grp = pctl->groups + i;
  43
  44                 if (!strcmp(grp->name, group))
  45                         return grp;
  46         }
  47
  48         return NULL;
  49 }
  50
  51 static struct sunxi_pinctrl_function *
  52 sunxi_pinctrl_find_function_by_name(struct sunxi_pinctrl *pctl,
  53                                     const char *name)
  54 {
  55         struct sunxi_pinctrl_function *func = pctl->functions;
  56         int i;
  57
  58         for (i = 0; i < pctl->nfunctions; i++) {
  59                 if (!func[i].name)
  60                         break;
  61
  62                 if (!strcmp(func[i].name, name))
  63                         return func + i;
  64         }
  65
  66         return NULL;
  67 }
  68
  69 static struct sunxi_desc_function *
  70 sunxi_pinctrl_desc_find_function_by_name(struct sunxi_pinctrl *pctl,
  71                                          const char *pin_name,
  72                                          const char *func_name)
  73 {
  74         int i;
  75
  76         for (i = 0; i < pctl->desc->npins; i++) {
  77                 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
  78
  79                 if (!strcmp(pin->pin.name, pin_name)) {
  80                         struct sunxi_desc_function *func = pin->functions;
  81
  82                         while (func->name) {
  83                                 if (!strcmp(func->name, func_name))
  84                                         return func;
  85
  86                                 func++;
  87                         }
  88                 }
  89         }
  90
  91         return NULL;
  92 }
  93
  94 static struct sunxi_desc_function *
  95 sunxi_pinctrl_desc_find_function_by_pin(struct sunxi_pinctrl *pctl,
  96                                         const u16 pin_num,
  97                                         const char *func_name)
  98 {
  99         int i;
 100
 101         for (i = 0; i < pctl->desc->npins; i++) {
 102                 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
 103
 104                 if (pin->pin.number == pin_num) {
 105                         struct sunxi_desc_function *func = pin->functions;
 106
 107                         while (func->name) {
 108                                 if (!strcmp(func->name, func_name))
 109                                         return func;
 110
 111                                 func++;
 112                         }
 113                 }
 114         }
 115
 116         return NULL;
 117 }
 118
 119 static int sunxi_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
 120 {
 121         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 122
 123         return pctl->ngroups;
 124 }
 125
 126 static const char *sunxi_pctrl_get_group_name(struct pinctrl_dev *pctldev,
 127                                               unsigned group)
 128 {
 129         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 130
 131         return pctl->groups[group].name;
 132 }
 133
 134 static int sunxi_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
 135                                       unsigned group,
 136                                       const unsigned **pins,
 137                                       unsigned *num_pins)
 138 {
 139         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 140
 141         *pins = (unsigned *)&pctl->groups[group].pin;
 142         *num_pins = 1;
 143
 144         return 0;
 145 }
 146
 147 static int sunxi_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
 148                                       struct device_node *node,
 149                                       struct pinctrl_map **map,
 150                                       unsigned *num_maps)
 151 {
 152         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 153         unsigned long *pinconfig;
 154         struct property *prop;
 155         const char *function;
 156         const char *group;
 157         int ret, nmaps, i = 0;
 158         u32 val;
 159
 160         *map = NULL;
 161         *num_maps = 0;
 162
 163         ret = of_property_read_string(node, "allwinner,function", &function);
 164         if (ret) {
 165                 dev_err(pctl->dev,
 166                         "missing allwinner,function property in node %s\n",
 167                         node->name);
 168                 return -EINVAL;
 169         }
 170
 171         nmaps = of_property_count_strings(node, "allwinner,pins") * 2;
 172         if (nmaps < 0) {
 173                 dev_err(pctl->dev,
 174                         "missing allwinner,pins property in node %s\n",
 175                         node->name);
 176                 return -EINVAL;
 177         }
 178
 179         *map = kmalloc(nmaps * sizeof(struct pinctrl_map), GFP_KERNEL);
 180         if (!*map)
 181                 return -ENOMEM;
 182
 183         of_property_for_each_string(node, "allwinner,pins", prop, group) {
 184                 struct sunxi_pinctrl_group *grp =
 185                         sunxi_pinctrl_find_group_by_name(pctl, group);
 186                 int j = 0, configlen = 0;
 187
 188                 if (!grp) {
 189                         dev_err(pctl->dev, "unknown pin %s", group);
 190                         continue;
 191                 }
 192
 193                 if (!sunxi_pinctrl_desc_find_function_by_name(pctl,
 194                                                               grp->name,
 195                                                               function)) {
 196                         dev_err(pctl->dev, "unsupported function %s on pin %s",
 197                                 function, group);
 198                         continue;
 199                 }
 200
 201                 (*map)[i].type = PIN_MAP_TYPE_MUX_GROUP;
 202                 (*map)[i].data.mux.group = group;
 203                 (*map)[i].data.mux.function = function;
 204
 205                 i++;
 206
 207                 (*map)[i].type = PIN_MAP_TYPE_CONFIGS_GROUP;
 208                 (*map)[i].data.configs.group_or_pin = group;
 209
 210                 if (of_find_property(node, "allwinner,drive", NULL))
 211                         configlen++;
 212                 if (of_find_property(node, "allwinner,pull", NULL))
 213                         configlen++;
 214
 215                 pinconfig = kzalloc(configlen * sizeof(*pinconfig), GFP_KERNEL);
 216
 217                 if (!of_property_read_u32(node, "allwinner,drive", &val)) {
 218                         u16 strength = (val + 1) * 10;
 219                         pinconfig[j++] =
 220                                 pinconf_to_config_packed(PIN_CONFIG_DRIVE_STRENGTH,
 221                                                          strength);
 222                 }
 223
 224                 if (!of_property_read_u32(node, "allwinner,pull", &val)) {
 225                         enum pin_config_param pull = PIN_CONFIG_END;
 226                         if (val == 1)
 227                                 pull = PIN_CONFIG_BIAS_PULL_UP;
 228                         else if (val == 2)
 229                                 pull = PIN_CONFIG_BIAS_PULL_DOWN;
 230                         pinconfig[j++] = pinconf_to_config_packed(pull, 0);
 231                 }
 232
 233                 (*map)[i].data.configs.configs = pinconfig;
 234                 (*map)[i].data.configs.num_configs = configlen;
 235
 236                 i++;
 237         }
 238
 239         *num_maps = nmaps;
 240
 241         return 0;
 242 }
 243
 244 static void sunxi_pctrl_dt_free_map(struct pinctrl_dev *pctldev,
 245                                     struct pinctrl_map *map,
 246                                     unsigned num_maps)
 247 {
 248         int i;
 249
 250         for (i = 0; i < num_maps; i++) {
 251                 if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
 252                         kfree(map[i].data.configs.configs);
 253         }
 254
 255         kfree(map);
 256 }
 257
 258 static const struct pinctrl_ops sunxi_pctrl_ops = {
 259         .dt_node_to_map         = sunxi_pctrl_dt_node_to_map,
 260         .dt_free_map            = sunxi_pctrl_dt_free_map,
 261         .get_groups_count       = sunxi_pctrl_get_groups_count,
 262         .get_group_name         = sunxi_pctrl_get_group_name,
 263         .get_group_pins         = sunxi_pctrl_get_group_pins,
 264 };
 265
 266 static int sunxi_pconf_group_get(struct pinctrl_dev *pctldev,
 267                                  unsigned group,
 268                                  unsigned long *config)
 269 {
 270         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 271
 272         *config = pctl->groups[group].config;
 273
 274         return 0;
 275 }
 276
 277 static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev,
 278                                  unsigned group,
 279                                  unsigned long *configs,
 280                                  unsigned num_configs)
 281 {
 282         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 283         struct sunxi_pinctrl_group *g = &pctl->groups[group];
 284         unsigned long flags;
 285         u32 val, mask;
 286         u16 strength;
 287         u8 dlevel;
 288         int i;
 289
 290         spin_lock_irqsave(&pctl->lock, flags);
 291
 292         for (i = 0; i < num_configs; i++) {
 293                 switch (pinconf_to_config_param(configs[i])) {
 294                 case PIN_CONFIG_DRIVE_STRENGTH:
 295                         strength = pinconf_to_config_argument(configs[i]);
 296                         if (strength > 40) {
 297                                 spin_unlock_irqrestore(&pctl->lock, flags);
 298                                 return -EINVAL;
 299                         }
 300                         /*
 301                          * We convert from mA to what the register expects:
 302                          *   0: 10mA
 303                          *   1: 20mA
 304                          *   2: 30mA
 305                          *   3: 40mA
 306                          */
 307                         dlevel = strength / 10 - 1;
 308                         val = readl(pctl->membase + sunxi_dlevel_reg(g->pin));
 309                         mask = DLEVEL_PINS_MASK << sunxi_dlevel_offset(g->pin);
 310                         writel((val & ~mask)
 311                                 | dlevel << sunxi_dlevel_offset(g->pin),
 312                                 pctl->membase + sunxi_dlevel_reg(g->pin));
 313                         break;
 314                 case PIN_CONFIG_BIAS_PULL_UP:
 315                         val = readl(pctl->membase + sunxi_pull_reg(g->pin));
 316                         mask = PULL_PINS_MASK << sunxi_pull_offset(g->pin);
 317                         writel((val & ~mask) | 1 << sunxi_pull_offset(g->pin),
 318                                 pctl->membase + sunxi_pull_reg(g->pin));
 319                         break;
 320                 case PIN_CONFIG_BIAS_PULL_DOWN:
 321                         val = readl(pctl->membase + sunxi_pull_reg(g->pin));
 322                         mask = PULL_PINS_MASK << sunxi_pull_offset(g->pin);
 323                         writel((val & ~mask) | 2 << sunxi_pull_offset(g->pin),
 324                                 pctl->membase + sunxi_pull_reg(g->pin));
 325                         break;
 326                 default:
 327                         break;
 328                 }
 329                 /* cache the config value */
 330                 g->config = configs[i];
 331         } /* for each config */
 332
 333         spin_unlock_irqrestore(&pctl->lock, flags);
 334
 335         return 0;
 336 }
 337
 338 static const struct pinconf_ops sunxi_pconf_ops = {
 339         .pin_config_group_get   = sunxi_pconf_group_get,
 340         .pin_config_group_set   = sunxi_pconf_group_set,
 341 };
 342
 343 static int sunxi_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
 344 {
 345         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 346
 347         return pctl->nfunctions;
 348 }
 349
 350 static const char *sunxi_pmx_get_func_name(struct pinctrl_dev *pctldev,
 351                                            unsigned function)
 352 {
 353         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 354
 355         return pctl->functions[function].name;
 356 }
 357
 358 static int sunxi_pmx_get_func_groups(struct pinctrl_dev *pctldev,
 359                                      unsigned function,
 360                                      const char * const **groups,
 361                                      unsigned * const num_groups)
 362 {
 363         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 364
 365         *groups = pctl->functions[function].groups;
 366         *num_groups = pctl->functions[function].ngroups;
 367
 368         return 0;
 369 }
 370
 371 static void sunxi_pmx_set(struct pinctrl_dev *pctldev,
 372                                  unsigned pin,
 373                                  u8 config)
 374 {
 375         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 376         unsigned long flags;
 377         u32 val, mask;
 378
 379         spin_lock_irqsave(&pctl->lock, flags);
 380
 381         val = readl(pctl->membase + sunxi_mux_reg(pin));
 382         mask = MUX_PINS_MASK << sunxi_mux_offset(pin);
 383         writel((val & ~mask) | config << sunxi_mux_offset(pin),
 384                 pctl->membase + sunxi_mux_reg(pin));
 385
 386         spin_unlock_irqrestore(&pctl->lock, flags);
 387 }
 388
 389 static int sunxi_pmx_enable(struct pinctrl_dev *pctldev,
 390                             unsigned function,
 391                             unsigned group)
 392 {
 393         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 394         struct sunxi_pinctrl_group *g = pctl->groups + group;
 395         struct sunxi_pinctrl_function *func = pctl->functions + function;
 396         struct sunxi_desc_function *desc =
 397                 sunxi_pinctrl_desc_find_function_by_name(pctl,
 398                                                          g->name,
 399                                                          func->name);
 400
 401         if (!desc)
 402                 return -EINVAL;
 403
 404         sunxi_pmx_set(pctldev, g->pin, desc->muxval);
 405
 406         return 0;
 407 }
 408
 409 static int
 410 sunxi_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
 411                         struct pinctrl_gpio_range *range,
 412                         unsigned offset,
 413                         bool input)
 414 {
 415         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 416         struct sunxi_desc_function *desc;
 417         const char *func;
 418
 419         if (input)
 420                 func = "gpio_in";
 421         else
 422                 func = "gpio_out";
 423
 424         desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, func);
 425         if (!desc)
 426                 return -EINVAL;
 427
 428         sunxi_pmx_set(pctldev, offset, desc->muxval);
 429
 430         return 0;
 431 }
 432
 433 static const struct pinmux_ops sunxi_pmx_ops = {
 434         .get_functions_count    = sunxi_pmx_get_funcs_cnt,
 435         .get_function_name      = sunxi_pmx_get_func_name,
 436         .get_function_groups    = sunxi_pmx_get_func_groups,
 437         .enable                 = sunxi_pmx_enable,
 438         .gpio_set_direction     = sunxi_pmx_gpio_set_direction,
 439 };
 440
 441 static struct pinctrl_desc sunxi_pctrl_desc = {
 442         .confops        = &sunxi_pconf_ops,
 443         .pctlops        = &sunxi_pctrl_ops,
 444         .pmxops         = &sunxi_pmx_ops,
 445 };
 446
 447 static int sunxi_pinctrl_gpio_request(struct gpio_chip *chip, unsigned offset)
 448 {
 449         return pinctrl_request_gpio(chip->base + offset);
 450 }
 451
 452 static void sunxi_pinctrl_gpio_free(struct gpio_chip *chip, unsigned offset)
 453 {
 454         pinctrl_free_gpio(chip->base + offset);
 455 }
 456
 457 static int sunxi_pinctrl_gpio_direction_input(struct gpio_chip *chip,
 458                                         unsigned offset)
 459 {
 460         return pinctrl_gpio_direction_input(chip->base + offset);
 461 }
 462
 463 static int sunxi_pinctrl_gpio_get(struct gpio_chip *chip, unsigned offset)
 464 {
 465         struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev);
 466
 467         u32 reg = sunxi_data_reg(offset);
 468         u8 index = sunxi_data_offset(offset);
 469         u32 val = (readl(pctl->membase + reg) >> index) & DATA_PINS_MASK;
 470
 471         return val;
 472 }
 473
 474 static void sunxi_pinctrl_gpio_set(struct gpio_chip *chip,
 475                                 unsigned offset, int value)
 476 {
 477         struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev);
 478         u32 reg = sunxi_data_reg(offset);
 479         u8 index = sunxi_data_offset(offset);
 480         unsigned long flags;
 481         u32 regval;
 482
 483         spin_lock_irqsave(&pctl->lock, flags);
 484
 485         regval = readl(pctl->membase + reg);
 486
 487         if (value)
 488                 regval |= BIT(index);
 489         else
 490                 regval &= ~(BIT(index));
 491
 492         writel(regval, pctl->membase + reg);
 493
 494         spin_unlock_irqrestore(&pctl->lock, flags);
 495 }
 496
 497 static int sunxi_pinctrl_gpio_direction_output(struct gpio_chip *chip,
 498                                         unsigned offset, int value)
 499 {
 500         sunxi_pinctrl_gpio_set(chip, offset, value);
 501         return pinctrl_gpio_direction_output(chip->base + offset);
 502 }
 503
 504 static int sunxi_pinctrl_gpio_of_xlate(struct gpio_chip *gc,
 505                                 const struct of_phandle_args *gpiospec,
 506                                 u32 *flags)
 507 {
 508         int pin, base;
 509
 510         base = PINS_PER_BANK * gpiospec->args[0];
 511         pin = base + gpiospec->args[1];
 512
 513         if (pin > (gc->base + gc->ngpio))
 514                 return -EINVAL;
 515
 516         if (flags)
 517                 *flags = gpiospec->args[2];
 518
 519         return pin;
 520 }
 521
 522 static int sunxi_pinctrl_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
 523 {
 524         struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev);
 525         struct sunxi_desc_function *desc;
 526
 527         if (offset >= chip->ngpio)
 528                 return -ENXIO;
 529
 530         desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, "irq");
 531         if (!desc)
 532                 return -EINVAL;
 533
 534         pctl->irq_array[desc->irqnum] = offset;
 535
 536         dev_dbg(chip->dev, "%s: request IRQ for GPIO %d, return %d\n",
 537                 chip->label, offset + chip->base, desc->irqnum);
 538
 539         return irq_find_mapping(pctl->domain, desc->irqnum);
 540 }
 541
 542
 543 static int sunxi_pinctrl_irq_set_type(struct irq_data *d,
 544                                       unsigned int type)
 545 {
 546         struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
 547         u32 reg = sunxi_irq_cfg_reg(d->hwirq);
 548         u8 index = sunxi_irq_cfg_offset(d->hwirq);
 549         unsigned long flags;
 550         u32 regval;
 551         u8 mode;
 552
 553         switch (type) {
 554         case IRQ_TYPE_EDGE_RISING:
 555                 mode = IRQ_EDGE_RISING;
 556                 break;
 557         case IRQ_TYPE_EDGE_FALLING:
 558                 mode = IRQ_EDGE_FALLING;
 559                 break;
 560         case IRQ_TYPE_EDGE_BOTH:
 561                 mode = IRQ_EDGE_BOTH;
 562                 break;
 563         case IRQ_TYPE_LEVEL_HIGH:
 564                 mode = IRQ_LEVEL_HIGH;
 565                 break;
 566         case IRQ_TYPE_LEVEL_LOW:
 567                 mode = IRQ_LEVEL_LOW;
 568                 break;
 569         default:
 570                 return -EINVAL;
 571         }
 572
 573         spin_lock_irqsave(&pctl->lock, flags);
 574
 575         regval = readl(pctl->membase + reg);
 576         regval &= ~(IRQ_CFG_IRQ_MASK << index);
 577         writel(regval | (mode << index), pctl->membase + reg);
 578
 579         spin_unlock_irqrestore(&pctl->lock, flags);
 580
 581         return 0;
 582 }
 583
 584 static void sunxi_pinctrl_irq_mask_ack(struct irq_data *d)
 585 {
 586         struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
 587         u32 ctrl_reg = sunxi_irq_ctrl_reg(d->hwirq);
 588         u8 ctrl_idx = sunxi_irq_ctrl_offset(d->hwirq);
 589         u32 status_reg = sunxi_irq_status_reg(d->hwirq);
 590         u8 status_idx = sunxi_irq_status_offset(d->hwirq);
 591         unsigned long flags;
 592         u32 val;
 593
 594         spin_lock_irqsave(&pctl->lock, flags);
 595
 596         /* Mask the IRQ */
 597         val = readl(pctl->membase + ctrl_reg);
 598         writel(val & ~(1 << ctrl_idx), pctl->membase + ctrl_reg);
 599
 600         /* Clear the IRQ */
 601         writel(1 << status_idx, pctl->membase + status_reg);
 602
 603         spin_unlock_irqrestore(&pctl->lock, flags);
 604 }
 605
 606 static void sunxi_pinctrl_irq_mask(struct irq_data *d)
 607 {
 608         struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
 609         u32 reg = sunxi_irq_ctrl_reg(d->hwirq);
 610         u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
 611         unsigned long flags;
 612         u32 val;
 613
 614         spin_lock_irqsave(&pctl->lock, flags);
 615
 616         /* Mask the IRQ */
 617         val = readl(pctl->membase + reg);
 618         writel(val & ~(1 << idx), pctl->membase + reg);
 619
 620         spin_unlock_irqrestore(&pctl->lock, flags);
 621 }
 622
 623 static void sunxi_pinctrl_irq_unmask(struct irq_data *d)
 624 {
 625         struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
 626         struct sunxi_desc_function *func;
 627         u32 reg = sunxi_irq_ctrl_reg(d->hwirq);
 628         u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
 629         unsigned long flags;
 630         u32 val;
 631
 632         func = sunxi_pinctrl_desc_find_function_by_pin(pctl,
 633                                                        pctl->irq_array[d->hwirq],
 634                                                        "irq");
 635
 636         /* Change muxing to INT mode */
 637         sunxi_pmx_set(pctl->pctl_dev, pctl->irq_array[d->hwirq], func->muxval);
 638
 639         spin_lock_irqsave(&pctl->lock, flags);
 640
 641         /* Unmask the IRQ */
 642         val = readl(pctl->membase + reg);
 643         writel(val | (1 << idx), pctl->membase + reg);
 644
 645         spin_unlock_irqrestore(&pctl->lock, flags);
 646 }
 647
 648 static struct irq_chip sunxi_pinctrl_irq_chip = {
 649         .irq_mask       = sunxi_pinctrl_irq_mask,
 650         .irq_mask_ack   = sunxi_pinctrl_irq_mask_ack,
 651         .irq_unmask     = sunxi_pinctrl_irq_unmask,
 652         .irq_set_type   = sunxi_pinctrl_irq_set_type,
 653 };
 654
 655 static void sunxi_pinctrl_irq_handler(unsigned irq, struct irq_desc *desc)
 656 {
 657         struct irq_chip *chip = irq_get_chip(irq);
 658         struct sunxi_pinctrl *pctl = irq_get_handler_data(irq);
 659         const unsigned long reg = readl(pctl->membase + IRQ_STATUS_REG);
 660
 661         /* Clear all interrupts */
 662         writel(reg, pctl->membase + IRQ_STATUS_REG);
 663
 664         if (reg) {
 665                 int irqoffset;
 666
 667                 chained_irq_enter(chip, desc);
 668                 for_each_set_bit(irqoffset, &reg, SUNXI_IRQ_NUMBER) {
 669                         int pin_irq = irq_find_mapping(pctl->domain, irqoffset);
 670                         generic_handle_irq(pin_irq);
 671                 }
 672                 chained_irq_exit(chip, desc);
 673         }
 674 }
 675
 676 static struct of_device_id sunxi_pinctrl_match[] = {
 677         { .compatible = "allwinner,sun5i-a10s-pinctrl", .data = (void *)&sun5i_a10s_pinctrl_data },
 678         { .compatible = "allwinner,sun5i-a13-pinctrl", .data = (void *)&sun5i_a13_pinctrl_data },
 679         { .compatible = "allwinner,sun6i-a31-pinctrl", .data = (void *)&sun6i_a31_pinctrl_data },
 680         { .compatible = "allwinner,sun6i-a31-r-pinctrl", .data = (void *)&sun6i_a31_r_pinctrl_data },
 681         { .compatible = "allwinner,sun7i-a20-pinctrl", .data = (void *)&sun7i_a20_pinctrl_data },
 682         {}
 683 };
 684 MODULE_DEVICE_TABLE(of, sunxi_pinctrl_match);
 685
 686 static int sunxi_pinctrl_add_function(struct sunxi_pinctrl *pctl,
 687                                         const char *name)
 688 {
 689         struct sunxi_pinctrl_function *func = pctl->functions;
 690
 691         while (func->name) {
 692                 /* function already there */
 693                 if (strcmp(func->name, name) == 0) {
 694                         func->ngroups++;
 695                         return -EEXIST;
 696                 }
 697                 func++;
 698         }
 699
 700         func->name = name;
 701         func->ngroups = 1;
 702
 703         pctl->nfunctions++;
 704
 705         return 0;
 706 }
 707
 708 static int sunxi_pinctrl_build_state(struct platform_device *pdev)
 709 {
 710         struct sunxi_pinctrl *pctl = platform_get_drvdata(pdev);
 711         int i;
 712
 713         pctl->ngroups = pctl->desc->npins;
 714
 715         /* Allocate groups */
 716         pctl->groups = devm_kzalloc(&pdev->dev,
 717                                     pctl->ngroups * sizeof(*pctl->groups),
 718                                     GFP_KERNEL);
 719         if (!pctl->groups)
 720                 return -ENOMEM;
 721
 722         for (i = 0; i < pctl->desc->npins; i++) {
 723                 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
 724                 struct sunxi_pinctrl_group *group = pctl->groups + i;
 725
 726                 group->name = pin->pin.name;
 727                 group->pin = pin->pin.number;
 728         }
 729
 730         /*
 731          * We suppose that we won't have any more functions than pins,
 732          * we'll reallocate that later anyway
 733          */
 734         pctl->functions = devm_kzalloc(&pdev->dev,
 735                                 pctl->desc->npins * sizeof(*pctl->functions),
 736                                 GFP_KERNEL);
 737         if (!pctl->functions)
 738                 return -ENOMEM;
 739
 740         /* Count functions and their associated groups */
 741         for (i = 0; i < pctl->desc->npins; i++) {
 742                 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
 743                 struct sunxi_desc_function *func = pin->functions;
 744
 745                 while (func->name) {
 746                         sunxi_pinctrl_add_function(pctl, func->name);
 747                         func++;
 748                 }
 749         }
 750
 751         pctl->functions = krealloc(pctl->functions,
 752                                 pctl->nfunctions * sizeof(*pctl->functions),
 753                                 GFP_KERNEL);
 754
 755         for (i = 0; i < pctl->desc->npins; i++) {
 756                 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
 757                 struct sunxi_desc_function *func = pin->functions;
 758
 759                 while (func->name) {
 760                         struct sunxi_pinctrl_function *func_item;
 761                         const char **func_grp;
 762
 763                         func_item = sunxi_pinctrl_find_function_by_name(pctl,
 764                                                                         func->name);
 765                         if (!func_item)
 766                                 return -EINVAL;
 767
 768                         if (!func_item->groups) {
 769                                 func_item->groups =
 770                                         devm_kzalloc(&pdev->dev,
 771                                                      func_item->ngroups * sizeof(*func_item->groups),
 772                                                      GFP_KERNEL);
 773                                 if (!func_item->groups)
 774                                         return -ENOMEM;
 775                         }
 776
 777                         func_grp = func_item->groups;
 778                         while (*func_grp)
 779                                 func_grp++;
 780
 781                         *func_grp = pin->pin.name;
 782                         func++;
 783                 }
 784         }
 785
 786         return 0;
 787 }
 788
 789 int sunxi_pinctrl_init(struct platform_device *pdev,
 790                        const struct sunxi_pinctrl_desc *desc)
 791 {
 792         struct device_node *node = pdev->dev.of_node;
 793         struct pinctrl_pin_desc *pins;
 794         struct sunxi_pinctrl *pctl;
 795         struct reset_control *rstc;
 796         struct resource *res;
 797         int i, ret, last_pin;
 798         struct clk *clk;
 799
 800         pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
 801         if (!pctl)
 802                 return -ENOMEM;
 803         platform_set_drvdata(pdev, pctl);
 804
 805         spin_lock_init(&pctl->lock);
 806
 807         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 808         pctl->membase = devm_ioremap_resource(&pdev->dev, res);
 809         if (IS_ERR(pctl->membase))
 810                 return PTR_ERR(pctl->membase);
 811
 812         pctl->desc = desc;
 813
 814         ret = sunxi_pinctrl_build_state(pdev);
 815         if (ret) {
 816                 dev_err(&pdev->dev, "dt probe failed: %d\n", ret);
 817                 return ret;
 818         }
 819
 820         pins = devm_kzalloc(&pdev->dev,
 821                             pctl->desc->npins * sizeof(*pins),
 822                             GFP_KERNEL);
 823         if (!pins)
 824                 return -ENOMEM;
 825
 826         for (i = 0; i < pctl->desc->npins; i++)
 827                 pins[i] = pctl->desc->pins[i].pin;
 828
 829         sunxi_pctrl_desc.name = dev_name(&pdev->dev);
 830         sunxi_pctrl_desc.owner = THIS_MODULE;
 831         sunxi_pctrl_desc.pins = pins;
 832         sunxi_pctrl_desc.npins = pctl->desc->npins;
 833         pctl->dev = &pdev->dev;
 834         pctl->pctl_dev = pinctrl_register(&sunxi_pctrl_desc,
 835                                           &pdev->dev, pctl);
 836         if (!pctl->pctl_dev) {
 837                 dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
 838                 return -EINVAL;
 839         }
 840
 841         pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL);
 842         if (!pctl->chip) {
 843                 ret = -ENOMEM;
 844                 goto pinctrl_error;
 845         }
 846
 847         last_pin = pctl->desc->pins[pctl->desc->npins - 1].pin.number;
 848         pctl->chip->owner = THIS_MODULE;
 849         pctl->chip->request = sunxi_pinctrl_gpio_request,
 850         pctl->chip->free = sunxi_pinctrl_gpio_free,
 851         pctl->chip->direction_input = sunxi_pinctrl_gpio_direction_input,
 852         pctl->chip->direction_output = sunxi_pinctrl_gpio_direction_output,
 853         pctl->chip->get = sunxi_pinctrl_gpio_get,
 854         pctl->chip->set = sunxi_pinctrl_gpio_set,
 855         pctl->chip->of_xlate = sunxi_pinctrl_gpio_of_xlate,
 856         pctl->chip->to_irq = sunxi_pinctrl_gpio_to_irq,
 857         pctl->chip->of_gpio_n_cells = 3,
 858         pctl->chip->can_sleep = false,
 859         pctl->chip->ngpio = round_up(last_pin, PINS_PER_BANK) -
 860                             pctl->desc->pin_base;
 861         pctl->chip->label = dev_name(&pdev->dev);
 862         pctl->chip->dev = &pdev->dev;
 863         pctl->chip->base = pctl->desc->pin_base;
 864
 865         ret = gpiochip_add(pctl->chip);
 866         if (ret)
 867                 goto pinctrl_error;
 868
 869         for (i = 0; i < pctl->desc->npins; i++) {
 870                 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
 871
 872                 ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev),
 873                                              pin->pin.number,
 874                                              pin->pin.number, 1);
 875                 if (ret)
 876                         goto gpiochip_error;
 877         }
 878
 879         clk = devm_clk_get(&pdev->dev, NULL);
 880         if (IS_ERR(clk)) {
 881                 ret = PTR_ERR(clk);
 882                 goto gpiochip_error;
 883         }
 884
 885         ret = clk_prepare_enable(clk);
 886         if (ret)
 887                 goto gpiochip_error;
 888
 889         rstc = devm_reset_control_get_optional(&pdev->dev, NULL);
 890         if (!IS_ERR(rstc)) {
 891                 ret = reset_control_deassert(rstc);
 892                 if (ret)
 893                         goto clk_error;
 894         }
 895
 896         pctl->irq = irq_of_parse_and_map(node, 0);
 897         if (!pctl->irq) {
 898                 ret = -EINVAL;
 899                 goto rstc_error;
 900         }
 901
 902         pctl->domain = irq_domain_add_linear(node, SUNXI_IRQ_NUMBER,
 903                                              &irq_domain_simple_ops, NULL);
 904         if (!pctl->domain) {
 905                 dev_err(&pdev->dev, "Couldn't register IRQ domain\n");
 906                 ret = -ENOMEM;
 907                 goto rstc_error;
 908         }
 909
 910         for (i = 0; i < SUNXI_IRQ_NUMBER; i++) {
 911                 int irqno = irq_create_mapping(pctl->domain, i);
 912
 913                 irq_set_chip_and_handler(irqno, &sunxi_pinctrl_irq_chip,
 914                                          handle_simple_irq);
 915                 irq_set_chip_data(irqno, pctl);
 916         };
 917
 918         irq_set_chained_handler(pctl->irq, sunxi_pinctrl_irq_handler);
 919         irq_set_handler_data(pctl->irq, pctl);
 920
 921         dev_info(&pdev->dev, "initialized sunXi PIO driver\n");
 922
 923         return 0;
 924
 925 rstc_error:
 926         if (!IS_ERR(rstc))
 927                 reset_control_assert(rstc);
 928 clk_error:
 929         clk_disable_unprepare(clk);
 930 gpiochip_error:
 931         if (gpiochip_remove(pctl->chip))
 932                 dev_err(&pdev->dev, "failed to remove gpio chip\n");
 933 pinctrl_error:
 934         pinctrl_unregister(pctl->pctl_dev);
 935         return ret;
 936 }
 937
 938 static int sunxi_pinctrl_probe(struct platform_device *pdev)
 939 {
 940         const struct of_device_id *device;
 941
 942         device = of_match_device(sunxi_pinctrl_match, &pdev->dev);
 943         if (!device)
 944                 return -ENODEV;
 945
 946         return sunxi_pinctrl_init(pdev, device->data);
 947 }
 948
 949 static struct platform_driver sunxi_pinctrl_driver = {
 950         .probe = sunxi_pinctrl_probe,
 951         .driver = {
 952                 .name = "sunxi-pinctrl",
 953                 .owner = THIS_MODULE,
 954                 .of_match_table = sunxi_pinctrl_match,
 955         },
 956 };
 957 module_platform_driver(sunxi_pinctrl_driver);
 958
 959 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
 960 MODULE_DESCRIPTION("Allwinner A1X pinctrl driver");
 961 MODULE_LICENSE("GPL");