2 * Allwinner A1X SoCs pinctrl driver.
4 * Copyright (C) 2012 Maxime Ripard
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
14 #include <linux/clk.h>
15 #include <linux/gpio/driver.h>
16 #include <linux/irqdomain.h>
17 #include <linux/irqchip/chained_irq.h>
18 #include <linux/export.h>
20 #include <linux/of_address.h>
21 #include <linux/of_device.h>
22 #include <linux/of_irq.h>
23 #include <linux/pinctrl/consumer.h>
24 #include <linux/pinctrl/machine.h>
25 #include <linux/pinctrl/pinctrl.h>
26 #include <linux/pinctrl/pinconf-generic.h>
27 #include <linux/pinctrl/pinmux.h>
28 #include <linux/platform_device.h>
29 #include <linux/slab.h>
31 #include <dt-bindings/pinctrl/sun4i-a10.h>
34 #include "pinctrl-sunxi.h"
36 static struct irq_chip sunxi_pinctrl_edge_irq_chip;
37 static struct irq_chip sunxi_pinctrl_level_irq_chip;
39 static struct sunxi_pinctrl_group *
40 sunxi_pinctrl_find_group_by_name(struct sunxi_pinctrl *pctl, const char *group)
44 for (i = 0; i < pctl->ngroups; i++) {
45 struct sunxi_pinctrl_group *grp = pctl->groups + i;
47 if (!strcmp(grp->name, group))
54 static struct sunxi_pinctrl_function *
55 sunxi_pinctrl_find_function_by_name(struct sunxi_pinctrl *pctl,
58 struct sunxi_pinctrl_function *func = pctl->functions;
61 for (i = 0; i < pctl->nfunctions; i++) {
65 if (!strcmp(func[i].name, name))
72 static struct sunxi_desc_function *
73 sunxi_pinctrl_desc_find_function_by_name(struct sunxi_pinctrl *pctl,
75 const char *func_name)
79 for (i = 0; i < pctl->desc->npins; i++) {
80 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
82 if (!strcmp(pin->pin.name, pin_name)) {
83 struct sunxi_desc_function *func = pin->functions;
86 if (!strcmp(func->name, func_name))
97 static struct sunxi_desc_function *
98 sunxi_pinctrl_desc_find_function_by_pin(struct sunxi_pinctrl *pctl,
100 const char *func_name)
104 for (i = 0; i < pctl->desc->npins; i++) {
105 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
107 if (pin->pin.number == pin_num) {
108 struct sunxi_desc_function *func = pin->functions;
111 if (!strcmp(func->name, func_name))
122 static int sunxi_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
124 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
126 return pctl->ngroups;
129 static const char *sunxi_pctrl_get_group_name(struct pinctrl_dev *pctldev,
132 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
134 return pctl->groups[group].name;
137 static int sunxi_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
139 const unsigned **pins,
142 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
144 *pins = (unsigned *)&pctl->groups[group].pin;
150 static bool sunxi_pctrl_has_bias_prop(struct device_node *node)
152 return of_find_property(node, "bias-pull-up", NULL) ||
153 of_find_property(node, "bias-pull-down", NULL) ||
154 of_find_property(node, "bias-disable", NULL) ||
155 of_find_property(node, "allwinner,pull", NULL);
158 static bool sunxi_pctrl_has_drive_prop(struct device_node *node)
160 return of_find_property(node, "drive-strength", NULL) ||
161 of_find_property(node, "allwinner,drive", NULL);
164 static int sunxi_pctrl_parse_bias_prop(struct device_node *node)
168 /* Try the new style binding */
169 if (of_find_property(node, "bias-pull-up", NULL))
170 return PIN_CONFIG_BIAS_PULL_UP;
172 if (of_find_property(node, "bias-pull-down", NULL))
173 return PIN_CONFIG_BIAS_PULL_DOWN;
175 if (of_find_property(node, "bias-disable", NULL))
176 return PIN_CONFIG_BIAS_DISABLE;
178 /* And fall back to the old binding */
179 if (of_property_read_u32(node, "allwinner,pull", &val))
183 case SUN4I_PINCTRL_NO_PULL:
184 return PIN_CONFIG_BIAS_DISABLE;
185 case SUN4I_PINCTRL_PULL_UP:
186 return PIN_CONFIG_BIAS_PULL_UP;
187 case SUN4I_PINCTRL_PULL_DOWN:
188 return PIN_CONFIG_BIAS_PULL_DOWN;
194 static int sunxi_pctrl_parse_drive_prop(struct device_node *node)
198 /* Try the new style binding */
199 if (!of_property_read_u32(node, "drive-strength", &val)) {
200 /* We can't go below 10mA ... */
204 /* ... and only up to 40 mA ... */
208 /* by steps of 10 mA */
209 return rounddown(val, 10);
212 /* And then fall back to the old binding */
213 if (of_property_read_u32(node, "allwinner,drive", &val))
216 return (val + 1) * 10;
219 static const char *sunxi_pctrl_parse_function_prop(struct device_node *node)
221 const char *function;
224 /* Try the generic binding */
225 ret = of_property_read_string(node, "function", &function);
229 /* And fall back to our legacy one */
230 ret = of_property_read_string(node, "allwinner,function", &function);
237 static const char *sunxi_pctrl_find_pins_prop(struct device_node *node,
242 /* Try the generic binding */
243 count = of_property_count_strings(node, "pins");
249 /* And fall back to our legacy one */
250 count = of_property_count_strings(node, "allwinner,pins");
253 return "allwinner,pins";
259 static unsigned long *sunxi_pctrl_build_pin_config(struct device_node *node,
262 unsigned long *pinconfig;
263 unsigned int configlen = 0, idx = 0;
266 if (sunxi_pctrl_has_drive_prop(node))
268 if (sunxi_pctrl_has_bias_prop(node))
272 * If we don't have any configuration, bail out
277 pinconfig = kzalloc(configlen * sizeof(*pinconfig), GFP_KERNEL);
279 return ERR_PTR(-ENOMEM);
281 if (sunxi_pctrl_has_drive_prop(node)) {
282 int drive = sunxi_pctrl_parse_drive_prop(node);
288 pinconfig[idx++] = pinconf_to_config_packed(PIN_CONFIG_DRIVE_STRENGTH,
292 if (sunxi_pctrl_has_bias_prop(node)) {
293 int pull = sunxi_pctrl_parse_bias_prop(node);
300 if (pull != PIN_CONFIG_BIAS_DISABLE)
301 arg = 1; /* hardware uses weak pull resistors */
303 pinconfig[idx++] = pinconf_to_config_packed(pull, arg);
315 static int sunxi_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
316 struct device_node *node,
317 struct pinctrl_map **map,
320 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
321 unsigned long *pinconfig;
322 struct property *prop;
323 const char *function, *pin_prop;
325 int ret, npins, nmaps, configlen = 0, i = 0;
330 function = sunxi_pctrl_parse_function_prop(node);
332 dev_err(pctl->dev, "missing function property in node %s\n",
337 pin_prop = sunxi_pctrl_find_pins_prop(node, &npins);
339 dev_err(pctl->dev, "missing pins property in node %s\n",
345 * We have two maps for each pin: one for the function, one
346 * for the configuration (bias, strength, etc).
348 * We might be slightly overshooting, since we might not have
352 *map = kmalloc(nmaps * sizeof(struct pinctrl_map), GFP_KERNEL);
356 pinconfig = sunxi_pctrl_build_pin_config(node, &configlen);
357 if (IS_ERR(pinconfig)) {
358 ret = PTR_ERR(pinconfig);
362 of_property_for_each_string(node, pin_prop, prop, group) {
363 struct sunxi_pinctrl_group *grp =
364 sunxi_pinctrl_find_group_by_name(pctl, group);
367 dev_err(pctl->dev, "unknown pin %s", group);
371 if (!sunxi_pinctrl_desc_find_function_by_name(pctl,
374 dev_err(pctl->dev, "unsupported function %s on pin %s",
379 (*map)[i].type = PIN_MAP_TYPE_MUX_GROUP;
380 (*map)[i].data.mux.group = group;
381 (*map)[i].data.mux.function = function;
386 (*map)[i].type = PIN_MAP_TYPE_CONFIGS_GROUP;
387 (*map)[i].data.configs.group_or_pin = group;
388 (*map)[i].data.configs.configs = pinconfig;
389 (*map)[i].data.configs.num_configs = configlen;
397 * We know have the number of maps we need, we can resize our
400 *map = krealloc(*map, i * sizeof(struct pinctrl_map), GFP_KERNEL);
412 static void sunxi_pctrl_dt_free_map(struct pinctrl_dev *pctldev,
413 struct pinctrl_map *map,
418 /* pin config is never in the first map */
419 for (i = 1; i < num_maps; i++) {
420 if (map[i].type != PIN_MAP_TYPE_CONFIGS_GROUP)
424 * All the maps share the same pin config,
425 * free only the first one we find.
427 kfree(map[i].data.configs.configs);
434 static const struct pinctrl_ops sunxi_pctrl_ops = {
435 .dt_node_to_map = sunxi_pctrl_dt_node_to_map,
436 .dt_free_map = sunxi_pctrl_dt_free_map,
437 .get_groups_count = sunxi_pctrl_get_groups_count,
438 .get_group_name = sunxi_pctrl_get_group_name,
439 .get_group_pins = sunxi_pctrl_get_group_pins,
442 static int sunxi_pconf_reg(unsigned pin, enum pin_config_param param,
443 u32 *offset, u32 *shift, u32 *mask)
446 case PIN_CONFIG_DRIVE_STRENGTH:
447 *offset = sunxi_dlevel_reg(pin);
448 *shift = sunxi_dlevel_offset(pin);
449 *mask = DLEVEL_PINS_MASK;
452 case PIN_CONFIG_BIAS_PULL_UP:
453 case PIN_CONFIG_BIAS_PULL_DOWN:
454 case PIN_CONFIG_BIAS_DISABLE:
455 *offset = sunxi_pull_reg(pin);
456 *shift = sunxi_pull_offset(pin);
457 *mask = PULL_PINS_MASK;
467 static int sunxi_pconf_get(struct pinctrl_dev *pctldev, unsigned pin,
468 unsigned long *config)
470 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
471 enum pin_config_param param = pinconf_to_config_param(*config);
472 u32 offset, shift, mask, val;
476 pin -= pctl->desc->pin_base;
478 ret = sunxi_pconf_reg(pin, param, &offset, &shift, &mask);
482 val = (readl(pctl->membase + offset) >> shift) & mask;
484 switch (pinconf_to_config_param(*config)) {
485 case PIN_CONFIG_DRIVE_STRENGTH:
486 arg = (val + 1) * 10;
489 case PIN_CONFIG_BIAS_PULL_UP:
490 if (val != SUN4I_PINCTRL_PULL_UP)
492 arg = 1; /* hardware is weak pull-up */
495 case PIN_CONFIG_BIAS_PULL_DOWN:
496 if (val != SUN4I_PINCTRL_PULL_DOWN)
498 arg = 1; /* hardware is weak pull-down */
501 case PIN_CONFIG_BIAS_DISABLE:
502 if (val != SUN4I_PINCTRL_NO_PULL)
508 /* sunxi_pconf_reg should catch anything unsupported */
513 *config = pinconf_to_config_packed(param, arg);
518 static int sunxi_pconf_group_get(struct pinctrl_dev *pctldev,
520 unsigned long *config)
522 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
523 struct sunxi_pinctrl_group *g = &pctl->groups[group];
525 /* We only support 1 pin per group. Chain it to the pin callback */
526 return sunxi_pconf_get(pctldev, g->pin, config);
529 static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev,
531 unsigned long *configs,
532 unsigned num_configs)
534 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
535 struct sunxi_pinctrl_group *g = &pctl->groups[group];
536 unsigned pin = g->pin - pctl->desc->pin_base;
539 for (i = 0; i < num_configs; i++) {
540 enum pin_config_param param;
542 u32 offset, shift, mask, reg;
546 param = pinconf_to_config_param(configs[i]);
547 arg = pinconf_to_config_argument(configs[i]);
549 ret = sunxi_pconf_reg(pin, param, &offset, &shift, &mask);
554 case PIN_CONFIG_DRIVE_STRENGTH:
555 if (arg < 10 || arg > 40)
558 * We convert from mA to what the register expects:
566 case PIN_CONFIG_BIAS_DISABLE:
569 case PIN_CONFIG_BIAS_PULL_UP:
574 case PIN_CONFIG_BIAS_PULL_DOWN:
580 /* sunxi_pconf_reg should catch anything unsupported */
585 spin_lock_irqsave(&pctl->lock, flags);
586 reg = readl(pctl->membase + offset);
587 reg &= ~(mask << shift);
588 writel(reg | val << shift, pctl->membase + offset);
589 spin_unlock_irqrestore(&pctl->lock, flags);
590 } /* for each config */
595 static const struct pinconf_ops sunxi_pconf_ops = {
597 .pin_config_get = sunxi_pconf_get,
598 .pin_config_group_get = sunxi_pconf_group_get,
599 .pin_config_group_set = sunxi_pconf_group_set,
602 static int sunxi_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
604 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
606 return pctl->nfunctions;
609 static const char *sunxi_pmx_get_func_name(struct pinctrl_dev *pctldev,
612 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
614 return pctl->functions[function].name;
617 static int sunxi_pmx_get_func_groups(struct pinctrl_dev *pctldev,
619 const char * const **groups,
620 unsigned * const num_groups)
622 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
624 *groups = pctl->functions[function].groups;
625 *num_groups = pctl->functions[function].ngroups;
630 static void sunxi_pmx_set(struct pinctrl_dev *pctldev,
634 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
638 spin_lock_irqsave(&pctl->lock, flags);
640 pin -= pctl->desc->pin_base;
641 val = readl(pctl->membase + sunxi_mux_reg(pin));
642 mask = MUX_PINS_MASK << sunxi_mux_offset(pin);
643 writel((val & ~mask) | config << sunxi_mux_offset(pin),
644 pctl->membase + sunxi_mux_reg(pin));
646 spin_unlock_irqrestore(&pctl->lock, flags);
649 static int sunxi_pmx_set_mux(struct pinctrl_dev *pctldev,
653 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
654 struct sunxi_pinctrl_group *g = pctl->groups + group;
655 struct sunxi_pinctrl_function *func = pctl->functions + function;
656 struct sunxi_desc_function *desc =
657 sunxi_pinctrl_desc_find_function_by_name(pctl,
664 sunxi_pmx_set(pctldev, g->pin, desc->muxval);
670 sunxi_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
671 struct pinctrl_gpio_range *range,
675 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
676 struct sunxi_desc_function *desc;
684 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, func);
688 sunxi_pmx_set(pctldev, offset, desc->muxval);
693 static const struct pinmux_ops sunxi_pmx_ops = {
694 .get_functions_count = sunxi_pmx_get_funcs_cnt,
695 .get_function_name = sunxi_pmx_get_func_name,
696 .get_function_groups = sunxi_pmx_get_func_groups,
697 .set_mux = sunxi_pmx_set_mux,
698 .gpio_set_direction = sunxi_pmx_gpio_set_direction,
701 static int sunxi_pinctrl_gpio_direction_input(struct gpio_chip *chip,
704 return pinctrl_gpio_direction_input(chip->base + offset);
707 static int sunxi_pinctrl_gpio_get(struct gpio_chip *chip, unsigned offset)
709 struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
710 u32 reg = sunxi_data_reg(offset);
711 u8 index = sunxi_data_offset(offset);
712 bool set_mux = pctl->desc->irq_read_needs_mux &&
713 gpiochip_line_is_irq(chip, offset);
714 u32 pin = offset + chip->base;
718 sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_INPUT);
720 val = (readl(pctl->membase + reg) >> index) & DATA_PINS_MASK;
723 sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_IRQ);
728 static void sunxi_pinctrl_gpio_set(struct gpio_chip *chip,
729 unsigned offset, int value)
731 struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
732 u32 reg = sunxi_data_reg(offset);
733 u8 index = sunxi_data_offset(offset);
737 spin_lock_irqsave(&pctl->lock, flags);
739 regval = readl(pctl->membase + reg);
742 regval |= BIT(index);
744 regval &= ~(BIT(index));
746 writel(regval, pctl->membase + reg);
748 spin_unlock_irqrestore(&pctl->lock, flags);
751 static int sunxi_pinctrl_gpio_direction_output(struct gpio_chip *chip,
752 unsigned offset, int value)
754 sunxi_pinctrl_gpio_set(chip, offset, value);
755 return pinctrl_gpio_direction_output(chip->base + offset);
758 static int sunxi_pinctrl_gpio_of_xlate(struct gpio_chip *gc,
759 const struct of_phandle_args *gpiospec,
764 base = PINS_PER_BANK * gpiospec->args[0];
765 pin = base + gpiospec->args[1];
771 *flags = gpiospec->args[2];
776 static int sunxi_pinctrl_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
778 struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
779 struct sunxi_desc_function *desc;
780 unsigned pinnum = pctl->desc->pin_base + offset;
783 if (offset >= chip->ngpio)
786 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pinnum, "irq");
790 irqnum = desc->irqbank * IRQ_PER_BANK + desc->irqnum;
792 dev_dbg(chip->parent, "%s: request IRQ for GPIO %d, return %d\n",
793 chip->label, offset + chip->base, irqnum);
795 return irq_find_mapping(pctl->domain, irqnum);
798 static int sunxi_pinctrl_irq_request_resources(struct irq_data *d)
800 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
801 struct sunxi_desc_function *func;
804 func = sunxi_pinctrl_desc_find_function_by_pin(pctl,
805 pctl->irq_array[d->hwirq], "irq");
809 ret = gpiochip_lock_as_irq(pctl->chip,
810 pctl->irq_array[d->hwirq] - pctl->desc->pin_base);
812 dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n",
817 /* Change muxing to INT mode */
818 sunxi_pmx_set(pctl->pctl_dev, pctl->irq_array[d->hwirq], func->muxval);
823 static void sunxi_pinctrl_irq_release_resources(struct irq_data *d)
825 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
827 gpiochip_unlock_as_irq(pctl->chip,
828 pctl->irq_array[d->hwirq] - pctl->desc->pin_base);
831 static int sunxi_pinctrl_irq_set_type(struct irq_data *d, unsigned int type)
833 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
834 u32 reg = sunxi_irq_cfg_reg(d->hwirq, pctl->desc->irq_bank_base);
835 u8 index = sunxi_irq_cfg_offset(d->hwirq);
841 case IRQ_TYPE_EDGE_RISING:
842 mode = IRQ_EDGE_RISING;
844 case IRQ_TYPE_EDGE_FALLING:
845 mode = IRQ_EDGE_FALLING;
847 case IRQ_TYPE_EDGE_BOTH:
848 mode = IRQ_EDGE_BOTH;
850 case IRQ_TYPE_LEVEL_HIGH:
851 mode = IRQ_LEVEL_HIGH;
853 case IRQ_TYPE_LEVEL_LOW:
854 mode = IRQ_LEVEL_LOW;
860 spin_lock_irqsave(&pctl->lock, flags);
862 if (type & IRQ_TYPE_LEVEL_MASK)
863 irq_set_chip_handler_name_locked(d, &sunxi_pinctrl_level_irq_chip,
864 handle_fasteoi_irq, NULL);
866 irq_set_chip_handler_name_locked(d, &sunxi_pinctrl_edge_irq_chip,
867 handle_edge_irq, NULL);
869 regval = readl(pctl->membase + reg);
870 regval &= ~(IRQ_CFG_IRQ_MASK << index);
871 writel(regval | (mode << index), pctl->membase + reg);
873 spin_unlock_irqrestore(&pctl->lock, flags);
878 static void sunxi_pinctrl_irq_ack(struct irq_data *d)
880 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
881 u32 status_reg = sunxi_irq_status_reg(d->hwirq,
882 pctl->desc->irq_bank_base);
883 u8 status_idx = sunxi_irq_status_offset(d->hwirq);
886 writel(1 << status_idx, pctl->membase + status_reg);
889 static void sunxi_pinctrl_irq_mask(struct irq_data *d)
891 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
892 u32 reg = sunxi_irq_ctrl_reg(d->hwirq, pctl->desc->irq_bank_base);
893 u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
897 spin_lock_irqsave(&pctl->lock, flags);
900 val = readl(pctl->membase + reg);
901 writel(val & ~(1 << idx), pctl->membase + reg);
903 spin_unlock_irqrestore(&pctl->lock, flags);
906 static void sunxi_pinctrl_irq_unmask(struct irq_data *d)
908 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
909 u32 reg = sunxi_irq_ctrl_reg(d->hwirq, pctl->desc->irq_bank_base);
910 u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
914 spin_lock_irqsave(&pctl->lock, flags);
917 val = readl(pctl->membase + reg);
918 writel(val | (1 << idx), pctl->membase + reg);
920 spin_unlock_irqrestore(&pctl->lock, flags);
923 static void sunxi_pinctrl_irq_ack_unmask(struct irq_data *d)
925 sunxi_pinctrl_irq_ack(d);
926 sunxi_pinctrl_irq_unmask(d);
929 static struct irq_chip sunxi_pinctrl_edge_irq_chip = {
930 .name = "sunxi_pio_edge",
931 .irq_ack = sunxi_pinctrl_irq_ack,
932 .irq_mask = sunxi_pinctrl_irq_mask,
933 .irq_unmask = sunxi_pinctrl_irq_unmask,
934 .irq_request_resources = sunxi_pinctrl_irq_request_resources,
935 .irq_release_resources = sunxi_pinctrl_irq_release_resources,
936 .irq_set_type = sunxi_pinctrl_irq_set_type,
937 .flags = IRQCHIP_SKIP_SET_WAKE,
940 static struct irq_chip sunxi_pinctrl_level_irq_chip = {
941 .name = "sunxi_pio_level",
942 .irq_eoi = sunxi_pinctrl_irq_ack,
943 .irq_mask = sunxi_pinctrl_irq_mask,
944 .irq_unmask = sunxi_pinctrl_irq_unmask,
945 /* Define irq_enable / disable to avoid spurious irqs for drivers
946 * using these to suppress irqs while they clear the irq source */
947 .irq_enable = sunxi_pinctrl_irq_ack_unmask,
948 .irq_disable = sunxi_pinctrl_irq_mask,
949 .irq_request_resources = sunxi_pinctrl_irq_request_resources,
950 .irq_release_resources = sunxi_pinctrl_irq_release_resources,
951 .irq_set_type = sunxi_pinctrl_irq_set_type,
952 .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_EOI_THREADED |
953 IRQCHIP_EOI_IF_HANDLED,
956 static int sunxi_pinctrl_irq_of_xlate(struct irq_domain *d,
957 struct device_node *node,
959 unsigned int intsize,
960 unsigned long *out_hwirq,
961 unsigned int *out_type)
963 struct sunxi_pinctrl *pctl = d->host_data;
964 struct sunxi_desc_function *desc;
970 base = PINS_PER_BANK * intspec[0];
971 pin = pctl->desc->pin_base + base + intspec[1];
973 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pin, "irq");
977 *out_hwirq = desc->irqbank * PINS_PER_BANK + desc->irqnum;
978 *out_type = intspec[2];
983 static struct irq_domain_ops sunxi_pinctrl_irq_domain_ops = {
984 .xlate = sunxi_pinctrl_irq_of_xlate,
987 static void sunxi_pinctrl_irq_handler(struct irq_desc *desc)
989 unsigned int irq = irq_desc_get_irq(desc);
990 struct irq_chip *chip = irq_desc_get_chip(desc);
991 struct sunxi_pinctrl *pctl = irq_desc_get_handler_data(desc);
992 unsigned long bank, reg, val;
994 for (bank = 0; bank < pctl->desc->irq_banks; bank++)
995 if (irq == pctl->irq[bank])
998 if (bank == pctl->desc->irq_banks)
1001 reg = sunxi_irq_status_reg_from_bank(bank, pctl->desc->irq_bank_base);
1002 val = readl(pctl->membase + reg);
1007 chained_irq_enter(chip, desc);
1008 for_each_set_bit(irqoffset, &val, IRQ_PER_BANK) {
1009 int pin_irq = irq_find_mapping(pctl->domain,
1010 bank * IRQ_PER_BANK + irqoffset);
1011 generic_handle_irq(pin_irq);
1013 chained_irq_exit(chip, desc);
1017 static int sunxi_pinctrl_add_function(struct sunxi_pinctrl *pctl,
1020 struct sunxi_pinctrl_function *func = pctl->functions;
1022 while (func->name) {
1023 /* function already there */
1024 if (strcmp(func->name, name) == 0) {
1039 static int sunxi_pinctrl_build_state(struct platform_device *pdev)
1041 struct sunxi_pinctrl *pctl = platform_get_drvdata(pdev);
1047 * We assume that the number of groups is the number of pins
1048 * given in the data array.
1050 * This will not always be true, since some pins might not be
1051 * available in the current variant, but fortunately for us,
1052 * this means that the number of pins is the maximum group
1053 * number we will ever see.
1055 pctl->groups = devm_kzalloc(&pdev->dev,
1056 pctl->desc->npins * sizeof(*pctl->groups),
1061 for (i = 0; i < pctl->desc->npins; i++) {
1062 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1063 struct sunxi_pinctrl_group *group = pctl->groups + pctl->ngroups;
1065 if (pin->variant && !(pctl->variant & pin->variant))
1068 group->name = pin->pin.name;
1069 group->pin = pin->pin.number;
1071 /* And now we count the actual number of pins / groups */
1076 * We suppose that we won't have any more functions than pins,
1077 * we'll reallocate that later anyway
1079 pctl->functions = devm_kzalloc(&pdev->dev,
1080 pctl->ngroups * sizeof(*pctl->functions),
1082 if (!pctl->functions)
1085 /* Count functions and their associated groups */
1086 for (i = 0; i < pctl->desc->npins; i++) {
1087 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1088 struct sunxi_desc_function *func;
1090 if (pin->variant && !(pctl->variant & pin->variant))
1093 for (func = pin->functions; func->name; func++) {
1094 if (func->variant && !(pctl->variant & func->variant))
1097 /* Create interrupt mapping while we're at it */
1098 if (!strcmp(func->name, "irq")) {
1099 int irqnum = func->irqnum + func->irqbank * IRQ_PER_BANK;
1100 pctl->irq_array[irqnum] = pin->pin.number;
1103 sunxi_pinctrl_add_function(pctl, func->name);
1107 /* And now allocated and fill the array for real */
1108 pctl->functions = krealloc(pctl->functions,
1109 pctl->nfunctions * sizeof(*pctl->functions),
1111 if (!pctl->functions) {
1112 kfree(pctl->functions);
1116 for (i = 0; i < pctl->desc->npins; i++) {
1117 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1118 struct sunxi_desc_function *func;
1120 if (pin->variant && !(pctl->variant & pin->variant))
1123 for (func = pin->functions; func->name; func++) {
1124 struct sunxi_pinctrl_function *func_item;
1125 const char **func_grp;
1127 if (func->variant && !(pctl->variant & func->variant))
1130 func_item = sunxi_pinctrl_find_function_by_name(pctl,
1135 if (!func_item->groups) {
1137 devm_kzalloc(&pdev->dev,
1138 func_item->ngroups * sizeof(*func_item->groups),
1140 if (!func_item->groups)
1144 func_grp = func_item->groups;
1148 *func_grp = pin->pin.name;
1155 static int sunxi_pinctrl_get_debounce_div(struct clk *clk, int freq, int *diff)
1157 unsigned long clock = clk_get_rate(clk);
1158 unsigned int best_diff, best_div;
1161 best_diff = abs(freq - clock);
1164 for (i = 1; i < 8; i++) {
1165 int cur_diff = abs(freq - (clock >> i));
1167 if (cur_diff < best_diff) {
1168 best_diff = cur_diff;
1177 static int sunxi_pinctrl_setup_debounce(struct sunxi_pinctrl *pctl,
1178 struct device_node *node)
1180 unsigned int hosc_diff, losc_diff;
1181 unsigned int hosc_div, losc_div;
1182 struct clk *hosc, *losc;
1186 /* Deal with old DTs that didn't have the oscillators */
1187 if (of_count_phandle_with_args(node, "clocks", "#clock-cells") != 3)
1190 /* If we don't have any setup, bail out */
1191 if (!of_find_property(node, "input-debounce", NULL))
1194 losc = devm_clk_get(pctl->dev, "losc");
1196 return PTR_ERR(losc);
1198 hosc = devm_clk_get(pctl->dev, "hosc");
1200 return PTR_ERR(hosc);
1202 for (i = 0; i < pctl->desc->irq_banks; i++) {
1203 unsigned long debounce_freq;
1206 ret = of_property_read_u32_index(node, "input-debounce",
1214 debounce_freq = DIV_ROUND_CLOSEST(USEC_PER_SEC, debounce);
1215 losc_div = sunxi_pinctrl_get_debounce_div(losc,
1219 hosc_div = sunxi_pinctrl_get_debounce_div(hosc,
1223 if (hosc_diff < losc_diff) {
1231 writel(src | div << 4,
1233 sunxi_irq_debounce_reg_from_bank(i,
1234 pctl->desc->irq_bank_base));
1240 int sunxi_pinctrl_init_with_variant(struct platform_device *pdev,
1241 const struct sunxi_pinctrl_desc *desc,
1242 unsigned long variant)
1244 struct device_node *node = pdev->dev.of_node;
1245 struct pinctrl_desc *pctrl_desc;
1246 struct pinctrl_pin_desc *pins;
1247 struct sunxi_pinctrl *pctl;
1248 struct resource *res;
1249 int i, ret, last_pin, pin_idx;
1252 pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
1255 platform_set_drvdata(pdev, pctl);
1257 spin_lock_init(&pctl->lock);
1259 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1260 pctl->membase = devm_ioremap_resource(&pdev->dev, res);
1261 if (IS_ERR(pctl->membase))
1262 return PTR_ERR(pctl->membase);
1264 pctl->dev = &pdev->dev;
1266 pctl->variant = variant;
1268 pctl->irq_array = devm_kcalloc(&pdev->dev,
1269 IRQ_PER_BANK * pctl->desc->irq_banks,
1270 sizeof(*pctl->irq_array),
1272 if (!pctl->irq_array)
1275 ret = sunxi_pinctrl_build_state(pdev);
1277 dev_err(&pdev->dev, "dt probe failed: %d\n", ret);
1281 pins = devm_kzalloc(&pdev->dev,
1282 pctl->desc->npins * sizeof(*pins),
1287 for (i = 0, pin_idx = 0; i < pctl->desc->npins; i++) {
1288 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1290 if (pin->variant && !(pctl->variant & pin->variant))
1293 pins[pin_idx++] = pin->pin;
1296 pctrl_desc = devm_kzalloc(&pdev->dev,
1297 sizeof(*pctrl_desc),
1302 pctrl_desc->name = dev_name(&pdev->dev);
1303 pctrl_desc->owner = THIS_MODULE;
1304 pctrl_desc->pins = pins;
1305 pctrl_desc->npins = pctl->ngroups;
1306 pctrl_desc->confops = &sunxi_pconf_ops;
1307 pctrl_desc->pctlops = &sunxi_pctrl_ops;
1308 pctrl_desc->pmxops = &sunxi_pmx_ops;
1310 pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, pctrl_desc, pctl);
1311 if (IS_ERR(pctl->pctl_dev)) {
1312 dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
1313 return PTR_ERR(pctl->pctl_dev);
1316 pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL);
1320 last_pin = pctl->desc->pins[pctl->desc->npins - 1].pin.number;
1321 pctl->chip->owner = THIS_MODULE;
1322 pctl->chip->request = gpiochip_generic_request,
1323 pctl->chip->free = gpiochip_generic_free,
1324 pctl->chip->direction_input = sunxi_pinctrl_gpio_direction_input,
1325 pctl->chip->direction_output = sunxi_pinctrl_gpio_direction_output,
1326 pctl->chip->get = sunxi_pinctrl_gpio_get,
1327 pctl->chip->set = sunxi_pinctrl_gpio_set,
1328 pctl->chip->of_xlate = sunxi_pinctrl_gpio_of_xlate,
1329 pctl->chip->to_irq = sunxi_pinctrl_gpio_to_irq,
1330 pctl->chip->of_gpio_n_cells = 3,
1331 pctl->chip->can_sleep = false,
1332 pctl->chip->ngpio = round_up(last_pin, PINS_PER_BANK) -
1333 pctl->desc->pin_base;
1334 pctl->chip->label = dev_name(&pdev->dev);
1335 pctl->chip->parent = &pdev->dev;
1336 pctl->chip->base = pctl->desc->pin_base;
1338 ret = gpiochip_add_data(pctl->chip, pctl);
1342 for (i = 0; i < pctl->desc->npins; i++) {
1343 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1345 ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev),
1346 pin->pin.number - pctl->desc->pin_base,
1347 pin->pin.number, 1);
1349 goto gpiochip_error;
1352 clk = devm_clk_get(&pdev->dev, NULL);
1355 goto gpiochip_error;
1358 ret = clk_prepare_enable(clk);
1360 goto gpiochip_error;
1362 pctl->irq = devm_kcalloc(&pdev->dev,
1363 pctl->desc->irq_banks,
1371 for (i = 0; i < pctl->desc->irq_banks; i++) {
1372 pctl->irq[i] = platform_get_irq(pdev, i);
1373 if (pctl->irq[i] < 0) {
1379 pctl->domain = irq_domain_add_linear(node,
1380 pctl->desc->irq_banks * IRQ_PER_BANK,
1381 &sunxi_pinctrl_irq_domain_ops,
1383 if (!pctl->domain) {
1384 dev_err(&pdev->dev, "Couldn't register IRQ domain\n");
1389 for (i = 0; i < (pctl->desc->irq_banks * IRQ_PER_BANK); i++) {
1390 int irqno = irq_create_mapping(pctl->domain, i);
1392 irq_set_chip_and_handler(irqno, &sunxi_pinctrl_edge_irq_chip,
1394 irq_set_chip_data(irqno, pctl);
1397 for (i = 0; i < pctl->desc->irq_banks; i++) {
1398 /* Mask and clear all IRQs before registering a handler */
1399 writel(0, pctl->membase + sunxi_irq_ctrl_reg_from_bank(i,
1400 pctl->desc->irq_bank_base));
1402 pctl->membase + sunxi_irq_status_reg_from_bank(i,
1403 pctl->desc->irq_bank_base));
1405 irq_set_chained_handler_and_data(pctl->irq[i],
1406 sunxi_pinctrl_irq_handler,
1410 sunxi_pinctrl_setup_debounce(pctl, node);
1412 dev_info(&pdev->dev, "initialized sunXi PIO driver\n");
1417 clk_disable_unprepare(clk);
1419 gpiochip_remove(pctl->chip);