2 * Allwinner A1X SoCs pinctrl driver.
4 * Copyright (C) 2012 Maxime Ripard
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
13 #ifndef __PINCTRL_SUNXI_H
14 #define __PINCTRL_SUNXI_H
16 #include <linux/kernel.h>
17 #include <linux/spinlock.h>
31 #define SUNXI_PINCTRL_PIN(bank, pin) \
32 PINCTRL_PIN(P ## bank ## _BASE + (pin), "P" #bank #pin)
34 #define SUNXI_PIN_NAME_MAX_LEN 5
36 #define BANK_MEM_SIZE 0x24
37 #define MUX_REGS_OFFSET 0x0
38 #define DATA_REGS_OFFSET 0x10
39 #define DLEVEL_REGS_OFFSET 0x14
40 #define PULL_REGS_OFFSET 0x1c
42 #define PINS_PER_BANK 32
43 #define MUX_PINS_PER_REG 8
44 #define MUX_PINS_BITS 4
45 #define MUX_PINS_MASK 0x0f
46 #define DATA_PINS_PER_REG 32
47 #define DATA_PINS_BITS 1
48 #define DATA_PINS_MASK 0x01
49 #define DLEVEL_PINS_PER_REG 16
50 #define DLEVEL_PINS_BITS 2
51 #define DLEVEL_PINS_MASK 0x03
52 #define PULL_PINS_PER_REG 16
53 #define PULL_PINS_BITS 2
54 #define PULL_PINS_MASK 0x03
56 #define IRQ_PER_BANK 32
58 #define IRQ_CFG_REG 0x200
59 #define IRQ_CFG_IRQ_PER_REG 8
60 #define IRQ_CFG_IRQ_BITS 4
61 #define IRQ_CFG_IRQ_MASK ((1 << IRQ_CFG_IRQ_BITS) - 1)
62 #define IRQ_CTRL_REG 0x210
63 #define IRQ_CTRL_IRQ_PER_REG 32
64 #define IRQ_CTRL_IRQ_BITS 1
65 #define IRQ_CTRL_IRQ_MASK ((1 << IRQ_CTRL_IRQ_BITS) - 1)
66 #define IRQ_STATUS_REG 0x214
67 #define IRQ_STATUS_IRQ_PER_REG 32
68 #define IRQ_STATUS_IRQ_BITS 1
69 #define IRQ_STATUS_IRQ_MASK ((1 << IRQ_STATUS_IRQ_BITS) - 1)
71 #define IRQ_MEM_SIZE 0x20
73 #define IRQ_EDGE_RISING 0x00
74 #define IRQ_EDGE_FALLING 0x01
75 #define IRQ_LEVEL_HIGH 0x02
76 #define IRQ_LEVEL_LOW 0x03
77 #define IRQ_EDGE_BOTH 0x04
79 struct sunxi_desc_function {
86 struct sunxi_desc_pin {
87 struct pinctrl_pin_desc pin;
88 struct sunxi_desc_function *functions;
91 struct sunxi_pinctrl_desc {
92 const struct sunxi_desc_pin *pins;
98 struct sunxi_pinctrl_function {
104 struct sunxi_pinctrl_group {
106 unsigned long config;
110 struct sunxi_pinctrl {
111 void __iomem *membase;
112 struct gpio_chip *chip;
113 const struct sunxi_pinctrl_desc *desc;
115 struct irq_domain *domain;
116 struct sunxi_pinctrl_function *functions;
118 struct sunxi_pinctrl_group *groups;
123 struct pinctrl_dev *pctl_dev;
126 #define SUNXI_PIN(_pin, ...) \
129 .functions = (struct sunxi_desc_function[]){ \
130 __VA_ARGS__, { } }, \
133 #define SUNXI_FUNCTION(_val, _name) \
139 #define SUNXI_FUNCTION_IRQ(_val, _irq) \
146 #define SUNXI_FUNCTION_IRQ_BANK(_val, _bank, _irq) \
155 * The sunXi PIO registers are organized as is:
156 * 0x00 - 0x0c Muxing values.
157 * 8 pins per register, each pin having a 4bits value
159 * 32 bits per register, each pin corresponding to one bit
160 * 0x14 - 0x18 Drive level
161 * 16 pins per register, each pin having a 2bits value
162 * 0x1c - 0x20 Pull-Up values
163 * 16 pins per register, each pin having a 2bits value
165 * This is for the first bank. Each bank will have the same layout,
166 * with an offset being a multiple of 0x24.
168 * The following functions calculate from the pin number the register
169 * and the bit offset that we should access.
171 static inline u32 sunxi_mux_reg(u16 pin)
173 u8 bank = pin / PINS_PER_BANK;
174 u32 offset = bank * BANK_MEM_SIZE;
175 offset += MUX_REGS_OFFSET;
176 offset += pin % PINS_PER_BANK / MUX_PINS_PER_REG * 0x04;
177 return round_down(offset, 4);
180 static inline u32 sunxi_mux_offset(u16 pin)
182 u32 pin_num = pin % MUX_PINS_PER_REG;
183 return pin_num * MUX_PINS_BITS;
186 static inline u32 sunxi_data_reg(u16 pin)
188 u8 bank = pin / PINS_PER_BANK;
189 u32 offset = bank * BANK_MEM_SIZE;
190 offset += DATA_REGS_OFFSET;
191 offset += pin % PINS_PER_BANK / DATA_PINS_PER_REG * 0x04;
192 return round_down(offset, 4);
195 static inline u32 sunxi_data_offset(u16 pin)
197 u32 pin_num = pin % DATA_PINS_PER_REG;
198 return pin_num * DATA_PINS_BITS;
201 static inline u32 sunxi_dlevel_reg(u16 pin)
203 u8 bank = pin / PINS_PER_BANK;
204 u32 offset = bank * BANK_MEM_SIZE;
205 offset += DLEVEL_REGS_OFFSET;
206 offset += pin % PINS_PER_BANK / DLEVEL_PINS_PER_REG * 0x04;
207 return round_down(offset, 4);
210 static inline u32 sunxi_dlevel_offset(u16 pin)
212 u32 pin_num = pin % DLEVEL_PINS_PER_REG;
213 return pin_num * DLEVEL_PINS_BITS;
216 static inline u32 sunxi_pull_reg(u16 pin)
218 u8 bank = pin / PINS_PER_BANK;
219 u32 offset = bank * BANK_MEM_SIZE;
220 offset += PULL_REGS_OFFSET;
221 offset += pin % PINS_PER_BANK / PULL_PINS_PER_REG * 0x04;
222 return round_down(offset, 4);
225 static inline u32 sunxi_pull_offset(u16 pin)
227 u32 pin_num = pin % PULL_PINS_PER_REG;
228 return pin_num * PULL_PINS_BITS;
231 static inline u32 sunxi_irq_cfg_reg(u16 irq)
233 u8 bank = irq / IRQ_PER_BANK;
234 u8 reg = (irq % IRQ_PER_BANK) / IRQ_CFG_IRQ_PER_REG * 0x04;
236 return IRQ_CFG_REG + bank * IRQ_MEM_SIZE + reg;
239 static inline u32 sunxi_irq_cfg_offset(u16 irq)
241 u32 irq_num = irq % IRQ_CFG_IRQ_PER_REG;
242 return irq_num * IRQ_CFG_IRQ_BITS;
245 static inline u32 sunxi_irq_ctrl_reg_from_bank(u8 bank)
247 return IRQ_CTRL_REG + bank * IRQ_MEM_SIZE;
250 static inline u32 sunxi_irq_ctrl_reg(u16 irq)
252 u8 bank = irq / IRQ_PER_BANK;
254 return sunxi_irq_ctrl_reg_from_bank(bank);
257 static inline u32 sunxi_irq_ctrl_offset(u16 irq)
259 u32 irq_num = irq % IRQ_CTRL_IRQ_PER_REG;
260 return irq_num * IRQ_CTRL_IRQ_BITS;
263 static inline u32 sunxi_irq_status_reg_from_bank(u8 bank)
265 return IRQ_STATUS_REG + bank * IRQ_MEM_SIZE;
268 static inline u32 sunxi_irq_status_reg(u16 irq)
270 u8 bank = irq / IRQ_PER_BANK;
272 return sunxi_irq_status_reg_from_bank(bank);
275 static inline u32 sunxi_irq_status_offset(u16 irq)
277 u32 irq_num = irq % IRQ_STATUS_IRQ_PER_REG;
278 return irq_num * IRQ_STATUS_IRQ_BITS;
281 int sunxi_pinctrl_init(struct platform_device *pdev,
282 const struct sunxi_pinctrl_desc *desc);
284 #endif /* __PINCTRL_SUNXI_H */