2 * Intel Running Average Power Limit (RAPL) Driver
3 * Copyright (c) 2013, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.
18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/list.h>
23 #include <linux/types.h>
24 #include <linux/device.h>
25 #include <linux/slab.h>
26 #include <linux/log2.h>
27 #include <linux/bitmap.h>
28 #include <linux/delay.h>
29 #include <linux/sysfs.h>
30 #include <linux/cpu.h>
31 #include <linux/powercap.h>
32 #include <asm/iosf_mbi.h>
34 #include <asm/processor.h>
35 #include <asm/cpu_device_id.h>
38 #define MSR_PLATFORM_POWER_LIMIT 0x0000065C
40 /* bitmasks for RAPL MSRs, used by primitive access functions */
41 #define ENERGY_STATUS_MASK 0xffffffff
43 #define POWER_LIMIT1_MASK 0x7FFF
44 #define POWER_LIMIT1_ENABLE BIT(15)
45 #define POWER_LIMIT1_CLAMP BIT(16)
47 #define POWER_LIMIT2_MASK (0x7FFFULL<<32)
48 #define POWER_LIMIT2_ENABLE BIT_ULL(47)
49 #define POWER_LIMIT2_CLAMP BIT_ULL(48)
50 #define POWER_PACKAGE_LOCK BIT_ULL(63)
51 #define POWER_PP_LOCK BIT(31)
53 #define TIME_WINDOW1_MASK (0x7FULL<<17)
54 #define TIME_WINDOW2_MASK (0x7FULL<<49)
56 #define POWER_UNIT_OFFSET 0
57 #define POWER_UNIT_MASK 0x0F
59 #define ENERGY_UNIT_OFFSET 0x08
60 #define ENERGY_UNIT_MASK 0x1F00
62 #define TIME_UNIT_OFFSET 0x10
63 #define TIME_UNIT_MASK 0xF0000
65 #define POWER_INFO_MAX_MASK (0x7fffULL<<32)
66 #define POWER_INFO_MIN_MASK (0x7fffULL<<16)
67 #define POWER_INFO_MAX_TIME_WIN_MASK (0x3fULL<<48)
68 #define POWER_INFO_THERMAL_SPEC_MASK 0x7fff
70 #define PERF_STATUS_THROTTLE_TIME_MASK 0xffffffff
71 #define PP_POLICY_MASK 0x1F
73 /* Non HW constants */
74 #define RAPL_PRIMITIVE_DERIVED BIT(1) /* not from raw data */
75 #define RAPL_PRIMITIVE_DUMMY BIT(2)
77 #define TIME_WINDOW_MAX_MSEC 40000
78 #define TIME_WINDOW_MIN_MSEC 250
79 #define ENERGY_UNIT_SCALE 1000 /* scale from driver unit to powercap unit */
81 ARBITRARY_UNIT, /* no translation */
87 enum rapl_domain_type {
88 RAPL_DOMAIN_PACKAGE, /* entire package/socket */
89 RAPL_DOMAIN_PP0, /* core power plane */
90 RAPL_DOMAIN_PP1, /* graphics uncore */
91 RAPL_DOMAIN_DRAM,/* DRAM control_type */
92 RAPL_DOMAIN_PLATFORM, /* PSys control_type */
96 enum rapl_domain_msr_id {
97 RAPL_DOMAIN_MSR_LIMIT,
98 RAPL_DOMAIN_MSR_STATUS,
100 RAPL_DOMAIN_MSR_POLICY,
101 RAPL_DOMAIN_MSR_INFO,
105 /* per domain data, some are optional */
106 enum rapl_primitives {
112 PL1_ENABLE, /* power limit 1, aka long term */
113 PL1_CLAMP, /* allow frequency to go below OS request */
114 PL2_ENABLE, /* power limit 2, aka short term, instantaneous */
117 TIME_WINDOW1, /* long term */
118 TIME_WINDOW2, /* short term */
127 /* below are not raw primitive data */
132 #define NR_RAW_PRIMITIVES (NR_RAPL_PRIMITIVES - 2)
134 /* Can be expanded to include events, etc.*/
135 struct rapl_domain_data {
136 u64 primitives[NR_RAPL_PRIMITIVES];
137 unsigned long timestamp;
147 #define DOMAIN_STATE_INACTIVE BIT(0)
148 #define DOMAIN_STATE_POWER_LIMIT_SET BIT(1)
149 #define DOMAIN_STATE_BIOS_LOCKED BIT(2)
151 #define NR_POWER_LIMITS (2)
152 struct rapl_power_limit {
153 struct powercap_zone_constraint *constraint;
154 int prim_id; /* primitive ID used to enable */
155 struct rapl_domain *domain;
159 static const char pl1_name[] = "long_term";
160 static const char pl2_name[] = "short_term";
165 enum rapl_domain_type id;
166 int msrs[RAPL_DOMAIN_MSR_MAX];
167 struct powercap_zone power_zone;
168 struct rapl_domain_data rdd;
169 struct rapl_power_limit rpl[NR_POWER_LIMITS];
170 u64 attr_map; /* track capabilities */
172 unsigned int domain_energy_unit;
173 struct rapl_package *rp;
175 #define power_zone_to_rapl_domain(_zone) \
176 container_of(_zone, struct rapl_domain, power_zone)
179 /* Each physical package contains multiple domains, these are the common
180 * data across RAPL domains within a package.
182 struct rapl_package {
183 unsigned int id; /* physical package/socket id */
184 unsigned int nr_domains;
185 unsigned long domain_map; /* bit map of active domains */
186 unsigned int power_unit;
187 unsigned int energy_unit;
188 unsigned int time_unit;
189 struct rapl_domain *domains; /* array of domains, sized at runtime */
190 struct powercap_zone *power_zone; /* keep track of parent zone */
191 int nr_cpus; /* active cpus on the package, topology info is lost during
192 * cpu hotplug. so we have to track ourselves.
194 unsigned long power_limit_irq; /* keep track of package power limit
195 * notify interrupt enable status.
197 struct list_head plist;
198 int lead_cpu; /* one active cpu per package for access */
201 struct rapl_defaults {
202 u8 floor_freq_reg_addr;
203 int (*check_unit)(struct rapl_package *rp, int cpu);
204 void (*set_floor_freq)(struct rapl_domain *rd, bool mode);
205 u64 (*compute_time_window)(struct rapl_package *rp, u64 val,
207 unsigned int dram_domain_energy_unit;
209 static struct rapl_defaults *rapl_defaults;
211 /* Sideband MBI registers */
212 #define IOSF_CPU_POWER_BUDGET_CTL_BYT (0x2)
213 #define IOSF_CPU_POWER_BUDGET_CTL_TNG (0xdf)
215 #define PACKAGE_PLN_INT_SAVED BIT(0)
216 #define MAX_PRIM_NAME (32)
218 /* per domain data. used to describe individual knobs such that access function
219 * can be consolidated into one instead of many inline functions.
221 struct rapl_primitive_info {
225 enum rapl_domain_msr_id id;
230 #define PRIMITIVE_INFO_INIT(p, m, s, i, u, f) { \
239 static void rapl_init_domains(struct rapl_package *rp);
240 static int rapl_read_data_raw(struct rapl_domain *rd,
241 enum rapl_primitives prim,
242 bool xlate, u64 *data);
243 static int rapl_write_data_raw(struct rapl_domain *rd,
244 enum rapl_primitives prim,
245 unsigned long long value);
246 static u64 rapl_unit_xlate(struct rapl_domain *rd,
247 enum unit_type type, u64 value,
249 static void package_power_limit_irq_save(struct rapl_package *rp);
251 static LIST_HEAD(rapl_packages); /* guarded by CPU hotplug lock */
253 static const char * const rapl_domain_names[] = {
261 static struct powercap_control_type *control_type; /* PowerCap Controller */
262 static struct rapl_domain *platform_rapl_domain; /* Platform (PSys) domain */
264 /* caller to ensure CPU hotplug lock is held */
265 static struct rapl_package *find_package_by_id(int id)
267 struct rapl_package *rp;
269 list_for_each_entry(rp, &rapl_packages, plist) {
277 /* caller must hold cpu hotplug lock */
278 static void rapl_cleanup_data(void)
280 struct rapl_package *p, *tmp;
282 list_for_each_entry_safe(p, tmp, &rapl_packages, plist) {
289 static int get_energy_counter(struct powercap_zone *power_zone, u64 *energy_raw)
291 struct rapl_domain *rd;
294 /* prevent CPU hotplug, make sure the RAPL domain does not go
295 * away while reading the counter.
298 rd = power_zone_to_rapl_domain(power_zone);
300 if (!rapl_read_data_raw(rd, ENERGY_COUNTER, true, &energy_now)) {
301 *energy_raw = energy_now;
311 static int get_max_energy_counter(struct powercap_zone *pcd_dev, u64 *energy)
313 struct rapl_domain *rd = power_zone_to_rapl_domain(pcd_dev);
315 *energy = rapl_unit_xlate(rd, ENERGY_UNIT, ENERGY_STATUS_MASK, 0);
319 static int release_zone(struct powercap_zone *power_zone)
321 struct rapl_domain *rd = power_zone_to_rapl_domain(power_zone);
322 struct rapl_package *rp = rd->rp;
324 /* package zone is the last zone of a package, we can free
325 * memory here since all children has been unregistered.
327 if (rd->id == RAPL_DOMAIN_PACKAGE) {
336 static int find_nr_power_limit(struct rapl_domain *rd)
340 for (i = 0; i < NR_POWER_LIMITS; i++) {
341 if (rd->rpl[i].name == NULL)
348 static int set_domain_enable(struct powercap_zone *power_zone, bool mode)
350 struct rapl_domain *rd = power_zone_to_rapl_domain(power_zone);
352 if (rd->state & DOMAIN_STATE_BIOS_LOCKED)
356 rapl_write_data_raw(rd, PL1_ENABLE, mode);
357 if (rapl_defaults->set_floor_freq)
358 rapl_defaults->set_floor_freq(rd, mode);
364 static int get_domain_enable(struct powercap_zone *power_zone, bool *mode)
366 struct rapl_domain *rd = power_zone_to_rapl_domain(power_zone);
369 if (rd->state & DOMAIN_STATE_BIOS_LOCKED) {
374 if (rapl_read_data_raw(rd, PL1_ENABLE, true, &val)) {
384 /* per RAPL domain ops, in the order of rapl_domain_type */
385 static const struct powercap_zone_ops zone_ops[] = {
386 /* RAPL_DOMAIN_PACKAGE */
388 .get_energy_uj = get_energy_counter,
389 .get_max_energy_range_uj = get_max_energy_counter,
390 .release = release_zone,
391 .set_enable = set_domain_enable,
392 .get_enable = get_domain_enable,
394 /* RAPL_DOMAIN_PP0 */
396 .get_energy_uj = get_energy_counter,
397 .get_max_energy_range_uj = get_max_energy_counter,
398 .release = release_zone,
399 .set_enable = set_domain_enable,
400 .get_enable = get_domain_enable,
402 /* RAPL_DOMAIN_PP1 */
404 .get_energy_uj = get_energy_counter,
405 .get_max_energy_range_uj = get_max_energy_counter,
406 .release = release_zone,
407 .set_enable = set_domain_enable,
408 .get_enable = get_domain_enable,
410 /* RAPL_DOMAIN_DRAM */
412 .get_energy_uj = get_energy_counter,
413 .get_max_energy_range_uj = get_max_energy_counter,
414 .release = release_zone,
415 .set_enable = set_domain_enable,
416 .get_enable = get_domain_enable,
418 /* RAPL_DOMAIN_PLATFORM */
420 .get_energy_uj = get_energy_counter,
421 .get_max_energy_range_uj = get_max_energy_counter,
422 .release = release_zone,
423 .set_enable = set_domain_enable,
424 .get_enable = get_domain_enable,
428 static int set_power_limit(struct powercap_zone *power_zone, int id,
431 struct rapl_domain *rd;
432 struct rapl_package *rp;
436 rd = power_zone_to_rapl_domain(power_zone);
439 if (rd->state & DOMAIN_STATE_BIOS_LOCKED) {
440 dev_warn(&power_zone->dev, "%s locked by BIOS, monitoring only\n",
446 switch (rd->rpl[id].prim_id) {
448 rapl_write_data_raw(rd, POWER_LIMIT1, power_limit);
451 rapl_write_data_raw(rd, POWER_LIMIT2, power_limit);
457 package_power_limit_irq_save(rp);
463 static int get_current_power_limit(struct powercap_zone *power_zone, int id,
466 struct rapl_domain *rd;
472 rd = power_zone_to_rapl_domain(power_zone);
473 switch (rd->rpl[id].prim_id) {
484 if (rapl_read_data_raw(rd, prim, true, &val))
494 static int set_time_window(struct powercap_zone *power_zone, int id,
497 struct rapl_domain *rd;
501 rd = power_zone_to_rapl_domain(power_zone);
502 switch (rd->rpl[id].prim_id) {
504 rapl_write_data_raw(rd, TIME_WINDOW1, window);
507 rapl_write_data_raw(rd, TIME_WINDOW2, window);
516 static int get_time_window(struct powercap_zone *power_zone, int id, u64 *data)
518 struct rapl_domain *rd;
523 rd = power_zone_to_rapl_domain(power_zone);
524 switch (rd->rpl[id].prim_id) {
526 ret = rapl_read_data_raw(rd, TIME_WINDOW1, true, &val);
529 ret = rapl_read_data_raw(rd, TIME_WINDOW2, true, &val);
542 static const char *get_constraint_name(struct powercap_zone *power_zone, int id)
544 struct rapl_power_limit *rpl;
545 struct rapl_domain *rd;
547 rd = power_zone_to_rapl_domain(power_zone);
548 rpl = (struct rapl_power_limit *) &rd->rpl[id];
554 static int get_max_power(struct powercap_zone *power_zone, int id,
557 struct rapl_domain *rd;
563 rd = power_zone_to_rapl_domain(power_zone);
564 switch (rd->rpl[id].prim_id) {
566 prim = THERMAL_SPEC_POWER;
575 if (rapl_read_data_raw(rd, prim, true, &val))
585 static const struct powercap_zone_constraint_ops constraint_ops = {
586 .set_power_limit_uw = set_power_limit,
587 .get_power_limit_uw = get_current_power_limit,
588 .set_time_window_us = set_time_window,
589 .get_time_window_us = get_time_window,
590 .get_max_power_uw = get_max_power,
591 .get_name = get_constraint_name,
594 /* called after domain detection and package level data are set */
595 static void rapl_init_domains(struct rapl_package *rp)
598 struct rapl_domain *rd = rp->domains;
600 for (i = 0; i < RAPL_DOMAIN_MAX; i++) {
601 unsigned int mask = rp->domain_map & (1 << i);
603 case BIT(RAPL_DOMAIN_PACKAGE):
604 rd->name = rapl_domain_names[RAPL_DOMAIN_PACKAGE];
605 rd->id = RAPL_DOMAIN_PACKAGE;
606 rd->msrs[0] = MSR_PKG_POWER_LIMIT;
607 rd->msrs[1] = MSR_PKG_ENERGY_STATUS;
608 rd->msrs[2] = MSR_PKG_PERF_STATUS;
610 rd->msrs[4] = MSR_PKG_POWER_INFO;
611 rd->rpl[0].prim_id = PL1_ENABLE;
612 rd->rpl[0].name = pl1_name;
613 rd->rpl[1].prim_id = PL2_ENABLE;
614 rd->rpl[1].name = pl2_name;
616 case BIT(RAPL_DOMAIN_PP0):
617 rd->name = rapl_domain_names[RAPL_DOMAIN_PP0];
618 rd->id = RAPL_DOMAIN_PP0;
619 rd->msrs[0] = MSR_PP0_POWER_LIMIT;
620 rd->msrs[1] = MSR_PP0_ENERGY_STATUS;
622 rd->msrs[3] = MSR_PP0_POLICY;
624 rd->rpl[0].prim_id = PL1_ENABLE;
625 rd->rpl[0].name = pl1_name;
627 case BIT(RAPL_DOMAIN_PP1):
628 rd->name = rapl_domain_names[RAPL_DOMAIN_PP1];
629 rd->id = RAPL_DOMAIN_PP1;
630 rd->msrs[0] = MSR_PP1_POWER_LIMIT;
631 rd->msrs[1] = MSR_PP1_ENERGY_STATUS;
633 rd->msrs[3] = MSR_PP1_POLICY;
635 rd->rpl[0].prim_id = PL1_ENABLE;
636 rd->rpl[0].name = pl1_name;
638 case BIT(RAPL_DOMAIN_DRAM):
639 rd->name = rapl_domain_names[RAPL_DOMAIN_DRAM];
640 rd->id = RAPL_DOMAIN_DRAM;
641 rd->msrs[0] = MSR_DRAM_POWER_LIMIT;
642 rd->msrs[1] = MSR_DRAM_ENERGY_STATUS;
643 rd->msrs[2] = MSR_DRAM_PERF_STATUS;
645 rd->msrs[4] = MSR_DRAM_POWER_INFO;
646 rd->rpl[0].prim_id = PL1_ENABLE;
647 rd->rpl[0].name = pl1_name;
648 rd->domain_energy_unit =
649 rapl_defaults->dram_domain_energy_unit;
650 if (rd->domain_energy_unit)
651 pr_info("DRAM domain energy unit %dpj\n",
652 rd->domain_energy_unit);
662 static u64 rapl_unit_xlate(struct rapl_domain *rd, enum unit_type type,
663 u64 value, int to_raw)
666 struct rapl_package *rp = rd->rp;
671 units = rp->power_unit;
674 scale = ENERGY_UNIT_SCALE;
675 /* per domain unit takes precedence */
676 if (rd && rd->domain_energy_unit)
677 units = rd->domain_energy_unit;
679 units = rp->energy_unit;
682 return rapl_defaults->compute_time_window(rp, value, to_raw);
689 return div64_u64(value, units) * scale;
693 return div64_u64(value, scale);
696 /* in the order of enum rapl_primitives */
697 static struct rapl_primitive_info rpi[] = {
698 /* name, mask, shift, msr index, unit divisor */
699 PRIMITIVE_INFO_INIT(ENERGY_COUNTER, ENERGY_STATUS_MASK, 0,
700 RAPL_DOMAIN_MSR_STATUS, ENERGY_UNIT, 0),
701 PRIMITIVE_INFO_INIT(POWER_LIMIT1, POWER_LIMIT1_MASK, 0,
702 RAPL_DOMAIN_MSR_LIMIT, POWER_UNIT, 0),
703 PRIMITIVE_INFO_INIT(POWER_LIMIT2, POWER_LIMIT2_MASK, 32,
704 RAPL_DOMAIN_MSR_LIMIT, POWER_UNIT, 0),
705 PRIMITIVE_INFO_INIT(FW_LOCK, POWER_PP_LOCK, 31,
706 RAPL_DOMAIN_MSR_LIMIT, ARBITRARY_UNIT, 0),
707 PRIMITIVE_INFO_INIT(PL1_ENABLE, POWER_LIMIT1_ENABLE, 15,
708 RAPL_DOMAIN_MSR_LIMIT, ARBITRARY_UNIT, 0),
709 PRIMITIVE_INFO_INIT(PL1_CLAMP, POWER_LIMIT1_CLAMP, 16,
710 RAPL_DOMAIN_MSR_LIMIT, ARBITRARY_UNIT, 0),
711 PRIMITIVE_INFO_INIT(PL2_ENABLE, POWER_LIMIT2_ENABLE, 47,
712 RAPL_DOMAIN_MSR_LIMIT, ARBITRARY_UNIT, 0),
713 PRIMITIVE_INFO_INIT(PL2_CLAMP, POWER_LIMIT2_CLAMP, 48,
714 RAPL_DOMAIN_MSR_LIMIT, ARBITRARY_UNIT, 0),
715 PRIMITIVE_INFO_INIT(TIME_WINDOW1, TIME_WINDOW1_MASK, 17,
716 RAPL_DOMAIN_MSR_LIMIT, TIME_UNIT, 0),
717 PRIMITIVE_INFO_INIT(TIME_WINDOW2, TIME_WINDOW2_MASK, 49,
718 RAPL_DOMAIN_MSR_LIMIT, TIME_UNIT, 0),
719 PRIMITIVE_INFO_INIT(THERMAL_SPEC_POWER, POWER_INFO_THERMAL_SPEC_MASK,
720 0, RAPL_DOMAIN_MSR_INFO, POWER_UNIT, 0),
721 PRIMITIVE_INFO_INIT(MAX_POWER, POWER_INFO_MAX_MASK, 32,
722 RAPL_DOMAIN_MSR_INFO, POWER_UNIT, 0),
723 PRIMITIVE_INFO_INIT(MIN_POWER, POWER_INFO_MIN_MASK, 16,
724 RAPL_DOMAIN_MSR_INFO, POWER_UNIT, 0),
725 PRIMITIVE_INFO_INIT(MAX_TIME_WINDOW, POWER_INFO_MAX_TIME_WIN_MASK, 48,
726 RAPL_DOMAIN_MSR_INFO, TIME_UNIT, 0),
727 PRIMITIVE_INFO_INIT(THROTTLED_TIME, PERF_STATUS_THROTTLE_TIME_MASK, 0,
728 RAPL_DOMAIN_MSR_PERF, TIME_UNIT, 0),
729 PRIMITIVE_INFO_INIT(PRIORITY_LEVEL, PP_POLICY_MASK, 0,
730 RAPL_DOMAIN_MSR_POLICY, ARBITRARY_UNIT, 0),
732 PRIMITIVE_INFO_INIT(AVERAGE_POWER, 0, 0, 0, POWER_UNIT,
733 RAPL_PRIMITIVE_DERIVED),
737 /* Read primitive data based on its related struct rapl_primitive_info.
738 * if xlate flag is set, return translated data based on data units, i.e.
739 * time, energy, and power.
740 * RAPL MSRs are non-architectual and are laid out not consistently across
741 * domains. Here we use primitive info to allow writing consolidated access
743 * For a given primitive, it is processed by MSR mask and shift. Unit conversion
744 * is pre-assigned based on RAPL unit MSRs read at init time.
745 * 63-------------------------- 31--------------------------- 0
747 * | |<- shift ----------------|
748 * 63-------------------------- 31--------------------------- 0
750 static int rapl_read_data_raw(struct rapl_domain *rd,
751 enum rapl_primitives prim,
752 bool xlate, u64 *data)
756 struct rapl_primitive_info *rp = &rpi[prim];
759 if (!rp->name || rp->flag & RAPL_PRIMITIVE_DUMMY)
762 msr = rd->msrs[rp->id];
766 cpu = rd->rp->lead_cpu;
768 /* special-case package domain, which uses a different bit*/
769 if (prim == FW_LOCK && rd->id == RAPL_DOMAIN_PACKAGE) {
770 rp->mask = POWER_PACKAGE_LOCK;
773 /* non-hardware data are collected by the polling thread */
774 if (rp->flag & RAPL_PRIMITIVE_DERIVED) {
775 *data = rd->rdd.primitives[prim];
779 if (rdmsrl_safe_on_cpu(cpu, msr, &value)) {
780 pr_debug("failed to read msr 0x%x on cpu %d\n", msr, cpu);
784 final = value & rp->mask;
785 final = final >> rp->shift;
787 *data = rapl_unit_xlate(rd, rp->unit, final, 0);
795 static int msrl_update_safe(u32 msr_no, u64 clear_mask, u64 set_mask)
800 err = rdmsrl_safe(msr_no, &val);
807 err = wrmsrl_safe(msr_no, val);
813 static void msrl_update_func(void *info)
815 struct msrl_action *ma = info;
817 ma->err = msrl_update_safe(ma->msr_no, ma->clear_mask, ma->set_mask);
820 /* Similar use of primitive info in the read counterpart */
821 static int rapl_write_data_raw(struct rapl_domain *rd,
822 enum rapl_primitives prim,
823 unsigned long long value)
825 struct rapl_primitive_info *rp = &rpi[prim];
828 struct msrl_action ma;
831 cpu = rd->rp->lead_cpu;
832 bits = rapl_unit_xlate(rd, rp->unit, value, 1);
833 bits |= bits << rp->shift;
834 memset(&ma, 0, sizeof(ma));
836 ma.msr_no = rd->msrs[rp->id];
837 ma.clear_mask = rp->mask;
840 ret = smp_call_function_single(cpu, msrl_update_func, &ma, 1);
850 * Raw RAPL data stored in MSRs are in certain scales. We need to
851 * convert them into standard units based on the units reported in
852 * the RAPL unit MSRs. This is specific to CPUs as the method to
853 * calculate units differ on different CPUs.
854 * We convert the units to below format based on CPUs.
856 * energy unit: picoJoules : Represented in picoJoules by default
857 * power unit : microWatts : Represented in milliWatts by default
858 * time unit : microseconds: Represented in seconds by default
860 static int rapl_check_unit_core(struct rapl_package *rp, int cpu)
865 if (rdmsrl_safe_on_cpu(cpu, MSR_RAPL_POWER_UNIT, &msr_val)) {
866 pr_err("Failed to read power unit MSR 0x%x on CPU %d, exit.\n",
867 MSR_RAPL_POWER_UNIT, cpu);
871 value = (msr_val & ENERGY_UNIT_MASK) >> ENERGY_UNIT_OFFSET;
872 rp->energy_unit = ENERGY_UNIT_SCALE * 1000000 / (1 << value);
874 value = (msr_val & POWER_UNIT_MASK) >> POWER_UNIT_OFFSET;
875 rp->power_unit = 1000000 / (1 << value);
877 value = (msr_val & TIME_UNIT_MASK) >> TIME_UNIT_OFFSET;
878 rp->time_unit = 1000000 / (1 << value);
880 pr_debug("Core CPU package %d energy=%dpJ, time=%dus, power=%duW\n",
881 rp->id, rp->energy_unit, rp->time_unit, rp->power_unit);
886 static int rapl_check_unit_atom(struct rapl_package *rp, int cpu)
891 if (rdmsrl_safe_on_cpu(cpu, MSR_RAPL_POWER_UNIT, &msr_val)) {
892 pr_err("Failed to read power unit MSR 0x%x on CPU %d, exit.\n",
893 MSR_RAPL_POWER_UNIT, cpu);
896 value = (msr_val & ENERGY_UNIT_MASK) >> ENERGY_UNIT_OFFSET;
897 rp->energy_unit = ENERGY_UNIT_SCALE * 1 << value;
899 value = (msr_val & POWER_UNIT_MASK) >> POWER_UNIT_OFFSET;
900 rp->power_unit = (1 << value) * 1000;
902 value = (msr_val & TIME_UNIT_MASK) >> TIME_UNIT_OFFSET;
903 rp->time_unit = 1000000 / (1 << value);
905 pr_debug("Atom package %d energy=%dpJ, time=%dus, power=%duW\n",
906 rp->id, rp->energy_unit, rp->time_unit, rp->power_unit);
911 static void power_limit_irq_save_cpu(void *info)
914 struct rapl_package *rp = (struct rapl_package *)info;
916 /* save the state of PLN irq mask bit before disabling it */
917 rdmsr_safe(MSR_IA32_PACKAGE_THERM_INTERRUPT, &l, &h);
918 if (!(rp->power_limit_irq & PACKAGE_PLN_INT_SAVED)) {
919 rp->power_limit_irq = l & PACKAGE_THERM_INT_PLN_ENABLE;
920 rp->power_limit_irq |= PACKAGE_PLN_INT_SAVED;
922 l &= ~PACKAGE_THERM_INT_PLN_ENABLE;
923 wrmsr_safe(MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h);
928 * When package power limit is set artificially low by RAPL, LVT
929 * thermal interrupt for package power limit should be ignored
930 * since we are not really exceeding the real limit. The intention
931 * is to avoid excessive interrupts while we are trying to save power.
932 * A useful feature might be routing the package_power_limit interrupt
933 * to userspace via eventfd. once we have a usecase, this is simple
934 * to do by adding an atomic notifier.
937 static void package_power_limit_irq_save(struct rapl_package *rp)
939 if (!boot_cpu_has(X86_FEATURE_PTS) || !boot_cpu_has(X86_FEATURE_PLN))
942 smp_call_function_single(rp->lead_cpu, power_limit_irq_save_cpu, rp, 1);
945 static void power_limit_irq_restore_cpu(void *info)
948 struct rapl_package *rp = (struct rapl_package *)info;
950 rdmsr_safe(MSR_IA32_PACKAGE_THERM_INTERRUPT, &l, &h);
952 if (rp->power_limit_irq & PACKAGE_THERM_INT_PLN_ENABLE)
953 l |= PACKAGE_THERM_INT_PLN_ENABLE;
955 l &= ~PACKAGE_THERM_INT_PLN_ENABLE;
957 wrmsr_safe(MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h);
960 /* restore per package power limit interrupt enable state */
961 static void package_power_limit_irq_restore(struct rapl_package *rp)
963 if (!boot_cpu_has(X86_FEATURE_PTS) || !boot_cpu_has(X86_FEATURE_PLN))
966 /* irq enable state not saved, nothing to restore */
967 if (!(rp->power_limit_irq & PACKAGE_PLN_INT_SAVED))
970 smp_call_function_single(rp->lead_cpu, power_limit_irq_restore_cpu, rp, 1);
973 static void set_floor_freq_default(struct rapl_domain *rd, bool mode)
975 int nr_powerlimit = find_nr_power_limit(rd);
977 /* always enable clamp such that p-state can go below OS requested
978 * range. power capping priority over guranteed frequency.
980 rapl_write_data_raw(rd, PL1_CLAMP, mode);
982 /* some domains have pl2 */
983 if (nr_powerlimit > 1) {
984 rapl_write_data_raw(rd, PL2_ENABLE, mode);
985 rapl_write_data_raw(rd, PL2_CLAMP, mode);
989 static void set_floor_freq_atom(struct rapl_domain *rd, bool enable)
991 static u32 power_ctrl_orig_val;
994 if (!rapl_defaults->floor_freq_reg_addr) {
995 pr_err("Invalid floor frequency config register\n");
999 if (!power_ctrl_orig_val)
1000 iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_CR_READ,
1001 rapl_defaults->floor_freq_reg_addr,
1002 &power_ctrl_orig_val);
1003 mdata = power_ctrl_orig_val;
1005 mdata &= ~(0x7f << 8);
1008 iosf_mbi_write(BT_MBI_UNIT_PMC, MBI_CR_WRITE,
1009 rapl_defaults->floor_freq_reg_addr, mdata);
1012 static u64 rapl_compute_time_window_core(struct rapl_package *rp, u64 value,
1015 u64 f, y; /* fraction and exp. used for time unit */
1018 * Special processing based on 2^Y*(1+F/4), refer
1019 * to Intel Software Developer's manual Vol.3B: CH 14.9.3.
1022 f = (value & 0x60) >> 5;
1024 value = (1 << y) * (4 + f) * rp->time_unit / 4;
1026 do_div(value, rp->time_unit);
1028 f = div64_u64(4 * (value - (1 << y)), 1 << y);
1029 value = (y & 0x1f) | ((f & 0x3) << 5);
1034 static u64 rapl_compute_time_window_atom(struct rapl_package *rp, u64 value,
1038 * Atom time unit encoding is straight forward val * time_unit,
1039 * where time_unit is default to 1 sec. Never 0.
1042 return (value) ? value *= rp->time_unit : rp->time_unit;
1044 value = div64_u64(value, rp->time_unit);
1049 static const struct rapl_defaults rapl_defaults_core = {
1050 .floor_freq_reg_addr = 0,
1051 .check_unit = rapl_check_unit_core,
1052 .set_floor_freq = set_floor_freq_default,
1053 .compute_time_window = rapl_compute_time_window_core,
1056 static const struct rapl_defaults rapl_defaults_hsw_server = {
1057 .check_unit = rapl_check_unit_core,
1058 .set_floor_freq = set_floor_freq_default,
1059 .compute_time_window = rapl_compute_time_window_core,
1060 .dram_domain_energy_unit = 15300,
1063 static const struct rapl_defaults rapl_defaults_byt = {
1064 .floor_freq_reg_addr = IOSF_CPU_POWER_BUDGET_CTL_BYT,
1065 .check_unit = rapl_check_unit_atom,
1066 .set_floor_freq = set_floor_freq_atom,
1067 .compute_time_window = rapl_compute_time_window_atom,
1070 static const struct rapl_defaults rapl_defaults_tng = {
1071 .floor_freq_reg_addr = IOSF_CPU_POWER_BUDGET_CTL_TNG,
1072 .check_unit = rapl_check_unit_atom,
1073 .set_floor_freq = set_floor_freq_atom,
1074 .compute_time_window = rapl_compute_time_window_atom,
1077 static const struct rapl_defaults rapl_defaults_ann = {
1078 .floor_freq_reg_addr = 0,
1079 .check_unit = rapl_check_unit_atom,
1080 .set_floor_freq = NULL,
1081 .compute_time_window = rapl_compute_time_window_atom,
1084 static const struct rapl_defaults rapl_defaults_cht = {
1085 .floor_freq_reg_addr = 0,
1086 .check_unit = rapl_check_unit_atom,
1087 .set_floor_freq = NULL,
1088 .compute_time_window = rapl_compute_time_window_atom,
1091 #define RAPL_CPU(_model, _ops) { \
1092 .vendor = X86_VENDOR_INTEL, \
1095 .driver_data = (kernel_ulong_t)&_ops, \
1098 static const struct x86_cpu_id rapl_ids[] __initconst = {
1099 RAPL_CPU(0x2a, rapl_defaults_core),/* Sandy Bridge */
1100 RAPL_CPU(0x2d, rapl_defaults_core),/* Sandy Bridge EP */
1101 RAPL_CPU(0x37, rapl_defaults_byt),/* Valleyview */
1102 RAPL_CPU(0x3a, rapl_defaults_core),/* Ivy Bridge */
1103 RAPL_CPU(0x3c, rapl_defaults_core),/* Haswell */
1104 RAPL_CPU(0x3d, rapl_defaults_core),/* Broadwell */
1105 RAPL_CPU(0x3f, rapl_defaults_hsw_server),/* Haswell servers */
1106 RAPL_CPU(0x4f, rapl_defaults_hsw_server),/* Broadwell servers */
1107 RAPL_CPU(0x45, rapl_defaults_core),/* Haswell ULT */
1108 RAPL_CPU(0x46, rapl_defaults_core),/* Haswell */
1109 RAPL_CPU(0x47, rapl_defaults_core),/* Broadwell-H */
1110 RAPL_CPU(0x4E, rapl_defaults_core),/* Skylake */
1111 RAPL_CPU(0x4C, rapl_defaults_cht),/* Braswell/Cherryview */
1112 RAPL_CPU(0x4A, rapl_defaults_tng),/* Tangier */
1113 RAPL_CPU(0x56, rapl_defaults_core),/* Future Xeon */
1114 RAPL_CPU(0x5A, rapl_defaults_ann),/* Annidale */
1115 RAPL_CPU(0X5C, rapl_defaults_core),/* Broxton */
1116 RAPL_CPU(0x5E, rapl_defaults_core),/* Skylake-H/S */
1117 RAPL_CPU(0x57, rapl_defaults_hsw_server),/* Knights Landing */
1120 MODULE_DEVICE_TABLE(x86cpu, rapl_ids);
1122 /* read once for all raw primitive data for all packages, domains */
1123 static void rapl_update_domain_data(void)
1127 struct rapl_package *rp;
1129 list_for_each_entry(rp, &rapl_packages, plist) {
1130 for (dmn = 0; dmn < rp->nr_domains; dmn++) {
1131 pr_debug("update package %d domain %s data\n", rp->id,
1132 rp->domains[dmn].name);
1133 /* exclude non-raw primitives */
1134 for (prim = 0; prim < NR_RAW_PRIMITIVES; prim++)
1135 if (!rapl_read_data_raw(&rp->domains[dmn], prim,
1138 rp->domains[dmn].rdd.primitives[prim] =
1145 static int rapl_unregister_powercap(void)
1147 struct rapl_package *rp;
1148 struct rapl_domain *rd, *rd_package = NULL;
1150 /* unregister all active rapl packages from the powercap layer,
1153 list_for_each_entry(rp, &rapl_packages, plist) {
1154 package_power_limit_irq_restore(rp);
1156 for (rd = rp->domains; rd < rp->domains + rp->nr_domains;
1158 pr_debug("remove package, undo power limit on %d: %s\n",
1160 rapl_write_data_raw(rd, PL1_ENABLE, 0);
1161 rapl_write_data_raw(rd, PL1_CLAMP, 0);
1162 if (find_nr_power_limit(rd) > 1) {
1163 rapl_write_data_raw(rd, PL2_ENABLE, 0);
1164 rapl_write_data_raw(rd, PL2_CLAMP, 0);
1166 if (rd->id == RAPL_DOMAIN_PACKAGE) {
1170 powercap_unregister_zone(control_type, &rd->power_zone);
1172 /* do the package zone last */
1174 powercap_unregister_zone(control_type,
1175 &rd_package->power_zone);
1178 if (platform_rapl_domain) {
1179 powercap_unregister_zone(control_type,
1180 &platform_rapl_domain->power_zone);
1181 kfree(platform_rapl_domain);
1184 powercap_unregister_control_type(control_type);
1189 static int rapl_package_register_powercap(struct rapl_package *rp)
1191 struct rapl_domain *rd;
1193 char dev_name[17]; /* max domain name = 7 + 1 + 8 for int + 1 for null*/
1194 struct powercap_zone *power_zone = NULL;
1197 /* first we register package domain as the parent zone*/
1198 for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++) {
1199 if (rd->id == RAPL_DOMAIN_PACKAGE) {
1200 nr_pl = find_nr_power_limit(rd);
1201 pr_debug("register socket %d package domain %s\n",
1203 memset(dev_name, 0, sizeof(dev_name));
1204 snprintf(dev_name, sizeof(dev_name), "%s-%d",
1206 power_zone = powercap_register_zone(&rd->power_zone,
1212 if (IS_ERR(power_zone)) {
1213 pr_debug("failed to register package, %d\n",
1215 ret = PTR_ERR(power_zone);
1218 /* track parent zone in per package/socket data */
1219 rp->power_zone = power_zone;
1220 /* done, only one package domain per socket */
1225 pr_err("no package domain found, unknown topology!\n");
1229 /* now register domains as children of the socket/package*/
1230 for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++) {
1231 if (rd->id == RAPL_DOMAIN_PACKAGE)
1233 /* number of power limits per domain varies */
1234 nr_pl = find_nr_power_limit(rd);
1235 power_zone = powercap_register_zone(&rd->power_zone,
1236 control_type, rd->name,
1238 &zone_ops[rd->id], nr_pl,
1241 if (IS_ERR(power_zone)) {
1242 pr_debug("failed to register power_zone, %d:%s:%s\n",
1243 rp->id, rd->name, dev_name);
1244 ret = PTR_ERR(power_zone);
1252 /* clean up previously initialized domains within the package if we
1253 * failed after the first domain setup.
1255 while (--rd >= rp->domains) {
1256 pr_debug("unregister package %d domain %s\n", rp->id, rd->name);
1257 powercap_unregister_zone(control_type, &rd->power_zone);
1263 static int rapl_register_psys(void)
1265 struct rapl_domain *rd;
1266 struct powercap_zone *power_zone;
1269 if (rdmsrl_safe_on_cpu(0, MSR_PLATFORM_ENERGY_STATUS, &val) || !val)
1272 if (rdmsrl_safe_on_cpu(0, MSR_PLATFORM_POWER_LIMIT, &val) || !val)
1275 rd = kzalloc(sizeof(*rd), GFP_KERNEL);
1279 rd->name = rapl_domain_names[RAPL_DOMAIN_PLATFORM];
1280 rd->id = RAPL_DOMAIN_PLATFORM;
1281 rd->msrs[0] = MSR_PLATFORM_POWER_LIMIT;
1282 rd->msrs[1] = MSR_PLATFORM_ENERGY_STATUS;
1283 rd->rpl[0].prim_id = PL1_ENABLE;
1284 rd->rpl[0].name = pl1_name;
1285 rd->rpl[1].prim_id = PL2_ENABLE;
1286 rd->rpl[1].name = pl2_name;
1287 rd->rp = find_package_by_id(0);
1289 power_zone = powercap_register_zone(&rd->power_zone, control_type,
1291 &zone_ops[RAPL_DOMAIN_PLATFORM],
1292 2, &constraint_ops);
1294 if (IS_ERR(power_zone)) {
1296 return PTR_ERR(power_zone);
1299 platform_rapl_domain = rd;
1304 static int rapl_register_powercap(void)
1306 struct rapl_domain *rd;
1307 struct rapl_package *rp;
1310 control_type = powercap_register_control_type(NULL, "intel-rapl", NULL);
1311 if (IS_ERR(control_type)) {
1312 pr_debug("failed to register powercap control_type.\n");
1313 return PTR_ERR(control_type);
1315 /* read the initial data */
1316 rapl_update_domain_data();
1317 list_for_each_entry(rp, &rapl_packages, plist)
1318 if (rapl_package_register_powercap(rp))
1319 goto err_cleanup_package;
1321 /* Don't bail out if PSys is not supported */
1322 rapl_register_psys();
1326 err_cleanup_package:
1327 /* clean up previously initialized packages */
1328 list_for_each_entry_continue_reverse(rp, &rapl_packages, plist) {
1329 for (rd = rp->domains; rd < rp->domains + rp->nr_domains;
1331 pr_debug("unregister zone/package %d, %s domain\n",
1333 powercap_unregister_zone(control_type, &rd->power_zone);
1340 static int rapl_check_domain(int cpu, int domain)
1346 case RAPL_DOMAIN_PACKAGE:
1347 msr = MSR_PKG_ENERGY_STATUS;
1349 case RAPL_DOMAIN_PP0:
1350 msr = MSR_PP0_ENERGY_STATUS;
1352 case RAPL_DOMAIN_PP1:
1353 msr = MSR_PP1_ENERGY_STATUS;
1355 case RAPL_DOMAIN_DRAM:
1356 msr = MSR_DRAM_ENERGY_STATUS;
1358 case RAPL_DOMAIN_PLATFORM:
1359 /* PSYS(PLATFORM) is not a CPU domain, so avoid printng error */
1362 pr_err("invalid domain id %d\n", domain);
1365 /* make sure domain counters are available and contains non-zero
1366 * values, otherwise skip it.
1368 if (rdmsrl_safe_on_cpu(cpu, msr, &val) || !val)
1374 /* Detect active and valid domains for the given CPU, caller must
1375 * ensure the CPU belongs to the targeted package and CPU hotlug is disabled.
1377 static int rapl_detect_domains(struct rapl_package *rp, int cpu)
1381 struct rapl_domain *rd;
1384 for (i = 0; i < RAPL_DOMAIN_MAX; i++) {
1385 /* use physical package id to read counters */
1386 if (!rapl_check_domain(cpu, i)) {
1387 rp->domain_map |= 1 << i;
1388 pr_info("Found RAPL domain %s\n", rapl_domain_names[i]);
1391 rp->nr_domains = bitmap_weight(&rp->domain_map, RAPL_DOMAIN_MAX);
1392 if (!rp->nr_domains) {
1393 pr_err("no valid rapl domains found in package %d\n", rp->id);
1397 pr_debug("found %d domains on package %d\n", rp->nr_domains, rp->id);
1399 rp->domains = kcalloc(rp->nr_domains + 1, sizeof(struct rapl_domain),
1405 rapl_init_domains(rp);
1407 for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++) {
1408 /* check if the domain is locked by BIOS */
1409 ret = rapl_read_data_raw(rd, FW_LOCK, false, &locked);
1413 pr_info("RAPL package %d domain %s locked by BIOS\n",
1415 rd->state |= DOMAIN_STATE_BIOS_LOCKED;
1424 static bool is_package_new(int package)
1426 struct rapl_package *rp;
1428 /* caller prevents cpu hotplug, there will be no new packages added
1429 * or deleted while traversing the package list, no need for locking.
1431 list_for_each_entry(rp, &rapl_packages, plist)
1432 if (package == rp->id)
1438 /* RAPL interface can be made of a two-level hierarchy: package level and domain
1439 * level. We first detect the number of packages then domains of each package.
1440 * We have to consider the possiblity of CPU online/offline due to hotplug and
1443 static int rapl_detect_topology(void)
1447 struct rapl_package *new_package, *rp;
1449 for_each_online_cpu(i) {
1450 phy_package_id = topology_physical_package_id(i);
1451 if (is_package_new(phy_package_id)) {
1452 new_package = kzalloc(sizeof(*rp), GFP_KERNEL);
1454 rapl_cleanup_data();
1457 /* add the new package to the list */
1458 new_package->id = phy_package_id;
1459 new_package->nr_cpus = 1;
1460 /* use the first active cpu of the package to access */
1461 new_package->lead_cpu = i;
1462 /* check if the package contains valid domains */
1463 if (rapl_detect_domains(new_package, i) ||
1464 rapl_defaults->check_unit(new_package, i)) {
1465 kfree(new_package->domains);
1467 /* free up the packages already initialized */
1468 rapl_cleanup_data();
1471 INIT_LIST_HEAD(&new_package->plist);
1472 list_add(&new_package->plist, &rapl_packages);
1474 rp = find_package_by_id(phy_package_id);
1483 /* called from CPU hotplug notifier, hotplug lock held */
1484 static void rapl_remove_package(struct rapl_package *rp)
1486 struct rapl_domain *rd, *rd_package = NULL;
1488 for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++) {
1489 if (rd->id == RAPL_DOMAIN_PACKAGE) {
1493 pr_debug("remove package %d, %s domain\n", rp->id, rd->name);
1494 powercap_unregister_zone(control_type, &rd->power_zone);
1496 /* do parent zone last */
1497 powercap_unregister_zone(control_type, &rd_package->power_zone);
1498 list_del(&rp->plist);
1502 /* called from CPU hotplug notifier, hotplug lock held */
1503 static int rapl_add_package(int cpu)
1507 struct rapl_package *rp;
1509 phy_package_id = topology_physical_package_id(cpu);
1510 rp = kzalloc(sizeof(struct rapl_package), GFP_KERNEL);
1514 /* add the new package to the list */
1515 rp->id = phy_package_id;
1519 /* check if the package contains valid domains */
1520 if (rapl_detect_domains(rp, cpu) ||
1521 rapl_defaults->check_unit(rp, cpu)) {
1523 goto err_free_package;
1525 if (!rapl_package_register_powercap(rp)) {
1526 INIT_LIST_HEAD(&rp->plist);
1527 list_add(&rp->plist, &rapl_packages);
1538 /* Handles CPU hotplug on multi-socket systems.
1539 * If a CPU goes online as the first CPU of the physical package
1540 * we add the RAPL package to the system. Similarly, when the last
1541 * CPU of the package is removed, we remove the RAPL package and its
1542 * associated domains. Cooling devices are handled accordingly at
1545 static int rapl_cpu_callback(struct notifier_block *nfb,
1546 unsigned long action, void *hcpu)
1548 unsigned long cpu = (unsigned long)hcpu;
1550 struct rapl_package *rp;
1553 phy_package_id = topology_physical_package_id(cpu);
1556 case CPU_ONLINE_FROZEN:
1557 case CPU_DOWN_FAILED:
1558 case CPU_DOWN_FAILED_FROZEN:
1559 rp = find_package_by_id(phy_package_id);
1563 rapl_add_package(cpu);
1565 case CPU_DOWN_PREPARE:
1566 case CPU_DOWN_PREPARE_FROZEN:
1567 rp = find_package_by_id(phy_package_id);
1570 if (--rp->nr_cpus == 0)
1571 rapl_remove_package(rp);
1572 else if (cpu == rp->lead_cpu) {
1573 /* choose another active cpu in the package */
1574 lead_cpu = cpumask_any_but(topology_core_cpumask(cpu), cpu);
1575 if (lead_cpu < nr_cpu_ids)
1576 rp->lead_cpu = lead_cpu;
1577 else /* should never go here */
1578 pr_err("no active cpu available for package %d\n",
1586 static struct notifier_block rapl_cpu_notifier = {
1587 .notifier_call = rapl_cpu_callback,
1590 static int __init rapl_init(void)
1593 const struct x86_cpu_id *id;
1595 id = x86_match_cpu(rapl_ids);
1597 pr_err("driver does not support CPU family %d model %d\n",
1598 boot_cpu_data.x86, boot_cpu_data.x86_model);
1603 rapl_defaults = (struct rapl_defaults *)id->driver_data;
1605 cpu_notifier_register_begin();
1607 /* prevent CPU hotplug during detection */
1609 ret = rapl_detect_topology();
1613 if (rapl_register_powercap()) {
1614 rapl_cleanup_data();
1618 __register_hotcpu_notifier(&rapl_cpu_notifier);
1621 cpu_notifier_register_done();
1626 static void __exit rapl_exit(void)
1628 cpu_notifier_register_begin();
1630 __unregister_hotcpu_notifier(&rapl_cpu_notifier);
1631 rapl_unregister_powercap();
1632 rapl_cleanup_data();
1634 cpu_notifier_register_done();
1637 module_init(rapl_init);
1638 module_exit(rapl_exit);
1640 MODULE_DESCRIPTION("Driver for Intel RAPL (Running Average Power Limit)");
1641 MODULE_AUTHOR("Jacob Pan <jacob.jun.pan@intel.com>");
1642 MODULE_LICENSE("GPL v2");