drivers/ptp/ptp_pch.c

   1 /*
   2  * PTP 1588 clock using the EG20T PCH
   3  *
   4  * Copyright (C) 2010 OMICRON electronics GmbH
   5  * Copyright (C) 2011-2012 LAPIS SEMICONDUCTOR Co., LTD.
   6  *
   7  * This code was derived from the IXP46X driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; version 2 of the License.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307, USA.
  21  */
  22
  23 #include <linux/device.h>
  24 #include <linux/err.h>
  25 #include <linux/init.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/io.h>
  28 #include <linux/irq.h>
  29 #include <linux/kernel.h>
  30 #include <linux/module.h>
  31 #include <linux/pci.h>
  32 #include <linux/ptp_clock_kernel.h>
  33
  34 #define STATION_ADDR_LEN        20
  35 #define PCI_DEVICE_ID_PCH_1588  0x8819
  36 #define IO_MEM_BAR 1
  37
  38 #define DEFAULT_ADDEND 0xA0000000
  39 #define TICKS_NS_SHIFT  5
  40 #define N_EXT_TS        2
  41
  42 enum pch_status {
  43         PCH_SUCCESS,
  44         PCH_INVALIDPARAM,
  45         PCH_NOTIMESTAMP,
  46         PCH_INTERRUPTMODEINUSE,
  47         PCH_FAILED,
  48         PCH_UNSUPPORTED,
  49 };
  50 /**
  51  * struct pch_ts_regs - IEEE 1588 registers
  52  */
  53 struct pch_ts_regs {
  54         u32 control;
  55         u32 event;
  56         u32 addend;
  57         u32 accum;
  58         u32 test;
  59         u32 ts_compare;
  60         u32 rsystime_lo;
  61         u32 rsystime_hi;
  62         u32 systime_lo;
  63         u32 systime_hi;
  64         u32 trgt_lo;
  65         u32 trgt_hi;
  66         u32 asms_lo;
  67         u32 asms_hi;
  68         u32 amms_lo;
  69         u32 amms_hi;
  70         u32 ch_control;
  71         u32 ch_event;
  72         u32 tx_snap_lo;
  73         u32 tx_snap_hi;
  74         u32 rx_snap_lo;
  75         u32 rx_snap_hi;
  76         u32 src_uuid_lo;
  77         u32 src_uuid_hi;
  78         u32 can_status;
  79         u32 can_snap_lo;
  80         u32 can_snap_hi;
  81         u32 ts_sel;
  82         u32 ts_st[6];
  83         u32 reserve1[14];
  84         u32 stl_max_set_en;
  85         u32 stl_max_set;
  86         u32 reserve2[13];
  87         u32 srst;
  88 };
  89
  90 #define PCH_TSC_RESET           (1 << 0)
  91 #define PCH_TSC_TTM_MASK        (1 << 1)
  92 #define PCH_TSC_ASMS_MASK       (1 << 2)
  93 #define PCH_TSC_AMMS_MASK       (1 << 3)
  94 #define PCH_TSC_PPSM_MASK       (1 << 4)
  95 #define PCH_TSE_TTIPEND         (1 << 1)
  96 #define PCH_TSE_SNS             (1 << 2)
  97 #define PCH_TSE_SNM             (1 << 3)
  98 #define PCH_TSE_PPS             (1 << 4)
  99 #define PCH_CC_MM               (1 << 0)
 100 #define PCH_CC_TA               (1 << 1)
 101
 102 #define PCH_CC_MODE_SHIFT       16
 103 #define PCH_CC_MODE_MASK        0x001F0000
 104 #define PCH_CC_VERSION          (1 << 31)
 105 #define PCH_CE_TXS              (1 << 0)
 106 #define PCH_CE_RXS              (1 << 1)
 107 #define PCH_CE_OVR              (1 << 0)
 108 #define PCH_CE_VAL              (1 << 1)
 109 #define PCH_ECS_ETH             (1 << 0)
 110
 111 #define PCH_ECS_CAN             (1 << 1)
 112 #define PCH_STATION_BYTES       6
 113
 114 #define PCH_IEEE1588_ETH        (1 << 0)
 115 #define PCH_IEEE1588_CAN        (1 << 1)
 116 /**
 117  * struct pch_dev - Driver private data
 118  */
 119 struct pch_dev {
 120         struct pch_ts_regs *regs;
 121         struct ptp_clock *ptp_clock;
 122         struct ptp_clock_info caps;
 123         int exts0_enabled;
 124         int exts1_enabled;
 125
 126         u32 mem_base;
 127         u32 mem_size;
 128         u32 irq;
 129         struct pci_dev *pdev;
 130         spinlock_t register_lock;
 131 };
 132
 133 /**
 134  * struct pch_params - 1588 module parameter
 135  */
 136 struct pch_params {
 137         u8 station[STATION_ADDR_LEN];
 138 };
 139
 140 /* structure to hold the module parameters */
 141 static struct pch_params pch_param = {
 142         "00:00:00:00:00:00"
 143 };
 144
 145 /*
 146  * Register access functions
 147  */
 148 static inline void pch_eth_enable_set(struct pch_dev *chip)
 149 {
 150         u32 val;
 151         /* SET the eth_enable bit */
 152         val = ioread32(&chip->regs->ts_sel) | (PCH_ECS_ETH);
 153         iowrite32(val, (&chip->regs->ts_sel));
 154 }
 155
 156 static u64 pch_systime_read(struct pch_ts_regs *regs)
 157 {
 158         u64 ns;
 159         u32 lo, hi;
 160
 161         lo = ioread32(&regs->systime_lo);
 162         hi = ioread32(&regs->systime_hi);
 163
 164         ns = ((u64) hi) << 32;
 165         ns |= lo;
 166         ns <<= TICKS_NS_SHIFT;
 167
 168         return ns;
 169 }
 170
 171 static void pch_systime_write(struct pch_ts_regs *regs, u64 ns)
 172 {
 173         u32 hi, lo;
 174
 175         ns >>= TICKS_NS_SHIFT;
 176         hi = ns >> 32;
 177         lo = ns & 0xffffffff;
 178
 179         iowrite32(lo, &regs->systime_lo);
 180         iowrite32(hi, &regs->systime_hi);
 181 }
 182
 183 static inline void pch_block_reset(struct pch_dev *chip)
 184 {
 185         u32 val;
 186         /* Reset Hardware Assist block */
 187         val = ioread32(&chip->regs->control) | PCH_TSC_RESET;
 188         iowrite32(val, (&chip->regs->control));
 189         val = val & ~PCH_TSC_RESET;
 190         iowrite32(val, (&chip->regs->control));
 191 }
 192
 193 u32 pch_ch_control_read(struct pci_dev *pdev)
 194 {
 195         struct pch_dev *chip = pci_get_drvdata(pdev);
 196         u32 val;
 197
 198         val = ioread32(&chip->regs->ch_control);
 199
 200         return val;
 201 }
 202 EXPORT_SYMBOL(pch_ch_control_read);
 203
 204 void pch_ch_control_write(struct pci_dev *pdev, u32 val)
 205 {
 206         struct pch_dev *chip = pci_get_drvdata(pdev);
 207
 208         iowrite32(val, (&chip->regs->ch_control));
 209 }
 210 EXPORT_SYMBOL(pch_ch_control_write);
 211
 212 u32 pch_ch_event_read(struct pci_dev *pdev)
 213 {
 214         struct pch_dev *chip = pci_get_drvdata(pdev);
 215         u32 val;
 216
 217         val = ioread32(&chip->regs->ch_event);
 218
 219         return val;
 220 }
 221 EXPORT_SYMBOL(pch_ch_event_read);
 222
 223 void pch_ch_event_write(struct pci_dev *pdev, u32 val)
 224 {
 225         struct pch_dev *chip = pci_get_drvdata(pdev);
 226
 227         iowrite32(val, (&chip->regs->ch_event));
 228 }
 229 EXPORT_SYMBOL(pch_ch_event_write);
 230
 231 u32 pch_src_uuid_lo_read(struct pci_dev *pdev)
 232 {
 233         struct pch_dev *chip = pci_get_drvdata(pdev);
 234         u32 val;
 235
 236         val = ioread32(&chip->regs->src_uuid_lo);
 237
 238         return val;
 239 }
 240 EXPORT_SYMBOL(pch_src_uuid_lo_read);
 241
 242 u32 pch_src_uuid_hi_read(struct pci_dev *pdev)
 243 {
 244         struct pch_dev *chip = pci_get_drvdata(pdev);
 245         u32 val;
 246
 247         val = ioread32(&chip->regs->src_uuid_hi);
 248
 249         return val;
 250 }
 251 EXPORT_SYMBOL(pch_src_uuid_hi_read);
 252
 253 u64 pch_rx_snap_read(struct pci_dev *pdev)
 254 {
 255         struct pch_dev *chip = pci_get_drvdata(pdev);
 256         u64 ns;
 257         u32 lo, hi;
 258
 259         lo = ioread32(&chip->regs->rx_snap_lo);
 260         hi = ioread32(&chip->regs->rx_snap_hi);
 261
 262         ns = ((u64) hi) << 32;
 263         ns |= lo;
 264         ns <<= TICKS_NS_SHIFT;
 265
 266         return ns;
 267 }
 268 EXPORT_SYMBOL(pch_rx_snap_read);
 269
 270 u64 pch_tx_snap_read(struct pci_dev *pdev)
 271 {
 272         struct pch_dev *chip = pci_get_drvdata(pdev);
 273         u64 ns;
 274         u32 lo, hi;
 275
 276         lo = ioread32(&chip->regs->tx_snap_lo);
 277         hi = ioread32(&chip->regs->tx_snap_hi);
 278
 279         ns = ((u64) hi) << 32;
 280         ns |= lo;
 281         ns <<= TICKS_NS_SHIFT;
 282
 283         return ns;
 284 }
 285 EXPORT_SYMBOL(pch_tx_snap_read);
 286
 287 /* This function enables all 64 bits in system time registers [high & low].
 288 This is a work-around for non continuous value in the SystemTime Register*/
 289 static void pch_set_system_time_count(struct pch_dev *chip)
 290 {
 291         iowrite32(0x01, &chip->regs->stl_max_set_en);
 292         iowrite32(0xFFFFFFFF, &chip->regs->stl_max_set);
 293         iowrite32(0x00, &chip->regs->stl_max_set_en);
 294 }
 295
 296 static void pch_reset(struct pch_dev *chip)
 297 {
 298         /* Reset Hardware Assist */
 299         pch_block_reset(chip);
 300
 301         /* enable all 32 bits in system time registers */
 302         pch_set_system_time_count(chip);
 303 }
 304
 305 /**
 306  * pch_set_station_address() - This API sets the station address used by
 307  *                                  IEEE 1588 hardware when looking at PTP
 308  *                                  traffic on the  ethernet interface
 309  * @addr:       dress which contain the column separated address to be used.
 310  */
 311 int pch_set_station_address(u8 *addr, struct pci_dev *pdev)
 312 {
 313         s32 i;
 314         struct pch_dev *chip = pci_get_drvdata(pdev);
 315
 316         /* Verify the parameter */
 317         if ((chip->regs == 0) || addr == (u8 *)NULL) {
 318                 dev_err(&pdev->dev,
 319                         "invalid params returning PCH_INVALIDPARAM\n");
 320                 return PCH_INVALIDPARAM;
 321         }
 322         /* For all station address bytes */
 323         for (i = 0; i < PCH_STATION_BYTES; i++) {
 324                 u32 val;
 325                 s32 tmp;
 326
 327                 tmp = hex_to_bin(addr[i * 3]);
 328                 if (tmp < 0) {
 329                         dev_err(&pdev->dev,
 330                                 "invalid params returning PCH_INVALIDPARAM\n");
 331                         return PCH_INVALIDPARAM;
 332                 }
 333                 val = tmp * 16;
 334                 tmp = hex_to_bin(addr[(i * 3) + 1]);
 335                 if (tmp < 0) {
 336                         dev_err(&pdev->dev,
 337                                 "invalid params returning PCH_INVALIDPARAM\n");
 338                         return PCH_INVALIDPARAM;
 339                 }
 340                 val += tmp;
 341                 /* Expects ':' separated addresses */
 342                 if ((i < 5) && (addr[(i * 3) + 2] != ':')) {
 343                         dev_err(&pdev->dev,
 344                                 "invalid params returning PCH_INVALIDPARAM\n");
 345                         return PCH_INVALIDPARAM;
 346                 }
 347
 348                 /* Ideally we should set the address only after validating
 349                                                          entire string */
 350                 dev_dbg(&pdev->dev, "invoking pch_station_set\n");
 351                 iowrite32(val, &chip->regs->ts_st[i]);
 352         }
 353         return 0;
 354 }
 355 EXPORT_SYMBOL(pch_set_station_address);
 356
 357 /*
 358  * Interrupt service routine
 359  */
 360 static irqreturn_t isr(int irq, void *priv)
 361 {
 362         struct pch_dev *pch_dev = priv;
 363         struct pch_ts_regs *regs = pch_dev->regs;
 364         struct ptp_clock_event event;
 365         u32 ack = 0, lo, hi, val;
 366
 367         val = ioread32(&regs->event);
 368
 369         if (val & PCH_TSE_SNS) {
 370                 ack |= PCH_TSE_SNS;
 371                 if (pch_dev->exts0_enabled) {
 372                         hi = ioread32(&regs->asms_hi);
 373                         lo = ioread32(&regs->asms_lo);
 374                         event.type = PTP_CLOCK_EXTTS;
 375                         event.index = 0;
 376                         event.timestamp = ((u64) hi) << 32;
 377                         event.timestamp |= lo;
 378                         event.timestamp <<= TICKS_NS_SHIFT;
 379                         ptp_clock_event(pch_dev->ptp_clock, &event);
 380                 }
 381         }
 382
 383         if (val & PCH_TSE_SNM) {
 384                 ack |= PCH_TSE_SNM;
 385                 if (pch_dev->exts1_enabled) {
 386                         hi = ioread32(&regs->amms_hi);
 387                         lo = ioread32(&regs->amms_lo);
 388                         event.type = PTP_CLOCK_EXTTS;
 389                         event.index = 1;
 390                         event.timestamp = ((u64) hi) << 32;
 391                         event.timestamp |= lo;
 392                         event.timestamp <<= TICKS_NS_SHIFT;
 393                         ptp_clock_event(pch_dev->ptp_clock, &event);
 394                 }
 395         }
 396
 397         if (val & PCH_TSE_TTIPEND)
 398                 ack |= PCH_TSE_TTIPEND; /* this bit seems to be always set */
 399
 400         if (ack) {
 401                 iowrite32(ack, &regs->event);
 402                 return IRQ_HANDLED;
 403         } else
 404                 return IRQ_NONE;
 405 }
 406
 407 /*
 408  * PTP clock operations
 409  */
 410
 411 static int ptp_pch_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
 412 {
 413         u64 adj;
 414         u32 diff, addend;
 415         int neg_adj = 0;
 416         struct pch_dev *pch_dev = container_of(ptp, struct pch_dev, caps);
 417         struct pch_ts_regs *regs = pch_dev->regs;
 418
 419         if (ppb < 0) {
 420                 neg_adj = 1;
 421                 ppb = -ppb;
 422         }
 423         addend = DEFAULT_ADDEND;
 424         adj = addend;
 425         adj *= ppb;
 426         diff = div_u64(adj, 1000000000ULL);
 427
 428         addend = neg_adj ? addend - diff : addend + diff;
 429
 430         iowrite32(addend, &regs->addend);
 431
 432         return 0;
 433 }
 434
 435 static int ptp_pch_adjtime(struct ptp_clock_info *ptp, s64 delta)
 436 {
 437         s64 now;
 438         unsigned long flags;
 439         struct pch_dev *pch_dev = container_of(ptp, struct pch_dev, caps);
 440         struct pch_ts_regs *regs = pch_dev->regs;
 441
 442         spin_lock_irqsave(&pch_dev->register_lock, flags);
 443         now = pch_systime_read(regs);
 444         now += delta;
 445         pch_systime_write(regs, now);
 446         spin_unlock_irqrestore(&pch_dev->register_lock, flags);
 447
 448         return 0;
 449 }
 450
 451 static int ptp_pch_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
 452 {
 453         u64 ns;
 454         u32 remainder;
 455         unsigned long flags;
 456         struct pch_dev *pch_dev = container_of(ptp, struct pch_dev, caps);
 457         struct pch_ts_regs *regs = pch_dev->regs;
 458
 459         spin_lock_irqsave(&pch_dev->register_lock, flags);
 460         ns = pch_systime_read(regs);
 461         spin_unlock_irqrestore(&pch_dev->register_lock, flags);
 462
 463         ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder);
 464         ts->tv_nsec = remainder;
 465         return 0;
 466 }
 467
 468 static int ptp_pch_settime(struct ptp_clock_info *ptp,
 469                            const struct timespec *ts)
 470 {
 471         u64 ns;
 472         unsigned long flags;
 473         struct pch_dev *pch_dev = container_of(ptp, struct pch_dev, caps);
 474         struct pch_ts_regs *regs = pch_dev->regs;
 475
 476         ns = ts->tv_sec * 1000000000ULL;
 477         ns += ts->tv_nsec;
 478
 479         spin_lock_irqsave(&pch_dev->register_lock, flags);
 480         pch_systime_write(regs, ns);
 481         spin_unlock_irqrestore(&pch_dev->register_lock, flags);
 482
 483         return 0;
 484 }
 485
 486 static int ptp_pch_enable(struct ptp_clock_info *ptp,
 487                           struct ptp_clock_request *rq, int on)
 488 {
 489         struct pch_dev *pch_dev = container_of(ptp, struct pch_dev, caps);
 490
 491         switch (rq->type) {
 492         case PTP_CLK_REQ_EXTTS:
 493                 switch (rq->extts.index) {
 494                 case 0:
 495                         pch_dev->exts0_enabled = on ? 1 : 0;
 496                         break;
 497                 case 1:
 498                         pch_dev->exts1_enabled = on ? 1 : 0;
 499                         break;
 500                 default:
 501                         return -EINVAL;
 502                 }
 503                 return 0;
 504         default:
 505                 break;
 506         }
 507
 508         return -EOPNOTSUPP;
 509 }
 510
 511 static struct ptp_clock_info ptp_pch_caps = {
 512         .owner          = THIS_MODULE,
 513         .name           = "PCH timer",
 514         .max_adj        = 50000000,
 515         .n_ext_ts       = N_EXT_TS,
 516         .pps            = 0,
 517         .adjfreq        = ptp_pch_adjfreq,
 518         .adjtime        = ptp_pch_adjtime,
 519         .gettime        = ptp_pch_gettime,
 520         .settime        = ptp_pch_settime,
 521         .enable         = ptp_pch_enable,
 522 };
 523
 524
 525 #ifdef CONFIG_PM
 526 static s32 pch_suspend(struct pci_dev *pdev, pm_message_t state)
 527 {
 528         pci_disable_device(pdev);
 529         pci_enable_wake(pdev, PCI_D3hot, 0);
 530
 531         if (pci_save_state(pdev) != 0) {
 532                 dev_err(&pdev->dev, "could not save PCI config state\n");
 533                 return -ENOMEM;
 534         }
 535         pci_set_power_state(pdev, pci_choose_state(pdev, state));
 536
 537         return 0;
 538 }
 539
 540 static s32 pch_resume(struct pci_dev *pdev)
 541 {
 542         s32 ret;
 543
 544         pci_set_power_state(pdev, PCI_D0);
 545         pci_restore_state(pdev);
 546         ret = pci_enable_device(pdev);
 547         if (ret) {
 548                 dev_err(&pdev->dev, "pci_enable_device failed\n");
 549                 return ret;
 550         }
 551         pci_enable_wake(pdev, PCI_D3hot, 0);
 552         return 0;
 553 }
 554 #else
 555 #define pch_suspend NULL
 556 #define pch_resume NULL
 557 #endif
 558
 559 static void __devexit pch_remove(struct pci_dev *pdev)
 560 {
 561         struct pch_dev *chip = pci_get_drvdata(pdev);
 562
 563         ptp_clock_unregister(chip->ptp_clock);
 564         /* free the interrupt */
 565         if (pdev->irq != 0)
 566                 free_irq(pdev->irq, chip);
 567
 568         /* unmap the virtual IO memory space */
 569         if (chip->regs != 0) {
 570                 iounmap(chip->regs);
 571                 chip->regs = 0;
 572         }
 573         /* release the reserved IO memory space */
 574         if (chip->mem_base != 0) {
 575                 release_mem_region(chip->mem_base, chip->mem_size);
 576                 chip->mem_base = 0;
 577         }
 578         pci_disable_device(pdev);
 579         kfree(chip);
 580         dev_info(&pdev->dev, "complete\n");
 581 }
 582
 583 static s32 __devinit
 584 pch_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 585 {
 586         s32 ret;
 587         unsigned long flags;
 588         struct pch_dev *chip;
 589
 590         chip = kzalloc(sizeof(struct pch_dev), GFP_KERNEL);
 591         if (chip == NULL)
 592                 return -ENOMEM;
 593
 594         /* enable the 1588 pci device */
 595         ret = pci_enable_device(pdev);
 596         if (ret != 0) {
 597                 dev_err(&pdev->dev, "could not enable the pci device\n");
 598                 goto err_pci_en;
 599         }
 600
 601         chip->mem_base = pci_resource_start(pdev, IO_MEM_BAR);
 602         if (!chip->mem_base) {
 603                 dev_err(&pdev->dev, "could not locate IO memory address\n");
 604                 ret = -ENODEV;
 605                 goto err_pci_start;
 606         }
 607
 608         /* retrieve the available length of the IO memory space */
 609         chip->mem_size = pci_resource_len(pdev, IO_MEM_BAR);
 610
 611         /* allocate the memory for the device registers */
 612         if (!request_mem_region(chip->mem_base, chip->mem_size, "1588_regs")) {
 613                 dev_err(&pdev->dev,
 614                         "could not allocate register memory space\n");
 615                 ret = -EBUSY;
 616                 goto err_req_mem_region;
 617         }
 618
 619         /* get the virtual address to the 1588 registers */
 620         chip->regs = ioremap(chip->mem_base, chip->mem_size);
 621
 622         if (!chip->regs) {
 623                 dev_err(&pdev->dev, "Could not get virtual address\n");
 624                 ret = -ENOMEM;
 625                 goto err_ioremap;
 626         }
 627
 628         chip->caps = ptp_pch_caps;
 629         chip->ptp_clock = ptp_clock_register(&chip->caps);
 630
 631         if (IS_ERR(chip->ptp_clock))
 632                 return PTR_ERR(chip->ptp_clock);
 633
 634         spin_lock_init(&chip->register_lock);
 635
 636         ret = request_irq(pdev->irq, &isr, IRQF_SHARED, KBUILD_MODNAME, chip);
 637         if (ret != 0) {
 638                 dev_err(&pdev->dev, "failed to get irq %d\n", pdev->irq);
 639                 goto err_req_irq;
 640         }
 641
 642         /* indicate success */
 643         chip->irq = pdev->irq;
 644         chip->pdev = pdev;
 645         pci_set_drvdata(pdev, chip);
 646
 647         spin_lock_irqsave(&chip->register_lock, flags);
 648         /* reset the ieee1588 h/w */
 649         pch_reset(chip);
 650
 651         iowrite32(DEFAULT_ADDEND, &chip->regs->addend);
 652         iowrite32(1, &chip->regs->trgt_lo);
 653         iowrite32(0, &chip->regs->trgt_hi);
 654         iowrite32(PCH_TSE_TTIPEND, &chip->regs->event);
 655         /* Version: IEEE1588 v1 and IEEE1588-2008,  Mode: All Evwnt, Locked  */
 656         iowrite32(0x80020000, &chip->regs->ch_control);
 657
 658         pch_eth_enable_set(chip);
 659
 660         if (strcmp(pch_param.station, "00:00:00:00:00:00") != 0) {
 661                 if (pch_set_station_address(pch_param.station, pdev) != 0) {
 662                         dev_err(&pdev->dev,
 663                         "Invalid station address parameter\n"
 664                         "Module loaded but station address not set correctly\n"
 665                         );
 666                 }
 667         }
 668         spin_unlock_irqrestore(&chip->register_lock, flags);
 669         return 0;
 670
 671 err_req_irq:
 672         ptp_clock_unregister(chip->ptp_clock);
 673         iounmap(chip->regs);
 674         chip->regs = 0;
 675
 676 err_ioremap:
 677         release_mem_region(chip->mem_base, chip->mem_size);
 678
 679 err_req_mem_region:
 680         chip->mem_base = 0;
 681
 682 err_pci_start:
 683         pci_disable_device(pdev);
 684
 685 err_pci_en:
 686         kfree(chip);
 687         dev_err(&pdev->dev, "probe failed(ret=0x%x)\n", ret);
 688
 689         return ret;
 690 }
 691
 692 static DEFINE_PCI_DEVICE_TABLE(pch_ieee1588_pcidev_id) = {
 693         {
 694           .vendor = PCI_VENDOR_ID_INTEL,
 695           .device = PCI_DEVICE_ID_PCH_1588
 696          },
 697         {0}
 698 };
 699
 700 static struct pci_driver pch_driver = {
 701         .name = KBUILD_MODNAME,
 702         .id_table = pch_ieee1588_pcidev_id,
 703         .probe = pch_probe,
 704         .remove = pch_remove,
 705         .suspend = pch_suspend,
 706         .resume = pch_resume,
 707 };
 708
 709 static void __exit ptp_pch_exit(void)
 710 {
 711         pci_unregister_driver(&pch_driver);
 712 }
 713
 714 static s32 __init ptp_pch_init(void)
 715 {
 716         s32 ret;
 717
 718         /* register the driver with the pci core */
 719         ret = pci_register_driver(&pch_driver);
 720
 721         return ret;
 722 }
 723
 724 module_init(ptp_pch_init);
 725 module_exit(ptp_pch_exit);
 726
 727 module_param_string(station, pch_param.station, sizeof pch_param.station, 0444);
 728 MODULE_PARM_DESC(station,
 729          "IEEE 1588 station address to use - column separated hex values");
 730
 731 MODULE_AUTHOR("LAPIS SEMICONDUCTOR, <tshimizu818@gmail.com>");
 732 MODULE_DESCRIPTION("PTP clock using the EG20T timer");
 733 MODULE_LICENSE("GPL");