2 * Intel Low Power Subsystem PWM controller driver
4 * Copyright (C) 2014, Intel Corporation
5 * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
6 * Author: Chew Kean Ho <kean.ho.chew@intel.com>
7 * Author: Chang Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com>
8 * Author: Chew Chiau Ee <chiau.ee.chew@intel.com>
9 * Author: Alan Cox <alan@linux.intel.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #include <linux/delay.h>
18 #include <linux/iopoll.h>
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/time.h>
26 #define PWM 0x00000000
27 #define PWM_ENABLE BIT(31)
28 #define PWM_SW_UPDATE BIT(30)
29 #define PWM_BASE_UNIT_SHIFT 8
30 #define PWM_ON_TIME_DIV_MASK 0x000000ff
32 /* Size of each PWM register space if multiple */
33 #define PWM_SIZE 0x400
35 struct pwm_lpss_chip {
38 const struct pwm_lpss_boardinfo *info;
41 static inline struct pwm_lpss_chip *to_lpwm(struct pwm_chip *chip)
43 return container_of(chip, struct pwm_lpss_chip, chip);
46 static inline u32 pwm_lpss_read(const struct pwm_device *pwm)
48 struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);
50 return readl(lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM);
53 static inline void pwm_lpss_write(const struct pwm_device *pwm, u32 value)
55 struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);
57 writel(value, lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM);
60 static int pwm_lpss_update(struct pwm_device *pwm)
62 struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);
63 const void __iomem *addr = lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM;
64 const unsigned int ms = 500 * USEC_PER_MSEC;
68 pwm_lpss_write(pwm, pwm_lpss_read(pwm) | PWM_SW_UPDATE);
71 * PWM Configuration register has SW_UPDATE bit that is set when a new
72 * configuration is written to the register. The bit is automatically
73 * cleared at the start of the next output cycle by the IP block.
75 * If one writes a new configuration to the register while it still has
76 * the bit enabled, PWM may freeze. That is, while one can still write
77 * to the register, it won't have an effect. Thus, we try to sleep long
78 * enough that the bit gets cleared and make sure the bit is not
79 * enabled while we update the configuration.
81 err = readl_poll_timeout(addr, val, !(val & PWM_SW_UPDATE), 40, ms);
83 dev_err(pwm->chip->dev, "PWM_SW_UPDATE was not cleared\n");
88 static inline int pwm_lpss_is_updating(struct pwm_device *pwm)
90 return (pwm_lpss_read(pwm) & PWM_SW_UPDATE) ? -EBUSY : 0;
93 static void pwm_lpss_prepare(struct pwm_lpss_chip *lpwm, struct pwm_device *pwm,
94 int duty_ns, int period_ns)
96 unsigned long long on_time_div;
97 unsigned long c = lpwm->info->clk_rate, base_unit_range;
98 unsigned long long base_unit, freq = NSEC_PER_SEC;
101 do_div(freq, period_ns);
105 * base_unit = round(base_unit_range * freq / c)
107 base_unit_range = BIT(lpwm->info->base_unit_bits) - 1;
108 freq *= base_unit_range;
110 base_unit = DIV_ROUND_CLOSEST_ULL(freq, c);
112 on_time_div = 255ULL * duty_ns;
113 do_div(on_time_div, period_ns);
114 on_time_div = 255ULL - on_time_div;
116 ctrl = pwm_lpss_read(pwm);
117 ctrl &= ~PWM_ON_TIME_DIV_MASK;
118 ctrl &= ~(base_unit_range << PWM_BASE_UNIT_SHIFT);
119 base_unit &= base_unit_range;
120 ctrl |= (u32) base_unit << PWM_BASE_UNIT_SHIFT;
122 pwm_lpss_write(pwm, ctrl);
125 static int pwm_lpss_apply(struct pwm_chip *chip, struct pwm_device *pwm,
126 struct pwm_state *state)
128 struct pwm_lpss_chip *lpwm = to_lpwm(chip);
131 if (state->enabled) {
132 if (!pwm_is_enabled(pwm)) {
133 pm_runtime_get_sync(chip->dev);
134 ret = pwm_lpss_is_updating(pwm);
136 pm_runtime_put(chip->dev);
139 pwm_lpss_prepare(lpwm, pwm, state->duty_cycle, state->period);
140 ret = pwm_lpss_update(pwm);
142 pm_runtime_put(chip->dev);
145 pwm_lpss_write(pwm, pwm_lpss_read(pwm) | PWM_ENABLE);
147 ret = pwm_lpss_is_updating(pwm);
150 pwm_lpss_prepare(lpwm, pwm, state->duty_cycle, state->period);
151 return pwm_lpss_update(pwm);
153 } else if (pwm_is_enabled(pwm)) {
154 pwm_lpss_write(pwm, pwm_lpss_read(pwm) & ~PWM_ENABLE);
155 pm_runtime_put(chip->dev);
161 static const struct pwm_ops pwm_lpss_ops = {
162 .apply = pwm_lpss_apply,
163 .owner = THIS_MODULE,
166 struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev, struct resource *r,
167 const struct pwm_lpss_boardinfo *info)
169 struct pwm_lpss_chip *lpwm;
173 lpwm = devm_kzalloc(dev, sizeof(*lpwm), GFP_KERNEL);
175 return ERR_PTR(-ENOMEM);
177 lpwm->regs = devm_ioremap_resource(dev, r);
178 if (IS_ERR(lpwm->regs))
179 return ERR_CAST(lpwm->regs);
183 c = lpwm->info->clk_rate;
185 return ERR_PTR(-EINVAL);
187 lpwm->chip.dev = dev;
188 lpwm->chip.ops = &pwm_lpss_ops;
189 lpwm->chip.base = -1;
190 lpwm->chip.npwm = info->npwm;
192 ret = pwmchip_add(&lpwm->chip);
194 dev_err(dev, "failed to add PWM chip: %d\n", ret);
200 EXPORT_SYMBOL_GPL(pwm_lpss_probe);
202 int pwm_lpss_remove(struct pwm_lpss_chip *lpwm)
204 return pwmchip_remove(&lpwm->chip);
206 EXPORT_SYMBOL_GPL(pwm_lpss_remove);
208 MODULE_DESCRIPTION("PWM driver for Intel LPSS");
209 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
210 MODULE_LICENSE("GPL v2");