drivers/regulator/pfuze100-regulator.c

   1 /*
   2  * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  17  */
  18 #include <linux/mfd/pfuze.h>
  19 #include <linux/regulator/machine.h>
  20 #include <linux/regulator/driver.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/kernel.h>
  23 #include <linux/slab.h>
  24 #include <linux/init.h>
  25 #include <linux/err.h>
  26 #include "pfuze-regulator.h"
  27
  28 static const int pfuze100_sw1[] = {
  29 #ifdef PFUZE100_FIRST_VERSION
  30         650000, 662500, 675000, 687500, 700000, 712500, 725000, 737500,
  31         750000, 762500, 775000, 787500, 800000, 812500, 825000, 837500,
  32         850000, 862500, 875000, 887500, 900000, 912500, 925000, 937500,
  33         950000, 962500, 975000, 987500, 1000000, 1012500, 1025000, 1037500,
  34         1050000, 1062500, 1075000, 1087500, 1100000, 1112500, 1125000, 1137500,
  35         1150000, 1162500, 1175000, 1187500, 1200000, 1212500, 1225000, 1237500,
  36         1250000, 1262500, 1275000, 1287500, 1300000, 1312500, 1325000, 1337500,
  37         1350000, 1362500, 1375000, 1387500, 1400000, 1412500, 1425000, 1437500,
  38 #else
  39         300000, 325000, 350000, 375000, 400000, 425000, 450000, 475000,
  40         500000, 525000, 550000, 575000, 600000, 625000, 650000, 675000,
  41         700000, 725000, 750000, 775000, 800000, 825000, 850000, 875000,
  42         900000, 925000, 950000, 975000, 1000000, 1025000, 1050000, 1075000,
  43         1100000, 1125000, 1150000, 1175000, 1200000, 1225000, 1250000, 1275000,
  44         1300000, 1325000, 1350000, 1375000, 1400000, 1425000, 1450000, 1475000,
  45         1500000, 1525000, 1550000, 1575000, 1600000, 1625000, 1650000, 1675000,
  46         1700000, 1725000, 1750000, 1775000, 1800000, 1825000, 1850000, 1875000,
  47 #endif
  48 };
  49
  50 #if  PFUZE100_SW2_VOL6
  51 static const int pfuze100_sw2[] = {
  52         800000, 850000, 900000, 950000, 1000000, 1050000, 1100000, 1150000,
  53         1200000, 1250000, 1300000, 1350000, 1400000, 1450000, 1500000, 1550000,
  54         1600000, 1650000, 1700000, 1750000, 1800000, 1850000, 1900000, 1950000,
  55         2000000, 2050000, 2100000, 2150000, 2200000, 2250000, 2300000, 2350000,
  56         2400000, 2450000, 2500000, 2550000, 2600000, 2650000, 2700000, 2750000,
  57         2800000, 2850000, 2900000, 2950000, 3000000, 3050000, 3100000, 3150000,
  58         3200000, 3250000, 3300000, 3300000, 3300000, 3300000, 3300000, 3300000,
  59         3300000, 3300000, 3300000, 3300000, 3300000, 3300000, 3300000, 3950000,
  60 };
  61 #else
  62 static const int pfuze100_sw2[] = {
  63         400000, 425000, 450000, 475000, 500000, 525000, 550000, 575000,
  64         600000, 625000, 650000, 675000, 700000, 725000, 750000, 775000,
  65         800000, 825000, 850000, 875000, 900000, 925000, 950000, 975000,
  66         1000000, 1025000, 1050000, 1075000, 1100000, 1125000, 1150000, 1175000,
  67         1200000, 1225000, 1250000, 1275000, 1300000, 1325000, 1350000, 1375000,
  68         1400000, 1425000, 1450000, 1475000, 1500000, 1525000, 1550000, 1575000,
  69         1600000, 1625000, 1650000, 1675000, 1700000, 1725000, 1750000, 1775000,
  70         1800000, 1825000, 1850000, 1875000, 1900000, 1925000, 1950000, 1975000,
  71 };
  72 #endif
  73
  74 #if PFUZE100_SW3_VOL6
  75 static const int pfuze100_sw3[] = {
  76         800000, 850000, 900000, 950000, 1000000, 1050000, 1100000, 1150000,
  77         1200000, 1250000, 1300000, 1350000, 1400000, 1450000, 1500000, 1550000,
  78         1600000, 1650000, 1700000, 1750000, 1800000, 1850000, 1900000, 1950000,
  79         2000000, 2050000, 2100000, 2150000, 2200000, 2250000, 2300000, 2350000,
  80         2400000, 2450000, 2500000, 2550000, 2600000, 2650000, 2700000, 2750000,
  81         2800000, 2850000, 2900000, 2950000, 3000000, 3050000, 3100000, 3150000,
  82         3200000, 3250000, 3300000, 3300000, 3300000, 3300000, 3300000, 3300000,
  83         3300000, 3300000, 3300000, 3750000, 3800000, 3850000, 3900000, 3950000,
  84 };
  85 #else
  86 static const int pfuze100_sw3[] = {
  87         400000, 425000, 450000, 475000, 500000, 525000, 550000, 575000,
  88         600000, 625000, 650000, 675000, 700000, 725000, 750000, 775000,
  89         800000, 825000, 850000, 875000, 900000, 925000, 950000, 975000,
  90         1000000, 1025000, 1050000, 1075000, 1100000, 1125000, 1150000, 1175000,
  91         1200000, 1225000, 1250000, 1275000, 1300000, 1325000, 1350000, 1375000,
  92         1400000, 1425000, 1450000, 1475000, 1500000, 1525000, 1550000, 1575000,
  93         1600000, 1625000, 1650000, 1675000, 1700000, 1725000, 1750000, 1775000,
  94         1800000, 1825000, 1850000, 1875000, 1900000, 1925000, 1950000, 1975000,
  95 };
  96 #endif
  97
  98 #if PFUZE100_SW4_VOL6
  99 static const int pfuze100_sw4[] = {
 100         800000, 850000, 900000, 950000, 1000000, 1050000, 1100000, 1150000,
 101         1200000, 1250000, 1300000, 1350000, 1400000, 1450000, 1500000, 1550000,
 102         1600000, 1650000, 1700000, 1750000, 1800000, 1850000, 1900000, 1950000,
 103         2000000, 2050000, 2100000, 2150000, 2200000, 2250000, 2300000, 2350000,
 104         2400000, 2450000, 2500000, 2550000, 2600000, 2650000, 2700000, 2750000,
 105         2800000, 2850000, 2900000, 2950000, 3000000, 3050000, 3100000, 3150000,
 106         3200000, 3250000, 3300000, 3300000, 3300000, 3300000, 3300000, 3300000,
 107         3300000, 3300000, 3300000, 3300000, 3300000, 3300000, 3300000, 3950000,
 108 };
 109
 110 #else
 111 static const int pfuze100_sw4[] = {
 112         400000, 425000, 450000, 475000, 500000, 525000, 550000, 575000,
 113         600000, 625000, 650000, 675000, 700000, 725000, 750000, 775000,
 114         800000, 825000, 850000, 875000, 900000, 925000, 950000, 975000,
 115         1000000, 1025000, 1050000, 1075000, 1100000, 1125000, 1150000, 1175000,
 116         1200000, 1225000, 1250000, 1275000, 1300000, 1325000, 1350000, 1375000,
 117         1400000, 1425000, 1450000, 1475000, 1500000, 1525000, 1550000, 1575000,
 118         1600000, 1625000, 1650000, 1675000, 1700000, 1725000, 1750000, 1775000,
 119         1800000, 1825000, 1850000, 1875000, 1900000, 1925000, 1950000, 1975000,
 120 };
 121 #endif
 122
 123 static const int pfuze100_swbst[] = {
 124         5000000, 5050000, 5100000, 5150000,
 125 };
 126
 127 static const int pfuze100_vsnvs[] = {
 128         1200000, 1500000, 1800000, 3000000,
 129 };
 130
 131 static const int pfuze100_vrefddr[] = {
 132         750000,
 133 };
 134
 135 static const int pfuze100_vgen12[] = {
 136
 137 #ifdef PFUZE100_FIRST_VERSION
 138         1200000, 1250000, 1300000, 1350000, 1400000, 1450000, 1500000, 1550000,
 139 #else
 140         800000, 850000, 900000, 950000, 1000000, 1050000, 1100000, 1150000,
 141         1200000, 1250000, 1300000, 1350000, 1400000, 1450000, 1500000, 1550000,
 142 #endif
 143 };
 144
 145 static const int pfuze100_vgen36[] = {
 146         1800000, 1900000, 2000000, 2100000, 2200000, 2300000, 2400000, 2500000,
 147         2600000, 2700000, 2800000, 2900000, 3000000, 3100000, 3200000, 3300000,
 148 };
 149
 150 static struct regulator_ops pfuze100_ldo_regulator_ops;
 151 static struct regulator_ops pfuze100_fixed_regulator_ops;
 152 static struct regulator_ops pfuze100_sw_regulator_ops;
 153
 154 #define PFUZE100_FIXED_VOL_DEFINE(name, reg, voltages)          \
 155         PFUZE_FIXED_DEFINE(PFUZE100_, name, reg, voltages,      \
 156                         pfuze100_fixed_regulator_ops)
 157
 158 #define PFUZE100_SW_DEFINE(name, reg, voltages) \
 159         PFUZE_SW_DEFINE(PFUZE100_, name, reg, voltages, \
 160                         pfuze100_sw_regulator_ops)
 161
 162 #define PFUZE100_VGEN_DEFINE(name, reg, voltages)       \
 163         PFUZE_DEFINE(PFUZE100_, name, reg, voltages,    \
 164                         pfuze100_ldo_regulator_ops)
 165 /* SW1A */
 166 #define PFUZE100_SW1AVOL        32
 167 #define PFUZE100_SW1AVOL_VSEL   0
 168 #define PFUZE100_SW1AVOL_VSEL_M (0x3f<<0)
 169
 170 #define PFUZE100_SW1ASTANDBY    33
 171 #define PFUZE100_SW1ASTANDBY_STBY_VAL   (0x14)
 172 #define PFUZE100_SW1ASTANDBY_STBY_M     (0x3f<<0)
 173
 174 #define PFUZE100_SW1AOFF        34
 175 #define PFUZE100_SW1AOFF_OFF_VAL        (0x0<<0)
 176 #define PFUZE100_SW1AOFF_OFF_M  (0x3f<<0)
 177
 178 #define PFUZE100_SW1AMODE       35
 179 #define PFUZE100_SW1AMODE_OMODE_VAL     (0x0<<5)
 180 #define PFUZE100_SW1AMODE_OMODE_M       (0x1<<5)
 181 #define PFUZE100_SW1AMODE_MODE_VAL      0x7     /*Auto */
 182 #define PFUZE100_SW1AMODE_MODE_M        (0xf<<0)
 183
 184 #define PFUZE100_SW1ACON                36
 185 #define PFUZE100_SW1ACON_SPEED_VAL      (0x1<<6)        /*default */
 186 #define PFUZE100_SW1ACON_SPEED_M        (0x3<<6)
 187 #define PFUZE100_SW1ACON_PHASE_VAL      (0x1<<4)        /*default */
 188 #define PFUZE100_SW1ACON_PHASE_M        (0x3<<4)
 189 #define PFUZE100_SW1ACON_FREQ_VAL       (0x1<<2)        /*1Mhz */
 190 #define PFUZE100_SW1ACON_FREQ_M (0x3<<2)
 191 #define PFUZE100_SW1ACON_LIM_VAL        (0x0<<0)        /*2Imax */
 192 #define PFUZE100_SW1ACON_LIM_M  (0x3<<0)
 193
 194 /*SW1B*/
 195 #define PFUZE100_SW1BVOL        39
 196 #define PFUZE100_SW1BVOL_VSEL   0
 197 #define PFUZE100_SW1BVOL_VSEL_M (0x3f<<0)
 198
 199 #define PFUZE100_SW1BSTANDBY    40
 200 #define PFUZE100_SW1BSTANDBY_STBY_VAL   (0x14)
 201 #define PFUZE100_SW1BSTANDBY_STBY_M     (0x3f<<0)
 202
 203 #define PFUZE100_SW1BOFF        41
 204 #define PFUZE100_SW1BOFF_OFF_VAL        0x0
 205 #define PFUZE100_SW1BOFF_OFF_M  (0x3f<<0)
 206
 207 #define PFUZE100_SW1BMODE       42
 208 #define PFUZE100_SW1BMODE_OMODE_VAL     (0x0<<5)
 209 #define PFUZE100_SW1BMODE_OMODE_M       (0x1<<5)
 210 #define PFUZE100_SW1BMODE_MODE_VAL      (0x7<<0)
 211 #define PFUZE100_SW1BMODE_MODE_M        (0xf<<0)
 212
 213 #define PFUZE100_SW1BCON                43
 214 #define PFUZE100_SW1BCON_SPEED_VAL      (0x1<<6)
 215 #define PFUZE100_SW1BCON_SPEED_M        (0x3<<6)
 216 #define PFUZE100_SW1BCON_PHASE_VAL      (0x1<<4)
 217 #define PFUZE100_SW1BCON_PHASE_M        (0x3<<4)
 218 #define PFUZE100_SW1BCON_FREQ_VAL       (0x1<<2)
 219 #define PFUZE100_SW1BCON_FREQ_M (0x3<<2)
 220 #define PFUZE100_SW1BCON_LIM_VAL        (0x0<<0)
 221 #define PFUZE100_SW1BCON_LIM_M  (0x3<<0)
 222
 223 /*SW1C*/
 224 #define PFUZE100_SW1CVOL        46
 225 #define PFUZE100_SW1CVOL_VSEL   0
 226 #define PFUZE100_SW1CVOL_VSEL_M (0x3f<<0)
 227
 228 #define PFUZE100_SW1CSTANDBY    47
 229 #define PFUZE100_SW1CSTANDBY_STBY_VAL   (0x14)
 230 #define PFUZE100_SW1CSTANDBY_STBY_M     (0x3f<<0)
 231
 232 #define PFUZE100_SW1COFF        48
 233 #define PFUZE100_SW1COFF_OFF_VAL        0x0
 234 #define PFUZE100_SW1COFF_OFF_M  (0x3f<<0)
 235
 236 #define PFUZE100_SW1CMODE       49
 237 #define PFUZE100_SW1CMODE_OMODE_VAL     (0x0<<5)
 238 #define PFUZE100_SW1CMODE_OMODE_M       (0x1<<5)
 239 #define PFUZE100_SW1CMODE_MODE_VAL      (0x7<<0)
 240 #define PFUZE100_SW1CMODE_MODE_M        (0xf<<0)
 241
 242 #define PFUZE100_SW1CCON                50
 243 #define PFUZE100_SW1CCON_SPEED_VAL      (0x1<<6)
 244 #define PFUZE100_SW1CCON_SPEED_M        (0x3<<6)
 245 #define PFUZE100_SW1CCON_PHASE_VAL      (0x1<<4)
 246 #define PFUZE100_SW1CCON_PHASE_M        (0x3<<4)
 247 #define PFUZE100_SW1CCON_FREQ_VAL       (0x1<<2)
 248 #define PFUZE100_SW1CCON_FREQ_M         (0x3<<2)
 249 #define PFUZE100_SW1CCON_LIM_VAL        (0x0<<0)
 250 #define PFUZE100_SW1CCON_LIM_M          (0x3<<0)
 251
 252 /*SW2*/
 253 #define PFUZE100_SW2VOL         53
 254 #define PFUZE100_SW2VOL_VSEL    0
 255 #define PFUZE100_SW2VOL_VSEL_M  (0x3f<<0)
 256
 257 #define PFUZE100_SW2STANDBY     54
 258 #define PFUZE100_SW2STANDBY_STBY_VAL    0x0
 259 #define PFUZE100_SW2STANDBY_STBY_M      (0x3f<<0)
 260
 261 #define PFUZE100_SW2OFF 55
 262 #define PFUZE100_SW2OFF_OFF_VAL 0x0
 263 #define PFUZE100_SW2OFF_OFF_M   (0x7f<<0)
 264
 265 #define PFUZE100_SW2MODE        56
 266 #define PFUZE100_SW2MODE_OMODE_VAL      (0x0<<5)
 267 #define PFUZE100_SW2MODE_OMODE_M        (0x1<<5)
 268 #define PFUZE100_SW2MODE_MODE_VAL       (0x7<<0)
 269 #define PFUZE100_SW2MODE_MODE_M         (0xf<<0)
 270
 271 #define PFUZE100_SW2CON         57
 272 #define PFUZE100_SW2CON_SPEED_VAL       (0x1<<6)
 273 #define PFUZE100_SW2CON_SPEED_M         (0x3<<6)
 274 #define PFUZE100_SW2CON_PHASE_VAL       (0x1<<4)
 275 #define PFUZE100_SW2CON_PHASE_M         (0x3<<4)
 276 #define PFUZE100_SW2CON_FREQ_VAL        (0x1<<2)
 277 #define PFUZE100_SW2CON_FREQ_M          (0x3<<2)
 278 #define PFUZE100_SW2CON_LIM_VAL         (0x0<<0)
 279 #define PFUZE100_SW2CON_LIM_M           (0x3<<0)
 280
 281 /*SW3A*/
 282 #define PFUZE100_SW3AVOL        60
 283 #define PFUZE100_SW3AVOL_VSEL   0
 284 #define PFUZE100_SW3AVOL_VSEL_M (0x3f<<0)
 285
 286 #define PFUZE100_SW3ASTANDBY    61
 287 #define PFUZE100_SW3ASTANDBY_STBY_VAL   0x0
 288 #define PFUZE100_SW3ASTANDBY_STBY_M     (0x3f<<0)
 289
 290 #define PFUZE100_SW3AOFF        62
 291 #define PFUZE100_SW3AOFF_OFF_VAL        0x0
 292 #define PFUZE100_SW3AOFF_OFF_M  (0x3f<<0)
 293
 294 #define PFUZE100_SW3AMODE       63
 295 #define PFUZE100_SW3AMODE_OMODE_VAL     (0x0<<5)
 296 #define PFUZE100_SW3AMODE_OMODE_M       (0x1<<5)
 297 #define PFUZE100_SW3AMODE_MODE_VAL      (0x7<<0)
 298 #define PFUZE100_SW3AMODE_MODE_M        (0xf<<0)
 299
 300 #define PFUZE100_SW3ACON                64
 301 #define PFUZE100_SW3ACON_SPEED_VAL      (0x1<<6)
 302 #define PFUZE100_SW3ACON_SPEED_M        (0x3<<6)
 303 #define PFUZE100_SW3ACON_PHASE_VAL      (0x1<<4)
 304 #define PFUZE100_SW3ACON_PHASE_M        (0x3<<4)
 305 #define PFUZE100_SW3ACON_FREQ_VAL       (0x1<<2)
 306 #define PFUZE100_SW3ACON_FREQ_M         (0x3<<2)
 307 #define PFUZE100_SW3ACON_LIM_VAL        (0x0<<0)
 308 #define PFUZE100_SW3ACON_LIM_M          (0x3<<0)
 309
 310 /*SW3B*/
 311 #define PFUZE100_SW3BVOL        67
 312 #define PFUZE100_SW3BVOL_VSEL   0
 313 #define PFUZE100_SW3BVOL_VSEL_M (0x3f<<0)
 314
 315 #define PFUZE100_SW3BSTANDBY    68
 316 #define PFUZE100_SW3BSTANDBY_STBY_VAL   0x0
 317 #define PFUZE100_SW3BSTANDBY_STBY_M     (0x3f<<0)
 318
 319 #define PFUZE100_SW3BOFF        69
 320 #define PFUZE100_SW3BOFF_OFF_VAL        0x0
 321 #define PFUZE100_SW3BOFF_OFF_M  (0x3f<<0)
 322
 323 #define PFUZE100_SW3BMODE       70
 324 #define PFUZE100_SW3BMODE_OMODE_VAL     (0x0<<5)
 325 #define PFUZE100_SW3BMODE_OMODE_M       (0x1<<5)
 326 #define PFUZE100_SW3BMODE_MODE_VAL      (0x7<<0)
 327 #define PFUZE100_SW3BMODE_MODE_M        (0xf<<0)
 328
 329 #define PFUZE100_SW3BCON                71
 330 #define PFUZE100_SW3BCON_SPEED_VAL      (0x1<<6)
 331 #define PFUZE100_SW3BCON_SPEED_M        (0x3<<6)
 332 #define PFUZE100_SW3BCON_PHASE_VAL      (0x1<<4)
 333 #define PFUZE100_SW3BCON_PHASE_M        (0x3<<4)
 334 #define PFUZE100_SW3BCON_FREQ_VAL       (0x1<<2)
 335 #define PFUZE100_SW3BCON_FREQ_M         (0x3<<2)
 336 #define PFUZE100_SW3BCON_LIM_VAL        (0x0<<0)
 337 #define PFUZE100_SW3BCON_LIM_M          (0x3<<0)
 338
 339 /*SW4*/
 340 #define PFUZE100_SW4VOL         74
 341 #define PFUZE100_SW4VOL_VSEL    0
 342 #define PFUZE100_SW4VOL_VSEL_M  (0x3f<<0)
 343
 344 #define PFUZE100_SW4STANDBY     75
 345 #define PFUZE100_SW4STANDBY_STBY_VAL    0
 346 #define PFUZE100_SW4STANDBY_STBY_M      (0x3f<<0)
 347
 348 #define PFUZE100_SW4OFF         76
 349 #define PFUZE100_SW4OFF_OFF_VAL 0x0
 350 #define PFUZE100_SW4OFF_OFF_M   (0x3f<<0)
 351
 352 #define PFUZE100_SW4MODE        77
 353 #define PFUZE100_SW4MODE_OMODE_VAL      (0x0<<5)
 354 #define PFUZE100_SW4MODE_OMODE_M        (0x1<<5)
 355 #define PFUZE100_SW4MODE_MODE_VAL       (0x7<<0)
 356 #define PFUZE100_SW4MODE_MODE_M         (0xf<<0)
 357
 358 #define PFUZE100_SW4CON         78
 359 #define PFUZE100_SW4CON_SPEED_VAL       (0x1<<6)
 360 #define PFUZE100_SW4CON_SPEED_M         (0x3<<6)
 361 #define PFUZE100_SW4CON_PHASE_VAL       (0x1<<4)
 362 #define PFUZE100_SW4CON_PHASE_M         (0x3<<4)
 363 #define PFUZE100_SW4CON_FREQ_VAL        (0x1<<2)
 364 #define PFUZE100_SW4CON_FREQ_M          (0x3<<2)
 365 #define PFUZE100_SW4CON_LIM_VAL         (0x0<<0)
 366 #define PFUZE100_SW4CON_LIM_M           (0x3<<0)
 367
 368  /*SWBST*/
 369 #define PFUZE100_SWBSTCON1      102
 370 #define PFUZE100_SWBSTCON1_STBY_VAL     0x0
 371 #define PFUZE100_SWBSTCON1_STBY_M       (0x3<<5)
 372 #define PFUZE100_SWBSTCON1_SWBSTMOD_VAL (0x1<<2)
 373 #define PFUZE100_SWBSTCON1_SWBSTMOD_M   (0x3<<2)
 374 #define PFUZE100_SWBSTCON1_VSEL 0
 375 #define PFUZE100_SWBSTCON1_VSEL_M       (0x3<<0)
 376      /*VREFDDR*/
 377 #define PFUZE100_VREFDDRCON     106
 378 #define PFUZE100_VREFDDRCON_EN  (0x1<<4)
 379      /*VSNVS*/
 380 #define PFUZE100_VSNVSVOL               107
 381 #define PFUZE100_VSNVSVOL_VSEL  0
 382 #define PFUZE100_VSNVSVOL_VSEL_M        (0x3<<0)
 383 /*VGEN1*/
 384 #define PFUZE100_VGEN1VOL               108
 385 #define PFUZE100_VGEN1VOL_STBY_VAL      0x0
 386 #define PFUZE100_VGEN1VOL_STBY_M        (0x1<<5)
 387 #define PFUZE100_VGEN1VOL_EN    (0x1<<4)
 388 #define PFUZE100_VGEN1VOL_VSEL  0
 389 #ifdef PFUZE100_FIRST_VERSION
 390 #define PFUZE100_VGEN1VOL_VSEL_M        (0x7<<0)
 391 #else
 392 #define PFUZE100_VGEN1VOL_VSEL_M        (0xf<<0)
 393 #endif
 394 /*VGEN2*/
 395 #define PFUZE100_VGEN2VOL               109
 396 #define PFUZE100_VGEN2VOL_STBY_VAL      0x0
 397 #define PFUZE100_VGEN2VOL_STBY_M        (0x1<<5)
 398 #define PFUZE100_VGEN2VOL_EN    (0x1<<4)
 399 #define PFUZE100_VGEN2VOL_VSEL  0
 400 #ifdef PFUZE100_FIRST_VERSION
 401 #define PFUZE100_VGEN2VOL_VSEL_M        (0x7<<0)
 402 #else
 403 #define PFUZE100_VGEN2VOL_VSEL_M        (0xf<<0)
 404 #endif
 405 /*VGEN3*/
 406 #define PFUZE100_VGEN3VOL               110
 407 #define PFUZE100_VGEN3VOL_STBY_VAL      0x0
 408 #define PFUZE100_VGEN3VOL_STBY_M        (0x1<<5)
 409 #define PFUZE100_VGEN3VOL_EN    (0x1<<4)
 410 #define PFUZE100_VGEN3VOL_VSEL  0
 411 #define PFUZE100_VGEN3VOL_VSEL_M        (0xf<<0)
 412 /*VGEN4*/
 413 #define PFUZE100_VGEN4VOL               111
 414 #define PFUZE100_VGEN4VOL_STBY_VAL      0x0
 415 #define PFUZE100_VGEN4VOL_STBY_M        (0x1<<5)
 416 #define PFUZE100_VGEN4VOL_EN    (0x1<<4)
 417 #define PFUZE100_VGEN4VOL_VSEL  0
 418 #define PFUZE100_VGEN4VOL_VSEL_M        (0xf<<0)
 419 /*VGEN5*/
 420 #define PFUZE100_VGEN5VOL               112
 421 #define PFUZE100_VGEN5VOL_STBY_VAL      0x0
 422 #define PFUZE100_VGEN5VOL_STBY_M        (0x1<<5)
 423 #define PFUZE100_VGEN5VOL_EN    (0x1<<4)
 424 #define PFUZE100_VGEN5VOL_VSEL  0
 425 #define PFUZE100_VGEN5VOL_VSEL_M        (0xf<<0)
 426 /*VGEN6*/
 427 #define PFUZE100_VGEN6VOL               113
 428 #define PFUZE100_VGEN6VOL_STBY_VAL      0x0
 429 #define PFUZE100_VGEN6VOL_STBY_M        (0x1<<5)
 430 #define PFUZE100_VGEN6VOL_EN    (0x1<<4)
 431 #define PFUZE100_VGEN6VOL_VSEL  0
 432 #define PFUZE100_VGEN6VOL_VSEL_M        (0xf<<0)
 433 static struct pfuze_regulator pfuze100_regulators[] = {
 434         PFUZE100_SW_DEFINE(SW1A, SW1AVOL, pfuze100_sw1),
 435         PFUZE100_SW_DEFINE(SW1B, SW1BVOL, pfuze100_sw1),
 436         PFUZE100_SW_DEFINE(SW1C, SW1CVOL, pfuze100_sw1),
 437         PFUZE100_SW_DEFINE(SW2, SW2VOL, pfuze100_sw2),
 438         PFUZE100_SW_DEFINE(SW3A, SW3AVOL, pfuze100_sw3),
 439         PFUZE100_SW_DEFINE(SW3B, SW3BVOL, pfuze100_sw3),
 440         PFUZE100_SW_DEFINE(SW4, SW4VOL, pfuze100_sw4),
 441         PFUZE100_SW_DEFINE(SWBST, SWBSTCON1, pfuze100_swbst),
 442         PFUZE100_SW_DEFINE(VSNVS, VSNVSVOL, pfuze100_vsnvs),
 443         PFUZE100_FIXED_VOL_DEFINE(VREFDDR, VREFDDRCON, pfuze100_vrefddr),
 444         PFUZE100_VGEN_DEFINE(VGEN1, VGEN1VOL, pfuze100_vgen12),
 445         PFUZE100_VGEN_DEFINE(VGEN2, VGEN2VOL, pfuze100_vgen12),
 446         PFUZE100_VGEN_DEFINE(VGEN3, VGEN3VOL, pfuze100_vgen36),
 447         PFUZE100_VGEN_DEFINE(VGEN4, VGEN4VOL, pfuze100_vgen36),
 448         PFUZE100_VGEN_DEFINE(VGEN5, VGEN5VOL, pfuze100_vgen36),
 449         PFUZE100_VGEN_DEFINE(VGEN6, VGEN6VOL, pfuze100_vgen36),
 450 };
 451
 452 static int pfuze100_regulator_enable(struct regulator_dev *rdev)
 453 {
 454         struct pfuze_regulator_priv *priv = rdev_get_drvdata(rdev);
 455         int id = rdev_get_id(rdev);
 456         int ret;
 457
 458         dev_dbg(rdev_get_dev(rdev), "%s id: %d\n", __func__, id);
 459         pfuze_lock(priv->pfuze);
 460         ret = pfuze_reg_rmw(priv->pfuze, pfuze100_regulators[id].reg,
 461                             pfuze100_regulators[id].enable_bit,
 462                             pfuze100_regulators[id].enable_bit);
 463         pfuze_unlock(priv->pfuze);
 464         return ret;
 465 }
 466
 467 static int pfuze100_regulator_disable(struct regulator_dev *rdev)
 468 {
 469         struct pfuze_regulator_priv *priv = rdev_get_drvdata(rdev);
 470         int id = rdev_get_id(rdev);
 471         int ret;
 472
 473         dev_dbg(rdev_get_dev(rdev), "%s id: %d\n", __func__, id);
 474         pfuze_lock(priv->pfuze);
 475         ret = pfuze_reg_rmw(priv->pfuze, pfuze100_regulators[id].reg,
 476                             pfuze100_regulators[id].enable_bit, 0);
 477         pfuze_unlock(priv->pfuze);
 478         return ret;
 479 }
 480
 481 static int pfuze100_regulator_is_enabled(struct regulator_dev *rdev)
 482 {
 483         struct pfuze_regulator_priv *priv = rdev_get_drvdata(rdev);
 484         int id = rdev_get_id(rdev);
 485         int ret;
 486         unsigned char val;
 487
 488         pfuze_lock(priv->pfuze);
 489         ret = pfuze_reg_read(priv->pfuze, pfuze100_regulators[id].reg, &val);
 490         pfuze_unlock(priv->pfuze);
 491         if (ret)
 492                 return ret;
 493         dev_dbg(rdev_get_dev(rdev), "%s id: %d\n", __func__, id);
 494         return (val & pfuze100_regulators[id].enable_bit) != 0;
 495 }
 496
 497 int pfuze100_regulator_list_voltage(struct regulator_dev *rdev,
 498                                     unsigned selector)
 499 {
 500         int id = rdev_get_id(rdev);
 501
 502         if (selector >= pfuze100_regulators[id].desc.n_voltages)
 503                 return -EINVAL;
 504         return pfuze100_regulators[id].voltages[selector];
 505 }
 506
 507 int pfuze100_get_best_voltage_index(struct regulator_dev *rdev, int min_uV,
 508                                     int max_uV)
 509 {
 510         int reg_id = rdev_get_id(rdev);
 511         int i, bestmatch, bestindex;
 512
 513         bestmatch = INT_MAX;
 514         bestindex = -1;
 515         for (i = 0; i < pfuze100_regulators[reg_id].desc.n_voltages; i++) {
 516                 if (pfuze100_regulators[reg_id].voltages[i] >= min_uV &&
 517                     pfuze100_regulators[reg_id].voltages[i] < bestmatch) {
 518                         bestmatch = pfuze100_regulators[reg_id].voltages[i];
 519                         bestindex = i;
 520                 }
 521         }
 522         if (bestindex < 0 || bestmatch > max_uV) {
 523                 dev_warn(&rdev->dev, "no possible value for %d<=x<=%d uV\n",
 524                          min_uV, max_uV);
 525                 return -EINVAL;
 526         }
 527         return bestindex;
 528 }
 529
 530 EXPORT_SYMBOL_GPL(pfuze100_get_best_voltage_index);
 531
 532 static int
 533 pfuze100_regulator_set_voltage(struct regulator_dev *rdev, int min_uV,
 534                                int max_uV, unsigned *selector)
 535 {
 536
 537         struct pfuze_regulator_priv *priv = rdev_get_drvdata(rdev);
 538         int value, id = rdev_get_id(rdev);
 539         int ret;
 540
 541         dev_dbg(rdev_get_dev(rdev), "%s id: %d min_uV: %d max_uV: %d\n",
 542                 __func__, id, min_uV, max_uV);
 543         /* Find the best index */
 544         value = pfuze100_get_best_voltage_index(rdev, min_uV, max_uV);
 545         dev_dbg(rdev_get_dev(rdev), "%s best value: %d\n", __func__, value);
 546         if (value < 0)
 547                 return value;
 548         pfuze_lock(priv->pfuze);
 549         ret = pfuze_reg_rmw(priv->pfuze, pfuze100_regulators[id].reg,
 550                             pfuze100_regulators[id].vsel_mask,
 551                             value << pfuze100_regulators[id].vsel_shift);
 552         pfuze_unlock(priv->pfuze);
 553         return ret;
 554
 555 }
 556
 557 static int pfuze100_regulator_get_voltage(struct regulator_dev *rdev)
 558 {
 559         struct pfuze_regulator_priv *priv = rdev_get_drvdata(rdev);
 560         int ret, id = rdev_get_id(rdev);
 561         unsigned char val;
 562
 563         dev_dbg(rdev_get_dev(rdev), "%s id: %d\n", __func__, id);
 564         pfuze_lock(priv->pfuze);
 565         ret = pfuze_reg_read(priv->pfuze, pfuze100_regulators[id].reg, &val);
 566         pfuze_unlock(priv->pfuze);
 567         if (ret)
 568                 return ret;
 569         val = (val & pfuze100_regulators[id].vsel_mask)
 570             >> pfuze100_regulators[id].vsel_shift;
 571         dev_dbg(rdev_get_dev(rdev), "%s id: %d val: %d\n", __func__, id, val);
 572         BUG_ON(val > pfuze100_regulators[id].desc.n_voltages);
 573         return pfuze100_regulators[id].voltages[val];
 574 }
 575
 576 static struct regulator_ops pfuze100_ldo_regulator_ops = {
 577         .enable = pfuze100_regulator_enable,
 578         .disable = pfuze100_regulator_disable,
 579         .is_enabled = pfuze100_regulator_is_enabled,
 580         .list_voltage = pfuze100_regulator_list_voltage,
 581         .set_voltage = pfuze100_regulator_set_voltage,
 582         .get_voltage = pfuze100_regulator_get_voltage,
 583 };
 584
 585 static int pfuze100_fixed_regulator_set_voltage(struct regulator_dev *rdev,
 586                                                 int min_uV, int max_uV,
 587                                                 unsigned *selector)
 588 {
 589         int id = rdev_get_id(rdev);
 590
 591         dev_dbg(rdev_get_dev(rdev), "%s id: %d min_uV: %d max_uV: %d\n",
 592                 __func__, id, min_uV, max_uV);
 593         if (min_uV >= pfuze100_regulators[id].voltages[0] &&
 594             max_uV <= pfuze100_regulators[id].voltages[0])
 595                 return 0;
 596         else
 597                 return -EINVAL;
 598
 599 }
 600
 601 static int pfuze100_fixed_regulator_get_voltage(struct regulator_dev *rdev)
 602 {
 603         int id = rdev_get_id(rdev);
 604
 605         dev_dbg(rdev_get_dev(rdev), "%s id: %d\n", __func__, id);
 606         return pfuze100_regulators[id].voltages[0];
 607 }
 608
 609 static struct regulator_ops pfuze100_fixed_regulator_ops = {
 610         .enable = pfuze100_regulator_enable,
 611         .disable = pfuze100_regulator_disable,
 612         .is_enabled = pfuze100_regulator_is_enabled,
 613         .set_voltage = pfuze100_fixed_regulator_set_voltage,
 614         .get_voltage = pfuze100_fixed_regulator_get_voltage,
 615 };
 616
 617 static int pfuze100_sw_regulator_is_enabled(struct regulator_dev *rdev)
 618 {
 619         return 1;
 620 }
 621
 622 static struct regulator_ops pfuze100_sw_regulator_ops = {
 623         .is_enabled = pfuze100_sw_regulator_is_enabled,
 624         .list_voltage = pfuze100_regulator_list_voltage,
 625         .set_voltage = pfuze100_regulator_set_voltage,
 626         .get_voltage = pfuze100_regulator_get_voltage,
 627 };
 628
 629 static int __devinit pfuze100_regulator_probe(struct platform_device *pdev)
 630 {
 631         struct pfuze_regulator_priv *priv;
 632         struct mc_pfuze *pfuze100 = dev_get_drvdata(pdev->dev.parent);
 633         struct pfuze_regulator_platform_data *pdata =
 634             dev_get_platdata(&pdev->dev);
 635         struct pfuze_regulator_init_data *init_data;
 636         int i, ret;
 637         struct regulator *enabled_regulator;
 638
 639         priv = kzalloc(sizeof(*priv) +
 640                        pdata->num_regulators * sizeof(priv->regulators[0]),
 641                        GFP_KERNEL);
 642         if (!priv)
 643                 return -ENOMEM;
 644         priv->pfuze_regulators = pfuze100_regulators;
 645         priv->pfuze = pfuze100;
 646         pfuze_lock(pfuze100);
 647         ret = pfuze_reg_rmw(pfuze100, PFUZE100_SWBSTCON1,
 648                             PFUZE100_SWBSTCON1_SWBSTMOD_M,
 649                             PFUZE100_SWBSTCON1_SWBSTMOD_VAL);
 650         if (ret)
 651                 goto err_free;
 652         ret = pfuze_reg_rmw(pfuze100, PFUZE100_SW1ASTANDBY,
 653                             PFUZE100_SW1ASTANDBY_STBY_M,
 654                             PFUZE100_SW1ASTANDBY_STBY_VAL);
 655         if (ret)
 656                 goto err_free;
 657         ret = pfuze_reg_rmw(pfuze100, PFUZE100_SW1BSTANDBY,
 658                             PFUZE100_SW1BSTANDBY_STBY_M,
 659                             PFUZE100_SW1BSTANDBY_STBY_VAL);
 660         if (ret)
 661                 goto err_free;
 662         ret = pfuze_reg_rmw(pfuze100, PFUZE100_SW1CSTANDBY,
 663                             PFUZE100_SW1CSTANDBY_STBY_M,
 664                             PFUZE100_SW1CSTANDBY_STBY_VAL);
 665         if (ret)
 666                 goto err_free;
 667         pfuze_unlock(pfuze100);
 668         for (i = 0; i < pdata->num_regulators; i++) {
 669                 init_data = &pdata->regulators[i];
 670                 priv->regulators[i] =
 671                     regulator_register(&pfuze100_regulators[init_data->id].desc,
 672                                        &pdev->dev, init_data->init_data, priv);
 673                 if (IS_ERR(priv->regulators[i])) {
 674                         dev_err(&pdev->dev, "failed to register regulator %s\n",
 675                                 pfuze100_regulators[i].desc.name);
 676                         ret = PTR_ERR(priv->regulators[i]);
 677                         goto err;
 678                 }
 679         }
 680
 681         enabled_regulator = regulator_get(&pdev->dev, "P1V325_VDDARM_SW1AB");
 682         if (enabled_regulator)
 683                 regulator_set_voltage(enabled_regulator, 1325000, 1325000);
 684         enabled_regulator = regulator_get(&pdev->dev, "P1V325_VDDSOC_SW1C");
 685         if (enabled_regulator)
 686                 regulator_set_voltage(enabled_regulator, 1325000, 1325000);
 687 #if 0
 688         test_regulator = regulator_get(&pdev->dev, "P3V0_VDDHIGH_SW2");
 689         if (test_regulator)
 690                 regulator_set_voltage(test_regulator, 3000000, 3000000);
 691         test_regulator = regulator_get(&pdev->dev, "P1V5_DDR_SW3");
 692         if (test_regulator)
 693                 regulator_set_voltage(test_regulator, 1500000, 1500000);
 694         test_regulator = regulator_get(&pdev->dev, "P1V8_SW4");
 695         if (test_regulator)
 696                 regulator_set_voltage(test_regulator, 1800000, 1800000);
 697         test_regulator = regulator_get(&pdev->dev, "P5V0_SWBST");
 698         if (test_regulator)
 699                 regulator_set_voltage(test_regulator, 5000000, 5000000);
 700         test_regulator = regulator_get(&pdev->dev, "P3V0_STBY");
 701         if (test_regulator)
 702                 regulator_set_voltage(test_regulator, 3000000, 3000000);
 703         test_regulator = regulator_get(&pdev->dev, "P1V2_VGEN1");
 704         if (test_regulator) {
 705                 regulator_set_voltage(test_regulator, 1200000, 1200000);
 706                 regulator_enable(test_regulator);
 707         }
 708         test_regulator = regulator_get(&pdev->dev, "P1V5_VGEN2");
 709         if (test_regulator) {
 710                 regulator_set_voltage(test_regulator, 1500000, 1500000);
 711                 regulator_enable(test_regulator);
 712         }
 713         test_regulator = regulator_get(&pdev->dev, "P1V8_VGEN3");
 714         if (test_regulator) {
 715                 regulator_set_voltage(test_regulator, 1800000, 1800000);
 716                 regulator_enable(test_regulator);
 717         }
 718         test_regulator = regulator_get(&pdev->dev, "P1V8_VGEN4");
 719         if (test_regulator) {
 720                 regulator_set_voltage(test_regulator, 1800000, 1800000);
 721                 regulator_enable(test_regulator);
 722         }
 723         test_regulator = regulator_get(&pdev->dev, "P2V5_VGEN5");
 724         if (test_regulator) {
 725                 regulator_set_voltage(test_regulator, 2500000, 2500000);
 726                 regulator_enable(test_regulator);
 727         }
 728         test_regulator = regulator_get(&pdev->dev, "P2V8_VGEN6");
 729         if (test_regulator) {
 730                 regulator_set_voltage(test_regulator, 2800000, 2800000);
 731                 regulator_enable(test_regulator);
 732         }
 733 #endif
 734
 735         platform_set_drvdata(pdev, priv);
 736         return 0;
 737 err:
 738         while (--i >= 0)
 739                 regulator_unregister(priv->regulators[i]);
 740 err_free:
 741         pfuze_unlock(pfuze100);
 742         kfree(priv);
 743         return ret;
 744 }
 745
 746 static int __devexit pfuze100_regulator_remove(struct platform_device *pdev)
 747 {
 748         struct pfuze_regulator_priv *priv = platform_get_drvdata(pdev);
 749         struct pfuze_regulator_platform_data *pdata =
 750             dev_get_platdata(&pdev->dev);
 751         int i;
 752
 753         platform_set_drvdata(pdev, NULL);
 754         for (i = 0; i < pdata->num_regulators; i++)
 755                 regulator_unregister(priv->regulators[i]);
 756
 757         kfree(priv);
 758         return 0;
 759 }
 760
 761 static struct platform_driver pfuze100_regulator_driver = {
 762         .driver = {
 763                    .name = "pfuze100-regulator",
 764                    .owner = THIS_MODULE,
 765                    },
 766         .remove = __devexit_p(pfuze100_regulator_remove),
 767         .probe = pfuze100_regulator_probe,
 768 };
 769
 770 static int __init pfuze100_regulator_init(void)
 771 {
 772         return platform_driver_register(&pfuze100_regulator_driver);
 773 }
 774
 775 subsys_initcall(pfuze100_regulator_init);
 776
 777 static void __exit pfuze100_regulator_exit(void)
 778 {
 779         platform_driver_unregister(&pfuze100_regulator_driver);
 780 }
 781
 782 module_exit(pfuze100_regulator_exit);
 783
 784 MODULE_LICENSE("GPL v2");
 785 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
 786 MODULE_DESCRIPTION("Regulator Driver for Freescale PFUZE100 PMIC");
 787 MODULE_ALIAS("pfuze100-regulator");