drivers/rtc/rtc-jz4740.c

   1 /*
   2  *  Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
   3  *  Copyright (C) 2010, Paul Cercueil <paul@crapouillou.net>
   4  *       JZ4740 SoC RTC driver
   5  *
   6  *  This program is free software; you can redistribute it and/or modify it
   7  *  under  the terms of  the GNU General Public License as published by the
   8  *  Free Software Foundation;  either version 2 of the License, or (at your
   9  *  option) any later version.
  10  *
  11  *  You should have received a copy of the GNU General Public License along
  12  *  with this program; if not, write to the Free Software Foundation, Inc.,
  13  *  675 Mass Ave, Cambridge, MA 02139, USA.
  14  *
  15  */
  16
  17 #include <linux/clk.h>
  18 #include <linux/io.h>
  19 #include <linux/kernel.h>
  20 #include <linux/of_device.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/reboot.h>
  23 #include <linux/rtc.h>
  24 #include <linux/slab.h>
  25 #include <linux/spinlock.h>
  26
  27 #define JZ_REG_RTC_CTRL         0x00
  28 #define JZ_REG_RTC_SEC          0x04
  29 #define JZ_REG_RTC_SEC_ALARM    0x08
  30 #define JZ_REG_RTC_REGULATOR    0x0C
  31 #define JZ_REG_RTC_HIBERNATE    0x20
  32 #define JZ_REG_RTC_WAKEUP_FILTER        0x24
  33 #define JZ_REG_RTC_RESET_COUNTER        0x28
  34 #define JZ_REG_RTC_SCRATCHPAD   0x34
  35
  36 /* The following are present on the jz4780 */
  37 #define JZ_REG_RTC_WENR 0x3C
  38 #define JZ_RTC_WENR_WEN BIT(31)
  39
  40 #define JZ_RTC_CTRL_WRDY        BIT(7)
  41 #define JZ_RTC_CTRL_1HZ         BIT(6)
  42 #define JZ_RTC_CTRL_1HZ_IRQ     BIT(5)
  43 #define JZ_RTC_CTRL_AF          BIT(4)
  44 #define JZ_RTC_CTRL_AF_IRQ      BIT(3)
  45 #define JZ_RTC_CTRL_AE          BIT(2)
  46 #define JZ_RTC_CTRL_ENABLE      BIT(0)
  47
  48 /* Magic value to enable writes on jz4780 */
  49 #define JZ_RTC_WENR_MAGIC       0xA55A
  50
  51 #define JZ_RTC_WAKEUP_FILTER_MASK       0x0000FFE0
  52 #define JZ_RTC_RESET_COUNTER_MASK       0x00000FE0
  53
  54 enum jz4740_rtc_type {
  55         ID_JZ4740,
  56         ID_JZ4780,
  57 };
  58
  59 struct jz4740_rtc {
  60         void __iomem *base;
  61         enum jz4740_rtc_type type;
  62
  63         struct rtc_device *rtc;
  64         struct clk *clk;
  65
  66         int irq;
  67
  68         spinlock_t lock;
  69
  70         unsigned int min_wakeup_pin_assert_time;
  71         unsigned int reset_pin_assert_time;
  72 };
  73
  74 static struct device *dev_for_power_off;
  75
  76 static inline uint32_t jz4740_rtc_reg_read(struct jz4740_rtc *rtc, size_t reg)
  77 {
  78         return readl(rtc->base + reg);
  79 }
  80
  81 static int jz4740_rtc_wait_write_ready(struct jz4740_rtc *rtc)
  82 {
  83         uint32_t ctrl;
  84         int timeout = 1000;
  85
  86         do {
  87                 ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
  88         } while (!(ctrl & JZ_RTC_CTRL_WRDY) && --timeout);
  89
  90         return timeout ? 0 : -EIO;
  91 }
  92
  93 static inline int jz4780_rtc_enable_write(struct jz4740_rtc *rtc)
  94 {
  95         uint32_t ctrl;
  96         int ret, timeout = 1000;
  97
  98         ret = jz4740_rtc_wait_write_ready(rtc);
  99         if (ret != 0)
 100                 return ret;
 101
 102         writel(JZ_RTC_WENR_MAGIC, rtc->base + JZ_REG_RTC_WENR);
 103
 104         do {
 105                 ctrl = readl(rtc->base + JZ_REG_RTC_WENR);
 106         } while (!(ctrl & JZ_RTC_WENR_WEN) && --timeout);
 107
 108         return timeout ? 0 : -EIO;
 109 }
 110
 111 static inline int jz4740_rtc_reg_write(struct jz4740_rtc *rtc, size_t reg,
 112         uint32_t val)
 113 {
 114         int ret = 0;
 115
 116         if (rtc->type >= ID_JZ4780)
 117                 ret = jz4780_rtc_enable_write(rtc);
 118         if (ret == 0)
 119                 ret = jz4740_rtc_wait_write_ready(rtc);
 120         if (ret == 0)
 121                 writel(val, rtc->base + reg);
 122
 123         return ret;
 124 }
 125
 126 static int jz4740_rtc_ctrl_set_bits(struct jz4740_rtc *rtc, uint32_t mask,
 127         bool set)
 128 {
 129         int ret;
 130         unsigned long flags;
 131         uint32_t ctrl;
 132
 133         spin_lock_irqsave(&rtc->lock, flags);
 134
 135         ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
 136
 137         /* Don't clear interrupt flags by accident */
 138         ctrl |= JZ_RTC_CTRL_1HZ | JZ_RTC_CTRL_AF;
 139
 140         if (set)
 141                 ctrl |= mask;
 142         else
 143                 ctrl &= ~mask;
 144
 145         ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_CTRL, ctrl);
 146
 147         spin_unlock_irqrestore(&rtc->lock, flags);
 148
 149         return ret;
 150 }
 151
 152 static int jz4740_rtc_read_time(struct device *dev, struct rtc_time *time)
 153 {
 154         struct jz4740_rtc *rtc = dev_get_drvdata(dev);
 155         uint32_t secs, secs2;
 156         int timeout = 5;
 157
 158         /* If the seconds register is read while it is updated, it can contain a
 159          * bogus value. This can be avoided by making sure that two consecutive
 160          * reads have the same value.
 161          */
 162         secs = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
 163         secs2 = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
 164
 165         while (secs != secs2 && --timeout) {
 166                 secs = secs2;
 167                 secs2 = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
 168         }
 169
 170         if (timeout == 0)
 171                 return -EIO;
 172
 173         rtc_time_to_tm(secs, time);
 174
 175         return rtc_valid_tm(time);
 176 }
 177
 178 static int jz4740_rtc_set_mmss(struct device *dev, unsigned long secs)
 179 {
 180         struct jz4740_rtc *rtc = dev_get_drvdata(dev);
 181
 182         return jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC, secs);
 183 }
 184
 185 static int jz4740_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
 186 {
 187         struct jz4740_rtc *rtc = dev_get_drvdata(dev);
 188         uint32_t secs;
 189         uint32_t ctrl;
 190
 191         secs = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC_ALARM);
 192
 193         ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
 194
 195         alrm->enabled = !!(ctrl & JZ_RTC_CTRL_AE);
 196         alrm->pending = !!(ctrl & JZ_RTC_CTRL_AF);
 197
 198         rtc_time_to_tm(secs, &alrm->time);
 199
 200         return rtc_valid_tm(&alrm->time);
 201 }
 202
 203 static int jz4740_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
 204 {
 205         int ret;
 206         struct jz4740_rtc *rtc = dev_get_drvdata(dev);
 207         unsigned long secs;
 208
 209         rtc_tm_to_time(&alrm->time, &secs);
 210
 211         ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC_ALARM, secs);
 212         if (!ret)
 213                 ret = jz4740_rtc_ctrl_set_bits(rtc,
 214                         JZ_RTC_CTRL_AE | JZ_RTC_CTRL_AF_IRQ, alrm->enabled);
 215
 216         return ret;
 217 }
 218
 219 static int jz4740_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
 220 {
 221         struct jz4740_rtc *rtc = dev_get_drvdata(dev);
 222         return jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_AF_IRQ, enable);
 223 }
 224
 225 static const struct rtc_class_ops jz4740_rtc_ops = {
 226         .read_time      = jz4740_rtc_read_time,
 227         .set_mmss       = jz4740_rtc_set_mmss,
 228         .read_alarm     = jz4740_rtc_read_alarm,
 229         .set_alarm      = jz4740_rtc_set_alarm,
 230         .alarm_irq_enable = jz4740_rtc_alarm_irq_enable,
 231 };
 232
 233 static irqreturn_t jz4740_rtc_irq(int irq, void *data)
 234 {
 235         struct jz4740_rtc *rtc = data;
 236         uint32_t ctrl;
 237         unsigned long events = 0;
 238
 239         ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
 240
 241         if (ctrl & JZ_RTC_CTRL_1HZ)
 242                 events |= (RTC_UF | RTC_IRQF);
 243
 244         if (ctrl & JZ_RTC_CTRL_AF)
 245                 events |= (RTC_AF | RTC_IRQF);
 246
 247         rtc_update_irq(rtc->rtc, 1, events);
 248
 249         jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_1HZ | JZ_RTC_CTRL_AF, false);
 250
 251         return IRQ_HANDLED;
 252 }
 253
 254 static void jz4740_rtc_poweroff(struct device *dev)
 255 {
 256         struct jz4740_rtc *rtc = dev_get_drvdata(dev);
 257         jz4740_rtc_reg_write(rtc, JZ_REG_RTC_HIBERNATE, 1);
 258 }
 259
 260 static void jz4740_rtc_power_off(void)
 261 {
 262         struct jz4740_rtc *rtc = dev_get_drvdata(dev_for_power_off);
 263         unsigned long rtc_rate;
 264         unsigned long wakeup_filter_ticks;
 265         unsigned long reset_counter_ticks;
 266
 267         clk_prepare_enable(rtc->clk);
 268
 269         rtc_rate = clk_get_rate(rtc->clk);
 270
 271         /*
 272          * Set minimum wakeup pin assertion time: 100 ms.
 273          * Range is 0 to 2 sec if RTC is clocked at 32 kHz.
 274          */
 275         wakeup_filter_ticks =
 276                 (rtc->min_wakeup_pin_assert_time * rtc_rate) / 1000;
 277         if (wakeup_filter_ticks < JZ_RTC_WAKEUP_FILTER_MASK)
 278                 wakeup_filter_ticks &= JZ_RTC_WAKEUP_FILTER_MASK;
 279         else
 280                 wakeup_filter_ticks = JZ_RTC_WAKEUP_FILTER_MASK;
 281         jz4740_rtc_reg_write(rtc,
 282                              JZ_REG_RTC_WAKEUP_FILTER, wakeup_filter_ticks);
 283
 284         /*
 285          * Set reset pin low-level assertion time after wakeup: 60 ms.
 286          * Range is 0 to 125 ms if RTC is clocked at 32 kHz.
 287          */
 288         reset_counter_ticks = (rtc->reset_pin_assert_time * rtc_rate) / 1000;
 289         if (reset_counter_ticks < JZ_RTC_RESET_COUNTER_MASK)
 290                 reset_counter_ticks &= JZ_RTC_RESET_COUNTER_MASK;
 291         else
 292                 reset_counter_ticks = JZ_RTC_RESET_COUNTER_MASK;
 293         jz4740_rtc_reg_write(rtc,
 294                              JZ_REG_RTC_RESET_COUNTER, reset_counter_ticks);
 295
 296         jz4740_rtc_poweroff(dev_for_power_off);
 297         machine_halt();
 298 }
 299
 300 static const struct of_device_id jz4740_rtc_of_match[] = {
 301         { .compatible = "ingenic,jz4740-rtc", .data = (void *)ID_JZ4740 },
 302         { .compatible = "ingenic,jz4780-rtc", .data = (void *)ID_JZ4780 },
 303         {},
 304 };
 305
 306 static int jz4740_rtc_probe(struct platform_device *pdev)
 307 {
 308         int ret;
 309         struct jz4740_rtc *rtc;
 310         uint32_t scratchpad;
 311         struct resource *mem;
 312         const struct platform_device_id *id = platform_get_device_id(pdev);
 313         const struct of_device_id *of_id = of_match_device(
 314                         jz4740_rtc_of_match, &pdev->dev);
 315         struct device_node *np = pdev->dev.of_node;
 316
 317         rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
 318         if (!rtc)
 319                 return -ENOMEM;
 320
 321         if (of_id)
 322                 rtc->type = (enum jz4740_rtc_type)of_id->data;
 323         else
 324                 rtc->type = id->driver_data;
 325
 326         rtc->irq = platform_get_irq(pdev, 0);
 327         if (rtc->irq < 0) {
 328                 dev_err(&pdev->dev, "Failed to get platform irq\n");
 329                 return -ENOENT;
 330         }
 331
 332         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 333         rtc->base = devm_ioremap_resource(&pdev->dev, mem);
 334         if (IS_ERR(rtc->base))
 335                 return PTR_ERR(rtc->base);
 336
 337         rtc->clk = devm_clk_get(&pdev->dev, "rtc");
 338         if (IS_ERR(rtc->clk)) {
 339                 dev_err(&pdev->dev, "Failed to get RTC clock\n");
 340                 return PTR_ERR(rtc->clk);
 341         }
 342
 343         spin_lock_init(&rtc->lock);
 344
 345         platform_set_drvdata(pdev, rtc);
 346
 347         device_init_wakeup(&pdev->dev, 1);
 348
 349         rtc->rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
 350                                         &jz4740_rtc_ops, THIS_MODULE);
 351         if (IS_ERR(rtc->rtc)) {
 352                 ret = PTR_ERR(rtc->rtc);
 353                 dev_err(&pdev->dev, "Failed to register rtc device: %d\n", ret);
 354                 return ret;
 355         }
 356
 357         ret = devm_request_irq(&pdev->dev, rtc->irq, jz4740_rtc_irq, 0,
 358                                 pdev->name, rtc);
 359         if (ret) {
 360                 dev_err(&pdev->dev, "Failed to request rtc irq: %d\n", ret);
 361                 return ret;
 362         }
 363
 364         scratchpad = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SCRATCHPAD);
 365         if (scratchpad != 0x12345678) {
 366                 ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SCRATCHPAD, 0x12345678);
 367                 ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC, 0);
 368                 if (ret) {
 369                         dev_err(&pdev->dev, "Could not write write to RTC registers\n");
 370                         return ret;
 371                 }
 372         }
 373
 374         if (np && of_device_is_system_power_controller(np)) {
 375                 if (!pm_power_off) {
 376                         /* Default: 60ms */
 377                         rtc->reset_pin_assert_time = 60;
 378                         of_property_read_u32(np, "reset-pin-assert-time-ms",
 379                                              &rtc->reset_pin_assert_time);
 380
 381                         /* Default: 100ms */
 382                         rtc->min_wakeup_pin_assert_time = 100;
 383                         of_property_read_u32(np,
 384                                              "min-wakeup-pin-assert-time-ms",
 385                                              &rtc->min_wakeup_pin_assert_time);
 386
 387                         dev_for_power_off = &pdev->dev;
 388                         pm_power_off = jz4740_rtc_power_off;
 389                 } else {
 390                         dev_warn(&pdev->dev,
 391                                  "Poweroff handler already present!\n");
 392                 }
 393         }
 394
 395         return 0;
 396 }
 397
 398 #ifdef CONFIG_PM
 399 static int jz4740_rtc_suspend(struct device *dev)
 400 {
 401         struct jz4740_rtc *rtc = dev_get_drvdata(dev);
 402
 403         if (device_may_wakeup(dev))
 404                 enable_irq_wake(rtc->irq);
 405         return 0;
 406 }
 407
 408 static int jz4740_rtc_resume(struct device *dev)
 409 {
 410         struct jz4740_rtc *rtc = dev_get_drvdata(dev);
 411
 412         if (device_may_wakeup(dev))
 413                 disable_irq_wake(rtc->irq);
 414         return 0;
 415 }
 416
 417 static const struct dev_pm_ops jz4740_pm_ops = {
 418         .suspend = jz4740_rtc_suspend,
 419         .resume  = jz4740_rtc_resume,
 420 };
 421 #define JZ4740_RTC_PM_OPS (&jz4740_pm_ops)
 422
 423 #else
 424 #define JZ4740_RTC_PM_OPS NULL
 425 #endif  /* CONFIG_PM */
 426
 427 static const struct platform_device_id jz4740_rtc_ids[] = {
 428         { "jz4740-rtc", ID_JZ4740 },
 429         { "jz4780-rtc", ID_JZ4780 },
 430         {}
 431 };
 432
 433 static struct platform_driver jz4740_rtc_driver = {
 434         .probe   = jz4740_rtc_probe,
 435         .driver  = {
 436                 .name  = "jz4740-rtc",
 437                 .pm    = JZ4740_RTC_PM_OPS,
 438                 .of_match_table = of_match_ptr(jz4740_rtc_of_match),
 439         },
 440         .id_table = jz4740_rtc_ids,
 441 };
 442
 443 builtin_platform_driver(jz4740_rtc_driver);