2 * TI OMAP Real Time Clock interface for Linux
4 * Copyright (C) 2003 MontaVista Software, Inc.
5 * Author: George G. Davis <gdavis@mvista.com> or <source@mvista.com>
7 * Copyright (C) 2006 David Brownell (new RTC framework)
8 * Copyright (C) 2014 Johan Hovold <johan@kernel.org>
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
16 #include <dt-bindings/gpio/gpio.h>
17 #include <linux/bcd.h>
18 #include <linux/clk.h>
19 #include <linux/delay.h>
20 #include <linux/init.h>
22 #include <linux/ioport.h>
23 #include <linux/kernel.h>
24 #include <linux/module.h>
26 #include <linux/of_device.h>
27 #include <linux/pinctrl/pinctrl.h>
28 #include <linux/pinctrl/pinconf.h>
29 #include <linux/pinctrl/pinconf-generic.h>
30 #include <linux/platform_device.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/rtc.h>
35 * The OMAP RTC is a year/month/day/hours/minutes/seconds BCD clock
36 * with century-range alarm matching, driven by the 32kHz clock.
38 * The main user-visible ways it differs from PC RTCs are by omitting
39 * "don't care" alarm fields and sub-second periodic IRQs, and having
40 * an autoadjust mechanism to calibrate to the true oscillator rate.
42 * Board-specific wiring options include using split power mode with
43 * RTC_OFF_NOFF used as the reset signal (so the RTC won't be reset),
44 * and wiring RTC_WAKE_INT (so the RTC alarm can wake the system from
45 * low power modes) for OMAP1 boards (OMAP-L138 has this built into
46 * the SoC). See the BOARD-SPECIFIC CUSTOMIZATION comment.
50 #define OMAP_RTC_SECONDS_REG 0x00
51 #define OMAP_RTC_MINUTES_REG 0x04
52 #define OMAP_RTC_HOURS_REG 0x08
53 #define OMAP_RTC_DAYS_REG 0x0C
54 #define OMAP_RTC_MONTHS_REG 0x10
55 #define OMAP_RTC_YEARS_REG 0x14
56 #define OMAP_RTC_WEEKS_REG 0x18
58 #define OMAP_RTC_ALARM_SECONDS_REG 0x20
59 #define OMAP_RTC_ALARM_MINUTES_REG 0x24
60 #define OMAP_RTC_ALARM_HOURS_REG 0x28
61 #define OMAP_RTC_ALARM_DAYS_REG 0x2c
62 #define OMAP_RTC_ALARM_MONTHS_REG 0x30
63 #define OMAP_RTC_ALARM_YEARS_REG 0x34
65 #define OMAP_RTC_CTRL_REG 0x40
66 #define OMAP_RTC_STATUS_REG 0x44
67 #define OMAP_RTC_INTERRUPTS_REG 0x48
69 #define OMAP_RTC_COMP_LSB_REG 0x4c
70 #define OMAP_RTC_COMP_MSB_REG 0x50
71 #define OMAP_RTC_OSC_REG 0x54
73 #define OMAP_RTC_KICK0_REG 0x6c
74 #define OMAP_RTC_KICK1_REG 0x70
76 #define OMAP_RTC_IRQWAKEEN 0x7c
78 #define OMAP_RTC_ALARM2_SECONDS_REG 0x80
79 #define OMAP_RTC_ALARM2_MINUTES_REG 0x84
80 #define OMAP_RTC_ALARM2_HOURS_REG 0x88
81 #define OMAP_RTC_ALARM2_DAYS_REG 0x8c
82 #define OMAP_RTC_ALARM2_MONTHS_REG 0x90
83 #define OMAP_RTC_ALARM2_YEARS_REG 0x94
85 #define OMAP_RTC_PMIC_REG 0x98
87 /* OMAP_RTC_CTRL_REG bit fields: */
88 #define OMAP_RTC_CTRL_SPLIT BIT(7)
89 #define OMAP_RTC_CTRL_DISABLE BIT(6)
90 #define OMAP_RTC_CTRL_SET_32_COUNTER BIT(5)
91 #define OMAP_RTC_CTRL_TEST BIT(4)
92 #define OMAP_RTC_CTRL_MODE_12_24 BIT(3)
93 #define OMAP_RTC_CTRL_AUTO_COMP BIT(2)
94 #define OMAP_RTC_CTRL_ROUND_30S BIT(1)
95 #define OMAP_RTC_CTRL_STOP BIT(0)
97 /* OMAP_RTC_STATUS_REG bit fields: */
98 #define OMAP_RTC_STATUS_POWER_UP BIT(7)
99 #define OMAP_RTC_STATUS_ALARM2 BIT(7)
100 #define OMAP_RTC_STATUS_ALARM BIT(6)
101 #define OMAP_RTC_STATUS_1D_EVENT BIT(5)
102 #define OMAP_RTC_STATUS_1H_EVENT BIT(4)
103 #define OMAP_RTC_STATUS_1M_EVENT BIT(3)
104 #define OMAP_RTC_STATUS_1S_EVENT BIT(2)
105 #define OMAP_RTC_STATUS_RUN BIT(1)
106 #define OMAP_RTC_STATUS_BUSY BIT(0)
108 /* OMAP_RTC_INTERRUPTS_REG bit fields: */
109 #define OMAP_RTC_INTERRUPTS_IT_ALARM2 BIT(4)
110 #define OMAP_RTC_INTERRUPTS_IT_ALARM BIT(3)
111 #define OMAP_RTC_INTERRUPTS_IT_TIMER BIT(2)
113 /* OMAP_RTC_OSC_REG bit fields: */
114 #define OMAP_RTC_OSC_32KCLK_EN BIT(6)
115 #define OMAP_RTC_OSC_SEL_32KCLK_SRC BIT(3)
117 /* OMAP_RTC_IRQWAKEEN bit fields: */
118 #define OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN BIT(1)
120 /* OMAP_RTC_PMIC bit fields: */
121 #define OMAP_RTC_PMIC_POWER_EN_EN BIT(16)
122 #define OMAP_RTC_PMIC_EXT_WKUP_EN(x) BIT(x)
123 #define OMAP_RTC_PMIC_EXT_WKUP_POL(x) BIT(4 + x)
125 /* OMAP_RTC_KICKER values */
126 #define KICK0_VALUE 0x83e70b13
127 #define KICK1_VALUE 0x95a4f1e0
131 struct omap_rtc_device_type {
135 bool has_power_up_reset;
136 void (*lock)(struct omap_rtc *rtc);
137 void (*unlock)(struct omap_rtc *rtc);
141 struct rtc_device *rtc;
147 bool is_pmic_controller;
149 const struct omap_rtc_device_type *type;
150 struct pinctrl_dev *pctldev;
153 static inline u8 rtc_read(struct omap_rtc *rtc, unsigned int reg)
155 return readb(rtc->base + reg);
158 static inline u32 rtc_readl(struct omap_rtc *rtc, unsigned int reg)
160 return readl(rtc->base + reg);
163 static inline void rtc_write(struct omap_rtc *rtc, unsigned int reg, u8 val)
165 writeb(val, rtc->base + reg);
168 static inline void rtc_writel(struct omap_rtc *rtc, unsigned int reg, u32 val)
170 writel(val, rtc->base + reg);
173 static void am3352_rtc_unlock(struct omap_rtc *rtc)
175 rtc_writel(rtc, OMAP_RTC_KICK0_REG, KICK0_VALUE);
176 rtc_writel(rtc, OMAP_RTC_KICK1_REG, KICK1_VALUE);
179 static void am3352_rtc_lock(struct omap_rtc *rtc)
181 rtc_writel(rtc, OMAP_RTC_KICK0_REG, 0);
182 rtc_writel(rtc, OMAP_RTC_KICK1_REG, 0);
185 static void default_rtc_unlock(struct omap_rtc *rtc)
189 static void default_rtc_lock(struct omap_rtc *rtc)
194 * We rely on the rtc framework to handle locking (rtc->ops_lock),
195 * so the only other requirement is that register accesses which
196 * require BUSY to be clear are made with IRQs locally disabled
198 static void rtc_wait_not_busy(struct omap_rtc *rtc)
203 /* BUSY may stay active for 1/32768 second (~30 usec) */
204 for (count = 0; count < 50; count++) {
205 status = rtc_read(rtc, OMAP_RTC_STATUS_REG);
206 if (!(status & OMAP_RTC_STATUS_BUSY))
210 /* now we have ~15 usec to read/write various registers */
213 static irqreturn_t rtc_irq(int irq, void *dev_id)
215 struct omap_rtc *rtc = dev_id;
216 unsigned long events = 0;
219 irq_data = rtc_read(rtc, OMAP_RTC_STATUS_REG);
222 if (irq_data & OMAP_RTC_STATUS_ALARM) {
223 rtc->type->unlock(rtc);
224 rtc_write(rtc, OMAP_RTC_STATUS_REG, OMAP_RTC_STATUS_ALARM);
225 rtc->type->lock(rtc);
226 events |= RTC_IRQF | RTC_AF;
229 /* 1/sec periodic/update irq? */
230 if (irq_data & OMAP_RTC_STATUS_1S_EVENT)
231 events |= RTC_IRQF | RTC_UF;
233 rtc_update_irq(rtc->rtc, 1, events);
238 static int omap_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
240 struct omap_rtc *rtc = dev_get_drvdata(dev);
241 u8 reg, irqwake_reg = 0;
244 rtc_wait_not_busy(rtc);
245 reg = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
246 if (rtc->type->has_irqwakeen)
247 irqwake_reg = rtc_read(rtc, OMAP_RTC_IRQWAKEEN);
250 reg |= OMAP_RTC_INTERRUPTS_IT_ALARM;
251 irqwake_reg |= OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN;
253 reg &= ~OMAP_RTC_INTERRUPTS_IT_ALARM;
254 irqwake_reg &= ~OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN;
256 rtc_wait_not_busy(rtc);
257 rtc->type->unlock(rtc);
258 rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, reg);
259 if (rtc->type->has_irqwakeen)
260 rtc_write(rtc, OMAP_RTC_IRQWAKEEN, irqwake_reg);
261 rtc->type->lock(rtc);
267 /* this hardware doesn't support "don't care" alarm fields */
268 static int tm2bcd(struct rtc_time *tm)
270 if (rtc_valid_tm(tm) != 0)
273 tm->tm_sec = bin2bcd(tm->tm_sec);
274 tm->tm_min = bin2bcd(tm->tm_min);
275 tm->tm_hour = bin2bcd(tm->tm_hour);
276 tm->tm_mday = bin2bcd(tm->tm_mday);
278 tm->tm_mon = bin2bcd(tm->tm_mon + 1);
281 if (tm->tm_year < 100 || tm->tm_year > 199)
283 tm->tm_year = bin2bcd(tm->tm_year - 100);
288 static void bcd2tm(struct rtc_time *tm)
290 tm->tm_sec = bcd2bin(tm->tm_sec);
291 tm->tm_min = bcd2bin(tm->tm_min);
292 tm->tm_hour = bcd2bin(tm->tm_hour);
293 tm->tm_mday = bcd2bin(tm->tm_mday);
294 tm->tm_mon = bcd2bin(tm->tm_mon) - 1;
296 tm->tm_year = bcd2bin(tm->tm_year) + 100;
299 static void omap_rtc_read_time_raw(struct omap_rtc *rtc, struct rtc_time *tm)
301 tm->tm_sec = rtc_read(rtc, OMAP_RTC_SECONDS_REG);
302 tm->tm_min = rtc_read(rtc, OMAP_RTC_MINUTES_REG);
303 tm->tm_hour = rtc_read(rtc, OMAP_RTC_HOURS_REG);
304 tm->tm_mday = rtc_read(rtc, OMAP_RTC_DAYS_REG);
305 tm->tm_mon = rtc_read(rtc, OMAP_RTC_MONTHS_REG);
306 tm->tm_year = rtc_read(rtc, OMAP_RTC_YEARS_REG);
309 static int omap_rtc_read_time(struct device *dev, struct rtc_time *tm)
311 struct omap_rtc *rtc = dev_get_drvdata(dev);
313 /* we don't report wday/yday/isdst ... */
315 rtc_wait_not_busy(rtc);
316 omap_rtc_read_time_raw(rtc, tm);
324 static int omap_rtc_set_time(struct device *dev, struct rtc_time *tm)
326 struct omap_rtc *rtc = dev_get_drvdata(dev);
332 rtc_wait_not_busy(rtc);
334 rtc->type->unlock(rtc);
335 rtc_write(rtc, OMAP_RTC_YEARS_REG, tm->tm_year);
336 rtc_write(rtc, OMAP_RTC_MONTHS_REG, tm->tm_mon);
337 rtc_write(rtc, OMAP_RTC_DAYS_REG, tm->tm_mday);
338 rtc_write(rtc, OMAP_RTC_HOURS_REG, tm->tm_hour);
339 rtc_write(rtc, OMAP_RTC_MINUTES_REG, tm->tm_min);
340 rtc_write(rtc, OMAP_RTC_SECONDS_REG, tm->tm_sec);
341 rtc->type->lock(rtc);
348 static int omap_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
350 struct omap_rtc *rtc = dev_get_drvdata(dev);
354 rtc_wait_not_busy(rtc);
356 alm->time.tm_sec = rtc_read(rtc, OMAP_RTC_ALARM_SECONDS_REG);
357 alm->time.tm_min = rtc_read(rtc, OMAP_RTC_ALARM_MINUTES_REG);
358 alm->time.tm_hour = rtc_read(rtc, OMAP_RTC_ALARM_HOURS_REG);
359 alm->time.tm_mday = rtc_read(rtc, OMAP_RTC_ALARM_DAYS_REG);
360 alm->time.tm_mon = rtc_read(rtc, OMAP_RTC_ALARM_MONTHS_REG);
361 alm->time.tm_year = rtc_read(rtc, OMAP_RTC_ALARM_YEARS_REG);
367 interrupts = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
368 alm->enabled = !!(interrupts & OMAP_RTC_INTERRUPTS_IT_ALARM);
373 static int omap_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
375 struct omap_rtc *rtc = dev_get_drvdata(dev);
376 u8 reg, irqwake_reg = 0;
378 if (tm2bcd(&alm->time) < 0)
382 rtc_wait_not_busy(rtc);
384 rtc->type->unlock(rtc);
385 rtc_write(rtc, OMAP_RTC_ALARM_YEARS_REG, alm->time.tm_year);
386 rtc_write(rtc, OMAP_RTC_ALARM_MONTHS_REG, alm->time.tm_mon);
387 rtc_write(rtc, OMAP_RTC_ALARM_DAYS_REG, alm->time.tm_mday);
388 rtc_write(rtc, OMAP_RTC_ALARM_HOURS_REG, alm->time.tm_hour);
389 rtc_write(rtc, OMAP_RTC_ALARM_MINUTES_REG, alm->time.tm_min);
390 rtc_write(rtc, OMAP_RTC_ALARM_SECONDS_REG, alm->time.tm_sec);
392 reg = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
393 if (rtc->type->has_irqwakeen)
394 irqwake_reg = rtc_read(rtc, OMAP_RTC_IRQWAKEEN);
397 reg |= OMAP_RTC_INTERRUPTS_IT_ALARM;
398 irqwake_reg |= OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN;
400 reg &= ~OMAP_RTC_INTERRUPTS_IT_ALARM;
401 irqwake_reg &= ~OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN;
403 rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, reg);
404 if (rtc->type->has_irqwakeen)
405 rtc_write(rtc, OMAP_RTC_IRQWAKEEN, irqwake_reg);
406 rtc->type->lock(rtc);
413 static struct omap_rtc *omap_rtc_power_off_rtc;
416 * omap_rtc_poweroff: RTC-controlled power off
418 * The RTC can be used to control an external PMIC via the pmic_power_en pin,
419 * which can be configured to transition to OFF on ALARM2 events.
422 * The two-second alarm offset is the shortest offset possible as the alarm
423 * registers must be set before the next timer update and the offset
424 * calculation is too heavy for everything to be done within a single access
427 * Called with local interrupts disabled.
429 static void omap_rtc_power_off(void)
431 struct omap_rtc *rtc = omap_rtc_power_off_rtc;
436 rtc->type->unlock(rtc);
437 /* enable pmic_power_en control */
438 val = rtc_readl(rtc, OMAP_RTC_PMIC_REG);
439 rtc_writel(rtc, OMAP_RTC_PMIC_REG, val | OMAP_RTC_PMIC_POWER_EN_EN);
441 /* set alarm two seconds from now */
442 omap_rtc_read_time_raw(rtc, &tm);
444 rtc_tm_to_time(&tm, &now);
445 rtc_time_to_tm(now + 2, &tm);
447 if (tm2bcd(&tm) < 0) {
448 dev_err(&rtc->rtc->dev, "power off failed\n");
452 rtc_wait_not_busy(rtc);
454 rtc_write(rtc, OMAP_RTC_ALARM2_SECONDS_REG, tm.tm_sec);
455 rtc_write(rtc, OMAP_RTC_ALARM2_MINUTES_REG, tm.tm_min);
456 rtc_write(rtc, OMAP_RTC_ALARM2_HOURS_REG, tm.tm_hour);
457 rtc_write(rtc, OMAP_RTC_ALARM2_DAYS_REG, tm.tm_mday);
458 rtc_write(rtc, OMAP_RTC_ALARM2_MONTHS_REG, tm.tm_mon);
459 rtc_write(rtc, OMAP_RTC_ALARM2_YEARS_REG, tm.tm_year);
462 * enable ALARM2 interrupt
464 * NOTE: this fails on AM3352 if rtc_write (writeb) is used
466 val = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
467 rtc_writel(rtc, OMAP_RTC_INTERRUPTS_REG,
468 val | OMAP_RTC_INTERRUPTS_IT_ALARM2);
469 rtc->type->lock(rtc);
472 * Wait for alarm to trigger (within two seconds) and external PMIC to
473 * power off the system. Add a 500 ms margin for external latencies
474 * (e.g. debounce circuits).
479 static const struct rtc_class_ops omap_rtc_ops = {
480 .read_time = omap_rtc_read_time,
481 .set_time = omap_rtc_set_time,
482 .read_alarm = omap_rtc_read_alarm,
483 .set_alarm = omap_rtc_set_alarm,
484 .alarm_irq_enable = omap_rtc_alarm_irq_enable,
487 static const struct omap_rtc_device_type omap_rtc_default_type = {
488 .has_power_up_reset = true,
489 .lock = default_rtc_lock,
490 .unlock = default_rtc_unlock,
493 static const struct omap_rtc_device_type omap_rtc_am3352_type = {
494 .has_32kclk_en = true,
495 .has_irqwakeen = true,
496 .has_pmic_mode = true,
497 .lock = am3352_rtc_lock,
498 .unlock = am3352_rtc_unlock,
501 static const struct omap_rtc_device_type omap_rtc_da830_type = {
502 .lock = am3352_rtc_lock,
503 .unlock = am3352_rtc_unlock,
506 static const struct platform_device_id omap_rtc_id_table[] = {
509 .driver_data = (kernel_ulong_t)&omap_rtc_default_type,
511 .name = "am3352-rtc",
512 .driver_data = (kernel_ulong_t)&omap_rtc_am3352_type,
515 .driver_data = (kernel_ulong_t)&omap_rtc_da830_type,
520 MODULE_DEVICE_TABLE(platform, omap_rtc_id_table);
522 static const struct of_device_id omap_rtc_of_match[] = {
524 .compatible = "ti,am3352-rtc",
525 .data = &omap_rtc_am3352_type,
527 .compatible = "ti,da830-rtc",
528 .data = &omap_rtc_da830_type,
533 MODULE_DEVICE_TABLE(of, omap_rtc_of_match);
535 static const struct pinctrl_pin_desc rtc_pins_desc[] = {
536 PINCTRL_PIN(0, "ext_wakeup0"),
537 PINCTRL_PIN(1, "ext_wakeup1"),
538 PINCTRL_PIN(2, "ext_wakeup2"),
539 PINCTRL_PIN(3, "ext_wakeup3"),
542 static int rtc_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
547 static const char *rtc_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
553 static const struct pinctrl_ops rtc_pinctrl_ops = {
554 .get_groups_count = rtc_pinctrl_get_groups_count,
555 .get_group_name = rtc_pinctrl_get_group_name,
556 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
557 .dt_free_map = pinconf_generic_dt_free_map,
560 enum rtc_pin_config_param {
561 PIN_CONFIG_ACTIVE_HIGH = PIN_CONFIG_END + 1,
564 static const struct pinconf_generic_params rtc_params[] = {
565 {"ti,active-high", PIN_CONFIG_ACTIVE_HIGH, 0},
568 #ifdef CONFIG_DEBUG_FS
569 static const struct pin_config_item rtc_conf_items[ARRAY_SIZE(rtc_params)] = {
570 PCONFDUMP(PIN_CONFIG_ACTIVE_HIGH, "input active high", NULL, false),
574 static int rtc_pinconf_get(struct pinctrl_dev *pctldev,
575 unsigned int pin, unsigned long *config)
577 struct omap_rtc *rtc = pinctrl_dev_get_drvdata(pctldev);
578 unsigned int param = pinconf_to_config_param(*config);
582 rtc->type->unlock(rtc);
583 val = rtc_readl(rtc, OMAP_RTC_PMIC_REG);
584 rtc->type->lock(rtc);
587 case PIN_CONFIG_INPUT_ENABLE:
588 if (!(val & OMAP_RTC_PMIC_EXT_WKUP_EN(pin)))
591 case PIN_CONFIG_ACTIVE_HIGH:
592 if (val & OMAP_RTC_PMIC_EXT_WKUP_POL(pin))
599 *config = pinconf_to_config_packed(param, arg);
604 static int rtc_pinconf_set(struct pinctrl_dev *pctldev,
605 unsigned int pin, unsigned long *configs,
606 unsigned int num_configs)
608 struct omap_rtc *rtc = pinctrl_dev_get_drvdata(pctldev);
614 rtc->type->unlock(rtc);
615 val = rtc_readl(rtc, OMAP_RTC_PMIC_REG);
616 rtc->type->lock(rtc);
618 /* active low by default */
619 val |= OMAP_RTC_PMIC_EXT_WKUP_POL(pin);
621 for (i = 0; i < num_configs; i++) {
622 param = pinconf_to_config_param(configs[i]);
623 param_val = pinconf_to_config_argument(configs[i]);
626 case PIN_CONFIG_INPUT_ENABLE:
628 val |= OMAP_RTC_PMIC_EXT_WKUP_EN(pin);
630 val &= ~OMAP_RTC_PMIC_EXT_WKUP_EN(pin);
632 case PIN_CONFIG_ACTIVE_HIGH:
633 val &= ~OMAP_RTC_PMIC_EXT_WKUP_POL(pin);
636 dev_err(&rtc->rtc->dev, "Property %u not supported\n",
642 rtc->type->unlock(rtc);
643 rtc_writel(rtc, OMAP_RTC_PMIC_REG, val);
644 rtc->type->lock(rtc);
649 static const struct pinconf_ops rtc_pinconf_ops = {
651 .pin_config_get = rtc_pinconf_get,
652 .pin_config_set = rtc_pinconf_set,
655 static struct pinctrl_desc rtc_pinctrl_desc = {
656 .pins = rtc_pins_desc,
657 .npins = ARRAY_SIZE(rtc_pins_desc),
658 .pctlops = &rtc_pinctrl_ops,
659 .confops = &rtc_pinconf_ops,
660 .custom_params = rtc_params,
661 .num_custom_params = ARRAY_SIZE(rtc_params),
662 #ifdef CONFIG_DEBUG_FS
663 .custom_conf_items = rtc_conf_items,
665 .owner = THIS_MODULE,
668 static int omap_rtc_probe(struct platform_device *pdev)
670 struct omap_rtc *rtc;
671 struct resource *res;
672 u8 reg, mask, new_ctrl;
673 const struct platform_device_id *id_entry;
674 const struct of_device_id *of_id;
677 rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
681 of_id = of_match_device(omap_rtc_of_match, &pdev->dev);
683 rtc->type = of_id->data;
684 rtc->is_pmic_controller = rtc->type->has_pmic_mode &&
685 of_property_read_bool(pdev->dev.of_node,
686 "system-power-controller");
688 id_entry = platform_get_device_id(pdev);
689 rtc->type = (void *)id_entry->driver_data;
692 rtc->irq_timer = platform_get_irq(pdev, 0);
693 if (rtc->irq_timer <= 0)
696 rtc->irq_alarm = platform_get_irq(pdev, 1);
697 if (rtc->irq_alarm <= 0)
700 rtc->clk = devm_clk_get(&pdev->dev, "ext-clk");
701 if (!IS_ERR(rtc->clk))
702 rtc->has_ext_clk = true;
704 rtc->clk = devm_clk_get(&pdev->dev, "int-clk");
706 if (!IS_ERR(rtc->clk))
707 clk_prepare_enable(rtc->clk);
709 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
710 rtc->base = devm_ioremap_resource(&pdev->dev, res);
711 if (IS_ERR(rtc->base))
712 return PTR_ERR(rtc->base);
714 platform_set_drvdata(pdev, rtc);
716 /* Enable the clock/module so that we can access the registers */
717 pm_runtime_enable(&pdev->dev);
718 pm_runtime_get_sync(&pdev->dev);
720 rtc->type->unlock(rtc);
725 * NOTE: ALARM2 is not cleared on AM3352 if rtc_write (writeb) is used
727 rtc_writel(rtc, OMAP_RTC_INTERRUPTS_REG, 0);
729 /* enable RTC functional clock */
730 if (rtc->type->has_32kclk_en) {
731 reg = rtc_read(rtc, OMAP_RTC_OSC_REG);
732 rtc_writel(rtc, OMAP_RTC_OSC_REG,
733 reg | OMAP_RTC_OSC_32KCLK_EN);
736 /* clear old status */
737 reg = rtc_read(rtc, OMAP_RTC_STATUS_REG);
739 mask = OMAP_RTC_STATUS_ALARM;
741 if (rtc->type->has_pmic_mode)
742 mask |= OMAP_RTC_STATUS_ALARM2;
744 if (rtc->type->has_power_up_reset) {
745 mask |= OMAP_RTC_STATUS_POWER_UP;
746 if (reg & OMAP_RTC_STATUS_POWER_UP)
747 dev_info(&pdev->dev, "RTC power up reset detected\n");
751 rtc_write(rtc, OMAP_RTC_STATUS_REG, reg & mask);
753 /* On boards with split power, RTC_ON_NOFF won't reset the RTC */
754 reg = rtc_read(rtc, OMAP_RTC_CTRL_REG);
755 if (reg & OMAP_RTC_CTRL_STOP)
756 dev_info(&pdev->dev, "already running\n");
758 /* force to 24 hour mode */
759 new_ctrl = reg & (OMAP_RTC_CTRL_SPLIT | OMAP_RTC_CTRL_AUTO_COMP);
760 new_ctrl |= OMAP_RTC_CTRL_STOP;
763 * BOARD-SPECIFIC CUSTOMIZATION CAN GO HERE:
765 * - Device wake-up capability setting should come through chip
766 * init logic. OMAP1 boards should initialize the "wakeup capable"
767 * flag in the platform device if the board is wired right for
768 * being woken up by RTC alarm. For OMAP-L138, this capability
769 * is built into the SoC by the "Deep Sleep" capability.
771 * - Boards wired so RTC_ON_nOFF is used as the reset signal,
772 * rather than nPWRON_RESET, should forcibly enable split
773 * power mode. (Some chip errata report that RTC_CTRL_SPLIT
774 * is write-only, and always reads as zero...)
777 if (new_ctrl & OMAP_RTC_CTRL_SPLIT)
778 dev_info(&pdev->dev, "split power mode\n");
781 rtc_write(rtc, OMAP_RTC_CTRL_REG, new_ctrl);
784 * If we have the external clock then switch to it so we can keep
785 * ticking across suspend.
787 if (rtc->has_ext_clk) {
788 reg = rtc_read(rtc, OMAP_RTC_OSC_REG);
789 rtc_write(rtc, OMAP_RTC_OSC_REG,
790 reg | OMAP_RTC_OSC_SEL_32KCLK_SRC);
793 rtc->type->lock(rtc);
795 device_init_wakeup(&pdev->dev, true);
797 rtc->rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
798 &omap_rtc_ops, THIS_MODULE);
799 if (IS_ERR(rtc->rtc)) {
800 ret = PTR_ERR(rtc->rtc);
804 /* handle periodic and alarm irqs */
805 ret = devm_request_irq(&pdev->dev, rtc->irq_timer, rtc_irq, 0,
806 dev_name(&rtc->rtc->dev), rtc);
810 if (rtc->irq_timer != rtc->irq_alarm) {
811 ret = devm_request_irq(&pdev->dev, rtc->irq_alarm, rtc_irq, 0,
812 dev_name(&rtc->rtc->dev), rtc);
817 if (rtc->is_pmic_controller) {
819 omap_rtc_power_off_rtc = rtc;
820 pm_power_off = omap_rtc_power_off;
824 /* Support ext_wakeup pinconf */
825 rtc_pinctrl_desc.name = dev_name(&pdev->dev);
827 rtc->pctldev = pinctrl_register(&rtc_pinctrl_desc, &pdev->dev, rtc);
828 if (IS_ERR(rtc->pctldev)) {
829 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
830 return PTR_ERR(rtc->pctldev);
836 device_init_wakeup(&pdev->dev, false);
837 rtc->type->lock(rtc);
838 pm_runtime_put_sync(&pdev->dev);
839 pm_runtime_disable(&pdev->dev);
844 static int __exit omap_rtc_remove(struct platform_device *pdev)
846 struct omap_rtc *rtc = platform_get_drvdata(pdev);
849 if (pm_power_off == omap_rtc_power_off &&
850 omap_rtc_power_off_rtc == rtc) {
852 omap_rtc_power_off_rtc = NULL;
855 device_init_wakeup(&pdev->dev, 0);
857 if (!IS_ERR(rtc->clk))
858 clk_disable_unprepare(rtc->clk);
860 rtc->type->unlock(rtc);
861 /* leave rtc running, but disable irqs */
862 rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, 0);
864 if (rtc->has_ext_clk) {
865 reg = rtc_read(rtc, OMAP_RTC_OSC_REG);
866 reg &= ~OMAP_RTC_OSC_SEL_32KCLK_SRC;
867 rtc_write(rtc, OMAP_RTC_OSC_REG, reg);
870 rtc->type->lock(rtc);
872 /* Disable the clock/module */
873 pm_runtime_put_sync(&pdev->dev);
874 pm_runtime_disable(&pdev->dev);
876 /* Remove ext_wakeup pinconf */
877 pinctrl_unregister(rtc->pctldev);
882 #ifdef CONFIG_PM_SLEEP
883 static int omap_rtc_suspend(struct device *dev)
885 struct omap_rtc *rtc = dev_get_drvdata(dev);
887 rtc->interrupts_reg = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
889 rtc->type->unlock(rtc);
891 * FIXME: the RTC alarm is not currently acting as a wakeup event
892 * source on some platforms, and in fact this enable() call is just
893 * saving a flag that's never used...
895 if (device_may_wakeup(dev))
896 enable_irq_wake(rtc->irq_alarm);
898 rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, 0);
899 rtc->type->lock(rtc);
901 /* Disable the clock/module */
902 pm_runtime_put_sync(dev);
907 static int omap_rtc_resume(struct device *dev)
909 struct omap_rtc *rtc = dev_get_drvdata(dev);
911 /* Enable the clock/module so that we can access the registers */
912 pm_runtime_get_sync(dev);
914 rtc->type->unlock(rtc);
915 if (device_may_wakeup(dev))
916 disable_irq_wake(rtc->irq_alarm);
918 rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, rtc->interrupts_reg);
919 rtc->type->lock(rtc);
925 static SIMPLE_DEV_PM_OPS(omap_rtc_pm_ops, omap_rtc_suspend, omap_rtc_resume);
927 static void omap_rtc_shutdown(struct platform_device *pdev)
929 struct omap_rtc *rtc = platform_get_drvdata(pdev);
933 * Keep the ALARM interrupt enabled to allow the system to power up on
936 rtc->type->unlock(rtc);
937 mask = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
938 mask &= OMAP_RTC_INTERRUPTS_IT_ALARM;
939 rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, mask);
940 rtc->type->lock(rtc);
943 static struct platform_driver omap_rtc_driver = {
944 .probe = omap_rtc_probe,
945 .remove = __exit_p(omap_rtc_remove),
946 .shutdown = omap_rtc_shutdown,
949 .pm = &omap_rtc_pm_ops,
950 .of_match_table = omap_rtc_of_match,
952 .id_table = omap_rtc_id_table,
955 module_platform_driver(omap_rtc_driver);
957 MODULE_ALIAS("platform:omap_rtc");
958 MODULE_AUTHOR("George G. Davis (and others)");
959 MODULE_LICENSE("GPL");