2 * rtc-twl.c -- TWL Real Time Clock interface
4 * Copyright (C) 2007 MontaVista Software, Inc
5 * Author: Alexandre Rusev <source@mvista.com>
7 * Based on original TI driver twl4030-rtc.c
8 * Copyright (C) 2006 Texas Instruments, Inc.
11 * Copyright (C) 2003 MontaVista Software, Inc.
12 * Author: George G. Davis <gdavis@mvista.com> or <source@mvista.com>
13 * Copyright (C) 2006 David Brownell
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
21 #include <linux/kernel.h>
22 #include <linux/errno.h>
23 #include <linux/init.h>
24 #include <linux/module.h>
25 #include <linux/types.h>
26 #include <linux/rtc.h>
27 #include <linux/bcd.h>
28 #include <linux/platform_device.h>
29 #include <linux/interrupt.h>
31 #include <linux/i2c/twl.h>
35 * RTC block register offsets (use TWL_MODULE_RTC)
46 REG_ALARM_SECONDS_REG,
47 REG_ALARM_MINUTES_REG,
55 REG_RTC_INTERRUPTS_REG,
60 static const u8 twl4030_rtc_reg_map[] = {
61 [REG_SECONDS_REG] = 0x00,
62 [REG_MINUTES_REG] = 0x01,
63 [REG_HOURS_REG] = 0x02,
64 [REG_DAYS_REG] = 0x03,
65 [REG_MONTHS_REG] = 0x04,
66 [REG_YEARS_REG] = 0x05,
67 [REG_WEEKS_REG] = 0x06,
69 [REG_ALARM_SECONDS_REG] = 0x07,
70 [REG_ALARM_MINUTES_REG] = 0x08,
71 [REG_ALARM_HOURS_REG] = 0x09,
72 [REG_ALARM_DAYS_REG] = 0x0A,
73 [REG_ALARM_MONTHS_REG] = 0x0B,
74 [REG_ALARM_YEARS_REG] = 0x0C,
76 [REG_RTC_CTRL_REG] = 0x0D,
77 [REG_RTC_STATUS_REG] = 0x0E,
78 [REG_RTC_INTERRUPTS_REG] = 0x0F,
80 [REG_RTC_COMP_LSB_REG] = 0x10,
81 [REG_RTC_COMP_MSB_REG] = 0x11,
83 static const u8 twl6030_rtc_reg_map[] = {
84 [REG_SECONDS_REG] = 0x00,
85 [REG_MINUTES_REG] = 0x01,
86 [REG_HOURS_REG] = 0x02,
87 [REG_DAYS_REG] = 0x03,
88 [REG_MONTHS_REG] = 0x04,
89 [REG_YEARS_REG] = 0x05,
90 [REG_WEEKS_REG] = 0x06,
92 [REG_ALARM_SECONDS_REG] = 0x08,
93 [REG_ALARM_MINUTES_REG] = 0x09,
94 [REG_ALARM_HOURS_REG] = 0x0A,
95 [REG_ALARM_DAYS_REG] = 0x0B,
96 [REG_ALARM_MONTHS_REG] = 0x0C,
97 [REG_ALARM_YEARS_REG] = 0x0D,
99 [REG_RTC_CTRL_REG] = 0x10,
100 [REG_RTC_STATUS_REG] = 0x11,
101 [REG_RTC_INTERRUPTS_REG] = 0x12,
103 [REG_RTC_COMP_LSB_REG] = 0x13,
104 [REG_RTC_COMP_MSB_REG] = 0x14,
107 /* RTC_CTRL_REG bitfields */
108 #define BIT_RTC_CTRL_REG_STOP_RTC_M 0x01
109 #define BIT_RTC_CTRL_REG_ROUND_30S_M 0x02
110 #define BIT_RTC_CTRL_REG_AUTO_COMP_M 0x04
111 #define BIT_RTC_CTRL_REG_MODE_12_24_M 0x08
112 #define BIT_RTC_CTRL_REG_TEST_MODE_M 0x10
113 #define BIT_RTC_CTRL_REG_SET_32_COUNTER_M 0x20
114 #define BIT_RTC_CTRL_REG_GET_TIME_M 0x40
116 /* RTC_STATUS_REG bitfields */
117 #define BIT_RTC_STATUS_REG_RUN_M 0x02
118 #define BIT_RTC_STATUS_REG_1S_EVENT_M 0x04
119 #define BIT_RTC_STATUS_REG_1M_EVENT_M 0x08
120 #define BIT_RTC_STATUS_REG_1H_EVENT_M 0x10
121 #define BIT_RTC_STATUS_REG_1D_EVENT_M 0x20
122 #define BIT_RTC_STATUS_REG_ALARM_M 0x40
123 #define BIT_RTC_STATUS_REG_POWER_UP_M 0x80
125 /* RTC_INTERRUPTS_REG bitfields */
126 #define BIT_RTC_INTERRUPTS_REG_EVERY_M 0x03
127 #define BIT_RTC_INTERRUPTS_REG_IT_TIMER_M 0x04
128 #define BIT_RTC_INTERRUPTS_REG_IT_ALARM_M 0x08
131 /* REG_SECONDS_REG through REG_YEARS_REG is how many registers? */
132 #define ALL_TIME_REGS 6
134 /*----------------------------------------------------------------------*/
135 static u8 *rtc_reg_map;
138 * Supports 1 byte read from TWL RTC register.
140 static int twl_rtc_read_u8(u8 *data, u8 reg)
144 ret = twl_i2c_read_u8(TWL_MODULE_RTC, data, (rtc_reg_map[reg]));
146 pr_err("twl_rtc: Could not read TWL"
147 "register %X - error %d\n", reg, ret);
152 * Supports 1 byte write to TWL RTC registers.
154 static int twl_rtc_write_u8(u8 data, u8 reg)
158 ret = twl_i2c_write_u8(TWL_MODULE_RTC, data, (rtc_reg_map[reg]));
160 pr_err("twl_rtc: Could not write TWL"
161 "register %X - error %d\n", reg, ret);
166 * Cache the value for timer/alarm interrupts register; this is
167 * only changed by callers holding rtc ops lock (or resume).
169 static unsigned char rtc_irq_bits;
172 * Enable 1/second update and/or alarm interrupts.
174 static int set_rtc_irq_bit(unsigned char bit)
179 val = rtc_irq_bits | bit;
180 val &= ~BIT_RTC_INTERRUPTS_REG_EVERY_M;
181 ret = twl_rtc_write_u8(val, REG_RTC_INTERRUPTS_REG);
189 * Disable update and/or alarm interrupts.
191 static int mask_rtc_irq_bit(unsigned char bit)
196 val = rtc_irq_bits & ~bit;
197 ret = twl_rtc_write_u8(val, REG_RTC_INTERRUPTS_REG);
204 static int twl_rtc_alarm_irq_enable(struct device *dev, unsigned enabled)
209 ret = set_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_ALARM_M);
211 ret = mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_ALARM_M);
216 static int twl_rtc_update_irq_enable(struct device *dev, unsigned enabled)
221 ret = set_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_TIMER_M);
223 ret = mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_TIMER_M);
229 * Gets current TWL RTC time and date parameters.
231 * The RTC's time/alarm representation is not what gmtime(3) requires
234 * - Months are 1..12 vs Linux 0-11
235 * - Years are 0..99 vs Linux 1900..N (we assume 21st century)
237 static int twl_rtc_read_time(struct device *dev, struct rtc_time *tm)
239 unsigned char rtc_data[ALL_TIME_REGS + 1];
243 ret = twl_rtc_read_u8(&save_control, REG_RTC_CTRL_REG);
247 save_control |= BIT_RTC_CTRL_REG_GET_TIME_M;
249 ret = twl_rtc_write_u8(save_control, REG_RTC_CTRL_REG);
253 ret = twl_i2c_read(TWL_MODULE_RTC, rtc_data,
254 (rtc_reg_map[REG_SECONDS_REG]), ALL_TIME_REGS);
257 dev_err(dev, "rtc_read_time error %d\n", ret);
261 tm->tm_sec = bcd2bin(rtc_data[0]);
262 tm->tm_min = bcd2bin(rtc_data[1]);
263 tm->tm_hour = bcd2bin(rtc_data[2]);
264 tm->tm_mday = bcd2bin(rtc_data[3]);
265 tm->tm_mon = bcd2bin(rtc_data[4]) - 1;
266 tm->tm_year = bcd2bin(rtc_data[5]) + 100;
271 static int twl_rtc_set_time(struct device *dev, struct rtc_time *tm)
273 unsigned char save_control;
274 unsigned char rtc_data[ALL_TIME_REGS + 1];
277 rtc_data[1] = bin2bcd(tm->tm_sec);
278 rtc_data[2] = bin2bcd(tm->tm_min);
279 rtc_data[3] = bin2bcd(tm->tm_hour);
280 rtc_data[4] = bin2bcd(tm->tm_mday);
281 rtc_data[5] = bin2bcd(tm->tm_mon + 1);
282 rtc_data[6] = bin2bcd(tm->tm_year - 100);
284 /* Stop RTC while updating the TC registers */
285 ret = twl_rtc_read_u8(&save_control, REG_RTC_CTRL_REG);
289 save_control &= ~BIT_RTC_CTRL_REG_STOP_RTC_M;
290 twl_rtc_write_u8(save_control, REG_RTC_CTRL_REG);
294 /* update all the time registers in one shot */
295 ret = twl_i2c_write(TWL_MODULE_RTC, rtc_data,
296 (rtc_reg_map[REG_SECONDS_REG]), ALL_TIME_REGS);
298 dev_err(dev, "rtc_set_time error %d\n", ret);
303 save_control |= BIT_RTC_CTRL_REG_STOP_RTC_M;
304 ret = twl_rtc_write_u8(save_control, REG_RTC_CTRL_REG);
311 * Gets current TWL RTC alarm time.
313 static int twl_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
315 unsigned char rtc_data[ALL_TIME_REGS + 1];
318 ret = twl_i2c_read(TWL_MODULE_RTC, rtc_data,
319 (rtc_reg_map[REG_ALARM_SECONDS_REG]), ALL_TIME_REGS);
321 dev_err(dev, "rtc_read_alarm error %d\n", ret);
325 /* some of these fields may be wildcard/"match all" */
326 alm->time.tm_sec = bcd2bin(rtc_data[0]);
327 alm->time.tm_min = bcd2bin(rtc_data[1]);
328 alm->time.tm_hour = bcd2bin(rtc_data[2]);
329 alm->time.tm_mday = bcd2bin(rtc_data[3]);
330 alm->time.tm_mon = bcd2bin(rtc_data[4]) - 1;
331 alm->time.tm_year = bcd2bin(rtc_data[5]) + 100;
333 /* report cached alarm enable state */
334 if (rtc_irq_bits & BIT_RTC_INTERRUPTS_REG_IT_ALARM_M)
340 static int twl_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
342 unsigned char alarm_data[ALL_TIME_REGS + 1];
345 ret = twl_rtc_alarm_irq_enable(dev, 0);
349 alarm_data[1] = bin2bcd(alm->time.tm_sec);
350 alarm_data[2] = bin2bcd(alm->time.tm_min);
351 alarm_data[3] = bin2bcd(alm->time.tm_hour);
352 alarm_data[4] = bin2bcd(alm->time.tm_mday);
353 alarm_data[5] = bin2bcd(alm->time.tm_mon + 1);
354 alarm_data[6] = bin2bcd(alm->time.tm_year - 100);
356 /* update all the alarm registers in one shot */
357 ret = twl_i2c_write(TWL_MODULE_RTC, alarm_data,
358 (rtc_reg_map[REG_ALARM_SECONDS_REG]), ALL_TIME_REGS);
360 dev_err(dev, "rtc_set_alarm error %d\n", ret);
365 ret = twl_rtc_alarm_irq_enable(dev, 1);
370 static irqreturn_t twl_rtc_interrupt(int irq, void *rtc)
372 unsigned long events = 0;
377 #ifdef CONFIG_LOCKDEP
378 /* WORKAROUND for lockdep forcing IRQF_DISABLED on us, which
379 * we don't want and can't tolerate. Although it might be
380 * friendlier not to borrow this thread context...
385 res = twl_rtc_read_u8(&rd_reg, REG_RTC_STATUS_REG);
389 * Figure out source of interrupt: ALARM or TIMER in RTC_STATUS_REG.
390 * only one (ALARM or RTC) interrupt source may be enabled
391 * at time, we also could check our results
392 * by reading RTS_INTERRUPTS_REGISTER[IT_TIMER,IT_ALARM]
394 if (rd_reg & BIT_RTC_STATUS_REG_ALARM_M)
395 events |= RTC_IRQF | RTC_AF;
397 events |= RTC_IRQF | RTC_UF;
399 res = twl_rtc_write_u8(rd_reg | BIT_RTC_STATUS_REG_ALARM_M,
404 if (twl_class_is_4030()) {
405 /* Clear on Read enabled. RTC_IT bit of TWL4030_INT_PWR_ISR1
406 * needs 2 reads to clear the interrupt. One read is done in
407 * do_twl_pwrirq(). Doing the second read, to clear
410 * FIXME the reason PWR_ISR1 needs an extra read is that
411 * RTC_IF retriggered until we cleared REG_ALARM_M above.
412 * But re-reading like this is a bad hack; by doing so we
413 * risk wrongly clearing status for some other IRQ (losing
414 * the interrupt). Be smarter about handling RTC_UF ...
416 res = twl_i2c_read_u8(TWL4030_MODULE_INT,
417 &rd_reg, TWL4030_INT_PWR_ISR1);
422 /* Notify RTC core on event */
423 rtc_update_irq(rtc, 1, events);
430 static struct rtc_class_ops twl_rtc_ops = {
431 .read_time = twl_rtc_read_time,
432 .set_time = twl_rtc_set_time,
433 .read_alarm = twl_rtc_read_alarm,
434 .set_alarm = twl_rtc_set_alarm,
435 .alarm_irq_enable = twl_rtc_alarm_irq_enable,
436 .update_irq_enable = twl_rtc_update_irq_enable,
439 /*----------------------------------------------------------------------*/
441 static int __devinit twl_rtc_probe(struct platform_device *pdev)
443 struct rtc_device *rtc;
445 int irq = platform_get_irq(pdev, 0);
451 rtc = rtc_device_register(pdev->name,
452 &pdev->dev, &twl_rtc_ops, THIS_MODULE);
455 dev_err(&pdev->dev, "can't register RTC device, err %ld\n",
461 platform_set_drvdata(pdev, rtc);
463 ret = twl_rtc_read_u8(&rd_reg, REG_RTC_STATUS_REG);
467 if (rd_reg & BIT_RTC_STATUS_REG_POWER_UP_M)
468 dev_warn(&pdev->dev, "Power up reset detected.\n");
470 if (rd_reg & BIT_RTC_STATUS_REG_ALARM_M)
471 dev_warn(&pdev->dev, "Pending Alarm interrupt detected.\n");
473 /* Clear RTC Power up reset and pending alarm interrupts */
474 ret = twl_rtc_write_u8(rd_reg, REG_RTC_STATUS_REG);
478 ret = request_irq(irq, twl_rtc_interrupt,
480 dev_name(&rtc->dev), rtc);
482 dev_err(&pdev->dev, "IRQ is not free.\n");
486 if (twl_class_is_6030()) {
487 twl6030_interrupt_unmask(TWL6030_RTC_INT_MASK,
489 twl6030_interrupt_unmask(TWL6030_RTC_INT_MASK,
493 /* Check RTC module status, Enable if it is off */
494 ret = twl_rtc_read_u8(&rd_reg, REG_RTC_CTRL_REG);
498 if (!(rd_reg & BIT_RTC_CTRL_REG_STOP_RTC_M)) {
499 dev_info(&pdev->dev, "Enabling TWL-RTC.\n");
500 rd_reg = BIT_RTC_CTRL_REG_STOP_RTC_M;
501 ret = twl_rtc_write_u8(rd_reg, REG_RTC_CTRL_REG);
506 /* init cached IRQ enable bits */
507 ret = twl_rtc_read_u8(&rtc_irq_bits, REG_RTC_INTERRUPTS_REG);
516 rtc_device_unregister(rtc);
522 * Disable all TWL RTC module interrupts.
523 * Sets status flag to free.
525 static int __devexit twl_rtc_remove(struct platform_device *pdev)
527 /* leave rtc running, but disable irqs */
528 struct rtc_device *rtc = platform_get_drvdata(pdev);
529 int irq = platform_get_irq(pdev, 0);
531 mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_ALARM_M);
532 mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_TIMER_M);
533 if (twl_class_is_6030()) {
534 twl6030_interrupt_mask(TWL6030_RTC_INT_MASK,
536 twl6030_interrupt_mask(TWL6030_RTC_INT_MASK,
543 rtc_device_unregister(rtc);
544 platform_set_drvdata(pdev, NULL);
548 static void twl_rtc_shutdown(struct platform_device *pdev)
550 /* mask timer interrupts, but leave alarm interrupts on to enable
551 power-on when alarm is triggered */
552 mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_TIMER_M);
557 static unsigned char irqstat;
559 static int twl_rtc_suspend(struct platform_device *pdev, pm_message_t state)
561 irqstat = rtc_irq_bits;
563 mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_TIMER_M);
567 static int twl_rtc_resume(struct platform_device *pdev)
569 set_rtc_irq_bit(irqstat);
574 #define twl_rtc_suspend NULL
575 #define twl_rtc_resume NULL
578 MODULE_ALIAS("platform:twl_rtc");
580 static struct platform_driver twl4030rtc_driver = {
581 .probe = twl_rtc_probe,
582 .remove = __devexit_p(twl_rtc_remove),
583 .shutdown = twl_rtc_shutdown,
584 .suspend = twl_rtc_suspend,
585 .resume = twl_rtc_resume,
587 .owner = THIS_MODULE,
592 static int __init twl_rtc_init(void)
594 if (twl_class_is_4030())
595 rtc_reg_map = (u8 *) twl4030_rtc_reg_map;
597 rtc_reg_map = (u8 *) twl6030_rtc_reg_map;
599 return platform_driver_register(&twl4030rtc_driver);
601 module_init(twl_rtc_init);
603 static void __exit twl_rtc_exit(void)
605 platform_driver_unregister(&twl4030rtc_driver);
607 module_exit(twl_rtc_exit);
609 MODULE_AUTHOR("Texas Instruments, MontaVista Software");
610 MODULE_LICENSE("GPL");