1 #define DRV_NAME "advansys"
2 #define ASC_VERSION "3.4" /* AdvanSys Driver Version */
5 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
7 * Copyright (c) 1995-2000 Advanced System Products, Inc.
8 * Copyright (c) 2000-2001 ConnectCom Solutions, Inc.
9 * Copyright (c) 2007 Matthew Wilcox <matthew@wil.cx>
10 * All Rights Reserved.
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
19 * As of March 8, 2000 Advanced System Products, Inc. (AdvanSys)
20 * changed its name to ConnectCom Solutions, Inc.
21 * On June 18, 2001 Initio Corp. acquired ConnectCom's SCSI assets
24 #include <linux/module.h>
25 #include <linux/string.h>
26 #include <linux/kernel.h>
27 #include <linux/types.h>
28 #include <linux/ioport.h>
29 #include <linux/interrupt.h>
30 #include <linux/delay.h>
31 #include <linux/slab.h>
33 #include <linux/proc_fs.h>
34 #include <linux/init.h>
35 #include <linux/blkdev.h>
36 #include <linux/isa.h>
37 #include <linux/eisa.h>
38 #include <linux/pci.h>
39 #include <linux/spinlock.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/firmware.h>
46 #include <scsi/scsi_cmnd.h>
47 #include <scsi/scsi_device.h>
48 #include <scsi/scsi_tcq.h>
49 #include <scsi/scsi.h>
50 #include <scsi/scsi_host.h>
54 * 1. Although all of the necessary command mapping places have the
55 * appropriate dma_map.. APIs, the driver still processes its internal
56 * queue using bus_to_virt() and virt_to_bus() which are illegal under
57 * the API. The entire queue processing structure will need to be
58 * altered to fix this.
59 * 2. Need to add memory mapping workaround. Test the memory mapping.
60 * If it doesn't work revert to I/O port access. Can a test be done
62 * 3. Handle an interrupt not working. Keep an interrupt counter in
63 * the interrupt handler. In the timeout function if the interrupt
64 * has not occurred then print a message and run in polled mode.
65 * 4. Need to add support for target mode commands, cf. CAM XPT.
66 * 5. check DMA mapping functions for failure
67 * 6. Use scsi_transport_spi
68 * 7. advansys_info is not safe against multiple simultaneous callers
69 * 8. Add module_param to override ISA/VLB ioport array
71 #warning this driver is still not properly converted to the DMA API
73 /* Enable driver /proc statistics. */
74 #define ADVANSYS_STATS
76 /* Enable driver tracing. */
79 typedef unsigned char uchar;
89 #define UW_ERR (uint)(0xFFFF)
90 #define isodd_word(val) ((((uint)val) & (uint)0x0001) != 0)
92 #define PCI_VENDOR_ID_ASP 0x10cd
93 #define PCI_DEVICE_ID_ASP_1200A 0x1100
94 #define PCI_DEVICE_ID_ASP_ABP940 0x1200
95 #define PCI_DEVICE_ID_ASP_ABP940U 0x1300
96 #define PCI_DEVICE_ID_ASP_ABP940UW 0x2300
97 #define PCI_DEVICE_ID_38C0800_REV1 0x2500
98 #define PCI_DEVICE_ID_38C1600_REV1 0x2700
101 * Enable CC_VERY_LONG_SG_LIST to support up to 64K element SG lists.
102 * The SRB structure will have to be changed and the ASC_SRB2SCSIQ()
103 * macro re-defined to be able to obtain a ASC_SCSI_Q pointer from the
106 #define CC_VERY_LONG_SG_LIST 0
107 #define ASC_SRB2SCSIQ(srb_ptr) (srb_ptr)
109 #define PortAddr unsigned int /* port address size */
110 #define inp(port) inb(port)
111 #define outp(port, byte) outb((byte), (port))
113 #define inpw(port) inw(port)
114 #define outpw(port, word) outw((word), (port))
116 #define ASC_MAX_SG_QUEUE 7
117 #define ASC_MAX_SG_LIST 255
119 #define ASC_CS_TYPE unsigned short
121 #define ASC_IS_ISA (0x0001)
122 #define ASC_IS_ISAPNP (0x0081)
123 #define ASC_IS_EISA (0x0002)
124 #define ASC_IS_PCI (0x0004)
125 #define ASC_IS_PCI_ULTRA (0x0104)
126 #define ASC_IS_PCMCIA (0x0008)
127 #define ASC_IS_MCA (0x0020)
128 #define ASC_IS_VL (0x0040)
129 #define ASC_IS_WIDESCSI_16 (0x0100)
130 #define ASC_IS_WIDESCSI_32 (0x0200)
131 #define ASC_IS_BIG_ENDIAN (0x8000)
133 #define ASC_CHIP_MIN_VER_VL (0x01)
134 #define ASC_CHIP_MAX_VER_VL (0x07)
135 #define ASC_CHIP_MIN_VER_PCI (0x09)
136 #define ASC_CHIP_MAX_VER_PCI (0x0F)
137 #define ASC_CHIP_VER_PCI_BIT (0x08)
138 #define ASC_CHIP_MIN_VER_ISA (0x11)
139 #define ASC_CHIP_MIN_VER_ISA_PNP (0x21)
140 #define ASC_CHIP_MAX_VER_ISA (0x27)
141 #define ASC_CHIP_VER_ISA_BIT (0x30)
142 #define ASC_CHIP_VER_ISAPNP_BIT (0x20)
143 #define ASC_CHIP_VER_ASYN_BUG (0x21)
144 #define ASC_CHIP_VER_PCI 0x08
145 #define ASC_CHIP_VER_PCI_ULTRA_3150 (ASC_CHIP_VER_PCI | 0x02)
146 #define ASC_CHIP_VER_PCI_ULTRA_3050 (ASC_CHIP_VER_PCI | 0x03)
147 #define ASC_CHIP_MIN_VER_EISA (0x41)
148 #define ASC_CHIP_MAX_VER_EISA (0x47)
149 #define ASC_CHIP_VER_EISA_BIT (0x40)
150 #define ASC_CHIP_LATEST_VER_EISA ((ASC_CHIP_MIN_VER_EISA - 1) + 3)
151 #define ASC_MAX_VL_DMA_COUNT (0x07FFFFFFL)
152 #define ASC_MAX_PCI_DMA_COUNT (0xFFFFFFFFL)
153 #define ASC_MAX_ISA_DMA_COUNT (0x00FFFFFFL)
155 #define ASC_SCSI_ID_BITS 3
156 #define ASC_SCSI_TIX_TYPE uchar
157 #define ASC_ALL_DEVICE_BIT_SET 0xFF
158 #define ASC_SCSI_BIT_ID_TYPE uchar
159 #define ASC_MAX_TID 7
160 #define ASC_MAX_LUN 7
161 #define ASC_SCSI_WIDTH_BIT_SET 0xFF
162 #define ASC_MAX_SENSE_LEN 32
163 #define ASC_MIN_SENSE_LEN 14
164 #define ASC_SCSI_RESET_HOLD_TIME_US 60
167 * Narrow boards only support 12-byte commands, while wide boards
168 * extend to 16-byte commands.
170 #define ASC_MAX_CDB_LEN 12
171 #define ADV_MAX_CDB_LEN 16
173 #define MS_SDTR_LEN 0x03
174 #define MS_WDTR_LEN 0x02
176 #define ASC_SG_LIST_PER_Q 7
178 #define QS_READY 0x01
179 #define QS_DISC1 0x02
180 #define QS_DISC2 0x04
182 #define QS_ABORTED 0x40
184 #define QC_NO_CALLBACK 0x01
185 #define QC_SG_SWAP_QUEUE 0x02
186 #define QC_SG_HEAD 0x04
187 #define QC_DATA_IN 0x08
188 #define QC_DATA_OUT 0x10
189 #define QC_URGENT 0x20
190 #define QC_MSG_OUT 0x40
191 #define QC_REQ_SENSE 0x80
192 #define QCSG_SG_XFER_LIST 0x02
193 #define QCSG_SG_XFER_MORE 0x04
194 #define QCSG_SG_XFER_END 0x08
195 #define QD_IN_PROGRESS 0x00
196 #define QD_NO_ERROR 0x01
197 #define QD_ABORTED_BY_HOST 0x02
198 #define QD_WITH_ERROR 0x04
199 #define QD_INVALID_REQUEST 0x80
200 #define QD_INVALID_HOST_NUM 0x81
201 #define QD_INVALID_DEVICE 0x82
202 #define QD_ERR_INTERNAL 0xFF
203 #define QHSTA_NO_ERROR 0x00
204 #define QHSTA_M_SEL_TIMEOUT 0x11
205 #define QHSTA_M_DATA_OVER_RUN 0x12
206 #define QHSTA_M_DATA_UNDER_RUN 0x12
207 #define QHSTA_M_UNEXPECTED_BUS_FREE 0x13
208 #define QHSTA_M_BAD_BUS_PHASE_SEQ 0x14
209 #define QHSTA_D_QDONE_SG_LIST_CORRUPTED 0x21
210 #define QHSTA_D_ASC_DVC_ERROR_CODE_SET 0x22
211 #define QHSTA_D_HOST_ABORT_FAILED 0x23
212 #define QHSTA_D_EXE_SCSI_Q_FAILED 0x24
213 #define QHSTA_D_EXE_SCSI_Q_BUSY_TIMEOUT 0x25
214 #define QHSTA_D_ASPI_NO_BUF_POOL 0x26
215 #define QHSTA_M_WTM_TIMEOUT 0x41
216 #define QHSTA_M_BAD_CMPL_STATUS_IN 0x42
217 #define QHSTA_M_NO_AUTO_REQ_SENSE 0x43
218 #define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
219 #define QHSTA_M_TARGET_STATUS_BUSY 0x45
220 #define QHSTA_M_BAD_TAG_CODE 0x46
221 #define QHSTA_M_BAD_QUEUE_FULL_OR_BUSY 0x47
222 #define QHSTA_M_HUNG_REQ_SCSI_BUS_RESET 0x48
223 #define QHSTA_D_LRAM_CMP_ERROR 0x81
224 #define QHSTA_M_MICRO_CODE_ERROR_HALT 0xA1
225 #define ASC_FLAG_SCSIQ_REQ 0x01
226 #define ASC_FLAG_BIOS_SCSIQ_REQ 0x02
227 #define ASC_FLAG_BIOS_ASYNC_IO 0x04
228 #define ASC_FLAG_SRB_LINEAR_ADDR 0x08
229 #define ASC_FLAG_WIN16 0x10
230 #define ASC_FLAG_WIN32 0x20
231 #define ASC_FLAG_ISA_OVER_16MB 0x40
232 #define ASC_FLAG_DOS_VM_CALLBACK 0x80
233 #define ASC_TAG_FLAG_EXTRA_BYTES 0x10
234 #define ASC_TAG_FLAG_DISABLE_DISCONNECT 0x04
235 #define ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX 0x08
236 #define ASC_TAG_FLAG_DISABLE_CHK_COND_INT_HOST 0x40
237 #define ASC_SCSIQ_CPY_BEG 4
238 #define ASC_SCSIQ_SGHD_CPY_BEG 2
239 #define ASC_SCSIQ_B_FWD 0
240 #define ASC_SCSIQ_B_BWD 1
241 #define ASC_SCSIQ_B_STATUS 2
242 #define ASC_SCSIQ_B_QNO 3
243 #define ASC_SCSIQ_B_CNTL 4
244 #define ASC_SCSIQ_B_SG_QUEUE_CNT 5
245 #define ASC_SCSIQ_D_DATA_ADDR 8
246 #define ASC_SCSIQ_D_DATA_CNT 12
247 #define ASC_SCSIQ_B_SENSE_LEN 20
248 #define ASC_SCSIQ_DONE_INFO_BEG 22
249 #define ASC_SCSIQ_D_SRBPTR 22
250 #define ASC_SCSIQ_B_TARGET_IX 26
251 #define ASC_SCSIQ_B_CDB_LEN 28
252 #define ASC_SCSIQ_B_TAG_CODE 29
253 #define ASC_SCSIQ_W_VM_ID 30
254 #define ASC_SCSIQ_DONE_STATUS 32
255 #define ASC_SCSIQ_HOST_STATUS 33
256 #define ASC_SCSIQ_SCSI_STATUS 34
257 #define ASC_SCSIQ_CDB_BEG 36
258 #define ASC_SCSIQ_DW_REMAIN_XFER_ADDR 56
259 #define ASC_SCSIQ_DW_REMAIN_XFER_CNT 60
260 #define ASC_SCSIQ_B_FIRST_SG_WK_QP 48
261 #define ASC_SCSIQ_B_SG_WK_QP 49
262 #define ASC_SCSIQ_B_SG_WK_IX 50
263 #define ASC_SCSIQ_W_ALT_DC1 52
264 #define ASC_SCSIQ_B_LIST_CNT 6
265 #define ASC_SCSIQ_B_CUR_LIST_CNT 7
266 #define ASC_SGQ_B_SG_CNTL 4
267 #define ASC_SGQ_B_SG_HEAD_QP 5
268 #define ASC_SGQ_B_SG_LIST_CNT 6
269 #define ASC_SGQ_B_SG_CUR_LIST_CNT 7
270 #define ASC_SGQ_LIST_BEG 8
271 #define ASC_DEF_SCSI1_QNG 4
272 #define ASC_MAX_SCSI1_QNG 4
273 #define ASC_DEF_SCSI2_QNG 16
274 #define ASC_MAX_SCSI2_QNG 32
275 #define ASC_TAG_CODE_MASK 0x23
276 #define ASC_STOP_REQ_RISC_STOP 0x01
277 #define ASC_STOP_ACK_RISC_STOP 0x03
278 #define ASC_STOP_CLEAN_UP_BUSY_Q 0x10
279 #define ASC_STOP_CLEAN_UP_DISC_Q 0x20
280 #define ASC_STOP_HOST_REQ_RISC_HALT 0x40
281 #define ASC_TIDLUN_TO_IX(tid, lun) (ASC_SCSI_TIX_TYPE)((tid) + ((lun)<<ASC_SCSI_ID_BITS))
282 #define ASC_TID_TO_TARGET_ID(tid) (ASC_SCSI_BIT_ID_TYPE)(0x01 << (tid))
283 #define ASC_TIX_TO_TARGET_ID(tix) (0x01 << ((tix) & ASC_MAX_TID))
284 #define ASC_TIX_TO_TID(tix) ((tix) & ASC_MAX_TID)
285 #define ASC_TID_TO_TIX(tid) ((tid) & ASC_MAX_TID)
286 #define ASC_TIX_TO_LUN(tix) (((tix) >> ASC_SCSI_ID_BITS) & ASC_MAX_LUN)
287 #define ASC_QNO_TO_QADDR(q_no) ((ASC_QADR_BEG)+((int)(q_no) << 6))
289 typedef struct asc_scsiq_1 {
303 typedef struct asc_scsiq_2 {
312 typedef struct asc_scsiq_3 {
319 typedef struct asc_scsiq_4 {
320 uchar cdb[ASC_MAX_CDB_LEN];
321 uchar y_first_sg_list_qp;
322 uchar y_working_sg_qp;
323 uchar y_working_sg_ix;
326 ushort x_reconnect_rtn;
327 __le32 x_saved_data_addr;
328 __le32 x_saved_data_cnt;
331 typedef struct asc_q_done_info {
343 typedef struct asc_sg_list {
348 typedef struct asc_sg_head {
351 ushort entry_to_copy;
353 ASC_SG_LIST sg_list[0];
356 typedef struct asc_scsi_q {
360 ASC_SG_HEAD *sg_head;
361 ushort remain_sg_entry_cnt;
362 ushort next_sg_index;
365 typedef struct asc_scsi_req_q {
369 ASC_SG_HEAD *sg_head;
372 uchar cdb[ASC_MAX_CDB_LEN];
373 uchar sense[ASC_MIN_SENSE_LEN];
376 typedef struct asc_scsi_bios_req_q {
380 ASC_SG_HEAD *sg_head;
383 uchar cdb[ASC_MAX_CDB_LEN];
384 uchar sense[ASC_MIN_SENSE_LEN];
385 } ASC_SCSI_BIOS_REQ_Q;
387 typedef struct asc_risc_q {
396 typedef struct asc_sg_list_q {
402 uchar sg_cur_list_cnt;
405 typedef struct asc_risc_sg_list_q {
409 ASC_SG_LIST sg_list[7];
410 } ASC_RISC_SG_LIST_Q;
412 #define ASCQ_ERR_Q_STATUS 0x0D
413 #define ASCQ_ERR_CUR_QNG 0x17
414 #define ASCQ_ERR_SG_Q_LINKS 0x18
415 #define ASCQ_ERR_ISR_RE_ENTRY 0x1A
416 #define ASCQ_ERR_CRITICAL_RE_ENTRY 0x1B
417 #define ASCQ_ERR_ISR_ON_CRITICAL 0x1C
420 * Warning code values are set in ASC_DVC_VAR 'warn_code'.
422 #define ASC_WARN_NO_ERROR 0x0000
423 #define ASC_WARN_IO_PORT_ROTATE 0x0001
424 #define ASC_WARN_EEPROM_CHKSUM 0x0002
425 #define ASC_WARN_IRQ_MODIFIED 0x0004
426 #define ASC_WARN_AUTO_CONFIG 0x0008
427 #define ASC_WARN_CMD_QNG_CONFLICT 0x0010
428 #define ASC_WARN_EEPROM_RECOVER 0x0020
429 #define ASC_WARN_CFG_MSW_RECOVER 0x0040
432 * Error code values are set in {ASC/ADV}_DVC_VAR 'err_code'.
434 #define ASC_IERR_NO_CARRIER 0x0001 /* No more carrier memory */
435 #define ASC_IERR_MCODE_CHKSUM 0x0002 /* micro code check sum error */
436 #define ASC_IERR_SET_PC_ADDR 0x0004
437 #define ASC_IERR_START_STOP_CHIP 0x0008 /* start/stop chip failed */
438 #define ASC_IERR_ILLEGAL_CONNECTION 0x0010 /* Illegal cable connection */
439 #define ASC_IERR_SINGLE_END_DEVICE 0x0020 /* SE device on DIFF bus */
440 #define ASC_IERR_REVERSED_CABLE 0x0040 /* Narrow flat cable reversed */
441 #define ASC_IERR_SET_SCSI_ID 0x0080 /* set SCSI ID failed */
442 #define ASC_IERR_HVD_DEVICE 0x0100 /* HVD device on LVD port */
443 #define ASC_IERR_BAD_SIGNATURE 0x0200 /* signature not found */
444 #define ASC_IERR_NO_BUS_TYPE 0x0400
445 #define ASC_IERR_BIST_PRE_TEST 0x0800 /* BIST pre-test error */
446 #define ASC_IERR_BIST_RAM_TEST 0x1000 /* BIST RAM test error */
447 #define ASC_IERR_BAD_CHIPTYPE 0x2000 /* Invalid chip_type setting */
449 #define ASC_DEF_MAX_TOTAL_QNG (0xF0)
450 #define ASC_MIN_TAG_Q_PER_DVC (0x04)
451 #define ASC_MIN_FREE_Q (0x02)
452 #define ASC_MIN_TOTAL_QNG ((ASC_MAX_SG_QUEUE)+(ASC_MIN_FREE_Q))
453 #define ASC_MAX_TOTAL_QNG 240
454 #define ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG 16
455 #define ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG 8
456 #define ASC_MAX_PCI_INRAM_TOTAL_QNG 20
457 #define ASC_MAX_INRAM_TAG_QNG 16
458 #define ASC_IOADR_GAP 0x10
459 #define ASC_SYN_MAX_OFFSET 0x0F
460 #define ASC_DEF_SDTR_OFFSET 0x0F
461 #define ASC_SDTR_ULTRA_PCI_10MB_INDEX 0x02
462 #define ASYN_SDTR_DATA_FIX_PCI_REV_AB 0x41
464 /* The narrow chip only supports a limited selection of transfer rates.
465 * These are encoded in the range 0..7 or 0..15 depending whether the chip
466 * is Ultra-capable or not. These tables let us convert from one to the other.
468 static const unsigned char asc_syn_xfer_period[8] = {
469 25, 30, 35, 40, 50, 60, 70, 85
472 static const unsigned char asc_syn_ultra_xfer_period[16] = {
473 12, 19, 25, 32, 38, 44, 50, 57, 63, 69, 75, 82, 88, 94, 100, 107
476 typedef struct ext_msg {
482 uchar sdtr_xfer_period;
483 uchar sdtr_req_ack_offset;
498 #define xfer_period u_ext_msg.sdtr.sdtr_xfer_period
499 #define req_ack_offset u_ext_msg.sdtr.sdtr_req_ack_offset
500 #define wdtr_width u_ext_msg.wdtr.wdtr_width
501 #define mdp_b3 u_ext_msg.mdp_b3
502 #define mdp_b2 u_ext_msg.mdp_b2
503 #define mdp_b1 u_ext_msg.mdp_b1
504 #define mdp_b0 u_ext_msg.mdp_b0
506 typedef struct asc_dvc_cfg {
507 ASC_SCSI_BIT_ID_TYPE can_tagged_qng;
508 ASC_SCSI_BIT_ID_TYPE cmd_qng_enabled;
509 ASC_SCSI_BIT_ID_TYPE disc_enable;
510 ASC_SCSI_BIT_ID_TYPE sdtr_enable;
513 uchar isa_dma_channel;
516 ushort mcode_version;
517 uchar max_tag_qng[ASC_MAX_TID + 1];
518 uchar sdtr_period_offset[ASC_MAX_TID + 1];
519 uchar adapter_info[6];
522 #define ASC_DEF_DVC_CNTL 0xFFFF
523 #define ASC_DEF_CHIP_SCSI_ID 7
524 #define ASC_DEF_ISA_DMA_SPEED 4
525 #define ASC_INIT_STATE_BEG_GET_CFG 0x0001
526 #define ASC_INIT_STATE_END_GET_CFG 0x0002
527 #define ASC_INIT_STATE_BEG_SET_CFG 0x0004
528 #define ASC_INIT_STATE_END_SET_CFG 0x0008
529 #define ASC_INIT_STATE_BEG_LOAD_MC 0x0010
530 #define ASC_INIT_STATE_END_LOAD_MC 0x0020
531 #define ASC_INIT_STATE_BEG_INQUIRY 0x0040
532 #define ASC_INIT_STATE_END_INQUIRY 0x0080
533 #define ASC_INIT_RESET_SCSI_DONE 0x0100
534 #define ASC_INIT_STATE_WITHOUT_EEP 0x8000
535 #define ASC_BUG_FIX_IF_NOT_DWB 0x0001
536 #define ASC_BUG_FIX_ASYN_USE_SYN 0x0002
537 #define ASC_MIN_TAGGED_CMD 7
538 #define ASC_MAX_SCSI_RESET_WAIT 30
539 #define ASC_OVERRUN_BSIZE 64
541 struct asc_dvc_var; /* Forward Declaration. */
543 typedef struct asc_dvc_var {
549 ASC_SCSI_BIT_ID_TYPE init_sdtr;
550 ASC_SCSI_BIT_ID_TYPE sdtr_done;
551 ASC_SCSI_BIT_ID_TYPE use_tagged_qng;
552 ASC_SCSI_BIT_ID_TYPE unit_not_ready;
553 ASC_SCSI_BIT_ID_TYPE queue_full_or_busy;
554 ASC_SCSI_BIT_ID_TYPE start_motor;
556 dma_addr_t overrun_dma;
557 uchar scsi_reset_wait;
562 uchar in_critical_cnt;
563 uchar last_q_shortage;
565 uchar cur_dvc_qng[ASC_MAX_TID + 1];
566 uchar max_dvc_qng[ASC_MAX_TID + 1];
567 ASC_SCSI_Q *scsiq_busy_head[ASC_MAX_TID + 1];
568 ASC_SCSI_Q *scsiq_busy_tail[ASC_MAX_TID + 1];
569 const uchar *sdtr_period_tbl;
571 ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer_always;
574 uchar dos_int13_table[ASC_MAX_TID + 1];
575 unsigned int max_dma_count;
576 ASC_SCSI_BIT_ID_TYPE no_scam;
577 ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer;
578 uchar min_sdtr_index;
579 uchar max_sdtr_index;
580 struct asc_board *drv_ptr;
581 unsigned int uc_break;
584 typedef struct asc_dvc_inq_info {
585 uchar type[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
588 typedef struct asc_cap_info {
593 typedef struct asc_cap_info_array {
594 ASC_CAP_INFO cap_info[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
595 } ASC_CAP_INFO_ARRAY;
597 #define ASC_MCNTL_NO_SEL_TIMEOUT (ushort)0x0001
598 #define ASC_MCNTL_NULL_TARGET (ushort)0x0002
599 #define ASC_CNTL_INITIATOR (ushort)0x0001
600 #define ASC_CNTL_BIOS_GT_1GB (ushort)0x0002
601 #define ASC_CNTL_BIOS_GT_2_DISK (ushort)0x0004
602 #define ASC_CNTL_BIOS_REMOVABLE (ushort)0x0008
603 #define ASC_CNTL_NO_SCAM (ushort)0x0010
604 #define ASC_CNTL_INT_MULTI_Q (ushort)0x0080
605 #define ASC_CNTL_NO_LUN_SUPPORT (ushort)0x0040
606 #define ASC_CNTL_NO_VERIFY_COPY (ushort)0x0100
607 #define ASC_CNTL_RESET_SCSI (ushort)0x0200
608 #define ASC_CNTL_INIT_INQUIRY (ushort)0x0400
609 #define ASC_CNTL_INIT_VERBOSE (ushort)0x0800
610 #define ASC_CNTL_SCSI_PARITY (ushort)0x1000
611 #define ASC_CNTL_BURST_MODE (ushort)0x2000
612 #define ASC_CNTL_SDTR_ENABLE_ULTRA (ushort)0x4000
613 #define ASC_EEP_DVC_CFG_BEG_VL 2
614 #define ASC_EEP_MAX_DVC_ADDR_VL 15
615 #define ASC_EEP_DVC_CFG_BEG 32
616 #define ASC_EEP_MAX_DVC_ADDR 45
617 #define ASC_EEP_MAX_RETRY 20
620 * These macros keep the chip SCSI id and ISA DMA speed
621 * bitfields in board order. C bitfields aren't portable
622 * between big and little-endian platforms so they are
626 #define ASC_EEP_GET_CHIP_ID(cfg) ((cfg)->id_speed & 0x0f)
627 #define ASC_EEP_GET_DMA_SPD(cfg) (((cfg)->id_speed & 0xf0) >> 4)
628 #define ASC_EEP_SET_CHIP_ID(cfg, sid) \
629 ((cfg)->id_speed = ((cfg)->id_speed & 0xf0) | ((sid) & ASC_MAX_TID))
630 #define ASC_EEP_SET_DMA_SPD(cfg, spd) \
631 ((cfg)->id_speed = ((cfg)->id_speed & 0x0f) | ((spd) & 0x0f) << 4)
633 typedef struct asceep_config {
645 uchar id_speed; /* low order 4 bits is chip scsi id */
646 /* high order 4 bits is isa dma speed */
647 uchar dos_int13_table[ASC_MAX_TID + 1];
648 uchar adapter_info[6];
653 #define ASC_EEP_CMD_READ 0x80
654 #define ASC_EEP_CMD_WRITE 0x40
655 #define ASC_EEP_CMD_WRITE_ABLE 0x30
656 #define ASC_EEP_CMD_WRITE_DISABLE 0x00
657 #define ASCV_MSGOUT_BEG 0x0000
658 #define ASCV_MSGOUT_SDTR_PERIOD (ASCV_MSGOUT_BEG+3)
659 #define ASCV_MSGOUT_SDTR_OFFSET (ASCV_MSGOUT_BEG+4)
660 #define ASCV_BREAK_SAVED_CODE (ushort)0x0006
661 #define ASCV_MSGIN_BEG (ASCV_MSGOUT_BEG+8)
662 #define ASCV_MSGIN_SDTR_PERIOD (ASCV_MSGIN_BEG+3)
663 #define ASCV_MSGIN_SDTR_OFFSET (ASCV_MSGIN_BEG+4)
664 #define ASCV_SDTR_DATA_BEG (ASCV_MSGIN_BEG+8)
665 #define ASCV_SDTR_DONE_BEG (ASCV_SDTR_DATA_BEG+8)
666 #define ASCV_MAX_DVC_QNG_BEG (ushort)0x0020
667 #define ASCV_BREAK_ADDR (ushort)0x0028
668 #define ASCV_BREAK_NOTIFY_COUNT (ushort)0x002A
669 #define ASCV_BREAK_CONTROL (ushort)0x002C
670 #define ASCV_BREAK_HIT_COUNT (ushort)0x002E
672 #define ASCV_ASCDVC_ERR_CODE_W (ushort)0x0030
673 #define ASCV_MCODE_CHKSUM_W (ushort)0x0032
674 #define ASCV_MCODE_SIZE_W (ushort)0x0034
675 #define ASCV_STOP_CODE_B (ushort)0x0036
676 #define ASCV_DVC_ERR_CODE_B (ushort)0x0037
677 #define ASCV_OVERRUN_PADDR_D (ushort)0x0038
678 #define ASCV_OVERRUN_BSIZE_D (ushort)0x003C
679 #define ASCV_HALTCODE_W (ushort)0x0040
680 #define ASCV_CHKSUM_W (ushort)0x0042
681 #define ASCV_MC_DATE_W (ushort)0x0044
682 #define ASCV_MC_VER_W (ushort)0x0046
683 #define ASCV_NEXTRDY_B (ushort)0x0048
684 #define ASCV_DONENEXT_B (ushort)0x0049
685 #define ASCV_USE_TAGGED_QNG_B (ushort)0x004A
686 #define ASCV_SCSIBUSY_B (ushort)0x004B
687 #define ASCV_Q_DONE_IN_PROGRESS_B (ushort)0x004C
688 #define ASCV_CURCDB_B (ushort)0x004D
689 #define ASCV_RCLUN_B (ushort)0x004E
690 #define ASCV_BUSY_QHEAD_B (ushort)0x004F
691 #define ASCV_DISC1_QHEAD_B (ushort)0x0050
692 #define ASCV_DISC_ENABLE_B (ushort)0x0052
693 #define ASCV_CAN_TAGGED_QNG_B (ushort)0x0053
694 #define ASCV_HOSTSCSI_ID_B (ushort)0x0055
695 #define ASCV_MCODE_CNTL_B (ushort)0x0056
696 #define ASCV_NULL_TARGET_B (ushort)0x0057
697 #define ASCV_FREE_Q_HEAD_W (ushort)0x0058
698 #define ASCV_DONE_Q_TAIL_W (ushort)0x005A
699 #define ASCV_FREE_Q_HEAD_B (ushort)(ASCV_FREE_Q_HEAD_W+1)
700 #define ASCV_DONE_Q_TAIL_B (ushort)(ASCV_DONE_Q_TAIL_W+1)
701 #define ASCV_HOST_FLAG_B (ushort)0x005D
702 #define ASCV_TOTAL_READY_Q_B (ushort)0x0064
703 #define ASCV_VER_SERIAL_B (ushort)0x0065
704 #define ASCV_HALTCODE_SAVED_W (ushort)0x0066
705 #define ASCV_WTM_FLAG_B (ushort)0x0068
706 #define ASCV_RISC_FLAG_B (ushort)0x006A
707 #define ASCV_REQ_SG_LIST_QP (ushort)0x006B
708 #define ASC_HOST_FLAG_IN_ISR 0x01
709 #define ASC_HOST_FLAG_ACK_INT 0x02
710 #define ASC_RISC_FLAG_GEN_INT 0x01
711 #define ASC_RISC_FLAG_REQ_SG_LIST 0x02
712 #define IOP_CTRL (0x0F)
713 #define IOP_STATUS (0x0E)
714 #define IOP_INT_ACK IOP_STATUS
715 #define IOP_REG_IFC (0x0D)
716 #define IOP_SYN_OFFSET (0x0B)
717 #define IOP_EXTRA_CONTROL (0x0D)
718 #define IOP_REG_PC (0x0C)
719 #define IOP_RAM_ADDR (0x0A)
720 #define IOP_RAM_DATA (0x08)
721 #define IOP_EEP_DATA (0x06)
722 #define IOP_EEP_CMD (0x07)
723 #define IOP_VERSION (0x03)
724 #define IOP_CONFIG_HIGH (0x04)
725 #define IOP_CONFIG_LOW (0x02)
726 #define IOP_SIG_BYTE (0x01)
727 #define IOP_SIG_WORD (0x00)
728 #define IOP_REG_DC1 (0x0E)
729 #define IOP_REG_DC0 (0x0C)
730 #define IOP_REG_SB (0x0B)
731 #define IOP_REG_DA1 (0x0A)
732 #define IOP_REG_DA0 (0x08)
733 #define IOP_REG_SC (0x09)
734 #define IOP_DMA_SPEED (0x07)
735 #define IOP_REG_FLAG (0x07)
736 #define IOP_FIFO_H (0x06)
737 #define IOP_FIFO_L (0x04)
738 #define IOP_REG_ID (0x05)
739 #define IOP_REG_QP (0x03)
740 #define IOP_REG_IH (0x02)
741 #define IOP_REG_IX (0x01)
742 #define IOP_REG_AX (0x00)
743 #define IFC_REG_LOCK (0x00)
744 #define IFC_REG_UNLOCK (0x09)
745 #define IFC_WR_EN_FILTER (0x10)
746 #define IFC_RD_NO_EEPROM (0x10)
747 #define IFC_SLEW_RATE (0x20)
748 #define IFC_ACT_NEG (0x40)
749 #define IFC_INP_FILTER (0x80)
750 #define IFC_INIT_DEFAULT (IFC_ACT_NEG | IFC_REG_UNLOCK)
751 #define SC_SEL (uchar)(0x80)
752 #define SC_BSY (uchar)(0x40)
753 #define SC_ACK (uchar)(0x20)
754 #define SC_REQ (uchar)(0x10)
755 #define SC_ATN (uchar)(0x08)
756 #define SC_IO (uchar)(0x04)
757 #define SC_CD (uchar)(0x02)
758 #define SC_MSG (uchar)(0x01)
759 #define SEC_SCSI_CTL (uchar)(0x80)
760 #define SEC_ACTIVE_NEGATE (uchar)(0x40)
761 #define SEC_SLEW_RATE (uchar)(0x20)
762 #define SEC_ENABLE_FILTER (uchar)(0x10)
763 #define ASC_HALT_EXTMSG_IN (ushort)0x8000
764 #define ASC_HALT_CHK_CONDITION (ushort)0x8100
765 #define ASC_HALT_SS_QUEUE_FULL (ushort)0x8200
766 #define ASC_HALT_DISABLE_ASYN_USE_SYN_FIX (ushort)0x8300
767 #define ASC_HALT_ENABLE_ASYN_USE_SYN_FIX (ushort)0x8400
768 #define ASC_HALT_SDTR_REJECTED (ushort)0x4000
769 #define ASC_HALT_HOST_COPY_SG_LIST_TO_RISC ( ushort )0x2000
770 #define ASC_MAX_QNO 0xF8
771 #define ASC_DATA_SEC_BEG (ushort)0x0080
772 #define ASC_DATA_SEC_END (ushort)0x0080
773 #define ASC_CODE_SEC_BEG (ushort)0x0080
774 #define ASC_CODE_SEC_END (ushort)0x0080
775 #define ASC_QADR_BEG (0x4000)
776 #define ASC_QADR_USED (ushort)(ASC_MAX_QNO * 64)
777 #define ASC_QADR_END (ushort)0x7FFF
778 #define ASC_QLAST_ADR (ushort)0x7FC0
779 #define ASC_QBLK_SIZE 0x40
780 #define ASC_BIOS_DATA_QBEG 0xF8
781 #define ASC_MIN_ACTIVE_QNO 0x01
782 #define ASC_QLINK_END 0xFF
783 #define ASC_EEPROM_WORDS 0x10
784 #define ASC_MAX_MGS_LEN 0x10
785 #define ASC_BIOS_ADDR_DEF 0xDC00
786 #define ASC_BIOS_SIZE 0x3800
787 #define ASC_BIOS_RAM_OFF 0x3800
788 #define ASC_BIOS_RAM_SIZE 0x800
789 #define ASC_BIOS_MIN_ADDR 0xC000
790 #define ASC_BIOS_MAX_ADDR 0xEC00
791 #define ASC_BIOS_BANK_SIZE 0x0400
792 #define ASC_MCODE_START_ADDR 0x0080
793 #define ASC_CFG0_HOST_INT_ON 0x0020
794 #define ASC_CFG0_BIOS_ON 0x0040
795 #define ASC_CFG0_VERA_BURST_ON 0x0080
796 #define ASC_CFG0_SCSI_PARITY_ON 0x0800
797 #define ASC_CFG1_SCSI_TARGET_ON 0x0080
798 #define ASC_CFG1_LRAM_8BITS_ON 0x0800
799 #define ASC_CFG_MSW_CLR_MASK 0x3080
800 #define CSW_TEST1 (ASC_CS_TYPE)0x8000
801 #define CSW_AUTO_CONFIG (ASC_CS_TYPE)0x4000
802 #define CSW_RESERVED1 (ASC_CS_TYPE)0x2000
803 #define CSW_IRQ_WRITTEN (ASC_CS_TYPE)0x1000
804 #define CSW_33MHZ_SELECTED (ASC_CS_TYPE)0x0800
805 #define CSW_TEST2 (ASC_CS_TYPE)0x0400
806 #define CSW_TEST3 (ASC_CS_TYPE)0x0200
807 #define CSW_RESERVED2 (ASC_CS_TYPE)0x0100
808 #define CSW_DMA_DONE (ASC_CS_TYPE)0x0080
809 #define CSW_FIFO_RDY (ASC_CS_TYPE)0x0040
810 #define CSW_EEP_READ_DONE (ASC_CS_TYPE)0x0020
811 #define CSW_HALTED (ASC_CS_TYPE)0x0010
812 #define CSW_SCSI_RESET_ACTIVE (ASC_CS_TYPE)0x0008
813 #define CSW_PARITY_ERR (ASC_CS_TYPE)0x0004
814 #define CSW_SCSI_RESET_LATCH (ASC_CS_TYPE)0x0002
815 #define CSW_INT_PENDING (ASC_CS_TYPE)0x0001
816 #define CIW_CLR_SCSI_RESET_INT (ASC_CS_TYPE)0x1000
817 #define CIW_INT_ACK (ASC_CS_TYPE)0x0100
818 #define CIW_TEST1 (ASC_CS_TYPE)0x0200
819 #define CIW_TEST2 (ASC_CS_TYPE)0x0400
820 #define CIW_SEL_33MHZ (ASC_CS_TYPE)0x0800
821 #define CIW_IRQ_ACT (ASC_CS_TYPE)0x1000
822 #define CC_CHIP_RESET (uchar)0x80
823 #define CC_SCSI_RESET (uchar)0x40
824 #define CC_HALT (uchar)0x20
825 #define CC_SINGLE_STEP (uchar)0x10
826 #define CC_DMA_ABLE (uchar)0x08
827 #define CC_TEST (uchar)0x04
828 #define CC_BANK_ONE (uchar)0x02
829 #define CC_DIAG (uchar)0x01
830 #define ASC_1000_ID0W 0x04C1
831 #define ASC_1000_ID0W_FIX 0x00C1
832 #define ASC_1000_ID1B 0x25
833 #define ASC_EISA_REV_IOP_MASK (0x0C83)
834 #define ASC_EISA_CFG_IOP_MASK (0x0C86)
835 #define ASC_GET_EISA_SLOT(iop) (PortAddr)((iop) & 0xF000)
836 #define INS_HALTINT (ushort)0x6281
837 #define INS_HALT (ushort)0x6280
838 #define INS_SINT (ushort)0x6200
839 #define INS_RFLAG_WTM (ushort)0x7380
840 #define ASC_MC_SAVE_CODE_WSIZE 0x500
841 #define ASC_MC_SAVE_DATA_WSIZE 0x40
843 typedef struct asc_mc_saved {
844 ushort data[ASC_MC_SAVE_DATA_WSIZE];
845 ushort code[ASC_MC_SAVE_CODE_WSIZE];
848 #define AscGetQDoneInProgress(port) AscReadLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B)
849 #define AscPutQDoneInProgress(port, val) AscWriteLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B, val)
850 #define AscGetVarFreeQHead(port) AscReadLramWord((port), ASCV_FREE_Q_HEAD_W)
851 #define AscGetVarDoneQTail(port) AscReadLramWord((port), ASCV_DONE_Q_TAIL_W)
852 #define AscPutVarFreeQHead(port, val) AscWriteLramWord((port), ASCV_FREE_Q_HEAD_W, val)
853 #define AscPutVarDoneQTail(port, val) AscWriteLramWord((port), ASCV_DONE_Q_TAIL_W, val)
854 #define AscGetRiscVarFreeQHead(port) AscReadLramByte((port), ASCV_NEXTRDY_B)
855 #define AscGetRiscVarDoneQTail(port) AscReadLramByte((port), ASCV_DONENEXT_B)
856 #define AscPutRiscVarFreeQHead(port, val) AscWriteLramByte((port), ASCV_NEXTRDY_B, val)
857 #define AscPutRiscVarDoneQTail(port, val) AscWriteLramByte((port), ASCV_DONENEXT_B, val)
858 #define AscPutMCodeSDTRDoneAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id), (data))
859 #define AscGetMCodeSDTRDoneAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id))
860 #define AscPutMCodeInitSDTRAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id), data)
861 #define AscGetMCodeInitSDTRAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id))
862 #define AscGetChipSignatureByte(port) (uchar)inp((port)+IOP_SIG_BYTE)
863 #define AscGetChipSignatureWord(port) (ushort)inpw((port)+IOP_SIG_WORD)
864 #define AscGetChipVerNo(port) (uchar)inp((port)+IOP_VERSION)
865 #define AscGetChipCfgLsw(port) (ushort)inpw((port)+IOP_CONFIG_LOW)
866 #define AscGetChipCfgMsw(port) (ushort)inpw((port)+IOP_CONFIG_HIGH)
867 #define AscSetChipCfgLsw(port, data) outpw((port)+IOP_CONFIG_LOW, data)
868 #define AscSetChipCfgMsw(port, data) outpw((port)+IOP_CONFIG_HIGH, data)
869 #define AscGetChipEEPCmd(port) (uchar)inp((port)+IOP_EEP_CMD)
870 #define AscSetChipEEPCmd(port, data) outp((port)+IOP_EEP_CMD, data)
871 #define AscGetChipEEPData(port) (ushort)inpw((port)+IOP_EEP_DATA)
872 #define AscSetChipEEPData(port, data) outpw((port)+IOP_EEP_DATA, data)
873 #define AscGetChipLramAddr(port) (ushort)inpw((PortAddr)((port)+IOP_RAM_ADDR))
874 #define AscSetChipLramAddr(port, addr) outpw((PortAddr)((port)+IOP_RAM_ADDR), addr)
875 #define AscGetChipLramData(port) (ushort)inpw((port)+IOP_RAM_DATA)
876 #define AscSetChipLramData(port, data) outpw((port)+IOP_RAM_DATA, data)
877 #define AscGetChipIFC(port) (uchar)inp((port)+IOP_REG_IFC)
878 #define AscSetChipIFC(port, data) outp((port)+IOP_REG_IFC, data)
879 #define AscGetChipStatus(port) (ASC_CS_TYPE)inpw((port)+IOP_STATUS)
880 #define AscSetChipStatus(port, cs_val) outpw((port)+IOP_STATUS, cs_val)
881 #define AscGetChipControl(port) (uchar)inp((port)+IOP_CTRL)
882 #define AscSetChipControl(port, cc_val) outp((port)+IOP_CTRL, cc_val)
883 #define AscGetChipSyn(port) (uchar)inp((port)+IOP_SYN_OFFSET)
884 #define AscSetChipSyn(port, data) outp((port)+IOP_SYN_OFFSET, data)
885 #define AscSetPCAddr(port, data) outpw((port)+IOP_REG_PC, data)
886 #define AscGetPCAddr(port) (ushort)inpw((port)+IOP_REG_PC)
887 #define AscIsIntPending(port) (AscGetChipStatus(port) & (CSW_INT_PENDING | CSW_SCSI_RESET_LATCH))
888 #define AscGetChipScsiID(port) ((AscGetChipCfgLsw(port) >> 8) & ASC_MAX_TID)
889 #define AscGetExtraControl(port) (uchar)inp((port)+IOP_EXTRA_CONTROL)
890 #define AscSetExtraControl(port, data) outp((port)+IOP_EXTRA_CONTROL, data)
891 #define AscReadChipAX(port) (ushort)inpw((port)+IOP_REG_AX)
892 #define AscWriteChipAX(port, data) outpw((port)+IOP_REG_AX, data)
893 #define AscReadChipIX(port) (uchar)inp((port)+IOP_REG_IX)
894 #define AscWriteChipIX(port, data) outp((port)+IOP_REG_IX, data)
895 #define AscReadChipIH(port) (ushort)inpw((port)+IOP_REG_IH)
896 #define AscWriteChipIH(port, data) outpw((port)+IOP_REG_IH, data)
897 #define AscReadChipQP(port) (uchar)inp((port)+IOP_REG_QP)
898 #define AscWriteChipQP(port, data) outp((port)+IOP_REG_QP, data)
899 #define AscReadChipFIFO_L(port) (ushort)inpw((port)+IOP_REG_FIFO_L)
900 #define AscWriteChipFIFO_L(port, data) outpw((port)+IOP_REG_FIFO_L, data)
901 #define AscReadChipFIFO_H(port) (ushort)inpw((port)+IOP_REG_FIFO_H)
902 #define AscWriteChipFIFO_H(port, data) outpw((port)+IOP_REG_FIFO_H, data)
903 #define AscReadChipDmaSpeed(port) (uchar)inp((port)+IOP_DMA_SPEED)
904 #define AscWriteChipDmaSpeed(port, data) outp((port)+IOP_DMA_SPEED, data)
905 #define AscReadChipDA0(port) (ushort)inpw((port)+IOP_REG_DA0)
906 #define AscWriteChipDA0(port) outpw((port)+IOP_REG_DA0, data)
907 #define AscReadChipDA1(port) (ushort)inpw((port)+IOP_REG_DA1)
908 #define AscWriteChipDA1(port) outpw((port)+IOP_REG_DA1, data)
909 #define AscReadChipDC0(port) (ushort)inpw((port)+IOP_REG_DC0)
910 #define AscWriteChipDC0(port) outpw((port)+IOP_REG_DC0, data)
911 #define AscReadChipDC1(port) (ushort)inpw((port)+IOP_REG_DC1)
912 #define AscWriteChipDC1(port) outpw((port)+IOP_REG_DC1, data)
913 #define AscReadChipDvcID(port) (uchar)inp((port)+IOP_REG_ID)
914 #define AscWriteChipDvcID(port, data) outp((port)+IOP_REG_ID, data)
917 * These macros are used to convert a virtual address to a
918 * 32-bit value. This currently can be used on Linux Alpha
919 * which uses 64-bit virtual address but a 32-bit bus address.
920 * This is likely to break in the future, but doing this now
921 * will give us time to change the HW and FW to handle 64-bit
924 #define ADV_U32_TO_VADDR bus_to_virt
926 #define AdvPortAddr void __iomem * /* Virtual memory address size */
929 * Define Adv Library required memory access macros.
931 #define ADV_MEM_READB(addr) readb(addr)
932 #define ADV_MEM_READW(addr) readw(addr)
933 #define ADV_MEM_WRITEB(addr, byte) writeb(byte, addr)
934 #define ADV_MEM_WRITEW(addr, word) writew(word, addr)
935 #define ADV_MEM_WRITEDW(addr, dword) writel(dword, addr)
938 * Define total number of simultaneous maximum element scatter-gather
939 * request blocks per wide adapter. ASC_DEF_MAX_HOST_QNG (253) is the
940 * maximum number of outstanding commands per wide host adapter. Each
941 * command uses one or more ADV_SG_BLOCK each with 15 scatter-gather
942 * elements. Allow each command to have at least one ADV_SG_BLOCK structure.
943 * This allows about 15 commands to have the maximum 17 ADV_SG_BLOCK
944 * structures or 255 scatter-gather elements.
946 #define ADV_TOT_SG_BLOCK ASC_DEF_MAX_HOST_QNG
949 * Define maximum number of scatter-gather elements per request.
951 #define ADV_MAX_SG_LIST 255
952 #define NO_OF_SG_PER_BLOCK 15
954 #define ADV_EEP_DVC_CFG_BEGIN (0x00)
955 #define ADV_EEP_DVC_CFG_END (0x15)
956 #define ADV_EEP_DVC_CTL_BEGIN (0x16) /* location of OEM name */
957 #define ADV_EEP_MAX_WORD_ADDR (0x1E)
959 #define ADV_EEP_DELAY_MS 100
961 #define ADV_EEPROM_BIG_ENDIAN 0x8000 /* EEPROM Bit 15 */
962 #define ADV_EEPROM_BIOS_ENABLE 0x4000 /* EEPROM Bit 14 */
964 * For the ASC3550 Bit 13 is Termination Polarity control bit.
965 * For later ICs Bit 13 controls whether the CIS (Card Information
966 * Service Section) is loaded from EEPROM.
968 #define ADV_EEPROM_TERM_POL 0x2000 /* EEPROM Bit 13 */
969 #define ADV_EEPROM_CIS_LD 0x2000 /* EEPROM Bit 13 */
973 * If EEPROM Bit 11 is 0 for Function 0, then Function 0 will specify
974 * INT A in the PCI Configuration Space Int Pin field. If it is 1, then
975 * Function 0 will specify INT B.
977 * If EEPROM Bit 11 is 0 for Function 1, then Function 1 will specify
978 * INT B in the PCI Configuration Space Int Pin field. If it is 1, then
979 * Function 1 will specify INT A.
981 #define ADV_EEPROM_INTAB 0x0800 /* EEPROM Bit 11 */
983 typedef struct adveep_3550_config {
984 /* Word Offset, Description */
986 ushort cfg_lsw; /* 00 power up initialization */
987 /* bit 13 set - Term Polarity Control */
988 /* bit 14 set - BIOS Enable */
989 /* bit 15 set - Big Endian Mode */
990 ushort cfg_msw; /* 01 unused */
991 ushort disc_enable; /* 02 disconnect enable */
992 ushort wdtr_able; /* 03 Wide DTR able */
993 ushort sdtr_able; /* 04 Synchronous DTR able */
994 ushort start_motor; /* 05 send start up motor */
995 ushort tagqng_able; /* 06 tag queuing able */
996 ushort bios_scan; /* 07 BIOS device control */
997 ushort scam_tolerant; /* 08 no scam */
999 uchar adapter_scsi_id; /* 09 Host Adapter ID */
1000 uchar bios_boot_delay; /* power up wait */
1002 uchar scsi_reset_delay; /* 10 reset delay */
1003 uchar bios_id_lun; /* first boot device scsi id & lun */
1004 /* high nibble is lun */
1005 /* low nibble is scsi id */
1007 uchar termination; /* 11 0 - automatic */
1008 /* 1 - low off / high off */
1009 /* 2 - low off / high on */
1010 /* 3 - low on / high on */
1011 /* There is no low on / high off */
1013 uchar reserved1; /* reserved byte (not used) */
1015 ushort bios_ctrl; /* 12 BIOS control bits */
1016 /* bit 0 BIOS don't act as initiator. */
1017 /* bit 1 BIOS > 1 GB support */
1018 /* bit 2 BIOS > 2 Disk Support */
1019 /* bit 3 BIOS don't support removables */
1020 /* bit 4 BIOS support bootable CD */
1021 /* bit 5 BIOS scan enabled */
1022 /* bit 6 BIOS support multiple LUNs */
1023 /* bit 7 BIOS display of message */
1024 /* bit 8 SCAM disabled */
1025 /* bit 9 Reset SCSI bus during init. */
1027 /* bit 11 No verbose initialization. */
1028 /* bit 12 SCSI parity enabled */
1032 ushort ultra_able; /* 13 ULTRA speed able */
1033 ushort reserved2; /* 14 reserved */
1034 uchar max_host_qng; /* 15 maximum host queuing */
1035 uchar max_dvc_qng; /* maximum per device queuing */
1036 ushort dvc_cntl; /* 16 control bit for driver */
1037 ushort bug_fix; /* 17 control bit for bug fix */
1038 ushort serial_number_word1; /* 18 Board serial number word 1 */
1039 ushort serial_number_word2; /* 19 Board serial number word 2 */
1040 ushort serial_number_word3; /* 20 Board serial number word 3 */
1041 ushort check_sum; /* 21 EEP check sum */
1042 uchar oem_name[16]; /* 22 OEM name */
1043 ushort dvc_err_code; /* 30 last device driver error code */
1044 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
1045 ushort adv_err_addr; /* 32 last uc error address */
1046 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
1047 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
1048 ushort saved_adv_err_addr; /* 35 saved last uc error address */
1049 ushort num_of_err; /* 36 number of error */
1050 } ADVEEP_3550_CONFIG;
1052 typedef struct adveep_38C0800_config {
1053 /* Word Offset, Description */
1055 ushort cfg_lsw; /* 00 power up initialization */
1056 /* bit 13 set - Load CIS */
1057 /* bit 14 set - BIOS Enable */
1058 /* bit 15 set - Big Endian Mode */
1059 ushort cfg_msw; /* 01 unused */
1060 ushort disc_enable; /* 02 disconnect enable */
1061 ushort wdtr_able; /* 03 Wide DTR able */
1062 ushort sdtr_speed1; /* 04 SDTR Speed TID 0-3 */
1063 ushort start_motor; /* 05 send start up motor */
1064 ushort tagqng_able; /* 06 tag queuing able */
1065 ushort bios_scan; /* 07 BIOS device control */
1066 ushort scam_tolerant; /* 08 no scam */
1068 uchar adapter_scsi_id; /* 09 Host Adapter ID */
1069 uchar bios_boot_delay; /* power up wait */
1071 uchar scsi_reset_delay; /* 10 reset delay */
1072 uchar bios_id_lun; /* first boot device scsi id & lun */
1073 /* high nibble is lun */
1074 /* low nibble is scsi id */
1076 uchar termination_se; /* 11 0 - automatic */
1077 /* 1 - low off / high off */
1078 /* 2 - low off / high on */
1079 /* 3 - low on / high on */
1080 /* There is no low on / high off */
1082 uchar termination_lvd; /* 11 0 - automatic */
1083 /* 1 - low off / high off */
1084 /* 2 - low off / high on */
1085 /* 3 - low on / high on */
1086 /* There is no low on / high off */
1088 ushort bios_ctrl; /* 12 BIOS control bits */
1089 /* bit 0 BIOS don't act as initiator. */
1090 /* bit 1 BIOS > 1 GB support */
1091 /* bit 2 BIOS > 2 Disk Support */
1092 /* bit 3 BIOS don't support removables */
1093 /* bit 4 BIOS support bootable CD */
1094 /* bit 5 BIOS scan enabled */
1095 /* bit 6 BIOS support multiple LUNs */
1096 /* bit 7 BIOS display of message */
1097 /* bit 8 SCAM disabled */
1098 /* bit 9 Reset SCSI bus during init. */
1100 /* bit 11 No verbose initialization. */
1101 /* bit 12 SCSI parity enabled */
1105 ushort sdtr_speed2; /* 13 SDTR speed TID 4-7 */
1106 ushort sdtr_speed3; /* 14 SDTR speed TID 8-11 */
1107 uchar max_host_qng; /* 15 maximum host queueing */
1108 uchar max_dvc_qng; /* maximum per device queuing */
1109 ushort dvc_cntl; /* 16 control bit for driver */
1110 ushort sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */
1111 ushort serial_number_word1; /* 18 Board serial number word 1 */
1112 ushort serial_number_word2; /* 19 Board serial number word 2 */
1113 ushort serial_number_word3; /* 20 Board serial number word 3 */
1114 ushort check_sum; /* 21 EEP check sum */
1115 uchar oem_name[16]; /* 22 OEM name */
1116 ushort dvc_err_code; /* 30 last device driver error code */
1117 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
1118 ushort adv_err_addr; /* 32 last uc error address */
1119 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
1120 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
1121 ushort saved_adv_err_addr; /* 35 saved last uc error address */
1122 ushort reserved36; /* 36 reserved */
1123 ushort reserved37; /* 37 reserved */
1124 ushort reserved38; /* 38 reserved */
1125 ushort reserved39; /* 39 reserved */
1126 ushort reserved40; /* 40 reserved */
1127 ushort reserved41; /* 41 reserved */
1128 ushort reserved42; /* 42 reserved */
1129 ushort reserved43; /* 43 reserved */
1130 ushort reserved44; /* 44 reserved */
1131 ushort reserved45; /* 45 reserved */
1132 ushort reserved46; /* 46 reserved */
1133 ushort reserved47; /* 47 reserved */
1134 ushort reserved48; /* 48 reserved */
1135 ushort reserved49; /* 49 reserved */
1136 ushort reserved50; /* 50 reserved */
1137 ushort reserved51; /* 51 reserved */
1138 ushort reserved52; /* 52 reserved */
1139 ushort reserved53; /* 53 reserved */
1140 ushort reserved54; /* 54 reserved */
1141 ushort reserved55; /* 55 reserved */
1142 ushort cisptr_lsw; /* 56 CIS PTR LSW */
1143 ushort cisprt_msw; /* 57 CIS PTR MSW */
1144 ushort subsysvid; /* 58 SubSystem Vendor ID */
1145 ushort subsysid; /* 59 SubSystem ID */
1146 ushort reserved60; /* 60 reserved */
1147 ushort reserved61; /* 61 reserved */
1148 ushort reserved62; /* 62 reserved */
1149 ushort reserved63; /* 63 reserved */
1150 } ADVEEP_38C0800_CONFIG;
1152 typedef struct adveep_38C1600_config {
1153 /* Word Offset, Description */
1155 ushort cfg_lsw; /* 00 power up initialization */
1156 /* bit 11 set - Func. 0 INTB, Func. 1 INTA */
1157 /* clear - Func. 0 INTA, Func. 1 INTB */
1158 /* bit 13 set - Load CIS */
1159 /* bit 14 set - BIOS Enable */
1160 /* bit 15 set - Big Endian Mode */
1161 ushort cfg_msw; /* 01 unused */
1162 ushort disc_enable; /* 02 disconnect enable */
1163 ushort wdtr_able; /* 03 Wide DTR able */
1164 ushort sdtr_speed1; /* 04 SDTR Speed TID 0-3 */
1165 ushort start_motor; /* 05 send start up motor */
1166 ushort tagqng_able; /* 06 tag queuing able */
1167 ushort bios_scan; /* 07 BIOS device control */
1168 ushort scam_tolerant; /* 08 no scam */
1170 uchar adapter_scsi_id; /* 09 Host Adapter ID */
1171 uchar bios_boot_delay; /* power up wait */
1173 uchar scsi_reset_delay; /* 10 reset delay */
1174 uchar bios_id_lun; /* first boot device scsi id & lun */
1175 /* high nibble is lun */
1176 /* low nibble is scsi id */
1178 uchar termination_se; /* 11 0 - automatic */
1179 /* 1 - low off / high off */
1180 /* 2 - low off / high on */
1181 /* 3 - low on / high on */
1182 /* There is no low on / high off */
1184 uchar termination_lvd; /* 11 0 - automatic */
1185 /* 1 - low off / high off */
1186 /* 2 - low off / high on */
1187 /* 3 - low on / high on */
1188 /* There is no low on / high off */
1190 ushort bios_ctrl; /* 12 BIOS control bits */
1191 /* bit 0 BIOS don't act as initiator. */
1192 /* bit 1 BIOS > 1 GB support */
1193 /* bit 2 BIOS > 2 Disk Support */
1194 /* bit 3 BIOS don't support removables */
1195 /* bit 4 BIOS support bootable CD */
1196 /* bit 5 BIOS scan enabled */
1197 /* bit 6 BIOS support multiple LUNs */
1198 /* bit 7 BIOS display of message */
1199 /* bit 8 SCAM disabled */
1200 /* bit 9 Reset SCSI bus during init. */
1201 /* bit 10 Basic Integrity Checking disabled */
1202 /* bit 11 No verbose initialization. */
1203 /* bit 12 SCSI parity enabled */
1204 /* bit 13 AIPP (Asyn. Info. Ph. Prot.) dis. */
1207 ushort sdtr_speed2; /* 13 SDTR speed TID 4-7 */
1208 ushort sdtr_speed3; /* 14 SDTR speed TID 8-11 */
1209 uchar max_host_qng; /* 15 maximum host queueing */
1210 uchar max_dvc_qng; /* maximum per device queuing */
1211 ushort dvc_cntl; /* 16 control bit for driver */
1212 ushort sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */
1213 ushort serial_number_word1; /* 18 Board serial number word 1 */
1214 ushort serial_number_word2; /* 19 Board serial number word 2 */
1215 ushort serial_number_word3; /* 20 Board serial number word 3 */
1216 ushort check_sum; /* 21 EEP check sum */
1217 uchar oem_name[16]; /* 22 OEM name */
1218 ushort dvc_err_code; /* 30 last device driver error code */
1219 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
1220 ushort adv_err_addr; /* 32 last uc error address */
1221 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
1222 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
1223 ushort saved_adv_err_addr; /* 35 saved last uc error address */
1224 ushort reserved36; /* 36 reserved */
1225 ushort reserved37; /* 37 reserved */
1226 ushort reserved38; /* 38 reserved */
1227 ushort reserved39; /* 39 reserved */
1228 ushort reserved40; /* 40 reserved */
1229 ushort reserved41; /* 41 reserved */
1230 ushort reserved42; /* 42 reserved */
1231 ushort reserved43; /* 43 reserved */
1232 ushort reserved44; /* 44 reserved */
1233 ushort reserved45; /* 45 reserved */
1234 ushort reserved46; /* 46 reserved */
1235 ushort reserved47; /* 47 reserved */
1236 ushort reserved48; /* 48 reserved */
1237 ushort reserved49; /* 49 reserved */
1238 ushort reserved50; /* 50 reserved */
1239 ushort reserved51; /* 51 reserved */
1240 ushort reserved52; /* 52 reserved */
1241 ushort reserved53; /* 53 reserved */
1242 ushort reserved54; /* 54 reserved */
1243 ushort reserved55; /* 55 reserved */
1244 ushort cisptr_lsw; /* 56 CIS PTR LSW */
1245 ushort cisprt_msw; /* 57 CIS PTR MSW */
1246 ushort subsysvid; /* 58 SubSystem Vendor ID */
1247 ushort subsysid; /* 59 SubSystem ID */
1248 ushort reserved60; /* 60 reserved */
1249 ushort reserved61; /* 61 reserved */
1250 ushort reserved62; /* 62 reserved */
1251 ushort reserved63; /* 63 reserved */
1252 } ADVEEP_38C1600_CONFIG;
1257 #define ASC_EEP_CMD_DONE 0x0200
1260 #define BIOS_CTRL_BIOS 0x0001
1261 #define BIOS_CTRL_EXTENDED_XLAT 0x0002
1262 #define BIOS_CTRL_GT_2_DISK 0x0004
1263 #define BIOS_CTRL_BIOS_REMOVABLE 0x0008
1264 #define BIOS_CTRL_BOOTABLE_CD 0x0010
1265 #define BIOS_CTRL_MULTIPLE_LUN 0x0040
1266 #define BIOS_CTRL_DISPLAY_MSG 0x0080
1267 #define BIOS_CTRL_NO_SCAM 0x0100
1268 #define BIOS_CTRL_RESET_SCSI_BUS 0x0200
1269 #define BIOS_CTRL_INIT_VERBOSE 0x0800
1270 #define BIOS_CTRL_SCSI_PARITY 0x1000
1271 #define BIOS_CTRL_AIPP_DIS 0x2000
1273 #define ADV_3550_MEMSIZE 0x2000 /* 8 KB Internal Memory */
1275 #define ADV_38C0800_MEMSIZE 0x4000 /* 16 KB Internal Memory */
1278 * XXX - Since ASC38C1600 Rev.3 has a local RAM failure issue, there is
1279 * a special 16K Adv Library and Microcode version. After the issue is
1280 * resolved, should restore 32K support.
1282 * #define ADV_38C1600_MEMSIZE 0x8000L * 32 KB Internal Memory *
1284 #define ADV_38C1600_MEMSIZE 0x4000 /* 16 KB Internal Memory */
1287 * Byte I/O register address from base of 'iop_base'.
1289 #define IOPB_INTR_STATUS_REG 0x00
1290 #define IOPB_CHIP_ID_1 0x01
1291 #define IOPB_INTR_ENABLES 0x02
1292 #define IOPB_CHIP_TYPE_REV 0x03
1293 #define IOPB_RES_ADDR_4 0x04
1294 #define IOPB_RES_ADDR_5 0x05
1295 #define IOPB_RAM_DATA 0x06
1296 #define IOPB_RES_ADDR_7 0x07
1297 #define IOPB_FLAG_REG 0x08
1298 #define IOPB_RES_ADDR_9 0x09
1299 #define IOPB_RISC_CSR 0x0A
1300 #define IOPB_RES_ADDR_B 0x0B
1301 #define IOPB_RES_ADDR_C 0x0C
1302 #define IOPB_RES_ADDR_D 0x0D
1303 #define IOPB_SOFT_OVER_WR 0x0E
1304 #define IOPB_RES_ADDR_F 0x0F
1305 #define IOPB_MEM_CFG 0x10
1306 #define IOPB_RES_ADDR_11 0x11
1307 #define IOPB_GPIO_DATA 0x12
1308 #define IOPB_RES_ADDR_13 0x13
1309 #define IOPB_FLASH_PAGE 0x14
1310 #define IOPB_RES_ADDR_15 0x15
1311 #define IOPB_GPIO_CNTL 0x16
1312 #define IOPB_RES_ADDR_17 0x17
1313 #define IOPB_FLASH_DATA 0x18
1314 #define IOPB_RES_ADDR_19 0x19
1315 #define IOPB_RES_ADDR_1A 0x1A
1316 #define IOPB_RES_ADDR_1B 0x1B
1317 #define IOPB_RES_ADDR_1C 0x1C
1318 #define IOPB_RES_ADDR_1D 0x1D
1319 #define IOPB_RES_ADDR_1E 0x1E
1320 #define IOPB_RES_ADDR_1F 0x1F
1321 #define IOPB_DMA_CFG0 0x20
1322 #define IOPB_DMA_CFG1 0x21
1323 #define IOPB_TICKLE 0x22
1324 #define IOPB_DMA_REG_WR 0x23
1325 #define IOPB_SDMA_STATUS 0x24
1326 #define IOPB_SCSI_BYTE_CNT 0x25
1327 #define IOPB_HOST_BYTE_CNT 0x26
1328 #define IOPB_BYTE_LEFT_TO_XFER 0x27
1329 #define IOPB_BYTE_TO_XFER_0 0x28
1330 #define IOPB_BYTE_TO_XFER_1 0x29
1331 #define IOPB_BYTE_TO_XFER_2 0x2A
1332 #define IOPB_BYTE_TO_XFER_3 0x2B
1333 #define IOPB_ACC_GRP 0x2C
1334 #define IOPB_RES_ADDR_2D 0x2D
1335 #define IOPB_DEV_ID 0x2E
1336 #define IOPB_RES_ADDR_2F 0x2F
1337 #define IOPB_SCSI_DATA 0x30
1338 #define IOPB_RES_ADDR_31 0x31
1339 #define IOPB_RES_ADDR_32 0x32
1340 #define IOPB_SCSI_DATA_HSHK 0x33
1341 #define IOPB_SCSI_CTRL 0x34
1342 #define IOPB_RES_ADDR_35 0x35
1343 #define IOPB_RES_ADDR_36 0x36
1344 #define IOPB_RES_ADDR_37 0x37
1345 #define IOPB_RAM_BIST 0x38
1346 #define IOPB_PLL_TEST 0x39
1347 #define IOPB_PCI_INT_CFG 0x3A
1348 #define IOPB_RES_ADDR_3B 0x3B
1349 #define IOPB_RFIFO_CNT 0x3C
1350 #define IOPB_RES_ADDR_3D 0x3D
1351 #define IOPB_RES_ADDR_3E 0x3E
1352 #define IOPB_RES_ADDR_3F 0x3F
1355 * Word I/O register address from base of 'iop_base'.
1357 #define IOPW_CHIP_ID_0 0x00 /* CID0 */
1358 #define IOPW_CTRL_REG 0x02 /* CC */
1359 #define IOPW_RAM_ADDR 0x04 /* LA */
1360 #define IOPW_RAM_DATA 0x06 /* LD */
1361 #define IOPW_RES_ADDR_08 0x08
1362 #define IOPW_RISC_CSR 0x0A /* CSR */
1363 #define IOPW_SCSI_CFG0 0x0C /* CFG0 */
1364 #define IOPW_SCSI_CFG1 0x0E /* CFG1 */
1365 #define IOPW_RES_ADDR_10 0x10
1366 #define IOPW_SEL_MASK 0x12 /* SM */
1367 #define IOPW_RES_ADDR_14 0x14
1368 #define IOPW_FLASH_ADDR 0x16 /* FA */
1369 #define IOPW_RES_ADDR_18 0x18
1370 #define IOPW_EE_CMD 0x1A /* EC */
1371 #define IOPW_EE_DATA 0x1C /* ED */
1372 #define IOPW_SFIFO_CNT 0x1E /* SFC */
1373 #define IOPW_RES_ADDR_20 0x20
1374 #define IOPW_Q_BASE 0x22 /* QB */
1375 #define IOPW_QP 0x24 /* QP */
1376 #define IOPW_IX 0x26 /* IX */
1377 #define IOPW_SP 0x28 /* SP */
1378 #define IOPW_PC 0x2A /* PC */
1379 #define IOPW_RES_ADDR_2C 0x2C
1380 #define IOPW_RES_ADDR_2E 0x2E
1381 #define IOPW_SCSI_DATA 0x30 /* SD */
1382 #define IOPW_SCSI_DATA_HSHK 0x32 /* SDH */
1383 #define IOPW_SCSI_CTRL 0x34 /* SC */
1384 #define IOPW_HSHK_CFG 0x36 /* HCFG */
1385 #define IOPW_SXFR_STATUS 0x36 /* SXS */
1386 #define IOPW_SXFR_CNTL 0x38 /* SXL */
1387 #define IOPW_SXFR_CNTH 0x3A /* SXH */
1388 #define IOPW_RES_ADDR_3C 0x3C
1389 #define IOPW_RFIFO_DATA 0x3E /* RFD */
1392 * Doubleword I/O register address from base of 'iop_base'.
1394 #define IOPDW_RES_ADDR_0 0x00
1395 #define IOPDW_RAM_DATA 0x04
1396 #define IOPDW_RES_ADDR_8 0x08
1397 #define IOPDW_RES_ADDR_C 0x0C
1398 #define IOPDW_RES_ADDR_10 0x10
1399 #define IOPDW_COMMA 0x14
1400 #define IOPDW_COMMB 0x18
1401 #define IOPDW_RES_ADDR_1C 0x1C
1402 #define IOPDW_SDMA_ADDR0 0x20
1403 #define IOPDW_SDMA_ADDR1 0x24
1404 #define IOPDW_SDMA_COUNT 0x28
1405 #define IOPDW_SDMA_ERROR 0x2C
1406 #define IOPDW_RDMA_ADDR0 0x30
1407 #define IOPDW_RDMA_ADDR1 0x34
1408 #define IOPDW_RDMA_COUNT 0x38
1409 #define IOPDW_RDMA_ERROR 0x3C
1411 #define ADV_CHIP_ID_BYTE 0x25
1412 #define ADV_CHIP_ID_WORD 0x04C1
1414 #define ADV_INTR_ENABLE_HOST_INTR 0x01
1415 #define ADV_INTR_ENABLE_SEL_INTR 0x02
1416 #define ADV_INTR_ENABLE_DPR_INTR 0x04
1417 #define ADV_INTR_ENABLE_RTA_INTR 0x08
1418 #define ADV_INTR_ENABLE_RMA_INTR 0x10
1419 #define ADV_INTR_ENABLE_RST_INTR 0x20
1420 #define ADV_INTR_ENABLE_DPE_INTR 0x40
1421 #define ADV_INTR_ENABLE_GLOBAL_INTR 0x80
1423 #define ADV_INTR_STATUS_INTRA 0x01
1424 #define ADV_INTR_STATUS_INTRB 0x02
1425 #define ADV_INTR_STATUS_INTRC 0x04
1427 #define ADV_RISC_CSR_STOP (0x0000)
1428 #define ADV_RISC_TEST_COND (0x2000)
1429 #define ADV_RISC_CSR_RUN (0x4000)
1430 #define ADV_RISC_CSR_SINGLE_STEP (0x8000)
1432 #define ADV_CTRL_REG_HOST_INTR 0x0100
1433 #define ADV_CTRL_REG_SEL_INTR 0x0200
1434 #define ADV_CTRL_REG_DPR_INTR 0x0400
1435 #define ADV_CTRL_REG_RTA_INTR 0x0800
1436 #define ADV_CTRL_REG_RMA_INTR 0x1000
1437 #define ADV_CTRL_REG_RES_BIT14 0x2000
1438 #define ADV_CTRL_REG_DPE_INTR 0x4000
1439 #define ADV_CTRL_REG_POWER_DONE 0x8000
1440 #define ADV_CTRL_REG_ANY_INTR 0xFF00
1442 #define ADV_CTRL_REG_CMD_RESET 0x00C6
1443 #define ADV_CTRL_REG_CMD_WR_IO_REG 0x00C5
1444 #define ADV_CTRL_REG_CMD_RD_IO_REG 0x00C4
1445 #define ADV_CTRL_REG_CMD_WR_PCI_CFG_SPACE 0x00C3
1446 #define ADV_CTRL_REG_CMD_RD_PCI_CFG_SPACE 0x00C2
1448 #define ADV_TICKLE_NOP 0x00
1449 #define ADV_TICKLE_A 0x01
1450 #define ADV_TICKLE_B 0x02
1451 #define ADV_TICKLE_C 0x03
1453 #define AdvIsIntPending(port) \
1454 (AdvReadWordRegister(port, IOPW_CTRL_REG) & ADV_CTRL_REG_HOST_INTR)
1457 * SCSI_CFG0 Register bit definitions
1459 #define TIMER_MODEAB 0xC000 /* Watchdog, Second, and Select. Timer Ctrl. */
1460 #define PARITY_EN 0x2000 /* Enable SCSI Parity Error detection */
1461 #define EVEN_PARITY 0x1000 /* Select Even Parity */
1462 #define WD_LONG 0x0800 /* Watchdog Interval, 1: 57 min, 0: 13 sec */
1463 #define QUEUE_128 0x0400 /* Queue Size, 1: 128 byte, 0: 64 byte */
1464 #define PRIM_MODE 0x0100 /* Primitive SCSI mode */
1465 #define SCAM_EN 0x0080 /* Enable SCAM selection */
1466 #define SEL_TMO_LONG 0x0040 /* Sel/Resel Timeout, 1: 400 ms, 0: 1.6 ms */
1467 #define CFRM_ID 0x0020 /* SCAM id sel. confirm., 1: fast, 0: 6.4 ms */
1468 #define OUR_ID_EN 0x0010 /* Enable OUR_ID bits */
1469 #define OUR_ID 0x000F /* SCSI ID */
1472 * SCSI_CFG1 Register bit definitions
1474 #define BIG_ENDIAN 0x8000 /* Enable Big Endian Mode MIO:15, EEP:15 */
1475 #define TERM_POL 0x2000 /* Terminator Polarity Ctrl. MIO:13, EEP:13 */
1476 #define SLEW_RATE 0x1000 /* SCSI output buffer slew rate */
1477 #define FILTER_SEL 0x0C00 /* Filter Period Selection */
1478 #define FLTR_DISABLE 0x0000 /* Input Filtering Disabled */
1479 #define FLTR_11_TO_20NS 0x0800 /* Input Filtering 11ns to 20ns */
1480 #define FLTR_21_TO_39NS 0x0C00 /* Input Filtering 21ns to 39ns */
1481 #define ACTIVE_DBL 0x0200 /* Disable Active Negation */
1482 #define DIFF_MODE 0x0100 /* SCSI differential Mode (Read-Only) */
1483 #define DIFF_SENSE 0x0080 /* 1: No SE cables, 0: SE cable (Read-Only) */
1484 #define TERM_CTL_SEL 0x0040 /* Enable TERM_CTL_H and TERM_CTL_L */
1485 #define TERM_CTL 0x0030 /* External SCSI Termination Bits */
1486 #define TERM_CTL_H 0x0020 /* Enable External SCSI Upper Termination */
1487 #define TERM_CTL_L 0x0010 /* Enable External SCSI Lower Termination */
1488 #define CABLE_DETECT 0x000F /* External SCSI Cable Connection Status */
1491 * Addendum for ASC-38C0800 Chip
1493 * The ASC-38C1600 Chip uses the same definitions except that the
1494 * bus mode override bits [12:10] have been moved to byte register
1495 * offset 0xE (IOPB_SOFT_OVER_WR) bits [12:10]. The [12:10] bits in
1496 * SCSI_CFG1 are read-only and always available. Bit 14 (DIS_TERM_DRV)
1497 * is not needed. The [12:10] bits in IOPB_SOFT_OVER_WR are write-only.
1498 * Also each ASC-38C1600 function or channel uses only cable bits [5:4]
1499 * and [1:0]. Bits [14], [7:6], [3:2] are unused.
1501 #define DIS_TERM_DRV 0x4000 /* 1: Read c_det[3:0], 0: cannot read */
1502 #define HVD_LVD_SE 0x1C00 /* Device Detect Bits */
1503 #define HVD 0x1000 /* HVD Device Detect */
1504 #define LVD 0x0800 /* LVD Device Detect */
1505 #define SE 0x0400 /* SE Device Detect */
1506 #define TERM_LVD 0x00C0 /* LVD Termination Bits */
1507 #define TERM_LVD_HI 0x0080 /* Enable LVD Upper Termination */
1508 #define TERM_LVD_LO 0x0040 /* Enable LVD Lower Termination */
1509 #define TERM_SE 0x0030 /* SE Termination Bits */
1510 #define TERM_SE_HI 0x0020 /* Enable SE Upper Termination */
1511 #define TERM_SE_LO 0x0010 /* Enable SE Lower Termination */
1512 #define C_DET_LVD 0x000C /* LVD Cable Detect Bits */
1513 #define C_DET3 0x0008 /* Cable Detect for LVD External Wide */
1514 #define C_DET2 0x0004 /* Cable Detect for LVD Internal Wide */
1515 #define C_DET_SE 0x0003 /* SE Cable Detect Bits */
1516 #define C_DET1 0x0002 /* Cable Detect for SE Internal Wide */
1517 #define C_DET0 0x0001 /* Cable Detect for SE Internal Narrow */
1519 #define CABLE_ILLEGAL_A 0x7
1520 /* x 0 0 0 | on on | Illegal (all 3 connectors are used) */
1522 #define CABLE_ILLEGAL_B 0xB
1523 /* 0 x 0 0 | on on | Illegal (all 3 connectors are used) */
1526 * MEM_CFG Register bit definitions
1528 #define BIOS_EN 0x40 /* BIOS Enable MIO:14,EEP:14 */
1529 #define FAST_EE_CLK 0x20 /* Diagnostic Bit */
1530 #define RAM_SZ 0x1C /* Specify size of RAM to RISC */
1531 #define RAM_SZ_2KB 0x00 /* 2 KB */
1532 #define RAM_SZ_4KB 0x04 /* 4 KB */
1533 #define RAM_SZ_8KB 0x08 /* 8 KB */
1534 #define RAM_SZ_16KB 0x0C /* 16 KB */
1535 #define RAM_SZ_32KB 0x10 /* 32 KB */
1536 #define RAM_SZ_64KB 0x14 /* 64 KB */
1539 * DMA_CFG0 Register bit definitions
1541 * This register is only accessible to the host.
1543 #define BC_THRESH_ENB 0x80 /* PCI DMA Start Conditions */
1544 #define FIFO_THRESH 0x70 /* PCI DMA FIFO Threshold */
1545 #define FIFO_THRESH_16B 0x00 /* 16 bytes */
1546 #define FIFO_THRESH_32B 0x20 /* 32 bytes */
1547 #define FIFO_THRESH_48B 0x30 /* 48 bytes */
1548 #define FIFO_THRESH_64B 0x40 /* 64 bytes */
1549 #define FIFO_THRESH_80B 0x50 /* 80 bytes (default) */
1550 #define FIFO_THRESH_96B 0x60 /* 96 bytes */
1551 #define FIFO_THRESH_112B 0x70 /* 112 bytes */
1552 #define START_CTL 0x0C /* DMA start conditions */
1553 #define START_CTL_TH 0x00 /* Wait threshold level (default) */
1554 #define START_CTL_ID 0x04 /* Wait SDMA/SBUS idle */
1555 #define START_CTL_THID 0x08 /* Wait threshold and SDMA/SBUS idle */
1556 #define START_CTL_EMFU 0x0C /* Wait SDMA FIFO empty/full */
1557 #define READ_CMD 0x03 /* Memory Read Method */
1558 #define READ_CMD_MR 0x00 /* Memory Read */
1559 #define READ_CMD_MRL 0x02 /* Memory Read Long */
1560 #define READ_CMD_MRM 0x03 /* Memory Read Multiple (default) */
1563 * ASC-38C0800 RAM BIST Register bit definitions
1565 #define RAM_TEST_MODE 0x80
1566 #define PRE_TEST_MODE 0x40
1567 #define NORMAL_MODE 0x00
1568 #define RAM_TEST_DONE 0x10
1569 #define RAM_TEST_STATUS 0x0F
1570 #define RAM_TEST_HOST_ERROR 0x08
1571 #define RAM_TEST_INTRAM_ERROR 0x04
1572 #define RAM_TEST_RISC_ERROR 0x02
1573 #define RAM_TEST_SCSI_ERROR 0x01
1574 #define RAM_TEST_SUCCESS 0x00
1575 #define PRE_TEST_VALUE 0x05
1576 #define NORMAL_VALUE 0x00
1579 * ASC38C1600 Definitions
1581 * IOPB_PCI_INT_CFG Bit Field Definitions
1584 #define INTAB_LD 0x80 /* Value loaded from EEPROM Bit 11. */
1587 * Bit 1 can be set to change the interrupt for the Function to operate in
1588 * Totem Pole mode. By default Bit 1 is 0 and the interrupt operates in
1589 * Open Drain mode. Both functions of the ASC38C1600 must be set to the same
1590 * mode, otherwise the operating mode is undefined.
1592 #define TOTEMPOLE 0x02
1595 * Bit 0 can be used to change the Int Pin for the Function. The value is
1596 * 0 by default for both Functions with Function 0 using INT A and Function
1597 * B using INT B. For Function 0 if set, INT B is used. For Function 1 if set,
1600 * EEPROM Word 0 Bit 11 for each Function may change the initial Int Pin
1601 * value specified in the PCI Configuration Space.
1606 * Adv Library Status Definitions
1610 #define ADV_SUCCESS 1
1612 #define ADV_ERROR (-1)
1615 * ADV_DVC_VAR 'warn_code' values
1617 #define ASC_WARN_BUSRESET_ERROR 0x0001 /* SCSI Bus Reset error */
1618 #define ASC_WARN_EEPROM_CHKSUM 0x0002 /* EEP check sum error */
1619 #define ASC_WARN_EEPROM_TERMINATION 0x0004 /* EEP termination bad field */
1620 #define ASC_WARN_ERROR 0xFFFF /* ADV_ERROR return */
1622 #define ADV_MAX_TID 15 /* max. target identifier */
1623 #define ADV_MAX_LUN 7 /* max. logical unit number */
1626 * Fixed locations of microcode operating variables.
1628 #define ASC_MC_CODE_BEGIN_ADDR 0x0028 /* microcode start address */
1629 #define ASC_MC_CODE_END_ADDR 0x002A /* microcode end address */
1630 #define ASC_MC_CODE_CHK_SUM 0x002C /* microcode code checksum */
1631 #define ASC_MC_VERSION_DATE 0x0038 /* microcode version */
1632 #define ASC_MC_VERSION_NUM 0x003A /* microcode number */
1633 #define ASC_MC_BIOSMEM 0x0040 /* BIOS RISC Memory Start */
1634 #define ASC_MC_BIOSLEN 0x0050 /* BIOS RISC Memory Length */
1635 #define ASC_MC_BIOS_SIGNATURE 0x0058 /* BIOS Signature 0x55AA */
1636 #define ASC_MC_BIOS_VERSION 0x005A /* BIOS Version (2 bytes) */
1637 #define ASC_MC_SDTR_SPEED1 0x0090 /* SDTR Speed for TID 0-3 */
1638 #define ASC_MC_SDTR_SPEED2 0x0092 /* SDTR Speed for TID 4-7 */
1639 #define ASC_MC_SDTR_SPEED3 0x0094 /* SDTR Speed for TID 8-11 */
1640 #define ASC_MC_SDTR_SPEED4 0x0096 /* SDTR Speed for TID 12-15 */
1641 #define ASC_MC_CHIP_TYPE 0x009A
1642 #define ASC_MC_INTRB_CODE 0x009B
1643 #define ASC_MC_WDTR_ABLE 0x009C
1644 #define ASC_MC_SDTR_ABLE 0x009E
1645 #define ASC_MC_TAGQNG_ABLE 0x00A0
1646 #define ASC_MC_DISC_ENABLE 0x00A2
1647 #define ASC_MC_IDLE_CMD_STATUS 0x00A4
1648 #define ASC_MC_IDLE_CMD 0x00A6
1649 #define ASC_MC_IDLE_CMD_PARAMETER 0x00A8
1650 #define ASC_MC_DEFAULT_SCSI_CFG0 0x00AC
1651 #define ASC_MC_DEFAULT_SCSI_CFG1 0x00AE
1652 #define ASC_MC_DEFAULT_MEM_CFG 0x00B0
1653 #define ASC_MC_DEFAULT_SEL_MASK 0x00B2
1654 #define ASC_MC_SDTR_DONE 0x00B6
1655 #define ASC_MC_NUMBER_OF_QUEUED_CMD 0x00C0
1656 #define ASC_MC_NUMBER_OF_MAX_CMD 0x00D0
1657 #define ASC_MC_DEVICE_HSHK_CFG_TABLE 0x0100
1658 #define ASC_MC_CONTROL_FLAG 0x0122 /* Microcode control flag. */
1659 #define ASC_MC_WDTR_DONE 0x0124
1660 #define ASC_MC_CAM_MODE_MASK 0x015E /* CAM mode TID bitmask. */
1661 #define ASC_MC_ICQ 0x0160
1662 #define ASC_MC_IRQ 0x0164
1663 #define ASC_MC_PPR_ABLE 0x017A
1666 * BIOS LRAM variable absolute offsets.
1668 #define BIOS_CODESEG 0x54
1669 #define BIOS_CODELEN 0x56
1670 #define BIOS_SIGNATURE 0x58
1671 #define BIOS_VERSION 0x5A
1674 * Microcode Control Flags
1676 * Flags set by the Adv Library in RISC variable 'control_flag' (0x122)
1677 * and handled by the microcode.
1679 #define CONTROL_FLAG_IGNORE_PERR 0x0001 /* Ignore DMA Parity Errors */
1680 #define CONTROL_FLAG_ENABLE_AIPP 0x0002 /* Enabled AIPP checking. */
1683 * ASC_MC_DEVICE_HSHK_CFG_TABLE microcode table or HSHK_CFG register format
1685 #define HSHK_CFG_WIDE_XFR 0x8000
1686 #define HSHK_CFG_RATE 0x0F00
1687 #define HSHK_CFG_OFFSET 0x001F
1689 #define ASC_DEF_MAX_HOST_QNG 0xFD /* Max. number of host commands (253) */
1690 #define ASC_DEF_MIN_HOST_QNG 0x10 /* Min. number of host commands (16) */
1691 #define ASC_DEF_MAX_DVC_QNG 0x3F /* Max. number commands per device (63) */
1692 #define ASC_DEF_MIN_DVC_QNG 0x04 /* Min. number commands per device (4) */
1694 #define ASC_QC_DATA_CHECK 0x01 /* Require ASC_QC_DATA_OUT set or clear. */
1695 #define ASC_QC_DATA_OUT 0x02 /* Data out DMA transfer. */
1696 #define ASC_QC_START_MOTOR 0x04 /* Send auto-start motor before request. */
1697 #define ASC_QC_NO_OVERRUN 0x08 /* Don't report overrun. */
1698 #define ASC_QC_FREEZE_TIDQ 0x10 /* Freeze TID queue after request. XXX TBD */
1700 #define ASC_QSC_NO_DISC 0x01 /* Don't allow disconnect for request. */
1701 #define ASC_QSC_NO_TAGMSG 0x02 /* Don't allow tag queuing for request. */
1702 #define ASC_QSC_NO_SYNC 0x04 /* Don't use Synch. transfer on request. */
1703 #define ASC_QSC_NO_WIDE 0x08 /* Don't use Wide transfer on request. */
1704 #define ASC_QSC_REDO_DTR 0x10 /* Renegotiate WDTR/SDTR before request. */
1706 * Note: If a Tag Message is to be sent and neither ASC_QSC_HEAD_TAG or
1707 * ASC_QSC_ORDERED_TAG is set, then a Simple Tag Message (0x20) is used.
1709 #define ASC_QSC_HEAD_TAG 0x40 /* Use Head Tag Message (0x21). */
1710 #define ASC_QSC_ORDERED_TAG 0x80 /* Use Ordered Tag Message (0x22). */
1713 * All fields here are accessed by the board microcode and need to be
1716 typedef struct adv_carr_t {
1717 __le32 carr_va; /* Carrier Virtual Address */
1718 __le32 carr_pa; /* Carrier Physical Address */
1719 __le32 areq_vpa; /* ASC_SCSI_REQ_Q Virtual or Physical Address */
1721 * next_vpa [31:4] Carrier Virtual or Physical Next Pointer
1723 * next_vpa [3:1] Reserved Bits
1724 * next_vpa [0] Done Flag set in Response Queue.
1730 * Mask used to eliminate low 4 bits of carrier 'next_vpa' field.
1732 #define ASC_NEXT_VPA_MASK 0xFFFFFFF0
1734 #define ASC_RQ_DONE 0x00000001
1735 #define ASC_RQ_GOOD 0x00000002
1736 #define ASC_CQ_STOPPER 0x00000000
1738 #define ASC_GET_CARRP(carrp) ((carrp) & ASC_NEXT_VPA_MASK)
1741 * Each carrier is 64 bytes, and we need three additional
1742 * carrier for icq, irq, and the termination carrier.
1744 #define ADV_CARRIER_COUNT (ASC_DEF_MAX_HOST_QNG + 3)
1746 #define ADV_CARRIER_BUFSIZE \
1747 (ADV_CARRIER_COUNT * sizeof(ADV_CARR_T))
1750 * ASC_SCSI_REQ_Q 'a_flag' definitions
1752 * The Adv Library should limit use to the lower nibble (4 bits) of
1753 * a_flag. Drivers are free to use the upper nibble (4 bits) of a_flag.
1755 #define ADV_POLL_REQUEST 0x01 /* poll for request completion */
1756 #define ADV_SCSIQ_DONE 0x02 /* request done */
1757 #define ADV_DONT_RETRY 0x08 /* don't do retry */
1759 #define ADV_CHIP_ASC3550 0x01 /* Ultra-Wide IC */
1760 #define ADV_CHIP_ASC38C0800 0x02 /* Ultra2-Wide/LVD IC */
1761 #define ADV_CHIP_ASC38C1600 0x03 /* Ultra3-Wide/LVD2 IC */
1764 * Adapter temporary configuration structure
1766 * This structure can be discarded after initialization. Don't add
1767 * fields here needed after initialization.
1769 * Field naming convention:
1771 * *_enable indicates the field enables or disables a feature. The
1772 * value of the field is never reset.
1774 typedef struct adv_dvc_cfg {
1775 ushort disc_enable; /* enable disconnection */
1776 uchar chip_version; /* chip version */
1777 uchar termination; /* Term. Ctrl. bits 6-5 of SCSI_CFG1 register */
1778 ushort control_flag; /* Microcode Control Flag */
1779 ushort mcode_date; /* Microcode date */
1780 ushort mcode_version; /* Microcode version */
1781 ushort serial1; /* EEPROM serial number word 1 */
1782 ushort serial2; /* EEPROM serial number word 2 */
1783 ushort serial3; /* EEPROM serial number word 3 */
1787 struct adv_scsi_req_q;
1789 typedef struct adv_sg_block {
1793 uchar sg_cnt; /* Valid entries in block. */
1794 __le32 sg_ptr; /* Pointer to next sg block. */
1796 __le32 sg_addr; /* SG element address. */
1797 __le32 sg_count; /* SG element count. */
1798 } sg_list[NO_OF_SG_PER_BLOCK];
1802 * ADV_SCSI_REQ_Q - microcode request structure
1804 * All fields in this structure up to byte 60 are used by the microcode.
1805 * The microcode makes assumptions about the size and ordering of fields
1806 * in this structure. Do not change the structure definition here without
1807 * coordinating the change with the microcode.
1809 * All fields accessed by microcode must be maintained in little_endian
1812 typedef struct adv_scsi_req_q {
1813 uchar cntl; /* Ucode flags and state (ASC_MC_QC_*). */
1815 uchar target_id; /* Device target identifier. */
1816 uchar target_lun; /* Device target logical unit number. */
1817 __le32 data_addr; /* Data buffer physical address. */
1818 __le32 data_cnt; /* Data count. Ucode sets to residual. */
1823 uchar cdb_len; /* SCSI CDB length. Must <= 16 bytes. */
1825 uchar done_status; /* Completion status. */
1826 uchar scsi_status; /* SCSI status byte. */
1827 uchar host_status; /* Ucode host status. */
1828 uchar sg_working_ix;
1829 uchar cdb[12]; /* SCSI CDB bytes 0-11. */
1830 __le32 sg_real_addr; /* SG list physical address. */
1832 uchar cdb16[4]; /* SCSI CDB bytes 12-15. */
1836 * End of microcode structure - 60 bytes. The rest of the structure
1837 * is used by the Adv Library and ignored by the microcode.
1841 uchar pad[3]; /* Pad out to a word boundary. */
1842 ADV_SG_BLOCK *sg_list_ptr; /* SG list virtual address. */
1846 * The following two structures are used to process Wide Board requests.
1848 * The ADV_SCSI_REQ_Q structure in adv_req_t is passed to the Adv Library
1849 * and microcode with the ADV_SCSI_REQ_Q field 'srb_tag' set to the
1850 * SCSI request tag. The adv_req_t structure 'cmndp' field in turn points
1851 * to the Mid-Level SCSI request structure.
1853 * Zero or more ADV_SG_BLOCK are used with each ADV_SCSI_REQ_Q. Each
1854 * ADV_SG_BLOCK structure holds 15 scatter-gather elements. Under Linux
1855 * up to 255 scatter-gather elements may be used per request or
1858 * Both structures must be 32 byte aligned.
1860 typedef struct adv_sgblk {
1861 ADV_SG_BLOCK sg_block; /* Sgblock structure. */
1862 dma_addr_t sg_addr; /* Physical address */
1863 struct adv_sgblk *next_sgblkp; /* Next scatter-gather structure. */
1866 typedef struct adv_req {
1867 ADV_SCSI_REQ_Q scsi_req_q; /* Adv Library request structure. */
1868 uchar align[24]; /* Request structure padding. */
1869 struct scsi_cmnd *cmndp; /* Mid-Level SCSI command pointer. */
1870 dma_addr_t req_addr;
1871 adv_sgblk_t *sgblkp; /* Adv Library scatter-gather pointer. */
1872 } adv_req_t __aligned(32);
1875 * Adapter operation variable structure.
1877 * One structure is required per host adapter.
1879 * Field naming convention:
1881 * *_able indicates both whether a feature should be enabled or disabled
1882 * and whether a device isi capable of the feature. At initialization
1883 * this field may be set, but later if a device is found to be incapable
1884 * of the feature, the field is cleared.
1886 typedef struct adv_dvc_var {
1887 AdvPortAddr iop_base; /* I/O port address */
1888 ushort err_code; /* fatal error code */
1889 ushort bios_ctrl; /* BIOS control word, EEPROM word 12 */
1890 ushort wdtr_able; /* try WDTR for a device */
1891 ushort sdtr_able; /* try SDTR for a device */
1892 ushort ultra_able; /* try SDTR Ultra speed for a device */
1893 ushort sdtr_speed1; /* EEPROM SDTR Speed for TID 0-3 */
1894 ushort sdtr_speed2; /* EEPROM SDTR Speed for TID 4-7 */
1895 ushort sdtr_speed3; /* EEPROM SDTR Speed for TID 8-11 */
1896 ushort sdtr_speed4; /* EEPROM SDTR Speed for TID 12-15 */
1897 ushort tagqng_able; /* try tagged queuing with a device */
1898 ushort ppr_able; /* PPR message capable per TID bitmask. */
1899 uchar max_dvc_qng; /* maximum number of tagged commands per device */
1900 ushort start_motor; /* start motor command allowed */
1901 uchar scsi_reset_wait; /* delay in seconds after scsi bus reset */
1902 uchar chip_no; /* should be assigned by caller */
1903 uchar max_host_qng; /* maximum number of Q'ed command allowed */
1904 ushort no_scam; /* scam_tolerant of EEPROM */
1905 struct asc_board *drv_ptr; /* driver pointer to private structure */
1906 uchar chip_scsi_id; /* chip SCSI target ID */
1908 uchar bist_err_code;
1909 ADV_CARR_T *carrier;
1910 ADV_CARR_T *carr_freelist; /* Carrier free list. */
1911 dma_addr_t carrier_addr;
1912 ADV_CARR_T *icq_sp; /* Initiator command queue stopper pointer. */
1913 ADV_CARR_T *irq_sp; /* Initiator response queue stopper pointer. */
1914 ushort carr_pending_cnt; /* Count of pending carriers. */
1916 * Note: The following fields will not be used after initialization. The
1917 * driver may discard the buffer after initialization is done.
1919 ADV_DVC_CFG *cfg; /* temporary configuration structure */
1923 * Microcode idle loop commands
1925 #define IDLE_CMD_COMPLETED 0
1926 #define IDLE_CMD_STOP_CHIP 0x0001
1927 #define IDLE_CMD_STOP_CHIP_SEND_INT 0x0002
1928 #define IDLE_CMD_SEND_INT 0x0004
1929 #define IDLE_CMD_ABORT 0x0008
1930 #define IDLE_CMD_DEVICE_RESET 0x0010
1931 #define IDLE_CMD_SCSI_RESET_START 0x0020 /* Assert SCSI Bus Reset */
1932 #define IDLE_CMD_SCSI_RESET_END 0x0040 /* Deassert SCSI Bus Reset */
1933 #define IDLE_CMD_SCSIREQ 0x0080
1935 #define IDLE_CMD_STATUS_SUCCESS 0x0001
1936 #define IDLE_CMD_STATUS_FAILURE 0x0002
1939 * AdvSendIdleCmd() flag definitions.
1941 #define ADV_NOWAIT 0x01
1944 * Wait loop time out values.
1946 #define SCSI_WAIT_100_MSEC 100UL /* 100 milliseconds */
1947 #define SCSI_US_PER_MSEC 1000 /* microseconds per millisecond */
1948 #define SCSI_MAX_RETRY 10 /* retry count */
1950 #define ADV_ASYNC_RDMA_FAILURE 0x01 /* Fatal RDMA failure. */
1951 #define ADV_ASYNC_SCSI_BUS_RESET_DET 0x02 /* Detected SCSI Bus Reset. */
1952 #define ADV_ASYNC_CARRIER_READY_FAILURE 0x03 /* Carrier Ready failure. */
1953 #define ADV_RDMA_IN_CARR_AND_Q_INVALID 0x04 /* RDMAed-in data invalid. */
1955 #define ADV_HOST_SCSI_BUS_RESET 0x80 /* Host Initiated SCSI Bus Reset. */
1957 /* Read byte from a register. */
1958 #define AdvReadByteRegister(iop_base, reg_off) \
1959 (ADV_MEM_READB((iop_base) + (reg_off)))
1961 /* Write byte to a register. */
1962 #define AdvWriteByteRegister(iop_base, reg_off, byte) \
1963 (ADV_MEM_WRITEB((iop_base) + (reg_off), (byte)))
1965 /* Read word (2 bytes) from a register. */
1966 #define AdvReadWordRegister(iop_base, reg_off) \
1967 (ADV_MEM_READW((iop_base) + (reg_off)))
1969 /* Write word (2 bytes) to a register. */
1970 #define AdvWriteWordRegister(iop_base, reg_off, word) \
1971 (ADV_MEM_WRITEW((iop_base) + (reg_off), (word)))
1973 /* Write dword (4 bytes) to a register. */
1974 #define AdvWriteDWordRegister(iop_base, reg_off, dword) \
1975 (ADV_MEM_WRITEDW((iop_base) + (reg_off), (dword)))
1977 /* Read byte from LRAM. */
1978 #define AdvReadByteLram(iop_base, addr, byte) \
1980 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
1981 (byte) = ADV_MEM_READB((iop_base) + IOPB_RAM_DATA); \
1984 /* Write byte to LRAM. */
1985 #define AdvWriteByteLram(iop_base, addr, byte) \
1986 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
1987 ADV_MEM_WRITEB((iop_base) + IOPB_RAM_DATA, (byte)))
1989 /* Read word (2 bytes) from LRAM. */
1990 #define AdvReadWordLram(iop_base, addr, word) \
1992 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
1993 (word) = (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA)); \
1996 /* Write word (2 bytes) to LRAM. */
1997 #define AdvWriteWordLram(iop_base, addr, word) \
1998 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
1999 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
2001 /* Write little-endian double word (4 bytes) to LRAM */
2002 /* Because of unspecified C language ordering don't use auto-increment. */
2003 #define AdvWriteDWordLramNoSwap(iop_base, addr, dword) \
2004 ((ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
2005 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
2006 cpu_to_le16((ushort) ((dword) & 0xFFFF)))), \
2007 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr) + 2), \
2008 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
2009 cpu_to_le16((ushort) ((dword >> 16) & 0xFFFF)))))
2011 /* Read word (2 bytes) from LRAM assuming that the address is already set. */
2012 #define AdvReadWordAutoIncLram(iop_base) \
2013 (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA))
2015 /* Write word (2 bytes) to LRAM assuming that the address is already set. */
2016 #define AdvWriteWordAutoIncLram(iop_base, word) \
2017 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
2020 * Define macro to check for Condor signature.
2022 * Evaluate to ADV_TRUE if a Condor chip is found the specified port
2023 * address 'iop_base'. Otherwise evalue to ADV_FALSE.
2025 #define AdvFindSignature(iop_base) \
2026 (((AdvReadByteRegister((iop_base), IOPB_CHIP_ID_1) == \
2027 ADV_CHIP_ID_BYTE) && \
2028 (AdvReadWordRegister((iop_base), IOPW_CHIP_ID_0) == \
2029 ADV_CHIP_ID_WORD)) ? ADV_TRUE : ADV_FALSE)
2032 * Define macro to Return the version number of the chip at 'iop_base'.
2034 * The second parameter 'bus_type' is currently unused.
2036 #define AdvGetChipVersion(iop_base, bus_type) \
2037 AdvReadByteRegister((iop_base), IOPB_CHIP_TYPE_REV)
2040 * Abort an SRB in the chip's RISC Memory. The 'srb_tag' argument must
2041 * match the ASC_SCSI_REQ_Q 'srb_tag' field.
2043 * If the request has not yet been sent to the device it will simply be
2044 * aborted from RISC memory. If the request is disconnected it will be
2045 * aborted on reselection by sending an Abort Message to the target ID.
2048 * ADV_TRUE(1) - Queue was successfully aborted.
2049 * ADV_FALSE(0) - Queue was not found on the active queue list.
2051 #define AdvAbortQueue(asc_dvc, srb_tag) \
2052 AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_ABORT, \
2053 (ADV_DCNT) (srb_tag))
2056 * Send a Bus Device Reset Message to the specified target ID.
2058 * All outstanding commands will be purged if sending the
2059 * Bus Device Reset Message is successful.
2062 * ADV_TRUE(1) - All requests on the target are purged.
2063 * ADV_FALSE(0) - Couldn't issue Bus Device Reset Message; Requests
2066 #define AdvResetDevice(asc_dvc, target_id) \
2067 AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_DEVICE_RESET, \
2068 (ADV_DCNT) (target_id))
2071 * SCSI Wide Type definition.
2073 #define ADV_SCSI_BIT_ID_TYPE ushort
2076 * AdvInitScsiTarget() 'cntl_flag' options.
2078 #define ADV_SCAN_LUN 0x01
2079 #define ADV_CAPINFO_NOLUN 0x02
2082 * Convert target id to target id bit mask.
2084 #define ADV_TID_TO_TIDMASK(tid) (0x01 << ((tid) & ADV_MAX_TID))
2087 * ASC_SCSI_REQ_Q 'done_status' and 'host_status' return values.
2090 #define QD_NO_STATUS 0x00 /* Request not completed yet. */
2091 #define QD_NO_ERROR 0x01
2092 #define QD_ABORTED_BY_HOST 0x02
2093 #define QD_WITH_ERROR 0x04
2095 #define QHSTA_NO_ERROR 0x00
2096 #define QHSTA_M_SEL_TIMEOUT 0x11
2097 #define QHSTA_M_DATA_OVER_RUN 0x12
2098 #define QHSTA_M_UNEXPECTED_BUS_FREE 0x13
2099 #define QHSTA_M_QUEUE_ABORTED 0x15
2100 #define QHSTA_M_SXFR_SDMA_ERR 0x16 /* SXFR_STATUS SCSI DMA Error */
2101 #define QHSTA_M_SXFR_SXFR_PERR 0x17 /* SXFR_STATUS SCSI Bus Parity Error */
2102 #define QHSTA_M_RDMA_PERR 0x18 /* RISC PCI DMA parity error */
2103 #define QHSTA_M_SXFR_OFF_UFLW 0x19 /* SXFR_STATUS Offset Underflow */
2104 #define QHSTA_M_SXFR_OFF_OFLW 0x20 /* SXFR_STATUS Offset Overflow */
2105 #define QHSTA_M_SXFR_WD_TMO 0x21 /* SXFR_STATUS Watchdog Timeout */
2106 #define QHSTA_M_SXFR_DESELECTED 0x22 /* SXFR_STATUS Deselected */
2107 /* Note: QHSTA_M_SXFR_XFR_OFLW is identical to QHSTA_M_DATA_OVER_RUN. */
2108 #define QHSTA_M_SXFR_XFR_OFLW 0x12 /* SXFR_STATUS Transfer Overflow */
2109 #define QHSTA_M_SXFR_XFR_PH_ERR 0x24 /* SXFR_STATUS Transfer Phase Error */
2110 #define QHSTA_M_SXFR_UNKNOWN_ERROR 0x25 /* SXFR_STATUS Unknown Error */
2111 #define QHSTA_M_SCSI_BUS_RESET 0x30 /* Request aborted from SBR */
2112 #define QHSTA_M_SCSI_BUS_RESET_UNSOL 0x31 /* Request aborted from unsol. SBR */
2113 #define QHSTA_M_BUS_DEVICE_RESET 0x32 /* Request aborted from BDR */
2114 #define QHSTA_M_DIRECTION_ERR 0x35 /* Data Phase mismatch */
2115 #define QHSTA_M_DIRECTION_ERR_HUNG 0x36 /* Data Phase mismatch and bus hang */
2116 #define QHSTA_M_WTM_TIMEOUT 0x41
2117 #define QHSTA_M_BAD_CMPL_STATUS_IN 0x42
2118 #define QHSTA_M_NO_AUTO_REQ_SENSE 0x43
2119 #define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
2120 #define QHSTA_M_INVALID_DEVICE 0x45 /* Bad target ID */
2121 #define QHSTA_M_FROZEN_TIDQ 0x46 /* TID Queue frozen. */
2122 #define QHSTA_M_SGBACKUP_ERROR 0x47 /* Scatter-Gather backup error */
2124 /* Return the address that is aligned at the next doubleword >= to 'addr'. */
2125 #define ADV_32BALIGN(addr) (((ulong) (addr) + 0x1F) & ~0x1F)
2128 * Total contiguous memory needed for driver SG blocks.
2130 * ADV_MAX_SG_LIST must be defined by a driver. It is the maximum
2131 * number of scatter-gather elements the driver supports in a
2135 #define ADV_SG_LIST_MAX_BYTE_SIZE \
2136 (sizeof(ADV_SG_BLOCK) * \
2137 ((ADV_MAX_SG_LIST + (NO_OF_SG_PER_BLOCK - 1))/NO_OF_SG_PER_BLOCK))
2139 /* struct asc_board flags */
2140 #define ASC_IS_WIDE_BOARD 0x04 /* AdvanSys Wide Board */
2142 #define ASC_NARROW_BOARD(boardp) (((boardp)->flags & ASC_IS_WIDE_BOARD) == 0)
2144 #define NO_ISA_DMA 0xff /* No ISA DMA Channel Used */
2146 #define ASC_INFO_SIZE 128 /* advansys_info() line size */
2148 /* Asc Library return codes */
2151 #define ASC_NOERROR 1
2153 #define ASC_ERROR (-1)
2155 /* struct scsi_cmnd function return codes */
2156 #define STATUS_BYTE(byte) (byte)
2157 #define MSG_BYTE(byte) ((byte) << 8)
2158 #define HOST_BYTE(byte) ((byte) << 16)
2159 #define DRIVER_BYTE(byte) ((byte) << 24)
2161 #define ASC_STATS(shost, counter) ASC_STATS_ADD(shost, counter, 1)
2162 #ifndef ADVANSYS_STATS
2163 #define ASC_STATS_ADD(shost, counter, count)
2164 #else /* ADVANSYS_STATS */
2165 #define ASC_STATS_ADD(shost, counter, count) \
2166 (((struct asc_board *) shost_priv(shost))->asc_stats.counter += (count))
2167 #endif /* ADVANSYS_STATS */
2169 /* If the result wraps when calculating tenths, return 0. */
2170 #define ASC_TENTHS(num, den) \
2171 (((10 * ((num)/(den))) > (((num) * 10)/(den))) ? \
2172 0 : ((((num) * 10)/(den)) - (10 * ((num)/(den)))))
2175 * Display a message to the console.
2177 #define ASC_PRINT(s) \
2179 printk("advansys: "); \
2183 #define ASC_PRINT1(s, a1) \
2185 printk("advansys: "); \
2186 printk((s), (a1)); \
2189 #define ASC_PRINT2(s, a1, a2) \
2191 printk("advansys: "); \
2192 printk((s), (a1), (a2)); \
2195 #define ASC_PRINT3(s, a1, a2, a3) \
2197 printk("advansys: "); \
2198 printk((s), (a1), (a2), (a3)); \
2201 #define ASC_PRINT4(s, a1, a2, a3, a4) \
2203 printk("advansys: "); \
2204 printk((s), (a1), (a2), (a3), (a4)); \
2207 #ifndef ADVANSYS_DEBUG
2209 #define ASC_DBG(lvl, s...)
2210 #define ASC_DBG_PRT_SCSI_HOST(lvl, s)
2211 #define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp)
2212 #define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
2213 #define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone)
2214 #define ADV_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
2215 #define ASC_DBG_PRT_HEX(lvl, name, start, length)
2216 #define ASC_DBG_PRT_CDB(lvl, cdb, len)
2217 #define ASC_DBG_PRT_SENSE(lvl, sense, len)
2218 #define ASC_DBG_PRT_INQUIRY(lvl, inq, len)
2220 #else /* ADVANSYS_DEBUG */
2223 * Debugging Message Levels:
2225 * 1: High-Level Tracing
2226 * 2-N: Verbose Tracing
2229 #define ASC_DBG(lvl, format, arg...) { \
2230 if (asc_dbglvl >= (lvl)) \
2231 printk(KERN_DEBUG "%s: %s: " format, DRV_NAME, \
2232 __func__ , ## arg); \
2235 #define ASC_DBG_PRT_SCSI_HOST(lvl, s) \
2237 if (asc_dbglvl >= (lvl)) { \
2238 asc_prt_scsi_host(s); \
2242 #define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp) \
2244 if (asc_dbglvl >= (lvl)) { \
2245 asc_prt_asc_scsi_q(scsiqp); \
2249 #define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone) \
2251 if (asc_dbglvl >= (lvl)) { \
2252 asc_prt_asc_qdone_info(qdone); \
2256 #define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp) \
2258 if (asc_dbglvl >= (lvl)) { \
2259 asc_prt_adv_scsi_req_q(scsiqp); \
2263 #define ASC_DBG_PRT_HEX(lvl, name, start, length) \
2265 if (asc_dbglvl >= (lvl)) { \
2266 asc_prt_hex((name), (start), (length)); \
2270 #define ASC_DBG_PRT_CDB(lvl, cdb, len) \
2271 ASC_DBG_PRT_HEX((lvl), "CDB", (uchar *) (cdb), (len));
2273 #define ASC_DBG_PRT_SENSE(lvl, sense, len) \
2274 ASC_DBG_PRT_HEX((lvl), "SENSE", (uchar *) (sense), (len));
2276 #define ASC_DBG_PRT_INQUIRY(lvl, inq, len) \
2277 ASC_DBG_PRT_HEX((lvl), "INQUIRY", (uchar *) (inq), (len));
2278 #endif /* ADVANSYS_DEBUG */
2280 #ifdef ADVANSYS_STATS
2282 /* Per board statistics structure */
2284 /* Driver Entrypoint Statistics */
2285 unsigned int queuecommand; /* # calls to advansys_queuecommand() */
2286 unsigned int reset; /* # calls to advansys_eh_bus_reset() */
2287 unsigned int biosparam; /* # calls to advansys_biosparam() */
2288 unsigned int interrupt; /* # advansys_interrupt() calls */
2289 unsigned int callback; /* # calls to asc/adv_isr_callback() */
2290 unsigned int done; /* # calls to request's scsi_done function */
2291 unsigned int build_error; /* # asc/adv_build_req() ASC_ERROR returns. */
2292 unsigned int adv_build_noreq; /* # adv_build_req() adv_req_t alloc. fail. */
2293 unsigned int adv_build_nosg; /* # adv_build_req() adv_sgblk_t alloc. fail. */
2294 /* AscExeScsiQueue()/AdvExeScsiQueue() Statistics */
2295 unsigned int exe_noerror; /* # ASC_NOERROR returns. */
2296 unsigned int exe_busy; /* # ASC_BUSY returns. */
2297 unsigned int exe_error; /* # ASC_ERROR returns. */
2298 unsigned int exe_unknown; /* # unknown returns. */
2299 /* Data Transfer Statistics */
2300 unsigned int xfer_cnt; /* # I/O requests received */
2301 unsigned int xfer_elem; /* # scatter-gather elements */
2302 unsigned int xfer_sect; /* # 512-byte blocks */
2304 #endif /* ADVANSYS_STATS */
2307 * Structure allocated for each board.
2309 * This structure is allocated by scsi_host_alloc() at the end
2310 * of the 'Scsi_Host' structure starting at the 'hostdata'
2311 * field. It is guaranteed to be allocated from DMA-able memory.
2315 struct Scsi_Host *shost;
2316 uint flags; /* Board flags */
2319 ASC_DVC_VAR asc_dvc_var; /* Narrow board */
2320 ADV_DVC_VAR adv_dvc_var; /* Wide board */
2323 ASC_DVC_CFG asc_dvc_cfg; /* Narrow board */
2324 ADV_DVC_CFG adv_dvc_cfg; /* Wide board */
2326 ushort asc_n_io_port; /* Number I/O ports. */
2327 ADV_SCSI_BIT_ID_TYPE init_tidmask; /* Target init./valid mask */
2328 ushort reqcnt[ADV_MAX_TID + 1]; /* Starvation request count */
2329 ADV_SCSI_BIT_ID_TYPE queue_full; /* Queue full mask */
2330 ushort queue_full_cnt[ADV_MAX_TID + 1]; /* Queue full count */
2332 ASCEEP_CONFIG asc_eep; /* Narrow EEPROM config. */
2333 ADVEEP_3550_CONFIG adv_3550_eep; /* 3550 EEPROM config. */
2334 ADVEEP_38C0800_CONFIG adv_38C0800_eep; /* 38C0800 EEPROM config. */
2335 ADVEEP_38C1600_CONFIG adv_38C1600_eep; /* 38C1600 EEPROM config. */
2337 /* /proc/scsi/advansys/[0...] */
2338 #ifdef ADVANSYS_STATS
2339 struct asc_stats asc_stats; /* Board statistics */
2340 #endif /* ADVANSYS_STATS */
2342 * The following fields are used only for Narrow Boards.
2344 uchar sdtr_data[ASC_MAX_TID + 1]; /* SDTR information */
2346 * The following fields are used only for Wide Boards.
2348 void __iomem *ioremap_addr; /* I/O Memory remap address. */
2349 ushort ioport; /* I/O Port address. */
2350 adv_req_t *adv_reqp; /* Request structures. */
2351 dma_addr_t adv_reqp_addr;
2352 size_t adv_reqp_size;
2353 struct dma_pool *adv_sgblk_pool; /* Scatter-gather structures. */
2354 ushort bios_signature; /* BIOS Signature. */
2355 ushort bios_version; /* BIOS Version. */
2356 ushort bios_codeseg; /* BIOS Code Segment. */
2357 ushort bios_codelen; /* BIOS Code Segment Length. */
2360 #define asc_dvc_to_board(asc_dvc) container_of(asc_dvc, struct asc_board, \
2361 dvc_var.asc_dvc_var)
2362 #define adv_dvc_to_board(adv_dvc) container_of(adv_dvc, struct asc_board, \
2363 dvc_var.adv_dvc_var)
2364 #define adv_dvc_to_pdev(adv_dvc) to_pci_dev(adv_dvc_to_board(adv_dvc)->dev)
2366 #ifdef ADVANSYS_DEBUG
2367 static int asc_dbglvl = 3;
2370 * asc_prt_asc_dvc_var()
2372 static void asc_prt_asc_dvc_var(ASC_DVC_VAR *h)
2374 printk("ASC_DVC_VAR at addr 0x%lx\n", (ulong)h);
2376 printk(" iop_base 0x%x, err_code 0x%x, dvc_cntl 0x%x, bug_fix_cntl "
2377 "%d,\n", h->iop_base, h->err_code, h->dvc_cntl, h->bug_fix_cntl);
2379 printk(" bus_type %d, init_sdtr 0x%x,\n", h->bus_type,
2380 (unsigned)h->init_sdtr);
2382 printk(" sdtr_done 0x%x, use_tagged_qng 0x%x, unit_not_ready 0x%x, "
2383 "chip_no 0x%x,\n", (unsigned)h->sdtr_done,
2384 (unsigned)h->use_tagged_qng, (unsigned)h->unit_not_ready,
2385 (unsigned)h->chip_no);
2387 printk(" queue_full_or_busy 0x%x, start_motor 0x%x, scsi_reset_wait "
2388 "%u,\n", (unsigned)h->queue_full_or_busy,
2389 (unsigned)h->start_motor, (unsigned)h->scsi_reset_wait);
2391 printk(" is_in_int %u, max_total_qng %u, cur_total_qng %u, "
2392 "in_critical_cnt %u,\n", (unsigned)h->is_in_int,
2393 (unsigned)h->max_total_qng, (unsigned)h->cur_total_qng,
2394 (unsigned)h->in_critical_cnt);
2396 printk(" last_q_shortage %u, init_state 0x%x, no_scam 0x%x, "
2397 "pci_fix_asyn_xfer 0x%x,\n", (unsigned)h->last_q_shortage,
2398 (unsigned)h->init_state, (unsigned)h->no_scam,
2399 (unsigned)h->pci_fix_asyn_xfer);
2401 printk(" cfg 0x%lx\n", (ulong)h->cfg);
2405 * asc_prt_asc_dvc_cfg()
2407 static void asc_prt_asc_dvc_cfg(ASC_DVC_CFG *h)
2409 printk("ASC_DVC_CFG at addr 0x%lx\n", (ulong)h);
2411 printk(" can_tagged_qng 0x%x, cmd_qng_enabled 0x%x,\n",
2412 h->can_tagged_qng, h->cmd_qng_enabled);
2413 printk(" disc_enable 0x%x, sdtr_enable 0x%x,\n",
2414 h->disc_enable, h->sdtr_enable);
2416 printk(" chip_scsi_id %d, isa_dma_speed %d, isa_dma_channel %d, "
2417 "chip_version %d,\n", h->chip_scsi_id, h->isa_dma_speed,
2418 h->isa_dma_channel, h->chip_version);
2420 printk(" mcode_date 0x%x, mcode_version %d\n",
2421 h->mcode_date, h->mcode_version);
2425 * asc_prt_adv_dvc_var()
2427 * Display an ADV_DVC_VAR structure.
2429 static void asc_prt_adv_dvc_var(ADV_DVC_VAR *h)
2431 printk(" ADV_DVC_VAR at addr 0x%lx\n", (ulong)h);
2433 printk(" iop_base 0x%lx, err_code 0x%x, ultra_able 0x%x\n",
2434 (ulong)h->iop_base, h->err_code, (unsigned)h->ultra_able);
2436 printk(" sdtr_able 0x%x, wdtr_able 0x%x\n",
2437 (unsigned)h->sdtr_able, (unsigned)h->wdtr_able);
2439 printk(" start_motor 0x%x, scsi_reset_wait 0x%x\n",
2440 (unsigned)h->start_motor, (unsigned)h->scsi_reset_wait);
2442 printk(" max_host_qng %u, max_dvc_qng %u, carr_freelist 0x%p\n",
2443 (unsigned)h->max_host_qng, (unsigned)h->max_dvc_qng,
2446 printk(" icq_sp 0x%p, irq_sp 0x%p\n", h->icq_sp, h->irq_sp);
2448 printk(" no_scam 0x%x, tagqng_able 0x%x\n",
2449 (unsigned)h->no_scam, (unsigned)h->tagqng_able);
2451 printk(" chip_scsi_id 0x%x, cfg 0x%lx\n",
2452 (unsigned)h->chip_scsi_id, (ulong)h->cfg);
2456 * asc_prt_adv_dvc_cfg()
2458 * Display an ADV_DVC_CFG structure.
2460 static void asc_prt_adv_dvc_cfg(ADV_DVC_CFG *h)
2462 printk(" ADV_DVC_CFG at addr 0x%lx\n", (ulong)h);
2464 printk(" disc_enable 0x%x, termination 0x%x\n",
2465 h->disc_enable, h->termination);
2467 printk(" chip_version 0x%x, mcode_date 0x%x\n",
2468 h->chip_version, h->mcode_date);
2470 printk(" mcode_version 0x%x, control_flag 0x%x\n",
2471 h->mcode_version, h->control_flag);
2475 * asc_prt_scsi_host()
2477 static void asc_prt_scsi_host(struct Scsi_Host *s)
2479 struct asc_board *boardp = shost_priv(s);
2481 printk("Scsi_Host at addr 0x%p, device %s\n", s, dev_name(boardp->dev));
2482 printk(" host_busy %u, host_no %d,\n",
2483 atomic_read(&s->host_busy), s->host_no);
2485 printk(" base 0x%lx, io_port 0x%lx, irq %d,\n",
2486 (ulong)s->base, (ulong)s->io_port, boardp->irq);
2488 printk(" dma_channel %d, this_id %d, can_queue %d,\n",
2489 s->dma_channel, s->this_id, s->can_queue);
2491 printk(" cmd_per_lun %d, sg_tablesize %d, unchecked_isa_dma %d\n",
2492 s->cmd_per_lun, s->sg_tablesize, s->unchecked_isa_dma);
2494 if (ASC_NARROW_BOARD(boardp)) {
2495 asc_prt_asc_dvc_var(&boardp->dvc_var.asc_dvc_var);
2496 asc_prt_asc_dvc_cfg(&boardp->dvc_cfg.asc_dvc_cfg);
2498 asc_prt_adv_dvc_var(&boardp->dvc_var.adv_dvc_var);
2499 asc_prt_adv_dvc_cfg(&boardp->dvc_cfg.adv_dvc_cfg);
2506 * Print hexadecimal output in 4 byte groupings 32 bytes
2507 * or 8 double-words per line.
2509 static void asc_prt_hex(char *f, uchar *s, int l)
2516 printk("%s: (%d bytes)\n", f, l);
2518 for (i = 0; i < l; i += 32) {
2520 /* Display a maximum of 8 double-words per line. */
2521 if ((k = (l - i) / 4) >= 8) {
2528 for (j = 0; j < k; j++) {
2529 printk(" %2.2X%2.2X%2.2X%2.2X",
2530 (unsigned)s[i + (j * 4)],
2531 (unsigned)s[i + (j * 4) + 1],
2532 (unsigned)s[i + (j * 4) + 2],
2533 (unsigned)s[i + (j * 4) + 3]);
2541 printk(" %2.2X", (unsigned)s[i + (j * 4)]);
2544 printk(" %2.2X%2.2X",
2545 (unsigned)s[i + (j * 4)],
2546 (unsigned)s[i + (j * 4) + 1]);
2549 printk(" %2.2X%2.2X%2.2X",
2550 (unsigned)s[i + (j * 4) + 1],
2551 (unsigned)s[i + (j * 4) + 2],
2552 (unsigned)s[i + (j * 4) + 3]);
2561 * asc_prt_asc_scsi_q()
2563 static void asc_prt_asc_scsi_q(ASC_SCSI_Q *q)
2568 printk("ASC_SCSI_Q at addr 0x%lx\n", (ulong)q);
2571 (" target_ix 0x%x, target_lun %u, srb_tag 0x%x, tag_code 0x%x,\n",
2572 q->q2.target_ix, q->q1.target_lun, q->q2.srb_tag,
2576 (" data_addr 0x%lx, data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
2577 (ulong)le32_to_cpu(q->q1.data_addr),
2578 (ulong)le32_to_cpu(q->q1.data_cnt),
2579 (ulong)le32_to_cpu(q->q1.sense_addr), q->q1.sense_len);
2581 printk(" cdbptr 0x%lx, cdb_len %u, sg_head 0x%lx, sg_queue_cnt %u\n",
2582 (ulong)q->cdbptr, q->q2.cdb_len,
2583 (ulong)q->sg_head, q->q1.sg_queue_cnt);
2587 printk("ASC_SG_HEAD at addr 0x%lx\n", (ulong)sgp);
2588 printk(" entry_cnt %u, queue_cnt %u\n", sgp->entry_cnt,
2590 for (i = 0; i < sgp->entry_cnt; i++) {
2591 printk(" [%u]: addr 0x%lx, bytes %lu\n",
2592 i, (ulong)le32_to_cpu(sgp->sg_list[i].addr),
2593 (ulong)le32_to_cpu(sgp->sg_list[i].bytes));
2600 * asc_prt_asc_qdone_info()
2602 static void asc_prt_asc_qdone_info(ASC_QDONE_INFO *q)
2604 printk("ASC_QDONE_INFO at addr 0x%lx\n", (ulong)q);
2605 printk(" srb_tag 0x%x, target_ix %u, cdb_len %u, tag_code %u,\n",
2606 q->d2.srb_tag, q->d2.target_ix, q->d2.cdb_len,
2609 (" done_stat 0x%x, host_stat 0x%x, scsi_stat 0x%x, scsi_msg 0x%x\n",
2610 q->d3.done_stat, q->d3.host_stat, q->d3.scsi_stat, q->d3.scsi_msg);
2614 * asc_prt_adv_sgblock()
2616 * Display an ADV_SG_BLOCK structure.
2618 static void asc_prt_adv_sgblock(int sgblockno, ADV_SG_BLOCK *b)
2622 printk(" ADV_SG_BLOCK at addr 0x%lx (sgblockno %d)\n",
2623 (ulong)b, sgblockno);
2624 printk(" sg_cnt %u, sg_ptr 0x%lx\n",
2625 b->sg_cnt, (ulong)le32_to_cpu(b->sg_ptr));
2626 BUG_ON(b->sg_cnt > NO_OF_SG_PER_BLOCK);
2628 BUG_ON(b->sg_cnt != NO_OF_SG_PER_BLOCK);
2629 for (i = 0; i < b->sg_cnt; i++) {
2630 printk(" [%u]: sg_addr 0x%lx, sg_count 0x%lx\n",
2631 i, (ulong)b->sg_list[i].sg_addr,
2632 (ulong)b->sg_list[i].sg_count);
2637 * asc_prt_adv_scsi_req_q()
2639 * Display an ADV_SCSI_REQ_Q structure.
2641 static void asc_prt_adv_scsi_req_q(ADV_SCSI_REQ_Q *q)
2644 struct adv_sg_block *sg_ptr;
2645 adv_sgblk_t *sgblkp;
2647 printk("ADV_SCSI_REQ_Q at addr 0x%lx\n", (ulong)q);
2649 printk(" target_id %u, target_lun %u, srb_tag 0x%x, a_flag 0x%x\n",
2650 q->target_id, q->target_lun, q->srb_tag, q->a_flag);
2652 printk(" cntl 0x%x, data_addr 0x%lx\n",
2653 q->cntl, (ulong)le32_to_cpu(q->data_addr));
2655 printk(" data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
2656 (ulong)le32_to_cpu(q->data_cnt),
2657 (ulong)le32_to_cpu(q->sense_addr), q->sense_len);
2660 (" cdb_len %u, done_status 0x%x, host_status 0x%x, scsi_status 0x%x\n",
2661 q->cdb_len, q->done_status, q->host_status, q->scsi_status);
2663 printk(" sg_working_ix 0x%x, target_cmd %u\n",
2664 q->sg_working_ix, q->target_cmd);
2666 printk(" scsiq_rptr 0x%lx, sg_real_addr 0x%lx, sg_list_ptr 0x%lx\n",
2667 (ulong)le32_to_cpu(q->scsiq_rptr),
2668 (ulong)le32_to_cpu(q->sg_real_addr), (ulong)q->sg_list_ptr);
2670 /* Display the request's ADV_SG_BLOCK structures. */
2671 if (q->sg_list_ptr != NULL) {
2672 sgblkp = container_of(q->sg_list_ptr, adv_sgblk_t, sg_block);
2675 sg_ptr = &sgblkp->sg_block;
2676 asc_prt_adv_sgblock(sg_blk_cnt, sg_ptr);
2677 if (sg_ptr->sg_ptr == 0) {
2680 sgblkp = sgblkp->next_sgblkp;
2685 #endif /* ADVANSYS_DEBUG */
2690 * Return suitable for printing on the console with the argument
2691 * adapter's configuration information.
2693 * Note: The information line should not exceed ASC_INFO_SIZE bytes,
2694 * otherwise the static 'info' array will be overrun.
2696 static const char *advansys_info(struct Scsi_Host *shost)
2698 static char info[ASC_INFO_SIZE];
2699 struct asc_board *boardp = shost_priv(shost);
2700 ASC_DVC_VAR *asc_dvc_varp;
2701 ADV_DVC_VAR *adv_dvc_varp;
2703 char *widename = NULL;
2705 if (ASC_NARROW_BOARD(boardp)) {
2706 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
2707 ASC_DBG(1, "begin\n");
2708 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
2709 if ((asc_dvc_varp->bus_type & ASC_IS_ISAPNP) ==
2711 busname = "ISA PnP";
2716 "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X, DMA 0x%X",
2717 ASC_VERSION, busname,
2718 (ulong)shost->io_port,
2719 (ulong)shost->io_port + ASC_IOADR_GAP - 1,
2720 boardp->irq, shost->dma_channel);
2722 if (asc_dvc_varp->bus_type & ASC_IS_VL) {
2724 } else if (asc_dvc_varp->bus_type & ASC_IS_EISA) {
2726 } else if (asc_dvc_varp->bus_type & ASC_IS_PCI) {
2727 if ((asc_dvc_varp->bus_type & ASC_IS_PCI_ULTRA)
2728 == ASC_IS_PCI_ULTRA) {
2729 busname = "PCI Ultra";
2735 shost_printk(KERN_ERR, shost, "unknown bus "
2736 "type %d\n", asc_dvc_varp->bus_type);
2739 "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X",
2740 ASC_VERSION, busname, (ulong)shost->io_port,
2741 (ulong)shost->io_port + ASC_IOADR_GAP - 1,
2746 * Wide Adapter Information
2748 * Memory-mapped I/O is used instead of I/O space to access
2749 * the adapter, but display the I/O Port range. The Memory
2750 * I/O address is displayed through the driver /proc file.
2752 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
2753 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
2754 widename = "Ultra-Wide";
2755 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
2756 widename = "Ultra2-Wide";
2758 widename = "Ultra3-Wide";
2761 "AdvanSys SCSI %s: PCI %s: PCIMEM 0x%lX-0x%lX, IRQ 0x%X",
2762 ASC_VERSION, widename, (ulong)adv_dvc_varp->iop_base,
2763 (ulong)adv_dvc_varp->iop_base + boardp->asc_n_io_port - 1, boardp->irq);
2765 BUG_ON(strlen(info) >= ASC_INFO_SIZE);
2766 ASC_DBG(1, "end\n");
2770 #ifdef CONFIG_PROC_FS
2773 * asc_prt_board_devices()
2775 * Print driver information for devices attached to the board.
2777 static void asc_prt_board_devices(struct seq_file *m, struct Scsi_Host *shost)
2779 struct asc_board *boardp = shost_priv(shost);
2784 "\nDevice Information for AdvanSys SCSI Host %d:\n",
2787 if (ASC_NARROW_BOARD(boardp)) {
2788 chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
2790 chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
2793 seq_puts(m, "Target IDs Detected:");
2794 for (i = 0; i <= ADV_MAX_TID; i++) {
2795 if (boardp->init_tidmask & ADV_TID_TO_TIDMASK(i))
2796 seq_printf(m, " %X,", i);
2798 seq_printf(m, " (%X=Host Adapter)\n", chip_scsi_id);
2802 * Display Wide Board BIOS Information.
2804 static void asc_prt_adv_bios(struct seq_file *m, struct Scsi_Host *shost)
2806 struct asc_board *boardp = shost_priv(shost);
2807 ushort major, minor, letter;
2809 seq_puts(m, "\nROM BIOS Version: ");
2812 * If the BIOS saved a valid signature, then fill in
2813 * the BIOS code segment base address.
2815 if (boardp->bios_signature != 0x55AA) {
2816 seq_puts(m, "Disabled or Pre-3.1\n"
2817 "BIOS either disabled or Pre-3.1. If it is pre-3.1, then a newer version\n"
2818 "can be found at the ConnectCom FTP site: ftp://ftp.connectcom.net/pub\n");
2820 major = (boardp->bios_version >> 12) & 0xF;
2821 minor = (boardp->bios_version >> 8) & 0xF;
2822 letter = (boardp->bios_version & 0xFF);
2824 seq_printf(m, "%d.%d%c\n",
2826 letter >= 26 ? '?' : letter + 'A');
2828 * Current available ROM BIOS release is 3.1I for UW
2829 * and 3.2I for U2W. This code doesn't differentiate
2830 * UW and U2W boards.
2832 if (major < 3 || (major <= 3 && minor < 1) ||
2833 (major <= 3 && minor <= 1 && letter < ('I' - 'A'))) {
2834 seq_puts(m, "Newer version of ROM BIOS is available at the ConnectCom FTP site:\n"
2835 "ftp://ftp.connectcom.net/pub\n");
2841 * Add serial number to information bar if signature AAh
2842 * is found in at bit 15-9 (7 bits) of word 1.
2844 * Serial Number consists fo 12 alpha-numeric digits.
2846 * 1 - Product type (A,B,C,D..) Word0: 15-13 (3 bits)
2847 * 2 - MFG Location (A,B,C,D..) Word0: 12-10 (3 bits)
2848 * 3-4 - Product ID (0-99) Word0: 9-0 (10 bits)
2849 * 5 - Product revision (A-J) Word0: " "
2851 * Signature Word1: 15-9 (7 bits)
2852 * 6 - Year (0-9) Word1: 8-6 (3 bits) & Word2: 15 (1 bit)
2853 * 7-8 - Week of the year (1-52) Word1: 5-0 (6 bits)
2855 * 9-12 - Serial Number (A001-Z999) Word2: 14-0 (15 bits)
2857 * Note 1: Only production cards will have a serial number.
2859 * Note 2: Signature is most significant 7 bits (0xFE).
2861 * Returns ASC_TRUE if serial number found, otherwise returns ASC_FALSE.
2863 static int asc_get_eeprom_string(ushort *serialnum, uchar *cp)
2867 if ((serialnum[1] & 0xFE00) != ((ushort)0xAA << 8)) {
2871 * First word - 6 digits.
2875 /* Product type - 1st digit. */
2876 if ((*cp = 'A' + ((w & 0xE000) >> 13)) == 'H') {
2877 /* Product type is P=Prototype */
2882 /* Manufacturing location - 2nd digit. */
2883 *cp++ = 'A' + ((w & 0x1C00) >> 10);
2885 /* Product ID - 3rd, 4th digits. */
2887 *cp++ = '0' + (num / 100);
2889 *cp++ = '0' + (num / 10);
2891 /* Product revision - 5th digit. */
2892 *cp++ = 'A' + (num % 10);
2902 * If bit 15 of third word is set, then the
2903 * last digit of the year is greater than 7.
2905 if (serialnum[2] & 0x8000) {
2906 *cp++ = '8' + ((w & 0x1C0) >> 6);
2908 *cp++ = '0' + ((w & 0x1C0) >> 6);
2911 /* Week of year - 7th, 8th digits. */
2913 *cp++ = '0' + num / 10;
2920 w = serialnum[2] & 0x7FFF;
2922 /* Serial number - 9th digit. */
2923 *cp++ = 'A' + (w / 1000);
2925 /* 10th, 11th, 12th digits. */
2927 *cp++ = '0' + num / 100;
2929 *cp++ = '0' + num / 10;
2933 *cp = '\0'; /* Null Terminate the string. */
2939 * asc_prt_asc_board_eeprom()
2941 * Print board EEPROM configuration.
2943 static void asc_prt_asc_board_eeprom(struct seq_file *m, struct Scsi_Host *shost)
2945 struct asc_board *boardp = shost_priv(shost);
2946 ASC_DVC_VAR *asc_dvc_varp;
2950 int isa_dma_speed[] = { 10, 8, 7, 6, 5, 4, 3, 2 };
2951 #endif /* CONFIG_ISA */
2952 uchar serialstr[13];
2954 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
2955 ep = &boardp->eep_config.asc_eep;
2958 "\nEEPROM Settings for AdvanSys SCSI Host %d:\n",
2961 if (asc_get_eeprom_string((ushort *)&ep->adapter_info[0], serialstr)
2963 seq_printf(m, " Serial Number: %s\n", serialstr);
2964 else if (ep->adapter_info[5] == 0xBB)
2966 " Default Settings Used for EEPROM-less Adapter.\n");
2968 seq_puts(m, " Serial Number Signature Not Present.\n");
2971 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
2972 ASC_EEP_GET_CHIP_ID(ep), ep->max_total_qng,
2976 " cntl 0x%x, no_scam 0x%x\n", ep->cntl, ep->no_scam);
2978 seq_puts(m, " Target ID: ");
2979 for (i = 0; i <= ASC_MAX_TID; i++)
2980 seq_printf(m, " %d", i);
2982 seq_puts(m, "\n Disconnects: ");
2983 for (i = 0; i <= ASC_MAX_TID; i++)
2984 seq_printf(m, " %c",
2985 (ep->disc_enable & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
2987 seq_puts(m, "\n Command Queuing: ");
2988 for (i = 0; i <= ASC_MAX_TID; i++)
2989 seq_printf(m, " %c",
2990 (ep->use_cmd_qng & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
2992 seq_puts(m, "\n Start Motor: ");
2993 for (i = 0; i <= ASC_MAX_TID; i++)
2994 seq_printf(m, " %c",
2995 (ep->start_motor & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
2997 seq_puts(m, "\n Synchronous Transfer:");
2998 for (i = 0; i <= ASC_MAX_TID; i++)
2999 seq_printf(m, " %c",
3000 (ep->init_sdtr & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3004 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
3006 " Host ISA DMA speed: %d MB/S\n",
3007 isa_dma_speed[ASC_EEP_GET_DMA_SPD(ep)]);
3009 #endif /* CONFIG_ISA */
3013 * asc_prt_adv_board_eeprom()
3015 * Print board EEPROM configuration.
3017 static void asc_prt_adv_board_eeprom(struct seq_file *m, struct Scsi_Host *shost)
3019 struct asc_board *boardp = shost_priv(shost);
3020 ADV_DVC_VAR *adv_dvc_varp;
3023 uchar serialstr[13];
3024 ADVEEP_3550_CONFIG *ep_3550 = NULL;
3025 ADVEEP_38C0800_CONFIG *ep_38C0800 = NULL;
3026 ADVEEP_38C1600_CONFIG *ep_38C1600 = NULL;
3029 ushort sdtr_speed = 0;
3031 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
3032 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3033 ep_3550 = &boardp->eep_config.adv_3550_eep;
3034 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3035 ep_38C0800 = &boardp->eep_config.adv_38C0800_eep;
3037 ep_38C1600 = &boardp->eep_config.adv_38C1600_eep;
3041 "\nEEPROM Settings for AdvanSys SCSI Host %d:\n",
3044 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3045 wordp = &ep_3550->serial_number_word1;
3046 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3047 wordp = &ep_38C0800->serial_number_word1;
3049 wordp = &ep_38C1600->serial_number_word1;
3052 if (asc_get_eeprom_string(wordp, serialstr) == ASC_TRUE)
3053 seq_printf(m, " Serial Number: %s\n", serialstr);
3055 seq_puts(m, " Serial Number Signature Not Present.\n");
3057 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
3059 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3060 ep_3550->adapter_scsi_id,
3061 ep_3550->max_host_qng, ep_3550->max_dvc_qng);
3062 else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
3064 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3065 ep_38C0800->adapter_scsi_id,
3066 ep_38C0800->max_host_qng,
3067 ep_38C0800->max_dvc_qng);
3070 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3071 ep_38C1600->adapter_scsi_id,
3072 ep_38C1600->max_host_qng,
3073 ep_38C1600->max_dvc_qng);
3074 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3075 word = ep_3550->termination;
3076 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3077 word = ep_38C0800->termination_lvd;
3079 word = ep_38C1600->termination_lvd;
3083 termstr = "Low Off/High Off";
3086 termstr = "Low Off/High On";
3089 termstr = "Low On/High On";
3093 termstr = "Automatic";
3097 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
3099 " termination: %u (%s), bios_ctrl: 0x%x\n",
3100 ep_3550->termination, termstr,
3101 ep_3550->bios_ctrl);
3102 else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
3104 " termination: %u (%s), bios_ctrl: 0x%x\n",
3105 ep_38C0800->termination_lvd, termstr,
3106 ep_38C0800->bios_ctrl);
3109 " termination: %u (%s), bios_ctrl: 0x%x\n",
3110 ep_38C1600->termination_lvd, termstr,
3111 ep_38C1600->bios_ctrl);
3113 seq_puts(m, " Target ID: ");
3114 for (i = 0; i <= ADV_MAX_TID; i++)
3115 seq_printf(m, " %X", i);
3118 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3119 word = ep_3550->disc_enable;
3120 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3121 word = ep_38C0800->disc_enable;
3123 word = ep_38C1600->disc_enable;
3125 seq_puts(m, " Disconnects: ");
3126 for (i = 0; i <= ADV_MAX_TID; i++)
3127 seq_printf(m, " %c",
3128 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3131 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3132 word = ep_3550->tagqng_able;
3133 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3134 word = ep_38C0800->tagqng_able;
3136 word = ep_38C1600->tagqng_able;
3138 seq_puts(m, " Command Queuing: ");
3139 for (i = 0; i <= ADV_MAX_TID; i++)
3140 seq_printf(m, " %c",
3141 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3144 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3145 word = ep_3550->start_motor;
3146 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3147 word = ep_38C0800->start_motor;
3149 word = ep_38C1600->start_motor;
3151 seq_puts(m, " Start Motor: ");
3152 for (i = 0; i <= ADV_MAX_TID; i++)
3153 seq_printf(m, " %c",
3154 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3157 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3158 seq_puts(m, " Synchronous Transfer:");
3159 for (i = 0; i <= ADV_MAX_TID; i++)
3160 seq_printf(m, " %c",
3161 (ep_3550->sdtr_able & ADV_TID_TO_TIDMASK(i)) ?
3166 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3167 seq_puts(m, " Ultra Transfer: ");
3168 for (i = 0; i <= ADV_MAX_TID; i++)
3169 seq_printf(m, " %c",
3170 (ep_3550->ultra_able & ADV_TID_TO_TIDMASK(i))
3175 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3176 word = ep_3550->wdtr_able;
3177 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3178 word = ep_38C0800->wdtr_able;
3180 word = ep_38C1600->wdtr_able;
3182 seq_puts(m, " Wide Transfer: ");
3183 for (i = 0; i <= ADV_MAX_TID; i++)
3184 seq_printf(m, " %c",
3185 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3188 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800 ||
3189 adv_dvc_varp->chip_type == ADV_CHIP_ASC38C1600) {
3190 seq_puts(m, " Synchronous Transfer Speed (Mhz):\n ");
3191 for (i = 0; i <= ADV_MAX_TID; i++) {
3195 sdtr_speed = adv_dvc_varp->sdtr_speed1;
3196 } else if (i == 4) {
3197 sdtr_speed = adv_dvc_varp->sdtr_speed2;
3198 } else if (i == 8) {
3199 sdtr_speed = adv_dvc_varp->sdtr_speed3;
3200 } else if (i == 12) {
3201 sdtr_speed = adv_dvc_varp->sdtr_speed4;
3203 switch (sdtr_speed & ADV_MAX_TID) {
3226 seq_printf(m, "%X:%s ", i, speed_str);
3236 * asc_prt_driver_conf()
3238 static void asc_prt_driver_conf(struct seq_file *m, struct Scsi_Host *shost)
3240 struct asc_board *boardp = shost_priv(shost);
3244 "\nLinux Driver Configuration and Information for AdvanSys SCSI Host %d:\n",
3248 " host_busy %u, max_id %u, max_lun %llu, max_channel %u\n",
3249 atomic_read(&shost->host_busy), shost->max_id,
3250 shost->max_lun, shost->max_channel);
3253 " unique_id %d, can_queue %d, this_id %d, sg_tablesize %u, cmd_per_lun %u\n",
3254 shost->unique_id, shost->can_queue, shost->this_id,
3255 shost->sg_tablesize, shost->cmd_per_lun);
3258 " unchecked_isa_dma %d, use_clustering %d\n",
3259 shost->unchecked_isa_dma, shost->use_clustering);
3262 " flags 0x%x, last_reset 0x%lx, jiffies 0x%lx, asc_n_io_port 0x%x\n",
3263 boardp->flags, shost->last_reset, jiffies,
3264 boardp->asc_n_io_port);
3266 seq_printf(m, " io_port 0x%lx\n", shost->io_port);
3268 if (ASC_NARROW_BOARD(boardp)) {
3269 chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
3271 chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
3276 * asc_prt_asc_board_info()
3278 * Print dynamic board configuration information.
3280 static void asc_prt_asc_board_info(struct seq_file *m, struct Scsi_Host *shost)
3282 struct asc_board *boardp = shost_priv(shost);
3287 int renegotiate = 0;
3289 v = &boardp->dvc_var.asc_dvc_var;
3290 c = &boardp->dvc_cfg.asc_dvc_cfg;
3291 chip_scsi_id = c->chip_scsi_id;
3294 "\nAsc Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
3297 seq_printf(m, " chip_version %u, mcode_date 0x%x, "
3298 "mcode_version 0x%x, err_code %u\n",
3299 c->chip_version, c->mcode_date, c->mcode_version,
3302 /* Current number of commands waiting for the host. */
3304 " Total Command Pending: %d\n", v->cur_total_qng);
3306 seq_puts(m, " Command Queuing:");
3307 for (i = 0; i <= ASC_MAX_TID; i++) {
3308 if ((chip_scsi_id == i) ||
3309 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3312 seq_printf(m, " %X:%c",
3314 (v->use_tagged_qng & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3317 /* Current number of commands waiting for a device. */
3318 seq_puts(m, "\n Command Queue Pending:");
3319 for (i = 0; i <= ASC_MAX_TID; i++) {
3320 if ((chip_scsi_id == i) ||
3321 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3324 seq_printf(m, " %X:%u", i, v->cur_dvc_qng[i]);
3327 /* Current limit on number of commands that can be sent to a device. */
3328 seq_puts(m, "\n Command Queue Limit:");
3329 for (i = 0; i <= ASC_MAX_TID; i++) {
3330 if ((chip_scsi_id == i) ||
3331 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3334 seq_printf(m, " %X:%u", i, v->max_dvc_qng[i]);
3337 /* Indicate whether the device has returned queue full status. */
3338 seq_puts(m, "\n Command Queue Full:");
3339 for (i = 0; i <= ASC_MAX_TID; i++) {
3340 if ((chip_scsi_id == i) ||
3341 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3344 if (boardp->queue_full & ADV_TID_TO_TIDMASK(i))
3345 seq_printf(m, " %X:Y-%d",
3346 i, boardp->queue_full_cnt[i]);
3348 seq_printf(m, " %X:N", i);
3351 seq_puts(m, "\n Synchronous Transfer:");
3352 for (i = 0; i <= ASC_MAX_TID; i++) {
3353 if ((chip_scsi_id == i) ||
3354 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3357 seq_printf(m, " %X:%c",
3359 (v->sdtr_done & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3363 for (i = 0; i <= ASC_MAX_TID; i++) {
3364 uchar syn_period_ix;
3366 if ((chip_scsi_id == i) ||
3367 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) ||
3368 ((v->init_sdtr & ADV_TID_TO_TIDMASK(i)) == 0)) {
3372 seq_printf(m, " %X:", i);
3374 if ((boardp->sdtr_data[i] & ASC_SYN_MAX_OFFSET) == 0) {
3375 seq_puts(m, " Asynchronous");
3378 (boardp->sdtr_data[i] >> 4) & (v->max_sdtr_index -
3382 " Transfer Period Factor: %d (%d.%d Mhz),",
3383 v->sdtr_period_tbl[syn_period_ix],
3384 250 / v->sdtr_period_tbl[syn_period_ix],
3386 v->sdtr_period_tbl[syn_period_ix]));
3388 seq_printf(m, " REQ/ACK Offset: %d",
3389 boardp->sdtr_data[i] & ASC_SYN_MAX_OFFSET);
3392 if ((v->sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
3401 seq_puts(m, " * = Re-negotiation pending before next command.\n");
3406 * asc_prt_adv_board_info()
3408 * Print dynamic board configuration information.
3410 static void asc_prt_adv_board_info(struct seq_file *m, struct Scsi_Host *shost)
3412 struct asc_board *boardp = shost_priv(shost);
3416 AdvPortAddr iop_base;
3417 ushort chip_scsi_id;
3421 ushort sdtr_able, wdtr_able;
3422 ushort wdtr_done, sdtr_done;
3424 int renegotiate = 0;
3426 v = &boardp->dvc_var.adv_dvc_var;
3427 c = &boardp->dvc_cfg.adv_dvc_cfg;
3428 iop_base = v->iop_base;
3429 chip_scsi_id = v->chip_scsi_id;
3432 "\nAdv Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
3436 " iop_base 0x%lx, cable_detect: %X, err_code %u\n",
3437 (unsigned long)v->iop_base,
3438 AdvReadWordRegister(iop_base,IOPW_SCSI_CFG1) & CABLE_DETECT,
3441 seq_printf(m, " chip_version %u, mcode_date 0x%x, "
3442 "mcode_version 0x%x\n", c->chip_version,
3443 c->mcode_date, c->mcode_version);
3445 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
3446 seq_puts(m, " Queuing Enabled:");
3447 for (i = 0; i <= ADV_MAX_TID; i++) {
3448 if ((chip_scsi_id == i) ||
3449 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3453 seq_printf(m, " %X:%c",
3455 (tagqng_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3458 seq_puts(m, "\n Queue Limit:");
3459 for (i = 0; i <= ADV_MAX_TID; i++) {
3460 if ((chip_scsi_id == i) ||
3461 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3465 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + i,
3468 seq_printf(m, " %X:%d", i, lrambyte);
3471 seq_puts(m, "\n Command Pending:");
3472 for (i = 0; i <= ADV_MAX_TID; i++) {
3473 if ((chip_scsi_id == i) ||
3474 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3478 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_QUEUED_CMD + i,
3481 seq_printf(m, " %X:%d", i, lrambyte);
3485 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
3486 seq_puts(m, " Wide Enabled:");
3487 for (i = 0; i <= ADV_MAX_TID; i++) {
3488 if ((chip_scsi_id == i) ||
3489 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3493 seq_printf(m, " %X:%c",
3495 (wdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3499 AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, wdtr_done);
3500 seq_puts(m, " Transfer Bit Width:");
3501 for (i = 0; i <= ADV_MAX_TID; i++) {
3502 if ((chip_scsi_id == i) ||
3503 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3507 AdvReadWordLram(iop_base,
3508 ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i),
3511 seq_printf(m, " %X:%d",
3512 i, (lramword & 0x8000) ? 16 : 8);
3514 if ((wdtr_able & ADV_TID_TO_TIDMASK(i)) &&
3515 (wdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
3522 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
3523 seq_puts(m, " Synchronous Enabled:");
3524 for (i = 0; i <= ADV_MAX_TID; i++) {
3525 if ((chip_scsi_id == i) ||
3526 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3530 seq_printf(m, " %X:%c",
3532 (sdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3536 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, sdtr_done);
3537 for (i = 0; i <= ADV_MAX_TID; i++) {
3539 AdvReadWordLram(iop_base,
3540 ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i),
3542 lramword &= ~0x8000;
3544 if ((chip_scsi_id == i) ||
3545 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) ||
3546 ((sdtr_able & ADV_TID_TO_TIDMASK(i)) == 0)) {
3550 seq_printf(m, " %X:", i);
3552 if ((lramword & 0x1F) == 0) { /* Check for REQ/ACK Offset 0. */
3553 seq_puts(m, " Asynchronous");
3555 seq_puts(m, " Transfer Period Factor: ");
3557 if ((lramword & 0x1F00) == 0x1100) { /* 80 Mhz */
3558 seq_puts(m, "9 (80.0 Mhz),");
3559 } else if ((lramword & 0x1F00) == 0x1000) { /* 40 Mhz */
3560 seq_puts(m, "10 (40.0 Mhz),");
3561 } else { /* 20 Mhz or below. */
3563 period = (((lramword >> 8) * 25) + 50) / 4;
3565 if (period == 0) { /* Should never happen. */
3566 seq_printf(m, "%d (? Mhz), ", period);
3570 period, 250 / period,
3571 ASC_TENTHS(250, period));
3575 seq_printf(m, " REQ/ACK Offset: %d",
3579 if ((sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
3588 seq_puts(m, " * = Re-negotiation pending before next command.\n");
3592 #ifdef ADVANSYS_STATS
3594 * asc_prt_board_stats()
3596 static void asc_prt_board_stats(struct seq_file *m, struct Scsi_Host *shost)
3598 struct asc_board *boardp = shost_priv(shost);
3599 struct asc_stats *s = &boardp->asc_stats;
3602 "\nLinux Driver Statistics for AdvanSys SCSI Host %d:\n",
3606 " queuecommand %u, reset %u, biosparam %u, interrupt %u\n",
3607 s->queuecommand, s->reset, s->biosparam,
3611 " callback %u, done %u, build_error %u, build_noreq %u, build_nosg %u\n",
3612 s->callback, s->done, s->build_error,
3613 s->adv_build_noreq, s->adv_build_nosg);
3616 " exe_noerror %u, exe_busy %u, exe_error %u, exe_unknown %u\n",
3617 s->exe_noerror, s->exe_busy, s->exe_error,
3621 * Display data transfer statistics.
3623 if (s->xfer_cnt > 0) {
3624 seq_printf(m, " xfer_cnt %u, xfer_elem %u, ",
3625 s->xfer_cnt, s->xfer_elem);
3627 seq_printf(m, "xfer_bytes %u.%01u kb\n",
3628 s->xfer_sect / 2, ASC_TENTHS(s->xfer_sect, 2));
3630 /* Scatter gather transfer statistics */
3631 seq_printf(m, " avg_num_elem %u.%01u, ",
3632 s->xfer_elem / s->xfer_cnt,
3633 ASC_TENTHS(s->xfer_elem, s->xfer_cnt));
3635 seq_printf(m, "avg_elem_size %u.%01u kb, ",
3636 (s->xfer_sect / 2) / s->xfer_elem,
3637 ASC_TENTHS((s->xfer_sect / 2), s->xfer_elem));
3639 seq_printf(m, "avg_xfer_size %u.%01u kb\n",
3640 (s->xfer_sect / 2) / s->xfer_cnt,
3641 ASC_TENTHS((s->xfer_sect / 2), s->xfer_cnt));
3644 #endif /* ADVANSYS_STATS */
3647 * advansys_show_info() - /proc/scsi/advansys/{0,1,2,3,...}
3649 * m: seq_file to print into
3652 * Return the number of bytes read from or written to a
3653 * /proc/scsi/advansys/[0...] file.
3656 advansys_show_info(struct seq_file *m, struct Scsi_Host *shost)
3658 struct asc_board *boardp = shost_priv(shost);
3660 ASC_DBG(1, "begin\n");
3663 * User read of /proc/scsi/advansys/[0...] file.
3667 * Get board configuration information.
3669 * advansys_info() returns the board string from its own static buffer.
3671 /* Copy board information. */
3672 seq_printf(m, "%s\n", (char *)advansys_info(shost));
3674 * Display Wide Board BIOS Information.
3676 if (!ASC_NARROW_BOARD(boardp))
3677 asc_prt_adv_bios(m, shost);
3680 * Display driver information for each device attached to the board.
3682 asc_prt_board_devices(m, shost);
3685 * Display EEPROM configuration for the board.
3687 if (ASC_NARROW_BOARD(boardp))
3688 asc_prt_asc_board_eeprom(m, shost);
3690 asc_prt_adv_board_eeprom(m, shost);
3693 * Display driver configuration and information for the board.
3695 asc_prt_driver_conf(m, shost);
3697 #ifdef ADVANSYS_STATS
3699 * Display driver statistics for the board.
3701 asc_prt_board_stats(m, shost);
3702 #endif /* ADVANSYS_STATS */
3705 * Display Asc Library dynamic configuration information
3708 if (ASC_NARROW_BOARD(boardp))
3709 asc_prt_asc_board_info(m, shost);
3711 asc_prt_adv_board_info(m, shost);
3714 #endif /* CONFIG_PROC_FS */
3716 static void asc_scsi_done(struct scsi_cmnd *scp)
3718 scsi_dma_unmap(scp);
3719 ASC_STATS(scp->device->host, done);
3720 scp->scsi_done(scp);
3723 static void AscSetBank(PortAddr iop_base, uchar bank)
3727 val = AscGetChipControl(iop_base) &
3729 (CC_SINGLE_STEP | CC_TEST | CC_DIAG | CC_SCSI_RESET |
3733 } else if (bank == 2) {
3734 val |= CC_DIAG | CC_BANK_ONE;
3736 val &= ~CC_BANK_ONE;
3738 AscSetChipControl(iop_base, val);
3741 static void AscSetChipIH(PortAddr iop_base, ushort ins_code)
3743 AscSetBank(iop_base, 1);
3744 AscWriteChipIH(iop_base, ins_code);
3745 AscSetBank(iop_base, 0);
3748 static int AscStartChip(PortAddr iop_base)
3750 AscSetChipControl(iop_base, 0);
3751 if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) {
3757 static int AscStopChip(PortAddr iop_base)
3762 AscGetChipControl(iop_base) &
3763 (~(CC_SINGLE_STEP | CC_TEST | CC_DIAG));
3764 AscSetChipControl(iop_base, (uchar)(cc_val | CC_HALT));
3765 AscSetChipIH(iop_base, INS_HALT);
3766 AscSetChipIH(iop_base, INS_RFLAG_WTM);
3767 if ((AscGetChipStatus(iop_base) & CSW_HALTED) == 0) {
3773 static bool AscIsChipHalted(PortAddr iop_base)
3775 if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) {
3776 if ((AscGetChipControl(iop_base) & CC_HALT) != 0) {
3783 static bool AscResetChipAndScsiBus(ASC_DVC_VAR *asc_dvc)
3788 iop_base = asc_dvc->iop_base;
3789 while ((AscGetChipStatus(iop_base) & CSW_SCSI_RESET_ACTIVE)
3793 AscStopChip(iop_base);
3794 AscSetChipControl(iop_base, CC_CHIP_RESET | CC_SCSI_RESET | CC_HALT);
3796 AscSetChipIH(iop_base, INS_RFLAG_WTM);
3797 AscSetChipIH(iop_base, INS_HALT);
3798 AscSetChipControl(iop_base, CC_CHIP_RESET | CC_HALT);
3799 AscSetChipControl(iop_base, CC_HALT);
3801 AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT);
3802 AscSetChipStatus(iop_base, 0);
3803 return (AscIsChipHalted(iop_base));
3806 static int AscFindSignature(PortAddr iop_base)
3810 ASC_DBG(1, "AscGetChipSignatureByte(0x%x) 0x%x\n",
3811 iop_base, AscGetChipSignatureByte(iop_base));
3812 if (AscGetChipSignatureByte(iop_base) == (uchar)ASC_1000_ID1B) {
3813 ASC_DBG(1, "AscGetChipSignatureWord(0x%x) 0x%x\n",
3814 iop_base, AscGetChipSignatureWord(iop_base));
3815 sig_word = AscGetChipSignatureWord(iop_base);
3816 if ((sig_word == (ushort)ASC_1000_ID0W) ||
3817 (sig_word == (ushort)ASC_1000_ID0W_FIX)) {
3824 static void AscEnableInterrupt(PortAddr iop_base)
3828 cfg = AscGetChipCfgLsw(iop_base);
3829 AscSetChipCfgLsw(iop_base, cfg | ASC_CFG0_HOST_INT_ON);
3832 static void AscDisableInterrupt(PortAddr iop_base)
3836 cfg = AscGetChipCfgLsw(iop_base);
3837 AscSetChipCfgLsw(iop_base, cfg & (~ASC_CFG0_HOST_INT_ON));
3840 static uchar AscReadLramByte(PortAddr iop_base, ushort addr)
3842 unsigned char byte_data;
3843 unsigned short word_data;
3845 if (isodd_word(addr)) {
3846 AscSetChipLramAddr(iop_base, addr - 1);
3847 word_data = AscGetChipLramData(iop_base);
3848 byte_data = (word_data >> 8) & 0xFF;
3850 AscSetChipLramAddr(iop_base, addr);
3851 word_data = AscGetChipLramData(iop_base);
3852 byte_data = word_data & 0xFF;
3857 static ushort AscReadLramWord(PortAddr iop_base, ushort addr)
3861 AscSetChipLramAddr(iop_base, addr);
3862 word_data = AscGetChipLramData(iop_base);
3866 #if CC_VERY_LONG_SG_LIST
3867 static u32 AscReadLramDWord(PortAddr iop_base, ushort addr)
3869 ushort val_low, val_high;
3872 AscSetChipLramAddr(iop_base, addr);
3873 val_low = AscGetChipLramData(iop_base);
3874 val_high = AscGetChipLramData(iop_base);
3875 dword_data = ((u32) val_high << 16) | (u32) val_low;
3876 return (dword_data);
3878 #endif /* CC_VERY_LONG_SG_LIST */
3881 AscMemWordSetLram(PortAddr iop_base, ushort s_addr, ushort set_wval, int words)
3885 AscSetChipLramAddr(iop_base, s_addr);
3886 for (i = 0; i < words; i++) {
3887 AscSetChipLramData(iop_base, set_wval);
3891 static void AscWriteLramWord(PortAddr iop_base, ushort addr, ushort word_val)
3893 AscSetChipLramAddr(iop_base, addr);
3894 AscSetChipLramData(iop_base, word_val);
3897 static void AscWriteLramByte(PortAddr iop_base, ushort addr, uchar byte_val)
3901 if (isodd_word(addr)) {
3903 word_data = AscReadLramWord(iop_base, addr);
3904 word_data &= 0x00FF;
3905 word_data |= (((ushort)byte_val << 8) & 0xFF00);
3907 word_data = AscReadLramWord(iop_base, addr);
3908 word_data &= 0xFF00;
3909 word_data |= ((ushort)byte_val & 0x00FF);
3911 AscWriteLramWord(iop_base, addr, word_data);
3915 * Copy 2 bytes to LRAM.
3917 * The source data is assumed to be in little-endian order in memory
3918 * and is maintained in little-endian order when written to LRAM.
3921 AscMemWordCopyPtrToLram(PortAddr iop_base, ushort s_addr,
3922 const uchar *s_buffer, int words)
3926 AscSetChipLramAddr(iop_base, s_addr);
3927 for (i = 0; i < 2 * words; i += 2) {
3929 * On a little-endian system the second argument below
3930 * produces a little-endian ushort which is written to
3931 * LRAM in little-endian order. On a big-endian system
3932 * the second argument produces a big-endian ushort which
3933 * is "transparently" byte-swapped by outpw() and written
3934 * in little-endian order to LRAM.
3936 outpw(iop_base + IOP_RAM_DATA,
3937 ((ushort)s_buffer[i + 1] << 8) | s_buffer[i]);
3942 * Copy 4 bytes to LRAM.
3944 * The source data is assumed to be in little-endian order in memory
3945 * and is maintained in little-endian order when written to LRAM.
3948 AscMemDWordCopyPtrToLram(PortAddr iop_base,
3949 ushort s_addr, uchar *s_buffer, int dwords)
3953 AscSetChipLramAddr(iop_base, s_addr);
3954 for (i = 0; i < 4 * dwords; i += 4) {
3955 outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 1] << 8) | s_buffer[i]); /* LSW */
3956 outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 3] << 8) | s_buffer[i + 2]); /* MSW */
3961 * Copy 2 bytes from LRAM.
3963 * The source data is assumed to be in little-endian order in LRAM
3964 * and is maintained in little-endian order when written to memory.
3967 AscMemWordCopyPtrFromLram(PortAddr iop_base,
3968 ushort s_addr, uchar *d_buffer, int words)
3973 AscSetChipLramAddr(iop_base, s_addr);
3974 for (i = 0; i < 2 * words; i += 2) {
3975 word = inpw(iop_base + IOP_RAM_DATA);
3976 d_buffer[i] = word & 0xff;
3977 d_buffer[i + 1] = (word >> 8) & 0xff;
3981 static u32 AscMemSumLramWord(PortAddr iop_base, ushort s_addr, int words)
3986 for (i = 0; i < words; i++, s_addr += 2) {
3987 sum += AscReadLramWord(iop_base, s_addr);
3992 static ushort AscInitLram(ASC_DVC_VAR *asc_dvc)
3999 iop_base = asc_dvc->iop_base;
4001 AscMemWordSetLram(iop_base, ASC_QADR_BEG, 0,
4002 (ushort)(((int)(asc_dvc->max_total_qng + 2 + 1) *
4004 i = ASC_MIN_ACTIVE_QNO;
4005 s_addr = ASC_QADR_BEG + ASC_QBLK_SIZE;
4006 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
4008 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
4009 (uchar)(asc_dvc->max_total_qng));
4010 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
4013 s_addr += ASC_QBLK_SIZE;
4014 for (; i < asc_dvc->max_total_qng; i++, s_addr += ASC_QBLK_SIZE) {
4015 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
4017 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
4019 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
4022 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
4023 (uchar)ASC_QLINK_END);
4024 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
4025 (uchar)(asc_dvc->max_total_qng - 1));
4026 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
4027 (uchar)asc_dvc->max_total_qng);
4029 s_addr += ASC_QBLK_SIZE;
4030 for (; i <= (uchar)(asc_dvc->max_total_qng + 3);
4031 i++, s_addr += ASC_QBLK_SIZE) {
4032 AscWriteLramByte(iop_base,
4033 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_FWD), i);
4034 AscWriteLramByte(iop_base,
4035 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_BWD), i);
4036 AscWriteLramByte(iop_base,
4037 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_QNO), i);
4043 AscLoadMicroCode(PortAddr iop_base, ushort s_addr,
4044 const uchar *mcode_buf, ushort mcode_size)
4047 ushort mcode_word_size;
4048 ushort mcode_chksum;
4050 /* Write the microcode buffer starting at LRAM address 0. */
4051 mcode_word_size = (ushort)(mcode_size >> 1);
4052 AscMemWordSetLram(iop_base, s_addr, 0, mcode_word_size);
4053 AscMemWordCopyPtrToLram(iop_base, s_addr, mcode_buf, mcode_word_size);
4055 chksum = AscMemSumLramWord(iop_base, s_addr, mcode_word_size);
4056 ASC_DBG(1, "chksum 0x%lx\n", (ulong)chksum);
4057 mcode_chksum = (ushort)AscMemSumLramWord(iop_base,
4058 (ushort)ASC_CODE_SEC_BEG,
4059 (ushort)((mcode_size -
4063 ASC_DBG(1, "mcode_chksum 0x%lx\n", (ulong)mcode_chksum);
4064 AscWriteLramWord(iop_base, ASCV_MCODE_CHKSUM_W, mcode_chksum);
4065 AscWriteLramWord(iop_base, ASCV_MCODE_SIZE_W, mcode_size);
4069 static void AscInitQLinkVar(ASC_DVC_VAR *asc_dvc)
4075 iop_base = asc_dvc->iop_base;
4076 AscPutRiscVarFreeQHead(iop_base, 1);
4077 AscPutRiscVarDoneQTail(iop_base, asc_dvc->max_total_qng);
4078 AscPutVarFreeQHead(iop_base, 1);
4079 AscPutVarDoneQTail(iop_base, asc_dvc->max_total_qng);
4080 AscWriteLramByte(iop_base, ASCV_BUSY_QHEAD_B,
4081 (uchar)((int)asc_dvc->max_total_qng + 1));
4082 AscWriteLramByte(iop_base, ASCV_DISC1_QHEAD_B,
4083 (uchar)((int)asc_dvc->max_total_qng + 2));
4084 AscWriteLramByte(iop_base, (ushort)ASCV_TOTAL_READY_Q_B,
4085 asc_dvc->max_total_qng);
4086 AscWriteLramWord(iop_base, ASCV_ASCDVC_ERR_CODE_W, 0);
4087 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
4088 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, 0);
4089 AscWriteLramByte(iop_base, ASCV_SCSIBUSY_B, 0);
4090 AscWriteLramByte(iop_base, ASCV_WTM_FLAG_B, 0);
4091 AscPutQDoneInProgress(iop_base, 0);
4092 lram_addr = ASC_QADR_BEG;
4093 for (i = 0; i < 32; i++, lram_addr += 2) {
4094 AscWriteLramWord(iop_base, lram_addr, 0);
4098 static ushort AscInitMicroCodeVar(ASC_DVC_VAR *asc_dvc)
4105 struct asc_board *board = asc_dvc_to_board(asc_dvc);
4107 iop_base = asc_dvc->iop_base;
4109 for (i = 0; i <= ASC_MAX_TID; i++) {
4110 AscPutMCodeInitSDTRAtID(iop_base, i,
4111 asc_dvc->cfg->sdtr_period_offset[i]);
4114 AscInitQLinkVar(asc_dvc);
4115 AscWriteLramByte(iop_base, ASCV_DISC_ENABLE_B,
4116 asc_dvc->cfg->disc_enable);
4117 AscWriteLramByte(iop_base, ASCV_HOSTSCSI_ID_B,
4118 ASC_TID_TO_TARGET_ID(asc_dvc->cfg->chip_scsi_id));
4120 /* Ensure overrun buffer is aligned on an 8 byte boundary. */
4121 BUG_ON((unsigned long)asc_dvc->overrun_buf & 7);
4122 asc_dvc->overrun_dma = dma_map_single(board->dev, asc_dvc->overrun_buf,
4123 ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE);
4124 if (dma_mapping_error(board->dev, asc_dvc->overrun_dma)) {
4125 warn_code = -ENOMEM;
4128 phy_addr = cpu_to_le32(asc_dvc->overrun_dma);
4129 AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_PADDR_D,
4130 (uchar *)&phy_addr, 1);
4131 phy_size = cpu_to_le32(ASC_OVERRUN_BSIZE);
4132 AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_BSIZE_D,
4133 (uchar *)&phy_size, 1);
4135 asc_dvc->cfg->mcode_date =
4136 AscReadLramWord(iop_base, (ushort)ASCV_MC_DATE_W);
4137 asc_dvc->cfg->mcode_version =
4138 AscReadLramWord(iop_base, (ushort)ASCV_MC_VER_W);
4140 AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR);
4141 if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) {
4142 asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR;
4144 goto err_mcode_start;
4146 if (AscStartChip(iop_base) != 1) {
4147 asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP;
4149 goto err_mcode_start;
4155 dma_unmap_single(board->dev, asc_dvc->overrun_dma,
4156 ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE);
4158 asc_dvc->overrun_dma = 0;
4162 static ushort AscInitAsc1000Driver(ASC_DVC_VAR *asc_dvc)
4164 const struct firmware *fw;
4165 const char fwname[] = "advansys/mcode.bin";
4167 unsigned long chksum;
4171 iop_base = asc_dvc->iop_base;
4173 if ((asc_dvc->dvc_cntl & ASC_CNTL_RESET_SCSI) &&
4174 !(asc_dvc->init_state & ASC_INIT_RESET_SCSI_DONE)) {
4175 AscResetChipAndScsiBus(asc_dvc);
4176 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
4178 asc_dvc->init_state |= ASC_INIT_STATE_BEG_LOAD_MC;
4179 if (asc_dvc->err_code != 0)
4181 if (!AscFindSignature(asc_dvc->iop_base)) {
4182 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
4185 AscDisableInterrupt(iop_base);
4186 warn_code |= AscInitLram(asc_dvc);
4187 if (asc_dvc->err_code != 0)
4190 err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
4192 printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
4194 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
4198 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
4200 release_firmware(fw);
4201 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
4204 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
4205 (fw->data[1] << 8) | fw->data[0];
4206 ASC_DBG(1, "_asc_mcode_chksum 0x%lx\n", (ulong)chksum);
4207 if (AscLoadMicroCode(iop_base, 0, &fw->data[4],
4208 fw->size - 4) != chksum) {
4209 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
4210 release_firmware(fw);
4213 release_firmware(fw);
4214 warn_code |= AscInitMicroCodeVar(asc_dvc);
4215 if (!asc_dvc->overrun_dma)
4217 asc_dvc->init_state |= ASC_INIT_STATE_END_LOAD_MC;
4218 AscEnableInterrupt(iop_base);
4223 * Load the Microcode
4225 * Write the microcode image to RISC memory starting at address 0.
4227 * The microcode is stored compressed in the following format:
4229 * 254 word (508 byte) table indexed by byte code followed
4230 * by the following byte codes:
4233 * 00: Emit word 0 in table.
4234 * 01: Emit word 1 in table.
4236 * FD: Emit word 253 in table.
4239 * FE WW WW: (3 byte code) Word to emit is the next word WW WW.
4240 * FF BB WW WW: (4 byte code) Emit BB count times next word WW WW.
4242 * Returns 0 or an error if the checksum doesn't match
4244 static int AdvLoadMicrocode(AdvPortAddr iop_base, const unsigned char *buf,
4245 int size, int memsize, int chksum)
4247 int i, j, end, len = 0;
4250 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
4252 for (i = 253 * 2; i < size; i++) {
4253 if (buf[i] == 0xff) {
4254 unsigned short word = (buf[i + 3] << 8) | buf[i + 2];
4255 for (j = 0; j < buf[i + 1]; j++) {
4256 AdvWriteWordAutoIncLram(iop_base, word);
4260 } else if (buf[i] == 0xfe) {
4261 unsigned short word = (buf[i + 2] << 8) | buf[i + 1];
4262 AdvWriteWordAutoIncLram(iop_base, word);
4266 unsigned int off = buf[i] * 2;
4267 unsigned short word = (buf[off + 1] << 8) | buf[off];
4268 AdvWriteWordAutoIncLram(iop_base, word);
4275 while (len < memsize) {
4276 AdvWriteWordAutoIncLram(iop_base, 0);
4280 /* Verify the microcode checksum. */
4282 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
4284 for (len = 0; len < end; len += 2) {
4285 sum += AdvReadWordAutoIncLram(iop_base);
4289 return ASC_IERR_MCODE_CHKSUM;
4294 static void AdvBuildCarrierFreelist(struct adv_dvc_var *adv_dvc)
4296 off_t carr_offset = 0, next_offset;
4297 dma_addr_t carr_paddr;
4298 int carr_num = ADV_CARRIER_BUFSIZE / sizeof(ADV_CARR_T), i;
4300 for (i = 0; i < carr_num; i++) {
4301 carr_offset = i * sizeof(ADV_CARR_T);
4302 /* Get physical address of the carrier 'carrp'. */
4303 carr_paddr = adv_dvc->carrier_addr + carr_offset;
4305 adv_dvc->carrier[i].carr_pa = cpu_to_le32(carr_paddr);
4306 adv_dvc->carrier[i].carr_va = cpu_to_le32(carr_offset);
4307 adv_dvc->carrier[i].areq_vpa = 0;
4308 next_offset = carr_offset + sizeof(ADV_CARR_T);
4311 adv_dvc->carrier[i].next_vpa = cpu_to_le32(next_offset);
4314 * We cannot have a carrier with 'carr_va' of '0', as
4315 * a reference to this carrier would be interpreted as
4317 * So start at carrier 1 with the freelist.
4319 adv_dvc->carr_freelist = &adv_dvc->carrier[1];
4322 static ADV_CARR_T *adv_get_carrier(struct adv_dvc_var *adv_dvc, u32 offset)
4326 BUG_ON(offset > ADV_CARRIER_BUFSIZE);
4328 index = offset / sizeof(ADV_CARR_T);
4329 return &adv_dvc->carrier[index];
4332 static ADV_CARR_T *adv_get_next_carrier(struct adv_dvc_var *adv_dvc)
4334 ADV_CARR_T *carrp = adv_dvc->carr_freelist;
4335 u32 next_vpa = le32_to_cpu(carrp->next_vpa);
4337 if (next_vpa == 0 || next_vpa == ~0) {
4338 ASC_DBG(1, "invalid vpa offset 0x%x\n", next_vpa);
4342 adv_dvc->carr_freelist = adv_get_carrier(adv_dvc, next_vpa);
4344 * insert stopper carrier to terminate list
4346 carrp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
4352 * 'offset' is the index in the request pointer array
4354 static adv_req_t * adv_get_reqp(struct adv_dvc_var *adv_dvc, u32 offset)
4356 struct asc_board *boardp = adv_dvc->drv_ptr;
4358 BUG_ON(offset > adv_dvc->max_host_qng);
4359 return &boardp->adv_reqp[offset];
4363 * Send an idle command to the chip and wait for completion.
4365 * Command completion is polled for once per microsecond.
4367 * The function can be called from anywhere including an interrupt handler.
4368 * But the function is not re-entrant, so it uses the DvcEnter/LeaveCritical()
4369 * functions to prevent reentrancy.
4372 * ADV_TRUE - command completed successfully
4373 * ADV_FALSE - command failed
4374 * ADV_ERROR - command timed out
4377 AdvSendIdleCmd(ADV_DVC_VAR *asc_dvc,
4378 ushort idle_cmd, u32 idle_cmd_parameter)
4381 AdvPortAddr iop_base;
4383 iop_base = asc_dvc->iop_base;
4386 * Clear the idle command status which is set by the microcode
4387 * to a non-zero value to indicate when the command is completed.
4388 * The non-zero result is one of the IDLE_CMD_STATUS_* values
4390 AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS, (ushort)0);
4393 * Write the idle command value after the idle command parameter
4394 * has been written to avoid a race condition. If the order is not
4395 * followed, the microcode may process the idle command before the
4396 * parameters have been written to LRAM.
4398 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IDLE_CMD_PARAMETER,
4399 cpu_to_le32(idle_cmd_parameter));
4400 AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD, idle_cmd);
4403 * Tickle the RISC to tell it to process the idle command.
4405 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_B);
4406 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
4408 * Clear the tickle value. In the ASC-3550 the RISC flag
4409 * command 'clr_tickle_b' does not work unless the host
4412 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_NOP);
4415 /* Wait for up to 100 millisecond for the idle command to timeout. */
4416 for (i = 0; i < SCSI_WAIT_100_MSEC; i++) {
4417 /* Poll once each microsecond for command completion. */
4418 for (j = 0; j < SCSI_US_PER_MSEC; j++) {
4419 AdvReadWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS,
4427 BUG(); /* The idle command should never timeout. */
4432 * Reset SCSI Bus and purge all outstanding requests.
4435 * ADV_TRUE(1) - All requests are purged and SCSI Bus is reset.
4436 * ADV_FALSE(0) - Microcode command failed.
4437 * ADV_ERROR(-1) - Microcode command timed-out. Microcode or IC
4438 * may be hung which requires driver recovery.
4440 static int AdvResetSB(ADV_DVC_VAR *asc_dvc)
4445 * Send the SCSI Bus Reset idle start idle command which asserts
4446 * the SCSI Bus Reset signal.
4448 status = AdvSendIdleCmd(asc_dvc, (ushort)IDLE_CMD_SCSI_RESET_START, 0L);
4449 if (status != ADV_TRUE) {
4454 * Delay for the specified SCSI Bus Reset hold time.
4456 * The hold time delay is done on the host because the RISC has no
4457 * microsecond accurate timer.
4459 udelay(ASC_SCSI_RESET_HOLD_TIME_US);
4462 * Send the SCSI Bus Reset end idle command which de-asserts
4463 * the SCSI Bus Reset signal and purges any pending requests.
4465 status = AdvSendIdleCmd(asc_dvc, (ushort)IDLE_CMD_SCSI_RESET_END, 0L);
4466 if (status != ADV_TRUE) {
4470 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
4476 * Initialize the ASC-3550.
4478 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
4480 * For a non-fatal error return a warning code. If there are no warnings
4481 * then 0 is returned.
4483 * Needed after initialization for error recovery.
4485 static int AdvInitAsc3550Driver(ADV_DVC_VAR *asc_dvc)
4487 const struct firmware *fw;
4488 const char fwname[] = "advansys/3550.bin";
4489 AdvPortAddr iop_base;
4497 unsigned long chksum;
4500 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */
4501 ushort wdtr_able = 0, sdtr_able, tagqng_able;
4502 uchar max_cmd[ADV_MAX_TID + 1];
4504 /* If there is already an error, don't continue. */
4505 if (asc_dvc->err_code != 0)
4509 * The caller must set 'chip_type' to ADV_CHIP_ASC3550.
4511 if (asc_dvc->chip_type != ADV_CHIP_ASC3550) {
4512 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
4517 iop_base = asc_dvc->iop_base;
4520 * Save the RISC memory BIOS region before writing the microcode.
4521 * The BIOS may already be loaded and using its RISC LRAM region
4522 * so its region must be saved and restored.
4524 * Note: This code makes the assumption, which is currently true,
4525 * that a chip reset does not clear RISC LRAM.
4527 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
4528 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
4533 * Save current per TID negotiated values.
4535 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] == 0x55AA) {
4536 ushort bios_version, major, minor;
4539 bios_mem[(ASC_MC_BIOS_VERSION - ASC_MC_BIOSMEM) / 2];
4540 major = (bios_version >> 12) & 0xF;
4541 minor = (bios_version >> 8) & 0xF;
4542 if (major < 3 || (major == 3 && minor == 1)) {
4543 /* BIOS 3.1 and earlier location of 'wdtr_able' variable. */
4544 AdvReadWordLram(iop_base, 0x120, wdtr_able);
4546 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
4549 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
4550 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
4551 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
4552 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
4556 err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
4558 printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
4560 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
4564 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
4566 release_firmware(fw);
4567 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
4570 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
4571 (fw->data[1] << 8) | fw->data[0];
4572 asc_dvc->err_code = AdvLoadMicrocode(iop_base, &fw->data[4],
4573 fw->size - 4, ADV_3550_MEMSIZE,
4575 release_firmware(fw);
4576 if (asc_dvc->err_code)
4580 * Restore the RISC memory BIOS region.
4582 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
4583 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
4588 * Calculate and write the microcode code checksum to the microcode
4589 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
4591 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
4592 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
4594 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
4595 for (word = begin_addr; word < end_addr; word += 2) {
4596 code_sum += AdvReadWordAutoIncLram(iop_base);
4598 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
4601 * Read and save microcode version and date.
4603 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
4604 asc_dvc->cfg->mcode_date);
4605 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
4606 asc_dvc->cfg->mcode_version);
4609 * Set the chip type to indicate the ASC3550.
4611 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC3550);
4614 * If the PCI Configuration Command Register "Parity Error Response
4615 * Control" Bit was clear (0), then set the microcode variable
4616 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
4617 * to ignore DMA parity errors.
4619 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
4620 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
4621 word |= CONTROL_FLAG_IGNORE_PERR;
4622 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
4626 * For ASC-3550, setting the START_CTL_EMFU [3:2] bits sets a FIFO
4627 * threshold of 128 bytes. This register is only accessible to the host.
4629 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
4630 START_CTL_EMFU | READ_CMD_MRM);
4633 * Microcode operating variables for WDTR, SDTR, and command tag
4634 * queuing will be set in slave_configure() based on what a
4635 * device reports it is capable of in Inquiry byte 7.
4637 * If SCSI Bus Resets have been disabled, then directly set
4638 * SDTR and WDTR from the EEPROM configuration. This will allow
4639 * the BIOS and warm boot to work without a SCSI bus hang on
4640 * the Inquiry caused by host and target mismatched DTR values.
4641 * Without the SCSI Bus Reset, before an Inquiry a device can't
4642 * be assumed to be in Asynchronous, Narrow mode.
4644 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
4645 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
4646 asc_dvc->wdtr_able);
4647 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
4648 asc_dvc->sdtr_able);
4652 * Set microcode operating variables for SDTR_SPEED1, SDTR_SPEED2,
4653 * SDTR_SPEED3, and SDTR_SPEED4 based on the ULTRA EEPROM per TID
4654 * bitmask. These values determine the maximum SDTR speed negotiated
4657 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
4658 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
4659 * without determining here whether the device supports SDTR.
4661 * 4-bit speed SDTR speed name
4662 * =========== ===============
4663 * 0000b (0x0) SDTR disabled
4665 * 0010b (0x2) 10 Mhz
4666 * 0011b (0x3) 20 Mhz (Ultra)
4667 * 0100b (0x4) 40 Mhz (LVD/Ultra2)
4668 * 0101b (0x5) 80 Mhz (LVD2/Ultra3)
4669 * 0110b (0x6) Undefined
4671 * 1111b (0xF) Undefined
4674 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
4675 if (ADV_TID_TO_TIDMASK(tid) & asc_dvc->ultra_able) {
4676 /* Set Ultra speed for TID 'tid'. */
4677 word |= (0x3 << (4 * (tid % 4)));
4679 /* Set Fast speed for TID 'tid'. */
4680 word |= (0x2 << (4 * (tid % 4)));
4682 if (tid == 3) { /* Check if done with sdtr_speed1. */
4683 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, word);
4685 } else if (tid == 7) { /* Check if done with sdtr_speed2. */
4686 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, word);
4688 } else if (tid == 11) { /* Check if done with sdtr_speed3. */
4689 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, word);
4691 } else if (tid == 15) { /* Check if done with sdtr_speed4. */
4692 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, word);
4698 * Set microcode operating variable for the disconnect per TID bitmask.
4700 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
4701 asc_dvc->cfg->disc_enable);
4704 * Set SCSI_CFG0 Microcode Default Value.
4706 * The microcode will set the SCSI_CFG0 register using this value
4707 * after it is started below.
4709 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
4710 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
4711 asc_dvc->chip_scsi_id);
4714 * Determine SCSI_CFG1 Microcode Default Value.
4716 * The microcode will set the SCSI_CFG1 register using this value
4717 * after it is started below.
4720 /* Read current SCSI_CFG1 Register value. */
4721 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
4724 * If all three connectors are in use, return an error.
4726 if ((scsi_cfg1 & CABLE_ILLEGAL_A) == 0 ||
4727 (scsi_cfg1 & CABLE_ILLEGAL_B) == 0) {
4728 asc_dvc->err_code |= ASC_IERR_ILLEGAL_CONNECTION;
4733 * If the internal narrow cable is reversed all of the SCSI_CTRL
4734 * register signals will be set. Check for and return an error if
4735 * this condition is found.
4737 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
4738 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
4743 * If this is a differential board and a single-ended device
4744 * is attached to one of the connectors, return an error.
4746 if ((scsi_cfg1 & DIFF_MODE) && (scsi_cfg1 & DIFF_SENSE) == 0) {
4747 asc_dvc->err_code |= ASC_IERR_SINGLE_END_DEVICE;
4752 * If automatic termination control is enabled, then set the
4753 * termination value based on a table listed in a_condor.h.
4755 * If manual termination was specified with an EEPROM setting
4756 * then 'termination' was set-up in AdvInitFrom3550EEPROM() and
4757 * is ready to be 'ored' into SCSI_CFG1.
4759 if (asc_dvc->cfg->termination == 0) {
4761 * The software always controls termination by setting TERM_CTL_SEL.
4762 * If TERM_CTL_SEL were set to 0, the hardware would set termination.
4764 asc_dvc->cfg->termination |= TERM_CTL_SEL;
4766 switch (scsi_cfg1 & CABLE_DETECT) {
4767 /* TERM_CTL_H: on, TERM_CTL_L: on */
4774 asc_dvc->cfg->termination |= (TERM_CTL_H | TERM_CTL_L);
4777 /* TERM_CTL_H: on, TERM_CTL_L: off */
4783 asc_dvc->cfg->termination |= TERM_CTL_H;
4786 /* TERM_CTL_H: off, TERM_CTL_L: off */
4794 * Clear any set TERM_CTL_H and TERM_CTL_L bits.
4796 scsi_cfg1 &= ~TERM_CTL;
4799 * Invert the TERM_CTL_H and TERM_CTL_L bits and then
4800 * set 'scsi_cfg1'. The TERM_POL bit does not need to be
4801 * referenced, because the hardware internally inverts
4802 * the Termination High and Low bits if TERM_POL is set.
4804 scsi_cfg1 |= (TERM_CTL_SEL | (~asc_dvc->cfg->termination & TERM_CTL));
4807 * Set SCSI_CFG1 Microcode Default Value
4809 * Set filter value and possibly modified termination control
4810 * bits in the Microcode SCSI_CFG1 Register Value.
4812 * The microcode will set the SCSI_CFG1 register using this value
4813 * after it is started below.
4815 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1,
4816 FLTR_DISABLE | scsi_cfg1);
4819 * Set MEM_CFG Microcode Default Value
4821 * The microcode will set the MEM_CFG register using this value
4822 * after it is started below.
4824 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
4827 * ASC-3550 has 8KB internal memory.
4829 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
4830 BIOS_EN | RAM_SZ_8KB);
4833 * Set SEL_MASK Microcode Default Value
4835 * The microcode will set the SEL_MASK register using this value
4836 * after it is started below.
4838 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
4839 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
4841 AdvBuildCarrierFreelist(asc_dvc);
4844 * Set-up the Host->RISC Initiator Command Queue (ICQ).
4847 asc_dvc->icq_sp = adv_get_next_carrier(asc_dvc);
4848 if (!asc_dvc->icq_sp) {
4849 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
4854 * Set RISC ICQ physical address start value.
4856 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
4859 * Set-up the RISC->Host Initiator Response Queue (IRQ).
4861 asc_dvc->irq_sp = adv_get_next_carrier(asc_dvc);
4862 if (!asc_dvc->irq_sp) {
4863 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
4868 * Set RISC IRQ physical address start value.
4870 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
4871 asc_dvc->carr_pending_cnt = 0;
4873 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
4874 (ADV_INTR_ENABLE_HOST_INTR |
4875 ADV_INTR_ENABLE_GLOBAL_INTR));
4877 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
4878 AdvWriteWordRegister(iop_base, IOPW_PC, word);
4880 /* finally, finally, gentlemen, start your engine */
4881 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
4884 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
4885 * Resets should be performed. The RISC has to be running
4886 * to issue a SCSI Bus Reset.
4888 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
4890 * If the BIOS Signature is present in memory, restore the
4891 * BIOS Handshake Configuration Table and do not perform
4894 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
4897 * Restore per TID negotiated values.
4899 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
4900 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
4901 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
4903 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
4904 AdvWriteByteLram(iop_base,
4905 ASC_MC_NUMBER_OF_MAX_CMD + tid,
4909 if (AdvResetSB(asc_dvc) != ADV_TRUE) {
4910 warn_code = ASC_WARN_BUSRESET_ERROR;
4919 * Initialize the ASC-38C0800.
4921 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
4923 * For a non-fatal error return a warning code. If there are no warnings
4924 * then 0 is returned.
4926 * Needed after initialization for error recovery.
4928 static int AdvInitAsc38C0800Driver(ADV_DVC_VAR *asc_dvc)
4930 const struct firmware *fw;
4931 const char fwname[] = "advansys/38C0800.bin";
4932 AdvPortAddr iop_base;
4940 unsigned long chksum;
4944 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */
4945 ushort wdtr_able, sdtr_able, tagqng_able;
4946 uchar max_cmd[ADV_MAX_TID + 1];
4948 /* If there is already an error, don't continue. */
4949 if (asc_dvc->err_code != 0)
4953 * The caller must set 'chip_type' to ADV_CHIP_ASC38C0800.
4955 if (asc_dvc->chip_type != ADV_CHIP_ASC38C0800) {
4956 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
4961 iop_base = asc_dvc->iop_base;
4964 * Save the RISC memory BIOS region before writing the microcode.
4965 * The BIOS may already be loaded and using its RISC LRAM region
4966 * so its region must be saved and restored.
4968 * Note: This code makes the assumption, which is currently true,
4969 * that a chip reset does not clear RISC LRAM.
4971 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
4972 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
4977 * Save current per TID negotiated values.
4979 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
4980 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
4981 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
4982 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
4983 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
4988 * RAM BIST (RAM Built-In Self Test)
4990 * Address : I/O base + offset 0x38h register (byte).
4991 * Function: Bit 7-6(RW) : RAM mode
4992 * Normal Mode : 0x00
4993 * Pre-test Mode : 0x40
4994 * RAM Test Mode : 0x80
4996 * Bit 4(RO) : Done bit
4997 * Bit 3-0(RO) : Status
4999 * Int_RAM Error : 0x04
5004 * Note: RAM BIST code should be put right here, before loading the
5005 * microcode and after saving the RISC memory BIOS region.
5011 * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds.
5012 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return
5013 * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset
5014 * to NORMAL_MODE, return an error too.
5016 for (i = 0; i < 2; i++) {
5017 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE);
5018 mdelay(10); /* Wait for 10ms before reading back. */
5019 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
5020 if ((byte & RAM_TEST_DONE) == 0
5021 || (byte & 0x0F) != PRE_TEST_VALUE) {
5022 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
5026 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
5027 mdelay(10); /* Wait for 10ms before reading back. */
5028 if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST)
5030 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
5036 * LRAM Test - It takes about 1.5 ms to run through the test.
5038 * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds.
5039 * If Done bit not set or Status not 0, save register byte, set the
5040 * err_code, and return an error.
5042 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE);
5043 mdelay(10); /* Wait for 10ms before checking status. */
5045 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
5046 if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) {
5047 /* Get here if Done bit not set or Status not 0. */
5048 asc_dvc->bist_err_code = byte; /* for BIOS display message */
5049 asc_dvc->err_code = ASC_IERR_BIST_RAM_TEST;
5053 /* We need to reset back to normal mode after LRAM test passes. */
5054 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
5056 err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
5058 printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
5060 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
5064 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
5066 release_firmware(fw);
5067 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
5070 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
5071 (fw->data[1] << 8) | fw->data[0];
5072 asc_dvc->err_code = AdvLoadMicrocode(iop_base, &fw->data[4],
5073 fw->size - 4, ADV_38C0800_MEMSIZE,
5075 release_firmware(fw);
5076 if (asc_dvc->err_code)
5080 * Restore the RISC memory BIOS region.
5082 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
5083 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
5088 * Calculate and write the microcode code checksum to the microcode
5089 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
5091 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
5092 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
5094 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
5095 for (word = begin_addr; word < end_addr; word += 2) {
5096 code_sum += AdvReadWordAutoIncLram(iop_base);
5098 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
5101 * Read microcode version and date.
5103 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
5104 asc_dvc->cfg->mcode_date);
5105 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
5106 asc_dvc->cfg->mcode_version);
5109 * Set the chip type to indicate the ASC38C0800.
5111 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C0800);
5114 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
5115 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
5116 * cable detection and then we are able to read C_DET[3:0].
5118 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
5119 * Microcode Default Value' section below.
5121 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
5122 AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1,
5123 scsi_cfg1 | DIS_TERM_DRV);
5126 * If the PCI Configuration Command Register "Parity Error Response
5127 * Control" Bit was clear (0), then set the microcode variable
5128 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
5129 * to ignore DMA parity errors.
5131 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
5132 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5133 word |= CONTROL_FLAG_IGNORE_PERR;
5134 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5138 * For ASC-38C0800, set FIFO_THRESH_80B [6:4] bits and START_CTL_TH [3:2]
5139 * bits for the default FIFO threshold.
5141 * Note: ASC-38C0800 FIFO threshold has been changed to 256 bytes.
5143 * For DMA Errata #4 set the BC_THRESH_ENB bit.
5145 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
5146 BC_THRESH_ENB | FIFO_THRESH_80B | START_CTL_TH |
5150 * Microcode operating variables for WDTR, SDTR, and command tag
5151 * queuing will be set in slave_configure() based on what a
5152 * device reports it is capable of in Inquiry byte 7.
5154 * If SCSI Bus Resets have been disabled, then directly set
5155 * SDTR and WDTR from the EEPROM configuration. This will allow
5156 * the BIOS and warm boot to work without a SCSI bus hang on
5157 * the Inquiry caused by host and target mismatched DTR values.
5158 * Without the SCSI Bus Reset, before an Inquiry a device can't
5159 * be assumed to be in Asynchronous, Narrow mode.
5161 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
5162 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
5163 asc_dvc->wdtr_able);
5164 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
5165 asc_dvc->sdtr_able);
5169 * Set microcode operating variables for DISC and SDTR_SPEED1,
5170 * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM
5171 * configuration values.
5173 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
5174 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
5175 * without determining here whether the device supports SDTR.
5177 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
5178 asc_dvc->cfg->disc_enable);
5179 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1);
5180 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2);
5181 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3);
5182 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4);
5185 * Set SCSI_CFG0 Microcode Default Value.
5187 * The microcode will set the SCSI_CFG0 register using this value
5188 * after it is started below.
5190 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
5191 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
5192 asc_dvc->chip_scsi_id);
5195 * Determine SCSI_CFG1 Microcode Default Value.
5197 * The microcode will set the SCSI_CFG1 register using this value
5198 * after it is started below.
5201 /* Read current SCSI_CFG1 Register value. */
5202 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
5205 * If the internal narrow cable is reversed all of the SCSI_CTRL
5206 * register signals will be set. Check for and return an error if
5207 * this condition is found.
5209 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
5210 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
5215 * All kind of combinations of devices attached to one of four
5216 * connectors are acceptable except HVD device attached. For example,
5217 * LVD device can be attached to SE connector while SE device attached
5218 * to LVD connector. If LVD device attached to SE connector, it only
5219 * runs up to Ultra speed.
5221 * If an HVD device is attached to one of LVD connectors, return an
5222 * error. However, there is no way to detect HVD device attached to
5225 if (scsi_cfg1 & HVD) {
5226 asc_dvc->err_code = ASC_IERR_HVD_DEVICE;
5231 * If either SE or LVD automatic termination control is enabled, then
5232 * set the termination value based on a table listed in a_condor.h.
5234 * If manual termination was specified with an EEPROM setting then
5235 * 'termination' was set-up in AdvInitFrom38C0800EEPROM() and is ready
5236 * to be 'ored' into SCSI_CFG1.
5238 if ((asc_dvc->cfg->termination & TERM_SE) == 0) {
5239 /* SE automatic termination control is enabled. */
5240 switch (scsi_cfg1 & C_DET_SE) {
5241 /* TERM_SE_HI: on, TERM_SE_LO: on */
5245 asc_dvc->cfg->termination |= TERM_SE;
5248 /* TERM_SE_HI: on, TERM_SE_LO: off */
5250 asc_dvc->cfg->termination |= TERM_SE_HI;
5255 if ((asc_dvc->cfg->termination & TERM_LVD) == 0) {
5256 /* LVD automatic termination control is enabled. */
5257 switch (scsi_cfg1 & C_DET_LVD) {
5258 /* TERM_LVD_HI: on, TERM_LVD_LO: on */
5262 asc_dvc->cfg->termination |= TERM_LVD;
5265 /* TERM_LVD_HI: off, TERM_LVD_LO: off */
5272 * Clear any set TERM_SE and TERM_LVD bits.
5274 scsi_cfg1 &= (~TERM_SE & ~TERM_LVD);
5277 * Invert the TERM_SE and TERM_LVD bits and then set 'scsi_cfg1'.
5279 scsi_cfg1 |= (~asc_dvc->cfg->termination & 0xF0);
5282 * Clear BIG_ENDIAN, DIS_TERM_DRV, Terminator Polarity and HVD/LVD/SE
5283 * bits and set possibly modified termination control bits in the
5284 * Microcode SCSI_CFG1 Register Value.
5286 scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL & ~HVD_LVD_SE);
5289 * Set SCSI_CFG1 Microcode Default Value
5291 * Set possibly modified termination control and reset DIS_TERM_DRV
5292 * bits in the Microcode SCSI_CFG1 Register Value.
5294 * The microcode will set the SCSI_CFG1 register using this value
5295 * after it is started below.
5297 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
5300 * Set MEM_CFG Microcode Default Value
5302 * The microcode will set the MEM_CFG register using this value
5303 * after it is started below.
5305 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
5308 * ASC-38C0800 has 16KB internal memory.
5310 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
5311 BIOS_EN | RAM_SZ_16KB);
5314 * Set SEL_MASK Microcode Default Value
5316 * The microcode will set the SEL_MASK register using this value
5317 * after it is started below.
5319 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
5320 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
5322 AdvBuildCarrierFreelist(asc_dvc);
5325 * Set-up the Host->RISC Initiator Command Queue (ICQ).
5328 asc_dvc->icq_sp = adv_get_next_carrier(asc_dvc);
5329 if (!asc_dvc->icq_sp) {
5330 ASC_DBG(0, "Failed to get ICQ carrier\n");
5331 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
5336 * Set RISC ICQ physical address start value.
5337 * carr_pa is LE, must be native before write
5339 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
5342 * Set-up the RISC->Host Initiator Response Queue (IRQ).
5344 asc_dvc->irq_sp = adv_get_next_carrier(asc_dvc);
5345 if (!asc_dvc->irq_sp) {
5346 ASC_DBG(0, "Failed to get IRQ carrier\n");
5347 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
5352 * Set RISC IRQ physical address start value.
5354 * carr_pa is LE, must be native before write *
5356 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
5357 asc_dvc->carr_pending_cnt = 0;
5359 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
5360 (ADV_INTR_ENABLE_HOST_INTR |
5361 ADV_INTR_ENABLE_GLOBAL_INTR));
5363 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
5364 AdvWriteWordRegister(iop_base, IOPW_PC, word);
5366 /* finally, finally, gentlemen, start your engine */
5367 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
5370 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
5371 * Resets should be performed. The RISC has to be running
5372 * to issue a SCSI Bus Reset.
5374 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
5376 * If the BIOS Signature is present in memory, restore the
5377 * BIOS Handshake Configuration Table and do not perform
5380 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
5383 * Restore per TID negotiated values.
5385 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5386 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5387 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
5389 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
5390 AdvWriteByteLram(iop_base,
5391 ASC_MC_NUMBER_OF_MAX_CMD + tid,
5395 if (AdvResetSB(asc_dvc) != ADV_TRUE) {
5396 warn_code = ASC_WARN_BUSRESET_ERROR;
5405 * Initialize the ASC-38C1600.
5407 * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR.
5409 * For a non-fatal error return a warning code. If there are no warnings
5410 * then 0 is returned.
5412 * Needed after initialization for error recovery.
5414 static int AdvInitAsc38C1600Driver(ADV_DVC_VAR *asc_dvc)
5416 const struct firmware *fw;
5417 const char fwname[] = "advansys/38C1600.bin";
5418 AdvPortAddr iop_base;
5426 unsigned long chksum;
5430 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */
5431 ushort wdtr_able, sdtr_able, ppr_able, tagqng_able;
5432 uchar max_cmd[ASC_MAX_TID + 1];
5434 /* If there is already an error, don't continue. */
5435 if (asc_dvc->err_code != 0) {
5440 * The caller must set 'chip_type' to ADV_CHIP_ASC38C1600.
5442 if (asc_dvc->chip_type != ADV_CHIP_ASC38C1600) {
5443 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
5448 iop_base = asc_dvc->iop_base;
5451 * Save the RISC memory BIOS region before writing the microcode.
5452 * The BIOS may already be loaded and using its RISC LRAM region
5453 * so its region must be saved and restored.
5455 * Note: This code makes the assumption, which is currently true,
5456 * that a chip reset does not clear RISC LRAM.
5458 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
5459 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
5464 * Save current per TID negotiated values.
5466 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5467 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5468 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
5469 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
5470 for (tid = 0; tid <= ASC_MAX_TID; tid++) {
5471 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
5476 * RAM BIST (Built-In Self Test)
5478 * Address : I/O base + offset 0x38h register (byte).
5479 * Function: Bit 7-6(RW) : RAM mode
5480 * Normal Mode : 0x00
5481 * Pre-test Mode : 0x40
5482 * RAM Test Mode : 0x80
5484 * Bit 4(RO) : Done bit
5485 * Bit 3-0(RO) : Status
5487 * Int_RAM Error : 0x04
5492 * Note: RAM BIST code should be put right here, before loading the
5493 * microcode and after saving the RISC memory BIOS region.
5499 * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds.
5500 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return
5501 * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset
5502 * to NORMAL_MODE, return an error too.
5504 for (i = 0; i < 2; i++) {
5505 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE);
5506 mdelay(10); /* Wait for 10ms before reading back. */
5507 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
5508 if ((byte & RAM_TEST_DONE) == 0
5509 || (byte & 0x0F) != PRE_TEST_VALUE) {
5510 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
5514 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
5515 mdelay(10); /* Wait for 10ms before reading back. */
5516 if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST)
5518 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
5524 * LRAM Test - It takes about 1.5 ms to run through the test.
5526 * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds.
5527 * If Done bit not set or Status not 0, save register byte, set the
5528 * err_code, and return an error.
5530 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE);
5531 mdelay(10); /* Wait for 10ms before checking status. */
5533 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
5534 if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) {
5535 /* Get here if Done bit not set or Status not 0. */
5536 asc_dvc->bist_err_code = byte; /* for BIOS display message */
5537 asc_dvc->err_code = ASC_IERR_BIST_RAM_TEST;
5541 /* We need to reset back to normal mode after LRAM test passes. */
5542 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
5544 err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
5546 printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
5548 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
5552 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
5554 release_firmware(fw);
5555 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
5558 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
5559 (fw->data[1] << 8) | fw->data[0];
5560 asc_dvc->err_code = AdvLoadMicrocode(iop_base, &fw->data[4],
5561 fw->size - 4, ADV_38C1600_MEMSIZE,
5563 release_firmware(fw);
5564 if (asc_dvc->err_code)
5568 * Restore the RISC memory BIOS region.
5570 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
5571 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
5576 * Calculate and write the microcode code checksum to the microcode
5577 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
5579 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
5580 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
5582 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
5583 for (word = begin_addr; word < end_addr; word += 2) {
5584 code_sum += AdvReadWordAutoIncLram(iop_base);
5586 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
5589 * Read microcode version and date.
5591 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
5592 asc_dvc->cfg->mcode_date);
5593 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
5594 asc_dvc->cfg->mcode_version);
5597 * Set the chip type to indicate the ASC38C1600.
5599 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C1600);
5602 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
5603 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
5604 * cable detection and then we are able to read C_DET[3:0].
5606 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
5607 * Microcode Default Value' section below.
5609 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
5610 AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1,
5611 scsi_cfg1 | DIS_TERM_DRV);
5614 * If the PCI Configuration Command Register "Parity Error Response
5615 * Control" Bit was clear (0), then set the microcode variable
5616 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
5617 * to ignore DMA parity errors.
5619 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
5620 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5621 word |= CONTROL_FLAG_IGNORE_PERR;
5622 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5626 * If the BIOS control flag AIPP (Asynchronous Information
5627 * Phase Protection) disable bit is not set, then set the firmware
5628 * 'control_flag' CONTROL_FLAG_ENABLE_AIPP bit to enable
5629 * AIPP checking and encoding.
5631 if ((asc_dvc->bios_ctrl & BIOS_CTRL_AIPP_DIS) == 0) {
5632 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5633 word |= CONTROL_FLAG_ENABLE_AIPP;
5634 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5638 * For ASC-38C1600 use DMA_CFG0 default values: FIFO_THRESH_80B [6:4],
5639 * and START_CTL_TH [3:2].
5641 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
5642 FIFO_THRESH_80B | START_CTL_TH | READ_CMD_MRM);
5645 * Microcode operating variables for WDTR, SDTR, and command tag
5646 * queuing will be set in slave_configure() based on what a
5647 * device reports it is capable of in Inquiry byte 7.
5649 * If SCSI Bus Resets have been disabled, then directly set
5650 * SDTR and WDTR from the EEPROM configuration. This will allow
5651 * the BIOS and warm boot to work without a SCSI bus hang on
5652 * the Inquiry caused by host and target mismatched DTR values.
5653 * Without the SCSI Bus Reset, before an Inquiry a device can't
5654 * be assumed to be in Asynchronous, Narrow mode.
5656 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
5657 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
5658 asc_dvc->wdtr_able);
5659 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
5660 asc_dvc->sdtr_able);
5664 * Set microcode operating variables for DISC and SDTR_SPEED1,
5665 * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM
5666 * configuration values.
5668 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
5669 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
5670 * without determining here whether the device supports SDTR.
5672 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
5673 asc_dvc->cfg->disc_enable);
5674 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1);
5675 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2);
5676 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3);
5677 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4);
5680 * Set SCSI_CFG0 Microcode Default Value.
5682 * The microcode will set the SCSI_CFG0 register using this value
5683 * after it is started below.
5685 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
5686 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
5687 asc_dvc->chip_scsi_id);
5690 * Calculate SCSI_CFG1 Microcode Default Value.
5692 * The microcode will set the SCSI_CFG1 register using this value
5693 * after it is started below.
5695 * Each ASC-38C1600 function has only two cable detect bits.
5696 * The bus mode override bits are in IOPB_SOFT_OVER_WR.
5698 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
5701 * If the cable is reversed all of the SCSI_CTRL register signals
5702 * will be set. Check for and return an error if this condition is
5705 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
5706 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
5711 * Each ASC-38C1600 function has two connectors. Only an HVD device
5712 * can not be connected to either connector. An LVD device or SE device
5713 * may be connected to either connecor. If an SE device is connected,
5714 * then at most Ultra speed (20 Mhz) can be used on both connectors.
5716 * If an HVD device is attached, return an error.
5718 if (scsi_cfg1 & HVD) {
5719 asc_dvc->err_code |= ASC_IERR_HVD_DEVICE;
5724 * Each function in the ASC-38C1600 uses only the SE cable detect and
5725 * termination because there are two connectors for each function. Each
5726 * function may use either LVD or SE mode. Corresponding the SE automatic
5727 * termination control EEPROM bits are used for each function. Each
5728 * function has its own EEPROM. If SE automatic control is enabled for
5729 * the function, then set the termination value based on a table listed
5732 * If manual termination is specified in the EEPROM for the function,
5733 * then 'termination' was set-up in AscInitFrom38C1600EEPROM() and is
5734 * ready to be 'ored' into SCSI_CFG1.
5736 if ((asc_dvc->cfg->termination & TERM_SE) == 0) {
5737 struct pci_dev *pdev = adv_dvc_to_pdev(asc_dvc);
5738 /* SE automatic termination control is enabled. */
5739 switch (scsi_cfg1 & C_DET_SE) {
5740 /* TERM_SE_HI: on, TERM_SE_LO: on */
5744 asc_dvc->cfg->termination |= TERM_SE;
5748 if (PCI_FUNC(pdev->devfn) == 0) {
5749 /* Function 0 - TERM_SE_HI: off, TERM_SE_LO: off */
5751 /* Function 1 - TERM_SE_HI: on, TERM_SE_LO: off */
5752 asc_dvc->cfg->termination |= TERM_SE_HI;
5759 * Clear any set TERM_SE bits.
5761 scsi_cfg1 &= ~TERM_SE;
5764 * Invert the TERM_SE bits and then set 'scsi_cfg1'.
5766 scsi_cfg1 |= (~asc_dvc->cfg->termination & TERM_SE);
5769 * Clear Big Endian and Terminator Polarity bits and set possibly
5770 * modified termination control bits in the Microcode SCSI_CFG1
5773 * Big Endian bit is not used even on big endian machines.
5775 scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL);
5778 * Set SCSI_CFG1 Microcode Default Value
5780 * Set possibly modified termination control bits in the Microcode
5781 * SCSI_CFG1 Register Value.
5783 * The microcode will set the SCSI_CFG1 register using this value
5784 * after it is started below.
5786 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
5789 * Set MEM_CFG Microcode Default Value
5791 * The microcode will set the MEM_CFG register using this value
5792 * after it is started below.
5794 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
5797 * ASC-38C1600 has 32KB internal memory.
5799 * XXX - Since ASC38C1600 Rev.3 has a Local RAM failure issue, we come
5800 * out a special 16K Adv Library and Microcode version. After the issue
5801 * resolved, we should turn back to the 32K support. Both a_condor.h and
5802 * mcode.sas files also need to be updated.
5804 * AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
5805 * BIOS_EN | RAM_SZ_32KB);
5807 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
5808 BIOS_EN | RAM_SZ_16KB);
5811 * Set SEL_MASK Microcode Default Value
5813 * The microcode will set the SEL_MASK register using this value
5814 * after it is started below.
5816 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
5817 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
5819 AdvBuildCarrierFreelist(asc_dvc);
5822 * Set-up the Host->RISC Initiator Command Queue (ICQ).
5824 asc_dvc->icq_sp = adv_get_next_carrier(asc_dvc);
5825 if (!asc_dvc->icq_sp) {
5826 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
5831 * Set RISC ICQ physical address start value. Initialize the
5832 * COMMA register to the same value otherwise the RISC will
5833 * prematurely detect a command is available.
5835 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
5836 AdvWriteDWordRegister(iop_base, IOPDW_COMMA,
5837 le32_to_cpu(asc_dvc->icq_sp->carr_pa));
5840 * Set-up the RISC->Host Initiator Response Queue (IRQ).
5842 asc_dvc->irq_sp = adv_get_next_carrier(asc_dvc);
5843 if (!asc_dvc->irq_sp) {
5844 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
5849 * Set RISC IRQ physical address start value.
5851 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
5852 asc_dvc->carr_pending_cnt = 0;
5854 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
5855 (ADV_INTR_ENABLE_HOST_INTR |
5856 ADV_INTR_ENABLE_GLOBAL_INTR));
5857 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
5858 AdvWriteWordRegister(iop_base, IOPW_PC, word);
5860 /* finally, finally, gentlemen, start your engine */
5861 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
5864 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
5865 * Resets should be performed. The RISC has to be running
5866 * to issue a SCSI Bus Reset.
5868 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
5870 * If the BIOS Signature is present in memory, restore the
5871 * per TID microcode operating variables.
5873 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
5876 * Restore per TID negotiated values.
5878 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5879 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5880 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
5881 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
5883 for (tid = 0; tid <= ASC_MAX_TID; tid++) {
5884 AdvWriteByteLram(iop_base,
5885 ASC_MC_NUMBER_OF_MAX_CMD + tid,
5889 if (AdvResetSB(asc_dvc) != ADV_TRUE) {
5890 warn_code = ASC_WARN_BUSRESET_ERROR;
5899 * Reset chip and SCSI Bus.
5902 * ADV_TRUE(1) - Chip re-initialization and SCSI Bus Reset successful.
5903 * ADV_FALSE(0) - Chip re-initialization and SCSI Bus Reset failure.
5905 static int AdvResetChipAndSB(ADV_DVC_VAR *asc_dvc)
5908 ushort wdtr_able, sdtr_able, tagqng_able;
5909 ushort ppr_able = 0;
5910 uchar tid, max_cmd[ADV_MAX_TID + 1];
5911 AdvPortAddr iop_base;
5914 iop_base = asc_dvc->iop_base;
5917 * Save current per TID negotiated values.
5919 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5920 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5921 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
5922 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
5924 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
5925 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
5926 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
5931 * Force the AdvInitAsc3550/38C0800Driver() function to
5932 * perform a SCSI Bus Reset by clearing the BIOS signature word.
5933 * The initialization functions assumes a SCSI Bus Reset is not
5934 * needed if the BIOS signature word is present.
5936 AdvReadWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig);
5937 AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, 0);
5940 * Stop chip and reset it.
5942 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_STOP);
5943 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG, ADV_CTRL_REG_CMD_RESET);
5945 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
5946 ADV_CTRL_REG_CMD_WR_IO_REG);
5949 * Reset Adv Library error code, if any, and try
5950 * re-initializing the chip.
5952 asc_dvc->err_code = 0;
5953 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
5954 status = AdvInitAsc38C1600Driver(asc_dvc);
5955 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
5956 status = AdvInitAsc38C0800Driver(asc_dvc);
5958 status = AdvInitAsc3550Driver(asc_dvc);
5961 /* Translate initialization return value to status value. */
5969 * Restore the BIOS signature word.
5971 AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig);
5974 * Restore per TID negotiated values.
5976 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5977 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5978 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
5979 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
5981 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
5982 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
5983 AdvWriteByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
5991 * adv_async_callback() - Adv Library asynchronous event callback function.
5993 static void adv_async_callback(ADV_DVC_VAR *adv_dvc_varp, uchar code)
5996 case ADV_ASYNC_SCSI_BUS_RESET_DET:
5998 * The firmware detected a SCSI Bus reset.
6000 ASC_DBG(0, "ADV_ASYNC_SCSI_BUS_RESET_DET\n");
6003 case ADV_ASYNC_RDMA_FAILURE:
6005 * Handle RDMA failure by resetting the SCSI Bus and
6006 * possibly the chip if it is unresponsive. Log the error
6007 * with a unique code.
6009 ASC_DBG(0, "ADV_ASYNC_RDMA_FAILURE\n");
6010 AdvResetChipAndSB(adv_dvc_varp);
6013 case ADV_HOST_SCSI_BUS_RESET:
6015 * Host generated SCSI bus reset occurred.
6017 ASC_DBG(0, "ADV_HOST_SCSI_BUS_RESET\n");
6021 ASC_DBG(0, "unknown code 0x%x\n", code);
6027 * adv_isr_callback() - Second Level Interrupt Handler called by AdvISR().
6029 * Callback function for the Wide SCSI Adv Library.
6031 static void adv_isr_callback(ADV_DVC_VAR *adv_dvc_varp, ADV_SCSI_REQ_Q *scsiqp)
6033 struct asc_board *boardp = adv_dvc_varp->drv_ptr;
6036 adv_sgblk_t *sgblkp;
6037 struct scsi_cmnd *scp;
6039 dma_addr_t sense_addr;
6041 ASC_DBG(1, "adv_dvc_varp 0x%p, scsiqp 0x%p\n",
6042 adv_dvc_varp, scsiqp);
6043 ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp);
6046 * Get the adv_req_t structure for the command that has been
6047 * completed. The adv_req_t structure actually contains the
6048 * completed ADV_SCSI_REQ_Q structure.
6050 srb_tag = le32_to_cpu(scsiqp->srb_tag);
6051 scp = scsi_host_find_tag(boardp->shost, scsiqp->srb_tag);
6053 ASC_DBG(1, "scp 0x%p\n", scp);
6056 ("adv_isr_callback: scp is NULL; adv_req_t dropped.\n");
6059 ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len);
6061 reqp = (adv_req_t *)scp->host_scribble;
6062 ASC_DBG(1, "reqp 0x%lx\n", (ulong)reqp);
6064 ASC_PRINT("adv_isr_callback: reqp is NULL\n");
6068 * Remove backreferences to avoid duplicate
6069 * command completions.
6071 scp->host_scribble = NULL;
6074 ASC_STATS(boardp->shost, callback);
6075 ASC_DBG(1, "shost 0x%p\n", boardp->shost);
6077 sense_addr = le32_to_cpu(scsiqp->sense_addr);
6078 dma_unmap_single(boardp->dev, sense_addr,
6079 SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
6082 * 'done_status' contains the command's ending status.
6084 switch (scsiqp->done_status) {
6086 ASC_DBG(2, "QD_NO_ERROR\n");
6090 * Check for an underrun condition.
6092 * If there was no error and an underrun condition, then
6093 * then return the number of underrun bytes.
6095 resid_cnt = le32_to_cpu(scsiqp->data_cnt);
6096 if (scsi_bufflen(scp) != 0 && resid_cnt != 0 &&
6097 resid_cnt <= scsi_bufflen(scp)) {
6098 ASC_DBG(1, "underrun condition %lu bytes\n",
6100 scsi_set_resid(scp, resid_cnt);
6105 ASC_DBG(2, "QD_WITH_ERROR\n");
6106 switch (scsiqp->host_status) {
6107 case QHSTA_NO_ERROR:
6108 if (scsiqp->scsi_status == SAM_STAT_CHECK_CONDITION) {
6109 ASC_DBG(2, "SAM_STAT_CHECK_CONDITION\n");
6110 ASC_DBG_PRT_SENSE(2, scp->sense_buffer,
6111 SCSI_SENSE_BUFFERSIZE);
6113 * Note: The 'status_byte()' macro used by
6114 * target drivers defined in scsi.h shifts the
6115 * status byte returned by host drivers right
6116 * by 1 bit. This is why target drivers also
6117 * use right shifted status byte definitions.
6118 * For instance target drivers use
6119 * CHECK_CONDITION, defined to 0x1, instead of
6120 * the SCSI defined check condition value of
6121 * 0x2. Host drivers are supposed to return
6122 * the status byte as it is defined by SCSI.
6124 scp->result = DRIVER_BYTE(DRIVER_SENSE) |
6125 STATUS_BYTE(scsiqp->scsi_status);
6127 scp->result = STATUS_BYTE(scsiqp->scsi_status);
6132 /* Some other QHSTA error occurred. */
6133 ASC_DBG(1, "host_status 0x%x\n", scsiqp->host_status);
6134 scp->result = HOST_BYTE(DID_BAD_TARGET);
6139 case QD_ABORTED_BY_HOST:
6140 ASC_DBG(1, "QD_ABORTED_BY_HOST\n");
6142 HOST_BYTE(DID_ABORT) | STATUS_BYTE(scsiqp->scsi_status);
6146 ASC_DBG(1, "done_status 0x%x\n", scsiqp->done_status);
6148 HOST_BYTE(DID_ERROR) | STATUS_BYTE(scsiqp->scsi_status);
6153 * If the 'init_tidmask' bit isn't already set for the target and the
6154 * current request finished normally, then set the bit for the target
6155 * to indicate that a device is present.
6157 if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 &&
6158 scsiqp->done_status == QD_NO_ERROR &&
6159 scsiqp->host_status == QHSTA_NO_ERROR) {
6160 boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id);
6166 * Free all 'adv_sgblk_t' structures allocated for the request.
6168 while ((sgblkp = reqp->sgblkp) != NULL) {
6169 /* Remove 'sgblkp' from the request list. */
6170 reqp->sgblkp = sgblkp->next_sgblkp;
6172 dma_pool_free(boardp->adv_sgblk_pool, sgblkp,
6176 ASC_DBG(1, "done\n");
6180 * Adv Library Interrupt Service Routine
6182 * This function is called by a driver's interrupt service routine.
6183 * The function disables and re-enables interrupts.
6185 * When a microcode idle command is completed, the ADV_DVC_VAR
6186 * 'idle_cmd_done' field is set to ADV_TRUE.
6188 * Note: AdvISR() can be called when interrupts are disabled or even
6189 * when there is no hardware interrupt condition present. It will
6190 * always check for completed idle commands and microcode requests.
6191 * This is an important feature that shouldn't be changed because it
6192 * allows commands to be completed from polling mode loops.
6195 * ADV_TRUE(1) - interrupt was pending
6196 * ADV_FALSE(0) - no interrupt was pending
6198 static int AdvISR(ADV_DVC_VAR *asc_dvc)
6200 AdvPortAddr iop_base;
6203 ADV_CARR_T *free_carrp;
6204 __le32 irq_next_vpa;
6205 ADV_SCSI_REQ_Q *scsiq;
6208 iop_base = asc_dvc->iop_base;
6210 /* Reading the register clears the interrupt. */
6211 int_stat = AdvReadByteRegister(iop_base, IOPB_INTR_STATUS_REG);
6213 if ((int_stat & (ADV_INTR_STATUS_INTRA | ADV_INTR_STATUS_INTRB |
6214 ADV_INTR_STATUS_INTRC)) == 0) {
6219 * Notify the driver of an asynchronous microcode condition by
6220 * calling the adv_async_callback function. The function
6221 * is passed the microcode ASC_MC_INTRB_CODE byte value.
6223 if (int_stat & ADV_INTR_STATUS_INTRB) {
6226 AdvReadByteLram(iop_base, ASC_MC_INTRB_CODE, intrb_code);
6228 if (asc_dvc->chip_type == ADV_CHIP_ASC3550 ||
6229 asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
6230 if (intrb_code == ADV_ASYNC_CARRIER_READY_FAILURE &&
6231 asc_dvc->carr_pending_cnt != 0) {
6232 AdvWriteByteRegister(iop_base, IOPB_TICKLE,
6234 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
6235 AdvWriteByteRegister(iop_base,
6242 adv_async_callback(asc_dvc, intrb_code);
6246 * Check if the IRQ stopper carrier contains a completed request.
6248 while (((irq_next_vpa =
6249 le32_to_cpu(asc_dvc->irq_sp->next_vpa)) & ASC_RQ_DONE) != 0) {
6251 * Get a pointer to the newly completed ADV_SCSI_REQ_Q structure.
6252 * The RISC will have set 'areq_vpa' to a virtual address.
6254 * The firmware will have copied the ASC_SCSI_REQ_Q.scsiq_ptr
6255 * field to the carrier ADV_CARR_T.areq_vpa field. The conversion
6256 * below complements the conversion of ASC_SCSI_REQ_Q.scsiq_ptr'
6257 * in AdvExeScsiQueue().
6259 u32 pa_offset = le32_to_cpu(asc_dvc->irq_sp->areq_vpa);
6260 ASC_DBG(1, "irq_sp %p areq_vpa %u\n",
6261 asc_dvc->irq_sp, pa_offset);
6262 reqp = adv_get_reqp(asc_dvc, pa_offset);
6263 scsiq = &reqp->scsi_req_q;
6266 * Request finished with good status and the queue was not
6267 * DMAed to host memory by the firmware. Set all status fields
6268 * to indicate good status.
6270 if ((irq_next_vpa & ASC_RQ_GOOD) != 0) {
6271 scsiq->done_status = QD_NO_ERROR;
6272 scsiq->host_status = scsiq->scsi_status = 0;
6273 scsiq->data_cnt = 0L;
6277 * Advance the stopper pointer to the next carrier
6278 * ignoring the lower four bits. Free the previous
6281 free_carrp = asc_dvc->irq_sp;
6282 asc_dvc->irq_sp = adv_get_carrier(asc_dvc,
6283 ASC_GET_CARRP(irq_next_vpa));
6285 free_carrp->next_vpa = asc_dvc->carr_freelist->carr_va;
6286 asc_dvc->carr_freelist = free_carrp;
6287 asc_dvc->carr_pending_cnt--;
6289 target_bit = ADV_TID_TO_TIDMASK(scsiq->target_id);
6292 * Clear request microcode control flag.
6297 * Notify the driver of the completed request by passing
6298 * the ADV_SCSI_REQ_Q pointer to its callback function.
6300 scsiq->a_flag |= ADV_SCSIQ_DONE;
6301 adv_isr_callback(asc_dvc, scsiq);
6303 * Note: After the driver callback function is called, 'scsiq'
6304 * can no longer be referenced.
6306 * Fall through and continue processing other completed
6313 static int AscSetLibErrorCode(ASC_DVC_VAR *asc_dvc, ushort err_code)
6315 if (asc_dvc->err_code == 0) {
6316 asc_dvc->err_code = err_code;
6317 AscWriteLramWord(asc_dvc->iop_base, ASCV_ASCDVC_ERR_CODE_W,
6323 static void AscAckInterrupt(PortAddr iop_base)
6331 risc_flag = AscReadLramByte(iop_base, ASCV_RISC_FLAG_B);
6332 if (loop++ > 0x7FFF) {
6335 } while ((risc_flag & ASC_RISC_FLAG_GEN_INT) != 0);
6337 AscReadLramByte(iop_base,
6338 ASCV_HOST_FLAG_B) & (~ASC_HOST_FLAG_ACK_INT);
6339 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B,
6340 (uchar)(host_flag | ASC_HOST_FLAG_ACK_INT));
6341 AscSetChipStatus(iop_base, CIW_INT_ACK);
6343 while (AscGetChipStatus(iop_base) & CSW_INT_PENDING) {
6344 AscSetChipStatus(iop_base, CIW_INT_ACK);
6349 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag);
6352 static uchar AscGetSynPeriodIndex(ASC_DVC_VAR *asc_dvc, uchar syn_time)
6354 const uchar *period_table;
6359 period_table = asc_dvc->sdtr_period_tbl;
6360 max_index = (int)asc_dvc->max_sdtr_index;
6361 min_index = (int)asc_dvc->min_sdtr_index;
6362 if ((syn_time <= period_table[max_index])) {
6363 for (i = min_index; i < (max_index - 1); i++) {
6364 if (syn_time <= period_table[i]) {
6368 return (uchar)max_index;
6370 return (uchar)(max_index + 1);
6375 AscMsgOutSDTR(ASC_DVC_VAR *asc_dvc, uchar sdtr_period, uchar sdtr_offset)
6378 uchar sdtr_period_index;
6381 iop_base = asc_dvc->iop_base;
6382 sdtr_buf.msg_type = EXTENDED_MESSAGE;
6383 sdtr_buf.msg_len = MS_SDTR_LEN;
6384 sdtr_buf.msg_req = EXTENDED_SDTR;
6385 sdtr_buf.xfer_period = sdtr_period;
6386 sdtr_offset &= ASC_SYN_MAX_OFFSET;
6387 sdtr_buf.req_ack_offset = sdtr_offset;
6388 sdtr_period_index = AscGetSynPeriodIndex(asc_dvc, sdtr_period);
6389 if (sdtr_period_index <= asc_dvc->max_sdtr_index) {
6390 AscMemWordCopyPtrToLram(iop_base, ASCV_MSGOUT_BEG,
6392 sizeof(EXT_MSG) >> 1);
6393 return ((sdtr_period_index << 4) | sdtr_offset);
6395 sdtr_buf.req_ack_offset = 0;
6396 AscMemWordCopyPtrToLram(iop_base, ASCV_MSGOUT_BEG,
6398 sizeof(EXT_MSG) >> 1);
6404 AscCalSDTRData(ASC_DVC_VAR *asc_dvc, uchar sdtr_period, uchar syn_offset)
6407 uchar sdtr_period_ix;
6409 sdtr_period_ix = AscGetSynPeriodIndex(asc_dvc, sdtr_period);
6410 if (sdtr_period_ix > asc_dvc->max_sdtr_index)
6412 byte = (sdtr_period_ix << 4) | (syn_offset & ASC_SYN_MAX_OFFSET);
6416 static bool AscSetChipSynRegAtID(PortAddr iop_base, uchar id, uchar sdtr_data)
6418 ASC_SCSI_BIT_ID_TYPE org_id;
6422 AscSetBank(iop_base, 1);
6423 org_id = AscReadChipDvcID(iop_base);
6424 for (i = 0; i <= ASC_MAX_TID; i++) {
6425 if (org_id == (0x01 << i))
6428 org_id = (ASC_SCSI_BIT_ID_TYPE) i;
6429 AscWriteChipDvcID(iop_base, id);
6430 if (AscReadChipDvcID(iop_base) == (0x01 << id)) {
6431 AscSetBank(iop_base, 0);
6432 AscSetChipSyn(iop_base, sdtr_data);
6433 if (AscGetChipSyn(iop_base) != sdtr_data) {
6439 AscSetBank(iop_base, 1);
6440 AscWriteChipDvcID(iop_base, org_id);
6441 AscSetBank(iop_base, 0);
6445 static void AscSetChipSDTR(PortAddr iop_base, uchar sdtr_data, uchar tid_no)
6447 AscSetChipSynRegAtID(iop_base, tid_no, sdtr_data);
6448 AscPutMCodeSDTRDoneAtID(iop_base, tid_no, sdtr_data);
6451 static int AscIsrChipHalted(ASC_DVC_VAR *asc_dvc)
6457 ushort int_halt_code;
6458 ASC_SCSI_BIT_ID_TYPE scsi_busy;
6459 ASC_SCSI_BIT_ID_TYPE target_id;
6466 uchar q_cntl, tid_no;
6470 struct asc_board *boardp;
6472 BUG_ON(!asc_dvc->drv_ptr);
6473 boardp = asc_dvc->drv_ptr;
6475 iop_base = asc_dvc->iop_base;
6476 int_halt_code = AscReadLramWord(iop_base, ASCV_HALTCODE_W);
6478 halt_qp = AscReadLramByte(iop_base, ASCV_CURCDB_B);
6479 halt_q_addr = ASC_QNO_TO_QADDR(halt_qp);
6480 target_ix = AscReadLramByte(iop_base,
6481 (ushort)(halt_q_addr +
6482 (ushort)ASC_SCSIQ_B_TARGET_IX));
6483 q_cntl = AscReadLramByte(iop_base,
6484 (ushort)(halt_q_addr + (ushort)ASC_SCSIQ_B_CNTL));
6485 tid_no = ASC_TIX_TO_TID(target_ix);
6486 target_id = (uchar)ASC_TID_TO_TARGET_ID(tid_no);
6487 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
6488 asyn_sdtr = ASYN_SDTR_DATA_FIX_PCI_REV_AB;
6492 if (int_halt_code == ASC_HALT_DISABLE_ASYN_USE_SYN_FIX) {
6493 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
6494 AscSetChipSDTR(iop_base, 0, tid_no);
6495 boardp->sdtr_data[tid_no] = 0;
6497 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6499 } else if (int_halt_code == ASC_HALT_ENABLE_ASYN_USE_SYN_FIX) {
6500 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
6501 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
6502 boardp->sdtr_data[tid_no] = asyn_sdtr;
6504 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6506 } else if (int_halt_code == ASC_HALT_EXTMSG_IN) {
6507 AscMemWordCopyPtrFromLram(iop_base,
6510 sizeof(EXT_MSG) >> 1);
6512 if (ext_msg.msg_type == EXTENDED_MESSAGE &&
6513 ext_msg.msg_req == EXTENDED_SDTR &&
6514 ext_msg.msg_len == MS_SDTR_LEN) {
6516 if ((ext_msg.req_ack_offset > ASC_SYN_MAX_OFFSET)) {
6518 sdtr_accept = FALSE;
6519 ext_msg.req_ack_offset = ASC_SYN_MAX_OFFSET;
6521 if ((ext_msg.xfer_period <
6522 asc_dvc->sdtr_period_tbl[asc_dvc->min_sdtr_index])
6523 || (ext_msg.xfer_period >
6524 asc_dvc->sdtr_period_tbl[asc_dvc->
6526 sdtr_accept = FALSE;
6527 ext_msg.xfer_period =
6528 asc_dvc->sdtr_period_tbl[asc_dvc->
6533 AscCalSDTRData(asc_dvc, ext_msg.xfer_period,
6534 ext_msg.req_ack_offset);
6535 if ((sdtr_data == 0xFF)) {
6537 q_cntl |= QC_MSG_OUT;
6538 asc_dvc->init_sdtr &= ~target_id;
6539 asc_dvc->sdtr_done &= ~target_id;
6540 AscSetChipSDTR(iop_base, asyn_sdtr,
6542 boardp->sdtr_data[tid_no] = asyn_sdtr;
6545 if (ext_msg.req_ack_offset == 0) {
6547 q_cntl &= ~QC_MSG_OUT;
6548 asc_dvc->init_sdtr &= ~target_id;
6549 asc_dvc->sdtr_done &= ~target_id;
6550 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
6552 if (sdtr_accept && (q_cntl & QC_MSG_OUT)) {
6553 q_cntl &= ~QC_MSG_OUT;
6554 asc_dvc->sdtr_done |= target_id;
6555 asc_dvc->init_sdtr |= target_id;
6556 asc_dvc->pci_fix_asyn_xfer &=
6559 AscCalSDTRData(asc_dvc,
6560 ext_msg.xfer_period,
6563 AscSetChipSDTR(iop_base, sdtr_data,
6565 boardp->sdtr_data[tid_no] = sdtr_data;
6567 q_cntl |= QC_MSG_OUT;
6568 AscMsgOutSDTR(asc_dvc,
6569 ext_msg.xfer_period,
6570 ext_msg.req_ack_offset);
6571 asc_dvc->pci_fix_asyn_xfer &=
6574 AscCalSDTRData(asc_dvc,
6575 ext_msg.xfer_period,
6578 AscSetChipSDTR(iop_base, sdtr_data,
6580 boardp->sdtr_data[tid_no] = sdtr_data;
6581 asc_dvc->sdtr_done |= target_id;
6582 asc_dvc->init_sdtr |= target_id;
6586 AscWriteLramByte(iop_base,
6587 (ushort)(halt_q_addr +
6588 (ushort)ASC_SCSIQ_B_CNTL),
6590 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6592 } else if (ext_msg.msg_type == EXTENDED_MESSAGE &&
6593 ext_msg.msg_req == EXTENDED_WDTR &&
6594 ext_msg.msg_len == MS_WDTR_LEN) {
6596 ext_msg.wdtr_width = 0;
6597 AscMemWordCopyPtrToLram(iop_base,
6600 sizeof(EXT_MSG) >> 1);
6601 q_cntl |= QC_MSG_OUT;
6602 AscWriteLramByte(iop_base,
6603 (ushort)(halt_q_addr +
6604 (ushort)ASC_SCSIQ_B_CNTL),
6606 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6610 ext_msg.msg_type = MESSAGE_REJECT;
6611 AscMemWordCopyPtrToLram(iop_base,
6614 sizeof(EXT_MSG) >> 1);
6615 q_cntl |= QC_MSG_OUT;
6616 AscWriteLramByte(iop_base,
6617 (ushort)(halt_q_addr +
6618 (ushort)ASC_SCSIQ_B_CNTL),
6620 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6623 } else if (int_halt_code == ASC_HALT_CHK_CONDITION) {
6625 q_cntl |= QC_REQ_SENSE;
6627 if ((asc_dvc->init_sdtr & target_id) != 0) {
6629 asc_dvc->sdtr_done &= ~target_id;
6631 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
6632 q_cntl |= QC_MSG_OUT;
6633 AscMsgOutSDTR(asc_dvc,
6635 sdtr_period_tbl[(sdtr_data >> 4) &
6639 (uchar)(sdtr_data & (uchar)
6640 ASC_SYN_MAX_OFFSET));
6643 AscWriteLramByte(iop_base,
6644 (ushort)(halt_q_addr +
6645 (ushort)ASC_SCSIQ_B_CNTL), q_cntl);
6647 tag_code = AscReadLramByte(iop_base,
6648 (ushort)(halt_q_addr + (ushort)
6649 ASC_SCSIQ_B_TAG_CODE));
6651 if ((asc_dvc->pci_fix_asyn_xfer & target_id)
6652 && !(asc_dvc->pci_fix_asyn_xfer_always & target_id)
6655 tag_code |= (ASC_TAG_FLAG_DISABLE_DISCONNECT
6656 | ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX);
6659 AscWriteLramByte(iop_base,
6660 (ushort)(halt_q_addr +
6661 (ushort)ASC_SCSIQ_B_TAG_CODE),
6664 q_status = AscReadLramByte(iop_base,
6665 (ushort)(halt_q_addr + (ushort)
6666 ASC_SCSIQ_B_STATUS));
6667 q_status |= (QS_READY | QS_BUSY);
6668 AscWriteLramByte(iop_base,
6669 (ushort)(halt_q_addr +
6670 (ushort)ASC_SCSIQ_B_STATUS),
6673 scsi_busy = AscReadLramByte(iop_base, (ushort)ASCV_SCSIBUSY_B);
6674 scsi_busy &= ~target_id;
6675 AscWriteLramByte(iop_base, (ushort)ASCV_SCSIBUSY_B, scsi_busy);
6677 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6679 } else if (int_halt_code == ASC_HALT_SDTR_REJECTED) {
6681 AscMemWordCopyPtrFromLram(iop_base,
6684 sizeof(EXT_MSG) >> 1);
6686 if ((out_msg.msg_type == EXTENDED_MESSAGE) &&
6687 (out_msg.msg_len == MS_SDTR_LEN) &&
6688 (out_msg.msg_req == EXTENDED_SDTR)) {
6690 asc_dvc->init_sdtr &= ~target_id;
6691 asc_dvc->sdtr_done &= ~target_id;
6692 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
6693 boardp->sdtr_data[tid_no] = asyn_sdtr;
6695 q_cntl &= ~QC_MSG_OUT;
6696 AscWriteLramByte(iop_base,
6697 (ushort)(halt_q_addr +
6698 (ushort)ASC_SCSIQ_B_CNTL), q_cntl);
6699 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6701 } else if (int_halt_code == ASC_HALT_SS_QUEUE_FULL) {
6703 scsi_status = AscReadLramByte(iop_base,
6704 (ushort)((ushort)halt_q_addr +
6706 ASC_SCSIQ_SCSI_STATUS));
6708 AscReadLramByte(iop_base,
6709 (ushort)((ushort)ASC_QADR_BEG +
6710 (ushort)target_ix));
6711 if ((cur_dvc_qng > 0) && (asc_dvc->cur_dvc_qng[tid_no] > 0)) {
6713 scsi_busy = AscReadLramByte(iop_base,
6714 (ushort)ASCV_SCSIBUSY_B);
6715 scsi_busy |= target_id;
6716 AscWriteLramByte(iop_base,
6717 (ushort)ASCV_SCSIBUSY_B, scsi_busy);
6718 asc_dvc->queue_full_or_busy |= target_id;
6720 if (scsi_status == SAM_STAT_TASK_SET_FULL) {
6721 if (cur_dvc_qng > ASC_MIN_TAGGED_CMD) {
6723 asc_dvc->max_dvc_qng[tid_no] =
6726 AscWriteLramByte(iop_base,
6728 ASCV_MAX_DVC_QNG_BEG
6734 * Set the device queue depth to the
6735 * number of active requests when the
6736 * QUEUE FULL condition was encountered.
6738 boardp->queue_full |= target_id;
6739 boardp->queue_full_cnt[tid_no] =
6744 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6747 #if CC_VERY_LONG_SG_LIST
6748 else if (int_halt_code == ASC_HALT_HOST_COPY_SG_LIST_TO_RISC) {
6752 uchar first_sg_wk_q_no;
6753 ASC_SCSI_Q *scsiq; /* Ptr to driver request. */
6754 ASC_SG_HEAD *sg_head; /* Ptr to driver SG request. */
6755 ASC_SG_LIST_Q scsi_sg_q; /* Structure written to queue. */
6756 ushort sg_list_dwords;
6757 ushort sg_entry_cnt;
6761 q_no = AscReadLramByte(iop_base, (ushort)ASCV_REQ_SG_LIST_QP);
6762 if (q_no == ASC_QLINK_END)
6765 q_addr = ASC_QNO_TO_QADDR(q_no);
6768 * Convert the request's SRB pointer to a host ASC_SCSI_REQ
6769 * structure pointer using a macro provided by the driver.
6770 * The ASC_SCSI_REQ pointer provides a pointer to the
6771 * host ASC_SG_HEAD structure.
6773 /* Read request's SRB pointer. */
6774 scsiq = (ASC_SCSI_Q *)
6775 ASC_SRB2SCSIQ(ASC_U32_TO_VADDR(AscReadLramDWord(iop_base,
6778 ASC_SCSIQ_D_SRBPTR))));
6781 * Get request's first and working SG queue.
6783 sg_wk_q_no = AscReadLramByte(iop_base,
6785 ASC_SCSIQ_B_SG_WK_QP));
6787 first_sg_wk_q_no = AscReadLramByte(iop_base,
6789 ASC_SCSIQ_B_FIRST_SG_WK_QP));
6792 * Reset request's working SG queue back to the
6795 AscWriteLramByte(iop_base,
6797 (ushort)ASC_SCSIQ_B_SG_WK_QP),
6800 sg_head = scsiq->sg_head;
6803 * Set sg_entry_cnt to the number of SG elements
6804 * that will be completed on this interrupt.
6806 * Note: The allocated SG queues contain ASC_MAX_SG_LIST - 1
6807 * SG elements. The data_cnt and data_addr fields which
6808 * add 1 to the SG element capacity are not used when
6809 * restarting SG handling after a halt.
6811 if (scsiq->remain_sg_entry_cnt > (ASC_MAX_SG_LIST - 1)) {
6812 sg_entry_cnt = ASC_MAX_SG_LIST - 1;
6815 * Keep track of remaining number of SG elements that
6816 * will need to be handled on the next interrupt.
6818 scsiq->remain_sg_entry_cnt -= (ASC_MAX_SG_LIST - 1);
6820 sg_entry_cnt = scsiq->remain_sg_entry_cnt;
6821 scsiq->remain_sg_entry_cnt = 0;
6825 * Copy SG elements into the list of allocated SG queues.
6827 * Last index completed is saved in scsiq->next_sg_index.
6829 next_qp = first_sg_wk_q_no;
6830 q_addr = ASC_QNO_TO_QADDR(next_qp);
6831 scsi_sg_q.sg_head_qp = q_no;
6832 scsi_sg_q.cntl = QCSG_SG_XFER_LIST;
6833 for (i = 0; i < sg_head->queue_cnt; i++) {
6834 scsi_sg_q.seq_no = i + 1;
6835 if (sg_entry_cnt > ASC_SG_LIST_PER_Q) {
6836 sg_list_dwords = (uchar)(ASC_SG_LIST_PER_Q * 2);
6837 sg_entry_cnt -= ASC_SG_LIST_PER_Q;
6839 * After very first SG queue RISC FW uses next
6840 * SG queue first element then checks sg_list_cnt
6841 * against zero and then decrements, so set
6842 * sg_list_cnt 1 less than number of SG elements
6845 scsi_sg_q.sg_list_cnt = ASC_SG_LIST_PER_Q - 1;
6846 scsi_sg_q.sg_cur_list_cnt =
6847 ASC_SG_LIST_PER_Q - 1;
6850 * This is the last SG queue in the list of
6851 * allocated SG queues. If there are more
6852 * SG elements than will fit in the allocated
6853 * queues, then set the QCSG_SG_XFER_MORE flag.
6855 if (scsiq->remain_sg_entry_cnt != 0) {
6856 scsi_sg_q.cntl |= QCSG_SG_XFER_MORE;
6858 scsi_sg_q.cntl |= QCSG_SG_XFER_END;
6860 /* equals sg_entry_cnt * 2 */
6861 sg_list_dwords = sg_entry_cnt << 1;
6862 scsi_sg_q.sg_list_cnt = sg_entry_cnt - 1;
6863 scsi_sg_q.sg_cur_list_cnt = sg_entry_cnt - 1;
6867 scsi_sg_q.q_no = next_qp;
6868 AscMemWordCopyPtrToLram(iop_base,
6869 q_addr + ASC_SCSIQ_SGHD_CPY_BEG,
6870 (uchar *)&scsi_sg_q,
6871 sizeof(ASC_SG_LIST_Q) >> 1);
6873 AscMemDWordCopyPtrToLram(iop_base,
6874 q_addr + ASC_SGQ_LIST_BEG,
6876 sg_list[scsiq->next_sg_index],
6879 scsiq->next_sg_index += ASC_SG_LIST_PER_Q;
6882 * If the just completed SG queue contained the
6883 * last SG element, then no more SG queues need
6886 if (scsi_sg_q.cntl & QCSG_SG_XFER_END) {
6890 next_qp = AscReadLramByte(iop_base,
6893 q_addr = ASC_QNO_TO_QADDR(next_qp);
6897 * Clear the halt condition so the RISC will be restarted
6900 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6903 #endif /* CC_VERY_LONG_SG_LIST */
6909 * DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words)
6911 * Calling/Exit State:
6915 * Input an ASC_QDONE_INFO structure from the chip
6918 DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words)
6923 AscSetChipLramAddr(iop_base, s_addr);
6924 for (i = 0; i < 2 * words; i += 2) {
6928 word = inpw(iop_base + IOP_RAM_DATA);
6929 inbuf[i] = word & 0xff;
6930 inbuf[i + 1] = (word >> 8) & 0xff;
6932 ASC_DBG_PRT_HEX(2, "DvcGetQinfo", inbuf, 2 * words);
6936 _AscCopyLramScsiDoneQ(PortAddr iop_base,
6938 ASC_QDONE_INFO *scsiq, unsigned int max_dma_count)
6943 DvcGetQinfo(iop_base,
6944 q_addr + ASC_SCSIQ_DONE_INFO_BEG,
6946 (sizeof(ASC_SCSIQ_2) + sizeof(ASC_SCSIQ_3)) / 2);
6948 _val = AscReadLramWord(iop_base,
6949 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_STATUS));
6950 scsiq->q_status = (uchar)_val;
6951 scsiq->q_no = (uchar)(_val >> 8);
6952 _val = AscReadLramWord(iop_base,
6953 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_CNTL));
6954 scsiq->cntl = (uchar)_val;
6955 sg_queue_cnt = (uchar)(_val >> 8);
6956 _val = AscReadLramWord(iop_base,
6958 (ushort)ASC_SCSIQ_B_SENSE_LEN));
6959 scsiq->sense_len = (uchar)_val;
6960 scsiq->extra_bytes = (uchar)(_val >> 8);
6963 * Read high word of remain bytes from alternate location.
6965 scsiq->remain_bytes = (((u32)AscReadLramWord(iop_base,
6968 ASC_SCSIQ_W_ALT_DC1)))
6971 * Read low word of remain bytes from original location.
6973 scsiq->remain_bytes += AscReadLramWord(iop_base,
6974 (ushort)(q_addr + (ushort)
6975 ASC_SCSIQ_DW_REMAIN_XFER_CNT));
6977 scsiq->remain_bytes &= max_dma_count;
6978 return sg_queue_cnt;
6982 * asc_isr_callback() - Second Level Interrupt Handler called by AscISR().
6984 * Interrupt callback function for the Narrow SCSI Asc Library.
6986 static void asc_isr_callback(ASC_DVC_VAR *asc_dvc_varp, ASC_QDONE_INFO *qdonep)
6988 struct asc_board *boardp = asc_dvc_varp->drv_ptr;
6990 struct scsi_cmnd *scp;
6992 ASC_DBG(1, "asc_dvc_varp 0x%p, qdonep 0x%p\n", asc_dvc_varp, qdonep);
6993 ASC_DBG_PRT_ASC_QDONE_INFO(2, qdonep);
6996 * Decrease the srb_tag by 1 to find the SCSI command
6998 srb_tag = qdonep->d2.srb_tag - 1;
6999 scp = scsi_host_find_tag(boardp->shost, srb_tag);
7003 ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len);
7005 ASC_STATS(boardp->shost, callback);
7007 dma_unmap_single(boardp->dev, scp->SCp.dma_handle,
7008 SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
7010 * 'qdonep' contains the command's ending status.
7012 switch (qdonep->d3.done_stat) {
7014 ASC_DBG(2, "QD_NO_ERROR\n");
7018 * Check for an underrun condition.
7020 * If there was no error and an underrun condition, then
7021 * return the number of underrun bytes.
7023 if (scsi_bufflen(scp) != 0 && qdonep->remain_bytes != 0 &&
7024 qdonep->remain_bytes <= scsi_bufflen(scp)) {
7025 ASC_DBG(1, "underrun condition %u bytes\n",
7026 (unsigned)qdonep->remain_bytes);
7027 scsi_set_resid(scp, qdonep->remain_bytes);
7032 ASC_DBG(2, "QD_WITH_ERROR\n");
7033 switch (qdonep->d3.host_stat) {
7034 case QHSTA_NO_ERROR:
7035 if (qdonep->d3.scsi_stat == SAM_STAT_CHECK_CONDITION) {
7036 ASC_DBG(2, "SAM_STAT_CHECK_CONDITION\n");
7037 ASC_DBG_PRT_SENSE(2, scp->sense_buffer,
7038 SCSI_SENSE_BUFFERSIZE);
7040 * Note: The 'status_byte()' macro used by
7041 * target drivers defined in scsi.h shifts the
7042 * status byte returned by host drivers right
7043 * by 1 bit. This is why target drivers also
7044 * use right shifted status byte definitions.
7045 * For instance target drivers use
7046 * CHECK_CONDITION, defined to 0x1, instead of
7047 * the SCSI defined check condition value of
7048 * 0x2. Host drivers are supposed to return
7049 * the status byte as it is defined by SCSI.
7051 scp->result = DRIVER_BYTE(DRIVER_SENSE) |
7052 STATUS_BYTE(qdonep->d3.scsi_stat);
7054 scp->result = STATUS_BYTE(qdonep->d3.scsi_stat);
7059 /* QHSTA error occurred */
7060 ASC_DBG(1, "host_stat 0x%x\n", qdonep->d3.host_stat);
7061 scp->result = HOST_BYTE(DID_BAD_TARGET);
7066 case QD_ABORTED_BY_HOST:
7067 ASC_DBG(1, "QD_ABORTED_BY_HOST\n");
7069 HOST_BYTE(DID_ABORT) | MSG_BYTE(qdonep->d3.
7071 STATUS_BYTE(qdonep->d3.scsi_stat);
7075 ASC_DBG(1, "done_stat 0x%x\n", qdonep->d3.done_stat);
7077 HOST_BYTE(DID_ERROR) | MSG_BYTE(qdonep->d3.
7079 STATUS_BYTE(qdonep->d3.scsi_stat);
7084 * If the 'init_tidmask' bit isn't already set for the target and the
7085 * current request finished normally, then set the bit for the target
7086 * to indicate that a device is present.
7088 if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 &&
7089 qdonep->d3.done_stat == QD_NO_ERROR &&
7090 qdonep->d3.host_stat == QHSTA_NO_ERROR) {
7091 boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id);
7097 static int AscIsrQDone(ASC_DVC_VAR *asc_dvc)
7106 ASC_SCSI_BIT_ID_TYPE scsi_busy;
7107 ASC_SCSI_BIT_ID_TYPE target_id;
7111 uchar cur_target_qng;
7112 ASC_QDONE_INFO scsiq_buf;
7113 ASC_QDONE_INFO *scsiq;
7116 iop_base = asc_dvc->iop_base;
7118 scsiq = (ASC_QDONE_INFO *)&scsiq_buf;
7119 done_q_tail = (uchar)AscGetVarDoneQTail(iop_base);
7120 q_addr = ASC_QNO_TO_QADDR(done_q_tail);
7121 next_qp = AscReadLramByte(iop_base,
7122 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_FWD));
7123 if (next_qp != ASC_QLINK_END) {
7124 AscPutVarDoneQTail(iop_base, next_qp);
7125 q_addr = ASC_QNO_TO_QADDR(next_qp);
7126 sg_queue_cnt = _AscCopyLramScsiDoneQ(iop_base, q_addr, scsiq,
7127 asc_dvc->max_dma_count);
7128 AscWriteLramByte(iop_base,
7130 (ushort)ASC_SCSIQ_B_STATUS),
7132 q_status & (uchar)~(QS_READY |
7134 tid_no = ASC_TIX_TO_TID(scsiq->d2.target_ix);
7135 target_id = ASC_TIX_TO_TARGET_ID(scsiq->d2.target_ix);
7136 if ((scsiq->cntl & QC_SG_HEAD) != 0) {
7138 sg_list_qp = next_qp;
7139 for (q_cnt = 0; q_cnt < sg_queue_cnt; q_cnt++) {
7140 sg_list_qp = AscReadLramByte(iop_base,
7144 sg_q_addr = ASC_QNO_TO_QADDR(sg_list_qp);
7145 if (sg_list_qp == ASC_QLINK_END) {
7146 AscSetLibErrorCode(asc_dvc,
7147 ASCQ_ERR_SG_Q_LINKS);
7148 scsiq->d3.done_stat = QD_WITH_ERROR;
7149 scsiq->d3.host_stat =
7150 QHSTA_D_QDONE_SG_LIST_CORRUPTED;
7151 goto FATAL_ERR_QDONE;
7153 AscWriteLramByte(iop_base,
7154 (ushort)(sg_q_addr + (ushort)
7155 ASC_SCSIQ_B_STATUS),
7158 n_q_used = sg_queue_cnt + 1;
7159 AscPutVarDoneQTail(iop_base, sg_list_qp);
7161 if (asc_dvc->queue_full_or_busy & target_id) {
7162 cur_target_qng = AscReadLramByte(iop_base,
7168 if (cur_target_qng < asc_dvc->max_dvc_qng[tid_no]) {
7169 scsi_busy = AscReadLramByte(iop_base, (ushort)
7171 scsi_busy &= ~target_id;
7172 AscWriteLramByte(iop_base,
7173 (ushort)ASCV_SCSIBUSY_B,
7175 asc_dvc->queue_full_or_busy &= ~target_id;
7178 if (asc_dvc->cur_total_qng >= n_q_used) {
7179 asc_dvc->cur_total_qng -= n_q_used;
7180 if (asc_dvc->cur_dvc_qng[tid_no] != 0) {
7181 asc_dvc->cur_dvc_qng[tid_no]--;
7184 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_CUR_QNG);
7185 scsiq->d3.done_stat = QD_WITH_ERROR;
7186 goto FATAL_ERR_QDONE;
7188 if ((scsiq->d2.srb_tag == 0UL) ||
7189 ((scsiq->q_status & QS_ABORTED) != 0)) {
7191 } else if (scsiq->q_status == QS_DONE) {
7192 false_overrun = FALSE;
7193 if (scsiq->extra_bytes != 0) {
7194 scsiq->remain_bytes += scsiq->extra_bytes;
7196 if (scsiq->d3.done_stat == QD_WITH_ERROR) {
7197 if (scsiq->d3.host_stat ==
7198 QHSTA_M_DATA_OVER_RUN) {
7200 cntl & (QC_DATA_IN | QC_DATA_OUT))
7202 scsiq->d3.done_stat =
7204 scsiq->d3.host_stat =
7206 } else if (false_overrun) {
7207 scsiq->d3.done_stat =
7209 scsiq->d3.host_stat =
7212 } else if (scsiq->d3.host_stat ==
7213 QHSTA_M_HUNG_REQ_SCSI_BUS_RESET) {
7214 AscStopChip(iop_base);
7215 AscSetChipControl(iop_base,
7216 (uchar)(CC_SCSI_RESET
7219 AscSetChipControl(iop_base, CC_HALT);
7220 AscSetChipStatus(iop_base,
7221 CIW_CLR_SCSI_RESET_INT);
7222 AscSetChipStatus(iop_base, 0);
7223 AscSetChipControl(iop_base, 0);
7226 if ((scsiq->cntl & QC_NO_CALLBACK) == 0) {
7227 asc_isr_callback(asc_dvc, scsiq);
7229 if ((AscReadLramByte(iop_base,
7230 (ushort)(q_addr + (ushort)
7233 asc_dvc->unit_not_ready &= ~target_id;
7234 if (scsiq->d3.done_stat != QD_NO_ERROR) {
7235 asc_dvc->start_motor &=
7242 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_Q_STATUS);
7244 if ((scsiq->cntl & QC_NO_CALLBACK) == 0) {
7245 asc_isr_callback(asc_dvc, scsiq);
7253 static int AscISR(ASC_DVC_VAR *asc_dvc)
7255 ASC_CS_TYPE chipstat;
7257 ushort saved_ram_addr;
7259 uchar saved_ctrl_reg;
7264 iop_base = asc_dvc->iop_base;
7265 int_pending = FALSE;
7267 if (AscIsIntPending(iop_base) == 0)
7270 if ((asc_dvc->init_state & ASC_INIT_STATE_END_LOAD_MC) == 0) {
7273 if (asc_dvc->in_critical_cnt != 0) {
7274 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_ON_CRITICAL);
7277 if (asc_dvc->is_in_int) {
7278 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_RE_ENTRY);
7281 asc_dvc->is_in_int = TRUE;
7282 ctrl_reg = AscGetChipControl(iop_base);
7283 saved_ctrl_reg = ctrl_reg & (~(CC_SCSI_RESET | CC_CHIP_RESET |
7284 CC_SINGLE_STEP | CC_DIAG | CC_TEST));
7285 chipstat = AscGetChipStatus(iop_base);
7286 if (chipstat & CSW_SCSI_RESET_LATCH) {
7287 if (!(asc_dvc->bus_type & (ASC_IS_VL | ASC_IS_EISA))) {
7290 asc_dvc->sdtr_done = 0;
7291 saved_ctrl_reg &= (uchar)(~CC_HALT);
7292 while ((AscGetChipStatus(iop_base) &
7293 CSW_SCSI_RESET_ACTIVE) && (i-- > 0)) {
7296 AscSetChipControl(iop_base, (CC_CHIP_RESET | CC_HALT));
7297 AscSetChipControl(iop_base, CC_HALT);
7298 AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT);
7299 AscSetChipStatus(iop_base, 0);
7300 chipstat = AscGetChipStatus(iop_base);
7303 saved_ram_addr = AscGetChipLramAddr(iop_base);
7304 host_flag = AscReadLramByte(iop_base,
7306 (uchar)(~ASC_HOST_FLAG_IN_ISR);
7307 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B,
7308 (uchar)(host_flag | (uchar)ASC_HOST_FLAG_IN_ISR));
7309 if ((chipstat & CSW_INT_PENDING) || (int_pending)) {
7310 AscAckInterrupt(iop_base);
7312 if ((chipstat & CSW_HALTED) && (ctrl_reg & CC_SINGLE_STEP)) {
7313 if (AscIsrChipHalted(asc_dvc) == ERR) {
7314 goto ISR_REPORT_QDONE_FATAL_ERROR;
7316 saved_ctrl_reg &= (uchar)(~CC_HALT);
7319 ISR_REPORT_QDONE_FATAL_ERROR:
7320 if ((asc_dvc->dvc_cntl & ASC_CNTL_INT_MULTI_Q) != 0) {
7322 AscIsrQDone(asc_dvc)) & 0x01) != 0) {
7327 AscIsrQDone(asc_dvc)) == 1) {
7330 } while (status == 0x11);
7332 if ((status & 0x80) != 0)
7336 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag);
7337 AscSetChipLramAddr(iop_base, saved_ram_addr);
7338 AscSetChipControl(iop_base, saved_ctrl_reg);
7339 asc_dvc->is_in_int = FALSE;
7346 * Reset the host associated with the command 'scp'.
7348 * This function runs its own thread. Interrupts must be blocked but
7349 * sleeping is allowed and no locking other than for host structures is
7350 * required. Returns SUCCESS or FAILED.
7352 static int advansys_reset(struct scsi_cmnd *scp)
7354 struct Scsi_Host *shost = scp->device->host;
7355 struct asc_board *boardp = shost_priv(shost);
7356 unsigned long flags;
7360 ASC_DBG(1, "0x%p\n", scp);
7362 ASC_STATS(shost, reset);
7364 scmd_printk(KERN_INFO, scp, "SCSI host reset started...\n");
7366 if (ASC_NARROW_BOARD(boardp)) {
7367 ASC_DVC_VAR *asc_dvc = &boardp->dvc_var.asc_dvc_var;
7369 /* Reset the chip and SCSI bus. */
7370 ASC_DBG(1, "before AscInitAsc1000Driver()\n");
7371 status = AscInitAsc1000Driver(asc_dvc);
7373 /* Refer to ASC_IERR_* definitions for meaning of 'err_code'. */
7374 if (asc_dvc->err_code || !asc_dvc->overrun_dma) {
7375 scmd_printk(KERN_INFO, scp, "SCSI host reset error: "
7376 "0x%x, status: 0x%x\n", asc_dvc->err_code,
7379 } else if (status) {
7380 scmd_printk(KERN_INFO, scp, "SCSI host reset warning: "
7383 scmd_printk(KERN_INFO, scp, "SCSI host reset "
7387 ASC_DBG(1, "after AscInitAsc1000Driver()\n");
7390 * If the suggest reset bus flags are set, then reset the bus.
7391 * Otherwise only reset the device.
7393 ADV_DVC_VAR *adv_dvc = &boardp->dvc_var.adv_dvc_var;
7396 * Reset the chip and SCSI bus.
7398 ASC_DBG(1, "before AdvResetChipAndSB()\n");
7399 switch (AdvResetChipAndSB(adv_dvc)) {
7401 scmd_printk(KERN_INFO, scp, "SCSI host reset "
7406 scmd_printk(KERN_INFO, scp, "SCSI host reset error\n");
7410 spin_lock_irqsave(shost->host_lock, flags);
7412 spin_unlock_irqrestore(shost->host_lock, flags);
7415 ASC_DBG(1, "ret %d\n", ret);
7421 * advansys_biosparam()
7423 * Translate disk drive geometry if the "BIOS greater than 1 GB"
7424 * support is enabled for a drive.
7426 * ip (information pointer) is an int array with the following definition:
7432 advansys_biosparam(struct scsi_device *sdev, struct block_device *bdev,
7433 sector_t capacity, int ip[])
7435 struct asc_board *boardp = shost_priv(sdev->host);
7437 ASC_DBG(1, "begin\n");
7438 ASC_STATS(sdev->host, biosparam);
7439 if (ASC_NARROW_BOARD(boardp)) {
7440 if ((boardp->dvc_var.asc_dvc_var.dvc_cntl &
7441 ASC_CNTL_BIOS_GT_1GB) && capacity > 0x200000) {
7449 if ((boardp->dvc_var.adv_dvc_var.bios_ctrl &
7450 BIOS_CTRL_EXTENDED_XLAT) && capacity > 0x200000) {
7458 ip[2] = (unsigned long)capacity / (ip[0] * ip[1]);
7459 ASC_DBG(1, "end\n");
7464 * First-level interrupt handler.
7466 * 'dev_id' is a pointer to the interrupting adapter's Scsi_Host.
7468 static irqreturn_t advansys_interrupt(int irq, void *dev_id)
7470 struct Scsi_Host *shost = dev_id;
7471 struct asc_board *boardp = shost_priv(shost);
7472 irqreturn_t result = IRQ_NONE;
7474 ASC_DBG(2, "boardp 0x%p\n", boardp);
7475 spin_lock(shost->host_lock);
7476 if (ASC_NARROW_BOARD(boardp)) {
7477 if (AscIsIntPending(shost->io_port)) {
7478 result = IRQ_HANDLED;
7479 ASC_STATS(shost, interrupt);
7480 ASC_DBG(1, "before AscISR()\n");
7481 AscISR(&boardp->dvc_var.asc_dvc_var);
7484 ASC_DBG(1, "before AdvISR()\n");
7485 if (AdvISR(&boardp->dvc_var.adv_dvc_var)) {
7486 result = IRQ_HANDLED;
7487 ASC_STATS(shost, interrupt);
7490 spin_unlock(shost->host_lock);
7492 ASC_DBG(1, "end\n");
7496 static bool AscHostReqRiscHalt(PortAddr iop_base)
7500 uchar saved_stop_code;
7502 if (AscIsChipHalted(iop_base))
7504 saved_stop_code = AscReadLramByte(iop_base, ASCV_STOP_CODE_B);
7505 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B,
7506 ASC_STOP_HOST_REQ_RISC_HALT | ASC_STOP_REQ_RISC_STOP);
7508 if (AscIsChipHalted(iop_base)) {
7513 } while (count++ < 20);
7514 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, saved_stop_code);
7519 AscSetRunChipSynRegAtID(PortAddr iop_base, uchar tid_no, uchar sdtr_data)
7523 if (AscHostReqRiscHalt(iop_base)) {
7524 sta = AscSetChipSynRegAtID(iop_base, tid_no, sdtr_data);
7525 AscStartChip(iop_base);
7530 static void AscAsyncFix(ASC_DVC_VAR *asc_dvc, struct scsi_device *sdev)
7532 char type = sdev->type;
7533 ASC_SCSI_BIT_ID_TYPE tid_bits = 1 << sdev->id;
7535 if (!(asc_dvc->bug_fix_cntl & ASC_BUG_FIX_ASYN_USE_SYN))
7537 if (asc_dvc->init_sdtr & tid_bits)
7540 if ((type == TYPE_ROM) && (strncmp(sdev->vendor, "HP ", 3) == 0))
7541 asc_dvc->pci_fix_asyn_xfer_always |= tid_bits;
7543 asc_dvc->pci_fix_asyn_xfer |= tid_bits;
7544 if ((type == TYPE_PROCESSOR) || (type == TYPE_SCANNER) ||
7545 (type == TYPE_ROM) || (type == TYPE_TAPE))
7546 asc_dvc->pci_fix_asyn_xfer &= ~tid_bits;
7548 if (asc_dvc->pci_fix_asyn_xfer & tid_bits)
7549 AscSetRunChipSynRegAtID(asc_dvc->iop_base, sdev->id,
7550 ASYN_SDTR_DATA_FIX_PCI_REV_AB);
7554 advansys_narrow_slave_configure(struct scsi_device *sdev, ASC_DVC_VAR *asc_dvc)
7556 ASC_SCSI_BIT_ID_TYPE tid_bit = 1 << sdev->id;
7557 ASC_SCSI_BIT_ID_TYPE orig_use_tagged_qng = asc_dvc->use_tagged_qng;
7559 if (sdev->lun == 0) {
7560 ASC_SCSI_BIT_ID_TYPE orig_init_sdtr = asc_dvc->init_sdtr;
7561 if ((asc_dvc->cfg->sdtr_enable & tid_bit) && sdev->sdtr) {
7562 asc_dvc->init_sdtr |= tid_bit;
7564 asc_dvc->init_sdtr &= ~tid_bit;
7567 if (orig_init_sdtr != asc_dvc->init_sdtr)
7568 AscAsyncFix(asc_dvc, sdev);
7571 if (sdev->tagged_supported) {
7572 if (asc_dvc->cfg->cmd_qng_enabled & tid_bit) {
7573 if (sdev->lun == 0) {
7574 asc_dvc->cfg->can_tagged_qng |= tid_bit;
7575 asc_dvc->use_tagged_qng |= tid_bit;
7577 scsi_change_queue_depth(sdev,
7578 asc_dvc->max_dvc_qng[sdev->id]);
7581 if (sdev->lun == 0) {
7582 asc_dvc->cfg->can_tagged_qng &= ~tid_bit;
7583 asc_dvc->use_tagged_qng &= ~tid_bit;
7587 if ((sdev->lun == 0) &&
7588 (orig_use_tagged_qng != asc_dvc->use_tagged_qng)) {
7589 AscWriteLramByte(asc_dvc->iop_base, ASCV_DISC_ENABLE_B,
7590 asc_dvc->cfg->disc_enable);
7591 AscWriteLramByte(asc_dvc->iop_base, ASCV_USE_TAGGED_QNG_B,
7592 asc_dvc->use_tagged_qng);
7593 AscWriteLramByte(asc_dvc->iop_base, ASCV_CAN_TAGGED_QNG_B,
7594 asc_dvc->cfg->can_tagged_qng);
7596 asc_dvc->max_dvc_qng[sdev->id] =
7597 asc_dvc->cfg->max_tag_qng[sdev->id];
7598 AscWriteLramByte(asc_dvc->iop_base,
7599 (ushort)(ASCV_MAX_DVC_QNG_BEG + sdev->id),
7600 asc_dvc->max_dvc_qng[sdev->id]);
7607 * If the EEPROM enabled WDTR for the device and the device supports wide
7608 * bus (16 bit) transfers, then turn on the device's 'wdtr_able' bit and
7609 * write the new value to the microcode.
7612 advansys_wide_enable_wdtr(AdvPortAddr iop_base, unsigned short tidmask)
7614 unsigned short cfg_word;
7615 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, cfg_word);
7616 if ((cfg_word & tidmask) != 0)
7619 cfg_word |= tidmask;
7620 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, cfg_word);
7623 * Clear the microcode SDTR and WDTR negotiation done indicators for
7624 * the target to cause it to negotiate with the new setting set above.
7625 * WDTR when accepted causes the target to enter asynchronous mode, so
7626 * SDTR must be negotiated.
7628 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
7629 cfg_word &= ~tidmask;
7630 AdvWriteWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
7631 AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, cfg_word);
7632 cfg_word &= ~tidmask;
7633 AdvWriteWordLram(iop_base, ASC_MC_WDTR_DONE, cfg_word);
7637 * Synchronous Transfers
7639 * If the EEPROM enabled SDTR for the device and the device
7640 * supports synchronous transfers, then turn on the device's
7641 * 'sdtr_able' bit. Write the new value to the microcode.
7644 advansys_wide_enable_sdtr(AdvPortAddr iop_base, unsigned short tidmask)
7646 unsigned short cfg_word;
7647 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, cfg_word);
7648 if ((cfg_word & tidmask) != 0)
7651 cfg_word |= tidmask;
7652 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, cfg_word);
7655 * Clear the microcode "SDTR negotiation" done indicator for the
7656 * target to cause it to negotiate with the new setting set above.
7658 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
7659 cfg_word &= ~tidmask;
7660 AdvWriteWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
7664 * PPR (Parallel Protocol Request) Capable
7666 * If the device supports DT mode, then it must be PPR capable.
7667 * The PPR message will be used in place of the SDTR and WDTR
7668 * messages to negotiate synchronous speed and offset, transfer
7669 * width, and protocol options.
7671 static void advansys_wide_enable_ppr(ADV_DVC_VAR *adv_dvc,
7672 AdvPortAddr iop_base, unsigned short tidmask)
7674 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, adv_dvc->ppr_able);
7675 adv_dvc->ppr_able |= tidmask;
7676 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, adv_dvc->ppr_able);
7680 advansys_wide_slave_configure(struct scsi_device *sdev, ADV_DVC_VAR *adv_dvc)
7682 AdvPortAddr iop_base = adv_dvc->iop_base;
7683 unsigned short tidmask = 1 << sdev->id;
7685 if (sdev->lun == 0) {
7687 * Handle WDTR, SDTR, and Tag Queuing. If the feature
7688 * is enabled in the EEPROM and the device supports the
7689 * feature, then enable it in the microcode.
7692 if ((adv_dvc->wdtr_able & tidmask) && sdev->wdtr)
7693 advansys_wide_enable_wdtr(iop_base, tidmask);
7694 if ((adv_dvc->sdtr_able & tidmask) && sdev->sdtr)
7695 advansys_wide_enable_sdtr(iop_base, tidmask);
7696 if (adv_dvc->chip_type == ADV_CHIP_ASC38C1600 && sdev->ppr)
7697 advansys_wide_enable_ppr(adv_dvc, iop_base, tidmask);
7700 * Tag Queuing is disabled for the BIOS which runs in polled
7701 * mode and would see no benefit from Tag Queuing. Also by
7702 * disabling Tag Queuing in the BIOS devices with Tag Queuing
7703 * bugs will at least work with the BIOS.
7705 if ((adv_dvc->tagqng_able & tidmask) &&
7706 sdev->tagged_supported) {
7707 unsigned short cfg_word;
7708 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, cfg_word);
7709 cfg_word |= tidmask;
7710 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
7712 AdvWriteByteLram(iop_base,
7713 ASC_MC_NUMBER_OF_MAX_CMD + sdev->id,
7714 adv_dvc->max_dvc_qng);
7718 if ((adv_dvc->tagqng_able & tidmask) && sdev->tagged_supported)
7719 scsi_change_queue_depth(sdev, adv_dvc->max_dvc_qng);
7723 * Set the number of commands to queue per device for the
7724 * specified host adapter.
7726 static int advansys_slave_configure(struct scsi_device *sdev)
7728 struct asc_board *boardp = shost_priv(sdev->host);
7730 if (ASC_NARROW_BOARD(boardp))
7731 advansys_narrow_slave_configure(sdev,
7732 &boardp->dvc_var.asc_dvc_var);
7734 advansys_wide_slave_configure(sdev,
7735 &boardp->dvc_var.adv_dvc_var);
7740 static __le32 advansys_get_sense_buffer_dma(struct scsi_cmnd *scp)
7742 struct asc_board *board = shost_priv(scp->device->host);
7743 scp->SCp.dma_handle = dma_map_single(board->dev, scp->sense_buffer,
7744 SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
7745 dma_cache_sync(board->dev, scp->sense_buffer,
7746 SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
7747 return cpu_to_le32(scp->SCp.dma_handle);
7750 static int asc_build_req(struct asc_board *boardp, struct scsi_cmnd *scp,
7751 struct asc_scsi_q *asc_scsi_q)
7753 struct asc_dvc_var *asc_dvc = &boardp->dvc_var.asc_dvc_var;
7757 memset(asc_scsi_q, 0, sizeof(*asc_scsi_q));
7760 * Set the srb_tag to the command tag + 1, as
7761 * srb_tag '0' is used internally by the chip.
7763 srb_tag = scp->request->tag + 1;
7764 asc_scsi_q->q2.srb_tag = srb_tag;
7767 * Build the ASC_SCSI_Q request.
7769 asc_scsi_q->cdbptr = &scp->cmnd[0];
7770 asc_scsi_q->q2.cdb_len = scp->cmd_len;
7771 asc_scsi_q->q1.target_id = ASC_TID_TO_TARGET_ID(scp->device->id);
7772 asc_scsi_q->q1.target_lun = scp->device->lun;
7773 asc_scsi_q->q2.target_ix =
7774 ASC_TIDLUN_TO_IX(scp->device->id, scp->device->lun);
7775 asc_scsi_q->q1.sense_addr = advansys_get_sense_buffer_dma(scp);
7776 asc_scsi_q->q1.sense_len = SCSI_SENSE_BUFFERSIZE;
7779 * If there are any outstanding requests for the current target,
7780 * then every 255th request send an ORDERED request. This heuristic
7781 * tries to retain the benefit of request sorting while preventing
7782 * request starvation. 255 is the max number of tags or pending commands
7783 * a device may have outstanding.
7785 * The request count is incremented below for every successfully
7789 if ((asc_dvc->cur_dvc_qng[scp->device->id] > 0) &&
7790 (boardp->reqcnt[scp->device->id] % 255) == 0) {
7791 asc_scsi_q->q2.tag_code = ORDERED_QUEUE_TAG;
7793 asc_scsi_q->q2.tag_code = SIMPLE_QUEUE_TAG;
7796 /* Build ASC_SCSI_Q */
7797 use_sg = scsi_dma_map(scp);
7800 struct scatterlist *slp;
7801 struct asc_sg_head *asc_sg_head;
7803 if (use_sg > scp->device->host->sg_tablesize) {
7804 scmd_printk(KERN_ERR, scp, "use_sg %d > "
7805 "sg_tablesize %d\n", use_sg,
7806 scp->device->host->sg_tablesize);
7807 scsi_dma_unmap(scp);
7808 scp->result = HOST_BYTE(DID_ERROR);
7812 asc_sg_head = kzalloc(sizeof(asc_scsi_q->sg_head) +
7813 use_sg * sizeof(struct asc_sg_list), GFP_ATOMIC);
7815 scsi_dma_unmap(scp);
7816 scp->result = HOST_BYTE(DID_SOFT_ERROR);
7820 asc_scsi_q->q1.cntl |= QC_SG_HEAD;
7821 asc_scsi_q->sg_head = asc_sg_head;
7822 asc_scsi_q->q1.data_cnt = 0;
7823 asc_scsi_q->q1.data_addr = 0;
7824 /* This is a byte value, otherwise it would need to be swapped. */
7825 asc_sg_head->entry_cnt = asc_scsi_q->q1.sg_queue_cnt = use_sg;
7826 ASC_STATS_ADD(scp->device->host, xfer_elem,
7827 asc_sg_head->entry_cnt);
7830 * Convert scatter-gather list into ASC_SG_HEAD list.
7832 scsi_for_each_sg(scp, slp, use_sg, sgcnt) {
7833 asc_sg_head->sg_list[sgcnt].addr =
7834 cpu_to_le32(sg_dma_address(slp));
7835 asc_sg_head->sg_list[sgcnt].bytes =
7836 cpu_to_le32(sg_dma_len(slp));
7837 ASC_STATS_ADD(scp->device->host, xfer_sect,
7838 DIV_ROUND_UP(sg_dma_len(slp), 512));
7842 ASC_STATS(scp->device->host, xfer_cnt);
7844 ASC_DBG_PRT_ASC_SCSI_Q(2, asc_scsi_q);
7845 ASC_DBG_PRT_CDB(1, scp->cmnd, scp->cmd_len);
7851 * Build scatter-gather list for Adv Library (Wide Board).
7853 * Additional ADV_SG_BLOCK structures will need to be allocated
7854 * if the total number of scatter-gather elements exceeds
7855 * NO_OF_SG_PER_BLOCK (15). The ADV_SG_BLOCK structures are
7856 * assumed to be physically contiguous.
7859 * ADV_SUCCESS(1) - SG List successfully created
7860 * ADV_ERROR(-1) - SG List creation failed
7863 adv_get_sglist(struct asc_board *boardp, adv_req_t *reqp,
7864 ADV_SCSI_REQ_Q *scsiqp, struct scsi_cmnd *scp, int use_sg)
7866 adv_sgblk_t *sgblkp, *prev_sgblkp;
7867 struct scatterlist *slp;
7869 ADV_SG_BLOCK *sg_block, *prev_sg_block;
7870 dma_addr_t sgblk_paddr;
7873 slp = scsi_sglist(scp);
7874 sg_elem_cnt = use_sg;
7876 prev_sg_block = NULL;
7877 reqp->sgblkp = NULL;
7881 * Allocate a 'adv_sgblk_t' structure from the board free
7882 * list. One 'adv_sgblk_t' structure holds NO_OF_SG_PER_BLOCK
7883 * (15) scatter-gather elements.
7885 sgblkp = dma_pool_alloc(boardp->adv_sgblk_pool, GFP_ATOMIC,
7888 ASC_DBG(1, "no free adv_sgblk_t\n");
7889 ASC_STATS(scp->device->host, adv_build_nosg);
7892 * Allocation failed. Free 'adv_sgblk_t' structures
7893 * already allocated for the request.
7895 while ((sgblkp = reqp->sgblkp) != NULL) {
7896 /* Remove 'sgblkp' from the request list. */
7897 reqp->sgblkp = sgblkp->next_sgblkp;
7898 sgblkp->next_sgblkp = NULL;
7899 dma_pool_free(boardp->adv_sgblk_pool, sgblkp,
7904 /* Complete 'adv_sgblk_t' board allocation. */
7905 sgblkp->sg_addr = sgblk_paddr;
7906 sgblkp->next_sgblkp = NULL;
7907 sg_block = &sgblkp->sg_block;
7910 * Check if this is the first 'adv_sgblk_t' for the
7913 if (reqp->sgblkp == NULL) {
7914 /* Request's first scatter-gather block. */
7915 reqp->sgblkp = sgblkp;
7918 * Set ADV_SCSI_REQ_T ADV_SG_BLOCK virtual and physical
7921 scsiqp->sg_list_ptr = sg_block;
7922 scsiqp->sg_real_addr = cpu_to_le32(sgblk_paddr);
7924 /* Request's second or later scatter-gather block. */
7925 prev_sgblkp->next_sgblkp = sgblkp;
7928 * Point the previous ADV_SG_BLOCK structure to
7929 * the newly allocated ADV_SG_BLOCK structure.
7931 prev_sg_block->sg_ptr = cpu_to_le32(sgblk_paddr);
7934 for (i = 0; i < NO_OF_SG_PER_BLOCK; i++) {
7935 sg_block->sg_list[i].sg_addr =
7936 cpu_to_le32(sg_dma_address(slp));
7937 sg_block->sg_list[i].sg_count =
7938 cpu_to_le32(sg_dma_len(slp));
7939 ASC_STATS_ADD(scp->device->host, xfer_sect,
7940 DIV_ROUND_UP(sg_dma_len(slp), 512));
7942 if (--sg_elem_cnt == 0) {
7944 * Last ADV_SG_BLOCK and scatter-gather entry.
7946 sg_block->sg_cnt = i + 1;
7947 sg_block->sg_ptr = 0L; /* Last ADV_SG_BLOCK in list. */
7952 sg_block->sg_cnt = NO_OF_SG_PER_BLOCK;
7953 prev_sg_block = sg_block;
7954 prev_sgblkp = sgblkp;
7959 * Build a request structure for the Adv Library (Wide Board).
7961 * If an adv_req_t can not be allocated to issue the request,
7962 * then return ASC_BUSY. If an error occurs, then return ASC_ERROR.
7964 * Multi-byte fields in the ASC_SCSI_REQ_Q that are used by the
7965 * microcode for DMA addresses or math operations are byte swapped
7966 * to little-endian order.
7969 adv_build_req(struct asc_board *boardp, struct scsi_cmnd *scp,
7970 adv_req_t **adv_reqpp)
7972 u32 srb_tag = scp->request->tag;
7974 ADV_SCSI_REQ_Q *scsiqp;
7977 dma_addr_t sense_addr;
7980 * Allocate an adv_req_t structure from the board to execute
7983 reqp = &boardp->adv_reqp[srb_tag];
7984 if (reqp->cmndp && reqp->cmndp != scp ) {
7985 ASC_DBG(1, "no free adv_req_t\n");
7986 ASC_STATS(scp->device->host, adv_build_noreq);
7990 reqp->req_addr = boardp->adv_reqp_addr + (srb_tag * sizeof(adv_req_t));
7992 scsiqp = &reqp->scsi_req_q;
7995 * Initialize the structure.
7997 scsiqp->cntl = scsiqp->scsi_cntl = scsiqp->done_status = 0;
8000 * Set the srb_tag to the command tag.
8002 scsiqp->srb_tag = srb_tag;
8005 * Set 'host_scribble' to point to the adv_req_t structure.
8008 scp->host_scribble = (void *)reqp;
8011 * Build the ADV_SCSI_REQ_Q request.
8014 /* Set CDB length and copy it to the request structure. */
8015 scsiqp->cdb_len = scp->cmd_len;
8016 /* Copy first 12 CDB bytes to cdb[]. */
8017 memcpy(scsiqp->cdb, scp->cmnd, scp->cmd_len < 12 ? scp->cmd_len : 12);
8018 /* Copy last 4 CDB bytes, if present, to cdb16[]. */
8019 if (scp->cmd_len > 12) {
8020 int cdb16_len = scp->cmd_len - 12;
8022 memcpy(scsiqp->cdb16, &scp->cmnd[12], cdb16_len);
8025 scsiqp->target_id = scp->device->id;
8026 scsiqp->target_lun = scp->device->lun;
8028 sense_addr = dma_map_single(boardp->dev, scp->sense_buffer,
8029 SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
8030 scsiqp->sense_addr = cpu_to_le32(sense_addr);
8031 scsiqp->sense_len = cpu_to_le32(SCSI_SENSE_BUFFERSIZE);
8033 /* Build ADV_SCSI_REQ_Q */
8035 use_sg = scsi_dma_map(scp);
8037 /* Zero-length transfer */
8038 reqp->sgblkp = NULL;
8039 scsiqp->data_cnt = 0;
8041 scsiqp->data_addr = 0;
8042 scsiqp->sg_list_ptr = NULL;
8043 scsiqp->sg_real_addr = 0;
8045 if (use_sg > ADV_MAX_SG_LIST) {
8046 scmd_printk(KERN_ERR, scp, "use_sg %d > "
8047 "ADV_MAX_SG_LIST %d\n", use_sg,
8048 scp->device->host->sg_tablesize);
8049 scsi_dma_unmap(scp);
8050 scp->result = HOST_BYTE(DID_ERROR);
8052 scp->host_scribble = NULL;
8057 scsiqp->data_cnt = cpu_to_le32(scsi_bufflen(scp));
8059 ret = adv_get_sglist(boardp, reqp, scsiqp, scp, use_sg);
8060 if (ret != ADV_SUCCESS) {
8061 scsi_dma_unmap(scp);
8062 scp->result = HOST_BYTE(DID_ERROR);
8064 scp->host_scribble = NULL;
8069 ASC_STATS_ADD(scp->device->host, xfer_elem, use_sg);
8072 ASC_STATS(scp->device->host, xfer_cnt);
8074 ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp);
8075 ASC_DBG_PRT_CDB(1, scp->cmnd, scp->cmd_len);
8082 static int AscSgListToQueue(int sg_list)
8086 n_sg_list_qs = ((sg_list - 1) / ASC_SG_LIST_PER_Q);
8087 if (((sg_list - 1) % ASC_SG_LIST_PER_Q) != 0)
8089 return n_sg_list_qs + 1;
8093 AscGetNumOfFreeQueue(ASC_DVC_VAR *asc_dvc, uchar target_ix, uchar n_qs)
8097 ASC_SCSI_BIT_ID_TYPE target_id;
8100 target_id = ASC_TIX_TO_TARGET_ID(target_ix);
8101 tid_no = ASC_TIX_TO_TID(target_ix);
8102 if ((asc_dvc->unit_not_ready & target_id) ||
8103 (asc_dvc->queue_full_or_busy & target_id)) {
8107 cur_used_qs = (uint) asc_dvc->cur_total_qng +
8108 (uint) asc_dvc->last_q_shortage + (uint) ASC_MIN_FREE_Q;
8110 cur_used_qs = (uint) asc_dvc->cur_total_qng +
8111 (uint) ASC_MIN_FREE_Q;
8113 if ((uint) (cur_used_qs + n_qs) <= (uint) asc_dvc->max_total_qng) {
8114 cur_free_qs = (uint) asc_dvc->max_total_qng - cur_used_qs;
8115 if (asc_dvc->cur_dvc_qng[tid_no] >=
8116 asc_dvc->max_dvc_qng[tid_no]) {
8122 if ((n_qs > asc_dvc->last_q_shortage)
8123 && (n_qs <= (asc_dvc->max_total_qng - ASC_MIN_FREE_Q))) {
8124 asc_dvc->last_q_shortage = n_qs;
8130 static uchar AscAllocFreeQueue(PortAddr iop_base, uchar free_q_head)
8136 q_addr = ASC_QNO_TO_QADDR(free_q_head);
8137 q_status = (uchar)AscReadLramByte(iop_base,
8139 ASC_SCSIQ_B_STATUS));
8140 next_qp = AscReadLramByte(iop_base, (ushort)(q_addr + ASC_SCSIQ_B_FWD));
8141 if (((q_status & QS_READY) == 0) && (next_qp != ASC_QLINK_END))
8143 return ASC_QLINK_END;
8147 AscAllocMultipleFreeQueue(PortAddr iop_base, uchar free_q_head, uchar n_free_q)
8151 for (i = 0; i < n_free_q; i++) {
8152 free_q_head = AscAllocFreeQueue(iop_base, free_q_head);
8153 if (free_q_head == ASC_QLINK_END)
8161 * DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words)
8163 * Calling/Exit State:
8167 * Output an ASC_SCSI_Q structure to the chip
8170 DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words)
8174 ASC_DBG_PRT_HEX(2, "DvcPutScsiQ", outbuf, 2 * words);
8175 AscSetChipLramAddr(iop_base, s_addr);
8176 for (i = 0; i < 2 * words; i += 2) {
8177 if (i == 4 || i == 20) {
8180 outpw(iop_base + IOP_RAM_DATA,
8181 ((ushort)outbuf[i + 1] << 8) | outbuf[i]);
8185 static int AscPutReadyQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar q_no)
8190 uchar syn_period_ix;
8194 iop_base = asc_dvc->iop_base;
8195 if (((asc_dvc->init_sdtr & scsiq->q1.target_id) != 0) &&
8196 ((asc_dvc->sdtr_done & scsiq->q1.target_id) == 0)) {
8197 tid_no = ASC_TIX_TO_TID(scsiq->q2.target_ix);
8198 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
8200 (sdtr_data >> 4) & (asc_dvc->max_sdtr_index - 1);
8201 syn_offset = sdtr_data & ASC_SYN_MAX_OFFSET;
8202 AscMsgOutSDTR(asc_dvc,
8203 asc_dvc->sdtr_period_tbl[syn_period_ix],
8205 scsiq->q1.cntl |= QC_MSG_OUT;
8207 q_addr = ASC_QNO_TO_QADDR(q_no);
8208 if ((scsiq->q1.target_id & asc_dvc->use_tagged_qng) == 0) {
8209 scsiq->q2.tag_code &= ~SIMPLE_QUEUE_TAG;
8211 scsiq->q1.status = QS_FREE;
8212 AscMemWordCopyPtrToLram(iop_base,
8213 q_addr + ASC_SCSIQ_CDB_BEG,
8214 (uchar *)scsiq->cdbptr, scsiq->q2.cdb_len >> 1);
8216 DvcPutScsiQ(iop_base,
8217 q_addr + ASC_SCSIQ_CPY_BEG,
8218 (uchar *)&scsiq->q1.cntl,
8219 ((sizeof(ASC_SCSIQ_1) + sizeof(ASC_SCSIQ_2)) / 2) - 1);
8220 AscWriteLramWord(iop_base,
8221 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_STATUS),
8222 (ushort)(((ushort)scsiq->q1.
8223 q_no << 8) | (ushort)QS_READY));
8228 AscPutReadySgListQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar q_no)
8232 ASC_SG_HEAD *sg_head;
8233 ASC_SG_LIST_Q scsi_sg_q;
8234 __le32 saved_data_addr;
8235 __le32 saved_data_cnt;
8237 ushort sg_list_dwords;
8239 ushort sg_entry_cnt;
8243 iop_base = asc_dvc->iop_base;
8244 sg_head = scsiq->sg_head;
8245 saved_data_addr = scsiq->q1.data_addr;
8246 saved_data_cnt = scsiq->q1.data_cnt;
8247 scsiq->q1.data_addr = sg_head->sg_list[0].addr;
8248 scsiq->q1.data_cnt = sg_head->sg_list[0].bytes;
8249 #if CC_VERY_LONG_SG_LIST
8251 * If sg_head->entry_cnt is greater than ASC_MAX_SG_LIST
8252 * then not all SG elements will fit in the allocated queues.
8253 * The rest of the SG elements will be copied when the RISC
8254 * completes the SG elements that fit and halts.
8256 if (sg_head->entry_cnt > ASC_MAX_SG_LIST) {
8258 * Set sg_entry_cnt to be the number of SG elements that
8259 * will fit in the allocated SG queues. It is minus 1, because
8260 * the first SG element is handled above. ASC_MAX_SG_LIST is
8261 * already inflated by 1 to account for this. For example it
8262 * may be 50 which is 1 + 7 queues * 7 SG elements.
8264 sg_entry_cnt = ASC_MAX_SG_LIST - 1;
8267 * Keep track of remaining number of SG elements that will
8268 * need to be handled from a_isr.c.
8270 scsiq->remain_sg_entry_cnt =
8271 sg_head->entry_cnt - ASC_MAX_SG_LIST;
8273 #endif /* CC_VERY_LONG_SG_LIST */
8275 * Set sg_entry_cnt to be the number of SG elements that
8276 * will fit in the allocated SG queues. It is minus 1, because
8277 * the first SG element is handled above.
8279 sg_entry_cnt = sg_head->entry_cnt - 1;
8280 #if CC_VERY_LONG_SG_LIST
8282 #endif /* CC_VERY_LONG_SG_LIST */
8283 if (sg_entry_cnt != 0) {
8284 scsiq->q1.cntl |= QC_SG_HEAD;
8285 q_addr = ASC_QNO_TO_QADDR(q_no);
8287 scsiq->q1.sg_queue_cnt = sg_head->queue_cnt;
8288 scsi_sg_q.sg_head_qp = q_no;
8289 scsi_sg_q.cntl = QCSG_SG_XFER_LIST;
8290 for (i = 0; i < sg_head->queue_cnt; i++) {
8291 scsi_sg_q.seq_no = i + 1;
8292 if (sg_entry_cnt > ASC_SG_LIST_PER_Q) {
8293 sg_list_dwords = (uchar)(ASC_SG_LIST_PER_Q * 2);
8294 sg_entry_cnt -= ASC_SG_LIST_PER_Q;
8296 scsi_sg_q.sg_list_cnt =
8298 scsi_sg_q.sg_cur_list_cnt =
8301 scsi_sg_q.sg_list_cnt =
8302 ASC_SG_LIST_PER_Q - 1;
8303 scsi_sg_q.sg_cur_list_cnt =
8304 ASC_SG_LIST_PER_Q - 1;
8307 #if CC_VERY_LONG_SG_LIST
8309 * This is the last SG queue in the list of
8310 * allocated SG queues. If there are more
8311 * SG elements than will fit in the allocated
8312 * queues, then set the QCSG_SG_XFER_MORE flag.
8314 if (sg_head->entry_cnt > ASC_MAX_SG_LIST) {
8315 scsi_sg_q.cntl |= QCSG_SG_XFER_MORE;
8317 #endif /* CC_VERY_LONG_SG_LIST */
8318 scsi_sg_q.cntl |= QCSG_SG_XFER_END;
8319 #if CC_VERY_LONG_SG_LIST
8321 #endif /* CC_VERY_LONG_SG_LIST */
8322 sg_list_dwords = sg_entry_cnt << 1;
8324 scsi_sg_q.sg_list_cnt = sg_entry_cnt;
8325 scsi_sg_q.sg_cur_list_cnt =
8328 scsi_sg_q.sg_list_cnt =
8330 scsi_sg_q.sg_cur_list_cnt =
8335 next_qp = AscReadLramByte(iop_base,
8338 scsi_sg_q.q_no = next_qp;
8339 q_addr = ASC_QNO_TO_QADDR(next_qp);
8340 AscMemWordCopyPtrToLram(iop_base,
8341 q_addr + ASC_SCSIQ_SGHD_CPY_BEG,
8342 (uchar *)&scsi_sg_q,
8343 sizeof(ASC_SG_LIST_Q) >> 1);
8344 AscMemDWordCopyPtrToLram(iop_base,
8345 q_addr + ASC_SGQ_LIST_BEG,
8349 sg_index += ASC_SG_LIST_PER_Q;
8350 scsiq->next_sg_index = sg_index;
8353 scsiq->q1.cntl &= ~QC_SG_HEAD;
8355 sta = AscPutReadyQueue(asc_dvc, scsiq, q_no);
8356 scsiq->q1.data_addr = saved_data_addr;
8357 scsiq->q1.data_cnt = saved_data_cnt;
8362 AscSendScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar n_q_required)
8371 iop_base = asc_dvc->iop_base;
8372 target_ix = scsiq->q2.target_ix;
8373 tid_no = ASC_TIX_TO_TID(target_ix);
8375 free_q_head = (uchar)AscGetVarFreeQHead(iop_base);
8376 if (n_q_required > 1) {
8377 next_qp = AscAllocMultipleFreeQueue(iop_base, free_q_head,
8378 (uchar)n_q_required);
8379 if (next_qp != ASC_QLINK_END) {
8380 asc_dvc->last_q_shortage = 0;
8381 scsiq->sg_head->queue_cnt = n_q_required - 1;
8382 scsiq->q1.q_no = free_q_head;
8383 sta = AscPutReadySgListQueue(asc_dvc, scsiq,
8386 } else if (n_q_required == 1) {
8387 next_qp = AscAllocFreeQueue(iop_base, free_q_head);
8388 if (next_qp != ASC_QLINK_END) {
8389 scsiq->q1.q_no = free_q_head;
8390 sta = AscPutReadyQueue(asc_dvc, scsiq, free_q_head);
8394 AscPutVarFreeQHead(iop_base, next_qp);
8395 asc_dvc->cur_total_qng += n_q_required;
8396 asc_dvc->cur_dvc_qng[tid_no]++;
8401 #define ASC_SYN_OFFSET_ONE_DISABLE_LIST 16
8402 static uchar _syn_offset_one_disable_cmd[ASC_SYN_OFFSET_ONE_DISABLE_LIST] = {
8421 static int AscExeScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq)
8426 int disable_syn_offset_one_fix;
8429 ushort sg_entry_cnt = 0;
8430 ushort sg_entry_cnt_minus_one = 0;
8437 ASC_SG_HEAD *sg_head;
8438 unsigned long data_cnt;
8440 iop_base = asc_dvc->iop_base;
8441 sg_head = scsiq->sg_head;
8442 if (asc_dvc->err_code != 0)
8445 if ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0) {
8446 scsiq->q1.extra_bytes = 0;
8449 target_ix = scsiq->q2.target_ix;
8450 tid_no = ASC_TIX_TO_TID(target_ix);
8452 if (scsiq->cdbptr[0] == REQUEST_SENSE) {
8453 if ((asc_dvc->init_sdtr & scsiq->q1.target_id) != 0) {
8454 asc_dvc->sdtr_done &= ~scsiq->q1.target_id;
8455 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
8456 AscMsgOutSDTR(asc_dvc,
8458 sdtr_period_tbl[(sdtr_data >> 4) &
8462 (uchar)(sdtr_data & (uchar)
8463 ASC_SYN_MAX_OFFSET));
8464 scsiq->q1.cntl |= (QC_MSG_OUT | QC_URGENT);
8467 if (asc_dvc->in_critical_cnt != 0) {
8468 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_CRITICAL_RE_ENTRY);
8471 asc_dvc->in_critical_cnt++;
8472 if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) {
8473 if ((sg_entry_cnt = sg_head->entry_cnt) == 0) {
8474 asc_dvc->in_critical_cnt--;
8477 #if !CC_VERY_LONG_SG_LIST
8478 if (sg_entry_cnt > ASC_MAX_SG_LIST) {
8479 asc_dvc->in_critical_cnt--;
8482 #endif /* !CC_VERY_LONG_SG_LIST */
8483 if (sg_entry_cnt == 1) {
8484 scsiq->q1.data_addr = sg_head->sg_list[0].addr;
8485 scsiq->q1.data_cnt = sg_head->sg_list[0].bytes;
8486 scsiq->q1.cntl &= ~(QC_SG_HEAD | QC_SG_SWAP_QUEUE);
8488 sg_entry_cnt_minus_one = sg_entry_cnt - 1;
8490 scsi_cmd = scsiq->cdbptr[0];
8491 disable_syn_offset_one_fix = FALSE;
8492 if ((asc_dvc->pci_fix_asyn_xfer & scsiq->q1.target_id) &&
8493 !(asc_dvc->pci_fix_asyn_xfer_always & scsiq->q1.target_id)) {
8494 if (scsiq->q1.cntl & QC_SG_HEAD) {
8496 for (i = 0; i < sg_entry_cnt; i++) {
8497 data_cnt += le32_to_cpu(sg_head->sg_list[i].
8501 data_cnt = le32_to_cpu(scsiq->q1.data_cnt);
8503 if (data_cnt != 0UL) {
8504 if (data_cnt < 512UL) {
8505 disable_syn_offset_one_fix = TRUE;
8507 for (i = 0; i < ASC_SYN_OFFSET_ONE_DISABLE_LIST;
8510 _syn_offset_one_disable_cmd[i];
8511 if (disable_cmd == 0xFF) {
8514 if (scsi_cmd == disable_cmd) {
8515 disable_syn_offset_one_fix =
8523 if (disable_syn_offset_one_fix) {
8524 scsiq->q2.tag_code &= ~SIMPLE_QUEUE_TAG;
8525 scsiq->q2.tag_code |= (ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX |
8526 ASC_TAG_FLAG_DISABLE_DISCONNECT);
8528 scsiq->q2.tag_code &= 0x27;
8530 if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) {
8531 if (asc_dvc->bug_fix_cntl) {
8532 if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) {
8533 if ((scsi_cmd == READ_6) ||
8534 (scsi_cmd == READ_10)) {
8535 addr = le32_to_cpu(sg_head->
8537 [sg_entry_cnt_minus_one].
8539 le32_to_cpu(sg_head->
8541 [sg_entry_cnt_minus_one].
8544 (uchar)((ushort)addr & 0x0003);
8545 if ((extra_bytes != 0)
8549 ASC_TAG_FLAG_EXTRA_BYTES)
8551 scsiq->q2.tag_code |=
8552 ASC_TAG_FLAG_EXTRA_BYTES;
8553 scsiq->q1.extra_bytes =
8556 le32_to_cpu(sg_head->
8558 [sg_entry_cnt_minus_one].
8560 data_cnt -= extra_bytes;
8563 [sg_entry_cnt_minus_one].
8565 cpu_to_le32(data_cnt);
8570 sg_head->entry_to_copy = sg_head->entry_cnt;
8571 #if CC_VERY_LONG_SG_LIST
8573 * Set the sg_entry_cnt to the maximum possible. The rest of
8574 * the SG elements will be copied when the RISC completes the
8575 * SG elements that fit and halts.
8577 if (sg_entry_cnt > ASC_MAX_SG_LIST) {
8578 sg_entry_cnt = ASC_MAX_SG_LIST;
8580 #endif /* CC_VERY_LONG_SG_LIST */
8581 n_q_required = AscSgListToQueue(sg_entry_cnt);
8582 if ((AscGetNumOfFreeQueue(asc_dvc, target_ix, n_q_required) >=
8583 (uint) n_q_required)
8584 || ((scsiq->q1.cntl & QC_URGENT) != 0)) {
8586 AscSendScsiQueue(asc_dvc, scsiq,
8587 n_q_required)) == 1) {
8588 asc_dvc->in_critical_cnt--;
8593 if (asc_dvc->bug_fix_cntl) {
8594 if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) {
8595 if ((scsi_cmd == READ_6) ||
8596 (scsi_cmd == READ_10)) {
8598 le32_to_cpu(scsiq->q1.data_addr) +
8599 le32_to_cpu(scsiq->q1.data_cnt);
8601 (uchar)((ushort)addr & 0x0003);
8602 if ((extra_bytes != 0)
8606 ASC_TAG_FLAG_EXTRA_BYTES)
8609 le32_to_cpu(scsiq->q1.
8611 if (((ushort)data_cnt & 0x01FF)
8613 scsiq->q2.tag_code |=
8614 ASC_TAG_FLAG_EXTRA_BYTES;
8615 data_cnt -= extra_bytes;
8616 scsiq->q1.data_cnt =
8619 scsiq->q1.extra_bytes =
8627 if ((AscGetNumOfFreeQueue(asc_dvc, target_ix, 1) >= 1) ||
8628 ((scsiq->q1.cntl & QC_URGENT) != 0)) {
8629 if ((sta = AscSendScsiQueue(asc_dvc, scsiq,
8630 n_q_required)) == 1) {
8631 asc_dvc->in_critical_cnt--;
8636 asc_dvc->in_critical_cnt--;
8641 * AdvExeScsiQueue() - Send a request to the RISC microcode program.
8643 * Allocate a carrier structure, point the carrier to the ADV_SCSI_REQ_Q,
8644 * add the carrier to the ICQ (Initiator Command Queue), and tickle the
8645 * RISC to notify it a new command is ready to be executed.
8647 * If 'done_status' is not set to QD_DO_RETRY, then 'error_retry' will be
8648 * set to SCSI_MAX_RETRY.
8650 * Multi-byte fields in the ASC_SCSI_REQ_Q that are used by the microcode
8651 * for DMA addresses or math operations are byte swapped to little-endian
8655 * ADV_SUCCESS(1) - The request was successfully queued.
8656 * ADV_BUSY(0) - Resource unavailable; Retry again after pending
8657 * request completes.
8658 * ADV_ERROR(-1) - Invalid ADV_SCSI_REQ_Q request structure
8661 static int AdvExeScsiQueue(ADV_DVC_VAR *asc_dvc, adv_req_t *reqp)
8663 AdvPortAddr iop_base;
8664 ADV_CARR_T *new_carrp;
8665 ADV_SCSI_REQ_Q *scsiq = &reqp->scsi_req_q;
8668 * The ADV_SCSI_REQ_Q 'target_id' field should never exceed ADV_MAX_TID.
8670 if (scsiq->target_id > ADV_MAX_TID) {
8671 scsiq->host_status = QHSTA_M_INVALID_DEVICE;
8672 scsiq->done_status = QD_WITH_ERROR;
8676 iop_base = asc_dvc->iop_base;
8679 * Allocate a carrier ensuring at least one carrier always
8680 * remains on the freelist and initialize fields.
8682 new_carrp = adv_get_next_carrier(asc_dvc);
8684 ASC_DBG(1, "No free carriers\n");
8688 asc_dvc->carr_pending_cnt++;
8691 * Clear the ADV_SCSI_REQ_Q done flag.
8693 scsiq->a_flag &= ~ADV_SCSIQ_DONE;
8695 /* Save virtual and physical address of ADV_SCSI_REQ_Q and carrier. */
8696 scsiq->scsiq_ptr = cpu_to_le32(scsiq->srb_tag);
8697 scsiq->scsiq_rptr = cpu_to_le32(reqp->req_addr);
8699 scsiq->carr_va = asc_dvc->icq_sp->carr_va;
8700 scsiq->carr_pa = asc_dvc->icq_sp->carr_pa;
8703 * Use the current stopper to send the ADV_SCSI_REQ_Q command to
8704 * the microcode. The newly allocated stopper will become the new
8707 asc_dvc->icq_sp->areq_vpa = scsiq->scsiq_rptr;
8710 * Set the 'next_vpa' pointer for the old stopper to be the
8711 * physical address of the new stopper. The RISC can only
8712 * follow physical addresses.
8714 asc_dvc->icq_sp->next_vpa = new_carrp->carr_pa;
8717 * Set the host adapter stopper pointer to point to the new carrier.
8719 asc_dvc->icq_sp = new_carrp;
8721 if (asc_dvc->chip_type == ADV_CHIP_ASC3550 ||
8722 asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
8724 * Tickle the RISC to tell it to read its Command Queue Head pointer.
8726 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_A);
8727 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
8729 * Clear the tickle value. In the ASC-3550 the RISC flag
8730 * command 'clr_tickle_a' does not work unless the host
8733 AdvWriteByteRegister(iop_base, IOPB_TICKLE,
8736 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
8738 * Notify the RISC a carrier is ready by writing the physical
8739 * address of the new carrier stopper to the COMMA register.
8741 AdvWriteDWordRegister(iop_base, IOPDW_COMMA,
8742 le32_to_cpu(new_carrp->carr_pa));
8749 * Execute a single 'Scsi_Cmnd'.
8751 static int asc_execute_scsi_cmnd(struct scsi_cmnd *scp)
8754 struct asc_board *boardp = shost_priv(scp->device->host);
8756 ASC_DBG(1, "scp 0x%p\n", scp);
8758 if (ASC_NARROW_BOARD(boardp)) {
8759 ASC_DVC_VAR *asc_dvc = &boardp->dvc_var.asc_dvc_var;
8760 struct asc_scsi_q asc_scsi_q;
8762 /* asc_build_req() can not return ASC_BUSY. */
8763 ret = asc_build_req(boardp, scp, &asc_scsi_q);
8764 if (ret == ASC_ERROR) {
8765 ASC_STATS(scp->device->host, build_error);
8769 ret = AscExeScsiQueue(asc_dvc, &asc_scsi_q);
8770 kfree(asc_scsi_q.sg_head);
8771 err_code = asc_dvc->err_code;
8773 ADV_DVC_VAR *adv_dvc = &boardp->dvc_var.adv_dvc_var;
8774 adv_req_t *adv_reqp;
8776 switch (adv_build_req(boardp, scp, &adv_reqp)) {
8778 ASC_DBG(3, "adv_build_req ASC_NOERROR\n");
8781 ASC_DBG(1, "adv_build_req ASC_BUSY\n");
8783 * The asc_stats fields 'adv_build_noreq' and
8784 * 'adv_build_nosg' count wide board busy conditions.
8785 * They are updated in adv_build_req and
8786 * adv_get_sglist, respectively.
8791 ASC_DBG(1, "adv_build_req ASC_ERROR\n");
8792 ASC_STATS(scp->device->host, build_error);
8796 ret = AdvExeScsiQueue(adv_dvc, adv_reqp);
8797 err_code = adv_dvc->err_code;
8802 ASC_STATS(scp->device->host, exe_noerror);
8804 * Increment monotonically increasing per device
8805 * successful request counter. Wrapping doesn't matter.
8807 boardp->reqcnt[scp->device->id]++;
8808 ASC_DBG(1, "ExeScsiQueue() ASC_NOERROR\n");
8811 ASC_DBG(1, "ExeScsiQueue() ASC_BUSY\n");
8812 ASC_STATS(scp->device->host, exe_busy);
8815 scmd_printk(KERN_ERR, scp, "ExeScsiQueue() ASC_ERROR, "
8816 "err_code 0x%x\n", err_code);
8817 ASC_STATS(scp->device->host, exe_error);
8818 scp->result = HOST_BYTE(DID_ERROR);
8821 scmd_printk(KERN_ERR, scp, "ExeScsiQueue() unknown, "
8822 "err_code 0x%x\n", err_code);
8823 ASC_STATS(scp->device->host, exe_unknown);
8824 scp->result = HOST_BYTE(DID_ERROR);
8828 ASC_DBG(1, "end\n");
8833 * advansys_queuecommand() - interrupt-driven I/O entrypoint.
8835 * This function always returns 0. Command return status is saved
8836 * in the 'scp' result field.
8839 advansys_queuecommand_lck(struct scsi_cmnd *scp, void (*done)(struct scsi_cmnd *))
8841 struct Scsi_Host *shost = scp->device->host;
8842 int asc_res, result = 0;
8844 ASC_STATS(shost, queuecommand);
8845 scp->scsi_done = done;
8847 asc_res = asc_execute_scsi_cmnd(scp);
8853 result = SCSI_MLQUEUE_HOST_BUSY;
8864 static DEF_SCSI_QCMD(advansys_queuecommand)
8866 static ushort AscGetEisaChipCfg(PortAddr iop_base)
8868 PortAddr eisa_cfg_iop = (PortAddr) ASC_GET_EISA_SLOT(iop_base) |
8869 (PortAddr) (ASC_EISA_CFG_IOP_MASK);
8870 return inpw(eisa_cfg_iop);
8874 * Return the BIOS address of the adapter at the specified
8875 * I/O port and with the specified bus type.
8877 static unsigned short AscGetChipBiosAddress(PortAddr iop_base,
8878 unsigned short bus_type)
8880 unsigned short cfg_lsw;
8881 unsigned short bios_addr;
8884 * The PCI BIOS is re-located by the motherboard BIOS. Because
8885 * of this the driver can not determine where a PCI BIOS is
8886 * loaded and executes.
8888 if (bus_type & ASC_IS_PCI)
8891 if ((bus_type & ASC_IS_EISA) != 0) {
8892 cfg_lsw = AscGetEisaChipCfg(iop_base);
8894 bios_addr = ASC_BIOS_MIN_ADDR + cfg_lsw * ASC_BIOS_BANK_SIZE;
8898 cfg_lsw = AscGetChipCfgLsw(iop_base);
8901 * ISA PnP uses the top bit as the 32K BIOS flag
8903 if (bus_type == ASC_IS_ISAPNP)
8905 bios_addr = ASC_BIOS_MIN_ADDR + (cfg_lsw >> 12) * ASC_BIOS_BANK_SIZE;
8909 static uchar AscSetChipScsiID(PortAddr iop_base, uchar new_host_id)
8913 if (AscGetChipScsiID(iop_base) == new_host_id) {
8914 return (new_host_id);
8916 cfg_lsw = AscGetChipCfgLsw(iop_base);
8918 cfg_lsw |= (ushort)((new_host_id & ASC_MAX_TID) << 8);
8919 AscSetChipCfgLsw(iop_base, cfg_lsw);
8920 return (AscGetChipScsiID(iop_base));
8923 static unsigned char AscGetChipScsiCtrl(PortAddr iop_base)
8927 AscSetBank(iop_base, 1);
8928 sc = inp(iop_base + IOP_REG_SC);
8929 AscSetBank(iop_base, 0);
8933 static unsigned char AscGetChipVersion(PortAddr iop_base,
8934 unsigned short bus_type)
8936 if (bus_type & ASC_IS_EISA) {
8938 unsigned char revision;
8939 eisa_iop = (PortAddr) ASC_GET_EISA_SLOT(iop_base) |
8940 (PortAddr) ASC_EISA_REV_IOP_MASK;
8941 revision = inp(eisa_iop);
8942 return ASC_CHIP_MIN_VER_EISA - 1 + revision;
8944 return AscGetChipVerNo(iop_base);
8948 static void AscEnableIsaDma(uchar dma_channel)
8950 if (dma_channel < 4) {
8951 outp(0x000B, (ushort)(0xC0 | dma_channel));
8952 outp(0x000A, dma_channel);
8953 } else if (dma_channel < 8) {
8954 outp(0x00D6, (ushort)(0xC0 | (dma_channel - 4)));
8955 outp(0x00D4, (ushort)(dma_channel - 4));
8958 #endif /* CONFIG_ISA */
8960 static int AscStopQueueExe(PortAddr iop_base)
8964 if (AscReadLramByte(iop_base, ASCV_STOP_CODE_B) == 0) {
8965 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B,
8966 ASC_STOP_REQ_RISC_STOP);
8968 if (AscReadLramByte(iop_base, ASCV_STOP_CODE_B) &
8969 ASC_STOP_ACK_RISC_STOP) {
8973 } while (count++ < 20);
8978 static unsigned int AscGetMaxDmaCount(ushort bus_type)
8980 if (bus_type & ASC_IS_ISA)
8981 return ASC_MAX_ISA_DMA_COUNT;
8982 else if (bus_type & (ASC_IS_EISA | ASC_IS_VL))
8983 return ASC_MAX_VL_DMA_COUNT;
8984 return ASC_MAX_PCI_DMA_COUNT;
8988 static ushort AscGetIsaDmaChannel(PortAddr iop_base)
8992 channel = AscGetChipCfgLsw(iop_base) & 0x0003;
8993 if (channel == 0x03)
8995 else if (channel == 0x00)
8997 return (channel + 4);
9000 static ushort AscSetIsaDmaChannel(PortAddr iop_base, ushort dma_channel)
9005 if ((dma_channel >= 5) && (dma_channel <= 7)) {
9006 if (dma_channel == 7)
9009 value = dma_channel - 4;
9010 cfg_lsw = AscGetChipCfgLsw(iop_base) & 0xFFFC;
9012 AscSetChipCfgLsw(iop_base, cfg_lsw);
9013 return (AscGetIsaDmaChannel(iop_base));
9018 static uchar AscGetIsaDmaSpeed(PortAddr iop_base)
9022 AscSetBank(iop_base, 1);
9023 speed_value = AscReadChipDmaSpeed(iop_base);
9024 speed_value &= 0x07;
9025 AscSetBank(iop_base, 0);
9029 static uchar AscSetIsaDmaSpeed(PortAddr iop_base, uchar speed_value)
9031 speed_value &= 0x07;
9032 AscSetBank(iop_base, 1);
9033 AscWriteChipDmaSpeed(iop_base, speed_value);
9034 AscSetBank(iop_base, 0);
9035 return AscGetIsaDmaSpeed(iop_base);
9037 #endif /* CONFIG_ISA */
9039 static ushort AscInitAscDvcVar(ASC_DVC_VAR *asc_dvc)
9046 iop_base = asc_dvc->iop_base;
9048 asc_dvc->err_code = 0;
9049 if ((asc_dvc->bus_type &
9050 (ASC_IS_ISA | ASC_IS_PCI | ASC_IS_EISA | ASC_IS_VL)) == 0) {
9051 asc_dvc->err_code |= ASC_IERR_NO_BUS_TYPE;
9053 AscSetChipControl(iop_base, CC_HALT);
9054 AscSetChipStatus(iop_base, 0);
9055 asc_dvc->bug_fix_cntl = 0;
9056 asc_dvc->pci_fix_asyn_xfer = 0;
9057 asc_dvc->pci_fix_asyn_xfer_always = 0;
9058 /* asc_dvc->init_state initialized in AscInitGetConfig(). */
9059 asc_dvc->sdtr_done = 0;
9060 asc_dvc->cur_total_qng = 0;
9061 asc_dvc->is_in_int = 0;
9062 asc_dvc->in_critical_cnt = 0;
9063 asc_dvc->last_q_shortage = 0;
9064 asc_dvc->use_tagged_qng = 0;
9065 asc_dvc->no_scam = 0;
9066 asc_dvc->unit_not_ready = 0;
9067 asc_dvc->queue_full_or_busy = 0;
9068 asc_dvc->redo_scam = 0;
9070 asc_dvc->min_sdtr_index = 0;
9071 asc_dvc->cfg->can_tagged_qng = 0;
9072 asc_dvc->cfg->cmd_qng_enabled = 0;
9073 asc_dvc->dvc_cntl = ASC_DEF_DVC_CNTL;
9074 asc_dvc->init_sdtr = 0;
9075 asc_dvc->max_total_qng = ASC_DEF_MAX_TOTAL_QNG;
9076 asc_dvc->scsi_reset_wait = 3;
9077 asc_dvc->start_motor = ASC_SCSI_WIDTH_BIT_SET;
9078 asc_dvc->max_dma_count = AscGetMaxDmaCount(asc_dvc->bus_type);
9079 asc_dvc->cfg->sdtr_enable = ASC_SCSI_WIDTH_BIT_SET;
9080 asc_dvc->cfg->disc_enable = ASC_SCSI_WIDTH_BIT_SET;
9081 asc_dvc->cfg->chip_scsi_id = ASC_DEF_CHIP_SCSI_ID;
9082 chip_version = AscGetChipVersion(iop_base, asc_dvc->bus_type);
9083 asc_dvc->cfg->chip_version = chip_version;
9084 asc_dvc->sdtr_period_tbl = asc_syn_xfer_period;
9085 asc_dvc->max_sdtr_index = 7;
9086 if ((asc_dvc->bus_type & ASC_IS_PCI) &&
9087 (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3150)) {
9088 asc_dvc->bus_type = ASC_IS_PCI_ULTRA;
9089 asc_dvc->sdtr_period_tbl = asc_syn_ultra_xfer_period;
9090 asc_dvc->max_sdtr_index = 15;
9091 if (chip_version == ASC_CHIP_VER_PCI_ULTRA_3150) {
9092 AscSetExtraControl(iop_base,
9093 (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE));
9094 } else if (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3050) {
9095 AscSetExtraControl(iop_base,
9096 (SEC_ACTIVE_NEGATE |
9097 SEC_ENABLE_FILTER));
9100 if (asc_dvc->bus_type == ASC_IS_PCI) {
9101 AscSetExtraControl(iop_base,
9102 (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE));
9105 asc_dvc->cfg->isa_dma_speed = ASC_DEF_ISA_DMA_SPEED;
9107 if ((asc_dvc->bus_type & ASC_IS_ISA) != 0) {
9108 if (chip_version >= ASC_CHIP_MIN_VER_ISA_PNP) {
9109 AscSetChipIFC(iop_base, IFC_INIT_DEFAULT);
9110 asc_dvc->bus_type = ASC_IS_ISAPNP;
9112 asc_dvc->cfg->isa_dma_channel =
9113 (uchar)AscGetIsaDmaChannel(iop_base);
9115 #endif /* CONFIG_ISA */
9116 for (i = 0; i <= ASC_MAX_TID; i++) {
9117 asc_dvc->cur_dvc_qng[i] = 0;
9118 asc_dvc->max_dvc_qng[i] = ASC_MAX_SCSI1_QNG;
9119 asc_dvc->scsiq_busy_head[i] = (ASC_SCSI_Q *)0L;
9120 asc_dvc->scsiq_busy_tail[i] = (ASC_SCSI_Q *)0L;
9121 asc_dvc->cfg->max_tag_qng[i] = ASC_MAX_INRAM_TAG_QNG;
9126 static int AscWriteEEPCmdReg(PortAddr iop_base, uchar cmd_reg)
9130 for (retry = 0; retry < ASC_EEP_MAX_RETRY; retry++) {
9131 unsigned char read_back;
9132 AscSetChipEEPCmd(iop_base, cmd_reg);
9134 read_back = AscGetChipEEPCmd(iop_base);
9135 if (read_back == cmd_reg)
9141 static void AscWaitEEPRead(void)
9146 static ushort AscReadEEPWord(PortAddr iop_base, uchar addr)
9151 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_DISABLE);
9153 cmd_reg = addr | ASC_EEP_CMD_READ;
9154 AscWriteEEPCmdReg(iop_base, cmd_reg);
9156 read_wval = AscGetChipEEPData(iop_base);
9161 static ushort AscGetEEPConfig(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf,
9169 int uchar_end_in_config = ASC_EEP_MAX_DVC_ADDR - 2;
9172 wbuf = (ushort *)cfg_buf;
9174 /* Read two config words; Byte-swapping done by AscReadEEPWord(). */
9175 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
9176 *wbuf = AscReadEEPWord(iop_base, (uchar)s_addr);
9179 if (bus_type & ASC_IS_VL) {
9180 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
9181 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
9183 cfg_beg = ASC_EEP_DVC_CFG_BEG;
9184 cfg_end = ASC_EEP_MAX_DVC_ADDR;
9186 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
9187 wval = AscReadEEPWord(iop_base, (uchar)s_addr);
9188 if (s_addr <= uchar_end_in_config) {
9190 * Swap all char fields - must unswap bytes already swapped
9191 * by AscReadEEPWord().
9193 *wbuf = le16_to_cpu(wval);
9195 /* Don't swap word field at the end - cntl field. */
9198 sum += wval; /* Checksum treats all EEPROM data as words. */
9201 * Read the checksum word which will be compared against 'sum'
9202 * by the caller. Word field already swapped.
9204 *wbuf = AscReadEEPWord(iop_base, (uchar)s_addr);
9208 static int AscTestExternalLram(ASC_DVC_VAR *asc_dvc)
9215 iop_base = asc_dvc->iop_base;
9217 q_addr = ASC_QNO_TO_QADDR(241);
9218 saved_word = AscReadLramWord(iop_base, q_addr);
9219 AscSetChipLramAddr(iop_base, q_addr);
9220 AscSetChipLramData(iop_base, 0x55AA);
9222 AscSetChipLramAddr(iop_base, q_addr);
9223 if (AscGetChipLramData(iop_base) == 0x55AA) {
9225 AscWriteLramWord(iop_base, q_addr, saved_word);
9230 static void AscWaitEEPWrite(void)
9235 static int AscWriteEEPDataReg(PortAddr iop_base, ushort data_reg)
9242 AscSetChipEEPData(iop_base, data_reg);
9244 read_back = AscGetChipEEPData(iop_base);
9245 if (read_back == data_reg) {
9248 if (retry++ > ASC_EEP_MAX_RETRY) {
9254 static ushort AscWriteEEPWord(PortAddr iop_base, uchar addr, ushort word_val)
9258 read_wval = AscReadEEPWord(iop_base, addr);
9259 if (read_wval != word_val) {
9260 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_ABLE);
9262 AscWriteEEPDataReg(iop_base, word_val);
9264 AscWriteEEPCmdReg(iop_base,
9265 (uchar)((uchar)ASC_EEP_CMD_WRITE | addr));
9267 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_DISABLE);
9269 return (AscReadEEPWord(iop_base, addr));
9274 static int AscSetEEPConfigOnce(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf,
9284 int uchar_end_in_config = ASC_EEP_MAX_DVC_ADDR - 2;
9286 wbuf = (ushort *)cfg_buf;
9289 /* Write two config words; AscWriteEEPWord() will swap bytes. */
9290 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
9292 if (*wbuf != AscWriteEEPWord(iop_base, (uchar)s_addr, *wbuf)) {
9296 if (bus_type & ASC_IS_VL) {
9297 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
9298 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
9300 cfg_beg = ASC_EEP_DVC_CFG_BEG;
9301 cfg_end = ASC_EEP_MAX_DVC_ADDR;
9303 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
9304 if (s_addr <= uchar_end_in_config) {
9306 * This is a char field. Swap char fields before they are
9307 * swapped again by AscWriteEEPWord().
9309 word = cpu_to_le16(*wbuf);
9311 AscWriteEEPWord(iop_base, (uchar)s_addr, word)) {
9315 /* Don't swap word field at the end - cntl field. */
9317 AscWriteEEPWord(iop_base, (uchar)s_addr, *wbuf)) {
9321 sum += *wbuf; /* Checksum calculated from word values. */
9323 /* Write checksum word. It will be swapped by AscWriteEEPWord(). */
9325 if (sum != AscWriteEEPWord(iop_base, (uchar)s_addr, sum)) {
9329 /* Read EEPROM back again. */
9330 wbuf = (ushort *)cfg_buf;
9332 * Read two config words; Byte-swapping done by AscReadEEPWord().
9334 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
9335 if (*wbuf != AscReadEEPWord(iop_base, (uchar)s_addr)) {
9339 if (bus_type & ASC_IS_VL) {
9340 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
9341 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
9343 cfg_beg = ASC_EEP_DVC_CFG_BEG;
9344 cfg_end = ASC_EEP_MAX_DVC_ADDR;
9346 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
9347 if (s_addr <= uchar_end_in_config) {
9349 * Swap all char fields. Must unswap bytes already swapped
9350 * by AscReadEEPWord().
9353 le16_to_cpu(AscReadEEPWord
9354 (iop_base, (uchar)s_addr));
9356 /* Don't swap word field at the end - cntl field. */
9357 word = AscReadEEPWord(iop_base, (uchar)s_addr);
9359 if (*wbuf != word) {
9363 /* Read checksum; Byte swapping not needed. */
9364 if (AscReadEEPWord(iop_base, (uchar)s_addr) != sum) {
9370 static int AscSetEEPConfig(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf,
9378 if ((n_error = AscSetEEPConfigOnce(iop_base, cfg_buf,
9382 if (++retry > ASC_EEP_MAX_RETRY) {
9389 static ushort AscInitFromEEP(ASC_DVC_VAR *asc_dvc)
9391 ASCEEP_CONFIG eep_config_buf;
9392 ASCEEP_CONFIG *eep_config;
9396 ushort cfg_msw, cfg_lsw;
9400 iop_base = asc_dvc->iop_base;
9402 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0x00FE);
9403 AscStopQueueExe(iop_base);
9404 if ((AscStopChip(iop_base) == FALSE) ||
9405 (AscGetChipScsiCtrl(iop_base) != 0)) {
9406 asc_dvc->init_state |= ASC_INIT_RESET_SCSI_DONE;
9407 AscResetChipAndScsiBus(asc_dvc);
9408 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
9410 if (!AscIsChipHalted(iop_base)) {
9411 asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP;
9414 AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR);
9415 if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) {
9416 asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR;
9419 eep_config = (ASCEEP_CONFIG *)&eep_config_buf;
9420 cfg_msw = AscGetChipCfgMsw(iop_base);
9421 cfg_lsw = AscGetChipCfgLsw(iop_base);
9422 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) {
9423 cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
9424 warn_code |= ASC_WARN_CFG_MSW_RECOVER;
9425 AscSetChipCfgMsw(iop_base, cfg_msw);
9427 chksum = AscGetEEPConfig(iop_base, eep_config, asc_dvc->bus_type);
9428 ASC_DBG(1, "chksum 0x%x\n", chksum);
9432 if (AscGetChipStatus(iop_base) & CSW_AUTO_CONFIG) {
9433 warn_code |= ASC_WARN_AUTO_CONFIG;
9434 if (asc_dvc->cfg->chip_version == 3) {
9435 if (eep_config->cfg_lsw != cfg_lsw) {
9436 warn_code |= ASC_WARN_EEPROM_RECOVER;
9437 eep_config->cfg_lsw =
9438 AscGetChipCfgLsw(iop_base);
9440 if (eep_config->cfg_msw != cfg_msw) {
9441 warn_code |= ASC_WARN_EEPROM_RECOVER;
9442 eep_config->cfg_msw =
9443 AscGetChipCfgMsw(iop_base);
9447 eep_config->cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
9448 eep_config->cfg_lsw |= ASC_CFG0_HOST_INT_ON;
9449 ASC_DBG(1, "eep_config->chksum 0x%x\n", eep_config->chksum);
9450 if (chksum != eep_config->chksum) {
9451 if (AscGetChipVersion(iop_base, asc_dvc->bus_type) ==
9452 ASC_CHIP_VER_PCI_ULTRA_3050) {
9453 ASC_DBG(1, "chksum error ignored; EEPROM-less board\n");
9454 eep_config->init_sdtr = 0xFF;
9455 eep_config->disc_enable = 0xFF;
9456 eep_config->start_motor = 0xFF;
9457 eep_config->use_cmd_qng = 0;
9458 eep_config->max_total_qng = 0xF0;
9459 eep_config->max_tag_qng = 0x20;
9460 eep_config->cntl = 0xBFFF;
9461 ASC_EEP_SET_CHIP_ID(eep_config, 7);
9462 eep_config->no_scam = 0;
9463 eep_config->adapter_info[0] = 0;
9464 eep_config->adapter_info[1] = 0;
9465 eep_config->adapter_info[2] = 0;
9466 eep_config->adapter_info[3] = 0;
9467 eep_config->adapter_info[4] = 0;
9468 /* Indicate EEPROM-less board. */
9469 eep_config->adapter_info[5] = 0xBB;
9472 ("AscInitFromEEP: EEPROM checksum error; Will try to re-write EEPROM.\n");
9474 warn_code |= ASC_WARN_EEPROM_CHKSUM;
9477 asc_dvc->cfg->sdtr_enable = eep_config->init_sdtr;
9478 asc_dvc->cfg->disc_enable = eep_config->disc_enable;
9479 asc_dvc->cfg->cmd_qng_enabled = eep_config->use_cmd_qng;
9480 asc_dvc->cfg->isa_dma_speed = ASC_EEP_GET_DMA_SPD(eep_config);
9481 asc_dvc->start_motor = eep_config->start_motor;
9482 asc_dvc->dvc_cntl = eep_config->cntl;
9483 asc_dvc->no_scam = eep_config->no_scam;
9484 asc_dvc->cfg->adapter_info[0] = eep_config->adapter_info[0];
9485 asc_dvc->cfg->adapter_info[1] = eep_config->adapter_info[1];
9486 asc_dvc->cfg->adapter_info[2] = eep_config->adapter_info[2];
9487 asc_dvc->cfg->adapter_info[3] = eep_config->adapter_info[3];
9488 asc_dvc->cfg->adapter_info[4] = eep_config->adapter_info[4];
9489 asc_dvc->cfg->adapter_info[5] = eep_config->adapter_info[5];
9490 if (!AscTestExternalLram(asc_dvc)) {
9491 if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) ==
9492 ASC_IS_PCI_ULTRA)) {
9493 eep_config->max_total_qng =
9494 ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG;
9495 eep_config->max_tag_qng =
9496 ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG;
9498 eep_config->cfg_msw |= 0x0800;
9500 AscSetChipCfgMsw(iop_base, cfg_msw);
9501 eep_config->max_total_qng = ASC_MAX_PCI_INRAM_TOTAL_QNG;
9502 eep_config->max_tag_qng = ASC_MAX_INRAM_TAG_QNG;
9506 if (eep_config->max_total_qng < ASC_MIN_TOTAL_QNG) {
9507 eep_config->max_total_qng = ASC_MIN_TOTAL_QNG;
9509 if (eep_config->max_total_qng > ASC_MAX_TOTAL_QNG) {
9510 eep_config->max_total_qng = ASC_MAX_TOTAL_QNG;
9512 if (eep_config->max_tag_qng > eep_config->max_total_qng) {
9513 eep_config->max_tag_qng = eep_config->max_total_qng;
9515 if (eep_config->max_tag_qng < ASC_MIN_TAG_Q_PER_DVC) {
9516 eep_config->max_tag_qng = ASC_MIN_TAG_Q_PER_DVC;
9518 asc_dvc->max_total_qng = eep_config->max_total_qng;
9519 if ((eep_config->use_cmd_qng & eep_config->disc_enable) !=
9520 eep_config->use_cmd_qng) {
9521 eep_config->disc_enable = eep_config->use_cmd_qng;
9522 warn_code |= ASC_WARN_CMD_QNG_CONFLICT;
9524 ASC_EEP_SET_CHIP_ID(eep_config,
9525 ASC_EEP_GET_CHIP_ID(eep_config) & ASC_MAX_TID);
9526 asc_dvc->cfg->chip_scsi_id = ASC_EEP_GET_CHIP_ID(eep_config);
9527 if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) &&
9528 !(asc_dvc->dvc_cntl & ASC_CNTL_SDTR_ENABLE_ULTRA)) {
9529 asc_dvc->min_sdtr_index = ASC_SDTR_ULTRA_PCI_10MB_INDEX;
9532 for (i = 0; i <= ASC_MAX_TID; i++) {
9533 asc_dvc->dos_int13_table[i] = eep_config->dos_int13_table[i];
9534 asc_dvc->cfg->max_tag_qng[i] = eep_config->max_tag_qng;
9535 asc_dvc->cfg->sdtr_period_offset[i] =
9536 (uchar)(ASC_DEF_SDTR_OFFSET |
9537 (asc_dvc->min_sdtr_index << 4));
9539 eep_config->cfg_msw = AscGetChipCfgMsw(iop_base);
9541 if ((i = AscSetEEPConfig(iop_base, eep_config,
9542 asc_dvc->bus_type)) != 0) {
9544 ("AscInitFromEEP: Failed to re-write EEPROM with %d errors.\n",
9548 ("AscInitFromEEP: Successfully re-wrote EEPROM.\n");
9554 static int AscInitGetConfig(struct Scsi_Host *shost)
9556 struct asc_board *board = shost_priv(shost);
9557 ASC_DVC_VAR *asc_dvc = &board->dvc_var.asc_dvc_var;
9558 unsigned short warn_code = 0;
9560 asc_dvc->init_state = ASC_INIT_STATE_BEG_GET_CFG;
9561 if (asc_dvc->err_code != 0)
9562 return asc_dvc->err_code;
9564 if (AscFindSignature(asc_dvc->iop_base)) {
9565 warn_code |= AscInitAscDvcVar(asc_dvc);
9566 warn_code |= AscInitFromEEP(asc_dvc);
9567 asc_dvc->init_state |= ASC_INIT_STATE_END_GET_CFG;
9568 if (asc_dvc->scsi_reset_wait > ASC_MAX_SCSI_RESET_WAIT)
9569 asc_dvc->scsi_reset_wait = ASC_MAX_SCSI_RESET_WAIT;
9571 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
9574 switch (warn_code) {
9575 case 0: /* No error */
9577 case ASC_WARN_IO_PORT_ROTATE:
9578 shost_printk(KERN_WARNING, shost, "I/O port address "
9581 case ASC_WARN_AUTO_CONFIG:
9582 shost_printk(KERN_WARNING, shost, "I/O port increment switch "
9585 case ASC_WARN_EEPROM_CHKSUM:
9586 shost_printk(KERN_WARNING, shost, "EEPROM checksum error\n");
9588 case ASC_WARN_IRQ_MODIFIED:
9589 shost_printk(KERN_WARNING, shost, "IRQ modified\n");
9591 case ASC_WARN_CMD_QNG_CONFLICT:
9592 shost_printk(KERN_WARNING, shost, "tag queuing enabled w/o "
9596 shost_printk(KERN_WARNING, shost, "unknown warning: 0x%x\n",
9601 if (asc_dvc->err_code != 0)
9602 shost_printk(KERN_ERR, shost, "error 0x%x at init_state "
9603 "0x%x\n", asc_dvc->err_code, asc_dvc->init_state);
9605 return asc_dvc->err_code;
9608 static int AscInitSetConfig(struct pci_dev *pdev, struct Scsi_Host *shost)
9610 struct asc_board *board = shost_priv(shost);
9611 ASC_DVC_VAR *asc_dvc = &board->dvc_var.asc_dvc_var;
9612 PortAddr iop_base = asc_dvc->iop_base;
9613 unsigned short cfg_msw;
9614 unsigned short warn_code = 0;
9616 asc_dvc->init_state |= ASC_INIT_STATE_BEG_SET_CFG;
9617 if (asc_dvc->err_code != 0)
9618 return asc_dvc->err_code;
9619 if (!AscFindSignature(asc_dvc->iop_base)) {
9620 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
9621 return asc_dvc->err_code;
9624 cfg_msw = AscGetChipCfgMsw(iop_base);
9625 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) {
9626 cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
9627 warn_code |= ASC_WARN_CFG_MSW_RECOVER;
9628 AscSetChipCfgMsw(iop_base, cfg_msw);
9630 if ((asc_dvc->cfg->cmd_qng_enabled & asc_dvc->cfg->disc_enable) !=
9631 asc_dvc->cfg->cmd_qng_enabled) {
9632 asc_dvc->cfg->disc_enable = asc_dvc->cfg->cmd_qng_enabled;
9633 warn_code |= ASC_WARN_CMD_QNG_CONFLICT;
9635 if (AscGetChipStatus(iop_base) & CSW_AUTO_CONFIG) {
9636 warn_code |= ASC_WARN_AUTO_CONFIG;
9639 if (asc_dvc->bus_type & ASC_IS_PCI) {
9641 AscSetChipCfgMsw(iop_base, cfg_msw);
9642 if ((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) {
9644 if ((pdev->device == PCI_DEVICE_ID_ASP_1200A) ||
9645 (pdev->device == PCI_DEVICE_ID_ASP_ABP940)) {
9646 asc_dvc->bug_fix_cntl |= ASC_BUG_FIX_IF_NOT_DWB;
9647 asc_dvc->bug_fix_cntl |=
9648 ASC_BUG_FIX_ASYN_USE_SYN;
9652 #endif /* CONFIG_PCI */
9653 if (asc_dvc->bus_type == ASC_IS_ISAPNP) {
9654 if (AscGetChipVersion(iop_base, asc_dvc->bus_type)
9655 == ASC_CHIP_VER_ASYN_BUG) {
9656 asc_dvc->bug_fix_cntl |= ASC_BUG_FIX_ASYN_USE_SYN;
9659 if (AscSetChipScsiID(iop_base, asc_dvc->cfg->chip_scsi_id) !=
9660 asc_dvc->cfg->chip_scsi_id) {
9661 asc_dvc->err_code |= ASC_IERR_SET_SCSI_ID;
9664 if (asc_dvc->bus_type & ASC_IS_ISA) {
9665 AscSetIsaDmaChannel(iop_base, asc_dvc->cfg->isa_dma_channel);
9666 AscSetIsaDmaSpeed(iop_base, asc_dvc->cfg->isa_dma_speed);
9668 #endif /* CONFIG_ISA */
9670 asc_dvc->init_state |= ASC_INIT_STATE_END_SET_CFG;
9672 switch (warn_code) {
9673 case 0: /* No error. */
9675 case ASC_WARN_IO_PORT_ROTATE:
9676 shost_printk(KERN_WARNING, shost, "I/O port address "
9679 case ASC_WARN_AUTO_CONFIG:
9680 shost_printk(KERN_WARNING, shost, "I/O port increment switch "
9683 case ASC_WARN_EEPROM_CHKSUM:
9684 shost_printk(KERN_WARNING, shost, "EEPROM checksum error\n");
9686 case ASC_WARN_IRQ_MODIFIED:
9687 shost_printk(KERN_WARNING, shost, "IRQ modified\n");
9689 case ASC_WARN_CMD_QNG_CONFLICT:
9690 shost_printk(KERN_WARNING, shost, "tag queuing w/o "
9694 shost_printk(KERN_WARNING, shost, "unknown warning: 0x%x\n",
9699 if (asc_dvc->err_code != 0)
9700 shost_printk(KERN_ERR, shost, "error 0x%x at init_state "
9701 "0x%x\n", asc_dvc->err_code, asc_dvc->init_state);
9703 return asc_dvc->err_code;
9707 * EEPROM Configuration.
9709 * All drivers should use this structure to set the default EEPROM
9710 * configuration. The BIOS now uses this structure when it is built.
9711 * Additional structure information can be found in a_condor.h where
9712 * the structure is defined.
9714 * The *_Field_IsChar structs are needed to correct for endianness.
9715 * These values are read from the board 16 bits at a time directly
9716 * into the structs. Because some fields are char, the values will be
9717 * in the wrong order. The *_Field_IsChar tells when to flip the
9718 * bytes. Data read and written to PCI memory is automatically swapped
9719 * on big-endian platforms so char fields read as words are actually being
9720 * unswapped on big-endian platforms.
9722 static ADVEEP_3550_CONFIG Default_3550_EEPROM_Config = {
9723 ADV_EEPROM_BIOS_ENABLE, /* cfg_lsw */
9724 0x0000, /* cfg_msw */
9725 0xFFFF, /* disc_enable */
9726 0xFFFF, /* wdtr_able */
9727 0xFFFF, /* sdtr_able */
9728 0xFFFF, /* start_motor */
9729 0xFFFF, /* tagqng_able */
9730 0xFFFF, /* bios_scan */
9731 0, /* scam_tolerant */
9732 7, /* adapter_scsi_id */
9733 0, /* bios_boot_delay */
9734 3, /* scsi_reset_delay */
9735 0, /* bios_id_lun */
9736 0, /* termination */
9738 0xFFE7, /* bios_ctrl */
9739 0xFFFF, /* ultra_able */
9741 ASC_DEF_MAX_HOST_QNG, /* max_host_qng */
9742 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
9745 0, /* serial_number_word1 */
9746 0, /* serial_number_word2 */
9747 0, /* serial_number_word3 */
9749 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
9750 , /* oem_name[16] */
9751 0, /* dvc_err_code */
9752 0, /* adv_err_code */
9753 0, /* adv_err_addr */
9754 0, /* saved_dvc_err_code */
9755 0, /* saved_adv_err_code */
9756 0, /* saved_adv_err_addr */
9760 static ADVEEP_3550_CONFIG ADVEEP_3550_Config_Field_IsChar = {
9763 0, /* -disc_enable */
9766 0, /* start_motor */
9767 0, /* tagqng_able */
9769 0, /* scam_tolerant */
9770 1, /* adapter_scsi_id */
9771 1, /* bios_boot_delay */
9772 1, /* scsi_reset_delay */
9773 1, /* bios_id_lun */
9774 1, /* termination */
9779 1, /* max_host_qng */
9780 1, /* max_dvc_qng */
9783 0, /* serial_number_word1 */
9784 0, /* serial_number_word2 */
9785 0, /* serial_number_word3 */
9787 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
9788 , /* oem_name[16] */
9789 0, /* dvc_err_code */
9790 0, /* adv_err_code */
9791 0, /* adv_err_addr */
9792 0, /* saved_dvc_err_code */
9793 0, /* saved_adv_err_code */
9794 0, /* saved_adv_err_addr */
9798 static ADVEEP_38C0800_CONFIG Default_38C0800_EEPROM_Config = {
9799 ADV_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
9800 0x0000, /* 01 cfg_msw */
9801 0xFFFF, /* 02 disc_enable */
9802 0xFFFF, /* 03 wdtr_able */
9803 0x4444, /* 04 sdtr_speed1 */
9804 0xFFFF, /* 05 start_motor */
9805 0xFFFF, /* 06 tagqng_able */
9806 0xFFFF, /* 07 bios_scan */
9807 0, /* 08 scam_tolerant */
9808 7, /* 09 adapter_scsi_id */
9809 0, /* bios_boot_delay */
9810 3, /* 10 scsi_reset_delay */
9811 0, /* bios_id_lun */
9812 0, /* 11 termination_se */
9813 0, /* termination_lvd */
9814 0xFFE7, /* 12 bios_ctrl */
9815 0x4444, /* 13 sdtr_speed2 */
9816 0x4444, /* 14 sdtr_speed3 */
9817 ASC_DEF_MAX_HOST_QNG, /* 15 max_host_qng */
9818 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
9819 0, /* 16 dvc_cntl */
9820 0x4444, /* 17 sdtr_speed4 */
9821 0, /* 18 serial_number_word1 */
9822 0, /* 19 serial_number_word2 */
9823 0, /* 20 serial_number_word3 */
9824 0, /* 21 check_sum */
9825 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
9826 , /* 22-29 oem_name[16] */
9827 0, /* 30 dvc_err_code */
9828 0, /* 31 adv_err_code */
9829 0, /* 32 adv_err_addr */
9830 0, /* 33 saved_dvc_err_code */
9831 0, /* 34 saved_adv_err_code */
9832 0, /* 35 saved_adv_err_addr */
9833 0, /* 36 reserved */
9834 0, /* 37 reserved */
9835 0, /* 38 reserved */
9836 0, /* 39 reserved */
9837 0, /* 40 reserved */
9838 0, /* 41 reserved */
9839 0, /* 42 reserved */
9840 0, /* 43 reserved */
9841 0, /* 44 reserved */
9842 0, /* 45 reserved */
9843 0, /* 46 reserved */
9844 0, /* 47 reserved */
9845 0, /* 48 reserved */
9846 0, /* 49 reserved */
9847 0, /* 50 reserved */
9848 0, /* 51 reserved */
9849 0, /* 52 reserved */
9850 0, /* 53 reserved */
9851 0, /* 54 reserved */
9852 0, /* 55 reserved */
9853 0, /* 56 cisptr_lsw */
9854 0, /* 57 cisprt_msw */
9855 PCI_VENDOR_ID_ASP, /* 58 subsysvid */
9856 PCI_DEVICE_ID_38C0800_REV1, /* 59 subsysid */
9857 0, /* 60 reserved */
9858 0, /* 61 reserved */
9859 0, /* 62 reserved */
9863 static ADVEEP_38C0800_CONFIG ADVEEP_38C0800_Config_Field_IsChar = {
9866 0, /* 02 disc_enable */
9867 0, /* 03 wdtr_able */
9868 0, /* 04 sdtr_speed1 */
9869 0, /* 05 start_motor */
9870 0, /* 06 tagqng_able */
9871 0, /* 07 bios_scan */
9872 0, /* 08 scam_tolerant */
9873 1, /* 09 adapter_scsi_id */
9874 1, /* bios_boot_delay */
9875 1, /* 10 scsi_reset_delay */
9876 1, /* bios_id_lun */
9877 1, /* 11 termination_se */
9878 1, /* termination_lvd */
9879 0, /* 12 bios_ctrl */
9880 0, /* 13 sdtr_speed2 */
9881 0, /* 14 sdtr_speed3 */
9882 1, /* 15 max_host_qng */
9883 1, /* max_dvc_qng */
9884 0, /* 16 dvc_cntl */
9885 0, /* 17 sdtr_speed4 */
9886 0, /* 18 serial_number_word1 */
9887 0, /* 19 serial_number_word2 */
9888 0, /* 20 serial_number_word3 */
9889 0, /* 21 check_sum */
9890 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
9891 , /* 22-29 oem_name[16] */
9892 0, /* 30 dvc_err_code */
9893 0, /* 31 adv_err_code */
9894 0, /* 32 adv_err_addr */
9895 0, /* 33 saved_dvc_err_code */
9896 0, /* 34 saved_adv_err_code */
9897 0, /* 35 saved_adv_err_addr */
9898 0, /* 36 reserved */
9899 0, /* 37 reserved */
9900 0, /* 38 reserved */
9901 0, /* 39 reserved */
9902 0, /* 40 reserved */
9903 0, /* 41 reserved */
9904 0, /* 42 reserved */
9905 0, /* 43 reserved */
9906 0, /* 44 reserved */
9907 0, /* 45 reserved */
9908 0, /* 46 reserved */
9909 0, /* 47 reserved */
9910 0, /* 48 reserved */
9911 0, /* 49 reserved */
9912 0, /* 50 reserved */
9913 0, /* 51 reserved */
9914 0, /* 52 reserved */
9915 0, /* 53 reserved */
9916 0, /* 54 reserved */
9917 0, /* 55 reserved */
9918 0, /* 56 cisptr_lsw */
9919 0, /* 57 cisprt_msw */
9920 0, /* 58 subsysvid */
9921 0, /* 59 subsysid */
9922 0, /* 60 reserved */
9923 0, /* 61 reserved */
9924 0, /* 62 reserved */
9928 static ADVEEP_38C1600_CONFIG Default_38C1600_EEPROM_Config = {
9929 ADV_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
9930 0x0000, /* 01 cfg_msw */
9931 0xFFFF, /* 02 disc_enable */
9932 0xFFFF, /* 03 wdtr_able */
9933 0x5555, /* 04 sdtr_speed1 */
9934 0xFFFF, /* 05 start_motor */
9935 0xFFFF, /* 06 tagqng_able */
9936 0xFFFF, /* 07 bios_scan */
9937 0, /* 08 scam_tolerant */
9938 7, /* 09 adapter_scsi_id */
9939 0, /* bios_boot_delay */
9940 3, /* 10 scsi_reset_delay */
9941 0, /* bios_id_lun */
9942 0, /* 11 termination_se */
9943 0, /* termination_lvd */
9944 0xFFE7, /* 12 bios_ctrl */
9945 0x5555, /* 13 sdtr_speed2 */
9946 0x5555, /* 14 sdtr_speed3 */
9947 ASC_DEF_MAX_HOST_QNG, /* 15 max_host_qng */
9948 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
9949 0, /* 16 dvc_cntl */
9950 0x5555, /* 17 sdtr_speed4 */
9951 0, /* 18 serial_number_word1 */
9952 0, /* 19 serial_number_word2 */
9953 0, /* 20 serial_number_word3 */
9954 0, /* 21 check_sum */
9955 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
9956 , /* 22-29 oem_name[16] */
9957 0, /* 30 dvc_err_code */
9958 0, /* 31 adv_err_code */
9959 0, /* 32 adv_err_addr */
9960 0, /* 33 saved_dvc_err_code */
9961 0, /* 34 saved_adv_err_code */
9962 0, /* 35 saved_adv_err_addr */
9963 0, /* 36 reserved */
9964 0, /* 37 reserved */
9965 0, /* 38 reserved */
9966 0, /* 39 reserved */
9967 0, /* 40 reserved */
9968 0, /* 41 reserved */
9969 0, /* 42 reserved */
9970 0, /* 43 reserved */
9971 0, /* 44 reserved */
9972 0, /* 45 reserved */
9973 0, /* 46 reserved */
9974 0, /* 47 reserved */
9975 0, /* 48 reserved */
9976 0, /* 49 reserved */
9977 0, /* 50 reserved */
9978 0, /* 51 reserved */
9979 0, /* 52 reserved */
9980 0, /* 53 reserved */
9981 0, /* 54 reserved */
9982 0, /* 55 reserved */
9983 0, /* 56 cisptr_lsw */
9984 0, /* 57 cisprt_msw */
9985 PCI_VENDOR_ID_ASP, /* 58 subsysvid */
9986 PCI_DEVICE_ID_38C1600_REV1, /* 59 subsysid */
9987 0, /* 60 reserved */
9988 0, /* 61 reserved */
9989 0, /* 62 reserved */
9993 static ADVEEP_38C1600_CONFIG ADVEEP_38C1600_Config_Field_IsChar = {
9996 0, /* 02 disc_enable */
9997 0, /* 03 wdtr_able */
9998 0, /* 04 sdtr_speed1 */
9999 0, /* 05 start_motor */
10000 0, /* 06 tagqng_able */
10001 0, /* 07 bios_scan */
10002 0, /* 08 scam_tolerant */
10003 1, /* 09 adapter_scsi_id */
10004 1, /* bios_boot_delay */
10005 1, /* 10 scsi_reset_delay */
10006 1, /* bios_id_lun */
10007 1, /* 11 termination_se */
10008 1, /* termination_lvd */
10009 0, /* 12 bios_ctrl */
10010 0, /* 13 sdtr_speed2 */
10011 0, /* 14 sdtr_speed3 */
10012 1, /* 15 max_host_qng */
10013 1, /* max_dvc_qng */
10014 0, /* 16 dvc_cntl */
10015 0, /* 17 sdtr_speed4 */
10016 0, /* 18 serial_number_word1 */
10017 0, /* 19 serial_number_word2 */
10018 0, /* 20 serial_number_word3 */
10019 0, /* 21 check_sum */
10020 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
10021 , /* 22-29 oem_name[16] */
10022 0, /* 30 dvc_err_code */
10023 0, /* 31 adv_err_code */
10024 0, /* 32 adv_err_addr */
10025 0, /* 33 saved_dvc_err_code */
10026 0, /* 34 saved_adv_err_code */
10027 0, /* 35 saved_adv_err_addr */
10028 0, /* 36 reserved */
10029 0, /* 37 reserved */
10030 0, /* 38 reserved */
10031 0, /* 39 reserved */
10032 0, /* 40 reserved */
10033 0, /* 41 reserved */
10034 0, /* 42 reserved */
10035 0, /* 43 reserved */
10036 0, /* 44 reserved */
10037 0, /* 45 reserved */
10038 0, /* 46 reserved */
10039 0, /* 47 reserved */
10040 0, /* 48 reserved */
10041 0, /* 49 reserved */
10042 0, /* 50 reserved */
10043 0, /* 51 reserved */
10044 0, /* 52 reserved */
10045 0, /* 53 reserved */
10046 0, /* 54 reserved */
10047 0, /* 55 reserved */
10048 0, /* 56 cisptr_lsw */
10049 0, /* 57 cisprt_msw */
10050 0, /* 58 subsysvid */
10051 0, /* 59 subsysid */
10052 0, /* 60 reserved */
10053 0, /* 61 reserved */
10054 0, /* 62 reserved */
10055 0 /* 63 reserved */
10060 * Wait for EEPROM command to complete
10062 static void AdvWaitEEPCmd(AdvPortAddr iop_base)
10066 for (eep_delay_ms = 0; eep_delay_ms < ADV_EEP_DELAY_MS; eep_delay_ms++) {
10067 if (AdvReadWordRegister(iop_base, IOPW_EE_CMD) &
10068 ASC_EEP_CMD_DONE) {
10073 if ((AdvReadWordRegister(iop_base, IOPW_EE_CMD) & ASC_EEP_CMD_DONE) ==
10079 * Read the EEPROM from specified location
10081 static ushort AdvReadEEPWord(AdvPortAddr iop_base, int eep_word_addr)
10083 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10084 ASC_EEP_CMD_READ | eep_word_addr);
10085 AdvWaitEEPCmd(iop_base);
10086 return AdvReadWordRegister(iop_base, IOPW_EE_DATA);
10090 * Write the EEPROM from 'cfg_buf'.
10092 static void AdvSet3550EEPConfig(AdvPortAddr iop_base,
10093 ADVEEP_3550_CONFIG *cfg_buf)
10096 ushort addr, chksum;
10097 ushort *charfields;
10099 wbuf = (ushort *)cfg_buf;
10100 charfields = (ushort *)&ADVEEP_3550_Config_Field_IsChar;
10103 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
10104 AdvWaitEEPCmd(iop_base);
10107 * Write EEPROM from word 0 to word 20.
10109 for (addr = ADV_EEP_DVC_CFG_BEGIN;
10110 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
10113 if (*charfields++) {
10114 word = cpu_to_le16(*wbuf);
10118 chksum += *wbuf; /* Checksum is calculated from word values. */
10119 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
10120 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10121 ASC_EEP_CMD_WRITE | addr);
10122 AdvWaitEEPCmd(iop_base);
10123 mdelay(ADV_EEP_DELAY_MS);
10127 * Write EEPROM checksum at word 21.
10129 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
10130 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
10131 AdvWaitEEPCmd(iop_base);
10136 * Write EEPROM OEM name at words 22 to 29.
10138 for (addr = ADV_EEP_DVC_CTL_BEGIN;
10139 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
10142 if (*charfields++) {
10143 word = cpu_to_le16(*wbuf);
10147 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
10148 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10149 ASC_EEP_CMD_WRITE | addr);
10150 AdvWaitEEPCmd(iop_base);
10152 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
10153 AdvWaitEEPCmd(iop_base);
10157 * Write the EEPROM from 'cfg_buf'.
10159 static void AdvSet38C0800EEPConfig(AdvPortAddr iop_base,
10160 ADVEEP_38C0800_CONFIG *cfg_buf)
10163 ushort *charfields;
10164 ushort addr, chksum;
10166 wbuf = (ushort *)cfg_buf;
10167 charfields = (ushort *)&ADVEEP_38C0800_Config_Field_IsChar;
10170 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
10171 AdvWaitEEPCmd(iop_base);
10174 * Write EEPROM from word 0 to word 20.
10176 for (addr = ADV_EEP_DVC_CFG_BEGIN;
10177 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
10180 if (*charfields++) {
10181 word = cpu_to_le16(*wbuf);
10185 chksum += *wbuf; /* Checksum is calculated from word values. */
10186 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
10187 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10188 ASC_EEP_CMD_WRITE | addr);
10189 AdvWaitEEPCmd(iop_base);
10190 mdelay(ADV_EEP_DELAY_MS);
10194 * Write EEPROM checksum at word 21.
10196 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
10197 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
10198 AdvWaitEEPCmd(iop_base);
10203 * Write EEPROM OEM name at words 22 to 29.
10205 for (addr = ADV_EEP_DVC_CTL_BEGIN;
10206 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
10209 if (*charfields++) {
10210 word = cpu_to_le16(*wbuf);
10214 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
10215 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10216 ASC_EEP_CMD_WRITE | addr);
10217 AdvWaitEEPCmd(iop_base);
10219 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
10220 AdvWaitEEPCmd(iop_base);
10224 * Write the EEPROM from 'cfg_buf'.
10226 static void AdvSet38C1600EEPConfig(AdvPortAddr iop_base,
10227 ADVEEP_38C1600_CONFIG *cfg_buf)
10230 ushort *charfields;
10231 ushort addr, chksum;
10233 wbuf = (ushort *)cfg_buf;
10234 charfields = (ushort *)&ADVEEP_38C1600_Config_Field_IsChar;
10237 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
10238 AdvWaitEEPCmd(iop_base);
10241 * Write EEPROM from word 0 to word 20.
10243 for (addr = ADV_EEP_DVC_CFG_BEGIN;
10244 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
10247 if (*charfields++) {
10248 word = cpu_to_le16(*wbuf);
10252 chksum += *wbuf; /* Checksum is calculated from word values. */
10253 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
10254 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10255 ASC_EEP_CMD_WRITE | addr);
10256 AdvWaitEEPCmd(iop_base);
10257 mdelay(ADV_EEP_DELAY_MS);
10261 * Write EEPROM checksum at word 21.
10263 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
10264 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
10265 AdvWaitEEPCmd(iop_base);
10270 * Write EEPROM OEM name at words 22 to 29.
10272 for (addr = ADV_EEP_DVC_CTL_BEGIN;
10273 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
10276 if (*charfields++) {
10277 word = cpu_to_le16(*wbuf);
10281 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
10282 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10283 ASC_EEP_CMD_WRITE | addr);
10284 AdvWaitEEPCmd(iop_base);
10286 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
10287 AdvWaitEEPCmd(iop_base);
10291 * Read EEPROM configuration into the specified buffer.
10293 * Return a checksum based on the EEPROM configuration read.
10295 static ushort AdvGet3550EEPConfig(AdvPortAddr iop_base,
10296 ADVEEP_3550_CONFIG *cfg_buf)
10298 ushort wval, chksum;
10301 ushort *charfields;
10303 charfields = (ushort *)&ADVEEP_3550_Config_Field_IsChar;
10304 wbuf = (ushort *)cfg_buf;
10307 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
10308 eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
10309 wval = AdvReadEEPWord(iop_base, eep_addr);
10310 chksum += wval; /* Checksum is calculated from word values. */
10311 if (*charfields++) {
10312 *wbuf = le16_to_cpu(wval);
10317 /* Read checksum word. */
10318 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
10322 /* Read rest of EEPROM not covered by the checksum. */
10323 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
10324 eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
10325 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
10326 if (*charfields++) {
10327 *wbuf = le16_to_cpu(*wbuf);
10334 * Read EEPROM configuration into the specified buffer.
10336 * Return a checksum based on the EEPROM configuration read.
10338 static ushort AdvGet38C0800EEPConfig(AdvPortAddr iop_base,
10339 ADVEEP_38C0800_CONFIG *cfg_buf)
10341 ushort wval, chksum;
10344 ushort *charfields;
10346 charfields = (ushort *)&ADVEEP_38C0800_Config_Field_IsChar;
10347 wbuf = (ushort *)cfg_buf;
10350 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
10351 eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
10352 wval = AdvReadEEPWord(iop_base, eep_addr);
10353 chksum += wval; /* Checksum is calculated from word values. */
10354 if (*charfields++) {
10355 *wbuf = le16_to_cpu(wval);
10360 /* Read checksum word. */
10361 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
10365 /* Read rest of EEPROM not covered by the checksum. */
10366 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
10367 eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
10368 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
10369 if (*charfields++) {
10370 *wbuf = le16_to_cpu(*wbuf);
10377 * Read EEPROM configuration into the specified buffer.
10379 * Return a checksum based on the EEPROM configuration read.
10381 static ushort AdvGet38C1600EEPConfig(AdvPortAddr iop_base,
10382 ADVEEP_38C1600_CONFIG *cfg_buf)
10384 ushort wval, chksum;
10387 ushort *charfields;
10389 charfields = (ushort *)&ADVEEP_38C1600_Config_Field_IsChar;
10390 wbuf = (ushort *)cfg_buf;
10393 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
10394 eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
10395 wval = AdvReadEEPWord(iop_base, eep_addr);
10396 chksum += wval; /* Checksum is calculated from word values. */
10397 if (*charfields++) {
10398 *wbuf = le16_to_cpu(wval);
10403 /* Read checksum word. */
10404 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
10408 /* Read rest of EEPROM not covered by the checksum. */
10409 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
10410 eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
10411 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
10412 if (*charfields++) {
10413 *wbuf = le16_to_cpu(*wbuf);
10420 * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and
10421 * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while
10422 * all of this is done.
10424 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
10426 * For a non-fatal error return a warning code. If there are no warnings
10427 * then 0 is returned.
10429 * Note: Chip is stopped on entry.
10431 static int AdvInitFrom3550EEP(ADV_DVC_VAR *asc_dvc)
10433 AdvPortAddr iop_base;
10435 ADVEEP_3550_CONFIG eep_config;
10437 iop_base = asc_dvc->iop_base;
10442 * Read the board's EEPROM configuration.
10444 * Set default values if a bad checksum is found.
10446 if (AdvGet3550EEPConfig(iop_base, &eep_config) != eep_config.check_sum) {
10447 warn_code |= ASC_WARN_EEPROM_CHKSUM;
10450 * Set EEPROM default values.
10452 memcpy(&eep_config, &Default_3550_EEPROM_Config,
10453 sizeof(ADVEEP_3550_CONFIG));
10456 * Assume the 6 byte board serial number that was read from
10457 * EEPROM is correct even if the EEPROM checksum failed.
10459 eep_config.serial_number_word3 =
10460 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
10462 eep_config.serial_number_word2 =
10463 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
10465 eep_config.serial_number_word1 =
10466 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
10468 AdvSet3550EEPConfig(iop_base, &eep_config);
10471 * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the
10472 * EEPROM configuration that was read.
10474 * This is the mapping of EEPROM fields to Adv Library fields.
10476 asc_dvc->wdtr_able = eep_config.wdtr_able;
10477 asc_dvc->sdtr_able = eep_config.sdtr_able;
10478 asc_dvc->ultra_able = eep_config.ultra_able;
10479 asc_dvc->tagqng_able = eep_config.tagqng_able;
10480 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
10481 asc_dvc->max_host_qng = eep_config.max_host_qng;
10482 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
10483 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ADV_MAX_TID);
10484 asc_dvc->start_motor = eep_config.start_motor;
10485 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
10486 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
10487 asc_dvc->no_scam = eep_config.scam_tolerant;
10488 asc_dvc->cfg->serial1 = eep_config.serial_number_word1;
10489 asc_dvc->cfg->serial2 = eep_config.serial_number_word2;
10490 asc_dvc->cfg->serial3 = eep_config.serial_number_word3;
10493 * Set the host maximum queuing (max. 253, min. 16) and the per device
10494 * maximum queuing (max. 63, min. 4).
10496 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
10497 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10498 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
10499 /* If the value is zero, assume it is uninitialized. */
10500 if (eep_config.max_host_qng == 0) {
10501 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10503 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
10507 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
10508 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10509 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
10510 /* If the value is zero, assume it is uninitialized. */
10511 if (eep_config.max_dvc_qng == 0) {
10512 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10514 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
10519 * If 'max_dvc_qng' is greater than 'max_host_qng', then
10520 * set 'max_dvc_qng' to 'max_host_qng'.
10522 if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
10523 eep_config.max_dvc_qng = eep_config.max_host_qng;
10527 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng'
10528 * values based on possibly adjusted EEPROM values.
10530 asc_dvc->max_host_qng = eep_config.max_host_qng;
10531 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
10534 * If the EEPROM 'termination' field is set to automatic (0), then set
10535 * the ADV_DVC_CFG 'termination' field to automatic also.
10537 * If the termination is specified with a non-zero 'termination'
10538 * value check that a legal value is set and set the ADV_DVC_CFG
10539 * 'termination' field appropriately.
10541 if (eep_config.termination == 0) {
10542 asc_dvc->cfg->termination = 0; /* auto termination */
10544 /* Enable manual control with low off / high off. */
10545 if (eep_config.termination == 1) {
10546 asc_dvc->cfg->termination = TERM_CTL_SEL;
10548 /* Enable manual control with low off / high on. */
10549 } else if (eep_config.termination == 2) {
10550 asc_dvc->cfg->termination = TERM_CTL_SEL | TERM_CTL_H;
10552 /* Enable manual control with low on / high on. */
10553 } else if (eep_config.termination == 3) {
10554 asc_dvc->cfg->termination =
10555 TERM_CTL_SEL | TERM_CTL_H | TERM_CTL_L;
10558 * The EEPROM 'termination' field contains a bad value. Use
10559 * automatic termination instead.
10561 asc_dvc->cfg->termination = 0;
10562 warn_code |= ASC_WARN_EEPROM_TERMINATION;
10570 * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and
10571 * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while
10572 * all of this is done.
10574 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
10576 * For a non-fatal error return a warning code. If there are no warnings
10577 * then 0 is returned.
10579 * Note: Chip is stopped on entry.
10581 static int AdvInitFrom38C0800EEP(ADV_DVC_VAR *asc_dvc)
10583 AdvPortAddr iop_base;
10585 ADVEEP_38C0800_CONFIG eep_config;
10586 uchar tid, termination;
10587 ushort sdtr_speed = 0;
10589 iop_base = asc_dvc->iop_base;
10594 * Read the board's EEPROM configuration.
10596 * Set default values if a bad checksum is found.
10598 if (AdvGet38C0800EEPConfig(iop_base, &eep_config) !=
10599 eep_config.check_sum) {
10600 warn_code |= ASC_WARN_EEPROM_CHKSUM;
10603 * Set EEPROM default values.
10605 memcpy(&eep_config, &Default_38C0800_EEPROM_Config,
10606 sizeof(ADVEEP_38C0800_CONFIG));
10609 * Assume the 6 byte board serial number that was read from
10610 * EEPROM is correct even if the EEPROM checksum failed.
10612 eep_config.serial_number_word3 =
10613 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
10615 eep_config.serial_number_word2 =
10616 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
10618 eep_config.serial_number_word1 =
10619 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
10621 AdvSet38C0800EEPConfig(iop_base, &eep_config);
10624 * Set ADV_DVC_VAR and ADV_DVC_CFG variables from the
10625 * EEPROM configuration that was read.
10627 * This is the mapping of EEPROM fields to Adv Library fields.
10629 asc_dvc->wdtr_able = eep_config.wdtr_able;
10630 asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1;
10631 asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2;
10632 asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3;
10633 asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4;
10634 asc_dvc->tagqng_able = eep_config.tagqng_able;
10635 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
10636 asc_dvc->max_host_qng = eep_config.max_host_qng;
10637 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
10638 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ADV_MAX_TID);
10639 asc_dvc->start_motor = eep_config.start_motor;
10640 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
10641 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
10642 asc_dvc->no_scam = eep_config.scam_tolerant;
10643 asc_dvc->cfg->serial1 = eep_config.serial_number_word1;
10644 asc_dvc->cfg->serial2 = eep_config.serial_number_word2;
10645 asc_dvc->cfg->serial3 = eep_config.serial_number_word3;
10648 * For every Target ID if any of its 'sdtr_speed[1234]' bits
10649 * are set, then set an 'sdtr_able' bit for it.
10651 asc_dvc->sdtr_able = 0;
10652 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
10654 sdtr_speed = asc_dvc->sdtr_speed1;
10655 } else if (tid == 4) {
10656 sdtr_speed = asc_dvc->sdtr_speed2;
10657 } else if (tid == 8) {
10658 sdtr_speed = asc_dvc->sdtr_speed3;
10659 } else if (tid == 12) {
10660 sdtr_speed = asc_dvc->sdtr_speed4;
10662 if (sdtr_speed & ADV_MAX_TID) {
10663 asc_dvc->sdtr_able |= (1 << tid);
10669 * Set the host maximum queuing (max. 253, min. 16) and the per device
10670 * maximum queuing (max. 63, min. 4).
10672 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
10673 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10674 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
10675 /* If the value is zero, assume it is uninitialized. */
10676 if (eep_config.max_host_qng == 0) {
10677 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10679 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
10683 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
10684 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10685 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
10686 /* If the value is zero, assume it is uninitialized. */
10687 if (eep_config.max_dvc_qng == 0) {
10688 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10690 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
10695 * If 'max_dvc_qng' is greater than 'max_host_qng', then
10696 * set 'max_dvc_qng' to 'max_host_qng'.
10698 if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
10699 eep_config.max_dvc_qng = eep_config.max_host_qng;
10703 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng'
10704 * values based on possibly adjusted EEPROM values.
10706 asc_dvc->max_host_qng = eep_config.max_host_qng;
10707 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
10710 * If the EEPROM 'termination' field is set to automatic (0), then set
10711 * the ADV_DVC_CFG 'termination' field to automatic also.
10713 * If the termination is specified with a non-zero 'termination'
10714 * value check that a legal value is set and set the ADV_DVC_CFG
10715 * 'termination' field appropriately.
10717 if (eep_config.termination_se == 0) {
10718 termination = 0; /* auto termination for SE */
10720 /* Enable manual control with low off / high off. */
10721 if (eep_config.termination_se == 1) {
10724 /* Enable manual control with low off / high on. */
10725 } else if (eep_config.termination_se == 2) {
10726 termination = TERM_SE_HI;
10728 /* Enable manual control with low on / high on. */
10729 } else if (eep_config.termination_se == 3) {
10730 termination = TERM_SE;
10733 * The EEPROM 'termination_se' field contains a bad value.
10734 * Use automatic termination instead.
10737 warn_code |= ASC_WARN_EEPROM_TERMINATION;
10741 if (eep_config.termination_lvd == 0) {
10742 asc_dvc->cfg->termination = termination; /* auto termination for LVD */
10744 /* Enable manual control with low off / high off. */
10745 if (eep_config.termination_lvd == 1) {
10746 asc_dvc->cfg->termination = termination;
10748 /* Enable manual control with low off / high on. */
10749 } else if (eep_config.termination_lvd == 2) {
10750 asc_dvc->cfg->termination = termination | TERM_LVD_HI;
10752 /* Enable manual control with low on / high on. */
10753 } else if (eep_config.termination_lvd == 3) {
10754 asc_dvc->cfg->termination = termination | TERM_LVD;
10757 * The EEPROM 'termination_lvd' field contains a bad value.
10758 * Use automatic termination instead.
10760 asc_dvc->cfg->termination = termination;
10761 warn_code |= ASC_WARN_EEPROM_TERMINATION;
10769 * Read the board's EEPROM configuration. Set fields in ASC_DVC_VAR and
10770 * ASC_DVC_CFG based on the EEPROM settings. The chip is stopped while
10771 * all of this is done.
10773 * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR.
10775 * For a non-fatal error return a warning code. If there are no warnings
10776 * then 0 is returned.
10778 * Note: Chip is stopped on entry.
10780 static int AdvInitFrom38C1600EEP(ADV_DVC_VAR *asc_dvc)
10782 AdvPortAddr iop_base;
10784 ADVEEP_38C1600_CONFIG eep_config;
10785 uchar tid, termination;
10786 ushort sdtr_speed = 0;
10788 iop_base = asc_dvc->iop_base;
10793 * Read the board's EEPROM configuration.
10795 * Set default values if a bad checksum is found.
10797 if (AdvGet38C1600EEPConfig(iop_base, &eep_config) !=
10798 eep_config.check_sum) {
10799 struct pci_dev *pdev = adv_dvc_to_pdev(asc_dvc);
10800 warn_code |= ASC_WARN_EEPROM_CHKSUM;
10803 * Set EEPROM default values.
10805 memcpy(&eep_config, &Default_38C1600_EEPROM_Config,
10806 sizeof(ADVEEP_38C1600_CONFIG));
10808 if (PCI_FUNC(pdev->devfn) != 0) {
10811 * Disable Bit 14 (BIOS_ENABLE) to fix SPARC Ultra 60
10812 * and old Mac system booting problem. The Expansion
10813 * ROM must be disabled in Function 1 for these systems
10815 eep_config.cfg_lsw &= ~ADV_EEPROM_BIOS_ENABLE;
10817 * Clear the INTAB (bit 11) if the GPIO 0 input
10818 * indicates the Function 1 interrupt line is wired
10821 * Set/Clear Bit 11 (INTAB) from the GPIO bit 0 input:
10822 * 1 - Function 1 interrupt line wired to INT A.
10823 * 0 - Function 1 interrupt line wired to INT B.
10825 * Note: Function 0 is always wired to INTA.
10826 * Put all 5 GPIO bits in input mode and then read
10827 * their input values.
10829 AdvWriteByteRegister(iop_base, IOPB_GPIO_CNTL, 0);
10830 ints = AdvReadByteRegister(iop_base, IOPB_GPIO_DATA);
10831 if ((ints & 0x01) == 0)
10832 eep_config.cfg_lsw &= ~ADV_EEPROM_INTAB;
10836 * Assume the 6 byte board serial number that was read from
10837 * EEPROM is correct even if the EEPROM checksum failed.
10839 eep_config.serial_number_word3 =
10840 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
10841 eep_config.serial_number_word2 =
10842 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
10843 eep_config.serial_number_word1 =
10844 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
10846 AdvSet38C1600EEPConfig(iop_base, &eep_config);
10850 * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the
10851 * EEPROM configuration that was read.
10853 * This is the mapping of EEPROM fields to Adv Library fields.
10855 asc_dvc->wdtr_able = eep_config.wdtr_able;
10856 asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1;
10857 asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2;
10858 asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3;
10859 asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4;
10860 asc_dvc->ppr_able = 0;
10861 asc_dvc->tagqng_able = eep_config.tagqng_able;
10862 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
10863 asc_dvc->max_host_qng = eep_config.max_host_qng;
10864 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
10865 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ASC_MAX_TID);
10866 asc_dvc->start_motor = eep_config.start_motor;
10867 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
10868 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
10869 asc_dvc->no_scam = eep_config.scam_tolerant;
10872 * For every Target ID if any of its 'sdtr_speed[1234]' bits
10873 * are set, then set an 'sdtr_able' bit for it.
10875 asc_dvc->sdtr_able = 0;
10876 for (tid = 0; tid <= ASC_MAX_TID; tid++) {
10878 sdtr_speed = asc_dvc->sdtr_speed1;
10879 } else if (tid == 4) {
10880 sdtr_speed = asc_dvc->sdtr_speed2;
10881 } else if (tid == 8) {
10882 sdtr_speed = asc_dvc->sdtr_speed3;
10883 } else if (tid == 12) {
10884 sdtr_speed = asc_dvc->sdtr_speed4;
10886 if (sdtr_speed & ASC_MAX_TID) {
10887 asc_dvc->sdtr_able |= (1 << tid);
10893 * Set the host maximum queuing (max. 253, min. 16) and the per device
10894 * maximum queuing (max. 63, min. 4).
10896 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
10897 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10898 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
10899 /* If the value is zero, assume it is uninitialized. */
10900 if (eep_config.max_host_qng == 0) {
10901 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10903 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
10907 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
10908 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10909 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
10910 /* If the value is zero, assume it is uninitialized. */
10911 if (eep_config.max_dvc_qng == 0) {
10912 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10914 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
10919 * If 'max_dvc_qng' is greater than 'max_host_qng', then
10920 * set 'max_dvc_qng' to 'max_host_qng'.
10922 if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
10923 eep_config.max_dvc_qng = eep_config.max_host_qng;
10927 * Set ASC_DVC_VAR 'max_host_qng' and ASC_DVC_VAR 'max_dvc_qng'
10928 * values based on possibly adjusted EEPROM values.
10930 asc_dvc->max_host_qng = eep_config.max_host_qng;
10931 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
10934 * If the EEPROM 'termination' field is set to automatic (0), then set
10935 * the ASC_DVC_CFG 'termination' field to automatic also.
10937 * If the termination is specified with a non-zero 'termination'
10938 * value check that a legal value is set and set the ASC_DVC_CFG
10939 * 'termination' field appropriately.
10941 if (eep_config.termination_se == 0) {
10942 termination = 0; /* auto termination for SE */
10944 /* Enable manual control with low off / high off. */
10945 if (eep_config.termination_se == 1) {
10948 /* Enable manual control with low off / high on. */
10949 } else if (eep_config.termination_se == 2) {
10950 termination = TERM_SE_HI;
10952 /* Enable manual control with low on / high on. */
10953 } else if (eep_config.termination_se == 3) {
10954 termination = TERM_SE;
10957 * The EEPROM 'termination_se' field contains a bad value.
10958 * Use automatic termination instead.
10961 warn_code |= ASC_WARN_EEPROM_TERMINATION;
10965 if (eep_config.termination_lvd == 0) {
10966 asc_dvc->cfg->termination = termination; /* auto termination for LVD */
10968 /* Enable manual control with low off / high off. */
10969 if (eep_config.termination_lvd == 1) {
10970 asc_dvc->cfg->termination = termination;
10972 /* Enable manual control with low off / high on. */
10973 } else if (eep_config.termination_lvd == 2) {
10974 asc_dvc->cfg->termination = termination | TERM_LVD_HI;
10976 /* Enable manual control with low on / high on. */
10977 } else if (eep_config.termination_lvd == 3) {
10978 asc_dvc->cfg->termination = termination | TERM_LVD;
10981 * The EEPROM 'termination_lvd' field contains a bad value.
10982 * Use automatic termination instead.
10984 asc_dvc->cfg->termination = termination;
10985 warn_code |= ASC_WARN_EEPROM_TERMINATION;
10993 * Initialize the ADV_DVC_VAR structure.
10995 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
10997 * For a non-fatal error return a warning code. If there are no warnings
10998 * then 0 is returned.
11000 static int AdvInitGetConfig(struct pci_dev *pdev, struct Scsi_Host *shost)
11002 struct asc_board *board = shost_priv(shost);
11003 ADV_DVC_VAR *asc_dvc = &board->dvc_var.adv_dvc_var;
11004 unsigned short warn_code = 0;
11005 AdvPortAddr iop_base = asc_dvc->iop_base;
11009 asc_dvc->err_code = 0;
11012 * Save the state of the PCI Configuration Command Register
11013 * "Parity Error Response Control" Bit. If the bit is clear (0),
11014 * in AdvInitAsc3550/38C0800Driver() tell the microcode to ignore
11015 * DMA parity errors.
11017 asc_dvc->cfg->control_flag = 0;
11018 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
11019 if ((cmd & PCI_COMMAND_PARITY) == 0)
11020 asc_dvc->cfg->control_flag |= CONTROL_FLAG_IGNORE_PERR;
11022 asc_dvc->cfg->chip_version =
11023 AdvGetChipVersion(iop_base, asc_dvc->bus_type);
11025 ASC_DBG(1, "iopb_chip_id_1: 0x%x 0x%x\n",
11026 (ushort)AdvReadByteRegister(iop_base, IOPB_CHIP_ID_1),
11027 (ushort)ADV_CHIP_ID_BYTE);
11029 ASC_DBG(1, "iopw_chip_id_0: 0x%x 0x%x\n",
11030 (ushort)AdvReadWordRegister(iop_base, IOPW_CHIP_ID_0),
11031 (ushort)ADV_CHIP_ID_WORD);
11034 * Reset the chip to start and allow register writes.
11036 if (AdvFindSignature(iop_base) == 0) {
11037 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
11041 * The caller must set 'chip_type' to a valid setting.
11043 if (asc_dvc->chip_type != ADV_CHIP_ASC3550 &&
11044 asc_dvc->chip_type != ADV_CHIP_ASC38C0800 &&
11045 asc_dvc->chip_type != ADV_CHIP_ASC38C1600) {
11046 asc_dvc->err_code |= ASC_IERR_BAD_CHIPTYPE;
11053 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
11054 ADV_CTRL_REG_CMD_RESET);
11056 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
11057 ADV_CTRL_REG_CMD_WR_IO_REG);
11059 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
11060 status = AdvInitFrom38C1600EEP(asc_dvc);
11061 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
11062 status = AdvInitFrom38C0800EEP(asc_dvc);
11064 status = AdvInitFrom3550EEP(asc_dvc);
11066 warn_code |= status;
11069 if (warn_code != 0)
11070 shost_printk(KERN_WARNING, shost, "warning: 0x%x\n", warn_code);
11072 if (asc_dvc->err_code)
11073 shost_printk(KERN_ERR, shost, "error code 0x%x\n",
11074 asc_dvc->err_code);
11076 return asc_dvc->err_code;
11080 static struct scsi_host_template advansys_template = {
11081 .proc_name = DRV_NAME,
11082 #ifdef CONFIG_PROC_FS
11083 .show_info = advansys_show_info,
11086 .info = advansys_info,
11087 .queuecommand = advansys_queuecommand,
11088 .eh_host_reset_handler = advansys_reset,
11089 .bios_param = advansys_biosparam,
11090 .slave_configure = advansys_slave_configure,
11092 * Because the driver may control an ISA adapter 'unchecked_isa_dma'
11093 * must be set. The flag will be cleared in advansys_board_found
11094 * for non-ISA adapters.
11096 .unchecked_isa_dma = 1,
11098 * All adapters controlled by this driver are capable of large
11099 * scatter-gather lists. According to the mid-level SCSI documentation
11100 * this obviates any performance gain provided by setting
11101 * 'use_clustering'. But empirically while CPU utilization is increased
11102 * by enabling clustering, I/O throughput increases as well.
11104 .use_clustering = ENABLE_CLUSTERING,
11108 static int advansys_wide_init_chip(struct Scsi_Host *shost)
11110 struct asc_board *board = shost_priv(shost);
11111 struct adv_dvc_var *adv_dvc = &board->dvc_var.adv_dvc_var;
11112 size_t sgblk_pool_size;
11113 int warn_code, err_code;
11116 * Allocate buffer carrier structures. The total size
11117 * is about 8 KB, so allocate all at once.
11119 adv_dvc->carrier = dma_alloc_coherent(board->dev,
11120 ADV_CARRIER_BUFSIZE, &adv_dvc->carrier_addr, GFP_KERNEL);
11121 ASC_DBG(1, "carrier 0x%p\n", adv_dvc->carrier);
11123 if (!adv_dvc->carrier)
11124 goto kmalloc_failed;
11127 * Allocate up to 'max_host_qng' request structures for the Wide
11128 * board. The total size is about 16 KB, so allocate all at once.
11129 * If the allocation fails decrement and try again.
11131 board->adv_reqp_size = adv_dvc->max_host_qng * sizeof(adv_req_t);
11132 if (board->adv_reqp_size & 0x1f) {
11133 ASC_DBG(1, "unaligned reqp %lu bytes\n", sizeof(adv_req_t));
11134 board->adv_reqp_size = ADV_32BALIGN(board->adv_reqp_size);
11136 board->adv_reqp = dma_alloc_coherent(board->dev, board->adv_reqp_size,
11137 &board->adv_reqp_addr, GFP_KERNEL);
11139 if (!board->adv_reqp)
11140 goto kmalloc_failed;
11142 ASC_DBG(1, "reqp 0x%p, req_cnt %d, bytes %lu\n", board->adv_reqp,
11143 adv_dvc->max_host_qng, board->adv_reqp_size);
11146 * Allocate up to ADV_TOT_SG_BLOCK request structures for
11147 * the Wide board. Each structure is about 136 bytes.
11149 sgblk_pool_size = sizeof(adv_sgblk_t) * ADV_TOT_SG_BLOCK;
11150 board->adv_sgblk_pool = dma_pool_create("adv_sgblk", board->dev,
11151 sgblk_pool_size, 32, 0);
11153 ASC_DBG(1, "sg_cnt %d * %lu = %lu bytes\n", ADV_TOT_SG_BLOCK,
11154 sizeof(adv_sgblk_t), sgblk_pool_size);
11156 if (!board->adv_sgblk_pool)
11157 goto kmalloc_failed;
11159 if (adv_dvc->chip_type == ADV_CHIP_ASC3550) {
11160 ASC_DBG(2, "AdvInitAsc3550Driver()\n");
11161 warn_code = AdvInitAsc3550Driver(adv_dvc);
11162 } else if (adv_dvc->chip_type == ADV_CHIP_ASC38C0800) {
11163 ASC_DBG(2, "AdvInitAsc38C0800Driver()\n");
11164 warn_code = AdvInitAsc38C0800Driver(adv_dvc);
11166 ASC_DBG(2, "AdvInitAsc38C1600Driver()\n");
11167 warn_code = AdvInitAsc38C1600Driver(adv_dvc);
11169 err_code = adv_dvc->err_code;
11171 if (warn_code || err_code) {
11172 shost_printk(KERN_WARNING, shost, "error: warn 0x%x, error "
11173 "0x%x\n", warn_code, err_code);
11179 shost_printk(KERN_ERR, shost, "error: kmalloc() failed\n");
11180 err_code = ADV_ERROR;
11185 static void advansys_wide_free_mem(struct asc_board *board)
11187 struct adv_dvc_var *adv_dvc = &board->dvc_var.adv_dvc_var;
11189 if (adv_dvc->carrier) {
11190 dma_free_coherent(board->dev, ADV_CARRIER_BUFSIZE,
11191 adv_dvc->carrier, adv_dvc->carrier_addr);
11192 adv_dvc->carrier = NULL;
11194 if (board->adv_reqp) {
11195 dma_free_coherent(board->dev, board->adv_reqp_size,
11196 board->adv_reqp, board->adv_reqp_addr);
11197 board->adv_reqp = NULL;
11199 if (board->adv_sgblk_pool) {
11200 dma_pool_destroy(board->adv_sgblk_pool);
11201 board->adv_sgblk_pool = NULL;
11205 static int advansys_board_found(struct Scsi_Host *shost, unsigned int iop,
11208 struct pci_dev *pdev;
11209 struct asc_board *boardp = shost_priv(shost);
11210 ASC_DVC_VAR *asc_dvc_varp = NULL;
11211 ADV_DVC_VAR *adv_dvc_varp = NULL;
11212 int share_irq, warn_code, ret;
11214 pdev = (bus_type == ASC_IS_PCI) ? to_pci_dev(boardp->dev) : NULL;
11216 if (ASC_NARROW_BOARD(boardp)) {
11217 ASC_DBG(1, "narrow board\n");
11218 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
11219 asc_dvc_varp->bus_type = bus_type;
11220 asc_dvc_varp->drv_ptr = boardp;
11221 asc_dvc_varp->cfg = &boardp->dvc_cfg.asc_dvc_cfg;
11222 asc_dvc_varp->iop_base = iop;
11225 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
11226 adv_dvc_varp->drv_ptr = boardp;
11227 adv_dvc_varp->cfg = &boardp->dvc_cfg.adv_dvc_cfg;
11228 if (pdev->device == PCI_DEVICE_ID_ASP_ABP940UW) {
11229 ASC_DBG(1, "wide board ASC-3550\n");
11230 adv_dvc_varp->chip_type = ADV_CHIP_ASC3550;
11231 } else if (pdev->device == PCI_DEVICE_ID_38C0800_REV1) {
11232 ASC_DBG(1, "wide board ASC-38C0800\n");
11233 adv_dvc_varp->chip_type = ADV_CHIP_ASC38C0800;
11235 ASC_DBG(1, "wide board ASC-38C1600\n");
11236 adv_dvc_varp->chip_type = ADV_CHIP_ASC38C1600;
11239 boardp->asc_n_io_port = pci_resource_len(pdev, 1);
11240 boardp->ioremap_addr = pci_ioremap_bar(pdev, 1);
11241 if (!boardp->ioremap_addr) {
11242 shost_printk(KERN_ERR, shost, "ioremap(%lx, %d) "
11244 (long)pci_resource_start(pdev, 1),
11245 boardp->asc_n_io_port);
11249 adv_dvc_varp->iop_base = (AdvPortAddr)boardp->ioremap_addr;
11250 ASC_DBG(1, "iop_base: 0x%p\n", adv_dvc_varp->iop_base);
11253 * Even though it isn't used to access wide boards, other
11254 * than for the debug line below, save I/O Port address so
11255 * that it can be reported.
11257 boardp->ioport = iop;
11259 ASC_DBG(1, "iopb_chip_id_1 0x%x, iopw_chip_id_0 0x%x\n",
11260 (ushort)inp(iop + 1), (ushort)inpw(iop));
11261 #endif /* CONFIG_PCI */
11264 if (ASC_NARROW_BOARD(boardp)) {
11266 * Set the board bus type and PCI IRQ before
11267 * calling AscInitGetConfig().
11269 switch (asc_dvc_varp->bus_type) {
11272 shost->unchecked_isa_dma = TRUE;
11276 shost->unchecked_isa_dma = FALSE;
11280 shost->unchecked_isa_dma = FALSE;
11281 share_irq = IRQF_SHARED;
11283 #endif /* CONFIG_ISA */
11286 shost->unchecked_isa_dma = FALSE;
11287 share_irq = IRQF_SHARED;
11289 #endif /* CONFIG_PCI */
11291 shost_printk(KERN_ERR, shost, "unknown adapter type: "
11292 "%d\n", asc_dvc_varp->bus_type);
11293 shost->unchecked_isa_dma = TRUE;
11299 * NOTE: AscInitGetConfig() may change the board's
11300 * bus_type value. The bus_type value should no
11301 * longer be used. If the bus_type field must be
11302 * referenced only use the bit-wise AND operator "&".
11304 ASC_DBG(2, "AscInitGetConfig()\n");
11305 ret = AscInitGetConfig(shost) ? -ENODEV : 0;
11309 * For Wide boards set PCI information before calling
11310 * AdvInitGetConfig().
11312 shost->unchecked_isa_dma = FALSE;
11313 share_irq = IRQF_SHARED;
11314 ASC_DBG(2, "AdvInitGetConfig()\n");
11316 ret = AdvInitGetConfig(pdev, shost) ? -ENODEV : 0;
11317 #endif /* CONFIG_PCI */
11324 * Save the EEPROM configuration so that it can be displayed
11325 * from /proc/scsi/advansys/[0...].
11327 if (ASC_NARROW_BOARD(boardp)) {
11332 * Set the adapter's target id bit in the 'init_tidmask' field.
11334 boardp->init_tidmask |=
11335 ADV_TID_TO_TIDMASK(asc_dvc_varp->cfg->chip_scsi_id);
11338 * Save EEPROM settings for the board.
11340 ep = &boardp->eep_config.asc_eep;
11342 ep->init_sdtr = asc_dvc_varp->cfg->sdtr_enable;
11343 ep->disc_enable = asc_dvc_varp->cfg->disc_enable;
11344 ep->use_cmd_qng = asc_dvc_varp->cfg->cmd_qng_enabled;
11345 ASC_EEP_SET_DMA_SPD(ep, asc_dvc_varp->cfg->isa_dma_speed);
11346 ep->start_motor = asc_dvc_varp->start_motor;
11347 ep->cntl = asc_dvc_varp->dvc_cntl;
11348 ep->no_scam = asc_dvc_varp->no_scam;
11349 ep->max_total_qng = asc_dvc_varp->max_total_qng;
11350 ASC_EEP_SET_CHIP_ID(ep, asc_dvc_varp->cfg->chip_scsi_id);
11351 /* 'max_tag_qng' is set to the same value for every device. */
11352 ep->max_tag_qng = asc_dvc_varp->cfg->max_tag_qng[0];
11353 ep->adapter_info[0] = asc_dvc_varp->cfg->adapter_info[0];
11354 ep->adapter_info[1] = asc_dvc_varp->cfg->adapter_info[1];
11355 ep->adapter_info[2] = asc_dvc_varp->cfg->adapter_info[2];
11356 ep->adapter_info[3] = asc_dvc_varp->cfg->adapter_info[3];
11357 ep->adapter_info[4] = asc_dvc_varp->cfg->adapter_info[4];
11358 ep->adapter_info[5] = asc_dvc_varp->cfg->adapter_info[5];
11361 * Modify board configuration.
11363 ASC_DBG(2, "AscInitSetConfig()\n");
11364 ret = AscInitSetConfig(pdev, shost) ? -ENODEV : 0;
11368 ADVEEP_3550_CONFIG *ep_3550;
11369 ADVEEP_38C0800_CONFIG *ep_38C0800;
11370 ADVEEP_38C1600_CONFIG *ep_38C1600;
11373 * Save Wide EEP Configuration Information.
11375 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
11376 ep_3550 = &boardp->eep_config.adv_3550_eep;
11378 ep_3550->adapter_scsi_id = adv_dvc_varp->chip_scsi_id;
11379 ep_3550->max_host_qng = adv_dvc_varp->max_host_qng;
11380 ep_3550->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
11381 ep_3550->termination = adv_dvc_varp->cfg->termination;
11382 ep_3550->disc_enable = adv_dvc_varp->cfg->disc_enable;
11383 ep_3550->bios_ctrl = adv_dvc_varp->bios_ctrl;
11384 ep_3550->wdtr_able = adv_dvc_varp->wdtr_able;
11385 ep_3550->sdtr_able = adv_dvc_varp->sdtr_able;
11386 ep_3550->ultra_able = adv_dvc_varp->ultra_able;
11387 ep_3550->tagqng_able = adv_dvc_varp->tagqng_able;
11388 ep_3550->start_motor = adv_dvc_varp->start_motor;
11389 ep_3550->scsi_reset_delay =
11390 adv_dvc_varp->scsi_reset_wait;
11391 ep_3550->serial_number_word1 =
11392 adv_dvc_varp->cfg->serial1;
11393 ep_3550->serial_number_word2 =
11394 adv_dvc_varp->cfg->serial2;
11395 ep_3550->serial_number_word3 =
11396 adv_dvc_varp->cfg->serial3;
11397 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
11398 ep_38C0800 = &boardp->eep_config.adv_38C0800_eep;
11400 ep_38C0800->adapter_scsi_id =
11401 adv_dvc_varp->chip_scsi_id;
11402 ep_38C0800->max_host_qng = adv_dvc_varp->max_host_qng;
11403 ep_38C0800->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
11404 ep_38C0800->termination_lvd =
11405 adv_dvc_varp->cfg->termination;
11406 ep_38C0800->disc_enable =
11407 adv_dvc_varp->cfg->disc_enable;
11408 ep_38C0800->bios_ctrl = adv_dvc_varp->bios_ctrl;
11409 ep_38C0800->wdtr_able = adv_dvc_varp->wdtr_able;
11410 ep_38C0800->tagqng_able = adv_dvc_varp->tagqng_able;
11411 ep_38C0800->sdtr_speed1 = adv_dvc_varp->sdtr_speed1;
11412 ep_38C0800->sdtr_speed2 = adv_dvc_varp->sdtr_speed2;
11413 ep_38C0800->sdtr_speed3 = adv_dvc_varp->sdtr_speed3;
11414 ep_38C0800->sdtr_speed4 = adv_dvc_varp->sdtr_speed4;
11415 ep_38C0800->tagqng_able = adv_dvc_varp->tagqng_able;
11416 ep_38C0800->start_motor = adv_dvc_varp->start_motor;
11417 ep_38C0800->scsi_reset_delay =
11418 adv_dvc_varp->scsi_reset_wait;
11419 ep_38C0800->serial_number_word1 =
11420 adv_dvc_varp->cfg->serial1;
11421 ep_38C0800->serial_number_word2 =
11422 adv_dvc_varp->cfg->serial2;
11423 ep_38C0800->serial_number_word3 =
11424 adv_dvc_varp->cfg->serial3;
11426 ep_38C1600 = &boardp->eep_config.adv_38C1600_eep;
11428 ep_38C1600->adapter_scsi_id =
11429 adv_dvc_varp->chip_scsi_id;
11430 ep_38C1600->max_host_qng = adv_dvc_varp->max_host_qng;
11431 ep_38C1600->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
11432 ep_38C1600->termination_lvd =
11433 adv_dvc_varp->cfg->termination;
11434 ep_38C1600->disc_enable =
11435 adv_dvc_varp->cfg->disc_enable;
11436 ep_38C1600->bios_ctrl = adv_dvc_varp->bios_ctrl;
11437 ep_38C1600->wdtr_able = adv_dvc_varp->wdtr_able;
11438 ep_38C1600->tagqng_able = adv_dvc_varp->tagqng_able;
11439 ep_38C1600->sdtr_speed1 = adv_dvc_varp->sdtr_speed1;
11440 ep_38C1600->sdtr_speed2 = adv_dvc_varp->sdtr_speed2;
11441 ep_38C1600->sdtr_speed3 = adv_dvc_varp->sdtr_speed3;
11442 ep_38C1600->sdtr_speed4 = adv_dvc_varp->sdtr_speed4;
11443 ep_38C1600->tagqng_able = adv_dvc_varp->tagqng_able;
11444 ep_38C1600->start_motor = adv_dvc_varp->start_motor;
11445 ep_38C1600->scsi_reset_delay =
11446 adv_dvc_varp->scsi_reset_wait;
11447 ep_38C1600->serial_number_word1 =
11448 adv_dvc_varp->cfg->serial1;
11449 ep_38C1600->serial_number_word2 =
11450 adv_dvc_varp->cfg->serial2;
11451 ep_38C1600->serial_number_word3 =
11452 adv_dvc_varp->cfg->serial3;
11456 * Set the adapter's target id bit in the 'init_tidmask' field.
11458 boardp->init_tidmask |=
11459 ADV_TID_TO_TIDMASK(adv_dvc_varp->chip_scsi_id);
11463 * Channels are numbered beginning with 0. For AdvanSys one host
11464 * structure supports one channel. Multi-channel boards have a
11465 * separate host structure for each channel.
11467 shost->max_channel = 0;
11468 if (ASC_NARROW_BOARD(boardp)) {
11469 shost->max_id = ASC_MAX_TID + 1;
11470 shost->max_lun = ASC_MAX_LUN + 1;
11471 shost->max_cmd_len = ASC_MAX_CDB_LEN;
11473 shost->io_port = asc_dvc_varp->iop_base;
11474 boardp->asc_n_io_port = ASC_IOADR_GAP;
11475 shost->this_id = asc_dvc_varp->cfg->chip_scsi_id;
11477 /* Set maximum number of queues the adapter can handle. */
11478 shost->can_queue = asc_dvc_varp->max_total_qng;
11480 shost->max_id = ADV_MAX_TID + 1;
11481 shost->max_lun = ADV_MAX_LUN + 1;
11482 shost->max_cmd_len = ADV_MAX_CDB_LEN;
11485 * Save the I/O Port address and length even though
11486 * I/O ports are not used to access Wide boards.
11487 * Instead the Wide boards are accessed with
11488 * PCI Memory Mapped I/O.
11490 shost->io_port = iop;
11492 shost->this_id = adv_dvc_varp->chip_scsi_id;
11494 /* Set maximum number of queues the adapter can handle. */
11495 shost->can_queue = adv_dvc_varp->max_host_qng;
11497 ret = scsi_init_shared_tag_map(shost, shost->can_queue);
11499 shost_printk(KERN_ERR, shost, "init tag map failed\n");
11504 * Following v1.3.89, 'cmd_per_lun' is no longer needed
11505 * and should be set to zero.
11507 * But because of a bug introduced in v1.3.89 if the driver is
11508 * compiled as a module and 'cmd_per_lun' is zero, the Mid-Level
11509 * SCSI function 'allocate_device' will panic. To allow the driver
11510 * to work as a module in these kernels set 'cmd_per_lun' to 1.
11512 * Note: This is wrong. cmd_per_lun should be set to the depth
11513 * you want on untagged devices always.
11516 shost->cmd_per_lun = 1;
11518 shost->cmd_per_lun = 0;
11522 * Set the maximum number of scatter-gather elements the
11523 * adapter can handle.
11525 if (ASC_NARROW_BOARD(boardp)) {
11527 * Allow two commands with 'sg_tablesize' scatter-gather
11528 * elements to be executed simultaneously. This value is
11529 * the theoretical hardware limit. It may be decreased
11532 shost->sg_tablesize =
11533 (((asc_dvc_varp->max_total_qng - 2) / 2) *
11534 ASC_SG_LIST_PER_Q) + 1;
11536 shost->sg_tablesize = ADV_MAX_SG_LIST;
11540 * The value of 'sg_tablesize' can not exceed the SCSI
11541 * mid-level driver definition of SG_ALL. SG_ALL also
11542 * must not be exceeded, because it is used to define the
11543 * size of the scatter-gather table in 'struct asc_sg_head'.
11545 if (shost->sg_tablesize > SG_ALL) {
11546 shost->sg_tablesize = SG_ALL;
11549 ASC_DBG(1, "sg_tablesize: %d\n", shost->sg_tablesize);
11551 /* BIOS start address. */
11552 if (ASC_NARROW_BOARD(boardp)) {
11553 shost->base = AscGetChipBiosAddress(asc_dvc_varp->iop_base,
11554 asc_dvc_varp->bus_type);
11557 * Fill-in BIOS board variables. The Wide BIOS saves
11558 * information in LRAM that is used by the driver.
11560 AdvReadWordLram(adv_dvc_varp->iop_base,
11561 BIOS_SIGNATURE, boardp->bios_signature);
11562 AdvReadWordLram(adv_dvc_varp->iop_base,
11563 BIOS_VERSION, boardp->bios_version);
11564 AdvReadWordLram(adv_dvc_varp->iop_base,
11565 BIOS_CODESEG, boardp->bios_codeseg);
11566 AdvReadWordLram(adv_dvc_varp->iop_base,
11567 BIOS_CODELEN, boardp->bios_codelen);
11569 ASC_DBG(1, "bios_signature 0x%x, bios_version 0x%x\n",
11570 boardp->bios_signature, boardp->bios_version);
11572 ASC_DBG(1, "bios_codeseg 0x%x, bios_codelen 0x%x\n",
11573 boardp->bios_codeseg, boardp->bios_codelen);
11576 * If the BIOS saved a valid signature, then fill in
11577 * the BIOS code segment base address.
11579 if (boardp->bios_signature == 0x55AA) {
11581 * Convert x86 realmode code segment to a linear
11582 * address by shifting left 4.
11584 shost->base = ((ulong)boardp->bios_codeseg << 4);
11591 * Register Board Resources - I/O Port, DMA, IRQ
11594 /* Register DMA Channel for Narrow boards. */
11595 shost->dma_channel = NO_ISA_DMA; /* Default to no ISA DMA. */
11597 if (ASC_NARROW_BOARD(boardp)) {
11598 /* Register DMA channel for ISA bus. */
11599 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
11600 shost->dma_channel = asc_dvc_varp->cfg->isa_dma_channel;
11601 ret = request_dma(shost->dma_channel, DRV_NAME);
11603 shost_printk(KERN_ERR, shost, "request_dma() "
11605 shost->dma_channel, ret);
11608 AscEnableIsaDma(shost->dma_channel);
11611 #endif /* CONFIG_ISA */
11613 /* Register IRQ Number. */
11614 ASC_DBG(2, "request_irq(%d, %p)\n", boardp->irq, shost);
11616 ret = request_irq(boardp->irq, advansys_interrupt, share_irq,
11620 if (ret == -EBUSY) {
11621 shost_printk(KERN_ERR, shost, "request_irq(): IRQ 0x%x "
11622 "already in use\n", boardp->irq);
11623 } else if (ret == -EINVAL) {
11624 shost_printk(KERN_ERR, shost, "request_irq(): IRQ 0x%x "
11625 "not valid\n", boardp->irq);
11627 shost_printk(KERN_ERR, shost, "request_irq(): IRQ 0x%x "
11628 "failed with %d\n", boardp->irq, ret);
11634 * Initialize board RISC chip and enable interrupts.
11636 if (ASC_NARROW_BOARD(boardp)) {
11637 ASC_DBG(2, "AscInitAsc1000Driver()\n");
11639 asc_dvc_varp->overrun_buf = kzalloc(ASC_OVERRUN_BSIZE, GFP_KERNEL);
11640 if (!asc_dvc_varp->overrun_buf) {
11644 warn_code = AscInitAsc1000Driver(asc_dvc_varp);
11646 if (warn_code || asc_dvc_varp->err_code) {
11647 shost_printk(KERN_ERR, shost, "error: init_state 0x%x, "
11648 "warn 0x%x, error 0x%x\n",
11649 asc_dvc_varp->init_state, warn_code,
11650 asc_dvc_varp->err_code);
11651 if (!asc_dvc_varp->overrun_dma) {
11657 if (advansys_wide_init_chip(shost)) {
11663 ASC_DBG_PRT_SCSI_HOST(2, shost);
11665 ret = scsi_add_host(shost, boardp->dev);
11669 scsi_scan_host(shost);
11673 if (ASC_NARROW_BOARD(boardp)) {
11674 if (asc_dvc_varp->overrun_dma)
11675 dma_unmap_single(boardp->dev, asc_dvc_varp->overrun_dma,
11676 ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE);
11677 kfree(asc_dvc_varp->overrun_buf);
11679 advansys_wide_free_mem(boardp);
11681 free_irq(boardp->irq, shost);
11684 if (shost->dma_channel != NO_ISA_DMA)
11685 free_dma(shost->dma_channel);
11688 if (boardp->ioremap_addr)
11689 iounmap(boardp->ioremap_addr);
11695 * advansys_release()
11697 * Release resources allocated for a single AdvanSys adapter.
11699 static int advansys_release(struct Scsi_Host *shost)
11701 struct asc_board *board = shost_priv(shost);
11702 ASC_DBG(1, "begin\n");
11703 scsi_remove_host(shost);
11704 free_irq(board->irq, shost);
11706 if (shost->dma_channel != NO_ISA_DMA) {
11707 ASC_DBG(1, "free_dma()\n");
11708 free_dma(shost->dma_channel);
11711 if (ASC_NARROW_BOARD(board)) {
11712 dma_unmap_single(board->dev,
11713 board->dvc_var.asc_dvc_var.overrun_dma,
11714 ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE);
11715 kfree(board->dvc_var.asc_dvc_var.overrun_buf);
11717 iounmap(board->ioremap_addr);
11718 advansys_wide_free_mem(board);
11720 scsi_host_put(shost);
11721 ASC_DBG(1, "end\n");
11725 #define ASC_IOADR_TABLE_MAX_IX 11
11727 static PortAddr _asc_def_iop_base[ASC_IOADR_TABLE_MAX_IX] = {
11728 0x100, 0x0110, 0x120, 0x0130, 0x140, 0x0150, 0x0190,
11729 0x0210, 0x0230, 0x0250, 0x0330
11733 * The ISA IRQ number is found in bits 2 and 3 of the CfgLsw. It decodes as:
11739 static unsigned int advansys_isa_irq_no(PortAddr iop_base)
11741 unsigned short cfg_lsw = AscGetChipCfgLsw(iop_base);
11742 unsigned int chip_irq = ((cfg_lsw >> 2) & 0x03) + 10;
11743 if (chip_irq == 13)
11748 static int advansys_isa_probe(struct device *dev, unsigned int id)
11751 PortAddr iop_base = _asc_def_iop_base[id];
11752 struct Scsi_Host *shost;
11753 struct asc_board *board;
11755 if (!request_region(iop_base, ASC_IOADR_GAP, DRV_NAME)) {
11756 ASC_DBG(1, "I/O port 0x%x busy\n", iop_base);
11759 ASC_DBG(1, "probing I/O port 0x%x\n", iop_base);
11760 if (!AscFindSignature(iop_base))
11761 goto release_region;
11762 if (!(AscGetChipVersion(iop_base, ASC_IS_ISA) & ASC_CHIP_VER_ISA_BIT))
11763 goto release_region;
11766 shost = scsi_host_alloc(&advansys_template, sizeof(*board));
11768 goto release_region;
11770 board = shost_priv(shost);
11771 board->irq = advansys_isa_irq_no(iop_base);
11773 board->shost = shost;
11775 err = advansys_board_found(shost, iop_base, ASC_IS_ISA);
11779 dev_set_drvdata(dev, shost);
11783 scsi_host_put(shost);
11785 release_region(iop_base, ASC_IOADR_GAP);
11789 static int advansys_isa_remove(struct device *dev, unsigned int id)
11791 int ioport = _asc_def_iop_base[id];
11792 advansys_release(dev_get_drvdata(dev));
11793 release_region(ioport, ASC_IOADR_GAP);
11797 static struct isa_driver advansys_isa_driver = {
11798 .probe = advansys_isa_probe,
11799 .remove = advansys_isa_remove,
11801 .owner = THIS_MODULE,
11807 * The VLB IRQ number is found in bits 2 to 4 of the CfgLsw. It decodes as:
11817 static unsigned int advansys_vlb_irq_no(PortAddr iop_base)
11819 unsigned short cfg_lsw = AscGetChipCfgLsw(iop_base);
11820 unsigned int chip_irq = ((cfg_lsw >> 2) & 0x07) + 9;
11821 if ((chip_irq < 10) || (chip_irq == 13) || (chip_irq > 15))
11826 static int advansys_vlb_probe(struct device *dev, unsigned int id)
11829 PortAddr iop_base = _asc_def_iop_base[id];
11830 struct Scsi_Host *shost;
11831 struct asc_board *board;
11833 if (!request_region(iop_base, ASC_IOADR_GAP, DRV_NAME)) {
11834 ASC_DBG(1, "I/O port 0x%x busy\n", iop_base);
11837 ASC_DBG(1, "probing I/O port 0x%x\n", iop_base);
11838 if (!AscFindSignature(iop_base))
11839 goto release_region;
11841 * I don't think this condition can actually happen, but the old
11842 * driver did it, and the chances of finding a VLB setup in 2007
11843 * to do testing with is slight to none.
11845 if (AscGetChipVersion(iop_base, ASC_IS_VL) > ASC_CHIP_MAX_VER_VL)
11846 goto release_region;
11849 shost = scsi_host_alloc(&advansys_template, sizeof(*board));
11851 goto release_region;
11853 board = shost_priv(shost);
11854 board->irq = advansys_vlb_irq_no(iop_base);
11856 board->shost = shost;
11858 err = advansys_board_found(shost, iop_base, ASC_IS_VL);
11862 dev_set_drvdata(dev, shost);
11866 scsi_host_put(shost);
11868 release_region(iop_base, ASC_IOADR_GAP);
11872 static struct isa_driver advansys_vlb_driver = {
11873 .probe = advansys_vlb_probe,
11874 .remove = advansys_isa_remove,
11876 .owner = THIS_MODULE,
11877 .name = "advansys_vlb",
11881 static struct eisa_device_id advansys_eisa_table[] = {
11887 MODULE_DEVICE_TABLE(eisa, advansys_eisa_table);
11890 * EISA is a little more tricky than PCI; each EISA device may have two
11891 * channels, and this driver is written to make each channel its own Scsi_Host
11893 struct eisa_scsi_data {
11894 struct Scsi_Host *host[2];
11898 * The EISA IRQ number is found in bits 8 to 10 of the CfgLsw. It decodes as:
11908 static unsigned int advansys_eisa_irq_no(struct eisa_device *edev)
11910 unsigned short cfg_lsw = inw(edev->base_addr + 0xc86);
11911 unsigned int chip_irq = ((cfg_lsw >> 8) & 0x07) + 10;
11912 if ((chip_irq == 13) || (chip_irq > 15))
11917 static int advansys_eisa_probe(struct device *dev)
11919 int i, ioport, irq = 0;
11921 struct eisa_device *edev = to_eisa_device(dev);
11922 struct eisa_scsi_data *data;
11925 data = kzalloc(sizeof(*data), GFP_KERNEL);
11928 ioport = edev->base_addr + 0xc30;
11931 for (i = 0; i < 2; i++, ioport += 0x20) {
11932 struct asc_board *board;
11933 struct Scsi_Host *shost;
11934 if (!request_region(ioport, ASC_IOADR_GAP, DRV_NAME)) {
11935 printk(KERN_WARNING "Region %x-%x busy\n", ioport,
11936 ioport + ASC_IOADR_GAP - 1);
11939 if (!AscFindSignature(ioport)) {
11940 release_region(ioport, ASC_IOADR_GAP);
11945 * I don't know why we need to do this for EISA chips, but
11946 * not for any others. It looks to be equivalent to
11947 * AscGetChipCfgMsw, but I may have overlooked something,
11948 * so I'm not converting it until I get an EISA board to
11954 irq = advansys_eisa_irq_no(edev);
11957 shost = scsi_host_alloc(&advansys_template, sizeof(*board));
11959 goto release_region;
11961 board = shost_priv(shost);
11964 board->shost = shost;
11966 err = advansys_board_found(shost, ioport, ASC_IS_EISA);
11968 data->host[i] = shost;
11972 scsi_host_put(shost);
11974 release_region(ioport, ASC_IOADR_GAP);
11980 dev_set_drvdata(dev, data);
11984 kfree(data->host[0]);
11985 kfree(data->host[1]);
11991 static int advansys_eisa_remove(struct device *dev)
11994 struct eisa_scsi_data *data = dev_get_drvdata(dev);
11996 for (i = 0; i < 2; i++) {
11998 struct Scsi_Host *shost = data->host[i];
12001 ioport = shost->io_port;
12002 advansys_release(shost);
12003 release_region(ioport, ASC_IOADR_GAP);
12010 static struct eisa_driver advansys_eisa_driver = {
12011 .id_table = advansys_eisa_table,
12014 .probe = advansys_eisa_probe,
12015 .remove = advansys_eisa_remove,
12019 /* PCI Devices supported by this driver */
12020 static struct pci_device_id advansys_pci_tbl[] = {
12021 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_1200A,
12022 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
12023 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940,
12024 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
12025 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940U,
12026 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
12027 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940UW,
12028 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
12029 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_38C0800_REV1,
12030 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
12031 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_38C1600_REV1,
12032 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
12036 MODULE_DEVICE_TABLE(pci, advansys_pci_tbl);
12038 static void advansys_set_latency(struct pci_dev *pdev)
12040 if ((pdev->device == PCI_DEVICE_ID_ASP_1200A) ||
12041 (pdev->device == PCI_DEVICE_ID_ASP_ABP940)) {
12042 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0);
12045 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &latency);
12046 if (latency < 0x20)
12047 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x20);
12051 static int advansys_pci_probe(struct pci_dev *pdev,
12052 const struct pci_device_id *ent)
12055 struct Scsi_Host *shost;
12056 struct asc_board *board;
12058 err = pci_enable_device(pdev);
12061 err = pci_request_regions(pdev, DRV_NAME);
12063 goto disable_device;
12064 pci_set_master(pdev);
12065 advansys_set_latency(pdev);
12068 if (pci_resource_len(pdev, 0) == 0)
12069 goto release_region;
12071 ioport = pci_resource_start(pdev, 0);
12074 shost = scsi_host_alloc(&advansys_template, sizeof(*board));
12076 goto release_region;
12078 board = shost_priv(shost);
12079 board->irq = pdev->irq;
12080 board->dev = &pdev->dev;
12081 board->shost = shost;
12083 if (pdev->device == PCI_DEVICE_ID_ASP_ABP940UW ||
12084 pdev->device == PCI_DEVICE_ID_38C0800_REV1 ||
12085 pdev->device == PCI_DEVICE_ID_38C1600_REV1) {
12086 board->flags |= ASC_IS_WIDE_BOARD;
12089 err = advansys_board_found(shost, ioport, ASC_IS_PCI);
12093 pci_set_drvdata(pdev, shost);
12097 scsi_host_put(shost);
12099 pci_release_regions(pdev);
12101 pci_disable_device(pdev);
12106 static void advansys_pci_remove(struct pci_dev *pdev)
12108 advansys_release(pci_get_drvdata(pdev));
12109 pci_release_regions(pdev);
12110 pci_disable_device(pdev);
12113 static struct pci_driver advansys_pci_driver = {
12115 .id_table = advansys_pci_tbl,
12116 .probe = advansys_pci_probe,
12117 .remove = advansys_pci_remove,
12120 static int __init advansys_init(void)
12124 error = isa_register_driver(&advansys_isa_driver,
12125 ASC_IOADR_TABLE_MAX_IX);
12129 error = isa_register_driver(&advansys_vlb_driver,
12130 ASC_IOADR_TABLE_MAX_IX);
12132 goto unregister_isa;
12134 error = eisa_driver_register(&advansys_eisa_driver);
12136 goto unregister_vlb;
12138 error = pci_register_driver(&advansys_pci_driver);
12140 goto unregister_eisa;
12145 eisa_driver_unregister(&advansys_eisa_driver);
12147 isa_unregister_driver(&advansys_vlb_driver);
12149 isa_unregister_driver(&advansys_isa_driver);
12154 static void __exit advansys_exit(void)
12156 pci_unregister_driver(&advansys_pci_driver);
12157 eisa_driver_unregister(&advansys_eisa_driver);
12158 isa_unregister_driver(&advansys_vlb_driver);
12159 isa_unregister_driver(&advansys_isa_driver);
12162 module_init(advansys_init);
12163 module_exit(advansys_exit);
12165 MODULE_LICENSE("GPL");
12166 MODULE_FIRMWARE("advansys/mcode.bin");
12167 MODULE_FIRMWARE("advansys/3550.bin");
12168 MODULE_FIRMWARE("advansys/38C0800.bin");
12169 MODULE_FIRMWARE("advansys/38C1600.bin");