1 #define DRV_NAME "advansys"
2 #define ASC_VERSION "3.4" /* AdvanSys Driver Version */
5 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
7 * Copyright (c) 1995-2000 Advanced System Products, Inc.
8 * Copyright (c) 2000-2001 ConnectCom Solutions, Inc.
9 * Copyright (c) 2007 Matthew Wilcox <matthew@wil.cx>
10 * All Rights Reserved.
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
19 * As of March 8, 2000 Advanced System Products, Inc. (AdvanSys)
20 * changed its name to ConnectCom Solutions, Inc.
21 * On June 18, 2001 Initio Corp. acquired ConnectCom's SCSI assets
24 #include <linux/module.h>
25 #include <linux/string.h>
26 #include <linux/kernel.h>
27 #include <linux/types.h>
28 #include <linux/ioport.h>
29 #include <linux/interrupt.h>
30 #include <linux/delay.h>
31 #include <linux/slab.h>
33 #include <linux/proc_fs.h>
34 #include <linux/init.h>
35 #include <linux/blkdev.h>
36 #include <linux/isa.h>
37 #include <linux/eisa.h>
38 #include <linux/pci.h>
39 #include <linux/spinlock.h>
40 #include <linux/dma-mapping.h>
43 #include <asm/system.h>
46 #include <scsi/scsi_cmnd.h>
47 #include <scsi/scsi_device.h>
48 #include <scsi/scsi_tcq.h>
49 #include <scsi/scsi.h>
50 #include <scsi/scsi_host.h>
54 * 1. Although all of the necessary command mapping places have the
55 * appropriate dma_map.. APIs, the driver still processes its internal
56 * queue using bus_to_virt() and virt_to_bus() which are illegal under
57 * the API. The entire queue processing structure will need to be
58 * altered to fix this.
59 * 2. Need to add memory mapping workaround. Test the memory mapping.
60 * If it doesn't work revert to I/O port access. Can a test be done
62 * 3. Handle an interrupt not working. Keep an interrupt counter in
63 * the interrupt handler. In the timeout function if the interrupt
64 * has not occurred then print a message and run in polled mode.
65 * 4. Need to add support for target mode commands, cf. CAM XPT.
66 * 5. check DMA mapping functions for failure
67 * 6. Use scsi_transport_spi
68 * 7. advansys_info is not safe against multiple simultaneous callers
69 * 8. Add module_param to override ISA/VLB ioport array
71 #warning this driver is still not properly converted to the DMA API
73 /* Enable driver /proc statistics. */
74 #define ADVANSYS_STATS
76 /* Enable driver tracing. */
82 * Any instance where a 32-bit long or pointer type is assumed
83 * for precision or HW defined structures, the following define
84 * types must be used. In Linux the char, short, and int types
85 * are all consistent at 8, 16, and 32 bits respectively. Pointers
86 * and long types are 64 bits on Alpha and UltraSPARC.
88 #define ASC_PADDR __u32 /* Physical/Bus address data type. */
89 #define ASC_VADDR __u32 /* Virtual address data type. */
90 #define ASC_DCNT __u32 /* Unsigned Data count type. */
91 #define ASC_SDCNT __s32 /* Signed Data count type. */
94 * These macros are used to convert a virtual address to a
95 * 32-bit value. This currently can be used on Linux Alpha
96 * which uses 64-bit virtual address but a 32-bit bus address.
97 * This is likely to break in the future, but doing this now
98 * will give us time to change the HW and FW to handle 64-bit
101 #define ASC_VADDR_TO_U32 virt_to_bus
102 #define ASC_U32_TO_VADDR bus_to_virt
104 typedef unsigned char uchar;
114 #define UW_ERR (uint)(0xFFFF)
115 #define isodd_word(val) ((((uint)val) & (uint)0x0001) != 0)
117 #define PCI_VENDOR_ID_ASP 0x10cd
118 #define PCI_DEVICE_ID_ASP_1200A 0x1100
119 #define PCI_DEVICE_ID_ASP_ABP940 0x1200
120 #define PCI_DEVICE_ID_ASP_ABP940U 0x1300
121 #define PCI_DEVICE_ID_ASP_ABP940UW 0x2300
122 #define PCI_DEVICE_ID_38C0800_REV1 0x2500
123 #define PCI_DEVICE_ID_38C1600_REV1 0x2700
126 * Enable CC_VERY_LONG_SG_LIST to support up to 64K element SG lists.
127 * The SRB structure will have to be changed and the ASC_SRB2SCSIQ()
128 * macro re-defined to be able to obtain a ASC_SCSI_Q pointer from the
131 #define CC_VERY_LONG_SG_LIST 0
132 #define ASC_SRB2SCSIQ(srb_ptr) (srb_ptr)
134 #define PortAddr unsigned short /* port address size */
135 #define inp(port) inb(port)
136 #define outp(port, byte) outb((byte), (port))
138 #define inpw(port) inw(port)
139 #define outpw(port, word) outw((word), (port))
141 #define ASC_MAX_SG_QUEUE 7
142 #define ASC_MAX_SG_LIST 255
144 #define ASC_CS_TYPE unsigned short
146 #define ASC_IS_ISA (0x0001)
147 #define ASC_IS_ISAPNP (0x0081)
148 #define ASC_IS_EISA (0x0002)
149 #define ASC_IS_PCI (0x0004)
150 #define ASC_IS_PCI_ULTRA (0x0104)
151 #define ASC_IS_PCMCIA (0x0008)
152 #define ASC_IS_MCA (0x0020)
153 #define ASC_IS_VL (0x0040)
154 #define ASC_IS_WIDESCSI_16 (0x0100)
155 #define ASC_IS_WIDESCSI_32 (0x0200)
156 #define ASC_IS_BIG_ENDIAN (0x8000)
158 #define ASC_CHIP_MIN_VER_VL (0x01)
159 #define ASC_CHIP_MAX_VER_VL (0x07)
160 #define ASC_CHIP_MIN_VER_PCI (0x09)
161 #define ASC_CHIP_MAX_VER_PCI (0x0F)
162 #define ASC_CHIP_VER_PCI_BIT (0x08)
163 #define ASC_CHIP_MIN_VER_ISA (0x11)
164 #define ASC_CHIP_MIN_VER_ISA_PNP (0x21)
165 #define ASC_CHIP_MAX_VER_ISA (0x27)
166 #define ASC_CHIP_VER_ISA_BIT (0x30)
167 #define ASC_CHIP_VER_ISAPNP_BIT (0x20)
168 #define ASC_CHIP_VER_ASYN_BUG (0x21)
169 #define ASC_CHIP_VER_PCI 0x08
170 #define ASC_CHIP_VER_PCI_ULTRA_3150 (ASC_CHIP_VER_PCI | 0x02)
171 #define ASC_CHIP_VER_PCI_ULTRA_3050 (ASC_CHIP_VER_PCI | 0x03)
172 #define ASC_CHIP_MIN_VER_EISA (0x41)
173 #define ASC_CHIP_MAX_VER_EISA (0x47)
174 #define ASC_CHIP_VER_EISA_BIT (0x40)
175 #define ASC_CHIP_LATEST_VER_EISA ((ASC_CHIP_MIN_VER_EISA - 1) + 3)
176 #define ASC_MAX_VL_DMA_COUNT (0x07FFFFFFL)
177 #define ASC_MAX_PCI_DMA_COUNT (0xFFFFFFFFL)
178 #define ASC_MAX_ISA_DMA_COUNT (0x00FFFFFFL)
180 #define ASC_SCSI_ID_BITS 3
181 #define ASC_SCSI_TIX_TYPE uchar
182 #define ASC_ALL_DEVICE_BIT_SET 0xFF
183 #define ASC_SCSI_BIT_ID_TYPE uchar
184 #define ASC_MAX_TID 7
185 #define ASC_MAX_LUN 7
186 #define ASC_SCSI_WIDTH_BIT_SET 0xFF
187 #define ASC_MAX_SENSE_LEN 32
188 #define ASC_MIN_SENSE_LEN 14
189 #define ASC_SCSI_RESET_HOLD_TIME_US 60
192 * Narrow boards only support 12-byte commands, while wide boards
193 * extend to 16-byte commands.
195 #define ASC_MAX_CDB_LEN 12
196 #define ADV_MAX_CDB_LEN 16
198 #define MS_SDTR_LEN 0x03
199 #define MS_WDTR_LEN 0x02
201 #define ASC_SG_LIST_PER_Q 7
203 #define QS_READY 0x01
204 #define QS_DISC1 0x02
205 #define QS_DISC2 0x04
207 #define QS_ABORTED 0x40
209 #define QC_NO_CALLBACK 0x01
210 #define QC_SG_SWAP_QUEUE 0x02
211 #define QC_SG_HEAD 0x04
212 #define QC_DATA_IN 0x08
213 #define QC_DATA_OUT 0x10
214 #define QC_URGENT 0x20
215 #define QC_MSG_OUT 0x40
216 #define QC_REQ_SENSE 0x80
217 #define QCSG_SG_XFER_LIST 0x02
218 #define QCSG_SG_XFER_MORE 0x04
219 #define QCSG_SG_XFER_END 0x08
220 #define QD_IN_PROGRESS 0x00
221 #define QD_NO_ERROR 0x01
222 #define QD_ABORTED_BY_HOST 0x02
223 #define QD_WITH_ERROR 0x04
224 #define QD_INVALID_REQUEST 0x80
225 #define QD_INVALID_HOST_NUM 0x81
226 #define QD_INVALID_DEVICE 0x82
227 #define QD_ERR_INTERNAL 0xFF
228 #define QHSTA_NO_ERROR 0x00
229 #define QHSTA_M_SEL_TIMEOUT 0x11
230 #define QHSTA_M_DATA_OVER_RUN 0x12
231 #define QHSTA_M_DATA_UNDER_RUN 0x12
232 #define QHSTA_M_UNEXPECTED_BUS_FREE 0x13
233 #define QHSTA_M_BAD_BUS_PHASE_SEQ 0x14
234 #define QHSTA_D_QDONE_SG_LIST_CORRUPTED 0x21
235 #define QHSTA_D_ASC_DVC_ERROR_CODE_SET 0x22
236 #define QHSTA_D_HOST_ABORT_FAILED 0x23
237 #define QHSTA_D_EXE_SCSI_Q_FAILED 0x24
238 #define QHSTA_D_EXE_SCSI_Q_BUSY_TIMEOUT 0x25
239 #define QHSTA_D_ASPI_NO_BUF_POOL 0x26
240 #define QHSTA_M_WTM_TIMEOUT 0x41
241 #define QHSTA_M_BAD_CMPL_STATUS_IN 0x42
242 #define QHSTA_M_NO_AUTO_REQ_SENSE 0x43
243 #define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
244 #define QHSTA_M_TARGET_STATUS_BUSY 0x45
245 #define QHSTA_M_BAD_TAG_CODE 0x46
246 #define QHSTA_M_BAD_QUEUE_FULL_OR_BUSY 0x47
247 #define QHSTA_M_HUNG_REQ_SCSI_BUS_RESET 0x48
248 #define QHSTA_D_LRAM_CMP_ERROR 0x81
249 #define QHSTA_M_MICRO_CODE_ERROR_HALT 0xA1
250 #define ASC_FLAG_SCSIQ_REQ 0x01
251 #define ASC_FLAG_BIOS_SCSIQ_REQ 0x02
252 #define ASC_FLAG_BIOS_ASYNC_IO 0x04
253 #define ASC_FLAG_SRB_LINEAR_ADDR 0x08
254 #define ASC_FLAG_WIN16 0x10
255 #define ASC_FLAG_WIN32 0x20
256 #define ASC_FLAG_ISA_OVER_16MB 0x40
257 #define ASC_FLAG_DOS_VM_CALLBACK 0x80
258 #define ASC_TAG_FLAG_EXTRA_BYTES 0x10
259 #define ASC_TAG_FLAG_DISABLE_DISCONNECT 0x04
260 #define ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX 0x08
261 #define ASC_TAG_FLAG_DISABLE_CHK_COND_INT_HOST 0x40
262 #define ASC_SCSIQ_CPY_BEG 4
263 #define ASC_SCSIQ_SGHD_CPY_BEG 2
264 #define ASC_SCSIQ_B_FWD 0
265 #define ASC_SCSIQ_B_BWD 1
266 #define ASC_SCSIQ_B_STATUS 2
267 #define ASC_SCSIQ_B_QNO 3
268 #define ASC_SCSIQ_B_CNTL 4
269 #define ASC_SCSIQ_B_SG_QUEUE_CNT 5
270 #define ASC_SCSIQ_D_DATA_ADDR 8
271 #define ASC_SCSIQ_D_DATA_CNT 12
272 #define ASC_SCSIQ_B_SENSE_LEN 20
273 #define ASC_SCSIQ_DONE_INFO_BEG 22
274 #define ASC_SCSIQ_D_SRBPTR 22
275 #define ASC_SCSIQ_B_TARGET_IX 26
276 #define ASC_SCSIQ_B_CDB_LEN 28
277 #define ASC_SCSIQ_B_TAG_CODE 29
278 #define ASC_SCSIQ_W_VM_ID 30
279 #define ASC_SCSIQ_DONE_STATUS 32
280 #define ASC_SCSIQ_HOST_STATUS 33
281 #define ASC_SCSIQ_SCSI_STATUS 34
282 #define ASC_SCSIQ_CDB_BEG 36
283 #define ASC_SCSIQ_DW_REMAIN_XFER_ADDR 56
284 #define ASC_SCSIQ_DW_REMAIN_XFER_CNT 60
285 #define ASC_SCSIQ_B_FIRST_SG_WK_QP 48
286 #define ASC_SCSIQ_B_SG_WK_QP 49
287 #define ASC_SCSIQ_B_SG_WK_IX 50
288 #define ASC_SCSIQ_W_ALT_DC1 52
289 #define ASC_SCSIQ_B_LIST_CNT 6
290 #define ASC_SCSIQ_B_CUR_LIST_CNT 7
291 #define ASC_SGQ_B_SG_CNTL 4
292 #define ASC_SGQ_B_SG_HEAD_QP 5
293 #define ASC_SGQ_B_SG_LIST_CNT 6
294 #define ASC_SGQ_B_SG_CUR_LIST_CNT 7
295 #define ASC_SGQ_LIST_BEG 8
296 #define ASC_DEF_SCSI1_QNG 4
297 #define ASC_MAX_SCSI1_QNG 4
298 #define ASC_DEF_SCSI2_QNG 16
299 #define ASC_MAX_SCSI2_QNG 32
300 #define ASC_TAG_CODE_MASK 0x23
301 #define ASC_STOP_REQ_RISC_STOP 0x01
302 #define ASC_STOP_ACK_RISC_STOP 0x03
303 #define ASC_STOP_CLEAN_UP_BUSY_Q 0x10
304 #define ASC_STOP_CLEAN_UP_DISC_Q 0x20
305 #define ASC_STOP_HOST_REQ_RISC_HALT 0x40
306 #define ASC_TIDLUN_TO_IX(tid, lun) (ASC_SCSI_TIX_TYPE)((tid) + ((lun)<<ASC_SCSI_ID_BITS))
307 #define ASC_TID_TO_TARGET_ID(tid) (ASC_SCSI_BIT_ID_TYPE)(0x01 << (tid))
308 #define ASC_TIX_TO_TARGET_ID(tix) (0x01 << ((tix) & ASC_MAX_TID))
309 #define ASC_TIX_TO_TID(tix) ((tix) & ASC_MAX_TID)
310 #define ASC_TID_TO_TIX(tid) ((tid) & ASC_MAX_TID)
311 #define ASC_TIX_TO_LUN(tix) (((tix) >> ASC_SCSI_ID_BITS) & ASC_MAX_LUN)
312 #define ASC_QNO_TO_QADDR(q_no) ((ASC_QADR_BEG)+((int)(q_no) << 6))
314 typedef struct asc_scsiq_1 {
323 ASC_PADDR sense_addr;
328 typedef struct asc_scsiq_2 {
337 typedef struct asc_scsiq_3 {
344 typedef struct asc_scsiq_4 {
345 uchar cdb[ASC_MAX_CDB_LEN];
346 uchar y_first_sg_list_qp;
347 uchar y_working_sg_qp;
348 uchar y_working_sg_ix;
351 ushort x_reconnect_rtn;
352 ASC_PADDR x_saved_data_addr;
353 ASC_DCNT x_saved_data_cnt;
356 typedef struct asc_q_done_info {
365 ASC_DCNT remain_bytes;
368 typedef struct asc_sg_list {
373 typedef struct asc_sg_head {
376 ushort entry_to_copy;
378 ASC_SG_LIST sg_list[0];
381 typedef struct asc_scsi_q {
385 ASC_SG_HEAD *sg_head;
386 ushort remain_sg_entry_cnt;
387 ushort next_sg_index;
390 typedef struct asc_scsi_req_q {
394 ASC_SG_HEAD *sg_head;
397 uchar cdb[ASC_MAX_CDB_LEN];
398 uchar sense[ASC_MIN_SENSE_LEN];
401 typedef struct asc_scsi_bios_req_q {
405 ASC_SG_HEAD *sg_head;
408 uchar cdb[ASC_MAX_CDB_LEN];
409 uchar sense[ASC_MIN_SENSE_LEN];
410 } ASC_SCSI_BIOS_REQ_Q;
412 typedef struct asc_risc_q {
421 typedef struct asc_sg_list_q {
427 uchar sg_cur_list_cnt;
430 typedef struct asc_risc_sg_list_q {
434 ASC_SG_LIST sg_list[7];
435 } ASC_RISC_SG_LIST_Q;
437 #define ASCQ_ERR_Q_STATUS 0x0D
438 #define ASCQ_ERR_CUR_QNG 0x17
439 #define ASCQ_ERR_SG_Q_LINKS 0x18
440 #define ASCQ_ERR_ISR_RE_ENTRY 0x1A
441 #define ASCQ_ERR_CRITICAL_RE_ENTRY 0x1B
442 #define ASCQ_ERR_ISR_ON_CRITICAL 0x1C
445 * Warning code values are set in ASC_DVC_VAR 'warn_code'.
447 #define ASC_WARN_NO_ERROR 0x0000
448 #define ASC_WARN_IO_PORT_ROTATE 0x0001
449 #define ASC_WARN_EEPROM_CHKSUM 0x0002
450 #define ASC_WARN_IRQ_MODIFIED 0x0004
451 #define ASC_WARN_AUTO_CONFIG 0x0008
452 #define ASC_WARN_CMD_QNG_CONFLICT 0x0010
453 #define ASC_WARN_EEPROM_RECOVER 0x0020
454 #define ASC_WARN_CFG_MSW_RECOVER 0x0040
457 * Error code values are set in {ASC/ADV}_DVC_VAR 'err_code'.
459 #define ASC_IERR_NO_CARRIER 0x0001 /* No more carrier memory */
460 #define ASC_IERR_MCODE_CHKSUM 0x0002 /* micro code check sum error */
461 #define ASC_IERR_SET_PC_ADDR 0x0004
462 #define ASC_IERR_START_STOP_CHIP 0x0008 /* start/stop chip failed */
463 #define ASC_IERR_ILLEGAL_CONNECTION 0x0010 /* Illegal cable connection */
464 #define ASC_IERR_SINGLE_END_DEVICE 0x0020 /* SE device on DIFF bus */
465 #define ASC_IERR_REVERSED_CABLE 0x0040 /* Narrow flat cable reversed */
466 #define ASC_IERR_SET_SCSI_ID 0x0080 /* set SCSI ID failed */
467 #define ASC_IERR_HVD_DEVICE 0x0100 /* HVD device on LVD port */
468 #define ASC_IERR_BAD_SIGNATURE 0x0200 /* signature not found */
469 #define ASC_IERR_NO_BUS_TYPE 0x0400
470 #define ASC_IERR_BIST_PRE_TEST 0x0800 /* BIST pre-test error */
471 #define ASC_IERR_BIST_RAM_TEST 0x1000 /* BIST RAM test error */
472 #define ASC_IERR_BAD_CHIPTYPE 0x2000 /* Invalid chip_type setting */
474 #define ASC_DEF_MAX_TOTAL_QNG (0xF0)
475 #define ASC_MIN_TAG_Q_PER_DVC (0x04)
476 #define ASC_MIN_FREE_Q (0x02)
477 #define ASC_MIN_TOTAL_QNG ((ASC_MAX_SG_QUEUE)+(ASC_MIN_FREE_Q))
478 #define ASC_MAX_TOTAL_QNG 240
479 #define ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG 16
480 #define ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG 8
481 #define ASC_MAX_PCI_INRAM_TOTAL_QNG 20
482 #define ASC_MAX_INRAM_TAG_QNG 16
483 #define ASC_IOADR_GAP 0x10
484 #define ASC_MAX_SYN_XFER_NO 16
485 #define ASC_SYN_MAX_OFFSET 0x0F
486 #define ASC_DEF_SDTR_OFFSET 0x0F
487 #define ASC_SDTR_ULTRA_PCI_10MB_INDEX 0x02
488 #define SYN_XFER_NS_0 25
489 #define SYN_XFER_NS_1 30
490 #define SYN_XFER_NS_2 35
491 #define SYN_XFER_NS_3 40
492 #define SYN_XFER_NS_4 50
493 #define SYN_XFER_NS_5 60
494 #define SYN_XFER_NS_6 70
495 #define SYN_XFER_NS_7 85
496 #define SYN_ULTRA_XFER_NS_0 12
497 #define SYN_ULTRA_XFER_NS_1 19
498 #define SYN_ULTRA_XFER_NS_2 25
499 #define SYN_ULTRA_XFER_NS_3 32
500 #define SYN_ULTRA_XFER_NS_4 38
501 #define SYN_ULTRA_XFER_NS_5 44
502 #define SYN_ULTRA_XFER_NS_6 50
503 #define SYN_ULTRA_XFER_NS_7 57
504 #define SYN_ULTRA_XFER_NS_8 63
505 #define SYN_ULTRA_XFER_NS_9 69
506 #define SYN_ULTRA_XFER_NS_10 75
507 #define SYN_ULTRA_XFER_NS_11 82
508 #define SYN_ULTRA_XFER_NS_12 88
509 #define SYN_ULTRA_XFER_NS_13 94
510 #define SYN_ULTRA_XFER_NS_14 100
511 #define SYN_ULTRA_XFER_NS_15 107
513 typedef struct ext_msg {
519 uchar sdtr_xfer_period;
520 uchar sdtr_req_ack_offset;
535 #define xfer_period u_ext_msg.sdtr.sdtr_xfer_period
536 #define req_ack_offset u_ext_msg.sdtr.sdtr_req_ack_offset
537 #define wdtr_width u_ext_msg.wdtr.wdtr_width
538 #define mdp_b3 u_ext_msg.mdp_b3
539 #define mdp_b2 u_ext_msg.mdp_b2
540 #define mdp_b1 u_ext_msg.mdp_b1
541 #define mdp_b0 u_ext_msg.mdp_b0
543 typedef struct asc_dvc_cfg {
544 ASC_SCSI_BIT_ID_TYPE can_tagged_qng;
545 ASC_SCSI_BIT_ID_TYPE cmd_qng_enabled;
546 ASC_SCSI_BIT_ID_TYPE disc_enable;
547 ASC_SCSI_BIT_ID_TYPE sdtr_enable;
550 uchar isa_dma_channel;
553 ushort mcode_version;
554 uchar max_tag_qng[ASC_MAX_TID + 1];
556 uchar sdtr_period_offset[ASC_MAX_TID + 1];
557 uchar adapter_info[6];
560 #define ASC_DEF_DVC_CNTL 0xFFFF
561 #define ASC_DEF_CHIP_SCSI_ID 7
562 #define ASC_DEF_ISA_DMA_SPEED 4
563 #define ASC_INIT_STATE_BEG_GET_CFG 0x0001
564 #define ASC_INIT_STATE_END_GET_CFG 0x0002
565 #define ASC_INIT_STATE_BEG_SET_CFG 0x0004
566 #define ASC_INIT_STATE_END_SET_CFG 0x0008
567 #define ASC_INIT_STATE_BEG_LOAD_MC 0x0010
568 #define ASC_INIT_STATE_END_LOAD_MC 0x0020
569 #define ASC_INIT_STATE_BEG_INQUIRY 0x0040
570 #define ASC_INIT_STATE_END_INQUIRY 0x0080
571 #define ASC_INIT_RESET_SCSI_DONE 0x0100
572 #define ASC_INIT_STATE_WITHOUT_EEP 0x8000
573 #define ASC_BUG_FIX_IF_NOT_DWB 0x0001
574 #define ASC_BUG_FIX_ASYN_USE_SYN 0x0002
575 #define ASYN_SDTR_DATA_FIX_PCI_REV_AB 0x41
576 #define ASC_MIN_TAGGED_CMD 7
577 #define ASC_MAX_SCSI_RESET_WAIT 30
579 struct asc_dvc_var; /* Forward Declaration. */
581 typedef struct asc_dvc_var {
587 ASC_SCSI_BIT_ID_TYPE init_sdtr;
588 ASC_SCSI_BIT_ID_TYPE sdtr_done;
589 ASC_SCSI_BIT_ID_TYPE use_tagged_qng;
590 ASC_SCSI_BIT_ID_TYPE unit_not_ready;
591 ASC_SCSI_BIT_ID_TYPE queue_full_or_busy;
592 ASC_SCSI_BIT_ID_TYPE start_motor;
593 uchar scsi_reset_wait;
598 uchar in_critical_cnt;
599 uchar last_q_shortage;
601 uchar cur_dvc_qng[ASC_MAX_TID + 1];
602 uchar max_dvc_qng[ASC_MAX_TID + 1];
603 ASC_SCSI_Q *scsiq_busy_head[ASC_MAX_TID + 1];
604 ASC_SCSI_Q *scsiq_busy_tail[ASC_MAX_TID + 1];
605 uchar sdtr_period_tbl[ASC_MAX_SYN_XFER_NO];
607 ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer_always;
610 uchar dos_int13_table[ASC_MAX_TID + 1];
611 ASC_DCNT max_dma_count;
612 ASC_SCSI_BIT_ID_TYPE no_scam;
613 ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer;
614 uchar max_sdtr_index;
615 uchar host_init_sdtr_index;
616 struct asc_board *drv_ptr;
620 typedef struct asc_dvc_inq_info {
621 uchar type[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
624 typedef struct asc_cap_info {
629 typedef struct asc_cap_info_array {
630 ASC_CAP_INFO cap_info[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
631 } ASC_CAP_INFO_ARRAY;
633 #define ASC_MCNTL_NO_SEL_TIMEOUT (ushort)0x0001
634 #define ASC_MCNTL_NULL_TARGET (ushort)0x0002
635 #define ASC_CNTL_INITIATOR (ushort)0x0001
636 #define ASC_CNTL_BIOS_GT_1GB (ushort)0x0002
637 #define ASC_CNTL_BIOS_GT_2_DISK (ushort)0x0004
638 #define ASC_CNTL_BIOS_REMOVABLE (ushort)0x0008
639 #define ASC_CNTL_NO_SCAM (ushort)0x0010
640 #define ASC_CNTL_INT_MULTI_Q (ushort)0x0080
641 #define ASC_CNTL_NO_LUN_SUPPORT (ushort)0x0040
642 #define ASC_CNTL_NO_VERIFY_COPY (ushort)0x0100
643 #define ASC_CNTL_RESET_SCSI (ushort)0x0200
644 #define ASC_CNTL_INIT_INQUIRY (ushort)0x0400
645 #define ASC_CNTL_INIT_VERBOSE (ushort)0x0800
646 #define ASC_CNTL_SCSI_PARITY (ushort)0x1000
647 #define ASC_CNTL_BURST_MODE (ushort)0x2000
648 #define ASC_CNTL_SDTR_ENABLE_ULTRA (ushort)0x4000
649 #define ASC_EEP_DVC_CFG_BEG_VL 2
650 #define ASC_EEP_MAX_DVC_ADDR_VL 15
651 #define ASC_EEP_DVC_CFG_BEG 32
652 #define ASC_EEP_MAX_DVC_ADDR 45
653 #define ASC_EEP_MAX_RETRY 20
656 * These macros keep the chip SCSI id and ISA DMA speed
657 * bitfields in board order. C bitfields aren't portable
658 * between big and little-endian platforms so they are
662 #define ASC_EEP_GET_CHIP_ID(cfg) ((cfg)->id_speed & 0x0f)
663 #define ASC_EEP_GET_DMA_SPD(cfg) (((cfg)->id_speed & 0xf0) >> 4)
664 #define ASC_EEP_SET_CHIP_ID(cfg, sid) \
665 ((cfg)->id_speed = ((cfg)->id_speed & 0xf0) | ((sid) & ASC_MAX_TID))
666 #define ASC_EEP_SET_DMA_SPD(cfg, spd) \
667 ((cfg)->id_speed = ((cfg)->id_speed & 0x0f) | ((spd) & 0x0f) << 4)
669 typedef struct asceep_config {
681 uchar id_speed; /* low order 4 bits is chip scsi id */
682 /* high order 4 bits is isa dma speed */
683 uchar dos_int13_table[ASC_MAX_TID + 1];
684 uchar adapter_info[6];
689 #define ASC_EEP_CMD_READ 0x80
690 #define ASC_EEP_CMD_WRITE 0x40
691 #define ASC_EEP_CMD_WRITE_ABLE 0x30
692 #define ASC_EEP_CMD_WRITE_DISABLE 0x00
693 #define ASC_OVERRUN_BSIZE 0x00000048UL
694 #define ASCV_MSGOUT_BEG 0x0000
695 #define ASCV_MSGOUT_SDTR_PERIOD (ASCV_MSGOUT_BEG+3)
696 #define ASCV_MSGOUT_SDTR_OFFSET (ASCV_MSGOUT_BEG+4)
697 #define ASCV_BREAK_SAVED_CODE (ushort)0x0006
698 #define ASCV_MSGIN_BEG (ASCV_MSGOUT_BEG+8)
699 #define ASCV_MSGIN_SDTR_PERIOD (ASCV_MSGIN_BEG+3)
700 #define ASCV_MSGIN_SDTR_OFFSET (ASCV_MSGIN_BEG+4)
701 #define ASCV_SDTR_DATA_BEG (ASCV_MSGIN_BEG+8)
702 #define ASCV_SDTR_DONE_BEG (ASCV_SDTR_DATA_BEG+8)
703 #define ASCV_MAX_DVC_QNG_BEG (ushort)0x0020
704 #define ASCV_BREAK_ADDR (ushort)0x0028
705 #define ASCV_BREAK_NOTIFY_COUNT (ushort)0x002A
706 #define ASCV_BREAK_CONTROL (ushort)0x002C
707 #define ASCV_BREAK_HIT_COUNT (ushort)0x002E
709 #define ASCV_ASCDVC_ERR_CODE_W (ushort)0x0030
710 #define ASCV_MCODE_CHKSUM_W (ushort)0x0032
711 #define ASCV_MCODE_SIZE_W (ushort)0x0034
712 #define ASCV_STOP_CODE_B (ushort)0x0036
713 #define ASCV_DVC_ERR_CODE_B (ushort)0x0037
714 #define ASCV_OVERRUN_PADDR_D (ushort)0x0038
715 #define ASCV_OVERRUN_BSIZE_D (ushort)0x003C
716 #define ASCV_HALTCODE_W (ushort)0x0040
717 #define ASCV_CHKSUM_W (ushort)0x0042
718 #define ASCV_MC_DATE_W (ushort)0x0044
719 #define ASCV_MC_VER_W (ushort)0x0046
720 #define ASCV_NEXTRDY_B (ushort)0x0048
721 #define ASCV_DONENEXT_B (ushort)0x0049
722 #define ASCV_USE_TAGGED_QNG_B (ushort)0x004A
723 #define ASCV_SCSIBUSY_B (ushort)0x004B
724 #define ASCV_Q_DONE_IN_PROGRESS_B (ushort)0x004C
725 #define ASCV_CURCDB_B (ushort)0x004D
726 #define ASCV_RCLUN_B (ushort)0x004E
727 #define ASCV_BUSY_QHEAD_B (ushort)0x004F
728 #define ASCV_DISC1_QHEAD_B (ushort)0x0050
729 #define ASCV_DISC_ENABLE_B (ushort)0x0052
730 #define ASCV_CAN_TAGGED_QNG_B (ushort)0x0053
731 #define ASCV_HOSTSCSI_ID_B (ushort)0x0055
732 #define ASCV_MCODE_CNTL_B (ushort)0x0056
733 #define ASCV_NULL_TARGET_B (ushort)0x0057
734 #define ASCV_FREE_Q_HEAD_W (ushort)0x0058
735 #define ASCV_DONE_Q_TAIL_W (ushort)0x005A
736 #define ASCV_FREE_Q_HEAD_B (ushort)(ASCV_FREE_Q_HEAD_W+1)
737 #define ASCV_DONE_Q_TAIL_B (ushort)(ASCV_DONE_Q_TAIL_W+1)
738 #define ASCV_HOST_FLAG_B (ushort)0x005D
739 #define ASCV_TOTAL_READY_Q_B (ushort)0x0064
740 #define ASCV_VER_SERIAL_B (ushort)0x0065
741 #define ASCV_HALTCODE_SAVED_W (ushort)0x0066
742 #define ASCV_WTM_FLAG_B (ushort)0x0068
743 #define ASCV_RISC_FLAG_B (ushort)0x006A
744 #define ASCV_REQ_SG_LIST_QP (ushort)0x006B
745 #define ASC_HOST_FLAG_IN_ISR 0x01
746 #define ASC_HOST_FLAG_ACK_INT 0x02
747 #define ASC_RISC_FLAG_GEN_INT 0x01
748 #define ASC_RISC_FLAG_REQ_SG_LIST 0x02
749 #define IOP_CTRL (0x0F)
750 #define IOP_STATUS (0x0E)
751 #define IOP_INT_ACK IOP_STATUS
752 #define IOP_REG_IFC (0x0D)
753 #define IOP_SYN_OFFSET (0x0B)
754 #define IOP_EXTRA_CONTROL (0x0D)
755 #define IOP_REG_PC (0x0C)
756 #define IOP_RAM_ADDR (0x0A)
757 #define IOP_RAM_DATA (0x08)
758 #define IOP_EEP_DATA (0x06)
759 #define IOP_EEP_CMD (0x07)
760 #define IOP_VERSION (0x03)
761 #define IOP_CONFIG_HIGH (0x04)
762 #define IOP_CONFIG_LOW (0x02)
763 #define IOP_SIG_BYTE (0x01)
764 #define IOP_SIG_WORD (0x00)
765 #define IOP_REG_DC1 (0x0E)
766 #define IOP_REG_DC0 (0x0C)
767 #define IOP_REG_SB (0x0B)
768 #define IOP_REG_DA1 (0x0A)
769 #define IOP_REG_DA0 (0x08)
770 #define IOP_REG_SC (0x09)
771 #define IOP_DMA_SPEED (0x07)
772 #define IOP_REG_FLAG (0x07)
773 #define IOP_FIFO_H (0x06)
774 #define IOP_FIFO_L (0x04)
775 #define IOP_REG_ID (0x05)
776 #define IOP_REG_QP (0x03)
777 #define IOP_REG_IH (0x02)
778 #define IOP_REG_IX (0x01)
779 #define IOP_REG_AX (0x00)
780 #define IFC_REG_LOCK (0x00)
781 #define IFC_REG_UNLOCK (0x09)
782 #define IFC_WR_EN_FILTER (0x10)
783 #define IFC_RD_NO_EEPROM (0x10)
784 #define IFC_SLEW_RATE (0x20)
785 #define IFC_ACT_NEG (0x40)
786 #define IFC_INP_FILTER (0x80)
787 #define IFC_INIT_DEFAULT (IFC_ACT_NEG | IFC_REG_UNLOCK)
788 #define SC_SEL (uchar)(0x80)
789 #define SC_BSY (uchar)(0x40)
790 #define SC_ACK (uchar)(0x20)
791 #define SC_REQ (uchar)(0x10)
792 #define SC_ATN (uchar)(0x08)
793 #define SC_IO (uchar)(0x04)
794 #define SC_CD (uchar)(0x02)
795 #define SC_MSG (uchar)(0x01)
796 #define SEC_SCSI_CTL (uchar)(0x80)
797 #define SEC_ACTIVE_NEGATE (uchar)(0x40)
798 #define SEC_SLEW_RATE (uchar)(0x20)
799 #define SEC_ENABLE_FILTER (uchar)(0x10)
800 #define ASC_HALT_EXTMSG_IN (ushort)0x8000
801 #define ASC_HALT_CHK_CONDITION (ushort)0x8100
802 #define ASC_HALT_SS_QUEUE_FULL (ushort)0x8200
803 #define ASC_HALT_DISABLE_ASYN_USE_SYN_FIX (ushort)0x8300
804 #define ASC_HALT_ENABLE_ASYN_USE_SYN_FIX (ushort)0x8400
805 #define ASC_HALT_SDTR_REJECTED (ushort)0x4000
806 #define ASC_HALT_HOST_COPY_SG_LIST_TO_RISC ( ushort )0x2000
807 #define ASC_MAX_QNO 0xF8
808 #define ASC_DATA_SEC_BEG (ushort)0x0080
809 #define ASC_DATA_SEC_END (ushort)0x0080
810 #define ASC_CODE_SEC_BEG (ushort)0x0080
811 #define ASC_CODE_SEC_END (ushort)0x0080
812 #define ASC_QADR_BEG (0x4000)
813 #define ASC_QADR_USED (ushort)(ASC_MAX_QNO * 64)
814 #define ASC_QADR_END (ushort)0x7FFF
815 #define ASC_QLAST_ADR (ushort)0x7FC0
816 #define ASC_QBLK_SIZE 0x40
817 #define ASC_BIOS_DATA_QBEG 0xF8
818 #define ASC_MIN_ACTIVE_QNO 0x01
819 #define ASC_QLINK_END 0xFF
820 #define ASC_EEPROM_WORDS 0x10
821 #define ASC_MAX_MGS_LEN 0x10
822 #define ASC_BIOS_ADDR_DEF 0xDC00
823 #define ASC_BIOS_SIZE 0x3800
824 #define ASC_BIOS_RAM_OFF 0x3800
825 #define ASC_BIOS_RAM_SIZE 0x800
826 #define ASC_BIOS_MIN_ADDR 0xC000
827 #define ASC_BIOS_MAX_ADDR 0xEC00
828 #define ASC_BIOS_BANK_SIZE 0x0400
829 #define ASC_MCODE_START_ADDR 0x0080
830 #define ASC_CFG0_HOST_INT_ON 0x0020
831 #define ASC_CFG0_BIOS_ON 0x0040
832 #define ASC_CFG0_VERA_BURST_ON 0x0080
833 #define ASC_CFG0_SCSI_PARITY_ON 0x0800
834 #define ASC_CFG1_SCSI_TARGET_ON 0x0080
835 #define ASC_CFG1_LRAM_8BITS_ON 0x0800
836 #define ASC_CFG_MSW_CLR_MASK 0x3080
837 #define CSW_TEST1 (ASC_CS_TYPE)0x8000
838 #define CSW_AUTO_CONFIG (ASC_CS_TYPE)0x4000
839 #define CSW_RESERVED1 (ASC_CS_TYPE)0x2000
840 #define CSW_IRQ_WRITTEN (ASC_CS_TYPE)0x1000
841 #define CSW_33MHZ_SELECTED (ASC_CS_TYPE)0x0800
842 #define CSW_TEST2 (ASC_CS_TYPE)0x0400
843 #define CSW_TEST3 (ASC_CS_TYPE)0x0200
844 #define CSW_RESERVED2 (ASC_CS_TYPE)0x0100
845 #define CSW_DMA_DONE (ASC_CS_TYPE)0x0080
846 #define CSW_FIFO_RDY (ASC_CS_TYPE)0x0040
847 #define CSW_EEP_READ_DONE (ASC_CS_TYPE)0x0020
848 #define CSW_HALTED (ASC_CS_TYPE)0x0010
849 #define CSW_SCSI_RESET_ACTIVE (ASC_CS_TYPE)0x0008
850 #define CSW_PARITY_ERR (ASC_CS_TYPE)0x0004
851 #define CSW_SCSI_RESET_LATCH (ASC_CS_TYPE)0x0002
852 #define CSW_INT_PENDING (ASC_CS_TYPE)0x0001
853 #define CIW_CLR_SCSI_RESET_INT (ASC_CS_TYPE)0x1000
854 #define CIW_INT_ACK (ASC_CS_TYPE)0x0100
855 #define CIW_TEST1 (ASC_CS_TYPE)0x0200
856 #define CIW_TEST2 (ASC_CS_TYPE)0x0400
857 #define CIW_SEL_33MHZ (ASC_CS_TYPE)0x0800
858 #define CIW_IRQ_ACT (ASC_CS_TYPE)0x1000
859 #define CC_CHIP_RESET (uchar)0x80
860 #define CC_SCSI_RESET (uchar)0x40
861 #define CC_HALT (uchar)0x20
862 #define CC_SINGLE_STEP (uchar)0x10
863 #define CC_DMA_ABLE (uchar)0x08
864 #define CC_TEST (uchar)0x04
865 #define CC_BANK_ONE (uchar)0x02
866 #define CC_DIAG (uchar)0x01
867 #define ASC_1000_ID0W 0x04C1
868 #define ASC_1000_ID0W_FIX 0x00C1
869 #define ASC_1000_ID1B 0x25
870 #define ASC_EISA_REV_IOP_MASK (0x0C83)
871 #define ASC_EISA_CFG_IOP_MASK (0x0C86)
872 #define ASC_GET_EISA_SLOT(iop) (PortAddr)((iop) & 0xF000)
873 #define INS_HALTINT (ushort)0x6281
874 #define INS_HALT (ushort)0x6280
875 #define INS_SINT (ushort)0x6200
876 #define INS_RFLAG_WTM (ushort)0x7380
877 #define ASC_MC_SAVE_CODE_WSIZE 0x500
878 #define ASC_MC_SAVE_DATA_WSIZE 0x40
880 typedef struct asc_mc_saved {
881 ushort data[ASC_MC_SAVE_DATA_WSIZE];
882 ushort code[ASC_MC_SAVE_CODE_WSIZE];
885 #define AscGetQDoneInProgress(port) AscReadLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B)
886 #define AscPutQDoneInProgress(port, val) AscWriteLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B, val)
887 #define AscGetVarFreeQHead(port) AscReadLramWord((port), ASCV_FREE_Q_HEAD_W)
888 #define AscGetVarDoneQTail(port) AscReadLramWord((port), ASCV_DONE_Q_TAIL_W)
889 #define AscPutVarFreeQHead(port, val) AscWriteLramWord((port), ASCV_FREE_Q_HEAD_W, val)
890 #define AscPutVarDoneQTail(port, val) AscWriteLramWord((port), ASCV_DONE_Q_TAIL_W, val)
891 #define AscGetRiscVarFreeQHead(port) AscReadLramByte((port), ASCV_NEXTRDY_B)
892 #define AscGetRiscVarDoneQTail(port) AscReadLramByte((port), ASCV_DONENEXT_B)
893 #define AscPutRiscVarFreeQHead(port, val) AscWriteLramByte((port), ASCV_NEXTRDY_B, val)
894 #define AscPutRiscVarDoneQTail(port, val) AscWriteLramByte((port), ASCV_DONENEXT_B, val)
895 #define AscPutMCodeSDTRDoneAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id), (data))
896 #define AscGetMCodeSDTRDoneAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id))
897 #define AscPutMCodeInitSDTRAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id), data)
898 #define AscGetMCodeInitSDTRAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id))
899 #define AscSynIndexToPeriod(index) (uchar)(asc_dvc->sdtr_period_tbl[ (index) ])
900 #define AscGetChipSignatureByte(port) (uchar)inp((port)+IOP_SIG_BYTE)
901 #define AscGetChipSignatureWord(port) (ushort)inpw((port)+IOP_SIG_WORD)
902 #define AscGetChipVerNo(port) (uchar)inp((port)+IOP_VERSION)
903 #define AscGetChipCfgLsw(port) (ushort)inpw((port)+IOP_CONFIG_LOW)
904 #define AscGetChipCfgMsw(port) (ushort)inpw((port)+IOP_CONFIG_HIGH)
905 #define AscSetChipCfgLsw(port, data) outpw((port)+IOP_CONFIG_LOW, data)
906 #define AscSetChipCfgMsw(port, data) outpw((port)+IOP_CONFIG_HIGH, data)
907 #define AscGetChipEEPCmd(port) (uchar)inp((port)+IOP_EEP_CMD)
908 #define AscSetChipEEPCmd(port, data) outp((port)+IOP_EEP_CMD, data)
909 #define AscGetChipEEPData(port) (ushort)inpw((port)+IOP_EEP_DATA)
910 #define AscSetChipEEPData(port, data) outpw((port)+IOP_EEP_DATA, data)
911 #define AscGetChipLramAddr(port) (ushort)inpw((PortAddr)((port)+IOP_RAM_ADDR))
912 #define AscSetChipLramAddr(port, addr) outpw((PortAddr)((port)+IOP_RAM_ADDR), addr)
913 #define AscGetChipLramData(port) (ushort)inpw((port)+IOP_RAM_DATA)
914 #define AscSetChipLramData(port, data) outpw((port)+IOP_RAM_DATA, data)
915 #define AscGetChipIFC(port) (uchar)inp((port)+IOP_REG_IFC)
916 #define AscSetChipIFC(port, data) outp((port)+IOP_REG_IFC, data)
917 #define AscGetChipStatus(port) (ASC_CS_TYPE)inpw((port)+IOP_STATUS)
918 #define AscSetChipStatus(port, cs_val) outpw((port)+IOP_STATUS, cs_val)
919 #define AscGetChipControl(port) (uchar)inp((port)+IOP_CTRL)
920 #define AscSetChipControl(port, cc_val) outp((port)+IOP_CTRL, cc_val)
921 #define AscGetChipSyn(port) (uchar)inp((port)+IOP_SYN_OFFSET)
922 #define AscSetChipSyn(port, data) outp((port)+IOP_SYN_OFFSET, data)
923 #define AscSetPCAddr(port, data) outpw((port)+IOP_REG_PC, data)
924 #define AscGetPCAddr(port) (ushort)inpw((port)+IOP_REG_PC)
925 #define AscIsIntPending(port) (AscGetChipStatus(port) & (CSW_INT_PENDING | CSW_SCSI_RESET_LATCH))
926 #define AscGetChipScsiID(port) ((AscGetChipCfgLsw(port) >> 8) & ASC_MAX_TID)
927 #define AscGetExtraControl(port) (uchar)inp((port)+IOP_EXTRA_CONTROL)
928 #define AscSetExtraControl(port, data) outp((port)+IOP_EXTRA_CONTROL, data)
929 #define AscReadChipAX(port) (ushort)inpw((port)+IOP_REG_AX)
930 #define AscWriteChipAX(port, data) outpw((port)+IOP_REG_AX, data)
931 #define AscReadChipIX(port) (uchar)inp((port)+IOP_REG_IX)
932 #define AscWriteChipIX(port, data) outp((port)+IOP_REG_IX, data)
933 #define AscReadChipIH(port) (ushort)inpw((port)+IOP_REG_IH)
934 #define AscWriteChipIH(port, data) outpw((port)+IOP_REG_IH, data)
935 #define AscReadChipQP(port) (uchar)inp((port)+IOP_REG_QP)
936 #define AscWriteChipQP(port, data) outp((port)+IOP_REG_QP, data)
937 #define AscReadChipFIFO_L(port) (ushort)inpw((port)+IOP_REG_FIFO_L)
938 #define AscWriteChipFIFO_L(port, data) outpw((port)+IOP_REG_FIFO_L, data)
939 #define AscReadChipFIFO_H(port) (ushort)inpw((port)+IOP_REG_FIFO_H)
940 #define AscWriteChipFIFO_H(port, data) outpw((port)+IOP_REG_FIFO_H, data)
941 #define AscReadChipDmaSpeed(port) (uchar)inp((port)+IOP_DMA_SPEED)
942 #define AscWriteChipDmaSpeed(port, data) outp((port)+IOP_DMA_SPEED, data)
943 #define AscReadChipDA0(port) (ushort)inpw((port)+IOP_REG_DA0)
944 #define AscWriteChipDA0(port) outpw((port)+IOP_REG_DA0, data)
945 #define AscReadChipDA1(port) (ushort)inpw((port)+IOP_REG_DA1)
946 #define AscWriteChipDA1(port) outpw((port)+IOP_REG_DA1, data)
947 #define AscReadChipDC0(port) (ushort)inpw((port)+IOP_REG_DC0)
948 #define AscWriteChipDC0(port) outpw((port)+IOP_REG_DC0, data)
949 #define AscReadChipDC1(port) (ushort)inpw((port)+IOP_REG_DC1)
950 #define AscWriteChipDC1(port) outpw((port)+IOP_REG_DC1, data)
951 #define AscReadChipDvcID(port) (uchar)inp((port)+IOP_REG_ID)
952 #define AscWriteChipDvcID(port, data) outp((port)+IOP_REG_ID, data)
955 * Portable Data Types
957 * Any instance where a 32-bit long or pointer type is assumed
958 * for precision or HW defined structures, the following define
959 * types must be used. In Linux the char, short, and int types
960 * are all consistent at 8, 16, and 32 bits respectively. Pointers
961 * and long types are 64 bits on Alpha and UltraSPARC.
963 #define ADV_PADDR __u32 /* Physical address data type. */
964 #define ADV_VADDR __u32 /* Virtual address data type. */
965 #define ADV_DCNT __u32 /* Unsigned Data count type. */
966 #define ADV_SDCNT __s32 /* Signed Data count type. */
969 * These macros are used to convert a virtual address to a
970 * 32-bit value. This currently can be used on Linux Alpha
971 * which uses 64-bit virtual address but a 32-bit bus address.
972 * This is likely to break in the future, but doing this now
973 * will give us time to change the HW and FW to handle 64-bit
976 #define ADV_VADDR_TO_U32 virt_to_bus
977 #define ADV_U32_TO_VADDR bus_to_virt
979 #define AdvPortAddr void __iomem * /* Virtual memory address size */
982 * Define Adv Library required memory access macros.
984 #define ADV_MEM_READB(addr) readb(addr)
985 #define ADV_MEM_READW(addr) readw(addr)
986 #define ADV_MEM_WRITEB(addr, byte) writeb(byte, addr)
987 #define ADV_MEM_WRITEW(addr, word) writew(word, addr)
988 #define ADV_MEM_WRITEDW(addr, dword) writel(dword, addr)
990 #define ADV_CARRIER_COUNT (ASC_DEF_MAX_HOST_QNG + 15)
993 * Define total number of simultaneous maximum element scatter-gather
994 * request blocks per wide adapter. ASC_DEF_MAX_HOST_QNG (253) is the
995 * maximum number of outstanding commands per wide host adapter. Each
996 * command uses one or more ADV_SG_BLOCK each with 15 scatter-gather
997 * elements. Allow each command to have at least one ADV_SG_BLOCK structure.
998 * This allows about 15 commands to have the maximum 17 ADV_SG_BLOCK
999 * structures or 255 scatter-gather elements.
1002 #define ADV_TOT_SG_BLOCK ASC_DEF_MAX_HOST_QNG
1005 * Define Adv Library required maximum number of scatter-gather
1006 * elements per request.
1008 #define ADV_MAX_SG_LIST 255
1010 /* Number of SG blocks needed. */
1011 #define ADV_NUM_SG_BLOCK \
1012 ((ADV_MAX_SG_LIST + (NO_OF_SG_PER_BLOCK - 1))/NO_OF_SG_PER_BLOCK)
1014 /* Total contiguous memory needed for SG blocks. */
1015 #define ADV_SG_TOTAL_MEM_SIZE \
1016 (sizeof(ADV_SG_BLOCK) * ADV_NUM_SG_BLOCK)
1018 #define ADV_PAGE_SIZE PAGE_SIZE
1020 #define ADV_NUM_PAGE_CROSSING \
1021 ((ADV_SG_TOTAL_MEM_SIZE + (ADV_PAGE_SIZE - 1))/ADV_PAGE_SIZE)
1023 #define ADV_EEP_DVC_CFG_BEGIN (0x00)
1024 #define ADV_EEP_DVC_CFG_END (0x15)
1025 #define ADV_EEP_DVC_CTL_BEGIN (0x16) /* location of OEM name */
1026 #define ADV_EEP_MAX_WORD_ADDR (0x1E)
1028 #define ADV_EEP_DELAY_MS 100
1030 #define ADV_EEPROM_BIG_ENDIAN 0x8000 /* EEPROM Bit 15 */
1031 #define ADV_EEPROM_BIOS_ENABLE 0x4000 /* EEPROM Bit 14 */
1033 * For the ASC3550 Bit 13 is Termination Polarity control bit.
1034 * For later ICs Bit 13 controls whether the CIS (Card Information
1035 * Service Section) is loaded from EEPROM.
1037 #define ADV_EEPROM_TERM_POL 0x2000 /* EEPROM Bit 13 */
1038 #define ADV_EEPROM_CIS_LD 0x2000 /* EEPROM Bit 13 */
1042 * If EEPROM Bit 11 is 0 for Function 0, then Function 0 will specify
1043 * INT A in the PCI Configuration Space Int Pin field. If it is 1, then
1044 * Function 0 will specify INT B.
1046 * If EEPROM Bit 11 is 0 for Function 1, then Function 1 will specify
1047 * INT B in the PCI Configuration Space Int Pin field. If it is 1, then
1048 * Function 1 will specify INT A.
1050 #define ADV_EEPROM_INTAB 0x0800 /* EEPROM Bit 11 */
1052 typedef struct adveep_3550_config {
1053 /* Word Offset, Description */
1055 ushort cfg_lsw; /* 00 power up initialization */
1056 /* bit 13 set - Term Polarity Control */
1057 /* bit 14 set - BIOS Enable */
1058 /* bit 15 set - Big Endian Mode */
1059 ushort cfg_msw; /* 01 unused */
1060 ushort disc_enable; /* 02 disconnect enable */
1061 ushort wdtr_able; /* 03 Wide DTR able */
1062 ushort sdtr_able; /* 04 Synchronous DTR able */
1063 ushort start_motor; /* 05 send start up motor */
1064 ushort tagqng_able; /* 06 tag queuing able */
1065 ushort bios_scan; /* 07 BIOS device control */
1066 ushort scam_tolerant; /* 08 no scam */
1068 uchar adapter_scsi_id; /* 09 Host Adapter ID */
1069 uchar bios_boot_delay; /* power up wait */
1071 uchar scsi_reset_delay; /* 10 reset delay */
1072 uchar bios_id_lun; /* first boot device scsi id & lun */
1073 /* high nibble is lun */
1074 /* low nibble is scsi id */
1076 uchar termination; /* 11 0 - automatic */
1077 /* 1 - low off / high off */
1078 /* 2 - low off / high on */
1079 /* 3 - low on / high on */
1080 /* There is no low on / high off */
1082 uchar reserved1; /* reserved byte (not used) */
1084 ushort bios_ctrl; /* 12 BIOS control bits */
1085 /* bit 0 BIOS don't act as initiator. */
1086 /* bit 1 BIOS > 1 GB support */
1087 /* bit 2 BIOS > 2 Disk Support */
1088 /* bit 3 BIOS don't support removables */
1089 /* bit 4 BIOS support bootable CD */
1090 /* bit 5 BIOS scan enabled */
1091 /* bit 6 BIOS support multiple LUNs */
1092 /* bit 7 BIOS display of message */
1093 /* bit 8 SCAM disabled */
1094 /* bit 9 Reset SCSI bus during init. */
1096 /* bit 11 No verbose initialization. */
1097 /* bit 12 SCSI parity enabled */
1101 ushort ultra_able; /* 13 ULTRA speed able */
1102 ushort reserved2; /* 14 reserved */
1103 uchar max_host_qng; /* 15 maximum host queuing */
1104 uchar max_dvc_qng; /* maximum per device queuing */
1105 ushort dvc_cntl; /* 16 control bit for driver */
1106 ushort bug_fix; /* 17 control bit for bug fix */
1107 ushort serial_number_word1; /* 18 Board serial number word 1 */
1108 ushort serial_number_word2; /* 19 Board serial number word 2 */
1109 ushort serial_number_word3; /* 20 Board serial number word 3 */
1110 ushort check_sum; /* 21 EEP check sum */
1111 uchar oem_name[16]; /* 22 OEM name */
1112 ushort dvc_err_code; /* 30 last device driver error code */
1113 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
1114 ushort adv_err_addr; /* 32 last uc error address */
1115 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
1116 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
1117 ushort saved_adv_err_addr; /* 35 saved last uc error address */
1118 ushort num_of_err; /* 36 number of error */
1119 } ADVEEP_3550_CONFIG;
1121 typedef struct adveep_38C0800_config {
1122 /* Word Offset, Description */
1124 ushort cfg_lsw; /* 00 power up initialization */
1125 /* bit 13 set - Load CIS */
1126 /* bit 14 set - BIOS Enable */
1127 /* bit 15 set - Big Endian Mode */
1128 ushort cfg_msw; /* 01 unused */
1129 ushort disc_enable; /* 02 disconnect enable */
1130 ushort wdtr_able; /* 03 Wide DTR able */
1131 ushort sdtr_speed1; /* 04 SDTR Speed TID 0-3 */
1132 ushort start_motor; /* 05 send start up motor */
1133 ushort tagqng_able; /* 06 tag queuing able */
1134 ushort bios_scan; /* 07 BIOS device control */
1135 ushort scam_tolerant; /* 08 no scam */
1137 uchar adapter_scsi_id; /* 09 Host Adapter ID */
1138 uchar bios_boot_delay; /* power up wait */
1140 uchar scsi_reset_delay; /* 10 reset delay */
1141 uchar bios_id_lun; /* first boot device scsi id & lun */
1142 /* high nibble is lun */
1143 /* low nibble is scsi id */
1145 uchar termination_se; /* 11 0 - automatic */
1146 /* 1 - low off / high off */
1147 /* 2 - low off / high on */
1148 /* 3 - low on / high on */
1149 /* There is no low on / high off */
1151 uchar termination_lvd; /* 11 0 - automatic */
1152 /* 1 - low off / high off */
1153 /* 2 - low off / high on */
1154 /* 3 - low on / high on */
1155 /* There is no low on / high off */
1157 ushort bios_ctrl; /* 12 BIOS control bits */
1158 /* bit 0 BIOS don't act as initiator. */
1159 /* bit 1 BIOS > 1 GB support */
1160 /* bit 2 BIOS > 2 Disk Support */
1161 /* bit 3 BIOS don't support removables */
1162 /* bit 4 BIOS support bootable CD */
1163 /* bit 5 BIOS scan enabled */
1164 /* bit 6 BIOS support multiple LUNs */
1165 /* bit 7 BIOS display of message */
1166 /* bit 8 SCAM disabled */
1167 /* bit 9 Reset SCSI bus during init. */
1169 /* bit 11 No verbose initialization. */
1170 /* bit 12 SCSI parity enabled */
1174 ushort sdtr_speed2; /* 13 SDTR speed TID 4-7 */
1175 ushort sdtr_speed3; /* 14 SDTR speed TID 8-11 */
1176 uchar max_host_qng; /* 15 maximum host queueing */
1177 uchar max_dvc_qng; /* maximum per device queuing */
1178 ushort dvc_cntl; /* 16 control bit for driver */
1179 ushort sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */
1180 ushort serial_number_word1; /* 18 Board serial number word 1 */
1181 ushort serial_number_word2; /* 19 Board serial number word 2 */
1182 ushort serial_number_word3; /* 20 Board serial number word 3 */
1183 ushort check_sum; /* 21 EEP check sum */
1184 uchar oem_name[16]; /* 22 OEM name */
1185 ushort dvc_err_code; /* 30 last device driver error code */
1186 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
1187 ushort adv_err_addr; /* 32 last uc error address */
1188 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
1189 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
1190 ushort saved_adv_err_addr; /* 35 saved last uc error address */
1191 ushort reserved36; /* 36 reserved */
1192 ushort reserved37; /* 37 reserved */
1193 ushort reserved38; /* 38 reserved */
1194 ushort reserved39; /* 39 reserved */
1195 ushort reserved40; /* 40 reserved */
1196 ushort reserved41; /* 41 reserved */
1197 ushort reserved42; /* 42 reserved */
1198 ushort reserved43; /* 43 reserved */
1199 ushort reserved44; /* 44 reserved */
1200 ushort reserved45; /* 45 reserved */
1201 ushort reserved46; /* 46 reserved */
1202 ushort reserved47; /* 47 reserved */
1203 ushort reserved48; /* 48 reserved */
1204 ushort reserved49; /* 49 reserved */
1205 ushort reserved50; /* 50 reserved */
1206 ushort reserved51; /* 51 reserved */
1207 ushort reserved52; /* 52 reserved */
1208 ushort reserved53; /* 53 reserved */
1209 ushort reserved54; /* 54 reserved */
1210 ushort reserved55; /* 55 reserved */
1211 ushort cisptr_lsw; /* 56 CIS PTR LSW */
1212 ushort cisprt_msw; /* 57 CIS PTR MSW */
1213 ushort subsysvid; /* 58 SubSystem Vendor ID */
1214 ushort subsysid; /* 59 SubSystem ID */
1215 ushort reserved60; /* 60 reserved */
1216 ushort reserved61; /* 61 reserved */
1217 ushort reserved62; /* 62 reserved */
1218 ushort reserved63; /* 63 reserved */
1219 } ADVEEP_38C0800_CONFIG;
1221 typedef struct adveep_38C1600_config {
1222 /* Word Offset, Description */
1224 ushort cfg_lsw; /* 00 power up initialization */
1225 /* bit 11 set - Func. 0 INTB, Func. 1 INTA */
1226 /* clear - Func. 0 INTA, Func. 1 INTB */
1227 /* bit 13 set - Load CIS */
1228 /* bit 14 set - BIOS Enable */
1229 /* bit 15 set - Big Endian Mode */
1230 ushort cfg_msw; /* 01 unused */
1231 ushort disc_enable; /* 02 disconnect enable */
1232 ushort wdtr_able; /* 03 Wide DTR able */
1233 ushort sdtr_speed1; /* 04 SDTR Speed TID 0-3 */
1234 ushort start_motor; /* 05 send start up motor */
1235 ushort tagqng_able; /* 06 tag queuing able */
1236 ushort bios_scan; /* 07 BIOS device control */
1237 ushort scam_tolerant; /* 08 no scam */
1239 uchar adapter_scsi_id; /* 09 Host Adapter ID */
1240 uchar bios_boot_delay; /* power up wait */
1242 uchar scsi_reset_delay; /* 10 reset delay */
1243 uchar bios_id_lun; /* first boot device scsi id & lun */
1244 /* high nibble is lun */
1245 /* low nibble is scsi id */
1247 uchar termination_se; /* 11 0 - automatic */
1248 /* 1 - low off / high off */
1249 /* 2 - low off / high on */
1250 /* 3 - low on / high on */
1251 /* There is no low on / high off */
1253 uchar termination_lvd; /* 11 0 - automatic */
1254 /* 1 - low off / high off */
1255 /* 2 - low off / high on */
1256 /* 3 - low on / high on */
1257 /* There is no low on / high off */
1259 ushort bios_ctrl; /* 12 BIOS control bits */
1260 /* bit 0 BIOS don't act as initiator. */
1261 /* bit 1 BIOS > 1 GB support */
1262 /* bit 2 BIOS > 2 Disk Support */
1263 /* bit 3 BIOS don't support removables */
1264 /* bit 4 BIOS support bootable CD */
1265 /* bit 5 BIOS scan enabled */
1266 /* bit 6 BIOS support multiple LUNs */
1267 /* bit 7 BIOS display of message */
1268 /* bit 8 SCAM disabled */
1269 /* bit 9 Reset SCSI bus during init. */
1270 /* bit 10 Basic Integrity Checking disabled */
1271 /* bit 11 No verbose initialization. */
1272 /* bit 12 SCSI parity enabled */
1273 /* bit 13 AIPP (Asyn. Info. Ph. Prot.) dis. */
1276 ushort sdtr_speed2; /* 13 SDTR speed TID 4-7 */
1277 ushort sdtr_speed3; /* 14 SDTR speed TID 8-11 */
1278 uchar max_host_qng; /* 15 maximum host queueing */
1279 uchar max_dvc_qng; /* maximum per device queuing */
1280 ushort dvc_cntl; /* 16 control bit for driver */
1281 ushort sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */
1282 ushort serial_number_word1; /* 18 Board serial number word 1 */
1283 ushort serial_number_word2; /* 19 Board serial number word 2 */
1284 ushort serial_number_word3; /* 20 Board serial number word 3 */
1285 ushort check_sum; /* 21 EEP check sum */
1286 uchar oem_name[16]; /* 22 OEM name */
1287 ushort dvc_err_code; /* 30 last device driver error code */
1288 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
1289 ushort adv_err_addr; /* 32 last uc error address */
1290 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
1291 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
1292 ushort saved_adv_err_addr; /* 35 saved last uc error address */
1293 ushort reserved36; /* 36 reserved */
1294 ushort reserved37; /* 37 reserved */
1295 ushort reserved38; /* 38 reserved */
1296 ushort reserved39; /* 39 reserved */
1297 ushort reserved40; /* 40 reserved */
1298 ushort reserved41; /* 41 reserved */
1299 ushort reserved42; /* 42 reserved */
1300 ushort reserved43; /* 43 reserved */
1301 ushort reserved44; /* 44 reserved */
1302 ushort reserved45; /* 45 reserved */
1303 ushort reserved46; /* 46 reserved */
1304 ushort reserved47; /* 47 reserved */
1305 ushort reserved48; /* 48 reserved */
1306 ushort reserved49; /* 49 reserved */
1307 ushort reserved50; /* 50 reserved */
1308 ushort reserved51; /* 51 reserved */
1309 ushort reserved52; /* 52 reserved */
1310 ushort reserved53; /* 53 reserved */
1311 ushort reserved54; /* 54 reserved */
1312 ushort reserved55; /* 55 reserved */
1313 ushort cisptr_lsw; /* 56 CIS PTR LSW */
1314 ushort cisprt_msw; /* 57 CIS PTR MSW */
1315 ushort subsysvid; /* 58 SubSystem Vendor ID */
1316 ushort subsysid; /* 59 SubSystem ID */
1317 ushort reserved60; /* 60 reserved */
1318 ushort reserved61; /* 61 reserved */
1319 ushort reserved62; /* 62 reserved */
1320 ushort reserved63; /* 63 reserved */
1321 } ADVEEP_38C1600_CONFIG;
1326 #define ASC_EEP_CMD_DONE 0x0200
1329 #define BIOS_CTRL_BIOS 0x0001
1330 #define BIOS_CTRL_EXTENDED_XLAT 0x0002
1331 #define BIOS_CTRL_GT_2_DISK 0x0004
1332 #define BIOS_CTRL_BIOS_REMOVABLE 0x0008
1333 #define BIOS_CTRL_BOOTABLE_CD 0x0010
1334 #define BIOS_CTRL_MULTIPLE_LUN 0x0040
1335 #define BIOS_CTRL_DISPLAY_MSG 0x0080
1336 #define BIOS_CTRL_NO_SCAM 0x0100
1337 #define BIOS_CTRL_RESET_SCSI_BUS 0x0200
1338 #define BIOS_CTRL_INIT_VERBOSE 0x0800
1339 #define BIOS_CTRL_SCSI_PARITY 0x1000
1340 #define BIOS_CTRL_AIPP_DIS 0x2000
1342 #define ADV_3550_MEMSIZE 0x2000 /* 8 KB Internal Memory */
1344 #define ADV_38C0800_MEMSIZE 0x4000 /* 16 KB Internal Memory */
1347 * XXX - Since ASC38C1600 Rev.3 has a local RAM failure issue, there is
1348 * a special 16K Adv Library and Microcode version. After the issue is
1349 * resolved, should restore 32K support.
1351 * #define ADV_38C1600_MEMSIZE 0x8000L * 32 KB Internal Memory *
1353 #define ADV_38C1600_MEMSIZE 0x4000 /* 16 KB Internal Memory */
1356 * Byte I/O register address from base of 'iop_base'.
1358 #define IOPB_INTR_STATUS_REG 0x00
1359 #define IOPB_CHIP_ID_1 0x01
1360 #define IOPB_INTR_ENABLES 0x02
1361 #define IOPB_CHIP_TYPE_REV 0x03
1362 #define IOPB_RES_ADDR_4 0x04
1363 #define IOPB_RES_ADDR_5 0x05
1364 #define IOPB_RAM_DATA 0x06
1365 #define IOPB_RES_ADDR_7 0x07
1366 #define IOPB_FLAG_REG 0x08
1367 #define IOPB_RES_ADDR_9 0x09
1368 #define IOPB_RISC_CSR 0x0A
1369 #define IOPB_RES_ADDR_B 0x0B
1370 #define IOPB_RES_ADDR_C 0x0C
1371 #define IOPB_RES_ADDR_D 0x0D
1372 #define IOPB_SOFT_OVER_WR 0x0E
1373 #define IOPB_RES_ADDR_F 0x0F
1374 #define IOPB_MEM_CFG 0x10
1375 #define IOPB_RES_ADDR_11 0x11
1376 #define IOPB_GPIO_DATA 0x12
1377 #define IOPB_RES_ADDR_13 0x13
1378 #define IOPB_FLASH_PAGE 0x14
1379 #define IOPB_RES_ADDR_15 0x15
1380 #define IOPB_GPIO_CNTL 0x16
1381 #define IOPB_RES_ADDR_17 0x17
1382 #define IOPB_FLASH_DATA 0x18
1383 #define IOPB_RES_ADDR_19 0x19
1384 #define IOPB_RES_ADDR_1A 0x1A
1385 #define IOPB_RES_ADDR_1B 0x1B
1386 #define IOPB_RES_ADDR_1C 0x1C
1387 #define IOPB_RES_ADDR_1D 0x1D
1388 #define IOPB_RES_ADDR_1E 0x1E
1389 #define IOPB_RES_ADDR_1F 0x1F
1390 #define IOPB_DMA_CFG0 0x20
1391 #define IOPB_DMA_CFG1 0x21
1392 #define IOPB_TICKLE 0x22
1393 #define IOPB_DMA_REG_WR 0x23
1394 #define IOPB_SDMA_STATUS 0x24
1395 #define IOPB_SCSI_BYTE_CNT 0x25
1396 #define IOPB_HOST_BYTE_CNT 0x26
1397 #define IOPB_BYTE_LEFT_TO_XFER 0x27
1398 #define IOPB_BYTE_TO_XFER_0 0x28
1399 #define IOPB_BYTE_TO_XFER_1 0x29
1400 #define IOPB_BYTE_TO_XFER_2 0x2A
1401 #define IOPB_BYTE_TO_XFER_3 0x2B
1402 #define IOPB_ACC_GRP 0x2C
1403 #define IOPB_RES_ADDR_2D 0x2D
1404 #define IOPB_DEV_ID 0x2E
1405 #define IOPB_RES_ADDR_2F 0x2F
1406 #define IOPB_SCSI_DATA 0x30
1407 #define IOPB_RES_ADDR_31 0x31
1408 #define IOPB_RES_ADDR_32 0x32
1409 #define IOPB_SCSI_DATA_HSHK 0x33
1410 #define IOPB_SCSI_CTRL 0x34
1411 #define IOPB_RES_ADDR_35 0x35
1412 #define IOPB_RES_ADDR_36 0x36
1413 #define IOPB_RES_ADDR_37 0x37
1414 #define IOPB_RAM_BIST 0x38
1415 #define IOPB_PLL_TEST 0x39
1416 #define IOPB_PCI_INT_CFG 0x3A
1417 #define IOPB_RES_ADDR_3B 0x3B
1418 #define IOPB_RFIFO_CNT 0x3C
1419 #define IOPB_RES_ADDR_3D 0x3D
1420 #define IOPB_RES_ADDR_3E 0x3E
1421 #define IOPB_RES_ADDR_3F 0x3F
1424 * Word I/O register address from base of 'iop_base'.
1426 #define IOPW_CHIP_ID_0 0x00 /* CID0 */
1427 #define IOPW_CTRL_REG 0x02 /* CC */
1428 #define IOPW_RAM_ADDR 0x04 /* LA */
1429 #define IOPW_RAM_DATA 0x06 /* LD */
1430 #define IOPW_RES_ADDR_08 0x08
1431 #define IOPW_RISC_CSR 0x0A /* CSR */
1432 #define IOPW_SCSI_CFG0 0x0C /* CFG0 */
1433 #define IOPW_SCSI_CFG1 0x0E /* CFG1 */
1434 #define IOPW_RES_ADDR_10 0x10
1435 #define IOPW_SEL_MASK 0x12 /* SM */
1436 #define IOPW_RES_ADDR_14 0x14
1437 #define IOPW_FLASH_ADDR 0x16 /* FA */
1438 #define IOPW_RES_ADDR_18 0x18
1439 #define IOPW_EE_CMD 0x1A /* EC */
1440 #define IOPW_EE_DATA 0x1C /* ED */
1441 #define IOPW_SFIFO_CNT 0x1E /* SFC */
1442 #define IOPW_RES_ADDR_20 0x20
1443 #define IOPW_Q_BASE 0x22 /* QB */
1444 #define IOPW_QP 0x24 /* QP */
1445 #define IOPW_IX 0x26 /* IX */
1446 #define IOPW_SP 0x28 /* SP */
1447 #define IOPW_PC 0x2A /* PC */
1448 #define IOPW_RES_ADDR_2C 0x2C
1449 #define IOPW_RES_ADDR_2E 0x2E
1450 #define IOPW_SCSI_DATA 0x30 /* SD */
1451 #define IOPW_SCSI_DATA_HSHK 0x32 /* SDH */
1452 #define IOPW_SCSI_CTRL 0x34 /* SC */
1453 #define IOPW_HSHK_CFG 0x36 /* HCFG */
1454 #define IOPW_SXFR_STATUS 0x36 /* SXS */
1455 #define IOPW_SXFR_CNTL 0x38 /* SXL */
1456 #define IOPW_SXFR_CNTH 0x3A /* SXH */
1457 #define IOPW_RES_ADDR_3C 0x3C
1458 #define IOPW_RFIFO_DATA 0x3E /* RFD */
1461 * Doubleword I/O register address from base of 'iop_base'.
1463 #define IOPDW_RES_ADDR_0 0x00
1464 #define IOPDW_RAM_DATA 0x04
1465 #define IOPDW_RES_ADDR_8 0x08
1466 #define IOPDW_RES_ADDR_C 0x0C
1467 #define IOPDW_RES_ADDR_10 0x10
1468 #define IOPDW_COMMA 0x14
1469 #define IOPDW_COMMB 0x18
1470 #define IOPDW_RES_ADDR_1C 0x1C
1471 #define IOPDW_SDMA_ADDR0 0x20
1472 #define IOPDW_SDMA_ADDR1 0x24
1473 #define IOPDW_SDMA_COUNT 0x28
1474 #define IOPDW_SDMA_ERROR 0x2C
1475 #define IOPDW_RDMA_ADDR0 0x30
1476 #define IOPDW_RDMA_ADDR1 0x34
1477 #define IOPDW_RDMA_COUNT 0x38
1478 #define IOPDW_RDMA_ERROR 0x3C
1480 #define ADV_CHIP_ID_BYTE 0x25
1481 #define ADV_CHIP_ID_WORD 0x04C1
1483 #define ADV_INTR_ENABLE_HOST_INTR 0x01
1484 #define ADV_INTR_ENABLE_SEL_INTR 0x02
1485 #define ADV_INTR_ENABLE_DPR_INTR 0x04
1486 #define ADV_INTR_ENABLE_RTA_INTR 0x08
1487 #define ADV_INTR_ENABLE_RMA_INTR 0x10
1488 #define ADV_INTR_ENABLE_RST_INTR 0x20
1489 #define ADV_INTR_ENABLE_DPE_INTR 0x40
1490 #define ADV_INTR_ENABLE_GLOBAL_INTR 0x80
1492 #define ADV_INTR_STATUS_INTRA 0x01
1493 #define ADV_INTR_STATUS_INTRB 0x02
1494 #define ADV_INTR_STATUS_INTRC 0x04
1496 #define ADV_RISC_CSR_STOP (0x0000)
1497 #define ADV_RISC_TEST_COND (0x2000)
1498 #define ADV_RISC_CSR_RUN (0x4000)
1499 #define ADV_RISC_CSR_SINGLE_STEP (0x8000)
1501 #define ADV_CTRL_REG_HOST_INTR 0x0100
1502 #define ADV_CTRL_REG_SEL_INTR 0x0200
1503 #define ADV_CTRL_REG_DPR_INTR 0x0400
1504 #define ADV_CTRL_REG_RTA_INTR 0x0800
1505 #define ADV_CTRL_REG_RMA_INTR 0x1000
1506 #define ADV_CTRL_REG_RES_BIT14 0x2000
1507 #define ADV_CTRL_REG_DPE_INTR 0x4000
1508 #define ADV_CTRL_REG_POWER_DONE 0x8000
1509 #define ADV_CTRL_REG_ANY_INTR 0xFF00
1511 #define ADV_CTRL_REG_CMD_RESET 0x00C6
1512 #define ADV_CTRL_REG_CMD_WR_IO_REG 0x00C5
1513 #define ADV_CTRL_REG_CMD_RD_IO_REG 0x00C4
1514 #define ADV_CTRL_REG_CMD_WR_PCI_CFG_SPACE 0x00C3
1515 #define ADV_CTRL_REG_CMD_RD_PCI_CFG_SPACE 0x00C2
1517 #define ADV_TICKLE_NOP 0x00
1518 #define ADV_TICKLE_A 0x01
1519 #define ADV_TICKLE_B 0x02
1520 #define ADV_TICKLE_C 0x03
1522 #define AdvIsIntPending(port) \
1523 (AdvReadWordRegister(port, IOPW_CTRL_REG) & ADV_CTRL_REG_HOST_INTR)
1526 * SCSI_CFG0 Register bit definitions
1528 #define TIMER_MODEAB 0xC000 /* Watchdog, Second, and Select. Timer Ctrl. */
1529 #define PARITY_EN 0x2000 /* Enable SCSI Parity Error detection */
1530 #define EVEN_PARITY 0x1000 /* Select Even Parity */
1531 #define WD_LONG 0x0800 /* Watchdog Interval, 1: 57 min, 0: 13 sec */
1532 #define QUEUE_128 0x0400 /* Queue Size, 1: 128 byte, 0: 64 byte */
1533 #define PRIM_MODE 0x0100 /* Primitive SCSI mode */
1534 #define SCAM_EN 0x0080 /* Enable SCAM selection */
1535 #define SEL_TMO_LONG 0x0040 /* Sel/Resel Timeout, 1: 400 ms, 0: 1.6 ms */
1536 #define CFRM_ID 0x0020 /* SCAM id sel. confirm., 1: fast, 0: 6.4 ms */
1537 #define OUR_ID_EN 0x0010 /* Enable OUR_ID bits */
1538 #define OUR_ID 0x000F /* SCSI ID */
1541 * SCSI_CFG1 Register bit definitions
1543 #define BIG_ENDIAN 0x8000 /* Enable Big Endian Mode MIO:15, EEP:15 */
1544 #define TERM_POL 0x2000 /* Terminator Polarity Ctrl. MIO:13, EEP:13 */
1545 #define SLEW_RATE 0x1000 /* SCSI output buffer slew rate */
1546 #define FILTER_SEL 0x0C00 /* Filter Period Selection */
1547 #define FLTR_DISABLE 0x0000 /* Input Filtering Disabled */
1548 #define FLTR_11_TO_20NS 0x0800 /* Input Filtering 11ns to 20ns */
1549 #define FLTR_21_TO_39NS 0x0C00 /* Input Filtering 21ns to 39ns */
1550 #define ACTIVE_DBL 0x0200 /* Disable Active Negation */
1551 #define DIFF_MODE 0x0100 /* SCSI differential Mode (Read-Only) */
1552 #define DIFF_SENSE 0x0080 /* 1: No SE cables, 0: SE cable (Read-Only) */
1553 #define TERM_CTL_SEL 0x0040 /* Enable TERM_CTL_H and TERM_CTL_L */
1554 #define TERM_CTL 0x0030 /* External SCSI Termination Bits */
1555 #define TERM_CTL_H 0x0020 /* Enable External SCSI Upper Termination */
1556 #define TERM_CTL_L 0x0010 /* Enable External SCSI Lower Termination */
1557 #define CABLE_DETECT 0x000F /* External SCSI Cable Connection Status */
1560 * Addendum for ASC-38C0800 Chip
1562 * The ASC-38C1600 Chip uses the same definitions except that the
1563 * bus mode override bits [12:10] have been moved to byte register
1564 * offset 0xE (IOPB_SOFT_OVER_WR) bits [12:10]. The [12:10] bits in
1565 * SCSI_CFG1 are read-only and always available. Bit 14 (DIS_TERM_DRV)
1566 * is not needed. The [12:10] bits in IOPB_SOFT_OVER_WR are write-only.
1567 * Also each ASC-38C1600 function or channel uses only cable bits [5:4]
1568 * and [1:0]. Bits [14], [7:6], [3:2] are unused.
1570 #define DIS_TERM_DRV 0x4000 /* 1: Read c_det[3:0], 0: cannot read */
1571 #define HVD_LVD_SE 0x1C00 /* Device Detect Bits */
1572 #define HVD 0x1000 /* HVD Device Detect */
1573 #define LVD 0x0800 /* LVD Device Detect */
1574 #define SE 0x0400 /* SE Device Detect */
1575 #define TERM_LVD 0x00C0 /* LVD Termination Bits */
1576 #define TERM_LVD_HI 0x0080 /* Enable LVD Upper Termination */
1577 #define TERM_LVD_LO 0x0040 /* Enable LVD Lower Termination */
1578 #define TERM_SE 0x0030 /* SE Termination Bits */
1579 #define TERM_SE_HI 0x0020 /* Enable SE Upper Termination */
1580 #define TERM_SE_LO 0x0010 /* Enable SE Lower Termination */
1581 #define C_DET_LVD 0x000C /* LVD Cable Detect Bits */
1582 #define C_DET3 0x0008 /* Cable Detect for LVD External Wide */
1583 #define C_DET2 0x0004 /* Cable Detect for LVD Internal Wide */
1584 #define C_DET_SE 0x0003 /* SE Cable Detect Bits */
1585 #define C_DET1 0x0002 /* Cable Detect for SE Internal Wide */
1586 #define C_DET0 0x0001 /* Cable Detect for SE Internal Narrow */
1588 #define CABLE_ILLEGAL_A 0x7
1589 /* x 0 0 0 | on on | Illegal (all 3 connectors are used) */
1591 #define CABLE_ILLEGAL_B 0xB
1592 /* 0 x 0 0 | on on | Illegal (all 3 connectors are used) */
1595 * MEM_CFG Register bit definitions
1597 #define BIOS_EN 0x40 /* BIOS Enable MIO:14,EEP:14 */
1598 #define FAST_EE_CLK 0x20 /* Diagnostic Bit */
1599 #define RAM_SZ 0x1C /* Specify size of RAM to RISC */
1600 #define RAM_SZ_2KB 0x00 /* 2 KB */
1601 #define RAM_SZ_4KB 0x04 /* 4 KB */
1602 #define RAM_SZ_8KB 0x08 /* 8 KB */
1603 #define RAM_SZ_16KB 0x0C /* 16 KB */
1604 #define RAM_SZ_32KB 0x10 /* 32 KB */
1605 #define RAM_SZ_64KB 0x14 /* 64 KB */
1608 * DMA_CFG0 Register bit definitions
1610 * This register is only accessible to the host.
1612 #define BC_THRESH_ENB 0x80 /* PCI DMA Start Conditions */
1613 #define FIFO_THRESH 0x70 /* PCI DMA FIFO Threshold */
1614 #define FIFO_THRESH_16B 0x00 /* 16 bytes */
1615 #define FIFO_THRESH_32B 0x20 /* 32 bytes */
1616 #define FIFO_THRESH_48B 0x30 /* 48 bytes */
1617 #define FIFO_THRESH_64B 0x40 /* 64 bytes */
1618 #define FIFO_THRESH_80B 0x50 /* 80 bytes (default) */
1619 #define FIFO_THRESH_96B 0x60 /* 96 bytes */
1620 #define FIFO_THRESH_112B 0x70 /* 112 bytes */
1621 #define START_CTL 0x0C /* DMA start conditions */
1622 #define START_CTL_TH 0x00 /* Wait threshold level (default) */
1623 #define START_CTL_ID 0x04 /* Wait SDMA/SBUS idle */
1624 #define START_CTL_THID 0x08 /* Wait threshold and SDMA/SBUS idle */
1625 #define START_CTL_EMFU 0x0C /* Wait SDMA FIFO empty/full */
1626 #define READ_CMD 0x03 /* Memory Read Method */
1627 #define READ_CMD_MR 0x00 /* Memory Read */
1628 #define READ_CMD_MRL 0x02 /* Memory Read Long */
1629 #define READ_CMD_MRM 0x03 /* Memory Read Multiple (default) */
1632 * ASC-38C0800 RAM BIST Register bit definitions
1634 #define RAM_TEST_MODE 0x80
1635 #define PRE_TEST_MODE 0x40
1636 #define NORMAL_MODE 0x00
1637 #define RAM_TEST_DONE 0x10
1638 #define RAM_TEST_STATUS 0x0F
1639 #define RAM_TEST_HOST_ERROR 0x08
1640 #define RAM_TEST_INTRAM_ERROR 0x04
1641 #define RAM_TEST_RISC_ERROR 0x02
1642 #define RAM_TEST_SCSI_ERROR 0x01
1643 #define RAM_TEST_SUCCESS 0x00
1644 #define PRE_TEST_VALUE 0x05
1645 #define NORMAL_VALUE 0x00
1648 * ASC38C1600 Definitions
1650 * IOPB_PCI_INT_CFG Bit Field Definitions
1653 #define INTAB_LD 0x80 /* Value loaded from EEPROM Bit 11. */
1656 * Bit 1 can be set to change the interrupt for the Function to operate in
1657 * Totem Pole mode. By default Bit 1 is 0 and the interrupt operates in
1658 * Open Drain mode. Both functions of the ASC38C1600 must be set to the same
1659 * mode, otherwise the operating mode is undefined.
1661 #define TOTEMPOLE 0x02
1664 * Bit 0 can be used to change the Int Pin for the Function. The value is
1665 * 0 by default for both Functions with Function 0 using INT A and Function
1666 * B using INT B. For Function 0 if set, INT B is used. For Function 1 if set,
1669 * EEPROM Word 0 Bit 11 for each Function may change the initial Int Pin
1670 * value specified in the PCI Configuration Space.
1675 * Adv Library Status Definitions
1679 #define ADV_SUCCESS 1
1681 #define ADV_ERROR (-1)
1684 * ADV_DVC_VAR 'warn_code' values
1686 #define ASC_WARN_BUSRESET_ERROR 0x0001 /* SCSI Bus Reset error */
1687 #define ASC_WARN_EEPROM_CHKSUM 0x0002 /* EEP check sum error */
1688 #define ASC_WARN_EEPROM_TERMINATION 0x0004 /* EEP termination bad field */
1689 #define ASC_WARN_ERROR 0xFFFF /* ADV_ERROR return */
1691 #define ADV_MAX_TID 15 /* max. target identifier */
1692 #define ADV_MAX_LUN 7 /* max. logical unit number */
1695 * Fixed locations of microcode operating variables.
1697 #define ASC_MC_CODE_BEGIN_ADDR 0x0028 /* microcode start address */
1698 #define ASC_MC_CODE_END_ADDR 0x002A /* microcode end address */
1699 #define ASC_MC_CODE_CHK_SUM 0x002C /* microcode code checksum */
1700 #define ASC_MC_VERSION_DATE 0x0038 /* microcode version */
1701 #define ASC_MC_VERSION_NUM 0x003A /* microcode number */
1702 #define ASC_MC_BIOSMEM 0x0040 /* BIOS RISC Memory Start */
1703 #define ASC_MC_BIOSLEN 0x0050 /* BIOS RISC Memory Length */
1704 #define ASC_MC_BIOS_SIGNATURE 0x0058 /* BIOS Signature 0x55AA */
1705 #define ASC_MC_BIOS_VERSION 0x005A /* BIOS Version (2 bytes) */
1706 #define ASC_MC_SDTR_SPEED1 0x0090 /* SDTR Speed for TID 0-3 */
1707 #define ASC_MC_SDTR_SPEED2 0x0092 /* SDTR Speed for TID 4-7 */
1708 #define ASC_MC_SDTR_SPEED3 0x0094 /* SDTR Speed for TID 8-11 */
1709 #define ASC_MC_SDTR_SPEED4 0x0096 /* SDTR Speed for TID 12-15 */
1710 #define ASC_MC_CHIP_TYPE 0x009A
1711 #define ASC_MC_INTRB_CODE 0x009B
1712 #define ASC_MC_WDTR_ABLE 0x009C
1713 #define ASC_MC_SDTR_ABLE 0x009E
1714 #define ASC_MC_TAGQNG_ABLE 0x00A0
1715 #define ASC_MC_DISC_ENABLE 0x00A2
1716 #define ASC_MC_IDLE_CMD_STATUS 0x00A4
1717 #define ASC_MC_IDLE_CMD 0x00A6
1718 #define ASC_MC_IDLE_CMD_PARAMETER 0x00A8
1719 #define ASC_MC_DEFAULT_SCSI_CFG0 0x00AC
1720 #define ASC_MC_DEFAULT_SCSI_CFG1 0x00AE
1721 #define ASC_MC_DEFAULT_MEM_CFG 0x00B0
1722 #define ASC_MC_DEFAULT_SEL_MASK 0x00B2
1723 #define ASC_MC_SDTR_DONE 0x00B6
1724 #define ASC_MC_NUMBER_OF_QUEUED_CMD 0x00C0
1725 #define ASC_MC_NUMBER_OF_MAX_CMD 0x00D0
1726 #define ASC_MC_DEVICE_HSHK_CFG_TABLE 0x0100
1727 #define ASC_MC_CONTROL_FLAG 0x0122 /* Microcode control flag. */
1728 #define ASC_MC_WDTR_DONE 0x0124
1729 #define ASC_MC_CAM_MODE_MASK 0x015E /* CAM mode TID bitmask. */
1730 #define ASC_MC_ICQ 0x0160
1731 #define ASC_MC_IRQ 0x0164
1732 #define ASC_MC_PPR_ABLE 0x017A
1735 * BIOS LRAM variable absolute offsets.
1737 #define BIOS_CODESEG 0x54
1738 #define BIOS_CODELEN 0x56
1739 #define BIOS_SIGNATURE 0x58
1740 #define BIOS_VERSION 0x5A
1743 * Microcode Control Flags
1745 * Flags set by the Adv Library in RISC variable 'control_flag' (0x122)
1746 * and handled by the microcode.
1748 #define CONTROL_FLAG_IGNORE_PERR 0x0001 /* Ignore DMA Parity Errors */
1749 #define CONTROL_FLAG_ENABLE_AIPP 0x0002 /* Enabled AIPP checking. */
1752 * ASC_MC_DEVICE_HSHK_CFG_TABLE microcode table or HSHK_CFG register format
1754 #define HSHK_CFG_WIDE_XFR 0x8000
1755 #define HSHK_CFG_RATE 0x0F00
1756 #define HSHK_CFG_OFFSET 0x001F
1758 #define ASC_DEF_MAX_HOST_QNG 0xFD /* Max. number of host commands (253) */
1759 #define ASC_DEF_MIN_HOST_QNG 0x10 /* Min. number of host commands (16) */
1760 #define ASC_DEF_MAX_DVC_QNG 0x3F /* Max. number commands per device (63) */
1761 #define ASC_DEF_MIN_DVC_QNG 0x04 /* Min. number commands per device (4) */
1763 #define ASC_QC_DATA_CHECK 0x01 /* Require ASC_QC_DATA_OUT set or clear. */
1764 #define ASC_QC_DATA_OUT 0x02 /* Data out DMA transfer. */
1765 #define ASC_QC_START_MOTOR 0x04 /* Send auto-start motor before request. */
1766 #define ASC_QC_NO_OVERRUN 0x08 /* Don't report overrun. */
1767 #define ASC_QC_FREEZE_TIDQ 0x10 /* Freeze TID queue after request. XXX TBD */
1769 #define ASC_QSC_NO_DISC 0x01 /* Don't allow disconnect for request. */
1770 #define ASC_QSC_NO_TAGMSG 0x02 /* Don't allow tag queuing for request. */
1771 #define ASC_QSC_NO_SYNC 0x04 /* Don't use Synch. transfer on request. */
1772 #define ASC_QSC_NO_WIDE 0x08 /* Don't use Wide transfer on request. */
1773 #define ASC_QSC_REDO_DTR 0x10 /* Renegotiate WDTR/SDTR before request. */
1775 * Note: If a Tag Message is to be sent and neither ASC_QSC_HEAD_TAG or
1776 * ASC_QSC_ORDERED_TAG is set, then a Simple Tag Message (0x20) is used.
1778 #define ASC_QSC_HEAD_TAG 0x40 /* Use Head Tag Message (0x21). */
1779 #define ASC_QSC_ORDERED_TAG 0x80 /* Use Ordered Tag Message (0x22). */
1782 * All fields here are accessed by the board microcode and need to be
1785 typedef struct adv_carr_t {
1786 ADV_VADDR carr_va; /* Carrier Virtual Address */
1787 ADV_PADDR carr_pa; /* Carrier Physical Address */
1788 ADV_VADDR areq_vpa; /* ASC_SCSI_REQ_Q Virtual or Physical Address */
1790 * next_vpa [31:4] Carrier Virtual or Physical Next Pointer
1792 * next_vpa [3:1] Reserved Bits
1793 * next_vpa [0] Done Flag set in Response Queue.
1799 * Mask used to eliminate low 4 bits of carrier 'next_vpa' field.
1801 #define ASC_NEXT_VPA_MASK 0xFFFFFFF0
1803 #define ASC_RQ_DONE 0x00000001
1804 #define ASC_RQ_GOOD 0x00000002
1805 #define ASC_CQ_STOPPER 0x00000000
1807 #define ASC_GET_CARRP(carrp) ((carrp) & ASC_NEXT_VPA_MASK)
1809 #define ADV_CARRIER_NUM_PAGE_CROSSING \
1810 (((ADV_CARRIER_COUNT * sizeof(ADV_CARR_T)) + \
1811 (ADV_PAGE_SIZE - 1))/ADV_PAGE_SIZE)
1813 #define ADV_CARRIER_BUFSIZE \
1814 ((ADV_CARRIER_COUNT + ADV_CARRIER_NUM_PAGE_CROSSING) * sizeof(ADV_CARR_T))
1817 * ASC_SCSI_REQ_Q 'a_flag' definitions
1819 * The Adv Library should limit use to the lower nibble (4 bits) of
1820 * a_flag. Drivers are free to use the upper nibble (4 bits) of a_flag.
1822 #define ADV_POLL_REQUEST 0x01 /* poll for request completion */
1823 #define ADV_SCSIQ_DONE 0x02 /* request done */
1824 #define ADV_DONT_RETRY 0x08 /* don't do retry */
1826 #define ADV_CHIP_ASC3550 0x01 /* Ultra-Wide IC */
1827 #define ADV_CHIP_ASC38C0800 0x02 /* Ultra2-Wide/LVD IC */
1828 #define ADV_CHIP_ASC38C1600 0x03 /* Ultra3-Wide/LVD2 IC */
1831 * Adapter temporary configuration structure
1833 * This structure can be discarded after initialization. Don't add
1834 * fields here needed after initialization.
1836 * Field naming convention:
1838 * *_enable indicates the field enables or disables a feature. The
1839 * value of the field is never reset.
1841 typedef struct adv_dvc_cfg {
1842 ushort disc_enable; /* enable disconnection */
1843 uchar chip_version; /* chip version */
1844 uchar termination; /* Term. Ctrl. bits 6-5 of SCSI_CFG1 register */
1845 ushort control_flag; /* Microcode Control Flag */
1846 ushort mcode_date; /* Microcode date */
1847 ushort mcode_version; /* Microcode version */
1848 ushort serial1; /* EEPROM serial number word 1 */
1849 ushort serial2; /* EEPROM serial number word 2 */
1850 ushort serial3; /* EEPROM serial number word 3 */
1854 struct adv_scsi_req_q;
1857 * Adapter operation variable structure.
1859 * One structure is required per host adapter.
1861 * Field naming convention:
1863 * *_able indicates both whether a feature should be enabled or disabled
1864 * and whether a device isi capable of the feature. At initialization
1865 * this field may be set, but later if a device is found to be incapable
1866 * of the feature, the field is cleared.
1868 typedef struct adv_dvc_var {
1869 AdvPortAddr iop_base; /* I/O port address */
1870 ushort err_code; /* fatal error code */
1871 ushort bios_ctrl; /* BIOS control word, EEPROM word 12 */
1872 ushort wdtr_able; /* try WDTR for a device */
1873 ushort sdtr_able; /* try SDTR for a device */
1874 ushort ultra_able; /* try SDTR Ultra speed for a device */
1875 ushort sdtr_speed1; /* EEPROM SDTR Speed for TID 0-3 */
1876 ushort sdtr_speed2; /* EEPROM SDTR Speed for TID 4-7 */
1877 ushort sdtr_speed3; /* EEPROM SDTR Speed for TID 8-11 */
1878 ushort sdtr_speed4; /* EEPROM SDTR Speed for TID 12-15 */
1879 ushort tagqng_able; /* try tagged queuing with a device */
1880 ushort ppr_able; /* PPR message capable per TID bitmask. */
1881 uchar max_dvc_qng; /* maximum number of tagged commands per device */
1882 ushort start_motor; /* start motor command allowed */
1883 uchar scsi_reset_wait; /* delay in seconds after scsi bus reset */
1884 uchar chip_no; /* should be assigned by caller */
1885 uchar max_host_qng; /* maximum number of Q'ed command allowed */
1886 ushort no_scam; /* scam_tolerant of EEPROM */
1887 struct asc_board *drv_ptr; /* driver pointer to private structure */
1888 uchar chip_scsi_id; /* chip SCSI target ID */
1890 uchar bist_err_code;
1891 ADV_CARR_T *carrier_buf;
1892 ADV_CARR_T *carr_freelist; /* Carrier free list. */
1893 ADV_CARR_T *icq_sp; /* Initiator command queue stopper pointer. */
1894 ADV_CARR_T *irq_sp; /* Initiator response queue stopper pointer. */
1895 ushort carr_pending_cnt; /* Count of pending carriers. */
1897 * Note: The following fields will not be used after initialization. The
1898 * driver may discard the buffer after initialization is done.
1900 ADV_DVC_CFG *cfg; /* temporary configuration structure */
1903 #define NO_OF_SG_PER_BLOCK 15
1905 typedef struct asc_sg_block {
1909 uchar sg_cnt; /* Valid entries in block. */
1910 ADV_PADDR sg_ptr; /* Pointer to next sg block. */
1912 ADV_PADDR sg_addr; /* SG element address. */
1913 ADV_DCNT sg_count; /* SG element count. */
1914 } sg_list[NO_OF_SG_PER_BLOCK];
1918 * ADV_SCSI_REQ_Q - microcode request structure
1920 * All fields in this structure up to byte 60 are used by the microcode.
1921 * The microcode makes assumptions about the size and ordering of fields
1922 * in this structure. Do not change the structure definition here without
1923 * coordinating the change with the microcode.
1925 * All fields accessed by microcode must be maintained in little_endian
1928 typedef struct adv_scsi_req_q {
1929 uchar cntl; /* Ucode flags and state (ASC_MC_QC_*). */
1931 uchar target_id; /* Device target identifier. */
1932 uchar target_lun; /* Device target logical unit number. */
1933 ADV_PADDR data_addr; /* Data buffer physical address. */
1934 ADV_DCNT data_cnt; /* Data count. Ucode sets to residual. */
1935 ADV_PADDR sense_addr;
1939 uchar cdb_len; /* SCSI CDB length. Must <= 16 bytes. */
1941 uchar done_status; /* Completion status. */
1942 uchar scsi_status; /* SCSI status byte. */
1943 uchar host_status; /* Ucode host status. */
1944 uchar sg_working_ix;
1945 uchar cdb[12]; /* SCSI CDB bytes 0-11. */
1946 ADV_PADDR sg_real_addr; /* SG list physical address. */
1947 ADV_PADDR scsiq_rptr;
1948 uchar cdb16[4]; /* SCSI CDB bytes 12-15. */
1949 ADV_VADDR scsiq_ptr;
1952 * End of microcode structure - 60 bytes. The rest of the structure
1953 * is used by the Adv Library and ignored by the microcode.
1956 ADV_SG_BLOCK *sg_list_ptr; /* SG list virtual address. */
1957 char *vdata_addr; /* Data buffer virtual address. */
1959 uchar pad[2]; /* Pad out to a word boundary. */
1963 * Microcode idle loop commands
1965 #define IDLE_CMD_COMPLETED 0
1966 #define IDLE_CMD_STOP_CHIP 0x0001
1967 #define IDLE_CMD_STOP_CHIP_SEND_INT 0x0002
1968 #define IDLE_CMD_SEND_INT 0x0004
1969 #define IDLE_CMD_ABORT 0x0008
1970 #define IDLE_CMD_DEVICE_RESET 0x0010
1971 #define IDLE_CMD_SCSI_RESET_START 0x0020 /* Assert SCSI Bus Reset */
1972 #define IDLE_CMD_SCSI_RESET_END 0x0040 /* Deassert SCSI Bus Reset */
1973 #define IDLE_CMD_SCSIREQ 0x0080
1975 #define IDLE_CMD_STATUS_SUCCESS 0x0001
1976 #define IDLE_CMD_STATUS_FAILURE 0x0002
1979 * AdvSendIdleCmd() flag definitions.
1981 #define ADV_NOWAIT 0x01
1984 * Wait loop time out values.
1986 #define SCSI_WAIT_100_MSEC 100UL /* 100 milliseconds */
1987 #define SCSI_US_PER_MSEC 1000 /* microseconds per millisecond */
1988 #define SCSI_MAX_RETRY 10 /* retry count */
1990 #define ADV_ASYNC_RDMA_FAILURE 0x01 /* Fatal RDMA failure. */
1991 #define ADV_ASYNC_SCSI_BUS_RESET_DET 0x02 /* Detected SCSI Bus Reset. */
1992 #define ADV_ASYNC_CARRIER_READY_FAILURE 0x03 /* Carrier Ready failure. */
1993 #define ADV_RDMA_IN_CARR_AND_Q_INVALID 0x04 /* RDMAed-in data invalid. */
1995 #define ADV_HOST_SCSI_BUS_RESET 0x80 /* Host Initiated SCSI Bus Reset. */
1997 /* Read byte from a register. */
1998 #define AdvReadByteRegister(iop_base, reg_off) \
1999 (ADV_MEM_READB((iop_base) + (reg_off)))
2001 /* Write byte to a register. */
2002 #define AdvWriteByteRegister(iop_base, reg_off, byte) \
2003 (ADV_MEM_WRITEB((iop_base) + (reg_off), (byte)))
2005 /* Read word (2 bytes) from a register. */
2006 #define AdvReadWordRegister(iop_base, reg_off) \
2007 (ADV_MEM_READW((iop_base) + (reg_off)))
2009 /* Write word (2 bytes) to a register. */
2010 #define AdvWriteWordRegister(iop_base, reg_off, word) \
2011 (ADV_MEM_WRITEW((iop_base) + (reg_off), (word)))
2013 /* Write dword (4 bytes) to a register. */
2014 #define AdvWriteDWordRegister(iop_base, reg_off, dword) \
2015 (ADV_MEM_WRITEDW((iop_base) + (reg_off), (dword)))
2017 /* Read byte from LRAM. */
2018 #define AdvReadByteLram(iop_base, addr, byte) \
2020 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
2021 (byte) = ADV_MEM_READB((iop_base) + IOPB_RAM_DATA); \
2024 /* Write byte to LRAM. */
2025 #define AdvWriteByteLram(iop_base, addr, byte) \
2026 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
2027 ADV_MEM_WRITEB((iop_base) + IOPB_RAM_DATA, (byte)))
2029 /* Read word (2 bytes) from LRAM. */
2030 #define AdvReadWordLram(iop_base, addr, word) \
2032 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
2033 (word) = (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA)); \
2036 /* Write word (2 bytes) to LRAM. */
2037 #define AdvWriteWordLram(iop_base, addr, word) \
2038 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
2039 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
2041 /* Write little-endian double word (4 bytes) to LRAM */
2042 /* Because of unspecified C language ordering don't use auto-increment. */
2043 #define AdvWriteDWordLramNoSwap(iop_base, addr, dword) \
2044 ((ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
2045 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
2046 cpu_to_le16((ushort) ((dword) & 0xFFFF)))), \
2047 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr) + 2), \
2048 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
2049 cpu_to_le16((ushort) ((dword >> 16) & 0xFFFF)))))
2051 /* Read word (2 bytes) from LRAM assuming that the address is already set. */
2052 #define AdvReadWordAutoIncLram(iop_base) \
2053 (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA))
2055 /* Write word (2 bytes) to LRAM assuming that the address is already set. */
2056 #define AdvWriteWordAutoIncLram(iop_base, word) \
2057 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
2060 * Define macro to check for Condor signature.
2062 * Evaluate to ADV_TRUE if a Condor chip is found the specified port
2063 * address 'iop_base'. Otherwise evalue to ADV_FALSE.
2065 #define AdvFindSignature(iop_base) \
2066 (((AdvReadByteRegister((iop_base), IOPB_CHIP_ID_1) == \
2067 ADV_CHIP_ID_BYTE) && \
2068 (AdvReadWordRegister((iop_base), IOPW_CHIP_ID_0) == \
2069 ADV_CHIP_ID_WORD)) ? ADV_TRUE : ADV_FALSE)
2072 * Define macro to Return the version number of the chip at 'iop_base'.
2074 * The second parameter 'bus_type' is currently unused.
2076 #define AdvGetChipVersion(iop_base, bus_type) \
2077 AdvReadByteRegister((iop_base), IOPB_CHIP_TYPE_REV)
2080 * Abort an SRB in the chip's RISC Memory. The 'srb_ptr' argument must
2081 * match the ASC_SCSI_REQ_Q 'srb_ptr' field.
2083 * If the request has not yet been sent to the device it will simply be
2084 * aborted from RISC memory. If the request is disconnected it will be
2085 * aborted on reselection by sending an Abort Message to the target ID.
2088 * ADV_TRUE(1) - Queue was successfully aborted.
2089 * ADV_FALSE(0) - Queue was not found on the active queue list.
2091 #define AdvAbortQueue(asc_dvc, scsiq) \
2092 AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_ABORT, \
2096 * Send a Bus Device Reset Message to the specified target ID.
2098 * All outstanding commands will be purged if sending the
2099 * Bus Device Reset Message is successful.
2102 * ADV_TRUE(1) - All requests on the target are purged.
2103 * ADV_FALSE(0) - Couldn't issue Bus Device Reset Message; Requests
2106 #define AdvResetDevice(asc_dvc, target_id) \
2107 AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_DEVICE_RESET, \
2108 (ADV_DCNT) (target_id))
2111 * SCSI Wide Type definition.
2113 #define ADV_SCSI_BIT_ID_TYPE ushort
2116 * AdvInitScsiTarget() 'cntl_flag' options.
2118 #define ADV_SCAN_LUN 0x01
2119 #define ADV_CAPINFO_NOLUN 0x02
2122 * Convert target id to target id bit mask.
2124 #define ADV_TID_TO_TIDMASK(tid) (0x01 << ((tid) & ADV_MAX_TID))
2127 * ASC_SCSI_REQ_Q 'done_status' and 'host_status' return values.
2130 #define QD_NO_STATUS 0x00 /* Request not completed yet. */
2131 #define QD_NO_ERROR 0x01
2132 #define QD_ABORTED_BY_HOST 0x02
2133 #define QD_WITH_ERROR 0x04
2135 #define QHSTA_NO_ERROR 0x00
2136 #define QHSTA_M_SEL_TIMEOUT 0x11
2137 #define QHSTA_M_DATA_OVER_RUN 0x12
2138 #define QHSTA_M_UNEXPECTED_BUS_FREE 0x13
2139 #define QHSTA_M_QUEUE_ABORTED 0x15
2140 #define QHSTA_M_SXFR_SDMA_ERR 0x16 /* SXFR_STATUS SCSI DMA Error */
2141 #define QHSTA_M_SXFR_SXFR_PERR 0x17 /* SXFR_STATUS SCSI Bus Parity Error */
2142 #define QHSTA_M_RDMA_PERR 0x18 /* RISC PCI DMA parity error */
2143 #define QHSTA_M_SXFR_OFF_UFLW 0x19 /* SXFR_STATUS Offset Underflow */
2144 #define QHSTA_M_SXFR_OFF_OFLW 0x20 /* SXFR_STATUS Offset Overflow */
2145 #define QHSTA_M_SXFR_WD_TMO 0x21 /* SXFR_STATUS Watchdog Timeout */
2146 #define QHSTA_M_SXFR_DESELECTED 0x22 /* SXFR_STATUS Deselected */
2147 /* Note: QHSTA_M_SXFR_XFR_OFLW is identical to QHSTA_M_DATA_OVER_RUN. */
2148 #define QHSTA_M_SXFR_XFR_OFLW 0x12 /* SXFR_STATUS Transfer Overflow */
2149 #define QHSTA_M_SXFR_XFR_PH_ERR 0x24 /* SXFR_STATUS Transfer Phase Error */
2150 #define QHSTA_M_SXFR_UNKNOWN_ERROR 0x25 /* SXFR_STATUS Unknown Error */
2151 #define QHSTA_M_SCSI_BUS_RESET 0x30 /* Request aborted from SBR */
2152 #define QHSTA_M_SCSI_BUS_RESET_UNSOL 0x31 /* Request aborted from unsol. SBR */
2153 #define QHSTA_M_BUS_DEVICE_RESET 0x32 /* Request aborted from BDR */
2154 #define QHSTA_M_DIRECTION_ERR 0x35 /* Data Phase mismatch */
2155 #define QHSTA_M_DIRECTION_ERR_HUNG 0x36 /* Data Phase mismatch and bus hang */
2156 #define QHSTA_M_WTM_TIMEOUT 0x41
2157 #define QHSTA_M_BAD_CMPL_STATUS_IN 0x42
2158 #define QHSTA_M_NO_AUTO_REQ_SENSE 0x43
2159 #define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
2160 #define QHSTA_M_INVALID_DEVICE 0x45 /* Bad target ID */
2161 #define QHSTA_M_FROZEN_TIDQ 0x46 /* TID Queue frozen. */
2162 #define QHSTA_M_SGBACKUP_ERROR 0x47 /* Scatter-Gather backup error */
2165 * DvcGetPhyAddr() flag arguments
2167 #define ADV_IS_SCSIQ_FLAG 0x01 /* 'addr' is ASC_SCSI_REQ_Q pointer */
2168 #define ADV_ASCGETSGLIST_VADDR 0x02 /* 'addr' is AscGetSGList() virtual addr */
2169 #define ADV_IS_SENSE_FLAG 0x04 /* 'addr' is sense virtual pointer */
2170 #define ADV_IS_DATA_FLAG 0x08 /* 'addr' is data virtual pointer */
2171 #define ADV_IS_SGLIST_FLAG 0x10 /* 'addr' is sglist virtual pointer */
2172 #define ADV_IS_CARRIER_FLAG 0x20 /* 'addr' is ADV_CARR_T pointer */
2174 /* Return the address that is aligned at the next doubleword >= to 'addr'. */
2175 #define ADV_8BALIGN(addr) (((ulong) (addr) + 0x7) & ~0x7)
2176 #define ADV_16BALIGN(addr) (((ulong) (addr) + 0xF) & ~0xF)
2177 #define ADV_32BALIGN(addr) (((ulong) (addr) + 0x1F) & ~0x1F)
2180 * Total contiguous memory needed for driver SG blocks.
2182 * ADV_MAX_SG_LIST must be defined by a driver. It is the maximum
2183 * number of scatter-gather elements the driver supports in a
2187 #define ADV_SG_LIST_MAX_BYTE_SIZE \
2188 (sizeof(ADV_SG_BLOCK) * \
2189 ((ADV_MAX_SG_LIST + (NO_OF_SG_PER_BLOCK - 1))/NO_OF_SG_PER_BLOCK))
2191 /* struct asc_board flags */
2192 #define ASC_IS_WIDE_BOARD 0x04 /* AdvanSys Wide Board */
2194 #define ASC_NARROW_BOARD(boardp) (((boardp)->flags & ASC_IS_WIDE_BOARD) == 0)
2196 #define NO_ISA_DMA 0xff /* No ISA DMA Channel Used */
2198 #define ASC_INFO_SIZE 128 /* advansys_info() line size */
2200 #ifdef CONFIG_PROC_FS
2201 /* /proc/scsi/advansys/[0...] related definitions */
2202 #define ASC_PRTBUF_SIZE 2048
2203 #define ASC_PRTLINE_SIZE 160
2205 #define ASC_PRT_NEXT() \
2209 if (leftlen == 0) { \
2214 #endif /* CONFIG_PROC_FS */
2216 /* Asc Library return codes */
2219 #define ASC_NOERROR 1
2221 #define ASC_ERROR (-1)
2223 /* struct scsi_cmnd function return codes */
2224 #define STATUS_BYTE(byte) (byte)
2225 #define MSG_BYTE(byte) ((byte) << 8)
2226 #define HOST_BYTE(byte) ((byte) << 16)
2227 #define DRIVER_BYTE(byte) ((byte) << 24)
2229 #define ASC_STATS(shost, counter) ASC_STATS_ADD(shost, counter, 1)
2230 #ifndef ADVANSYS_STATS
2231 #define ASC_STATS_ADD(shost, counter, count)
2232 #else /* ADVANSYS_STATS */
2233 #define ASC_STATS_ADD(shost, counter, count) \
2234 (((struct asc_board *) shost_priv(shost))->asc_stats.counter += (count))
2235 #endif /* ADVANSYS_STATS */
2237 #define ASC_CEILING(val, unit) (((val) + ((unit) - 1))/(unit))
2239 /* If the result wraps when calculating tenths, return 0. */
2240 #define ASC_TENTHS(num, den) \
2241 (((10 * ((num)/(den))) > (((num) * 10)/(den))) ? \
2242 0 : ((((num) * 10)/(den)) - (10 * ((num)/(den)))))
2245 * Display a message to the console.
2247 #define ASC_PRINT(s) \
2249 printk("advansys: "); \
2253 #define ASC_PRINT1(s, a1) \
2255 printk("advansys: "); \
2256 printk((s), (a1)); \
2259 #define ASC_PRINT2(s, a1, a2) \
2261 printk("advansys: "); \
2262 printk((s), (a1), (a2)); \
2265 #define ASC_PRINT3(s, a1, a2, a3) \
2267 printk("advansys: "); \
2268 printk((s), (a1), (a2), (a3)); \
2271 #define ASC_PRINT4(s, a1, a2, a3, a4) \
2273 printk("advansys: "); \
2274 printk((s), (a1), (a2), (a3), (a4)); \
2277 #ifndef ADVANSYS_DEBUG
2279 #define ASC_DBG(lvl, s...)
2280 #define ASC_DBG_PRT_SCSI_HOST(lvl, s)
2281 #define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp)
2282 #define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
2283 #define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone)
2284 #define ADV_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
2285 #define ASC_DBG_PRT_HEX(lvl, name, start, length)
2286 #define ASC_DBG_PRT_CDB(lvl, cdb, len)
2287 #define ASC_DBG_PRT_SENSE(lvl, sense, len)
2288 #define ASC_DBG_PRT_INQUIRY(lvl, inq, len)
2290 #else /* ADVANSYS_DEBUG */
2293 * Debugging Message Levels:
2295 * 1: High-Level Tracing
2296 * 2-N: Verbose Tracing
2299 #define ASC_DBG(lvl, format, arg...) { \
2300 if (asc_dbglvl >= (lvl)) \
2301 printk(KERN_DEBUG "%s: %s: " format, DRV_NAME, \
2302 __FUNCTION__ , ## arg); \
2305 #define ASC_DBG_PRT_SCSI_HOST(lvl, s) \
2307 if (asc_dbglvl >= (lvl)) { \
2308 asc_prt_scsi_host(s); \
2312 #define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp) \
2314 if (asc_dbglvl >= (lvl)) { \
2315 asc_prt_asc_scsi_q(scsiqp); \
2319 #define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone) \
2321 if (asc_dbglvl >= (lvl)) { \
2322 asc_prt_asc_qdone_info(qdone); \
2326 #define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp) \
2328 if (asc_dbglvl >= (lvl)) { \
2329 asc_prt_adv_scsi_req_q(scsiqp); \
2333 #define ASC_DBG_PRT_HEX(lvl, name, start, length) \
2335 if (asc_dbglvl >= (lvl)) { \
2336 asc_prt_hex((name), (start), (length)); \
2340 #define ASC_DBG_PRT_CDB(lvl, cdb, len) \
2341 ASC_DBG_PRT_HEX((lvl), "CDB", (uchar *) (cdb), (len));
2343 #define ASC_DBG_PRT_SENSE(lvl, sense, len) \
2344 ASC_DBG_PRT_HEX((lvl), "SENSE", (uchar *) (sense), (len));
2346 #define ASC_DBG_PRT_INQUIRY(lvl, inq, len) \
2347 ASC_DBG_PRT_HEX((lvl), "INQUIRY", (uchar *) (inq), (len));
2348 #endif /* ADVANSYS_DEBUG */
2350 #ifdef ADVANSYS_STATS
2352 /* Per board statistics structure */
2354 /* Driver Entrypoint Statistics */
2355 ADV_DCNT queuecommand; /* # calls to advansys_queuecommand() */
2356 ADV_DCNT reset; /* # calls to advansys_eh_bus_reset() */
2357 ADV_DCNT biosparam; /* # calls to advansys_biosparam() */
2358 ADV_DCNT interrupt; /* # advansys_interrupt() calls */
2359 ADV_DCNT callback; /* # calls to asc/adv_isr_callback() */
2360 ADV_DCNT done; /* # calls to request's scsi_done function */
2361 ADV_DCNT build_error; /* # asc/adv_build_req() ASC_ERROR returns. */
2362 ADV_DCNT adv_build_noreq; /* # adv_build_req() adv_req_t alloc. fail. */
2363 ADV_DCNT adv_build_nosg; /* # adv_build_req() adv_sgblk_t alloc. fail. */
2364 /* AscExeScsiQueue()/AdvExeScsiQueue() Statistics */
2365 ADV_DCNT exe_noerror; /* # ASC_NOERROR returns. */
2366 ADV_DCNT exe_busy; /* # ASC_BUSY returns. */
2367 ADV_DCNT exe_error; /* # ASC_ERROR returns. */
2368 ADV_DCNT exe_unknown; /* # unknown returns. */
2369 /* Data Transfer Statistics */
2370 ADV_DCNT cont_cnt; /* # non-scatter-gather I/O requests received */
2371 ADV_DCNT cont_xfer; /* # contiguous transfer 512-bytes */
2372 ADV_DCNT sg_cnt; /* # scatter-gather I/O requests received */
2373 ADV_DCNT sg_elem; /* # scatter-gather elements */
2374 ADV_DCNT sg_xfer; /* # scatter-gather transfer 512-bytes */
2376 #endif /* ADVANSYS_STATS */
2379 * Adv Library Request Structures
2381 * The following two structures are used to process Wide Board requests.
2383 * The ADV_SCSI_REQ_Q structure in adv_req_t is passed to the Adv Library
2384 * and microcode with the ADV_SCSI_REQ_Q field 'srb_ptr' pointing to the
2385 * adv_req_t. The adv_req_t structure 'cmndp' field in turn points to the
2386 * Mid-Level SCSI request structure.
2388 * Zero or more ADV_SG_BLOCK are used with each ADV_SCSI_REQ_Q. Each
2389 * ADV_SG_BLOCK structure holds 15 scatter-gather elements. Under Linux
2390 * up to 255 scatter-gather elements may be used per request or
2393 * Both structures must be 32 byte aligned.
2395 typedef struct adv_sgblk {
2396 ADV_SG_BLOCK sg_block; /* Sgblock structure. */
2397 uchar align[32]; /* Sgblock structure padding. */
2398 struct adv_sgblk *next_sgblkp; /* Next scatter-gather structure. */
2401 typedef struct adv_req {
2402 ADV_SCSI_REQ_Q scsi_req_q; /* Adv Library request structure. */
2403 uchar align[32]; /* Request structure padding. */
2404 struct scsi_cmnd *cmndp; /* Mid-Level SCSI command pointer. */
2405 adv_sgblk_t *sgblkp; /* Adv Library scatter-gather pointer. */
2406 struct adv_req *next_reqp; /* Next Request Structure. */
2410 * Structure allocated for each board.
2412 * This structure is allocated by scsi_host_alloc() at the end
2413 * of the 'Scsi_Host' structure starting at the 'hostdata'
2414 * field. It is guaranteed to be allocated from DMA-able memory.
2418 uint flags; /* Board flags */
2421 ASC_DVC_VAR asc_dvc_var; /* Narrow board */
2422 ADV_DVC_VAR adv_dvc_var; /* Wide board */
2425 ASC_DVC_CFG asc_dvc_cfg; /* Narrow board */
2426 ADV_DVC_CFG adv_dvc_cfg; /* Wide board */
2428 ushort asc_n_io_port; /* Number I/O ports. */
2429 ADV_SCSI_BIT_ID_TYPE init_tidmask; /* Target init./valid mask */
2430 ushort reqcnt[ADV_MAX_TID + 1]; /* Starvation request count */
2431 ADV_SCSI_BIT_ID_TYPE queue_full; /* Queue full mask */
2432 ushort queue_full_cnt[ADV_MAX_TID + 1]; /* Queue full count */
2434 ASCEEP_CONFIG asc_eep; /* Narrow EEPROM config. */
2435 ADVEEP_3550_CONFIG adv_3550_eep; /* 3550 EEPROM config. */
2436 ADVEEP_38C0800_CONFIG adv_38C0800_eep; /* 38C0800 EEPROM config. */
2437 ADVEEP_38C1600_CONFIG adv_38C1600_eep; /* 38C1600 EEPROM config. */
2439 ulong last_reset; /* Saved last reset time */
2440 /* /proc/scsi/advansys/[0...] */
2441 char *prtbuf; /* /proc print buffer */
2442 #ifdef ADVANSYS_STATS
2443 struct asc_stats asc_stats; /* Board statistics */
2444 #endif /* ADVANSYS_STATS */
2446 * The following fields are used only for Narrow Boards.
2448 uchar sdtr_data[ASC_MAX_TID + 1]; /* SDTR information */
2450 * The following fields are used only for Wide Boards.
2452 void __iomem *ioremap_addr; /* I/O Memory remap address. */
2453 ushort ioport; /* I/O Port address. */
2454 ADV_CARR_T *carrp; /* ADV_CARR_T memory block. */
2455 adv_req_t *orig_reqp; /* adv_req_t memory block. */
2456 adv_req_t *adv_reqp; /* Request structures. */
2457 adv_sgblk_t *adv_sgblkp; /* Scatter-gather structures. */
2458 ushort bios_signature; /* BIOS Signature. */
2459 ushort bios_version; /* BIOS Version. */
2460 ushort bios_codeseg; /* BIOS Code Segment. */
2461 ushort bios_codelen; /* BIOS Code Segment Length. */
2464 #define adv_dvc_to_board(adv_dvc) container_of(adv_dvc, struct asc_board, \
2465 dvc_var.adv_dvc_var)
2466 #define adv_dvc_to_pdev(adv_dvc) to_pci_dev(adv_dvc_to_board(adv_dvc)->dev)
2468 /* Overrun buffer used by all narrow boards. */
2469 static uchar overrun_buf[ASC_OVERRUN_BSIZE] = { 0 };
2471 #ifdef ADVANSYS_DEBUG
2472 static int asc_dbglvl = 3;
2475 * asc_prt_asc_dvc_var()
2477 static void asc_prt_asc_dvc_var(ASC_DVC_VAR *h)
2479 printk("ASC_DVC_VAR at addr 0x%lx\n", (ulong)h);
2481 printk(" iop_base 0x%x, err_code 0x%x, dvc_cntl 0x%x, bug_fix_cntl "
2482 "%d,\n", h->iop_base, h->err_code, h->dvc_cntl, h->bug_fix_cntl);
2484 printk(" bus_type %d, init_sdtr 0x%x,\n", h->bus_type,
2485 (unsigned)h->init_sdtr);
2487 printk(" sdtr_done 0x%x, use_tagged_qng 0x%x, unit_not_ready 0x%x, "
2488 "chip_no 0x%x,\n", (unsigned)h->sdtr_done,
2489 (unsigned)h->use_tagged_qng, (unsigned)h->unit_not_ready,
2490 (unsigned)h->chip_no);
2492 printk(" queue_full_or_busy 0x%x, start_motor 0x%x, scsi_reset_wait "
2493 "%u,\n", (unsigned)h->queue_full_or_busy,
2494 (unsigned)h->start_motor, (unsigned)h->scsi_reset_wait);
2496 printk(" is_in_int %u, max_total_qng %u, cur_total_qng %u, "
2497 "in_critical_cnt %u,\n", (unsigned)h->is_in_int,
2498 (unsigned)h->max_total_qng, (unsigned)h->cur_total_qng,
2499 (unsigned)h->in_critical_cnt);
2501 printk(" last_q_shortage %u, init_state 0x%x, no_scam 0x%x, "
2502 "pci_fix_asyn_xfer 0x%x,\n", (unsigned)h->last_q_shortage,
2503 (unsigned)h->init_state, (unsigned)h->no_scam,
2504 (unsigned)h->pci_fix_asyn_xfer);
2506 printk(" cfg 0x%lx\n", (ulong)h->cfg);
2510 * asc_prt_asc_dvc_cfg()
2512 static void asc_prt_asc_dvc_cfg(ASC_DVC_CFG *h)
2514 printk("ASC_DVC_CFG at addr 0x%lx\n", (ulong)h);
2516 printk(" can_tagged_qng 0x%x, cmd_qng_enabled 0x%x,\n",
2517 h->can_tagged_qng, h->cmd_qng_enabled);
2518 printk(" disc_enable 0x%x, sdtr_enable 0x%x,\n",
2519 h->disc_enable, h->sdtr_enable);
2521 printk(" chip_scsi_id %d, isa_dma_speed %d, isa_dma_channel %d, "
2522 "chip_version %d,\n", h->chip_scsi_id, h->isa_dma_speed,
2523 h->isa_dma_channel, h->chip_version);
2525 printk(" mcode_date 0x%x, mcode_version %d, overrun_buf 0x%p\n",
2526 h->mcode_date, h->mcode_version, h->overrun_buf);
2530 * asc_prt_adv_dvc_var()
2532 * Display an ADV_DVC_VAR structure.
2534 static void asc_prt_adv_dvc_var(ADV_DVC_VAR *h)
2536 printk(" ADV_DVC_VAR at addr 0x%lx\n", (ulong)h);
2538 printk(" iop_base 0x%lx, err_code 0x%x, ultra_able 0x%x\n",
2539 (ulong)h->iop_base, h->err_code, (unsigned)h->ultra_able);
2541 printk(" sdtr_able 0x%x, wdtr_able 0x%x\n",
2542 (unsigned)h->sdtr_able, (unsigned)h->wdtr_able);
2544 printk(" start_motor 0x%x, scsi_reset_wait 0x%x\n",
2545 (unsigned)h->start_motor, (unsigned)h->scsi_reset_wait);
2547 printk(" max_host_qng %u, max_dvc_qng %u, carr_freelist 0x%lxn\n",
2548 (unsigned)h->max_host_qng, (unsigned)h->max_dvc_qng,
2549 (ulong)h->carr_freelist);
2551 printk(" icq_sp 0x%lx, irq_sp 0x%lx\n",
2552 (ulong)h->icq_sp, (ulong)h->irq_sp);
2554 printk(" no_scam 0x%x, tagqng_able 0x%x\n",
2555 (unsigned)h->no_scam, (unsigned)h->tagqng_able);
2557 printk(" chip_scsi_id 0x%x, cfg 0x%lx\n",
2558 (unsigned)h->chip_scsi_id, (ulong)h->cfg);
2562 * asc_prt_adv_dvc_cfg()
2564 * Display an ADV_DVC_CFG structure.
2566 static void asc_prt_adv_dvc_cfg(ADV_DVC_CFG *h)
2568 printk(" ADV_DVC_CFG at addr 0x%lx\n", (ulong)h);
2570 printk(" disc_enable 0x%x, termination 0x%x\n",
2571 h->disc_enable, h->termination);
2573 printk(" chip_version 0x%x, mcode_date 0x%x\n",
2574 h->chip_version, h->mcode_date);
2576 printk(" mcode_version 0x%x, control_flag 0x%x\n",
2577 h->mcode_version, h->control_flag);
2581 * asc_prt_scsi_host()
2583 static void asc_prt_scsi_host(struct Scsi_Host *s)
2585 struct asc_board *boardp = shost_priv(s);
2587 printk("Scsi_Host at addr 0x%p, device %s\n", s, boardp->dev->bus_id);
2588 printk(" host_busy %u, host_no %d, last_reset %d,\n",
2589 s->host_busy, s->host_no, (unsigned)s->last_reset);
2591 printk(" base 0x%lx, io_port 0x%lx, irq %d,\n",
2592 (ulong)s->base, (ulong)s->io_port, boardp->irq);
2594 printk(" dma_channel %d, this_id %d, can_queue %d,\n",
2595 s->dma_channel, s->this_id, s->can_queue);
2597 printk(" cmd_per_lun %d, sg_tablesize %d, unchecked_isa_dma %d\n",
2598 s->cmd_per_lun, s->sg_tablesize, s->unchecked_isa_dma);
2600 if (ASC_NARROW_BOARD(boardp)) {
2601 asc_prt_asc_dvc_var(&boardp->dvc_var.asc_dvc_var);
2602 asc_prt_asc_dvc_cfg(&boardp->dvc_cfg.asc_dvc_cfg);
2604 asc_prt_adv_dvc_var(&boardp->dvc_var.adv_dvc_var);
2605 asc_prt_adv_dvc_cfg(&boardp->dvc_cfg.adv_dvc_cfg);
2612 * Print hexadecimal output in 4 byte groupings 32 bytes
2613 * or 8 double-words per line.
2615 static void asc_prt_hex(char *f, uchar *s, int l)
2622 printk("%s: (%d bytes)\n", f, l);
2624 for (i = 0; i < l; i += 32) {
2626 /* Display a maximum of 8 double-words per line. */
2627 if ((k = (l - i) / 4) >= 8) {
2634 for (j = 0; j < k; j++) {
2635 printk(" %2.2X%2.2X%2.2X%2.2X",
2636 (unsigned)s[i + (j * 4)],
2637 (unsigned)s[i + (j * 4) + 1],
2638 (unsigned)s[i + (j * 4) + 2],
2639 (unsigned)s[i + (j * 4) + 3]);
2647 printk(" %2.2X", (unsigned)s[i + (j * 4)]);
2650 printk(" %2.2X%2.2X",
2651 (unsigned)s[i + (j * 4)],
2652 (unsigned)s[i + (j * 4) + 1]);
2655 printk(" %2.2X%2.2X%2.2X",
2656 (unsigned)s[i + (j * 4) + 1],
2657 (unsigned)s[i + (j * 4) + 2],
2658 (unsigned)s[i + (j * 4) + 3]);
2667 * asc_prt_asc_scsi_q()
2669 static void asc_prt_asc_scsi_q(ASC_SCSI_Q *q)
2674 printk("ASC_SCSI_Q at addr 0x%lx\n", (ulong)q);
2677 (" target_ix 0x%x, target_lun %u, srb_ptr 0x%lx, tag_code 0x%x,\n",
2678 q->q2.target_ix, q->q1.target_lun, (ulong)q->q2.srb_ptr,
2682 (" data_addr 0x%lx, data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
2683 (ulong)le32_to_cpu(q->q1.data_addr),
2684 (ulong)le32_to_cpu(q->q1.data_cnt),
2685 (ulong)le32_to_cpu(q->q1.sense_addr), q->q1.sense_len);
2687 printk(" cdbptr 0x%lx, cdb_len %u, sg_head 0x%lx, sg_queue_cnt %u\n",
2688 (ulong)q->cdbptr, q->q2.cdb_len,
2689 (ulong)q->sg_head, q->q1.sg_queue_cnt);
2693 printk("ASC_SG_HEAD at addr 0x%lx\n", (ulong)sgp);
2694 printk(" entry_cnt %u, queue_cnt %u\n", sgp->entry_cnt,
2696 for (i = 0; i < sgp->entry_cnt; i++) {
2697 printk(" [%u]: addr 0x%lx, bytes %lu\n",
2698 i, (ulong)le32_to_cpu(sgp->sg_list[i].addr),
2699 (ulong)le32_to_cpu(sgp->sg_list[i].bytes));
2706 * asc_prt_asc_qdone_info()
2708 static void asc_prt_asc_qdone_info(ASC_QDONE_INFO *q)
2710 printk("ASC_QDONE_INFO at addr 0x%lx\n", (ulong)q);
2711 printk(" srb_ptr 0x%lx, target_ix %u, cdb_len %u, tag_code %u,\n",
2712 (ulong)q->d2.srb_ptr, q->d2.target_ix, q->d2.cdb_len,
2715 (" done_stat 0x%x, host_stat 0x%x, scsi_stat 0x%x, scsi_msg 0x%x\n",
2716 q->d3.done_stat, q->d3.host_stat, q->d3.scsi_stat, q->d3.scsi_msg);
2720 * asc_prt_adv_sgblock()
2722 * Display an ADV_SG_BLOCK structure.
2724 static void asc_prt_adv_sgblock(int sgblockno, ADV_SG_BLOCK *b)
2728 printk(" ASC_SG_BLOCK at addr 0x%lx (sgblockno %d)\n",
2729 (ulong)b, sgblockno);
2730 printk(" sg_cnt %u, sg_ptr 0x%lx\n",
2731 b->sg_cnt, (ulong)le32_to_cpu(b->sg_ptr));
2732 BUG_ON(b->sg_cnt > NO_OF_SG_PER_BLOCK);
2734 BUG_ON(b->sg_cnt != NO_OF_SG_PER_BLOCK);
2735 for (i = 0; i < b->sg_cnt; i++) {
2736 printk(" [%u]: sg_addr 0x%lx, sg_count 0x%lx\n",
2737 i, (ulong)b->sg_list[i].sg_addr,
2738 (ulong)b->sg_list[i].sg_count);
2743 * asc_prt_adv_scsi_req_q()
2745 * Display an ADV_SCSI_REQ_Q structure.
2747 static void asc_prt_adv_scsi_req_q(ADV_SCSI_REQ_Q *q)
2750 struct asc_sg_block *sg_ptr;
2752 printk("ADV_SCSI_REQ_Q at addr 0x%lx\n", (ulong)q);
2754 printk(" target_id %u, target_lun %u, srb_ptr 0x%lx, a_flag 0x%x\n",
2755 q->target_id, q->target_lun, (ulong)q->srb_ptr, q->a_flag);
2757 printk(" cntl 0x%x, data_addr 0x%lx, vdata_addr 0x%lx\n",
2758 q->cntl, (ulong)le32_to_cpu(q->data_addr), (ulong)q->vdata_addr);
2760 printk(" data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
2761 (ulong)le32_to_cpu(q->data_cnt),
2762 (ulong)le32_to_cpu(q->sense_addr), q->sense_len);
2765 (" cdb_len %u, done_status 0x%x, host_status 0x%x, scsi_status 0x%x\n",
2766 q->cdb_len, q->done_status, q->host_status, q->scsi_status);
2768 printk(" sg_working_ix 0x%x, target_cmd %u\n",
2769 q->sg_working_ix, q->target_cmd);
2771 printk(" scsiq_rptr 0x%lx, sg_real_addr 0x%lx, sg_list_ptr 0x%lx\n",
2772 (ulong)le32_to_cpu(q->scsiq_rptr),
2773 (ulong)le32_to_cpu(q->sg_real_addr), (ulong)q->sg_list_ptr);
2775 /* Display the request's ADV_SG_BLOCK structures. */
2776 if (q->sg_list_ptr != NULL) {
2780 * 'sg_ptr' is a physical address. Convert it to a virtual
2781 * address by indexing 'sg_blk_cnt' into the virtual address
2782 * array 'sg_list_ptr'.
2784 * XXX - Assumes all SG physical blocks are virtually contiguous.
2787 &(((ADV_SG_BLOCK *)(q->sg_list_ptr))[sg_blk_cnt]);
2788 asc_prt_adv_sgblock(sg_blk_cnt, sg_ptr);
2789 if (sg_ptr->sg_ptr == 0) {
2796 #endif /* ADVANSYS_DEBUG */
2801 * Return suitable for printing on the console with the argument
2802 * adapter's configuration information.
2804 * Note: The information line should not exceed ASC_INFO_SIZE bytes,
2805 * otherwise the static 'info' array will be overrun.
2807 static const char *advansys_info(struct Scsi_Host *shost)
2809 static char info[ASC_INFO_SIZE];
2810 struct asc_board *boardp = shost_priv(shost);
2811 ASC_DVC_VAR *asc_dvc_varp;
2812 ADV_DVC_VAR *adv_dvc_varp;
2814 char *widename = NULL;
2816 if (ASC_NARROW_BOARD(boardp)) {
2817 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
2818 ASC_DBG(1, "begin\n");
2819 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
2820 if ((asc_dvc_varp->bus_type & ASC_IS_ISAPNP) ==
2822 busname = "ISA PnP";
2827 "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X, DMA 0x%X",
2828 ASC_VERSION, busname,
2829 (ulong)shost->io_port,
2830 (ulong)shost->io_port + ASC_IOADR_GAP - 1,
2831 boardp->irq, shost->dma_channel);
2833 if (asc_dvc_varp->bus_type & ASC_IS_VL) {
2835 } else if (asc_dvc_varp->bus_type & ASC_IS_EISA) {
2837 } else if (asc_dvc_varp->bus_type & ASC_IS_PCI) {
2838 if ((asc_dvc_varp->bus_type & ASC_IS_PCI_ULTRA)
2839 == ASC_IS_PCI_ULTRA) {
2840 busname = "PCI Ultra";
2846 shost_printk(KERN_ERR, shost, "unknown bus "
2847 "type %d\n", asc_dvc_varp->bus_type);
2850 "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X",
2851 ASC_VERSION, busname, (ulong)shost->io_port,
2852 (ulong)shost->io_port + ASC_IOADR_GAP - 1,
2857 * Wide Adapter Information
2859 * Memory-mapped I/O is used instead of I/O space to access
2860 * the adapter, but display the I/O Port range. The Memory
2861 * I/O address is displayed through the driver /proc file.
2863 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
2864 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
2865 widename = "Ultra-Wide";
2866 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
2867 widename = "Ultra2-Wide";
2869 widename = "Ultra3-Wide";
2872 "AdvanSys SCSI %s: PCI %s: PCIMEM 0x%lX-0x%lX, IRQ 0x%X",
2873 ASC_VERSION, widename, (ulong)adv_dvc_varp->iop_base,
2874 (ulong)adv_dvc_varp->iop_base + boardp->asc_n_io_port - 1, boardp->irq);
2876 BUG_ON(strlen(info) >= ASC_INFO_SIZE);
2877 ASC_DBG(1, "end\n");
2881 #ifdef CONFIG_PROC_FS
2885 * If 'cp' is NULL print to the console, otherwise print to a buffer.
2887 * Return 0 if printing to the console, otherwise return the number of
2888 * bytes written to the buffer.
2890 * Note: If any single line is greater than ASC_PRTLINE_SIZE bytes the stack
2891 * will be corrupted. 's[]' is defined to be ASC_PRTLINE_SIZE bytes.
2893 static int asc_prt_line(char *buf, int buflen, char *fmt, ...)
2897 char s[ASC_PRTLINE_SIZE];
2899 va_start(args, fmt);
2900 ret = vsprintf(s, fmt, args);
2901 BUG_ON(ret >= ASC_PRTLINE_SIZE);
2906 ret = min(buflen, ret);
2907 memcpy(buf, s, ret);
2914 * asc_prt_board_devices()
2916 * Print driver information for devices attached to the board.
2918 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
2919 * cf. asc_prt_line().
2921 * Return the number of characters copied into 'cp'. No more than
2922 * 'cplen' characters will be copied to 'cp'.
2924 static int asc_prt_board_devices(struct Scsi_Host *shost, char *cp, int cplen)
2926 struct asc_board *boardp = shost_priv(shost);
2936 len = asc_prt_line(cp, leftlen,
2937 "\nDevice Information for AdvanSys SCSI Host %d:\n",
2941 if (ASC_NARROW_BOARD(boardp)) {
2942 chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
2944 chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
2947 len = asc_prt_line(cp, leftlen, "Target IDs Detected:");
2949 for (i = 0; i <= ADV_MAX_TID; i++) {
2950 if (boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) {
2951 len = asc_prt_line(cp, leftlen, " %X,", i);
2955 len = asc_prt_line(cp, leftlen, " (%X=Host Adapter)\n", chip_scsi_id);
2962 * Display Wide Board BIOS Information.
2964 static int asc_prt_adv_bios(struct Scsi_Host *shost, char *cp, int cplen)
2966 struct asc_board *boardp = shost_priv(shost);
2970 ushort major, minor, letter;
2975 len = asc_prt_line(cp, leftlen, "\nROM BIOS Version: ");
2979 * If the BIOS saved a valid signature, then fill in
2980 * the BIOS code segment base address.
2982 if (boardp->bios_signature != 0x55AA) {
2983 len = asc_prt_line(cp, leftlen, "Disabled or Pre-3.1\n");
2985 len = asc_prt_line(cp, leftlen,
2986 "BIOS either disabled or Pre-3.1. If it is pre-3.1, then a newer version\n");
2988 len = asc_prt_line(cp, leftlen,
2989 "can be found at the ConnectCom FTP site: ftp://ftp.connectcom.net/pub\n");
2992 major = (boardp->bios_version >> 12) & 0xF;
2993 minor = (boardp->bios_version >> 8) & 0xF;
2994 letter = (boardp->bios_version & 0xFF);
2996 len = asc_prt_line(cp, leftlen, "%d.%d%c\n",
2998 letter >= 26 ? '?' : letter + 'A');
3002 * Current available ROM BIOS release is 3.1I for UW
3003 * and 3.2I for U2W. This code doesn't differentiate
3004 * UW and U2W boards.
3006 if (major < 3 || (major <= 3 && minor < 1) ||
3007 (major <= 3 && minor <= 1 && letter < ('I' - 'A'))) {
3008 len = asc_prt_line(cp, leftlen,
3009 "Newer version of ROM BIOS is available at the ConnectCom FTP site:\n");
3011 len = asc_prt_line(cp, leftlen,
3012 "ftp://ftp.connectcom.net/pub\n");
3021 * Add serial number to information bar if signature AAh
3022 * is found in at bit 15-9 (7 bits) of word 1.
3024 * Serial Number consists fo 12 alpha-numeric digits.
3026 * 1 - Product type (A,B,C,D..) Word0: 15-13 (3 bits)
3027 * 2 - MFG Location (A,B,C,D..) Word0: 12-10 (3 bits)
3028 * 3-4 - Product ID (0-99) Word0: 9-0 (10 bits)
3029 * 5 - Product revision (A-J) Word0: " "
3031 * Signature Word1: 15-9 (7 bits)
3032 * 6 - Year (0-9) Word1: 8-6 (3 bits) & Word2: 15 (1 bit)
3033 * 7-8 - Week of the year (1-52) Word1: 5-0 (6 bits)
3035 * 9-12 - Serial Number (A001-Z999) Word2: 14-0 (15 bits)
3037 * Note 1: Only production cards will have a serial number.
3039 * Note 2: Signature is most significant 7 bits (0xFE).
3041 * Returns ASC_TRUE if serial number found, otherwise returns ASC_FALSE.
3043 static int asc_get_eeprom_string(ushort *serialnum, uchar *cp)
3047 if ((serialnum[1] & 0xFE00) != ((ushort)0xAA << 8)) {
3051 * First word - 6 digits.
3055 /* Product type - 1st digit. */
3056 if ((*cp = 'A' + ((w & 0xE000) >> 13)) == 'H') {
3057 /* Product type is P=Prototype */
3062 /* Manufacturing location - 2nd digit. */
3063 *cp++ = 'A' + ((w & 0x1C00) >> 10);
3065 /* Product ID - 3rd, 4th digits. */
3067 *cp++ = '0' + (num / 100);
3069 *cp++ = '0' + (num / 10);
3071 /* Product revision - 5th digit. */
3072 *cp++ = 'A' + (num % 10);
3082 * If bit 15 of third word is set, then the
3083 * last digit of the year is greater than 7.
3085 if (serialnum[2] & 0x8000) {
3086 *cp++ = '8' + ((w & 0x1C0) >> 6);
3088 *cp++ = '0' + ((w & 0x1C0) >> 6);
3091 /* Week of year - 7th, 8th digits. */
3093 *cp++ = '0' + num / 10;
3100 w = serialnum[2] & 0x7FFF;
3102 /* Serial number - 9th digit. */
3103 *cp++ = 'A' + (w / 1000);
3105 /* 10th, 11th, 12th digits. */
3107 *cp++ = '0' + num / 100;
3109 *cp++ = '0' + num / 10;
3113 *cp = '\0'; /* Null Terminate the string. */
3119 * asc_prt_asc_board_eeprom()
3121 * Print board EEPROM configuration.
3123 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
3124 * cf. asc_prt_line().
3126 * Return the number of characters copied into 'cp'. No more than
3127 * 'cplen' characters will be copied to 'cp'.
3129 static int asc_prt_asc_board_eeprom(struct Scsi_Host *shost, char *cp, int cplen)
3131 struct asc_board *boardp = shost_priv(shost);
3132 ASC_DVC_VAR *asc_dvc_varp;
3139 int isa_dma_speed[] = { 10, 8, 7, 6, 5, 4, 3, 2 };
3140 #endif /* CONFIG_ISA */
3141 uchar serialstr[13];
3143 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
3144 ep = &boardp->eep_config.asc_eep;
3149 len = asc_prt_line(cp, leftlen,
3150 "\nEEPROM Settings for AdvanSys SCSI Host %d:\n",
3154 if (asc_get_eeprom_string((ushort *)&ep->adapter_info[0], serialstr)
3157 asc_prt_line(cp, leftlen, " Serial Number: %s\n",
3161 if (ep->adapter_info[5] == 0xBB) {
3162 len = asc_prt_line(cp, leftlen,
3163 " Default Settings Used for EEPROM-less Adapter.\n");
3166 len = asc_prt_line(cp, leftlen,
3167 " Serial Number Signature Not Present.\n");
3172 len = asc_prt_line(cp, leftlen,
3173 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3174 ASC_EEP_GET_CHIP_ID(ep), ep->max_total_qng,
3178 len = asc_prt_line(cp, leftlen,
3179 " cntl 0x%x, no_scam 0x%x\n", ep->cntl, ep->no_scam);
3182 len = asc_prt_line(cp, leftlen, " Target ID: ");
3184 for (i = 0; i <= ASC_MAX_TID; i++) {
3185 len = asc_prt_line(cp, leftlen, " %d", i);
3188 len = asc_prt_line(cp, leftlen, "\n");
3191 len = asc_prt_line(cp, leftlen, " Disconnects: ");
3193 for (i = 0; i <= ASC_MAX_TID; i++) {
3194 len = asc_prt_line(cp, leftlen, " %c",
3196 disc_enable & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
3200 len = asc_prt_line(cp, leftlen, "\n");
3203 len = asc_prt_line(cp, leftlen, " Command Queuing: ");
3205 for (i = 0; i <= ASC_MAX_TID; i++) {
3206 len = asc_prt_line(cp, leftlen, " %c",
3208 use_cmd_qng & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
3212 len = asc_prt_line(cp, leftlen, "\n");
3215 len = asc_prt_line(cp, leftlen, " Start Motor: ");
3217 for (i = 0; i <= ASC_MAX_TID; i++) {
3218 len = asc_prt_line(cp, leftlen, " %c",
3220 start_motor & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
3224 len = asc_prt_line(cp, leftlen, "\n");
3227 len = asc_prt_line(cp, leftlen, " Synchronous Transfer:");
3229 for (i = 0; i <= ASC_MAX_TID; i++) {
3230 len = asc_prt_line(cp, leftlen, " %c",
3232 init_sdtr & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
3236 len = asc_prt_line(cp, leftlen, "\n");
3240 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
3241 len = asc_prt_line(cp, leftlen,
3242 " Host ISA DMA speed: %d MB/S\n",
3243 isa_dma_speed[ASC_EEP_GET_DMA_SPD(ep)]);
3246 #endif /* CONFIG_ISA */
3252 * asc_prt_adv_board_eeprom()
3254 * Print board EEPROM configuration.
3256 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
3257 * cf. asc_prt_line().
3259 * Return the number of characters copied into 'cp'. No more than
3260 * 'cplen' characters will be copied to 'cp'.
3262 static int asc_prt_adv_board_eeprom(struct Scsi_Host *shost, char *cp, int cplen)
3264 struct asc_board *boardp = shost_priv(shost);
3265 ADV_DVC_VAR *adv_dvc_varp;
3271 uchar serialstr[13];
3272 ADVEEP_3550_CONFIG *ep_3550 = NULL;
3273 ADVEEP_38C0800_CONFIG *ep_38C0800 = NULL;
3274 ADVEEP_38C1600_CONFIG *ep_38C1600 = NULL;
3277 ushort sdtr_speed = 0;
3279 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
3280 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3281 ep_3550 = &boardp->eep_config.adv_3550_eep;
3282 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3283 ep_38C0800 = &boardp->eep_config.adv_38C0800_eep;
3285 ep_38C1600 = &boardp->eep_config.adv_38C1600_eep;
3291 len = asc_prt_line(cp, leftlen,
3292 "\nEEPROM Settings for AdvanSys SCSI Host %d:\n",
3296 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3297 wordp = &ep_3550->serial_number_word1;
3298 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3299 wordp = &ep_38C0800->serial_number_word1;
3301 wordp = &ep_38C1600->serial_number_word1;
3304 if (asc_get_eeprom_string(wordp, serialstr) == ASC_TRUE) {
3306 asc_prt_line(cp, leftlen, " Serial Number: %s\n",
3310 len = asc_prt_line(cp, leftlen,
3311 " Serial Number Signature Not Present.\n");
3315 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3316 len = asc_prt_line(cp, leftlen,
3317 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3318 ep_3550->adapter_scsi_id,
3319 ep_3550->max_host_qng, ep_3550->max_dvc_qng);
3321 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3322 len = asc_prt_line(cp, leftlen,
3323 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3324 ep_38C0800->adapter_scsi_id,
3325 ep_38C0800->max_host_qng,
3326 ep_38C0800->max_dvc_qng);
3329 len = asc_prt_line(cp, leftlen,
3330 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3331 ep_38C1600->adapter_scsi_id,
3332 ep_38C1600->max_host_qng,
3333 ep_38C1600->max_dvc_qng);
3336 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3337 word = ep_3550->termination;
3338 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3339 word = ep_38C0800->termination_lvd;
3341 word = ep_38C1600->termination_lvd;
3345 termstr = "Low Off/High Off";
3348 termstr = "Low Off/High On";
3351 termstr = "Low On/High On";
3355 termstr = "Automatic";
3359 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3360 len = asc_prt_line(cp, leftlen,
3361 " termination: %u (%s), bios_ctrl: 0x%x\n",
3362 ep_3550->termination, termstr,
3363 ep_3550->bios_ctrl);
3365 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3366 len = asc_prt_line(cp, leftlen,
3367 " termination: %u (%s), bios_ctrl: 0x%x\n",
3368 ep_38C0800->termination_lvd, termstr,
3369 ep_38C0800->bios_ctrl);
3372 len = asc_prt_line(cp, leftlen,
3373 " termination: %u (%s), bios_ctrl: 0x%x\n",
3374 ep_38C1600->termination_lvd, termstr,
3375 ep_38C1600->bios_ctrl);
3379 len = asc_prt_line(cp, leftlen, " Target ID: ");
3381 for (i = 0; i <= ADV_MAX_TID; i++) {
3382 len = asc_prt_line(cp, leftlen, " %X", i);
3385 len = asc_prt_line(cp, leftlen, "\n");
3388 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3389 word = ep_3550->disc_enable;
3390 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3391 word = ep_38C0800->disc_enable;
3393 word = ep_38C1600->disc_enable;
3395 len = asc_prt_line(cp, leftlen, " Disconnects: ");
3397 for (i = 0; i <= ADV_MAX_TID; i++) {
3398 len = asc_prt_line(cp, leftlen, " %c",
3399 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3402 len = asc_prt_line(cp, leftlen, "\n");
3405 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3406 word = ep_3550->tagqng_able;
3407 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3408 word = ep_38C0800->tagqng_able;
3410 word = ep_38C1600->tagqng_able;
3412 len = asc_prt_line(cp, leftlen, " Command Queuing: ");
3414 for (i = 0; i <= ADV_MAX_TID; i++) {
3415 len = asc_prt_line(cp, leftlen, " %c",
3416 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3419 len = asc_prt_line(cp, leftlen, "\n");
3422 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3423 word = ep_3550->start_motor;
3424 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3425 word = ep_38C0800->start_motor;
3427 word = ep_38C1600->start_motor;
3429 len = asc_prt_line(cp, leftlen, " Start Motor: ");
3431 for (i = 0; i <= ADV_MAX_TID; i++) {
3432 len = asc_prt_line(cp, leftlen, " %c",
3433 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3436 len = asc_prt_line(cp, leftlen, "\n");
3439 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3440 len = asc_prt_line(cp, leftlen, " Synchronous Transfer:");
3442 for (i = 0; i <= ADV_MAX_TID; i++) {
3443 len = asc_prt_line(cp, leftlen, " %c",
3445 sdtr_able & ADV_TID_TO_TIDMASK(i)) ?
3449 len = asc_prt_line(cp, leftlen, "\n");
3453 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3454 len = asc_prt_line(cp, leftlen, " Ultra Transfer: ");
3456 for (i = 0; i <= ADV_MAX_TID; i++) {
3457 len = asc_prt_line(cp, leftlen, " %c",
3459 ultra_able & ADV_TID_TO_TIDMASK(i))
3463 len = asc_prt_line(cp, leftlen, "\n");
3467 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3468 word = ep_3550->wdtr_able;
3469 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3470 word = ep_38C0800->wdtr_able;
3472 word = ep_38C1600->wdtr_able;
3474 len = asc_prt_line(cp, leftlen, " Wide Transfer: ");
3476 for (i = 0; i <= ADV_MAX_TID; i++) {
3477 len = asc_prt_line(cp, leftlen, " %c",
3478 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3481 len = asc_prt_line(cp, leftlen, "\n");
3484 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800 ||
3485 adv_dvc_varp->chip_type == ADV_CHIP_ASC38C1600) {
3486 len = asc_prt_line(cp, leftlen,
3487 " Synchronous Transfer Speed (Mhz):\n ");
3489 for (i = 0; i <= ADV_MAX_TID; i++) {
3493 sdtr_speed = adv_dvc_varp->sdtr_speed1;
3494 } else if (i == 4) {
3495 sdtr_speed = adv_dvc_varp->sdtr_speed2;
3496 } else if (i == 8) {
3497 sdtr_speed = adv_dvc_varp->sdtr_speed3;
3498 } else if (i == 12) {
3499 sdtr_speed = adv_dvc_varp->sdtr_speed4;
3501 switch (sdtr_speed & ADV_MAX_TID) {
3524 len = asc_prt_line(cp, leftlen, "%X:%s ", i, speed_str);
3527 len = asc_prt_line(cp, leftlen, "\n ");
3532 len = asc_prt_line(cp, leftlen, "\n");
3540 * asc_prt_driver_conf()
3542 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
3543 * cf. asc_prt_line().
3545 * Return the number of characters copied into 'cp'. No more than
3546 * 'cplen' characters will be copied to 'cp'.
3548 static int asc_prt_driver_conf(struct Scsi_Host *shost, char *cp, int cplen)
3550 struct asc_board *boardp = shost_priv(shost);
3559 len = asc_prt_line(cp, leftlen,
3560 "\nLinux Driver Configuration and Information for AdvanSys SCSI Host %d:\n",
3564 len = asc_prt_line(cp, leftlen,
3565 " host_busy %u, last_reset %u, max_id %u, max_lun %u, max_channel %u\n",
3566 shost->host_busy, shost->last_reset, shost->max_id,
3567 shost->max_lun, shost->max_channel);
3570 len = asc_prt_line(cp, leftlen,
3571 " unique_id %d, can_queue %d, this_id %d, sg_tablesize %u, cmd_per_lun %u\n",
3572 shost->unique_id, shost->can_queue, shost->this_id,
3573 shost->sg_tablesize, shost->cmd_per_lun);
3576 len = asc_prt_line(cp, leftlen,
3577 " unchecked_isa_dma %d, use_clustering %d\n",
3578 shost->unchecked_isa_dma, shost->use_clustering);
3581 len = asc_prt_line(cp, leftlen,
3582 " flags 0x%x, last_reset 0x%x, jiffies 0x%x, asc_n_io_port 0x%x\n",
3583 boardp->flags, boardp->last_reset, jiffies,
3584 boardp->asc_n_io_port);
3587 len = asc_prt_line(cp, leftlen, " io_port 0x%x\n", shost->io_port);
3590 if (ASC_NARROW_BOARD(boardp)) {
3591 chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
3593 chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
3600 * asc_prt_asc_board_info()
3602 * Print dynamic board configuration information.
3604 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
3605 * cf. asc_prt_line().
3607 * Return the number of characters copied into 'cp'. No more than
3608 * 'cplen' characters will be copied to 'cp'.
3610 static int asc_prt_asc_board_info(struct Scsi_Host *shost, char *cp, int cplen)
3612 struct asc_board *boardp = shost_priv(shost);
3620 int renegotiate = 0;
3622 v = &boardp->dvc_var.asc_dvc_var;
3623 c = &boardp->dvc_cfg.asc_dvc_cfg;
3624 chip_scsi_id = c->chip_scsi_id;
3629 len = asc_prt_line(cp, leftlen,
3630 "\nAsc Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
3634 len = asc_prt_line(cp, leftlen, " chip_version %u, mcode_date 0x%x, "
3635 "mcode_version 0x%x, err_code %u\n",
3636 c->chip_version, c->mcode_date, c->mcode_version,
3640 /* Current number of commands waiting for the host. */
3641 len = asc_prt_line(cp, leftlen,
3642 " Total Command Pending: %d\n", v->cur_total_qng);
3645 len = asc_prt_line(cp, leftlen, " Command Queuing:");
3647 for (i = 0; i <= ASC_MAX_TID; i++) {
3648 if ((chip_scsi_id == i) ||
3649 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3652 len = asc_prt_line(cp, leftlen, " %X:%c",
3655 use_tagged_qng & ADV_TID_TO_TIDMASK(i)) ?
3659 len = asc_prt_line(cp, leftlen, "\n");
3662 /* Current number of commands waiting for a device. */
3663 len = asc_prt_line(cp, leftlen, " Command Queue Pending:");
3665 for (i = 0; i <= ASC_MAX_TID; i++) {
3666 if ((chip_scsi_id == i) ||
3667 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3670 len = asc_prt_line(cp, leftlen, " %X:%u", i, v->cur_dvc_qng[i]);
3673 len = asc_prt_line(cp, leftlen, "\n");
3676 /* Current limit on number of commands that can be sent to a device. */
3677 len = asc_prt_line(cp, leftlen, " Command Queue Limit:");
3679 for (i = 0; i <= ASC_MAX_TID; i++) {
3680 if ((chip_scsi_id == i) ||
3681 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3684 len = asc_prt_line(cp, leftlen, " %X:%u", i, v->max_dvc_qng[i]);
3687 len = asc_prt_line(cp, leftlen, "\n");
3690 /* Indicate whether the device has returned queue full status. */
3691 len = asc_prt_line(cp, leftlen, " Command Queue Full:");
3693 for (i = 0; i <= ASC_MAX_TID; i++) {
3694 if ((chip_scsi_id == i) ||
3695 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3698 if (boardp->queue_full & ADV_TID_TO_TIDMASK(i)) {
3699 len = asc_prt_line(cp, leftlen, " %X:Y-%d",
3700 i, boardp->queue_full_cnt[i]);
3702 len = asc_prt_line(cp, leftlen, " %X:N", i);
3706 len = asc_prt_line(cp, leftlen, "\n");
3709 len = asc_prt_line(cp, leftlen, " Synchronous Transfer:");
3711 for (i = 0; i <= ASC_MAX_TID; i++) {
3712 if ((chip_scsi_id == i) ||
3713 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3716 len = asc_prt_line(cp, leftlen, " %X:%c",
3719 sdtr_done & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
3723 len = asc_prt_line(cp, leftlen, "\n");
3726 for (i = 0; i <= ASC_MAX_TID; i++) {
3727 uchar syn_period_ix;
3729 if ((chip_scsi_id == i) ||
3730 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) ||
3731 ((v->init_sdtr & ADV_TID_TO_TIDMASK(i)) == 0)) {
3735 len = asc_prt_line(cp, leftlen, " %X:", i);
3738 if ((boardp->sdtr_data[i] & ASC_SYN_MAX_OFFSET) == 0) {
3739 len = asc_prt_line(cp, leftlen, " Asynchronous");
3743 (boardp->sdtr_data[i] >> 4) & (v->max_sdtr_index -
3746 len = asc_prt_line(cp, leftlen,
3747 " Transfer Period Factor: %d (%d.%d Mhz),",
3748 v->sdtr_period_tbl[syn_period_ix],
3750 v->sdtr_period_tbl[syn_period_ix],
3757 len = asc_prt_line(cp, leftlen, " REQ/ACK Offset: %d",
3759 sdtr_data[i] & ASC_SYN_MAX_OFFSET);
3763 if ((v->sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
3764 len = asc_prt_line(cp, leftlen, "*\n");
3767 len = asc_prt_line(cp, leftlen, "\n");
3773 len = asc_prt_line(cp, leftlen,
3774 " * = Re-negotiation pending before next command.\n");
3782 * asc_prt_adv_board_info()
3784 * Print dynamic board configuration information.
3786 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
3787 * cf. asc_prt_line().
3789 * Return the number of characters copied into 'cp'. No more than
3790 * 'cplen' characters will be copied to 'cp'.
3792 static int asc_prt_adv_board_info(struct Scsi_Host *shost, char *cp, int cplen)
3794 struct asc_board *boardp = shost_priv(shost);
3801 AdvPortAddr iop_base;
3802 ushort chip_scsi_id;
3806 ushort sdtr_able, wdtr_able;
3807 ushort wdtr_done, sdtr_done;
3809 int renegotiate = 0;
3811 v = &boardp->dvc_var.adv_dvc_var;
3812 c = &boardp->dvc_cfg.adv_dvc_cfg;
3813 iop_base = v->iop_base;
3814 chip_scsi_id = v->chip_scsi_id;
3819 len = asc_prt_line(cp, leftlen,
3820 "\nAdv Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
3824 len = asc_prt_line(cp, leftlen,
3825 " iop_base 0x%lx, cable_detect: %X, err_code %u\n",
3827 AdvReadWordRegister(iop_base,
3828 IOPW_SCSI_CFG1) & CABLE_DETECT,
3832 len = asc_prt_line(cp, leftlen, " chip_version %u, mcode_date 0x%x, "
3833 "mcode_version 0x%x\n", c->chip_version,
3834 c->mcode_date, c->mcode_version);
3837 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
3838 len = asc_prt_line(cp, leftlen, " Queuing Enabled:");
3840 for (i = 0; i <= ADV_MAX_TID; i++) {
3841 if ((chip_scsi_id == i) ||
3842 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3846 len = asc_prt_line(cp, leftlen, " %X:%c",
3848 (tagqng_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
3852 len = asc_prt_line(cp, leftlen, "\n");
3855 len = asc_prt_line(cp, leftlen, " Queue Limit:");
3857 for (i = 0; i <= ADV_MAX_TID; i++) {
3858 if ((chip_scsi_id == i) ||
3859 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3863 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + i,
3866 len = asc_prt_line(cp, leftlen, " %X:%d", i, lrambyte);
3869 len = asc_prt_line(cp, leftlen, "\n");
3872 len = asc_prt_line(cp, leftlen, " Command Pending:");
3874 for (i = 0; i <= ADV_MAX_TID; i++) {
3875 if ((chip_scsi_id == i) ||
3876 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3880 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_QUEUED_CMD + i,
3883 len = asc_prt_line(cp, leftlen, " %X:%d", i, lrambyte);
3886 len = asc_prt_line(cp, leftlen, "\n");
3889 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
3890 len = asc_prt_line(cp, leftlen, " Wide Enabled:");
3892 for (i = 0; i <= ADV_MAX_TID; i++) {
3893 if ((chip_scsi_id == i) ||
3894 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3898 len = asc_prt_line(cp, leftlen, " %X:%c",
3900 (wdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
3904 len = asc_prt_line(cp, leftlen, "\n");
3907 AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, wdtr_done);
3908 len = asc_prt_line(cp, leftlen, " Transfer Bit Width:");
3910 for (i = 0; i <= ADV_MAX_TID; i++) {
3911 if ((chip_scsi_id == i) ||
3912 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3916 AdvReadWordLram(iop_base,
3917 ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i),
3920 len = asc_prt_line(cp, leftlen, " %X:%d",
3921 i, (lramword & 0x8000) ? 16 : 8);
3924 if ((wdtr_able & ADV_TID_TO_TIDMASK(i)) &&
3925 (wdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
3926 len = asc_prt_line(cp, leftlen, "*");
3931 len = asc_prt_line(cp, leftlen, "\n");
3934 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
3935 len = asc_prt_line(cp, leftlen, " Synchronous Enabled:");
3937 for (i = 0; i <= ADV_MAX_TID; i++) {
3938 if ((chip_scsi_id == i) ||
3939 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3943 len = asc_prt_line(cp, leftlen, " %X:%c",
3945 (sdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
3949 len = asc_prt_line(cp, leftlen, "\n");
3952 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, sdtr_done);
3953 for (i = 0; i <= ADV_MAX_TID; i++) {
3955 AdvReadWordLram(iop_base,
3956 ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i),
3958 lramword &= ~0x8000;
3960 if ((chip_scsi_id == i) ||
3961 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) ||
3962 ((sdtr_able & ADV_TID_TO_TIDMASK(i)) == 0)) {
3966 len = asc_prt_line(cp, leftlen, " %X:", i);
3969 if ((lramword & 0x1F) == 0) { /* Check for REQ/ACK Offset 0. */
3970 len = asc_prt_line(cp, leftlen, " Asynchronous");
3974 asc_prt_line(cp, leftlen,
3975 " Transfer Period Factor: ");
3978 if ((lramword & 0x1F00) == 0x1100) { /* 80 Mhz */
3980 asc_prt_line(cp, leftlen, "9 (80.0 Mhz),");
3982 } else if ((lramword & 0x1F00) == 0x1000) { /* 40 Mhz */
3984 asc_prt_line(cp, leftlen, "10 (40.0 Mhz),");
3986 } else { /* 20 Mhz or below. */
3988 period = (((lramword >> 8) * 25) + 50) / 4;
3990 if (period == 0) { /* Should never happen. */
3992 asc_prt_line(cp, leftlen,
3996 len = asc_prt_line(cp, leftlen,
3998 period, 250 / period,
4005 len = asc_prt_line(cp, leftlen, " REQ/ACK Offset: %d",
4010 if ((sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
4011 len = asc_prt_line(cp, leftlen, "*\n");
4014 len = asc_prt_line(cp, leftlen, "\n");
4020 len = asc_prt_line(cp, leftlen,
4021 " * = Re-negotiation pending before next command.\n");
4031 * Copy proc information to a read buffer taking into account the current
4032 * read offset in the file and the remaining space in the read buffer.
4035 asc_proc_copy(off_t advoffset, off_t offset, char *curbuf, int leftlen,
4036 char *cp, int cplen)
4040 ASC_DBG(2, "offset %d, advoffset %d, cplen %d\n",
4041 (unsigned)offset, (unsigned)advoffset, cplen);
4042 if (offset <= advoffset) {
4043 /* Read offset below current offset, copy everything. */
4044 cnt = min(cplen, leftlen);
4045 ASC_DBG(2, "curbuf 0x%lx, cp 0x%lx, cnt %d\n",
4046 (ulong)curbuf, (ulong)cp, cnt);
4047 memcpy(curbuf, cp, cnt);
4048 } else if (offset < advoffset + cplen) {
4049 /* Read offset within current range, partial copy. */
4050 cnt = (advoffset + cplen) - offset;
4051 cp = (cp + cplen) - cnt;
4052 cnt = min(cnt, leftlen);
4053 ASC_DBG(2, "curbuf 0x%lx, cp 0x%lx, cnt %d\n",
4054 (ulong)curbuf, (ulong)cp, cnt);
4055 memcpy(curbuf, cp, cnt);
4060 #ifdef ADVANSYS_STATS
4062 * asc_prt_board_stats()
4064 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
4065 * cf. asc_prt_line().
4067 * Return the number of characters copied into 'cp'. No more than
4068 * 'cplen' characters will be copied to 'cp'.
4070 static int asc_prt_board_stats(struct Scsi_Host *shost, char *cp, int cplen)
4072 struct asc_board *boardp = shost_priv(shost);
4073 struct asc_stats *s = &boardp->asc_stats;
4075 int leftlen = cplen;
4076 int len, totlen = 0;
4078 len = asc_prt_line(cp, leftlen,
4079 "\nLinux Driver Statistics for AdvanSys SCSI Host %d:\n",
4083 len = asc_prt_line(cp, leftlen,
4084 " queuecommand %lu, reset %lu, biosparam %lu, interrupt %lu\n",
4085 s->queuecommand, s->reset, s->biosparam,
4089 len = asc_prt_line(cp, leftlen,
4090 " callback %lu, done %lu, build_error %lu, build_noreq %lu, build_nosg %lu\n",
4091 s->callback, s->done, s->build_error,
4092 s->adv_build_noreq, s->adv_build_nosg);
4095 len = asc_prt_line(cp, leftlen,
4096 " exe_noerror %lu, exe_busy %lu, exe_error %lu, exe_unknown %lu\n",
4097 s->exe_noerror, s->exe_busy, s->exe_error,
4102 * Display data transfer statistics.
4104 if (s->cont_cnt > 0) {
4105 len = asc_prt_line(cp, leftlen, " cont_cnt %lu, ", s->cont_cnt);
4108 len = asc_prt_line(cp, leftlen, "cont_xfer %lu.%01lu kb ",
4110 ASC_TENTHS(s->cont_xfer, 2));
4113 /* Contiguous transfer average size */
4114 len = asc_prt_line(cp, leftlen, "avg_xfer %lu.%01lu kb\n",
4115 (s->cont_xfer / 2) / s->cont_cnt,
4116 ASC_TENTHS((s->cont_xfer / 2), s->cont_cnt));
4120 if (s->sg_cnt > 0) {
4122 len = asc_prt_line(cp, leftlen, " sg_cnt %lu, sg_elem %lu, ",
4123 s->sg_cnt, s->sg_elem);
4126 len = asc_prt_line(cp, leftlen, "sg_xfer %lu.%01lu kb\n",
4127 s->sg_xfer / 2, ASC_TENTHS(s->sg_xfer, 2));
4130 /* Scatter gather transfer statistics */
4131 len = asc_prt_line(cp, leftlen, " avg_num_elem %lu.%01lu, ",
4132 s->sg_elem / s->sg_cnt,
4133 ASC_TENTHS(s->sg_elem, s->sg_cnt));
4136 len = asc_prt_line(cp, leftlen, "avg_elem_size %lu.%01lu kb, ",
4137 (s->sg_xfer / 2) / s->sg_elem,
4138 ASC_TENTHS((s->sg_xfer / 2), s->sg_elem));
4141 len = asc_prt_line(cp, leftlen, "avg_xfer_size %lu.%01lu kb\n",
4142 (s->sg_xfer / 2) / s->sg_cnt,
4143 ASC_TENTHS((s->sg_xfer / 2), s->sg_cnt));
4148 * Display request queuing statistics.
4150 len = asc_prt_line(cp, leftlen,
4151 " Active and Waiting Request Queues (Time Unit: %d HZ):\n",
4157 #endif /* ADVANSYS_STATS */
4160 * advansys_proc_info() - /proc/scsi/advansys/{0,1,2,3,...}
4162 * *buffer: I/O buffer
4163 * **start: if inout == FALSE pointer into buffer where user read should start
4164 * offset: current offset into a /proc/scsi/advansys/[0...] file
4165 * length: length of buffer
4166 * hostno: Scsi_Host host_no
4167 * inout: TRUE - user is writing; FALSE - user is reading
4169 * Return the number of bytes read from or written to a
4170 * /proc/scsi/advansys/[0...] file.
4172 * Note: This function uses the per board buffer 'prtbuf' which is
4173 * allocated when the board is initialized in advansys_detect(). The
4174 * buffer is ASC_PRTBUF_SIZE bytes. The function asc_proc_copy() is
4175 * used to write to the buffer. The way asc_proc_copy() is written
4176 * if 'prtbuf' is too small it will not be overwritten. Instead the
4177 * user just won't get all the available statistics.
4180 advansys_proc_info(struct Scsi_Host *shost, char *buffer, char **start,
4181 off_t offset, int length, int inout)
4183 struct asc_board *boardp = shost_priv(shost);
4192 ASC_DBG(1, "begin\n");
4195 * User write not supported.
4201 * User read of /proc/scsi/advansys/[0...] file.
4204 /* Copy read data starting at the beginning of the buffer. */
4212 * Get board configuration information.
4214 * advansys_info() returns the board string from its own static buffer.
4216 cp = (char *)advansys_info(shost);
4219 /* Copy board information. */
4220 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4224 ASC_DBG(1, "totcnt %d\n", totcnt);
4231 * Display Wide Board BIOS Information.
4233 if (!ASC_NARROW_BOARD(boardp)) {
4234 cp = boardp->prtbuf;
4235 cplen = asc_prt_adv_bios(shost, cp, ASC_PRTBUF_SIZE);
4236 BUG_ON(cplen >= ASC_PRTBUF_SIZE);
4237 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp,
4242 ASC_DBG(1, "totcnt %d\n", totcnt);
4250 * Display driver information for each device attached to the board.
4252 cp = boardp->prtbuf;
4253 cplen = asc_prt_board_devices(shost, cp, ASC_PRTBUF_SIZE);
4254 BUG_ON(cplen >= ASC_PRTBUF_SIZE);
4255 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4259 ASC_DBG(1, "totcnt %d\n", totcnt);
4266 * Display EEPROM configuration for the board.
4268 cp = boardp->prtbuf;
4269 if (ASC_NARROW_BOARD(boardp)) {
4270 cplen = asc_prt_asc_board_eeprom(shost, cp, ASC_PRTBUF_SIZE);
4272 cplen = asc_prt_adv_board_eeprom(shost, cp, ASC_PRTBUF_SIZE);
4274 BUG_ON(cplen >= ASC_PRTBUF_SIZE);
4275 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4279 ASC_DBG(1, "totcnt %d\n", totcnt);
4286 * Display driver configuration and information for the board.
4288 cp = boardp->prtbuf;
4289 cplen = asc_prt_driver_conf(shost, cp, ASC_PRTBUF_SIZE);
4290 BUG_ON(cplen >= ASC_PRTBUF_SIZE);
4291 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4295 ASC_DBG(1, "totcnt %d\n", totcnt);
4301 #ifdef ADVANSYS_STATS
4303 * Display driver statistics for the board.
4305 cp = boardp->prtbuf;
4306 cplen = asc_prt_board_stats(shost, cp, ASC_PRTBUF_SIZE);
4307 BUG_ON(cplen >= ASC_PRTBUF_SIZE);
4308 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4312 ASC_DBG(1, "totcnt %d\n", totcnt);
4317 #endif /* ADVANSYS_STATS */
4320 * Display Asc Library dynamic configuration information
4323 cp = boardp->prtbuf;
4324 if (ASC_NARROW_BOARD(boardp)) {
4325 cplen = asc_prt_asc_board_info(shost, cp, ASC_PRTBUF_SIZE);
4327 cplen = asc_prt_adv_board_info(shost, cp, ASC_PRTBUF_SIZE);
4329 BUG_ON(cplen >= ASC_PRTBUF_SIZE);
4330 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4334 ASC_DBG(1, "totcnt %d\n", totcnt);
4340 ASC_DBG(1, "totcnt %d\n", totcnt);
4344 #endif /* CONFIG_PROC_FS */
4346 static void asc_scsi_done(struct scsi_cmnd *scp)
4348 struct asc_board *boardp = shost_priv(scp->device->host);
4351 dma_unmap_sg(boardp->dev,
4352 (struct scatterlist *)scp->request_buffer,
4353 scp->use_sg, scp->sc_data_direction);
4354 else if (scp->request_bufflen)
4355 dma_unmap_single(boardp->dev, scp->SCp.dma_handle,
4356 scp->request_bufflen, scp->sc_data_direction);
4358 ASC_STATS(scp->device->host, done);
4360 scp->scsi_done(scp);
4363 static void AscSetBank(PortAddr iop_base, uchar bank)
4367 val = AscGetChipControl(iop_base) &
4369 (CC_SINGLE_STEP | CC_TEST | CC_DIAG | CC_SCSI_RESET |
4373 } else if (bank == 2) {
4374 val |= CC_DIAG | CC_BANK_ONE;
4376 val &= ~CC_BANK_ONE;
4378 AscSetChipControl(iop_base, val);
4381 static void AscSetChipIH(PortAddr iop_base, ushort ins_code)
4383 AscSetBank(iop_base, 1);
4384 AscWriteChipIH(iop_base, ins_code);
4385 AscSetBank(iop_base, 0);
4388 static int AscStartChip(PortAddr iop_base)
4390 AscSetChipControl(iop_base, 0);
4391 if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) {
4397 static int AscStopChip(PortAddr iop_base)
4402 AscGetChipControl(iop_base) &
4403 (~(CC_SINGLE_STEP | CC_TEST | CC_DIAG));
4404 AscSetChipControl(iop_base, (uchar)(cc_val | CC_HALT));
4405 AscSetChipIH(iop_base, INS_HALT);
4406 AscSetChipIH(iop_base, INS_RFLAG_WTM);
4407 if ((AscGetChipStatus(iop_base) & CSW_HALTED) == 0) {
4413 static int AscIsChipHalted(PortAddr iop_base)
4415 if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) {
4416 if ((AscGetChipControl(iop_base) & CC_HALT) != 0) {
4423 static int AscResetChipAndScsiBus(ASC_DVC_VAR *asc_dvc)
4428 iop_base = asc_dvc->iop_base;
4429 while ((AscGetChipStatus(iop_base) & CSW_SCSI_RESET_ACTIVE)
4433 AscStopChip(iop_base);
4434 AscSetChipControl(iop_base, CC_CHIP_RESET | CC_SCSI_RESET | CC_HALT);
4436 AscSetChipIH(iop_base, INS_RFLAG_WTM);
4437 AscSetChipIH(iop_base, INS_HALT);
4438 AscSetChipControl(iop_base, CC_CHIP_RESET | CC_HALT);
4439 AscSetChipControl(iop_base, CC_HALT);
4441 AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT);
4442 AscSetChipStatus(iop_base, 0);
4443 return (AscIsChipHalted(iop_base));
4446 static int AscFindSignature(PortAddr iop_base)
4450 ASC_DBG(1, "AscGetChipSignatureByte(0x%x) 0x%x\n",
4451 iop_base, AscGetChipSignatureByte(iop_base));
4452 if (AscGetChipSignatureByte(iop_base) == (uchar)ASC_1000_ID1B) {
4453 ASC_DBG(1, "AscGetChipSignatureWord(0x%x) 0x%x\n",
4454 iop_base, AscGetChipSignatureWord(iop_base));
4455 sig_word = AscGetChipSignatureWord(iop_base);
4456 if ((sig_word == (ushort)ASC_1000_ID0W) ||
4457 (sig_word == (ushort)ASC_1000_ID0W_FIX)) {
4464 static void AscEnableInterrupt(PortAddr iop_base)
4468 cfg = AscGetChipCfgLsw(iop_base);
4469 AscSetChipCfgLsw(iop_base, cfg | ASC_CFG0_HOST_INT_ON);
4472 static void AscDisableInterrupt(PortAddr iop_base)
4476 cfg = AscGetChipCfgLsw(iop_base);
4477 AscSetChipCfgLsw(iop_base, cfg & (~ASC_CFG0_HOST_INT_ON));
4480 static uchar AscReadLramByte(PortAddr iop_base, ushort addr)
4482 unsigned char byte_data;
4483 unsigned short word_data;
4485 if (isodd_word(addr)) {
4486 AscSetChipLramAddr(iop_base, addr - 1);
4487 word_data = AscGetChipLramData(iop_base);
4488 byte_data = (word_data >> 8) & 0xFF;
4490 AscSetChipLramAddr(iop_base, addr);
4491 word_data = AscGetChipLramData(iop_base);
4492 byte_data = word_data & 0xFF;
4497 static ushort AscReadLramWord(PortAddr iop_base, ushort addr)
4501 AscSetChipLramAddr(iop_base, addr);
4502 word_data = AscGetChipLramData(iop_base);
4506 #if CC_VERY_LONG_SG_LIST
4507 static ASC_DCNT AscReadLramDWord(PortAddr iop_base, ushort addr)
4509 ushort val_low, val_high;
4510 ASC_DCNT dword_data;
4512 AscSetChipLramAddr(iop_base, addr);
4513 val_low = AscGetChipLramData(iop_base);
4514 val_high = AscGetChipLramData(iop_base);
4515 dword_data = ((ASC_DCNT) val_high << 16) | (ASC_DCNT) val_low;
4516 return (dword_data);
4518 #endif /* CC_VERY_LONG_SG_LIST */
4521 AscMemWordSetLram(PortAddr iop_base, ushort s_addr, ushort set_wval, int words)
4525 AscSetChipLramAddr(iop_base, s_addr);
4526 for (i = 0; i < words; i++) {
4527 AscSetChipLramData(iop_base, set_wval);
4531 static void AscWriteLramWord(PortAddr iop_base, ushort addr, ushort word_val)
4533 AscSetChipLramAddr(iop_base, addr);
4534 AscSetChipLramData(iop_base, word_val);
4537 static void AscWriteLramByte(PortAddr iop_base, ushort addr, uchar byte_val)
4541 if (isodd_word(addr)) {
4543 word_data = AscReadLramWord(iop_base, addr);
4544 word_data &= 0x00FF;
4545 word_data |= (((ushort)byte_val << 8) & 0xFF00);
4547 word_data = AscReadLramWord(iop_base, addr);
4548 word_data &= 0xFF00;
4549 word_data |= ((ushort)byte_val & 0x00FF);
4551 AscWriteLramWord(iop_base, addr, word_data);
4555 * Copy 2 bytes to LRAM.
4557 * The source data is assumed to be in little-endian order in memory
4558 * and is maintained in little-endian order when written to LRAM.
4561 AscMemWordCopyPtrToLram(PortAddr iop_base,
4562 ushort s_addr, uchar *s_buffer, int words)
4566 AscSetChipLramAddr(iop_base, s_addr);
4567 for (i = 0; i < 2 * words; i += 2) {
4569 * On a little-endian system the second argument below
4570 * produces a little-endian ushort which is written to
4571 * LRAM in little-endian order. On a big-endian system
4572 * the second argument produces a big-endian ushort which
4573 * is "transparently" byte-swapped by outpw() and written
4574 * in little-endian order to LRAM.
4576 outpw(iop_base + IOP_RAM_DATA,
4577 ((ushort)s_buffer[i + 1] << 8) | s_buffer[i]);
4582 * Copy 4 bytes to LRAM.
4584 * The source data is assumed to be in little-endian order in memory
4585 * and is maintained in little-endian order when writen to LRAM.
4588 AscMemDWordCopyPtrToLram(PortAddr iop_base,
4589 ushort s_addr, uchar *s_buffer, int dwords)
4593 AscSetChipLramAddr(iop_base, s_addr);
4594 for (i = 0; i < 4 * dwords; i += 4) {
4595 outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 1] << 8) | s_buffer[i]); /* LSW */
4596 outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 3] << 8) | s_buffer[i + 2]); /* MSW */
4601 * Copy 2 bytes from LRAM.
4603 * The source data is assumed to be in little-endian order in LRAM
4604 * and is maintained in little-endian order when written to memory.
4607 AscMemWordCopyPtrFromLram(PortAddr iop_base,
4608 ushort s_addr, uchar *d_buffer, int words)
4613 AscSetChipLramAddr(iop_base, s_addr);
4614 for (i = 0; i < 2 * words; i += 2) {
4615 word = inpw(iop_base + IOP_RAM_DATA);
4616 d_buffer[i] = word & 0xff;
4617 d_buffer[i + 1] = (word >> 8) & 0xff;
4621 static ASC_DCNT AscMemSumLramWord(PortAddr iop_base, ushort s_addr, int words)
4627 for (i = 0; i < words; i++, s_addr += 2) {
4628 sum += AscReadLramWord(iop_base, s_addr);
4633 static ushort AscInitLram(ASC_DVC_VAR *asc_dvc)
4640 iop_base = asc_dvc->iop_base;
4642 AscMemWordSetLram(iop_base, ASC_QADR_BEG, 0,
4643 (ushort)(((int)(asc_dvc->max_total_qng + 2 + 1) *
4645 i = ASC_MIN_ACTIVE_QNO;
4646 s_addr = ASC_QADR_BEG + ASC_QBLK_SIZE;
4647 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
4649 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
4650 (uchar)(asc_dvc->max_total_qng));
4651 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
4654 s_addr += ASC_QBLK_SIZE;
4655 for (; i < asc_dvc->max_total_qng; i++, s_addr += ASC_QBLK_SIZE) {
4656 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
4658 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
4660 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
4663 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
4664 (uchar)ASC_QLINK_END);
4665 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
4666 (uchar)(asc_dvc->max_total_qng - 1));
4667 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
4668 (uchar)asc_dvc->max_total_qng);
4670 s_addr += ASC_QBLK_SIZE;
4671 for (; i <= (uchar)(asc_dvc->max_total_qng + 3);
4672 i++, s_addr += ASC_QBLK_SIZE) {
4673 AscWriteLramByte(iop_base,
4674 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_FWD), i);
4675 AscWriteLramByte(iop_base,
4676 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_BWD), i);
4677 AscWriteLramByte(iop_base,
4678 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_QNO), i);
4684 AscLoadMicroCode(PortAddr iop_base,
4685 ushort s_addr, uchar *mcode_buf, ushort mcode_size)
4688 ushort mcode_word_size;
4689 ushort mcode_chksum;
4691 /* Write the microcode buffer starting at LRAM address 0. */
4692 mcode_word_size = (ushort)(mcode_size >> 1);
4693 AscMemWordSetLram(iop_base, s_addr, 0, mcode_word_size);
4694 AscMemWordCopyPtrToLram(iop_base, s_addr, mcode_buf, mcode_word_size);
4696 chksum = AscMemSumLramWord(iop_base, s_addr, mcode_word_size);
4697 ASC_DBG(1, "chksum 0x%lx\n", (ulong)chksum);
4698 mcode_chksum = (ushort)AscMemSumLramWord(iop_base,
4699 (ushort)ASC_CODE_SEC_BEG,
4700 (ushort)((mcode_size -
4704 ASC_DBG(1, "mcode_chksum 0x%lx\n", (ulong)mcode_chksum);
4705 AscWriteLramWord(iop_base, ASCV_MCODE_CHKSUM_W, mcode_chksum);
4706 AscWriteLramWord(iop_base, ASCV_MCODE_SIZE_W, mcode_size);
4710 /* Microcode buffer is kept after initialization for error recovery. */
4711 static uchar _asc_mcode_buf[] = {
4712 0x01, 0x03, 0x01, 0x19, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
4713 0x00, 0x00, 0x00, 0x00, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F,
4714 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
4715 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
4716 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
4717 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC3, 0x12, 0x0D, 0x05,
4718 0x01, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
4719 0xFF, 0x80, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
4720 0x00, 0x00, 0x00, 0x23, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0xFF,
4721 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00,
4722 0x00, 0x00, 0xE4, 0x88, 0x00, 0x00, 0x00, 0x00, 0x80, 0x73, 0x48, 0x04,
4723 0x36, 0x00, 0x00, 0xA2, 0xC2, 0x00, 0x80, 0x73, 0x03, 0x23, 0x36, 0x40,
4724 0xB6, 0x00, 0x36, 0x00, 0x05, 0xD6, 0x0C, 0xD2, 0x12, 0xDA, 0x00, 0xA2,
4725 0xC2, 0x00, 0x92, 0x80, 0x1E, 0x98, 0x50, 0x00, 0xF5, 0x00, 0x48, 0x98,
4726 0xDF, 0x23, 0x36, 0x60, 0xB6, 0x00, 0x92, 0x80, 0x4F, 0x00, 0xF5, 0x00,
4727 0x48, 0x98, 0xEF, 0x23, 0x36, 0x60, 0xB6, 0x00, 0x92, 0x80, 0x80, 0x62,
4728 0x92, 0x80, 0x00, 0x46, 0x15, 0xEE, 0x13, 0xEA, 0x02, 0x01, 0x09, 0xD8,
4729 0xCD, 0x04, 0x4D, 0x00, 0x00, 0xA3, 0xD6, 0x00, 0xA6, 0x97, 0x7F, 0x23,
4730 0x04, 0x61, 0x84, 0x01, 0xE6, 0x84, 0xD2, 0xC1, 0x80, 0x73, 0xCD, 0x04,
4731 0x4D, 0x00, 0x00, 0xA3, 0xDA, 0x01, 0xA6, 0x97, 0xC6, 0x81, 0xC2, 0x88,
4732 0x80, 0x73, 0x80, 0x77, 0x00, 0x01, 0x01, 0xA1, 0xFE, 0x00, 0x4F, 0x00,
4733 0x84, 0x97, 0x07, 0xA6, 0x08, 0x01, 0x00, 0x33, 0x03, 0x00, 0xC2, 0x88,
4734 0x03, 0x03, 0x01, 0xDE, 0xC2, 0x88, 0xCE, 0x00, 0x69, 0x60, 0xCE, 0x00,
4735 0x02, 0x03, 0x4A, 0x60, 0x00, 0xA2, 0x78, 0x01, 0x80, 0x63, 0x07, 0xA6,
4736 0x24, 0x01, 0x78, 0x81, 0x03, 0x03, 0x80, 0x63, 0xE2, 0x00, 0x07, 0xA6,
4737 0x34, 0x01, 0x00, 0x33, 0x04, 0x00, 0xC2, 0x88, 0x03, 0x07, 0x02, 0x01,
4738 0x04, 0xCA, 0x0D, 0x23, 0x68, 0x98, 0x4D, 0x04, 0x04, 0x85, 0x05, 0xD8,
4739 0x0D, 0x23, 0x68, 0x98, 0xCD, 0x04, 0x15, 0x23, 0xF8, 0x88, 0xFB, 0x23,
4740 0x02, 0x61, 0x82, 0x01, 0x80, 0x63, 0x02, 0x03, 0x06, 0xA3, 0x62, 0x01,
4741 0x00, 0x33, 0x0A, 0x00, 0xC2, 0x88, 0x4E, 0x00, 0x07, 0xA3, 0x6E, 0x01,
4742 0x00, 0x33, 0x0B, 0x00, 0xC2, 0x88, 0xCD, 0x04, 0x36, 0x2D, 0x00, 0x33,
4743 0x1A, 0x00, 0xC2, 0x88, 0x50, 0x04, 0x88, 0x81, 0x06, 0xAB, 0x82, 0x01,
4744 0x88, 0x81, 0x4E, 0x00, 0x07, 0xA3, 0x92, 0x01, 0x50, 0x00, 0x00, 0xA3,
4745 0x3C, 0x01, 0x00, 0x05, 0x7C, 0x81, 0x46, 0x97, 0x02, 0x01, 0x05, 0xC6,
4746 0x04, 0x23, 0xA0, 0x01, 0x15, 0x23, 0xA1, 0x01, 0xBE, 0x81, 0xFD, 0x23,
4747 0x02, 0x61, 0x82, 0x01, 0x0A, 0xDA, 0x4A, 0x00, 0x06, 0x61, 0x00, 0xA0,
4748 0xB4, 0x01, 0x80, 0x63, 0xCD, 0x04, 0x36, 0x2D, 0x00, 0x33, 0x1B, 0x00,
4749 0xC2, 0x88, 0x06, 0x23, 0x68, 0x98, 0xCD, 0x04, 0xE6, 0x84, 0x06, 0x01,
4750 0x00, 0xA2, 0xD4, 0x01, 0x57, 0x60, 0x00, 0xA0, 0xDA, 0x01, 0xE6, 0x84,
4751 0x80, 0x23, 0xA0, 0x01, 0xE6, 0x84, 0x80, 0x73, 0x4B, 0x00, 0x06, 0x61,
4752 0x00, 0xA2, 0x00, 0x02, 0x04, 0x01, 0x0C, 0xDE, 0x02, 0x01, 0x03, 0xCC,
4753 0x4F, 0x00, 0x84, 0x97, 0xFC, 0x81, 0x08, 0x23, 0x02, 0x41, 0x82, 0x01,
4754 0x4F, 0x00, 0x62, 0x97, 0x48, 0x04, 0x84, 0x80, 0xF0, 0x97, 0x00, 0x46,
4755 0x56, 0x00, 0x03, 0xC0, 0x01, 0x23, 0xE8, 0x00, 0x81, 0x73, 0x06, 0x29,
4756 0x03, 0x42, 0x06, 0xE2, 0x03, 0xEE, 0x6B, 0xEB, 0x11, 0x23, 0xF8, 0x88,
4757 0x04, 0x98, 0xF0, 0x80, 0x80, 0x73, 0x80, 0x77, 0x07, 0xA4, 0x2A, 0x02,
4758 0x7C, 0x95, 0x06, 0xA6, 0x34, 0x02, 0x03, 0xA6, 0x4C, 0x04, 0x46, 0x82,
4759 0x04, 0x01, 0x03, 0xD8, 0xB4, 0x98, 0x6A, 0x96, 0x46, 0x82, 0xFE, 0x95,
4760 0x80, 0x67, 0x83, 0x03, 0x80, 0x63, 0xB6, 0x2D, 0x02, 0xA6, 0x6C, 0x02,
4761 0x07, 0xA6, 0x5A, 0x02, 0x06, 0xA6, 0x5E, 0x02, 0x03, 0xA6, 0x62, 0x02,
4762 0xC2, 0x88, 0x7C, 0x95, 0x48, 0x82, 0x60, 0x96, 0x48, 0x82, 0x04, 0x23,
4763 0xA0, 0x01, 0x14, 0x23, 0xA1, 0x01, 0x3C, 0x84, 0x04, 0x01, 0x0C, 0xDC,
4764 0xE0, 0x23, 0x25, 0x61, 0xEF, 0x00, 0x14, 0x01, 0x4F, 0x04, 0xA8, 0x01,
4765 0x6F, 0x00, 0xA5, 0x01, 0x03, 0x23, 0xA4, 0x01, 0x06, 0x23, 0x9C, 0x01,
4766 0x24, 0x2B, 0x1C, 0x01, 0x02, 0xA6, 0xAA, 0x02, 0x07, 0xA6, 0x5A, 0x02,
4767 0x06, 0xA6, 0x5E, 0x02, 0x03, 0xA6, 0x20, 0x04, 0x01, 0xA6, 0xB4, 0x02,
4768 0x00, 0xA6, 0xB4, 0x02, 0x00, 0x33, 0x12, 0x00, 0xC2, 0x88, 0x00, 0x0E,
4769 0x80, 0x63, 0x00, 0x43, 0x00, 0xA0, 0x8C, 0x02, 0x4D, 0x04, 0x04, 0x01,
4770 0x0B, 0xDC, 0xE7, 0x23, 0x04, 0x61, 0x84, 0x01, 0x10, 0x31, 0x12, 0x35,
4771 0x14, 0x01, 0xEC, 0x00, 0x6C, 0x38, 0x00, 0x3F, 0x00, 0x00, 0xEA, 0x82,
4772 0x18, 0x23, 0x04, 0x61, 0x18, 0xA0, 0xE2, 0x02, 0x04, 0x01, 0xA2, 0xC8,
4773 0x00, 0x33, 0x1F, 0x00, 0xC2, 0x88, 0x08, 0x31, 0x0A, 0x35, 0x0C, 0x39,
4774 0x0E, 0x3D, 0x7E, 0x98, 0xB6, 0x2D, 0x01, 0xA6, 0x14, 0x03, 0x00, 0xA6,
4775 0x14, 0x03, 0x07, 0xA6, 0x0C, 0x03, 0x06, 0xA6, 0x10, 0x03, 0x03, 0xA6,
4776 0x20, 0x04, 0x02, 0xA6, 0x6C, 0x02, 0x00, 0x33, 0x33, 0x00, 0xC2, 0x88,
4777 0x7C, 0x95, 0xEE, 0x82, 0x60, 0x96, 0xEE, 0x82, 0x82, 0x98, 0x80, 0x42,
4778 0x7E, 0x98, 0x64, 0xE4, 0x04, 0x01, 0x2D, 0xC8, 0x31, 0x05, 0x07, 0x01,
4779 0x00, 0xA2, 0x54, 0x03, 0x00, 0x43, 0x87, 0x01, 0x05, 0x05, 0x86, 0x98,
4780 0x7E, 0x98, 0x00, 0xA6, 0x16, 0x03, 0x07, 0xA6, 0x4C, 0x03, 0x03, 0xA6,
4781 0x3C, 0x04, 0x06, 0xA6, 0x50, 0x03, 0x01, 0xA6, 0x16, 0x03, 0x00, 0x33,
4782 0x25, 0x00, 0xC2, 0x88, 0x7C, 0x95, 0x32, 0x83, 0x60, 0x96, 0x32, 0x83,
4783 0x04, 0x01, 0x10, 0xCE, 0x07, 0xC8, 0x05, 0x05, 0xEB, 0x04, 0x00, 0x33,
4784 0x00, 0x20, 0xC0, 0x20, 0x81, 0x62, 0x72, 0x83, 0x00, 0x01, 0x05, 0x05,
4785 0xFF, 0xA2, 0x7A, 0x03, 0xB1, 0x01, 0x08, 0x23, 0xB2, 0x01, 0x2E, 0x83,
4786 0x05, 0x05, 0x15, 0x01, 0x00, 0xA2, 0x9A, 0x03, 0xEC, 0x00, 0x6E, 0x00,
4787 0x95, 0x01, 0x6C, 0x38, 0x00, 0x3F, 0x00, 0x00, 0x01, 0xA6, 0x96, 0x03,
4788 0x00, 0xA6, 0x96, 0x03, 0x10, 0x84, 0x80, 0x42, 0x7E, 0x98, 0x01, 0xA6,
4789 0xA4, 0x03, 0x00, 0xA6, 0xBC, 0x03, 0x10, 0x84, 0xA8, 0x98, 0x80, 0x42,
4790 0x01, 0xA6, 0xA4, 0x03, 0x07, 0xA6, 0xB2, 0x03, 0xD4, 0x83, 0x7C, 0x95,
4791 0xA8, 0x83, 0x00, 0x33, 0x2F, 0x00, 0xC2, 0x88, 0xA8, 0x98, 0x80, 0x42,
4792 0x00, 0xA6, 0xBC, 0x03, 0x07, 0xA6, 0xCA, 0x03, 0xD4, 0x83, 0x7C, 0x95,
4793 0xC0, 0x83, 0x00, 0x33, 0x26, 0x00, 0xC2, 0x88, 0x38, 0x2B, 0x80, 0x32,
4794 0x80, 0x36, 0x04, 0x23, 0xA0, 0x01, 0x12, 0x23, 0xA1, 0x01, 0x10, 0x84,
4795 0x07, 0xF0, 0x06, 0xA4, 0xF4, 0x03, 0x80, 0x6B, 0x80, 0x67, 0x05, 0x23,
4796 0x83, 0x03, 0x80, 0x63, 0x03, 0xA6, 0x0E, 0x04, 0x07, 0xA6, 0x06, 0x04,
4797 0x06, 0xA6, 0x0A, 0x04, 0x00, 0x33, 0x17, 0x00, 0xC2, 0x88, 0x7C, 0x95,
4798 0xF4, 0x83, 0x60, 0x96, 0xF4, 0x83, 0x20, 0x84, 0x07, 0xF0, 0x06, 0xA4,
4799 0x20, 0x04, 0x80, 0x6B, 0x80, 0x67, 0x05, 0x23, 0x83, 0x03, 0x80, 0x63,
4800 0xB6, 0x2D, 0x03, 0xA6, 0x3C, 0x04, 0x07, 0xA6, 0x34, 0x04, 0x06, 0xA6,
4801 0x38, 0x04, 0x00, 0x33, 0x30, 0x00, 0xC2, 0x88, 0x7C, 0x95, 0x20, 0x84,
4802 0x60, 0x96, 0x20, 0x84, 0x1D, 0x01, 0x06, 0xCC, 0x00, 0x33, 0x00, 0x84,
4803 0xC0, 0x20, 0x00, 0x23, 0xEA, 0x00, 0x81, 0x62, 0xA2, 0x0D, 0x80, 0x63,
4804 0x07, 0xA6, 0x5A, 0x04, 0x00, 0x33, 0x18, 0x00, 0xC2, 0x88, 0x03, 0x03,
4805 0x80, 0x63, 0xA3, 0x01, 0x07, 0xA4, 0x64, 0x04, 0x23, 0x01, 0x00, 0xA2,
4806 0x86, 0x04, 0x0A, 0xA0, 0x76, 0x04, 0xE0, 0x00, 0x00, 0x33, 0x1D, 0x00,
4807 0xC2, 0x88, 0x0B, 0xA0, 0x82, 0x04, 0xE0, 0x00, 0x00, 0x33, 0x1E, 0x00,
4808 0xC2, 0x88, 0x42, 0x23, 0xF8, 0x88, 0x00, 0x23, 0x22, 0xA3, 0xE6, 0x04,
4809 0x08, 0x23, 0x22, 0xA3, 0xA2, 0x04, 0x28, 0x23, 0x22, 0xA3, 0xAE, 0x04,
4810 0x02, 0x23, 0x22, 0xA3, 0xC4, 0x04, 0x42, 0x23, 0xF8, 0x88, 0x4A, 0x00,
4811 0x06, 0x61, 0x00, 0xA0, 0xAE, 0x04, 0x45, 0x23, 0xF8, 0x88, 0x04, 0x98,
4812 0x00, 0xA2, 0xC0, 0x04, 0xB4, 0x98, 0x00, 0x33, 0x00, 0x82, 0xC0, 0x20,
4813 0x81, 0x62, 0xE8, 0x81, 0x47, 0x23, 0xF8, 0x88, 0x04, 0x01, 0x0B, 0xDE,
4814 0x04, 0x98, 0xB4, 0x98, 0x00, 0x33, 0x00, 0x81, 0xC0, 0x20, 0x81, 0x62,
4815 0x14, 0x01, 0x00, 0xA0, 0x00, 0x02, 0x43, 0x23, 0xF8, 0x88, 0x04, 0x23,
4816 0xA0, 0x01, 0x44, 0x23, 0xA1, 0x01, 0x80, 0x73, 0x4D, 0x00, 0x03, 0xA3,
4817 0xF4, 0x04, 0x00, 0x33, 0x27, 0x00, 0xC2, 0x88, 0x04, 0x01, 0x04, 0xDC,
4818 0x02, 0x23, 0xA2, 0x01, 0x04, 0x23, 0xA0, 0x01, 0x04, 0x98, 0x26, 0x95,
4819 0x4B, 0x00, 0xF6, 0x00, 0x4F, 0x04, 0x4F, 0x00, 0x00, 0xA3, 0x22, 0x05,
4820 0x00, 0x05, 0x76, 0x00, 0x06, 0x61, 0x00, 0xA2, 0x1C, 0x05, 0x0A, 0x85,
4821 0x46, 0x97, 0xCD, 0x04, 0x24, 0x85, 0x48, 0x04, 0x84, 0x80, 0x02, 0x01,
4822 0x03, 0xDA, 0x80, 0x23, 0x82, 0x01, 0x34, 0x85, 0x02, 0x23, 0xA0, 0x01,
4823 0x4A, 0x00, 0x06, 0x61, 0x00, 0xA2, 0x40, 0x05, 0x1D, 0x01, 0x04, 0xD6,
4824 0xFF, 0x23, 0x86, 0x41, 0x4B, 0x60, 0xCB, 0x00, 0xFF, 0x23, 0x80, 0x01,
4825 0x49, 0x00, 0x81, 0x01, 0x04, 0x01, 0x02, 0xC8, 0x30, 0x01, 0x80, 0x01,
4826 0xF7, 0x04, 0x03, 0x01, 0x49, 0x04, 0x80, 0x01, 0xC9, 0x00, 0x00, 0x05,
4827 0x00, 0x01, 0xFF, 0xA0, 0x60, 0x05, 0x77, 0x04, 0x01, 0x23, 0xEA, 0x00,
4828 0x5D, 0x00, 0xFE, 0xC7, 0x00, 0x62, 0x00, 0x23, 0xEA, 0x00, 0x00, 0x63,
4829 0x07, 0xA4, 0xF8, 0x05, 0x03, 0x03, 0x02, 0xA0, 0x8E, 0x05, 0xF4, 0x85,
4830 0x00, 0x33, 0x2D, 0x00, 0xC2, 0x88, 0x04, 0xA0, 0xB8, 0x05, 0x80, 0x63,
4831 0x00, 0x23, 0xDF, 0x00, 0x4A, 0x00, 0x06, 0x61, 0x00, 0xA2, 0xA4, 0x05,
4832 0x1D, 0x01, 0x06, 0xD6, 0x02, 0x23, 0x02, 0x41, 0x82, 0x01, 0x50, 0x00,
4833 0x62, 0x97, 0x04, 0x85, 0x04, 0x23, 0x02, 0x41, 0x82, 0x01, 0x04, 0x85,
4834 0x08, 0xA0, 0xBE, 0x05, 0xF4, 0x85, 0x03, 0xA0, 0xC4, 0x05, 0xF4, 0x85,
4835 0x01, 0xA0, 0xCE, 0x05, 0x88, 0x00, 0x80, 0x63, 0xCC, 0x86, 0x07, 0xA0,
4836 0xEE, 0x05, 0x5F, 0x00, 0x00, 0x2B, 0xDF, 0x08, 0x00, 0xA2, 0xE6, 0x05,
4837 0x80, 0x67, 0x80, 0x63, 0x01, 0xA2, 0x7A, 0x06, 0x7C, 0x85, 0x06, 0x23,
4838 0x68, 0x98, 0x48, 0x23, 0xF8, 0x88, 0x07, 0x23, 0x80, 0x00, 0x06, 0x87,
4839 0x80, 0x63, 0x7C, 0x85, 0x00, 0x23, 0xDF, 0x00, 0x00, 0x63, 0x4A, 0x00,
4840 0x06, 0x61, 0x00, 0xA2, 0x36, 0x06, 0x1D, 0x01, 0x16, 0xD4, 0xC0, 0x23,
4841 0x07, 0x41, 0x83, 0x03, 0x80, 0x63, 0x06, 0xA6, 0x1C, 0x06, 0x00, 0x33,
4842 0x37, 0x00, 0xC2, 0x88, 0x1D, 0x01, 0x01, 0xD6, 0x20, 0x23, 0x63, 0x60,
4843 0x83, 0x03, 0x80, 0x63, 0x02, 0x23, 0xDF, 0x00, 0x07, 0xA6, 0x7C, 0x05,
4844 0xEF, 0x04, 0x6F, 0x00, 0x00, 0x63, 0x4B, 0x00, 0x06, 0x41, 0xCB, 0x00,
4845 0x52, 0x00, 0x06, 0x61, 0x00, 0xA2, 0x4E, 0x06, 0x1D, 0x01, 0x03, 0xCA,
4846 0xC0, 0x23, 0x07, 0x41, 0x00, 0x63, 0x1D, 0x01, 0x04, 0xCC, 0x00, 0x33,
4847 0x00, 0x83, 0xC0, 0x20, 0x81, 0x62, 0x80, 0x23, 0x07, 0x41, 0x00, 0x63,
4848 0x80, 0x67, 0x08, 0x23, 0x83, 0x03, 0x80, 0x63, 0x00, 0x63, 0x01, 0x23,
4849 0xDF, 0x00, 0x06, 0xA6, 0x84, 0x06, 0x07, 0xA6, 0x7C, 0x05, 0x80, 0x67,
4850 0x80, 0x63, 0x00, 0x33, 0x00, 0x40, 0xC0, 0x20, 0x81, 0x62, 0x00, 0x63,
4851 0x00, 0x00, 0xFE, 0x95, 0x83, 0x03, 0x80, 0x63, 0x06, 0xA6, 0x94, 0x06,
4852 0x07, 0xA6, 0x7C, 0x05, 0x00, 0x00, 0x01, 0xA0, 0x14, 0x07, 0x00, 0x2B,
4853 0x40, 0x0E, 0x80, 0x63, 0x01, 0x00, 0x06, 0xA6, 0xAA, 0x06, 0x07, 0xA6,
4854 0x7C, 0x05, 0x40, 0x0E, 0x80, 0x63, 0x00, 0x43, 0x00, 0xA0, 0xA2, 0x06,
4855 0x06, 0xA6, 0xBC, 0x06, 0x07, 0xA6, 0x7C, 0x05, 0x80, 0x67, 0x40, 0x0E,
4856 0x80, 0x63, 0x07, 0xA6, 0x7C, 0x05, 0x00, 0x23, 0xDF, 0x00, 0x00, 0x63,
4857 0x07, 0xA6, 0xD6, 0x06, 0x00, 0x33, 0x2A, 0x00, 0xC2, 0x88, 0x03, 0x03,
4858 0x80, 0x63, 0x89, 0x00, 0x0A, 0x2B, 0x07, 0xA6, 0xE8, 0x06, 0x00, 0x33,
4859 0x29, 0x00, 0xC2, 0x88, 0x00, 0x43, 0x00, 0xA2, 0xF4, 0x06, 0xC0, 0x0E,
4860 0x80, 0x63, 0xDE, 0x86, 0xC0, 0x0E, 0x00, 0x33, 0x00, 0x80, 0xC0, 0x20,
4861 0x81, 0x62, 0x04, 0x01, 0x02, 0xDA, 0x80, 0x63, 0x7C, 0x85, 0x80, 0x7B,
4862 0x80, 0x63, 0x06, 0xA6, 0x8C, 0x06, 0x00, 0x33, 0x2C, 0x00, 0xC2, 0x88,
4863 0x0C, 0xA2, 0x2E, 0x07, 0xFE, 0x95, 0x83, 0x03, 0x80, 0x63, 0x06, 0xA6,
4864 0x2C, 0x07, 0x07, 0xA6, 0x7C, 0x05, 0x00, 0x33, 0x3D, 0x00, 0xC2, 0x88,
4865 0x00, 0x00, 0x80, 0x67, 0x83, 0x03, 0x80, 0x63, 0x0C, 0xA0, 0x44, 0x07,
4866 0x07, 0xA6, 0x7C, 0x05, 0xBF, 0x23, 0x04, 0x61, 0x84, 0x01, 0xE6, 0x84,
4867 0x00, 0x63, 0xF0, 0x04, 0x01, 0x01, 0xF1, 0x00, 0x00, 0x01, 0xF2, 0x00,
4868 0x01, 0x05, 0x80, 0x01, 0x72, 0x04, 0x71, 0x00, 0x81, 0x01, 0x70, 0x04,
4869 0x80, 0x05, 0x81, 0x05, 0x00, 0x63, 0xF0, 0x04, 0xF2, 0x00, 0x72, 0x04,
4870 0x01, 0x01, 0xF1, 0x00, 0x70, 0x00, 0x81, 0x01, 0x70, 0x04, 0x71, 0x00,
4871 0x81, 0x01, 0x72, 0x00, 0x80, 0x01, 0x71, 0x04, 0x70, 0x00, 0x80, 0x01,
4872 0x70, 0x04, 0x00, 0x63, 0xF0, 0x04, 0xF2, 0x00, 0x72, 0x04, 0x00, 0x01,
4873 0xF1, 0x00, 0x70, 0x00, 0x80, 0x01, 0x70, 0x04, 0x71, 0x00, 0x80, 0x01,
4874 0x72, 0x00, 0x81, 0x01, 0x71, 0x04, 0x70, 0x00, 0x81, 0x01, 0x70, 0x04,
4875 0x00, 0x63, 0x00, 0x23, 0xB3, 0x01, 0x83, 0x05, 0xA3, 0x01, 0xA2, 0x01,
4876 0xA1, 0x01, 0x01, 0x23, 0xA0, 0x01, 0x00, 0x01, 0xC8, 0x00, 0x03, 0xA1,
4877 0xC4, 0x07, 0x00, 0x33, 0x07, 0x00, 0xC2, 0x88, 0x80, 0x05, 0x81, 0x05,
4878 0x04, 0x01, 0x11, 0xC8, 0x48, 0x00, 0xB0, 0x01, 0xB1, 0x01, 0x08, 0x23,
4879 0xB2, 0x01, 0x05, 0x01, 0x48, 0x04, 0x00, 0x43, 0x00, 0xA2, 0xE4, 0x07,
4880 0x00, 0x05, 0xDA, 0x87, 0x00, 0x01, 0xC8, 0x00, 0xFF, 0x23, 0x80, 0x01,
4881 0x05, 0x05, 0x00, 0x63, 0xF7, 0x04, 0x1A, 0x09, 0xF6, 0x08, 0x6E, 0x04,
4882 0x00, 0x02, 0x80, 0x43, 0x76, 0x08, 0x80, 0x02, 0x77, 0x04, 0x00, 0x63,
4883 0xF7, 0x04, 0x1A, 0x09, 0xF6, 0x08, 0x6E, 0x04, 0x00, 0x02, 0x00, 0xA0,
4884 0x14, 0x08, 0x16, 0x88, 0x00, 0x43, 0x76, 0x08, 0x80, 0x02, 0x77, 0x04,
4885 0x00, 0x63, 0xF3, 0x04, 0x00, 0x23, 0xF4, 0x00, 0x74, 0x00, 0x80, 0x43,
4886 0xF4, 0x00, 0xCF, 0x40, 0x00, 0xA2, 0x44, 0x08, 0x74, 0x04, 0x02, 0x01,
4887 0xF7, 0xC9, 0xF6, 0xD9, 0x00, 0x01, 0x01, 0xA1, 0x24, 0x08, 0x04, 0x98,
4888 0x26, 0x95, 0x24, 0x88, 0x73, 0x04, 0x00, 0x63, 0xF3, 0x04, 0x75, 0x04,
4889 0x5A, 0x88, 0x02, 0x01, 0x04, 0xD8, 0x46, 0x97, 0x04, 0x98, 0x26, 0x95,
4890 0x4A, 0x88, 0x75, 0x00, 0x00, 0xA3, 0x64, 0x08, 0x00, 0x05, 0x4E, 0x88,
4891 0x73, 0x04, 0x00, 0x63, 0x80, 0x7B, 0x80, 0x63, 0x06, 0xA6, 0x76, 0x08,
4892 0x00, 0x33, 0x3E, 0x00, 0xC2, 0x88, 0x80, 0x67, 0x83, 0x03, 0x80, 0x63,
4893 0x00, 0x63, 0x38, 0x2B, 0x9C, 0x88, 0x38, 0x2B, 0x92, 0x88, 0x32, 0x09,
4894 0x31, 0x05, 0x92, 0x98, 0x05, 0x05, 0xB2, 0x09, 0x00, 0x63, 0x00, 0x32,
4895 0x00, 0x36, 0x00, 0x3A, 0x00, 0x3E, 0x00, 0x63, 0x80, 0x32, 0x80, 0x36,
4896 0x80, 0x3A, 0x80, 0x3E, 0xB4, 0x3D, 0x00, 0x63, 0x38, 0x2B, 0x40, 0x32,
4897 0x40, 0x36, 0x40, 0x3A, 0x40, 0x3E, 0x00, 0x63, 0x5A, 0x20, 0xC9, 0x40,
4898 0x00, 0xA0, 0xB4, 0x08, 0x5D, 0x00, 0xFE, 0xC3, 0x00, 0x63, 0x80, 0x73,
4899 0xE6, 0x20, 0x02, 0x23, 0xE8, 0x00, 0x82, 0x73, 0xFF, 0xFD, 0x80, 0x73,
4900 0x13, 0x23, 0xF8, 0x88, 0x66, 0x20, 0xC0, 0x20, 0x04, 0x23, 0xA0, 0x01,
4901 0xA1, 0x23, 0xA1, 0x01, 0x81, 0x62, 0xE2, 0x88, 0x80, 0x73, 0x80, 0x77,
4902 0x68, 0x00, 0x00, 0xA2, 0x80, 0x00, 0x03, 0xC2, 0xF1, 0xC7, 0x41, 0x23,
4903 0xF8, 0x88, 0x11, 0x23, 0xA1, 0x01, 0x04, 0x23, 0xA0, 0x01, 0xE6, 0x84,
4906 static unsigned short _asc_mcode_size = sizeof(_asc_mcode_buf);
4907 static ADV_DCNT _asc_mcode_chksum = 0x012C453FUL;
4909 /* Microcode buffer is kept after initialization for error recovery. */
4910 static unsigned char _adv_asc3550_buf[] = {
4911 0x00, 0x00, 0x00, 0xf2, 0x00, 0xf0, 0x00, 0x16, 0x18, 0xe4, 0x00, 0xfc,
4912 0x01, 0x00, 0x48, 0xe4, 0xbe, 0x18, 0x18, 0x80, 0x03, 0xf6, 0x02, 0x00,
4913 0x00, 0xfa, 0xff, 0xff, 0x28, 0x0e, 0x9e, 0xe7, 0xff, 0x00, 0x82, 0xe7,
4914 0x00, 0xea, 0x00, 0xf6, 0x01, 0xe6, 0x09, 0xe7, 0x55, 0xf0, 0x01, 0xf6,
4915 0x01, 0xfa, 0x08, 0x00, 0x03, 0x00, 0x04, 0x00, 0x18, 0xf4, 0x10, 0x00,
4916 0x00, 0xec, 0x85, 0xf0, 0xbc, 0x00, 0xd5, 0xf0, 0x8e, 0x0c, 0x38, 0x54,
4917 0x00, 0xe6, 0x1e, 0xf0, 0x86, 0xf0, 0xb4, 0x00, 0x98, 0x57, 0xd0, 0x01,
4918 0x0c, 0x1c, 0x3e, 0x1c, 0x0c, 0x00, 0xbb, 0x00, 0xaa, 0x18, 0x02, 0x80,
4919 0x32, 0xf0, 0x01, 0xfc, 0x88, 0x0c, 0xc6, 0x12, 0x02, 0x13, 0x18, 0x40,
4920 0x00, 0x57, 0x01, 0xea, 0x3c, 0x00, 0x6c, 0x01, 0x6e, 0x01, 0x04, 0x12,
4921 0x3e, 0x57, 0x00, 0x80, 0x03, 0xe6, 0xb6, 0x00, 0xc0, 0x00, 0x01, 0x01,
4922 0x3e, 0x01, 0xda, 0x0f, 0x22, 0x10, 0x08, 0x12, 0x02, 0x4a, 0xb9, 0x54,
4923 0x03, 0x58, 0x1b, 0x80, 0x30, 0xe4, 0x4b, 0xe4, 0x20, 0x00, 0x32, 0x00,
4924 0x3e, 0x00, 0x80, 0x00, 0x24, 0x01, 0x3c, 0x01, 0x68, 0x01, 0x6a, 0x01,
4925 0x70, 0x01, 0x72, 0x01, 0x74, 0x01, 0x76, 0x01, 0x78, 0x01, 0x62, 0x0a,
4926 0x92, 0x0c, 0x2c, 0x10, 0x2e, 0x10, 0x06, 0x13, 0x4c, 0x1c, 0xbb, 0x55,
4927 0x3c, 0x56, 0x04, 0x80, 0x4a, 0xe4, 0x02, 0xee, 0x5b, 0xf0, 0xb1, 0xf0,
4928 0x03, 0xf7, 0x06, 0xf7, 0x03, 0xfc, 0x0f, 0x00, 0x40, 0x00, 0xbe, 0x00,
4929 0x00, 0x01, 0xb0, 0x08, 0x30, 0x13, 0x64, 0x15, 0x32, 0x1c, 0x38, 0x1c,
4930 0x4e, 0x1c, 0x10, 0x44, 0x02, 0x48, 0x00, 0x4c, 0x04, 0xea, 0x5d, 0xf0,
4931 0x04, 0xf6, 0x02, 0xfc, 0x05, 0x00, 0x34, 0x00, 0x36, 0x00, 0x98, 0x00,
4932 0xcc, 0x00, 0x20, 0x01, 0x4e, 0x01, 0x4e, 0x0b, 0x1e, 0x0e, 0x0c, 0x10,
4933 0x0a, 0x12, 0x04, 0x13, 0x40, 0x13, 0x30, 0x1c, 0x00, 0x4e, 0xbd, 0x56,
4934 0x06, 0x83, 0x00, 0xdc, 0x05, 0xf0, 0x09, 0xf0, 0x59, 0xf0, 0xa7, 0xf0,
4935 0xb8, 0xf0, 0x0e, 0xf7, 0x06, 0x00, 0x19, 0x00, 0x33, 0x00, 0x9b, 0x00,
4936 0xa4, 0x00, 0xb5, 0x00, 0xba, 0x00, 0xd0, 0x00, 0xe1, 0x00, 0xe7, 0x00,
4937 0xde, 0x03, 0x56, 0x0a, 0x14, 0x0e, 0x02, 0x10, 0x04, 0x10, 0x0a, 0x10,
4938 0x36, 0x10, 0x0a, 0x13, 0x12, 0x13, 0x52, 0x13, 0x10, 0x15, 0x14, 0x15,
4939 0xac, 0x16, 0x20, 0x1c, 0x34, 0x1c, 0x36, 0x1c, 0x08, 0x44, 0x38, 0x44,
4940 0x91, 0x44, 0x0a, 0x45, 0x48, 0x46, 0x01, 0x48, 0x68, 0x54, 0x83, 0x55,
4941 0xb0, 0x57, 0x01, 0x58, 0x83, 0x59, 0x05, 0xe6, 0x0b, 0xf0, 0x0c, 0xf0,
4942 0x5c, 0xf0, 0x4b, 0xf4, 0x04, 0xf8, 0x05, 0xf8, 0x02, 0xfa, 0x03, 0xfa,
4943 0x04, 0xfc, 0x05, 0xfc, 0x07, 0x00, 0x0a, 0x00, 0x0d, 0x00, 0x1c, 0x00,
4944 0x9e, 0x00, 0xa8, 0x00, 0xaa, 0x00, 0xb9, 0x00, 0xe0, 0x00, 0x22, 0x01,
4945 0x26, 0x01, 0x79, 0x01, 0x7a, 0x01, 0xc0, 0x01, 0xc2, 0x01, 0x7c, 0x02,
4946 0x5a, 0x03, 0xea, 0x04, 0xe8, 0x07, 0x68, 0x08, 0x69, 0x08, 0xba, 0x08,
4947 0xe9, 0x09, 0x06, 0x0b, 0x3a, 0x0e, 0x00, 0x10, 0x1a, 0x10, 0xed, 0x10,
4948 0xf1, 0x10, 0x06, 0x12, 0x0c, 0x13, 0x16, 0x13, 0x1e, 0x13, 0x82, 0x13,
4949 0x42, 0x14, 0xd6, 0x14, 0x8a, 0x15, 0xc6, 0x17, 0xd2, 0x17, 0x6b, 0x18,
4950 0x12, 0x1c, 0x46, 0x1c, 0x9c, 0x32, 0x00, 0x40, 0x0e, 0x47, 0x48, 0x47,
4951 0x41, 0x48, 0x89, 0x48, 0x80, 0x4c, 0x00, 0x54, 0x44, 0x55, 0xe5, 0x55,
4952 0x14, 0x56, 0x77, 0x57, 0xbf, 0x57, 0x40, 0x5c, 0x06, 0x80, 0x08, 0x90,
4953 0x03, 0xa1, 0xfe, 0x9c, 0xf0, 0x29, 0x02, 0xfe, 0xb8, 0x0c, 0xff, 0x10,
4954 0x00, 0x00, 0xd0, 0xfe, 0xcc, 0x18, 0x00, 0xcf, 0xfe, 0x80, 0x01, 0xff,
4955 0x03, 0x00, 0x00, 0xfe, 0x93, 0x15, 0xfe, 0x0f, 0x05, 0xff, 0x38, 0x00,
4956 0x00, 0xfe, 0x57, 0x24, 0x00, 0xfe, 0x48, 0x00, 0x4f, 0xff, 0x04, 0x00,
4957 0x00, 0x10, 0xff, 0x09, 0x00, 0x00, 0xff, 0x08, 0x01, 0x01, 0xff, 0x08,
4958 0xff, 0xff, 0xff, 0x27, 0x00, 0x00, 0xff, 0x10, 0xff, 0xff, 0xff, 0x0f,
4959 0x00, 0x00, 0xfe, 0x78, 0x56, 0xfe, 0x34, 0x12, 0xff, 0x21, 0x00, 0x00,
4960 0xfe, 0x04, 0xf7, 0xcf, 0x2a, 0x67, 0x0b, 0x01, 0xfe, 0xce, 0x0e, 0xfe,
4961 0x04, 0xf7, 0xcf, 0x67, 0x0b, 0x3c, 0x2a, 0xfe, 0x3d, 0xf0, 0xfe, 0x02,
4962 0x02, 0xfe, 0x20, 0xf0, 0x9c, 0xfe, 0x91, 0xf0, 0xfe, 0xf0, 0x01, 0xfe,
4963 0x90, 0xf0, 0xfe, 0xf0, 0x01, 0xfe, 0x8f, 0xf0, 0x9c, 0x05, 0x51, 0x3b,
4964 0x02, 0xfe, 0xd4, 0x0c, 0x01, 0xfe, 0x44, 0x0d, 0xfe, 0xdd, 0x12, 0xfe,
4965 0xfc, 0x10, 0xfe, 0x28, 0x1c, 0x05, 0xfe, 0xa6, 0x00, 0xfe, 0xd3, 0x12,
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5261 0x4d, 0xe4, 0x19, 0xba, 0xfe, 0x9c, 0x14, 0xb7, 0x19, 0x83, 0x60, 0x23,
5262 0xfe, 0x4d, 0xf4, 0x00, 0xdf, 0x89, 0x13, 0x06, 0xfe, 0xb4, 0x56, 0xfe,
5263 0xc3, 0x58, 0x03, 0x60, 0x13, 0x0b, 0x03, 0x15, 0x06, 0x01, 0x08, 0x26,
5264 0xe5, 0x15, 0x0b, 0x01, 0x08, 0x26, 0xe5, 0x15, 0x1a, 0x01, 0x08, 0x26,
5265 0xe5, 0x72, 0xfe, 0x89, 0x49, 0x01, 0x08, 0x03, 0x15, 0x06, 0x01, 0x08,
5266 0x26, 0xa6, 0x15, 0x1a, 0x01, 0x08, 0x26, 0xa6, 0x15, 0x06, 0x01, 0x08,
5267 0x26, 0xa6, 0xfe, 0x89, 0x49, 0x01, 0x08, 0x26, 0xa6, 0x72, 0xfe, 0x89,
5268 0x4a, 0x01, 0x08, 0x03, 0x60, 0x03, 0x1e, 0xcc, 0x07, 0x06, 0xfe, 0x44,
5269 0x13, 0xad, 0x12, 0xcc, 0xfe, 0x49, 0xf4, 0x00, 0x3b, 0x72, 0x9f, 0x5e,
5270 0xfe, 0x01, 0xec, 0xfe, 0x27, 0x01, 0xf1, 0x01, 0x08, 0x2f, 0x07, 0xfe,
5271 0xe3, 0x00, 0xfe, 0x20, 0x13, 0x1f, 0xfe, 0x5a, 0x15, 0x23, 0x12, 0xcd,
5272 0x01, 0x43, 0x1e, 0xcd, 0x07, 0x06, 0x45, 0x09, 0x4a, 0x06, 0x35, 0x03,
5273 0x0a, 0x42, 0x01, 0x0e, 0xed, 0x88, 0x07, 0x10, 0xa4, 0x0a, 0x80, 0x01,
5274 0x0e, 0x88, 0x0a, 0x51, 0x01, 0x9e, 0x03, 0x0a, 0x80, 0x01, 0x0e, 0x88,
5275 0xfe, 0x80, 0xe7, 0x10, 0x07, 0x10, 0x84, 0xfe, 0x45, 0x58, 0x01, 0xe3,
5276 0x88, 0x03, 0x0a, 0x42, 0x01, 0x0e, 0x88, 0x0a, 0x51, 0x01, 0x9e, 0x03,
5277 0x0a, 0x42, 0x01, 0x0e, 0xfe, 0x80, 0x80, 0xf2, 0xfe, 0x49, 0xe4, 0x10,
5278 0xa4, 0x0a, 0x80, 0x01, 0x0e, 0xf2, 0x0a, 0x51, 0x01, 0x82, 0x03, 0x17,
5279 0x10, 0x71, 0x66, 0xfe, 0x60, 0x01, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde,
5280 0xfe, 0x24, 0x1c, 0xfe, 0x1d, 0xf7, 0x1d, 0x90, 0xfe, 0xf6, 0x15, 0x01,
5281 0xfe, 0xfc, 0x16, 0xe0, 0x91, 0x1d, 0x66, 0xfe, 0x2c, 0x01, 0xfe, 0x2f,
5282 0x19, 0x03, 0xae, 0x21, 0xfe, 0xe6, 0x15, 0xfe, 0xda, 0x10, 0x17, 0x10,
5283 0x71, 0x05, 0xfe, 0x64, 0x01, 0xfe, 0x00, 0xf4, 0x19, 0xfe, 0x18, 0x58,
5284 0x05, 0xfe, 0x66, 0x01, 0xfe, 0x19, 0x58, 0x91, 0x19, 0xfe, 0x3c, 0x90,
5285 0xfe, 0x30, 0xf4, 0x06, 0xfe, 0x3c, 0x50, 0x66, 0xfe, 0x38, 0x00, 0xfe,
5286 0x0f, 0x79, 0xfe, 0x1c, 0xf7, 0x19, 0x90, 0xfe, 0x40, 0x16, 0xfe, 0xb6,
5287 0x14, 0x34, 0x03, 0xae, 0x21, 0xfe, 0x18, 0x16, 0xfe, 0x9c, 0x10, 0x17,
5288 0x10, 0x71, 0xfe, 0x83, 0x5a, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde, 0xfe,
5289 0x1d, 0xf7, 0x38, 0x90, 0xfe, 0x62, 0x16, 0xfe, 0x94, 0x14, 0xfe, 0x10,
5290 0x13, 0x91, 0x38, 0x66, 0x1b, 0xfe, 0xaf, 0x19, 0xfe, 0x98, 0xe7, 0x00,
5291 0x03, 0xae, 0x21, 0xfe, 0x56, 0x16, 0xfe, 0x6c, 0x10, 0x17, 0x10, 0x71,
5292 0xfe, 0x30, 0xbc, 0xfe, 0xb2, 0xbc, 0x91, 0xc5, 0x66, 0x1b, 0xfe, 0x0f,
5293 0x79, 0xfe, 0x1c, 0xf7, 0xc5, 0x90, 0xfe, 0x9a, 0x16, 0xfe, 0x5c, 0x14,
5294 0x34, 0x03, 0xae, 0x21, 0xfe, 0x86, 0x16, 0xfe, 0x42, 0x10, 0xfe, 0x02,
5295 0xf6, 0x10, 0x71, 0xfe, 0x18, 0xfe, 0x54, 0xfe, 0x19, 0xfe, 0x55, 0xfc,
5296 0xfe, 0x1d, 0xf7, 0x4f, 0x90, 0xfe, 0xc0, 0x16, 0xfe, 0x36, 0x14, 0xfe,
5297 0x1c, 0x13, 0x91, 0x4f, 0x47, 0xfe, 0x83, 0x58, 0xfe, 0xaf, 0x19, 0xfe,
5298 0x80, 0xe7, 0x10, 0xfe, 0x81, 0xe7, 0x10, 0x11, 0xfe, 0xdd, 0x00, 0x63,
5299 0x27, 0x03, 0x63, 0x27, 0xfe, 0x12, 0x45, 0x21, 0xfe, 0xb0, 0x16, 0x14,
5300 0x06, 0x37, 0x95, 0xa9, 0x02, 0x29, 0xfe, 0x39, 0xf0, 0xfe, 0x04, 0x17,
5301 0x23, 0x03, 0xfe, 0x7e, 0x18, 0x1c, 0x1a, 0x5d, 0x13, 0x0d, 0x03, 0x71,
5302 0x05, 0xcb, 0x1c, 0x06, 0xfe, 0xef, 0x12, 0xfe, 0xe1, 0x10, 0x78, 0x2c,
5303 0x46, 0x2f, 0x07, 0x2d, 0xfe, 0x3c, 0x13, 0xfe, 0x82, 0x14, 0xfe, 0x42,
5304 0x13, 0x3c, 0x8a, 0x0a, 0x42, 0x01, 0x0e, 0xb0, 0xfe, 0x3e, 0x12, 0xf0,
5305 0xfe, 0x45, 0x48, 0x01, 0xe3, 0xfe, 0x00, 0xcc, 0xb0, 0xfe, 0xf3, 0x13,
5306 0x3d, 0x75, 0x07, 0x10, 0xa3, 0x0a, 0x80, 0x01, 0x0e, 0xf2, 0x01, 0x6f,
5307 0xfe, 0x16, 0x10, 0x07, 0x7e, 0x85, 0xfe, 0x40, 0x14, 0xfe, 0x24, 0x12,
5308 0xf6, 0xfe, 0xd6, 0xf0, 0xfe, 0x24, 0x17, 0x17, 0x0b, 0x03, 0xfe, 0x9c,
5309 0xe7, 0x0b, 0x0f, 0xfe, 0x15, 0x00, 0x59, 0x76, 0x27, 0x01, 0xda, 0x17,
5310 0x06, 0x03, 0x3c, 0x8a, 0x09, 0x4a, 0x1d, 0x35, 0x11, 0x2d, 0x01, 0x6f,
5311 0x17, 0x06, 0x03, 0xfe, 0x38, 0x90, 0xfe, 0xba, 0x90, 0x79, 0xc7, 0x68,
5312 0xc8, 0xfe, 0x48, 0x55, 0x34, 0xfe, 0xc9, 0x55, 0x03, 0x1e, 0x98, 0x73,
5313 0x12, 0x98, 0x03, 0x0a, 0x99, 0x01, 0x0e, 0xf0, 0x0a, 0x40, 0x01, 0x0e,
5314 0xfe, 0x49, 0x44, 0x16, 0xfe, 0xf0, 0x17, 0x73, 0x75, 0x03, 0x0a, 0x42,
5315 0x01, 0x0e, 0x07, 0x10, 0x45, 0x0a, 0x51, 0x01, 0x9e, 0x0a, 0x40, 0x01,
5316 0x0e, 0x73, 0x75, 0x03, 0xfe, 0x4e, 0xe4, 0x1a, 0x64, 0xfe, 0x24, 0x18,
5317 0x05, 0xfe, 0x90, 0x00, 0xfe, 0x3a, 0x45, 0x5b, 0xfe, 0x4e, 0xe4, 0xc2,
5318 0x64, 0xfe, 0x36, 0x18, 0x05, 0xfe, 0x92, 0x00, 0xfe, 0x02, 0xe6, 0x1b,
5319 0xdc, 0xfe, 0x4e, 0xe4, 0xfe, 0x0b, 0x00, 0x64, 0xfe, 0x48, 0x18, 0x05,
5320 0xfe, 0x94, 0x00, 0xfe, 0x02, 0xe6, 0x19, 0xfe, 0x08, 0x10, 0x05, 0xfe,
5321 0x96, 0x00, 0xfe, 0x02, 0xe6, 0x2c, 0xfe, 0x4e, 0x45, 0xfe, 0x0c, 0x12,
5322 0xaf, 0xff, 0x04, 0x68, 0x54, 0xde, 0x1c, 0x69, 0x03, 0x07, 0x7a, 0xfe,
5323 0x5a, 0xf0, 0xfe, 0x74, 0x18, 0x24, 0xfe, 0x09, 0x00, 0xfe, 0x34, 0x10,
5324 0x07, 0x1b, 0xfe, 0x5a, 0xf0, 0xfe, 0x82, 0x18, 0x24, 0xc3, 0xfe, 0x26,
5325 0x10, 0x07, 0x1a, 0x5d, 0x24, 0x2c, 0xdc, 0x07, 0x0b, 0x5d, 0x24, 0x93,
5326 0xfe, 0x0e, 0x10, 0x07, 0x06, 0x5d, 0x24, 0x4d, 0x9f, 0xad, 0x03, 0x14,
5327 0xfe, 0x09, 0x00, 0x01, 0x33, 0xfe, 0x04, 0xfe, 0x7d, 0x05, 0x7f, 0xf9,
5328 0x03, 0x25, 0xfe, 0xca, 0x18, 0xfe, 0x14, 0xf0, 0x08, 0x65, 0xfe, 0xc6,
5329 0x18, 0x03, 0xff, 0x1a, 0x00, 0x00,
5332 static unsigned short _adv_asc3550_size = sizeof(_adv_asc3550_buf); /* 0x13AD */
5333 static ADV_DCNT _adv_asc3550_chksum = 0x04D52DDDUL; /* Expanded little-endian checksum. */
5335 /* Microcode buffer is kept after initialization for error recovery. */
5336 static unsigned char _adv_asc38C0800_buf[] = {
5337 0x00, 0x00, 0x00, 0xf2, 0x00, 0xf0, 0x00, 0xfc, 0x00, 0x16, 0x18, 0xe4,
5338 0x01, 0x00, 0x48, 0xe4, 0x18, 0x80, 0x03, 0xf6, 0x02, 0x00, 0xce, 0x19,
5339 0x00, 0xfa, 0xff, 0xff, 0x1c, 0x0f, 0x00, 0xf6, 0x9e, 0xe7, 0xff, 0x00,
5340 0x82, 0xe7, 0x00, 0xea, 0x01, 0xfa, 0x01, 0xe6, 0x09, 0xe7, 0x55, 0xf0,
5341 0x01, 0xf6, 0x03, 0x00, 0x04, 0x00, 0x10, 0x00, 0x1e, 0xf0, 0x85, 0xf0,
5342 0x18, 0xf4, 0x08, 0x00, 0xbc, 0x00, 0x38, 0x54, 0x00, 0xec, 0xd5, 0xf0,
5343 0x82, 0x0d, 0x00, 0xe6, 0x86, 0xf0, 0xb1, 0xf0, 0x98, 0x57, 0x01, 0xfc,
5344 0xb4, 0x00, 0xd4, 0x01, 0x0c, 0x1c, 0x3e, 0x1c, 0x3c, 0x00, 0xbb, 0x00,
5345 0x00, 0x10, 0xba, 0x19, 0x02, 0x80, 0x32, 0xf0, 0x7c, 0x0d, 0x02, 0x13,
5346 0xba, 0x13, 0x18, 0x40, 0x00, 0x57, 0x01, 0xea, 0x02, 0xfc, 0x03, 0xfc,
5347 0x3e, 0x00, 0x6c, 0x01, 0x6e, 0x01, 0x74, 0x01, 0x76, 0x01, 0xb9, 0x54,
5348 0x3e, 0x57, 0x00, 0x80, 0x03, 0xe6, 0xb6, 0x00, 0xc0, 0x00, 0x01, 0x01,
5349 0x3e, 0x01, 0x7a, 0x01, 0xca, 0x08, 0xce, 0x10, 0x16, 0x11, 0x04, 0x12,
5350 0x08, 0x12, 0x02, 0x4a, 0xbb, 0x55, 0x3c, 0x56, 0x03, 0x58, 0x1b, 0x80,
5351 0x30, 0xe4, 0x4b, 0xe4, 0x5d, 0xf0, 0x02, 0xfa, 0x20, 0x00, 0x32, 0x00,
5352 0x40, 0x00, 0x80, 0x00, 0x24, 0x01, 0x3c, 0x01, 0x68, 0x01, 0x6a, 0x01,
5353 0x70, 0x01, 0x72, 0x01, 0x78, 0x01, 0x7c, 0x01, 0x62, 0x0a, 0x86, 0x0d,
5354 0x06, 0x13, 0x4c, 0x1c, 0x04, 0x80, 0x4a, 0xe4, 0x02, 0xee, 0x5b, 0xf0,
5355 0x03, 0xf7, 0x0c, 0x00, 0x0f, 0x00, 0x47, 0x00, 0xbe, 0x00, 0x00, 0x01,
5356 0x20, 0x11, 0x5c, 0x16, 0x32, 0x1c, 0x38, 0x1c, 0x4e, 0x1c, 0x10, 0x44,
5357 0x00, 0x4c, 0x04, 0xea, 0x5c, 0xf0, 0xa7, 0xf0, 0x04, 0xf6, 0x03, 0xfa,
5358 0x05, 0x00, 0x34, 0x00, 0x36, 0x00, 0x98, 0x00, 0xcc, 0x00, 0x20, 0x01,
5359 0x4e, 0x01, 0x4a, 0x0b, 0x42, 0x0c, 0x12, 0x0f, 0x0c, 0x10, 0x22, 0x11,
5360 0x0a, 0x12, 0x04, 0x13, 0x30, 0x1c, 0x02, 0x48, 0x00, 0x4e, 0x42, 0x54,
5361 0x44, 0x55, 0xbd, 0x56, 0x06, 0x83, 0x00, 0xdc, 0x05, 0xf0, 0x09, 0xf0,
5362 0x59, 0xf0, 0xb8, 0xf0, 0x4b, 0xf4, 0x06, 0xf7, 0x0e, 0xf7, 0x04, 0xfc,
5363 0x05, 0xfc, 0x06, 0x00, 0x19, 0x00, 0x33, 0x00, 0x9b, 0x00, 0xa4, 0x00,
5364 0xb5, 0x00, 0xba, 0x00, 0xd0, 0x00, 0xe1, 0x00, 0xe7, 0x00, 0xe2, 0x03,
5365 0x08, 0x0f, 0x02, 0x10, 0x04, 0x10, 0x0a, 0x10, 0x0a, 0x13, 0x0c, 0x13,
5366 0x12, 0x13, 0x24, 0x14, 0x34, 0x14, 0x04, 0x16, 0x08, 0x16, 0xa4, 0x17,
5367 0x20, 0x1c, 0x34, 0x1c, 0x36, 0x1c, 0x08, 0x44, 0x38, 0x44, 0x91, 0x44,
5368 0x0a, 0x45, 0x48, 0x46, 0x01, 0x48, 0x68, 0x54, 0x3a, 0x55, 0x83, 0x55,
5369 0xe5, 0x55, 0xb0, 0x57, 0x01, 0x58, 0x83, 0x59, 0x05, 0xe6, 0x0b, 0xf0,
5370 0x0c, 0xf0, 0x04, 0xf8, 0x05, 0xf8, 0x07, 0x00, 0x0a, 0x00, 0x1c, 0x00,
5371 0x1e, 0x00, 0x9e, 0x00, 0xa8, 0x00, 0xaa, 0x00, 0xb9, 0x00, 0xe0, 0x00,
5372 0x22, 0x01, 0x26, 0x01, 0x79, 0x01, 0x7e, 0x01, 0xc4, 0x01, 0xc6, 0x01,
5373 0x80, 0x02, 0x5e, 0x03, 0xee, 0x04, 0x9a, 0x06, 0xf8, 0x07, 0x62, 0x08,
5374 0x68, 0x08, 0x69, 0x08, 0xd6, 0x08, 0xe9, 0x09, 0xfa, 0x0b, 0x2e, 0x0f,
5375 0x12, 0x10, 0x1a, 0x10, 0xed, 0x10, 0xf1, 0x10, 0x2a, 0x11, 0x06, 0x12,
5376 0x0c, 0x12, 0x3e, 0x12, 0x10, 0x13, 0x16, 0x13, 0x1e, 0x13, 0x46, 0x14,
5377 0x76, 0x14, 0x82, 0x14, 0x36, 0x15, 0xca, 0x15, 0x6b, 0x18, 0xbe, 0x18,
5378 0xca, 0x18, 0xe6, 0x19, 0x12, 0x1c, 0x46, 0x1c, 0x9c, 0x32, 0x00, 0x40,
5379 0x0e, 0x47, 0xfe, 0x9c, 0xf0, 0x2b, 0x02, 0xfe, 0xac, 0x0d, 0xff, 0x10,
5380 0x00, 0x00, 0xd7, 0xfe, 0xe8, 0x19, 0x00, 0xd6, 0xfe, 0x84, 0x01, 0xff,
5381 0x03, 0x00, 0x00, 0xfe, 0x93, 0x15, 0xfe, 0x0f, 0x05, 0xff, 0x38, 0x00,
5382 0x00, 0xfe, 0x57, 0x24, 0x00, 0xfe, 0x4c, 0x00, 0x5b, 0xff, 0x04, 0x00,
5383 0x00, 0x11, 0xff, 0x09, 0x00, 0x00, 0xff, 0x08, 0x01, 0x01, 0xff, 0x08,
5384 0xff, 0xff, 0xff, 0x27, 0x00, 0x00, 0xff, 0x10, 0xff, 0xff, 0xff, 0x11,
5385 0x00, 0x00, 0xfe, 0x78, 0x56, 0xfe, 0x34, 0x12, 0xff, 0x21, 0x00, 0x00,
5386 0xfe, 0x04, 0xf7, 0xd6, 0x2c, 0x99, 0x0a, 0x01, 0xfe, 0xc2, 0x0f, 0xfe,
5387 0x04, 0xf7, 0xd6, 0x99, 0x0a, 0x42, 0x2c, 0xfe, 0x3d, 0xf0, 0xfe, 0x06,
5388 0x02, 0xfe, 0x20, 0xf0, 0xa7, 0xfe, 0x91, 0xf0, 0xfe, 0xf4, 0x01, 0xfe,
5389 0x90, 0xf0, 0xfe, 0xf4, 0x01, 0xfe, 0x8f, 0xf0, 0xa7, 0x03, 0x5d, 0x4d,
5390 0x02, 0xfe, 0xc8, 0x0d, 0x01, 0xfe, 0x38, 0x0e, 0xfe, 0xdd, 0x12, 0xfe,
5391 0xfc, 0x10, 0xfe, 0x28, 0x1c, 0x03, 0xfe, 0xa6, 0x00, 0xfe, 0xd3, 0x12,
5392 0x41, 0x14, 0xfe, 0xa6, 0x00, 0xc2, 0xfe, 0x48, 0xf0, 0xfe, 0x8a, 0x02,
5393 0xfe, 0x49, 0xf0, 0xfe, 0xa4, 0x02, 0xfe, 0x4a, 0xf0, 0xfe, 0xc2, 0x02,
5394 0xfe, 0x46, 0xf0, 0xfe, 0x54, 0x02, 0xfe, 0x47, 0xf0, 0xfe, 0x5a, 0x02,
5395 0xfe, 0x43, 0xf0, 0xfe, 0x48, 0x02, 0xfe, 0x44, 0xf0, 0xfe, 0x4c, 0x02,
5396 0xfe, 0x45, 0xf0, 0xfe, 0x50, 0x02, 0x18, 0x0a, 0xaa, 0x18, 0x06, 0x14,
5397 0xa1, 0x02, 0x2b, 0xfe, 0x00, 0x1c, 0xe7, 0xfe, 0x02, 0x1c, 0xe6, 0xfe,
5398 0x1e, 0x1c, 0xfe, 0xe9, 0x10, 0x01, 0xfe, 0x18, 0x18, 0xfe, 0xe7, 0x10,
5399 0xfe, 0x06, 0xfc, 0xce, 0x09, 0x70, 0x01, 0xa8, 0x02, 0x2b, 0x15, 0x59,
5400 0x39, 0xa2, 0x01, 0xfe, 0x58, 0x10, 0x09, 0x70, 0x01, 0x87, 0xfe, 0xbd,
5401 0x10, 0x09, 0x70, 0x01, 0x87, 0xfe, 0xad, 0x10, 0xfe, 0x16, 0x1c, 0xfe,
5402 0x58, 0x1c, 0x18, 0x06, 0x14, 0xa1, 0x2c, 0x1c, 0x2b, 0xfe, 0x3d, 0xf0,
5403 0xfe, 0x06, 0x02, 0x23, 0xfe, 0x98, 0x02, 0xfe, 0x5a, 0x1c, 0xf8, 0xfe,
5404 0x14, 0x1c, 0x15, 0xfe, 0x30, 0x00, 0x39, 0xa2, 0x01, 0xfe, 0x48, 0x10,
5405 0x18, 0x06, 0x14, 0xa1, 0x02, 0xd7, 0x22, 0x20, 0x07, 0x11, 0x35, 0xfe,
5406 0x69, 0x10, 0x18, 0x06, 0x14, 0xa1, 0xfe, 0x04, 0xec, 0x20, 0x4f, 0x43,
5407 0x13, 0x20, 0xfe, 0x05, 0xf6, 0xce, 0x01, 0xfe, 0x4a, 0x17, 0x08, 0x54,
5408 0x58, 0x37, 0x12, 0x2f, 0x42, 0x92, 0x01, 0xfe, 0x82, 0x16, 0x02, 0x2b,
5409 0x09, 0x46, 0x01, 0x0e, 0x07, 0x00, 0x66, 0x01, 0x73, 0xfe, 0x18, 0x10,
5410 0xfe, 0x41, 0x58, 0x09, 0xa4, 0x01, 0x0e, 0xfe, 0xc8, 0x54, 0x6b, 0xfe,
5411 0x10, 0x03, 0x01, 0xfe, 0x82, 0x16, 0x02, 0x2b, 0x2c, 0x4f, 0xfe, 0x02,
5412 0xe8, 0x2a, 0xfe, 0xbf, 0x57, 0xfe, 0x9e, 0x43, 0xfe, 0x77, 0x57, 0xfe,
5413 0x27, 0xf0, 0xfe, 0xe0, 0x01, 0xfe, 0x07, 0x4b, 0xfe, 0x20, 0xf0, 0xa7,
5414 0xfe, 0x40, 0x1c, 0x1c, 0xd9, 0xfe, 0x26, 0xf0, 0xfe, 0x5a, 0x03, 0xfe,
5415 0xa0, 0xf0, 0xfe, 0x48, 0x03, 0xfe, 0x11, 0xf0, 0xa7, 0xfe, 0xef, 0x10,
5416 0xfe, 0x9f, 0xf0, 0xfe, 0x68, 0x03, 0xf9, 0x10, 0xfe, 0x11, 0x00, 0x02,
5417 0x65, 0x2c, 0xfe, 0x48, 0x1c, 0xf9, 0x08, 0x05, 0x1b, 0xfe, 0x18, 0x13,
5418 0x21, 0x22, 0xa3, 0xb7, 0x13, 0xa3, 0x09, 0x46, 0x01, 0x0e, 0xb7, 0x78,
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5715 0xfe, 0x89, 0x49, 0x01, 0x0b, 0x26, 0xb1, 0x76, 0xfe, 0x89, 0x4a, 0x01,
5716 0x0b, 0x04, 0x51, 0x04, 0x22, 0xd3, 0x07, 0x06, 0xfe, 0x48, 0x13, 0xb8,
5717 0x13, 0xd3, 0xfe, 0x49, 0xf4, 0x00, 0x4d, 0x76, 0xa9, 0x67, 0xfe, 0x01,
5718 0xec, 0xfe, 0x27, 0x01, 0xfe, 0x89, 0x48, 0xff, 0x02, 0x00, 0x10, 0x27,
5719 0xfe, 0x2e, 0x16, 0x32, 0x07, 0xfe, 0xe3, 0x00, 0xfe, 0x20, 0x13, 0x1d,
5720 0xfe, 0x52, 0x16, 0x21, 0x13, 0xd4, 0x01, 0x4b, 0x22, 0xd4, 0x07, 0x06,
5721 0x4e, 0x08, 0x54, 0x06, 0x37, 0x04, 0x09, 0x48, 0x01, 0x0e, 0xfb, 0x8e,
5722 0x07, 0x11, 0xae, 0x09, 0x84, 0x01, 0x0e, 0x8e, 0x09, 0x5d, 0x01, 0xa8,
5723 0x04, 0x09, 0x84, 0x01, 0x0e, 0x8e, 0xfe, 0x80, 0xe7, 0x11, 0x07, 0x11,
5724 0x8a, 0xfe, 0x45, 0x58, 0x01, 0xf0, 0x8e, 0x04, 0x09, 0x48, 0x01, 0x0e,
5725 0x8e, 0x09, 0x5d, 0x01, 0xa8, 0x04, 0x09, 0x48, 0x01, 0x0e, 0xfe, 0x80,
5726 0x80, 0xfe, 0x80, 0x4c, 0xfe, 0x49, 0xe4, 0x11, 0xae, 0x09, 0x84, 0x01,
5727 0x0e, 0xfe, 0x80, 0x4c, 0x09, 0x5d, 0x01, 0x87, 0x04, 0x18, 0x11, 0x75,
5728 0x6c, 0xfe, 0x60, 0x01, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde, 0xfe, 0x24,
5729 0x1c, 0xfe, 0x1d, 0xf7, 0x1b, 0x97, 0xfe, 0xee, 0x16, 0x01, 0xfe, 0xf4,
5730 0x17, 0xad, 0x9a, 0x1b, 0x6c, 0xfe, 0x2c, 0x01, 0xfe, 0x2f, 0x19, 0x04,
5731 0xb9, 0x23, 0xfe, 0xde, 0x16, 0xfe, 0xda, 0x10, 0x18, 0x11, 0x75, 0x03,
5732 0xfe, 0x64, 0x01, 0xfe, 0x00, 0xf4, 0x1f, 0xfe, 0x18, 0x58, 0x03, 0xfe,
5733 0x66, 0x01, 0xfe, 0x19, 0x58, 0x9a, 0x1f, 0xfe, 0x3c, 0x90, 0xfe, 0x30,
5734 0xf4, 0x06, 0xfe, 0x3c, 0x50, 0x6c, 0xfe, 0x38, 0x00, 0xfe, 0x0f, 0x79,
5735 0xfe, 0x1c, 0xf7, 0x1f, 0x97, 0xfe, 0x38, 0x17, 0xfe, 0xb6, 0x14, 0x35,
5736 0x04, 0xb9, 0x23, 0xfe, 0x10, 0x17, 0xfe, 0x9c, 0x10, 0x18, 0x11, 0x75,
5737 0xfe, 0x83, 0x5a, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde, 0xfe, 0x1d, 0xf7,
5738 0x2e, 0x97, 0xfe, 0x5a, 0x17, 0xfe, 0x94, 0x14, 0xec, 0x9a, 0x2e, 0x6c,
5739 0x1a, 0xfe, 0xaf, 0x19, 0xfe, 0x98, 0xe7, 0x00, 0x04, 0xb9, 0x23, 0xfe,
5740 0x4e, 0x17, 0xfe, 0x6c, 0x10, 0x18, 0x11, 0x75, 0xfe, 0x30, 0xbc, 0xfe,
5741 0xb2, 0xbc, 0x9a, 0xcb, 0x6c, 0x1a, 0xfe, 0x0f, 0x79, 0xfe, 0x1c, 0xf7,
5742 0xcb, 0x97, 0xfe, 0x92, 0x17, 0xfe, 0x5c, 0x14, 0x35, 0x04, 0xb9, 0x23,
5743 0xfe, 0x7e, 0x17, 0xfe, 0x42, 0x10, 0xfe, 0x02, 0xf6, 0x11, 0x75, 0xfe,
5744 0x18, 0xfe, 0x60, 0xfe, 0x19, 0xfe, 0x61, 0xfe, 0x03, 0xa1, 0xfe, 0x1d,
5745 0xf7, 0x5b, 0x97, 0xfe, 0xb8, 0x17, 0xfe, 0x36, 0x14, 0xfe, 0x1c, 0x13,
5746 0x9a, 0x5b, 0x41, 0xfe, 0x83, 0x58, 0xfe, 0xaf, 0x19, 0xfe, 0x80, 0xe7,
5747 0x11, 0xfe, 0x81, 0xe7, 0x11, 0x12, 0xfe, 0xdd, 0x00, 0x6a, 0x2a, 0x04,
5748 0x6a, 0x2a, 0xfe, 0x12, 0x45, 0x23, 0xfe, 0xa8, 0x17, 0x15, 0x06, 0x39,
5749 0xa0, 0xb4, 0x02, 0x2b, 0xfe, 0x39, 0xf0, 0xfe, 0xfc, 0x17, 0x21, 0x04,
5750 0xfe, 0x7e, 0x18, 0x1e, 0x19, 0x66, 0x0f, 0x0d, 0x04, 0x75, 0x03, 0xd2,
5751 0x1e, 0x06, 0xfe, 0xef, 0x12, 0xfe, 0xe1, 0x10, 0x7c, 0x6f, 0x4f, 0x32,
5752 0x07, 0x2f, 0xfe, 0x3c, 0x13, 0xf1, 0xfe, 0x42, 0x13, 0x42, 0x92, 0x09,
5753 0x48, 0x01, 0x0e, 0xbb, 0xeb, 0xfe, 0x41, 0x48, 0xfe, 0x45, 0x48, 0x01,
5754 0xf0, 0xfe, 0x00, 0xcc, 0xbb, 0xfe, 0xf3, 0x13, 0x43, 0x78, 0x07, 0x11,
5755 0xac, 0x09, 0x84, 0x01, 0x0e, 0xfe, 0x80, 0x4c, 0x01, 0x73, 0xfe, 0x16,
5756 0x10, 0x07, 0x82, 0x8b, 0xfe, 0x40, 0x14, 0xfe, 0x24, 0x12, 0xfe, 0x14,
5757 0x56, 0xfe, 0xd6, 0xf0, 0xfe, 0x1c, 0x18, 0x18, 0x0a, 0x04, 0xfe, 0x9c,
5758 0xe7, 0x0a, 0x10, 0xfe, 0x15, 0x00, 0x64, 0x79, 0x2a, 0x01, 0xe3, 0x18,
5759 0x06, 0x04, 0x42, 0x92, 0x08, 0x54, 0x1b, 0x37, 0x12, 0x2f, 0x01, 0x73,
5760 0x18, 0x06, 0x04, 0xfe, 0x38, 0x90, 0xfe, 0xba, 0x90, 0x3a, 0xce, 0x3b,
5761 0xcf, 0xfe, 0x48, 0x55, 0x35, 0xfe, 0xc9, 0x55, 0x04, 0x22, 0xa3, 0x77,
5762 0x13, 0xa3, 0x04, 0x09, 0xa4, 0x01, 0x0e, 0xfe, 0x41, 0x48, 0x09, 0x46,
5763 0x01, 0x0e, 0xfe, 0x49, 0x44, 0x17, 0xfe, 0xe8, 0x18, 0x77, 0x78, 0x04,
5764 0x09, 0x48, 0x01, 0x0e, 0x07, 0x11, 0x4e, 0x09, 0x5d, 0x01, 0xa8, 0x09,
5765 0x46, 0x01, 0x0e, 0x77, 0x78, 0x04, 0xfe, 0x4e, 0xe4, 0x19, 0x6b, 0xfe,
5766 0x1c, 0x19, 0x03, 0xfe, 0x90, 0x00, 0xfe, 0x3a, 0x45, 0xfe, 0x2c, 0x10,
5767 0xfe, 0x4e, 0xe4, 0xc9, 0x6b, 0xfe, 0x2e, 0x19, 0x03, 0xfe, 0x92, 0x00,
5768 0xfe, 0x02, 0xe6, 0x1a, 0xe5, 0xfe, 0x4e, 0xe4, 0xfe, 0x0b, 0x00, 0x6b,
5769 0xfe, 0x40, 0x19, 0x03, 0xfe, 0x94, 0x00, 0xfe, 0x02, 0xe6, 0x1f, 0xfe,
5770 0x08, 0x10, 0x03, 0xfe, 0x96, 0x00, 0xfe, 0x02, 0xe6, 0x6d, 0xfe, 0x4e,
5771 0x45, 0xea, 0xba, 0xff, 0x04, 0x68, 0x54, 0xe7, 0x1e, 0x6e, 0xfe, 0x08,
5772 0x1c, 0xfe, 0x67, 0x19, 0xfe, 0x0a, 0x1c, 0xfe, 0x1a, 0xf4, 0xfe, 0x00,
5773 0x04, 0xea, 0xfe, 0x48, 0xf4, 0x19, 0x7a, 0xfe, 0x74, 0x19, 0x0f, 0x19,
5774 0x04, 0x07, 0x7e, 0xfe, 0x5a, 0xf0, 0xfe, 0x84, 0x19, 0x25, 0xfe, 0x09,
5775 0x00, 0xfe, 0x34, 0x10, 0x07, 0x1a, 0xfe, 0x5a, 0xf0, 0xfe, 0x92, 0x19,
5776 0x25, 0xca, 0xfe, 0x26, 0x10, 0x07, 0x19, 0x66, 0x25, 0x6d, 0xe5, 0x07,
5777 0x0a, 0x66, 0x25, 0x9e, 0xfe, 0x0e, 0x10, 0x07, 0x06, 0x66, 0x25, 0x59,
5778 0xa9, 0xb8, 0x04, 0x15, 0xfe, 0x09, 0x00, 0x01, 0x36, 0xfe, 0x04, 0xfe,
5779 0x81, 0x03, 0x83, 0xfe, 0x40, 0x5c, 0x04, 0x1c, 0xf7, 0xfe, 0x14, 0xf0,
5780 0x0b, 0x27, 0xfe, 0xd6, 0x19, 0x1c, 0xf7, 0x7b, 0xf7, 0xfe, 0x82, 0xf0,
5781 0xfe, 0xda, 0x19, 0x04, 0xff, 0xcc, 0x00, 0x00,
5784 static unsigned short _adv_asc38C0800_size = sizeof(_adv_asc38C0800_buf); /* 0x14E1 */
5785 static ADV_DCNT _adv_asc38C0800_chksum = 0x050D3FD8UL; /* Expanded little-endian checksum. */
5787 /* Microcode buffer is kept after initialization for error recovery. */
5788 static unsigned char _adv_asc38C1600_buf[] = {
5789 0x00, 0x00, 0x00, 0xf2, 0x00, 0x16, 0x00, 0xfc, 0x00, 0x10, 0x00, 0xf0,
5790 0x18, 0xe4, 0x01, 0x00, 0x04, 0x1e, 0x48, 0xe4, 0x03, 0xf6, 0xf7, 0x13,
5791 0x2e, 0x1e, 0x02, 0x00, 0x07, 0x17, 0xc0, 0x5f, 0x00, 0xfa, 0xff, 0xff,
5792 0x04, 0x00, 0x00, 0xf6, 0x09, 0xe7, 0x82, 0xe7, 0x85, 0xf0, 0x86, 0xf0,
5793 0x4e, 0x10, 0x9e, 0xe7, 0xff, 0x00, 0x55, 0xf0, 0x01, 0xf6, 0x03, 0x00,
5794 0x98, 0x57, 0x01, 0xe6, 0x00, 0xea, 0x00, 0xec, 0x01, 0xfa, 0x18, 0xf4,
5795 0x08, 0x00, 0xf0, 0x1d, 0x38, 0x54, 0x32, 0xf0, 0x10, 0x00, 0xc2, 0x0e,
5796 0x1e, 0xf0, 0xd5, 0xf0, 0xbc, 0x00, 0x4b, 0xe4, 0x00, 0xe6, 0xb1, 0xf0,
5797 0xb4, 0x00, 0x02, 0x13, 0x3e, 0x1c, 0xc8, 0x47, 0x3e, 0x00, 0xd8, 0x01,
5798 0x06, 0x13, 0x0c, 0x1c, 0x5e, 0x1e, 0x00, 0x57, 0xc8, 0x57, 0x01, 0xfc,
5799 0xbc, 0x0e, 0xa2, 0x12, 0xb9, 0x54, 0x00, 0x80, 0x62, 0x0a, 0x5a, 0x12,
5800 0xc8, 0x15, 0x3e, 0x1e, 0x18, 0x40, 0xbd, 0x56, 0x03, 0xe6, 0x01, 0xea,
5801 0x5c, 0xf0, 0x0f, 0x00, 0x20, 0x00, 0x6c, 0x01, 0x6e, 0x01, 0x04, 0x12,
5802 0x04, 0x13, 0xbb, 0x55, 0x3c, 0x56, 0x3e, 0x57, 0x03, 0x58, 0x4a, 0xe4,
5803 0x40, 0x00, 0xb6, 0x00, 0xbb, 0x00, 0xc0, 0x00, 0x00, 0x01, 0x01, 0x01,
5804 0x3e, 0x01, 0x58, 0x0a, 0x44, 0x10, 0x0a, 0x12, 0x4c, 0x1c, 0x4e, 0x1c,
5805 0x02, 0x4a, 0x30, 0xe4, 0x05, 0xe6, 0x0c, 0x00, 0x3c, 0x00, 0x80, 0x00,
5806 0x24, 0x01, 0x3c, 0x01, 0x68, 0x01, 0x6a, 0x01, 0x70, 0x01, 0x72, 0x01,
5807 0x74, 0x01, 0x76, 0x01, 0x78, 0x01, 0x7c, 0x01, 0xc6, 0x0e, 0x0c, 0x10,
5808 0xac, 0x12, 0xae, 0x12, 0x16, 0x1a, 0x32, 0x1c, 0x6e, 0x1e, 0x02, 0x48,
5809 0x3a, 0x55, 0xc9, 0x57, 0x02, 0xee, 0x5b, 0xf0, 0x03, 0xf7, 0x06, 0xf7,
5810 0x03, 0xfc, 0x06, 0x00, 0x1e, 0x00, 0xbe, 0x00, 0xe1, 0x00, 0x0c, 0x12,
5811 0x18, 0x1a, 0x70, 0x1a, 0x30, 0x1c, 0x38, 0x1c, 0x10, 0x44, 0x00, 0x4c,
5812 0xb0, 0x57, 0x40, 0x5c, 0x4d, 0xe4, 0x04, 0xea, 0x5d, 0xf0, 0xa7, 0xf0,
5813 0x04, 0xf6, 0x02, 0xfc, 0x05, 0x00, 0x09, 0x00, 0x19, 0x00, 0x32, 0x00,
5814 0x33, 0x00, 0x34, 0x00, 0x36, 0x00, 0x98, 0x00, 0x9e, 0x00, 0xcc, 0x00,
5815 0x20, 0x01, 0x4e, 0x01, 0x79, 0x01, 0x3c, 0x09, 0x68, 0x0d, 0x02, 0x10,
5816 0x04, 0x10, 0x3a, 0x10, 0x08, 0x12, 0x0a, 0x13, 0x40, 0x16, 0x50, 0x16,
5817 0x00, 0x17, 0x4a, 0x19, 0x00, 0x4e, 0x00, 0x54, 0x01, 0x58, 0x00, 0xdc,
5818 0x05, 0xf0, 0x09, 0xf0, 0x59, 0xf0, 0xb8, 0xf0, 0x48, 0xf4, 0x0e, 0xf7,
5819 0x0a, 0x00, 0x9b, 0x00, 0x9c, 0x00, 0xa4, 0x00, 0xb5, 0x00, 0xba, 0x00,
5820 0xd0, 0x00, 0xe7, 0x00, 0xf0, 0x03, 0x69, 0x08, 0xe9, 0x09, 0x5c, 0x0c,
5821 0xb6, 0x12, 0xbc, 0x19, 0xd8, 0x1b, 0x20, 0x1c, 0x34, 0x1c, 0x36, 0x1c,
5822 0x42, 0x1d, 0x08, 0x44, 0x38, 0x44, 0x91, 0x44, 0x0a, 0x45, 0x48, 0x46,
5823 0x89, 0x48, 0x68, 0x54, 0x83, 0x55, 0x83, 0x59, 0x31, 0xe4, 0x02, 0xe6,
5824 0x07, 0xf0, 0x08, 0xf0, 0x0b, 0xf0, 0x0c, 0xf0, 0x4b, 0xf4, 0x04, 0xf8,
5825 0x05, 0xf8, 0x02, 0xfa, 0x03, 0xfa, 0x04, 0xfc, 0x05, 0xfc, 0x07, 0x00,
5826 0xa8, 0x00, 0xaa, 0x00, 0xb9, 0x00, 0xe0, 0x00, 0xe5, 0x00, 0x22, 0x01,
5827 0x26, 0x01, 0x60, 0x01, 0x7a, 0x01, 0x82, 0x01, 0xc8, 0x01, 0xca, 0x01,
5828 0x86, 0x02, 0x6a, 0x03, 0x18, 0x05, 0xb2, 0x07, 0x68, 0x08, 0x10, 0x0d,
5829 0x06, 0x10, 0x0a, 0x10, 0x0e, 0x10, 0x12, 0x10, 0x60, 0x10, 0xed, 0x10,
5830 0xf3, 0x10, 0x06, 0x12, 0x10, 0x12, 0x1e, 0x12, 0x0c, 0x13, 0x0e, 0x13,
5831 0x10, 0x13, 0xfe, 0x9c, 0xf0, 0x35, 0x05, 0xfe, 0xec, 0x0e, 0xff, 0x10,
5832 0x00, 0x00, 0xe9, 0xfe, 0x34, 0x1f, 0x00, 0xe8, 0xfe, 0x88, 0x01, 0xff,
5833 0x03, 0x00, 0x00, 0xfe, 0x93, 0x15, 0xfe, 0x0f, 0x05, 0xff, 0x38, 0x00,
5834 0x00, 0xfe, 0x57, 0x24, 0x00, 0xfe, 0x4c, 0x00, 0x65, 0xff, 0x04, 0x00,
5835 0x00, 0x1a, 0xff, 0x09, 0x00, 0x00, 0xff, 0x08, 0x01, 0x01, 0xff, 0x08,
5836 0xff, 0xff, 0xff, 0x27, 0x00, 0x00, 0xff, 0x10, 0xff, 0xff, 0xff, 0x13,
5837 0x00, 0x00, 0xfe, 0x78, 0x56, 0xfe, 0x34, 0x12, 0xff, 0x21, 0x00, 0x00,
5838 0xfe, 0x04, 0xf7, 0xe8, 0x37, 0x7d, 0x0d, 0x01, 0xfe, 0x4a, 0x11, 0xfe,
5839 0x04, 0xf7, 0xe8, 0x7d, 0x0d, 0x51, 0x37, 0xfe, 0x3d, 0xf0, 0xfe, 0x0c,
5840 0x02, 0xfe, 0x20, 0xf0, 0xbc, 0xfe, 0x91, 0xf0, 0xfe, 0xf8, 0x01, 0xfe,
5841 0x90, 0xf0, 0xfe, 0xf8, 0x01, 0xfe, 0x8f, 0xf0, 0xbc, 0x03, 0x67, 0x4d,
5842 0x05, 0xfe, 0x08, 0x0f, 0x01, 0xfe, 0x78, 0x0f, 0xfe, 0xdd, 0x12, 0x05,
5843 0xfe, 0x0e, 0x03, 0xfe, 0x28, 0x1c, 0x03, 0xfe, 0xa6, 0x00, 0xfe, 0xd1,
5844 0x12, 0x3e, 0x22, 0xfe, 0xa6, 0x00, 0xac, 0xfe, 0x48, 0xf0, 0xfe, 0x90,
5845 0x02, 0xfe, 0x49, 0xf0, 0xfe, 0xaa, 0x02, 0xfe, 0x4a, 0xf0, 0xfe, 0xc8,
5846 0x02, 0xfe, 0x46, 0xf0, 0xfe, 0x5a, 0x02, 0xfe, 0x47, 0xf0, 0xfe, 0x60,
5847 0x02, 0xfe, 0x43, 0xf0, 0xfe, 0x4e, 0x02, 0xfe, 0x44, 0xf0, 0xfe, 0x52,
5848 0x02, 0xfe, 0x45, 0xf0, 0xfe, 0x56, 0x02, 0x1c, 0x0d, 0xa2, 0x1c, 0x07,
5849 0x22, 0xb7, 0x05, 0x35, 0xfe, 0x00, 0x1c, 0xfe, 0xf1, 0x10, 0xfe, 0x02,
5850 0x1c, 0xf5, 0xfe, 0x1e, 0x1c, 0xfe, 0xe9, 0x10, 0x01, 0x5f, 0xfe, 0xe7,
5851 0x10, 0xfe, 0x06, 0xfc, 0xde, 0x0a, 0x81, 0x01, 0xa3, 0x05, 0x35, 0x1f,
5852 0x95, 0x47, 0xb8, 0x01, 0xfe, 0xe4, 0x11, 0x0a, 0x81, 0x01, 0x5c, 0xfe,
5853 0xbd, 0x10, 0x0a, 0x81, 0x01, 0x5c, 0xfe, 0xad, 0x10, 0xfe, 0x16, 0x1c,
5854 0xfe, 0x58, 0x1c, 0x1c, 0x07, 0x22, 0xb7, 0x37, 0x2a, 0x35, 0xfe, 0x3d,
5855 0xf0, 0xfe, 0x0c, 0x02, 0x2b, 0xfe, 0x9e, 0x02, 0xfe, 0x5a, 0x1c, 0xfe,
5856 0x12, 0x1c, 0xfe, 0x14, 0x1c, 0x1f, 0xfe, 0x30, 0x00, 0x47, 0xb8, 0x01,
5857 0xfe, 0xd4, 0x11, 0x1c, 0x07, 0x22, 0xb7, 0x05, 0xe9, 0x21, 0x2c, 0x09,
5858 0x1a, 0x31, 0xfe, 0x69, 0x10, 0x1c, 0x07, 0x22, 0xb7, 0xfe, 0x04, 0xec,
5859 0x2c, 0x60, 0x01, 0xfe, 0x1e, 0x1e, 0x20, 0x2c, 0xfe, 0x05, 0xf6, 0xde,
5860 0x01, 0xfe, 0x62, 0x1b, 0x01, 0x0c, 0x61, 0x4a, 0x44, 0x15, 0x56, 0x51,
5861 0x01, 0xfe, 0x9e, 0x1e, 0x01, 0xfe, 0x96, 0x1a, 0x05, 0x35, 0x0a, 0x57,
5862 0x01, 0x18, 0x09, 0x00, 0x36, 0x01, 0x85, 0xfe, 0x18, 0x10, 0xfe, 0x41,
5863 0x58, 0x0a, 0xba, 0x01, 0x18, 0xfe, 0xc8, 0x54, 0x7b, 0xfe, 0x1c, 0x03,
5864 0x01, 0xfe, 0x96, 0x1a, 0x05, 0x35, 0x37, 0x60, 0xfe, 0x02, 0xe8, 0x30,
5865 0xfe, 0xbf, 0x57, 0xfe, 0x9e, 0x43, 0xfe, 0x77, 0x57, 0xfe, 0x27, 0xf0,
5866 0xfe, 0xe4, 0x01, 0xfe, 0x07, 0x4b, 0xfe, 0x20, 0xf0, 0xbc, 0xfe, 0x40,
5867 0x1c, 0x2a, 0xeb, 0xfe, 0x26, 0xf0, 0xfe, 0x66, 0x03, 0xfe, 0xa0, 0xf0,
5868 0xfe, 0x54, 0x03, 0xfe, 0x11, 0xf0, 0xbc, 0xfe, 0xef, 0x10, 0xfe, 0x9f,
5869 0xf0, 0xfe, 0x74, 0x03, 0xfe, 0x46, 0x1c, 0x19, 0xfe, 0x11, 0x00, 0x05,
5870 0x70, 0x37, 0xfe, 0x48, 0x1c, 0xfe, 0x46, 0x1c, 0x01, 0x0c, 0x06, 0x28,
5871 0xfe, 0x18, 0x13, 0x26, 0x21, 0xb9, 0xc7, 0x20, 0xb9, 0x0a, 0x57, 0x01,
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6315 0x0f, 0xfe, 0x03, 0x80, 0x04, 0xfe, 0x83, 0x83, 0x33, 0x0b, 0x77, 0x0e,
6316 0xa8, 0x02, 0xff, 0x66, 0x00, 0x00,
6319 static unsigned short _adv_asc38C1600_size = sizeof(_adv_asc38C1600_buf); /* 0x1673 */
6320 static ADV_DCNT _adv_asc38C1600_chksum = 0x0604EF77UL; /* Expanded little-endian checksum. */
6322 static void AscInitQLinkVar(ASC_DVC_VAR *asc_dvc)
6328 iop_base = asc_dvc->iop_base;
6329 AscPutRiscVarFreeQHead(iop_base, 1);
6330 AscPutRiscVarDoneQTail(iop_base, asc_dvc->max_total_qng);
6331 AscPutVarFreeQHead(iop_base, 1);
6332 AscPutVarDoneQTail(iop_base, asc_dvc->max_total_qng);
6333 AscWriteLramByte(iop_base, ASCV_BUSY_QHEAD_B,
6334 (uchar)((int)asc_dvc->max_total_qng + 1));
6335 AscWriteLramByte(iop_base, ASCV_DISC1_QHEAD_B,
6336 (uchar)((int)asc_dvc->max_total_qng + 2));
6337 AscWriteLramByte(iop_base, (ushort)ASCV_TOTAL_READY_Q_B,
6338 asc_dvc->max_total_qng);
6339 AscWriteLramWord(iop_base, ASCV_ASCDVC_ERR_CODE_W, 0);
6340 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6341 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, 0);
6342 AscWriteLramByte(iop_base, ASCV_SCSIBUSY_B, 0);
6343 AscWriteLramByte(iop_base, ASCV_WTM_FLAG_B, 0);
6344 AscPutQDoneInProgress(iop_base, 0);
6345 lram_addr = ASC_QADR_BEG;
6346 for (i = 0; i < 32; i++, lram_addr += 2) {
6347 AscWriteLramWord(iop_base, lram_addr, 0);
6351 static ushort AscInitMicroCodeVar(ASC_DVC_VAR *asc_dvc)
6359 iop_base = asc_dvc->iop_base;
6361 for (i = 0; i <= ASC_MAX_TID; i++) {
6362 AscPutMCodeInitSDTRAtID(iop_base, i,
6363 asc_dvc->cfg->sdtr_period_offset[i]);
6366 AscInitQLinkVar(asc_dvc);
6367 AscWriteLramByte(iop_base, ASCV_DISC_ENABLE_B,
6368 asc_dvc->cfg->disc_enable);
6369 AscWriteLramByte(iop_base, ASCV_HOSTSCSI_ID_B,
6370 ASC_TID_TO_TARGET_ID(asc_dvc->cfg->chip_scsi_id));
6372 /* Align overrun buffer on an 8 byte boundary. */
6373 phy_addr = virt_to_bus(asc_dvc->cfg->overrun_buf);
6374 phy_addr = cpu_to_le32((phy_addr + 7) & ~0x7);
6375 AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_PADDR_D,
6376 (uchar *)&phy_addr, 1);
6377 phy_size = cpu_to_le32(ASC_OVERRUN_BSIZE - 8);
6378 AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_BSIZE_D,
6379 (uchar *)&phy_size, 1);
6381 asc_dvc->cfg->mcode_date =
6382 AscReadLramWord(iop_base, (ushort)ASCV_MC_DATE_W);
6383 asc_dvc->cfg->mcode_version =
6384 AscReadLramWord(iop_base, (ushort)ASCV_MC_VER_W);
6386 AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR);
6387 if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) {
6388 asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR;
6391 if (AscStartChip(iop_base) != 1) {
6392 asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP;
6399 static ushort AscInitAsc1000Driver(ASC_DVC_VAR *asc_dvc)
6404 iop_base = asc_dvc->iop_base;
6406 if ((asc_dvc->dvc_cntl & ASC_CNTL_RESET_SCSI) &&
6407 !(asc_dvc->init_state & ASC_INIT_RESET_SCSI_DONE)) {
6408 AscResetChipAndScsiBus(asc_dvc);
6409 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
6411 asc_dvc->init_state |= ASC_INIT_STATE_BEG_LOAD_MC;
6412 if (asc_dvc->err_code != 0)
6414 if (!AscFindSignature(asc_dvc->iop_base)) {
6415 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
6418 AscDisableInterrupt(iop_base);
6419 warn_code |= AscInitLram(asc_dvc);
6420 if (asc_dvc->err_code != 0)
6422 ASC_DBG(1, "_asc_mcode_chksum 0x%lx\n", (ulong)_asc_mcode_chksum);
6423 if (AscLoadMicroCode(iop_base, 0, _asc_mcode_buf,
6424 _asc_mcode_size) != _asc_mcode_chksum) {
6425 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
6428 warn_code |= AscInitMicroCodeVar(asc_dvc);
6429 asc_dvc->init_state |= ASC_INIT_STATE_END_LOAD_MC;
6430 AscEnableInterrupt(iop_base);
6435 * Load the Microcode
6437 * Write the microcode image to RISC memory starting at address 0.
6439 * The microcode is stored compressed in the following format:
6441 * 254 word (508 byte) table indexed by byte code followed
6442 * by the following byte codes:
6445 * 00: Emit word 0 in table.
6446 * 01: Emit word 1 in table.
6448 * FD: Emit word 253 in table.
6451 * FE WW WW: (3 byte code) Word to emit is the next word WW WW.
6452 * FF BB WW WW: (4 byte code) Emit BB count times next word WW WW.
6454 * Returns 0 or an error if the checksum doesn't match
6456 static int AdvLoadMicrocode(AdvPortAddr iop_base, unsigned char *buf, int size,
6457 int memsize, int chksum)
6459 int i, j, end, len = 0;
6462 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
6464 for (i = 253 * 2; i < size; i++) {
6465 if (buf[i] == 0xff) {
6466 unsigned short word = (buf[i + 3] << 8) | buf[i + 2];
6467 for (j = 0; j < buf[i + 1]; j++) {
6468 AdvWriteWordAutoIncLram(iop_base, word);
6472 } else if (buf[i] == 0xfe) {
6473 unsigned short word = (buf[i + 2] << 8) | buf[i + 1];
6474 AdvWriteWordAutoIncLram(iop_base, word);
6478 unsigned char off = buf[i] * 2;
6479 unsigned short word = (buf[off + 1] << 8) | buf[off];
6480 AdvWriteWordAutoIncLram(iop_base, word);
6487 while (len < memsize) {
6488 AdvWriteWordAutoIncLram(iop_base, 0);
6492 /* Verify the microcode checksum. */
6494 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
6496 for (len = 0; len < end; len += 2) {
6497 sum += AdvReadWordAutoIncLram(iop_base);
6501 return ASC_IERR_MCODE_CHKSUM;
6509 * Return the physical address of 'vaddr' and set '*lenp' to the
6510 * number of physically contiguous bytes that follow 'vaddr'.
6511 * 'flag' indicates the type of structure whose physical address
6512 * is being translated.
6514 * Note: Because Linux currently doesn't page the kernel and all
6515 * kernel buffers are physically contiguous, leave '*lenp' unchanged.
6518 DvcGetPhyAddr(ADV_DVC_VAR *asc_dvc, ADV_SCSI_REQ_Q *scsiq,
6519 uchar *vaddr, ADV_SDCNT *lenp, int flag)
6521 ADV_PADDR paddr = virt_to_bus(vaddr);
6523 ASC_DBG(4, "vaddr 0x%p, lenp 0x%p *lenp %lu, paddr 0x%lx\n",
6524 vaddr, lenp, (ulong)*((ulong *)lenp), (ulong)paddr);
6529 static void AdvBuildCarrierFreelist(struct adv_dvc_var *asc_dvc)
6533 ADV_PADDR carr_paddr;
6535 BUG_ON(!asc_dvc->carrier_buf);
6537 carrp = (ADV_CARR_T *) ADV_16BALIGN(asc_dvc->carrier_buf);
6538 asc_dvc->carr_freelist = NULL;
6539 if (carrp == asc_dvc->carrier_buf) {
6540 buf_size = ADV_CARRIER_BUFSIZE;
6542 buf_size = ADV_CARRIER_BUFSIZE - sizeof(ADV_CARR_T);
6546 /* Get physical address of the carrier 'carrp'. */
6547 ADV_DCNT contig_len = sizeof(ADV_CARR_T);
6548 carr_paddr = cpu_to_le32(DvcGetPhyAddr(asc_dvc, NULL,
6550 (ADV_SDCNT *)&contig_len,
6551 ADV_IS_CARRIER_FLAG));
6553 buf_size -= sizeof(ADV_CARR_T);
6556 * If the current carrier is not physically contiguous, then
6557 * maybe there was a page crossing. Try the next carrier
6558 * aligned start address.
6560 if (contig_len < sizeof(ADV_CARR_T)) {
6565 carrp->carr_pa = carr_paddr;
6566 carrp->carr_va = cpu_to_le32(ADV_VADDR_TO_U32(carrp));
6569 * Insert the carrier at the beginning of the freelist.
6572 cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->carr_freelist));
6573 asc_dvc->carr_freelist = carrp;
6576 } while (buf_size > 0);
6580 * Send an idle command to the chip and wait for completion.
6582 * Command completion is polled for once per microsecond.
6584 * The function can be called from anywhere including an interrupt handler.
6585 * But the function is not re-entrant, so it uses the DvcEnter/LeaveCritical()
6586 * functions to prevent reentrancy.
6589 * ADV_TRUE - command completed successfully
6590 * ADV_FALSE - command failed
6591 * ADV_ERROR - command timed out
6594 AdvSendIdleCmd(ADV_DVC_VAR *asc_dvc,
6595 ushort idle_cmd, ADV_DCNT idle_cmd_parameter)
6599 AdvPortAddr iop_base;
6601 iop_base = asc_dvc->iop_base;
6604 * Clear the idle command status which is set by the microcode
6605 * to a non-zero value to indicate when the command is completed.
6606 * The non-zero result is one of the IDLE_CMD_STATUS_* values
6608 AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS, (ushort)0);
6611 * Write the idle command value after the idle command parameter
6612 * has been written to avoid a race condition. If the order is not
6613 * followed, the microcode may process the idle command before the
6614 * parameters have been written to LRAM.
6616 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IDLE_CMD_PARAMETER,
6617 cpu_to_le32(idle_cmd_parameter));
6618 AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD, idle_cmd);
6621 * Tickle the RISC to tell it to process the idle command.
6623 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_B);
6624 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
6626 * Clear the tickle value. In the ASC-3550 the RISC flag
6627 * command 'clr_tickle_b' does not work unless the host
6630 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_NOP);
6633 /* Wait for up to 100 millisecond for the idle command to timeout. */
6634 for (i = 0; i < SCSI_WAIT_100_MSEC; i++) {
6635 /* Poll once each microsecond for command completion. */
6636 for (j = 0; j < SCSI_US_PER_MSEC; j++) {
6637 AdvReadWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS,
6645 BUG(); /* The idle command should never timeout. */
6650 * Reset SCSI Bus and purge all outstanding requests.
6653 * ADV_TRUE(1) - All requests are purged and SCSI Bus is reset.
6654 * ADV_FALSE(0) - Microcode command failed.
6655 * ADV_ERROR(-1) - Microcode command timed-out. Microcode or IC
6656 * may be hung which requires driver recovery.
6658 static int AdvResetSB(ADV_DVC_VAR *asc_dvc)
6663 * Send the SCSI Bus Reset idle start idle command which asserts
6664 * the SCSI Bus Reset signal.
6666 status = AdvSendIdleCmd(asc_dvc, (ushort)IDLE_CMD_SCSI_RESET_START, 0L);
6667 if (status != ADV_TRUE) {
6672 * Delay for the specified SCSI Bus Reset hold time.
6674 * The hold time delay is done on the host because the RISC has no
6675 * microsecond accurate timer.
6677 udelay(ASC_SCSI_RESET_HOLD_TIME_US);
6680 * Send the SCSI Bus Reset end idle command which de-asserts
6681 * the SCSI Bus Reset signal and purges any pending requests.
6683 status = AdvSendIdleCmd(asc_dvc, (ushort)IDLE_CMD_SCSI_RESET_END, 0L);
6684 if (status != ADV_TRUE) {
6688 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
6694 * Initialize the ASC-3550.
6696 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
6698 * For a non-fatal error return a warning code. If there are no warnings
6699 * then 0 is returned.
6701 * Needed after initialization for error recovery.
6703 static int AdvInitAsc3550Driver(ADV_DVC_VAR *asc_dvc)
6705 AdvPortAddr iop_base;
6714 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */
6715 ushort wdtr_able = 0, sdtr_able, tagqng_able;
6716 uchar max_cmd[ADV_MAX_TID + 1];
6718 /* If there is already an error, don't continue. */
6719 if (asc_dvc->err_code != 0)
6723 * The caller must set 'chip_type' to ADV_CHIP_ASC3550.
6725 if (asc_dvc->chip_type != ADV_CHIP_ASC3550) {
6726 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
6731 iop_base = asc_dvc->iop_base;
6734 * Save the RISC memory BIOS region before writing the microcode.
6735 * The BIOS may already be loaded and using its RISC LRAM region
6736 * so its region must be saved and restored.
6738 * Note: This code makes the assumption, which is currently true,
6739 * that a chip reset does not clear RISC LRAM.
6741 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
6742 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
6747 * Save current per TID negotiated values.
6749 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] == 0x55AA) {
6750 ushort bios_version, major, minor;
6753 bios_mem[(ASC_MC_BIOS_VERSION - ASC_MC_BIOSMEM) / 2];
6754 major = (bios_version >> 12) & 0xF;
6755 minor = (bios_version >> 8) & 0xF;
6756 if (major < 3 || (major == 3 && minor == 1)) {
6757 /* BIOS 3.1 and earlier location of 'wdtr_able' variable. */
6758 AdvReadWordLram(iop_base, 0x120, wdtr_able);
6760 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
6763 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
6764 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
6765 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
6766 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
6770 asc_dvc->err_code = AdvLoadMicrocode(iop_base, _adv_asc3550_buf,
6771 _adv_asc3550_size, ADV_3550_MEMSIZE,
6772 _adv_asc3550_chksum);
6773 if (asc_dvc->err_code)
6777 * Restore the RISC memory BIOS region.
6779 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
6780 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
6785 * Calculate and write the microcode code checksum to the microcode
6786 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
6788 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
6789 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
6791 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
6792 for (word = begin_addr; word < end_addr; word += 2) {
6793 code_sum += AdvReadWordAutoIncLram(iop_base);
6795 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
6798 * Read and save microcode version and date.
6800 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
6801 asc_dvc->cfg->mcode_date);
6802 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
6803 asc_dvc->cfg->mcode_version);
6806 * Set the chip type to indicate the ASC3550.
6808 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC3550);
6811 * If the PCI Configuration Command Register "Parity Error Response
6812 * Control" Bit was clear (0), then set the microcode variable
6813 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
6814 * to ignore DMA parity errors.
6816 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
6817 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
6818 word |= CONTROL_FLAG_IGNORE_PERR;
6819 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
6823 * For ASC-3550, setting the START_CTL_EMFU [3:2] bits sets a FIFO
6824 * threshold of 128 bytes. This register is only accessible to the host.
6826 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
6827 START_CTL_EMFU | READ_CMD_MRM);
6830 * Microcode operating variables for WDTR, SDTR, and command tag
6831 * queuing will be set in slave_configure() based on what a
6832 * device reports it is capable of in Inquiry byte 7.
6834 * If SCSI Bus Resets have been disabled, then directly set
6835 * SDTR and WDTR from the EEPROM configuration. This will allow
6836 * the BIOS and warm boot to work without a SCSI bus hang on
6837 * the Inquiry caused by host and target mismatched DTR values.
6838 * Without the SCSI Bus Reset, before an Inquiry a device can't
6839 * be assumed to be in Asynchronous, Narrow mode.
6841 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
6842 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
6843 asc_dvc->wdtr_able);
6844 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
6845 asc_dvc->sdtr_able);
6849 * Set microcode operating variables for SDTR_SPEED1, SDTR_SPEED2,
6850 * SDTR_SPEED3, and SDTR_SPEED4 based on the ULTRA EEPROM per TID
6851 * bitmask. These values determine the maximum SDTR speed negotiated
6854 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
6855 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
6856 * without determining here whether the device supports SDTR.
6858 * 4-bit speed SDTR speed name
6859 * =========== ===============
6860 * 0000b (0x0) SDTR disabled
6862 * 0010b (0x2) 10 Mhz
6863 * 0011b (0x3) 20 Mhz (Ultra)
6864 * 0100b (0x4) 40 Mhz (LVD/Ultra2)
6865 * 0101b (0x5) 80 Mhz (LVD2/Ultra3)
6866 * 0110b (0x6) Undefined
6868 * 1111b (0xF) Undefined
6871 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
6872 if (ADV_TID_TO_TIDMASK(tid) & asc_dvc->ultra_able) {
6873 /* Set Ultra speed for TID 'tid'. */
6874 word |= (0x3 << (4 * (tid % 4)));
6876 /* Set Fast speed for TID 'tid'. */
6877 word |= (0x2 << (4 * (tid % 4)));
6879 if (tid == 3) { /* Check if done with sdtr_speed1. */
6880 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, word);
6882 } else if (tid == 7) { /* Check if done with sdtr_speed2. */
6883 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, word);
6885 } else if (tid == 11) { /* Check if done with sdtr_speed3. */
6886 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, word);
6888 } else if (tid == 15) { /* Check if done with sdtr_speed4. */
6889 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, word);
6895 * Set microcode operating variable for the disconnect per TID bitmask.
6897 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
6898 asc_dvc->cfg->disc_enable);
6901 * Set SCSI_CFG0 Microcode Default Value.
6903 * The microcode will set the SCSI_CFG0 register using this value
6904 * after it is started below.
6906 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
6907 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
6908 asc_dvc->chip_scsi_id);
6911 * Determine SCSI_CFG1 Microcode Default Value.
6913 * The microcode will set the SCSI_CFG1 register using this value
6914 * after it is started below.
6917 /* Read current SCSI_CFG1 Register value. */
6918 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
6921 * If all three connectors are in use, return an error.
6923 if ((scsi_cfg1 & CABLE_ILLEGAL_A) == 0 ||
6924 (scsi_cfg1 & CABLE_ILLEGAL_B) == 0) {
6925 asc_dvc->err_code |= ASC_IERR_ILLEGAL_CONNECTION;
6930 * If the internal narrow cable is reversed all of the SCSI_CTRL
6931 * register signals will be set. Check for and return an error if
6932 * this condition is found.
6934 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
6935 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
6940 * If this is a differential board and a single-ended device
6941 * is attached to one of the connectors, return an error.
6943 if ((scsi_cfg1 & DIFF_MODE) && (scsi_cfg1 & DIFF_SENSE) == 0) {
6944 asc_dvc->err_code |= ASC_IERR_SINGLE_END_DEVICE;
6949 * If automatic termination control is enabled, then set the
6950 * termination value based on a table listed in a_condor.h.
6952 * If manual termination was specified with an EEPROM setting
6953 * then 'termination' was set-up in AdvInitFrom3550EEPROM() and
6954 * is ready to be 'ored' into SCSI_CFG1.
6956 if (asc_dvc->cfg->termination == 0) {
6958 * The software always controls termination by setting TERM_CTL_SEL.
6959 * If TERM_CTL_SEL were set to 0, the hardware would set termination.
6961 asc_dvc->cfg->termination |= TERM_CTL_SEL;
6963 switch (scsi_cfg1 & CABLE_DETECT) {
6964 /* TERM_CTL_H: on, TERM_CTL_L: on */
6971 asc_dvc->cfg->termination |= (TERM_CTL_H | TERM_CTL_L);
6974 /* TERM_CTL_H: on, TERM_CTL_L: off */
6980 asc_dvc->cfg->termination |= TERM_CTL_H;
6983 /* TERM_CTL_H: off, TERM_CTL_L: off */
6991 * Clear any set TERM_CTL_H and TERM_CTL_L bits.
6993 scsi_cfg1 &= ~TERM_CTL;
6996 * Invert the TERM_CTL_H and TERM_CTL_L bits and then
6997 * set 'scsi_cfg1'. The TERM_POL bit does not need to be
6998 * referenced, because the hardware internally inverts
6999 * the Termination High and Low bits if TERM_POL is set.
7001 scsi_cfg1 |= (TERM_CTL_SEL | (~asc_dvc->cfg->termination & TERM_CTL));
7004 * Set SCSI_CFG1 Microcode Default Value
7006 * Set filter value and possibly modified termination control
7007 * bits in the Microcode SCSI_CFG1 Register Value.
7009 * The microcode will set the SCSI_CFG1 register using this value
7010 * after it is started below.
7012 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1,
7013 FLTR_DISABLE | scsi_cfg1);
7016 * Set MEM_CFG Microcode Default Value
7018 * The microcode will set the MEM_CFG register using this value
7019 * after it is started below.
7021 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
7024 * ASC-3550 has 8KB internal memory.
7026 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
7027 BIOS_EN | RAM_SZ_8KB);
7030 * Set SEL_MASK Microcode Default Value
7032 * The microcode will set the SEL_MASK register using this value
7033 * after it is started below.
7035 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
7036 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
7038 AdvBuildCarrierFreelist(asc_dvc);
7041 * Set-up the Host->RISC Initiator Command Queue (ICQ).
7044 if ((asc_dvc->icq_sp = asc_dvc->carr_freelist) == NULL) {
7045 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
7048 asc_dvc->carr_freelist = (ADV_CARR_T *)
7049 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->icq_sp->next_vpa));
7052 * The first command issued will be placed in the stopper carrier.
7054 asc_dvc->icq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
7057 * Set RISC ICQ physical address start value.
7059 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
7062 * Set-up the RISC->Host Initiator Response Queue (IRQ).
7064 if ((asc_dvc->irq_sp = asc_dvc->carr_freelist) == NULL) {
7065 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
7068 asc_dvc->carr_freelist = (ADV_CARR_T *)
7069 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->next_vpa));
7072 * The first command completed by the RISC will be placed in
7075 * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is
7076 * completed the RISC will set the ASC_RQ_STOPPER bit.
7078 asc_dvc->irq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
7081 * Set RISC IRQ physical address start value.
7083 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
7084 asc_dvc->carr_pending_cnt = 0;
7086 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
7087 (ADV_INTR_ENABLE_HOST_INTR |
7088 ADV_INTR_ENABLE_GLOBAL_INTR));
7090 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
7091 AdvWriteWordRegister(iop_base, IOPW_PC, word);
7093 /* finally, finally, gentlemen, start your engine */
7094 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
7097 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
7098 * Resets should be performed. The RISC has to be running
7099 * to issue a SCSI Bus Reset.
7101 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
7103 * If the BIOS Signature is present in memory, restore the
7104 * BIOS Handshake Configuration Table and do not perform
7107 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
7110 * Restore per TID negotiated values.
7112 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
7113 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
7114 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
7116 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
7117 AdvWriteByteLram(iop_base,
7118 ASC_MC_NUMBER_OF_MAX_CMD + tid,
7122 if (AdvResetSB(asc_dvc) != ADV_TRUE) {
7123 warn_code = ASC_WARN_BUSRESET_ERROR;
7132 * Initialize the ASC-38C0800.
7134 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
7136 * For a non-fatal error return a warning code. If there are no warnings
7137 * then 0 is returned.
7139 * Needed after initialization for error recovery.
7141 static int AdvInitAsc38C0800Driver(ADV_DVC_VAR *asc_dvc)
7143 AdvPortAddr iop_base;
7153 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */
7154 ushort wdtr_able, sdtr_able, tagqng_able;
7155 uchar max_cmd[ADV_MAX_TID + 1];
7157 /* If there is already an error, don't continue. */
7158 if (asc_dvc->err_code != 0)
7162 * The caller must set 'chip_type' to ADV_CHIP_ASC38C0800.
7164 if (asc_dvc->chip_type != ADV_CHIP_ASC38C0800) {
7165 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
7170 iop_base = asc_dvc->iop_base;
7173 * Save the RISC memory BIOS region before writing the microcode.
7174 * The BIOS may already be loaded and using its RISC LRAM region
7175 * so its region must be saved and restored.
7177 * Note: This code makes the assumption, which is currently true,
7178 * that a chip reset does not clear RISC LRAM.
7180 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
7181 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
7186 * Save current per TID negotiated values.
7188 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
7189 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
7190 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
7191 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
7192 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
7197 * RAM BIST (RAM Built-In Self Test)
7199 * Address : I/O base + offset 0x38h register (byte).
7200 * Function: Bit 7-6(RW) : RAM mode
7201 * Normal Mode : 0x00
7202 * Pre-test Mode : 0x40
7203 * RAM Test Mode : 0x80
7205 * Bit 4(RO) : Done bit
7206 * Bit 3-0(RO) : Status
7208 * Int_RAM Error : 0x04
7213 * Note: RAM BIST code should be put right here, before loading the
7214 * microcode and after saving the RISC memory BIOS region.
7220 * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds.
7221 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return
7222 * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset
7223 * to NORMAL_MODE, return an error too.
7225 for (i = 0; i < 2; i++) {
7226 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE);
7227 mdelay(10); /* Wait for 10ms before reading back. */
7228 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
7229 if ((byte & RAM_TEST_DONE) == 0
7230 || (byte & 0x0F) != PRE_TEST_VALUE) {
7231 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
7235 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
7236 mdelay(10); /* Wait for 10ms before reading back. */
7237 if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST)
7239 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
7245 * LRAM Test - It takes about 1.5 ms to run through the test.
7247 * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds.
7248 * If Done bit not set or Status not 0, save register byte, set the
7249 * err_code, and return an error.
7251 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE);
7252 mdelay(10); /* Wait for 10ms before checking status. */
7254 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
7255 if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) {
7256 /* Get here if Done bit not set or Status not 0. */
7257 asc_dvc->bist_err_code = byte; /* for BIOS display message */
7258 asc_dvc->err_code = ASC_IERR_BIST_RAM_TEST;
7262 /* We need to reset back to normal mode after LRAM test passes. */
7263 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
7265 asc_dvc->err_code = AdvLoadMicrocode(iop_base, _adv_asc38C0800_buf,
7266 _adv_asc38C0800_size, ADV_38C0800_MEMSIZE,
7267 _adv_asc38C0800_chksum);
7268 if (asc_dvc->err_code)
7272 * Restore the RISC memory BIOS region.
7274 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
7275 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
7280 * Calculate and write the microcode code checksum to the microcode
7281 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
7283 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
7284 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
7286 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
7287 for (word = begin_addr; word < end_addr; word += 2) {
7288 code_sum += AdvReadWordAutoIncLram(iop_base);
7290 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
7293 * Read microcode version and date.
7295 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
7296 asc_dvc->cfg->mcode_date);
7297 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
7298 asc_dvc->cfg->mcode_version);
7301 * Set the chip type to indicate the ASC38C0800.
7303 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C0800);
7306 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
7307 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
7308 * cable detection and then we are able to read C_DET[3:0].
7310 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
7311 * Microcode Default Value' section below.
7313 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
7314 AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1,
7315 scsi_cfg1 | DIS_TERM_DRV);
7318 * If the PCI Configuration Command Register "Parity Error Response
7319 * Control" Bit was clear (0), then set the microcode variable
7320 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
7321 * to ignore DMA parity errors.
7323 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
7324 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
7325 word |= CONTROL_FLAG_IGNORE_PERR;
7326 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
7330 * For ASC-38C0800, set FIFO_THRESH_80B [6:4] bits and START_CTL_TH [3:2]
7331 * bits for the default FIFO threshold.
7333 * Note: ASC-38C0800 FIFO threshold has been changed to 256 bytes.
7335 * For DMA Errata #4 set the BC_THRESH_ENB bit.
7337 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
7338 BC_THRESH_ENB | FIFO_THRESH_80B | START_CTL_TH |
7342 * Microcode operating variables for WDTR, SDTR, and command tag
7343 * queuing will be set in slave_configure() based on what a
7344 * device reports it is capable of in Inquiry byte 7.
7346 * If SCSI Bus Resets have been disabled, then directly set
7347 * SDTR and WDTR from the EEPROM configuration. This will allow
7348 * the BIOS and warm boot to work without a SCSI bus hang on
7349 * the Inquiry caused by host and target mismatched DTR values.
7350 * Without the SCSI Bus Reset, before an Inquiry a device can't
7351 * be assumed to be in Asynchronous, Narrow mode.
7353 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
7354 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
7355 asc_dvc->wdtr_able);
7356 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
7357 asc_dvc->sdtr_able);
7361 * Set microcode operating variables for DISC and SDTR_SPEED1,
7362 * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM
7363 * configuration values.
7365 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
7366 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
7367 * without determining here whether the device supports SDTR.
7369 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
7370 asc_dvc->cfg->disc_enable);
7371 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1);
7372 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2);
7373 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3);
7374 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4);
7377 * Set SCSI_CFG0 Microcode Default Value.
7379 * The microcode will set the SCSI_CFG0 register using this value
7380 * after it is started below.
7382 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
7383 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
7384 asc_dvc->chip_scsi_id);
7387 * Determine SCSI_CFG1 Microcode Default Value.
7389 * The microcode will set the SCSI_CFG1 register using this value
7390 * after it is started below.
7393 /* Read current SCSI_CFG1 Register value. */
7394 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
7397 * If the internal narrow cable is reversed all of the SCSI_CTRL
7398 * register signals will be set. Check for and return an error if
7399 * this condition is found.
7401 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
7402 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
7407 * All kind of combinations of devices attached to one of four
7408 * connectors are acceptable except HVD device attached. For example,
7409 * LVD device can be attached to SE connector while SE device attached
7410 * to LVD connector. If LVD device attached to SE connector, it only
7411 * runs up to Ultra speed.
7413 * If an HVD device is attached to one of LVD connectors, return an
7414 * error. However, there is no way to detect HVD device attached to
7417 if (scsi_cfg1 & HVD) {
7418 asc_dvc->err_code = ASC_IERR_HVD_DEVICE;
7423 * If either SE or LVD automatic termination control is enabled, then
7424 * set the termination value based on a table listed in a_condor.h.
7426 * If manual termination was specified with an EEPROM setting then
7427 * 'termination' was set-up in AdvInitFrom38C0800EEPROM() and is ready
7428 * to be 'ored' into SCSI_CFG1.
7430 if ((asc_dvc->cfg->termination & TERM_SE) == 0) {
7431 /* SE automatic termination control is enabled. */
7432 switch (scsi_cfg1 & C_DET_SE) {
7433 /* TERM_SE_HI: on, TERM_SE_LO: on */
7437 asc_dvc->cfg->termination |= TERM_SE;
7440 /* TERM_SE_HI: on, TERM_SE_LO: off */
7442 asc_dvc->cfg->termination |= TERM_SE_HI;
7447 if ((asc_dvc->cfg->termination & TERM_LVD) == 0) {
7448 /* LVD automatic termination control is enabled. */
7449 switch (scsi_cfg1 & C_DET_LVD) {
7450 /* TERM_LVD_HI: on, TERM_LVD_LO: on */
7454 asc_dvc->cfg->termination |= TERM_LVD;
7457 /* TERM_LVD_HI: off, TERM_LVD_LO: off */
7464 * Clear any set TERM_SE and TERM_LVD bits.
7466 scsi_cfg1 &= (~TERM_SE & ~TERM_LVD);
7469 * Invert the TERM_SE and TERM_LVD bits and then set 'scsi_cfg1'.
7471 scsi_cfg1 |= (~asc_dvc->cfg->termination & 0xF0);
7474 * Clear BIG_ENDIAN, DIS_TERM_DRV, Terminator Polarity and HVD/LVD/SE
7475 * bits and set possibly modified termination control bits in the
7476 * Microcode SCSI_CFG1 Register Value.
7478 scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL & ~HVD_LVD_SE);
7481 * Set SCSI_CFG1 Microcode Default Value
7483 * Set possibly modified termination control and reset DIS_TERM_DRV
7484 * bits in the Microcode SCSI_CFG1 Register Value.
7486 * The microcode will set the SCSI_CFG1 register using this value
7487 * after it is started below.
7489 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
7492 * Set MEM_CFG Microcode Default Value
7494 * The microcode will set the MEM_CFG register using this value
7495 * after it is started below.
7497 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
7500 * ASC-38C0800 has 16KB internal memory.
7502 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
7503 BIOS_EN | RAM_SZ_16KB);
7506 * Set SEL_MASK Microcode Default Value
7508 * The microcode will set the SEL_MASK register using this value
7509 * after it is started below.
7511 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
7512 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
7514 AdvBuildCarrierFreelist(asc_dvc);
7517 * Set-up the Host->RISC Initiator Command Queue (ICQ).
7520 if ((asc_dvc->icq_sp = asc_dvc->carr_freelist) == NULL) {
7521 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
7524 asc_dvc->carr_freelist = (ADV_CARR_T *)
7525 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->icq_sp->next_vpa));
7528 * The first command issued will be placed in the stopper carrier.
7530 asc_dvc->icq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
7533 * Set RISC ICQ physical address start value.
7534 * carr_pa is LE, must be native before write
7536 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
7539 * Set-up the RISC->Host Initiator Response Queue (IRQ).
7541 if ((asc_dvc->irq_sp = asc_dvc->carr_freelist) == NULL) {
7542 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
7545 asc_dvc->carr_freelist = (ADV_CARR_T *)
7546 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->next_vpa));
7549 * The first command completed by the RISC will be placed in
7552 * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is
7553 * completed the RISC will set the ASC_RQ_STOPPER bit.
7555 asc_dvc->irq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
7558 * Set RISC IRQ physical address start value.
7560 * carr_pa is LE, must be native before write *
7562 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
7563 asc_dvc->carr_pending_cnt = 0;
7565 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
7566 (ADV_INTR_ENABLE_HOST_INTR |
7567 ADV_INTR_ENABLE_GLOBAL_INTR));
7569 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
7570 AdvWriteWordRegister(iop_base, IOPW_PC, word);
7572 /* finally, finally, gentlemen, start your engine */
7573 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
7576 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
7577 * Resets should be performed. The RISC has to be running
7578 * to issue a SCSI Bus Reset.
7580 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
7582 * If the BIOS Signature is present in memory, restore the
7583 * BIOS Handshake Configuration Table and do not perform
7586 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
7589 * Restore per TID negotiated values.
7591 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
7592 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
7593 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
7595 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
7596 AdvWriteByteLram(iop_base,
7597 ASC_MC_NUMBER_OF_MAX_CMD + tid,
7601 if (AdvResetSB(asc_dvc) != ADV_TRUE) {
7602 warn_code = ASC_WARN_BUSRESET_ERROR;
7611 * Initialize the ASC-38C1600.
7613 * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR.
7615 * For a non-fatal error return a warning code. If there are no warnings
7616 * then 0 is returned.
7618 * Needed after initialization for error recovery.
7620 static int AdvInitAsc38C1600Driver(ADV_DVC_VAR *asc_dvc)
7622 AdvPortAddr iop_base;
7632 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */
7633 ushort wdtr_able, sdtr_able, ppr_able, tagqng_able;
7634 uchar max_cmd[ASC_MAX_TID + 1];
7636 /* If there is already an error, don't continue. */
7637 if (asc_dvc->err_code != 0) {
7642 * The caller must set 'chip_type' to ADV_CHIP_ASC38C1600.
7644 if (asc_dvc->chip_type != ADV_CHIP_ASC38C1600) {
7645 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
7650 iop_base = asc_dvc->iop_base;
7653 * Save the RISC memory BIOS region before writing the microcode.
7654 * The BIOS may already be loaded and using its RISC LRAM region
7655 * so its region must be saved and restored.
7657 * Note: This code makes the assumption, which is currently true,
7658 * that a chip reset does not clear RISC LRAM.
7660 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
7661 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
7666 * Save current per TID negotiated values.
7668 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
7669 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
7670 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
7671 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
7672 for (tid = 0; tid <= ASC_MAX_TID; tid++) {
7673 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
7678 * RAM BIST (Built-In Self Test)
7680 * Address : I/O base + offset 0x38h register (byte).
7681 * Function: Bit 7-6(RW) : RAM mode
7682 * Normal Mode : 0x00
7683 * Pre-test Mode : 0x40
7684 * RAM Test Mode : 0x80
7686 * Bit 4(RO) : Done bit
7687 * Bit 3-0(RO) : Status
7689 * Int_RAM Error : 0x04
7694 * Note: RAM BIST code should be put right here, before loading the
7695 * microcode and after saving the RISC memory BIOS region.
7701 * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds.
7702 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return
7703 * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset
7704 * to NORMAL_MODE, return an error too.
7706 for (i = 0; i < 2; i++) {
7707 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE);
7708 mdelay(10); /* Wait for 10ms before reading back. */
7709 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
7710 if ((byte & RAM_TEST_DONE) == 0
7711 || (byte & 0x0F) != PRE_TEST_VALUE) {
7712 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
7716 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
7717 mdelay(10); /* Wait for 10ms before reading back. */
7718 if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST)
7720 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
7726 * LRAM Test - It takes about 1.5 ms to run through the test.
7728 * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds.
7729 * If Done bit not set or Status not 0, save register byte, set the
7730 * err_code, and return an error.
7732 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE);
7733 mdelay(10); /* Wait for 10ms before checking status. */
7735 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
7736 if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) {
7737 /* Get here if Done bit not set or Status not 0. */
7738 asc_dvc->bist_err_code = byte; /* for BIOS display message */
7739 asc_dvc->err_code = ASC_IERR_BIST_RAM_TEST;
7743 /* We need to reset back to normal mode after LRAM test passes. */
7744 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
7746 asc_dvc->err_code = AdvLoadMicrocode(iop_base, _adv_asc38C1600_buf,
7747 _adv_asc38C1600_size, ADV_38C1600_MEMSIZE,
7748 _adv_asc38C1600_chksum);
7749 if (asc_dvc->err_code)
7753 * Restore the RISC memory BIOS region.
7755 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
7756 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
7761 * Calculate and write the microcode code checksum to the microcode
7762 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
7764 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
7765 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
7767 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
7768 for (word = begin_addr; word < end_addr; word += 2) {
7769 code_sum += AdvReadWordAutoIncLram(iop_base);
7771 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
7774 * Read microcode version and date.
7776 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
7777 asc_dvc->cfg->mcode_date);
7778 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
7779 asc_dvc->cfg->mcode_version);
7782 * Set the chip type to indicate the ASC38C1600.
7784 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C1600);
7787 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
7788 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
7789 * cable detection and then we are able to read C_DET[3:0].
7791 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
7792 * Microcode Default Value' section below.
7794 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
7795 AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1,
7796 scsi_cfg1 | DIS_TERM_DRV);
7799 * If the PCI Configuration Command Register "Parity Error Response
7800 * Control" Bit was clear (0), then set the microcode variable
7801 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
7802 * to ignore DMA parity errors.
7804 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
7805 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
7806 word |= CONTROL_FLAG_IGNORE_PERR;
7807 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
7811 * If the BIOS control flag AIPP (Asynchronous Information
7812 * Phase Protection) disable bit is not set, then set the firmware
7813 * 'control_flag' CONTROL_FLAG_ENABLE_AIPP bit to enable
7814 * AIPP checking and encoding.
7816 if ((asc_dvc->bios_ctrl & BIOS_CTRL_AIPP_DIS) == 0) {
7817 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
7818 word |= CONTROL_FLAG_ENABLE_AIPP;
7819 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
7823 * For ASC-38C1600 use DMA_CFG0 default values: FIFO_THRESH_80B [6:4],
7824 * and START_CTL_TH [3:2].
7826 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
7827 FIFO_THRESH_80B | START_CTL_TH | READ_CMD_MRM);
7830 * Microcode operating variables for WDTR, SDTR, and command tag
7831 * queuing will be set in slave_configure() based on what a
7832 * device reports it is capable of in Inquiry byte 7.
7834 * If SCSI Bus Resets have been disabled, then directly set
7835 * SDTR and WDTR from the EEPROM configuration. This will allow
7836 * the BIOS and warm boot to work without a SCSI bus hang on
7837 * the Inquiry caused by host and target mismatched DTR values.
7838 * Without the SCSI Bus Reset, before an Inquiry a device can't
7839 * be assumed to be in Asynchronous, Narrow mode.
7841 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
7842 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
7843 asc_dvc->wdtr_able);
7844 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
7845 asc_dvc->sdtr_able);
7849 * Set microcode operating variables for DISC and SDTR_SPEED1,
7850 * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM
7851 * configuration values.
7853 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
7854 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
7855 * without determining here whether the device supports SDTR.
7857 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
7858 asc_dvc->cfg->disc_enable);
7859 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1);
7860 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2);
7861 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3);
7862 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4);
7865 * Set SCSI_CFG0 Microcode Default Value.
7867 * The microcode will set the SCSI_CFG0 register using this value
7868 * after it is started below.
7870 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
7871 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
7872 asc_dvc->chip_scsi_id);
7875 * Calculate SCSI_CFG1 Microcode Default Value.
7877 * The microcode will set the SCSI_CFG1 register using this value
7878 * after it is started below.
7880 * Each ASC-38C1600 function has only two cable detect bits.
7881 * The bus mode override bits are in IOPB_SOFT_OVER_WR.
7883 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
7886 * If the cable is reversed all of the SCSI_CTRL register signals
7887 * will be set. Check for and return an error if this condition is
7890 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
7891 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
7896 * Each ASC-38C1600 function has two connectors. Only an HVD device
7897 * can not be connected to either connector. An LVD device or SE device
7898 * may be connected to either connecor. If an SE device is connected,
7899 * then at most Ultra speed (20 Mhz) can be used on both connectors.
7901 * If an HVD device is attached, return an error.
7903 if (scsi_cfg1 & HVD) {
7904 asc_dvc->err_code |= ASC_IERR_HVD_DEVICE;
7909 * Each function in the ASC-38C1600 uses only the SE cable detect and
7910 * termination because there are two connectors for each function. Each
7911 * function may use either LVD or SE mode. Corresponding the SE automatic
7912 * termination control EEPROM bits are used for each function. Each
7913 * function has its own EEPROM. If SE automatic control is enabled for
7914 * the function, then set the termination value based on a table listed
7917 * If manual termination is specified in the EEPROM for the function,
7918 * then 'termination' was set-up in AscInitFrom38C1600EEPROM() and is
7919 * ready to be 'ored' into SCSI_CFG1.
7921 if ((asc_dvc->cfg->termination & TERM_SE) == 0) {
7922 struct pci_dev *pdev = adv_dvc_to_pdev(asc_dvc);
7923 /* SE automatic termination control is enabled. */
7924 switch (scsi_cfg1 & C_DET_SE) {
7925 /* TERM_SE_HI: on, TERM_SE_LO: on */
7929 asc_dvc->cfg->termination |= TERM_SE;
7933 if (PCI_FUNC(pdev->devfn) == 0) {
7934 /* Function 0 - TERM_SE_HI: off, TERM_SE_LO: off */
7936 /* Function 1 - TERM_SE_HI: on, TERM_SE_LO: off */
7937 asc_dvc->cfg->termination |= TERM_SE_HI;
7944 * Clear any set TERM_SE bits.
7946 scsi_cfg1 &= ~TERM_SE;
7949 * Invert the TERM_SE bits and then set 'scsi_cfg1'.
7951 scsi_cfg1 |= (~asc_dvc->cfg->termination & TERM_SE);
7954 * Clear Big Endian and Terminator Polarity bits and set possibly
7955 * modified termination control bits in the Microcode SCSI_CFG1
7958 * Big Endian bit is not used even on big endian machines.
7960 scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL);
7963 * Set SCSI_CFG1 Microcode Default Value
7965 * Set possibly modified termination control bits in the Microcode
7966 * SCSI_CFG1 Register Value.
7968 * The microcode will set the SCSI_CFG1 register using this value
7969 * after it is started below.
7971 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
7974 * Set MEM_CFG Microcode Default Value
7976 * The microcode will set the MEM_CFG register using this value
7977 * after it is started below.
7979 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
7982 * ASC-38C1600 has 32KB internal memory.
7984 * XXX - Since ASC38C1600 Rev.3 has a Local RAM failure issue, we come
7985 * out a special 16K Adv Library and Microcode version. After the issue
7986 * resolved, we should turn back to the 32K support. Both a_condor.h and
7987 * mcode.sas files also need to be updated.
7989 * AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
7990 * BIOS_EN | RAM_SZ_32KB);
7992 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
7993 BIOS_EN | RAM_SZ_16KB);
7996 * Set SEL_MASK Microcode Default Value
7998 * The microcode will set the SEL_MASK register using this value
7999 * after it is started below.
8001 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
8002 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
8004 AdvBuildCarrierFreelist(asc_dvc);
8007 * Set-up the Host->RISC Initiator Command Queue (ICQ).
8009 if ((asc_dvc->icq_sp = asc_dvc->carr_freelist) == NULL) {
8010 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
8013 asc_dvc->carr_freelist = (ADV_CARR_T *)
8014 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->icq_sp->next_vpa));
8017 * The first command issued will be placed in the stopper carrier.
8019 asc_dvc->icq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
8022 * Set RISC ICQ physical address start value. Initialize the
8023 * COMMA register to the same value otherwise the RISC will
8024 * prematurely detect a command is available.
8026 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
8027 AdvWriteDWordRegister(iop_base, IOPDW_COMMA,
8028 le32_to_cpu(asc_dvc->icq_sp->carr_pa));
8031 * Set-up the RISC->Host Initiator Response Queue (IRQ).
8033 if ((asc_dvc->irq_sp = asc_dvc->carr_freelist) == NULL) {
8034 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
8037 asc_dvc->carr_freelist = (ADV_CARR_T *)
8038 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->next_vpa));
8041 * The first command completed by the RISC will be placed in
8044 * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is
8045 * completed the RISC will set the ASC_RQ_STOPPER bit.
8047 asc_dvc->irq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
8050 * Set RISC IRQ physical address start value.
8052 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
8053 asc_dvc->carr_pending_cnt = 0;
8055 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
8056 (ADV_INTR_ENABLE_HOST_INTR |
8057 ADV_INTR_ENABLE_GLOBAL_INTR));
8058 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
8059 AdvWriteWordRegister(iop_base, IOPW_PC, word);
8061 /* finally, finally, gentlemen, start your engine */
8062 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
8065 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
8066 * Resets should be performed. The RISC has to be running
8067 * to issue a SCSI Bus Reset.
8069 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
8071 * If the BIOS Signature is present in memory, restore the
8072 * per TID microcode operating variables.
8074 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
8077 * Restore per TID negotiated values.
8079 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
8080 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
8081 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
8082 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
8084 for (tid = 0; tid <= ASC_MAX_TID; tid++) {
8085 AdvWriteByteLram(iop_base,
8086 ASC_MC_NUMBER_OF_MAX_CMD + tid,
8090 if (AdvResetSB(asc_dvc) != ADV_TRUE) {
8091 warn_code = ASC_WARN_BUSRESET_ERROR;
8100 * Reset chip and SCSI Bus.
8103 * ADV_TRUE(1) - Chip re-initialization and SCSI Bus Reset successful.
8104 * ADV_FALSE(0) - Chip re-initialization and SCSI Bus Reset failure.
8106 static int AdvResetChipAndSB(ADV_DVC_VAR *asc_dvc)
8109 ushort wdtr_able, sdtr_able, tagqng_able;
8110 ushort ppr_able = 0;
8111 uchar tid, max_cmd[ADV_MAX_TID + 1];
8112 AdvPortAddr iop_base;
8115 iop_base = asc_dvc->iop_base;
8118 * Save current per TID negotiated values.
8120 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
8121 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
8122 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
8123 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
8125 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
8126 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
8127 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
8132 * Force the AdvInitAsc3550/38C0800Driver() function to
8133 * perform a SCSI Bus Reset by clearing the BIOS signature word.
8134 * The initialization functions assumes a SCSI Bus Reset is not
8135 * needed if the BIOS signature word is present.
8137 AdvReadWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig);
8138 AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, 0);
8141 * Stop chip and reset it.
8143 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_STOP);
8144 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG, ADV_CTRL_REG_CMD_RESET);
8146 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
8147 ADV_CTRL_REG_CMD_WR_IO_REG);
8150 * Reset Adv Library error code, if any, and try
8151 * re-initializing the chip.
8153 asc_dvc->err_code = 0;
8154 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
8155 status = AdvInitAsc38C1600Driver(asc_dvc);
8156 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
8157 status = AdvInitAsc38C0800Driver(asc_dvc);
8159 status = AdvInitAsc3550Driver(asc_dvc);
8162 /* Translate initialization return value to status value. */
8170 * Restore the BIOS signature word.
8172 AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig);
8175 * Restore per TID negotiated values.
8177 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
8178 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
8179 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
8180 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
8182 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
8183 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
8184 AdvWriteByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
8192 * adv_async_callback() - Adv Library asynchronous event callback function.
8194 static void adv_async_callback(ADV_DVC_VAR *adv_dvc_varp, uchar code)
8197 case ADV_ASYNC_SCSI_BUS_RESET_DET:
8199 * The firmware detected a SCSI Bus reset.
8201 ASC_DBG(0, "ADV_ASYNC_SCSI_BUS_RESET_DET\n");
8204 case ADV_ASYNC_RDMA_FAILURE:
8206 * Handle RDMA failure by resetting the SCSI Bus and
8207 * possibly the chip if it is unresponsive. Log the error
8208 * with a unique code.
8210 ASC_DBG(0, "ADV_ASYNC_RDMA_FAILURE\n");
8211 AdvResetChipAndSB(adv_dvc_varp);
8214 case ADV_HOST_SCSI_BUS_RESET:
8216 * Host generated SCSI bus reset occurred.
8218 ASC_DBG(0, "ADV_HOST_SCSI_BUS_RESET\n");
8222 ASC_DBG(0, "unknown code 0x%x\n", code);
8228 * adv_isr_callback() - Second Level Interrupt Handler called by AdvISR().
8230 * Callback function for the Wide SCSI Adv Library.
8232 static void adv_isr_callback(ADV_DVC_VAR *adv_dvc_varp, ADV_SCSI_REQ_Q *scsiqp)
8234 struct asc_board *boardp;
8236 adv_sgblk_t *sgblkp;
8237 struct scsi_cmnd *scp;
8238 struct Scsi_Host *shost;
8241 ASC_DBG(1, "adv_dvc_varp 0x%lx, scsiqp 0x%lx\n",
8242 (ulong)adv_dvc_varp, (ulong)scsiqp);
8243 ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp);
8246 * Get the adv_req_t structure for the command that has been
8247 * completed. The adv_req_t structure actually contains the
8248 * completed ADV_SCSI_REQ_Q structure.
8250 reqp = (adv_req_t *)ADV_U32_TO_VADDR(scsiqp->srb_ptr);
8251 ASC_DBG(1, "reqp 0x%lx\n", (ulong)reqp);
8253 ASC_PRINT("adv_isr_callback: reqp is NULL\n");
8258 * Get the struct scsi_cmnd structure and Scsi_Host structure for the
8259 * command that has been completed.
8261 * Note: The adv_req_t request structure and adv_sgblk_t structure,
8262 * if any, are dropped, because a board structure pointer can not be
8266 ASC_DBG(1, "scp 0x%p\n", scp);
8269 ("adv_isr_callback: scp is NULL; adv_req_t dropped.\n");
8272 ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len);
8274 shost = scp->device->host;
8275 ASC_STATS(shost, callback);
8276 ASC_DBG(1, "shost 0x%p\n", shost);
8278 boardp = shost_priv(shost);
8279 BUG_ON(adv_dvc_varp != &boardp->dvc_var.adv_dvc_var);
8282 * 'done_status' contains the command's ending status.
8284 switch (scsiqp->done_status) {
8286 ASC_DBG(2, "QD_NO_ERROR\n");
8290 * Check for an underrun condition.
8292 * If there was no error and an underrun condition, then
8293 * then return the number of underrun bytes.
8295 resid_cnt = le32_to_cpu(scsiqp->data_cnt);
8296 if (scp->request_bufflen != 0 && resid_cnt != 0 &&
8297 resid_cnt <= scp->request_bufflen) {
8298 ASC_DBG(1, "underrun condition %lu bytes\n",
8300 scp->resid = resid_cnt;
8305 ASC_DBG(2, "QD_WITH_ERROR\n");
8306 switch (scsiqp->host_status) {
8307 case QHSTA_NO_ERROR:
8308 if (scsiqp->scsi_status == SAM_STAT_CHECK_CONDITION) {
8309 ASC_DBG(2, "SAM_STAT_CHECK_CONDITION\n");
8310 ASC_DBG_PRT_SENSE(2, scp->sense_buffer,
8311 sizeof(scp->sense_buffer));
8313 * Note: The 'status_byte()' macro used by
8314 * target drivers defined in scsi.h shifts the
8315 * status byte returned by host drivers right
8316 * by 1 bit. This is why target drivers also
8317 * use right shifted status byte definitions.
8318 * For instance target drivers use
8319 * CHECK_CONDITION, defined to 0x1, instead of
8320 * the SCSI defined check condition value of
8321 * 0x2. Host drivers are supposed to return
8322 * the status byte as it is defined by SCSI.
8324 scp->result = DRIVER_BYTE(DRIVER_SENSE) |
8325 STATUS_BYTE(scsiqp->scsi_status);
8327 scp->result = STATUS_BYTE(scsiqp->scsi_status);
8332 /* Some other QHSTA error occurred. */
8333 ASC_DBG(1, "host_status 0x%x\n", scsiqp->host_status);
8334 scp->result = HOST_BYTE(DID_BAD_TARGET);
8339 case QD_ABORTED_BY_HOST:
8340 ASC_DBG(1, "QD_ABORTED_BY_HOST\n");
8342 HOST_BYTE(DID_ABORT) | STATUS_BYTE(scsiqp->scsi_status);
8346 ASC_DBG(1, "done_status 0x%x\n", scsiqp->done_status);
8348 HOST_BYTE(DID_ERROR) | STATUS_BYTE(scsiqp->scsi_status);
8353 * If the 'init_tidmask' bit isn't already set for the target and the
8354 * current request finished normally, then set the bit for the target
8355 * to indicate that a device is present.
8357 if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 &&
8358 scsiqp->done_status == QD_NO_ERROR &&
8359 scsiqp->host_status == QHSTA_NO_ERROR) {
8360 boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id);
8366 * Free all 'adv_sgblk_t' structures allocated for the request.
8368 while ((sgblkp = reqp->sgblkp) != NULL) {
8369 /* Remove 'sgblkp' from the request list. */
8370 reqp->sgblkp = sgblkp->next_sgblkp;
8372 /* Add 'sgblkp' to the board free list. */
8373 sgblkp->next_sgblkp = boardp->adv_sgblkp;
8374 boardp->adv_sgblkp = sgblkp;
8378 * Free the adv_req_t structure used with the command by adding
8379 * it back to the board free list.
8381 reqp->next_reqp = boardp->adv_reqp;
8382 boardp->adv_reqp = reqp;
8384 ASC_DBG(1, "done\n");
8388 * Adv Library Interrupt Service Routine
8390 * This function is called by a driver's interrupt service routine.
8391 * The function disables and re-enables interrupts.
8393 * When a microcode idle command is completed, the ADV_DVC_VAR
8394 * 'idle_cmd_done' field is set to ADV_TRUE.
8396 * Note: AdvISR() can be called when interrupts are disabled or even
8397 * when there is no hardware interrupt condition present. It will
8398 * always check for completed idle commands and microcode requests.
8399 * This is an important feature that shouldn't be changed because it
8400 * allows commands to be completed from polling mode loops.
8403 * ADV_TRUE(1) - interrupt was pending
8404 * ADV_FALSE(0) - no interrupt was pending
8406 static int AdvISR(ADV_DVC_VAR *asc_dvc)
8408 AdvPortAddr iop_base;
8411 ADV_CARR_T *free_carrp;
8412 ADV_VADDR irq_next_vpa;
8413 ADV_SCSI_REQ_Q *scsiq;
8415 iop_base = asc_dvc->iop_base;
8417 /* Reading the register clears the interrupt. */
8418 int_stat = AdvReadByteRegister(iop_base, IOPB_INTR_STATUS_REG);
8420 if ((int_stat & (ADV_INTR_STATUS_INTRA | ADV_INTR_STATUS_INTRB |
8421 ADV_INTR_STATUS_INTRC)) == 0) {
8426 * Notify the driver of an asynchronous microcode condition by
8427 * calling the adv_async_callback function. The function
8428 * is passed the microcode ASC_MC_INTRB_CODE byte value.
8430 if (int_stat & ADV_INTR_STATUS_INTRB) {
8433 AdvReadByteLram(iop_base, ASC_MC_INTRB_CODE, intrb_code);
8435 if (asc_dvc->chip_type == ADV_CHIP_ASC3550 ||
8436 asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
8437 if (intrb_code == ADV_ASYNC_CARRIER_READY_FAILURE &&
8438 asc_dvc->carr_pending_cnt != 0) {
8439 AdvWriteByteRegister(iop_base, IOPB_TICKLE,
8441 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
8442 AdvWriteByteRegister(iop_base,
8449 adv_async_callback(asc_dvc, intrb_code);
8453 * Check if the IRQ stopper carrier contains a completed request.
8455 while (((irq_next_vpa =
8456 le32_to_cpu(asc_dvc->irq_sp->next_vpa)) & ASC_RQ_DONE) != 0) {
8458 * Get a pointer to the newly completed ADV_SCSI_REQ_Q structure.
8459 * The RISC will have set 'areq_vpa' to a virtual address.
8461 * The firmware will have copied the ASC_SCSI_REQ_Q.scsiq_ptr
8462 * field to the carrier ADV_CARR_T.areq_vpa field. The conversion
8463 * below complements the conversion of ASC_SCSI_REQ_Q.scsiq_ptr'
8464 * in AdvExeScsiQueue().
8466 scsiq = (ADV_SCSI_REQ_Q *)
8467 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->areq_vpa));
8470 * Request finished with good status and the queue was not
8471 * DMAed to host memory by the firmware. Set all status fields
8472 * to indicate good status.
8474 if ((irq_next_vpa & ASC_RQ_GOOD) != 0) {
8475 scsiq->done_status = QD_NO_ERROR;
8476 scsiq->host_status = scsiq->scsi_status = 0;
8477 scsiq->data_cnt = 0L;
8481 * Advance the stopper pointer to the next carrier
8482 * ignoring the lower four bits. Free the previous
8485 free_carrp = asc_dvc->irq_sp;
8486 asc_dvc->irq_sp = (ADV_CARR_T *)
8487 ADV_U32_TO_VADDR(ASC_GET_CARRP(irq_next_vpa));
8489 free_carrp->next_vpa =
8490 cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->carr_freelist));
8491 asc_dvc->carr_freelist = free_carrp;
8492 asc_dvc->carr_pending_cnt--;
8494 target_bit = ADV_TID_TO_TIDMASK(scsiq->target_id);
8497 * Clear request microcode control flag.
8502 * Notify the driver of the completed request by passing
8503 * the ADV_SCSI_REQ_Q pointer to its callback function.
8505 scsiq->a_flag |= ADV_SCSIQ_DONE;
8506 adv_isr_callback(asc_dvc, scsiq);
8508 * Note: After the driver callback function is called, 'scsiq'
8509 * can no longer be referenced.
8511 * Fall through and continue processing other completed
8518 static int AscSetLibErrorCode(ASC_DVC_VAR *asc_dvc, ushort err_code)
8520 if (asc_dvc->err_code == 0) {
8521 asc_dvc->err_code = err_code;
8522 AscWriteLramWord(asc_dvc->iop_base, ASCV_ASCDVC_ERR_CODE_W,
8528 static void AscAckInterrupt(PortAddr iop_base)
8536 risc_flag = AscReadLramByte(iop_base, ASCV_RISC_FLAG_B);
8537 if (loop++ > 0x7FFF) {
8540 } while ((risc_flag & ASC_RISC_FLAG_GEN_INT) != 0);
8542 AscReadLramByte(iop_base,
8543 ASCV_HOST_FLAG_B) & (~ASC_HOST_FLAG_ACK_INT);
8544 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B,
8545 (uchar)(host_flag | ASC_HOST_FLAG_ACK_INT));
8546 AscSetChipStatus(iop_base, CIW_INT_ACK);
8548 while (AscGetChipStatus(iop_base) & CSW_INT_PENDING) {
8549 AscSetChipStatus(iop_base, CIW_INT_ACK);
8554 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag);
8557 static uchar AscGetSynPeriodIndex(ASC_DVC_VAR *asc_dvc, uchar syn_time)
8559 uchar *period_table;
8564 period_table = asc_dvc->sdtr_period_tbl;
8565 max_index = (int)asc_dvc->max_sdtr_index;
8566 min_index = (int)asc_dvc->host_init_sdtr_index;
8567 if ((syn_time <= period_table[max_index])) {
8568 for (i = min_index; i < (max_index - 1); i++) {
8569 if (syn_time <= period_table[i]) {
8573 return (uchar)max_index;
8575 return (uchar)(max_index + 1);
8580 AscMsgOutSDTR(ASC_DVC_VAR *asc_dvc, uchar sdtr_period, uchar sdtr_offset)
8583 uchar sdtr_period_index;
8586 iop_base = asc_dvc->iop_base;
8587 sdtr_buf.msg_type = EXTENDED_MESSAGE;
8588 sdtr_buf.msg_len = MS_SDTR_LEN;
8589 sdtr_buf.msg_req = EXTENDED_SDTR;
8590 sdtr_buf.xfer_period = sdtr_period;
8591 sdtr_offset &= ASC_SYN_MAX_OFFSET;
8592 sdtr_buf.req_ack_offset = sdtr_offset;
8593 sdtr_period_index = AscGetSynPeriodIndex(asc_dvc, sdtr_period);
8594 if (sdtr_period_index <= asc_dvc->max_sdtr_index) {
8595 AscMemWordCopyPtrToLram(iop_base, ASCV_MSGOUT_BEG,
8597 sizeof(EXT_MSG) >> 1);
8598 return ((sdtr_period_index << 4) | sdtr_offset);
8600 sdtr_buf.req_ack_offset = 0;
8601 AscMemWordCopyPtrToLram(iop_base, ASCV_MSGOUT_BEG,
8603 sizeof(EXT_MSG) >> 1);
8609 AscCalSDTRData(ASC_DVC_VAR *asc_dvc, uchar sdtr_period, uchar syn_offset)
8612 uchar sdtr_period_ix;
8614 sdtr_period_ix = AscGetSynPeriodIndex(asc_dvc, sdtr_period);
8615 if (sdtr_period_ix > asc_dvc->max_sdtr_index) {
8618 byte = (sdtr_period_ix << 4) | (syn_offset & ASC_SYN_MAX_OFFSET);
8622 static int AscSetChipSynRegAtID(PortAddr iop_base, uchar id, uchar sdtr_data)
8624 ASC_SCSI_BIT_ID_TYPE org_id;
8628 AscSetBank(iop_base, 1);
8629 org_id = AscReadChipDvcID(iop_base);
8630 for (i = 0; i <= ASC_MAX_TID; i++) {
8631 if (org_id == (0x01 << i))
8634 org_id = (ASC_SCSI_BIT_ID_TYPE) i;
8635 AscWriteChipDvcID(iop_base, id);
8636 if (AscReadChipDvcID(iop_base) == (0x01 << id)) {
8637 AscSetBank(iop_base, 0);
8638 AscSetChipSyn(iop_base, sdtr_data);
8639 if (AscGetChipSyn(iop_base) != sdtr_data) {
8645 AscSetBank(iop_base, 1);
8646 AscWriteChipDvcID(iop_base, org_id);
8647 AscSetBank(iop_base, 0);
8651 static void AscSetChipSDTR(PortAddr iop_base, uchar sdtr_data, uchar tid_no)
8653 AscSetChipSynRegAtID(iop_base, tid_no, sdtr_data);
8654 AscPutMCodeSDTRDoneAtID(iop_base, tid_no, sdtr_data);
8657 static int AscIsrChipHalted(ASC_DVC_VAR *asc_dvc)
8663 ushort int_halt_code;
8664 ASC_SCSI_BIT_ID_TYPE scsi_busy;
8665 ASC_SCSI_BIT_ID_TYPE target_id;
8672 uchar q_cntl, tid_no;
8676 struct asc_board *boardp;
8678 BUG_ON(!asc_dvc->drv_ptr);
8679 boardp = asc_dvc->drv_ptr;
8681 iop_base = asc_dvc->iop_base;
8682 int_halt_code = AscReadLramWord(iop_base, ASCV_HALTCODE_W);
8684 halt_qp = AscReadLramByte(iop_base, ASCV_CURCDB_B);
8685 halt_q_addr = ASC_QNO_TO_QADDR(halt_qp);
8686 target_ix = AscReadLramByte(iop_base,
8687 (ushort)(halt_q_addr +
8688 (ushort)ASC_SCSIQ_B_TARGET_IX));
8689 q_cntl = AscReadLramByte(iop_base,
8690 (ushort)(halt_q_addr + (ushort)ASC_SCSIQ_B_CNTL));
8691 tid_no = ASC_TIX_TO_TID(target_ix);
8692 target_id = (uchar)ASC_TID_TO_TARGET_ID(tid_no);
8693 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
8694 asyn_sdtr = ASYN_SDTR_DATA_FIX_PCI_REV_AB;
8698 if (int_halt_code == ASC_HALT_DISABLE_ASYN_USE_SYN_FIX) {
8699 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
8700 AscSetChipSDTR(iop_base, 0, tid_no);
8701 boardp->sdtr_data[tid_no] = 0;
8703 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
8705 } else if (int_halt_code == ASC_HALT_ENABLE_ASYN_USE_SYN_FIX) {
8706 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
8707 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
8708 boardp->sdtr_data[tid_no] = asyn_sdtr;
8710 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
8712 } else if (int_halt_code == ASC_HALT_EXTMSG_IN) {
8713 AscMemWordCopyPtrFromLram(iop_base,
8716 sizeof(EXT_MSG) >> 1);
8718 if (ext_msg.msg_type == EXTENDED_MESSAGE &&
8719 ext_msg.msg_req == EXTENDED_SDTR &&
8720 ext_msg.msg_len == MS_SDTR_LEN) {
8722 if ((ext_msg.req_ack_offset > ASC_SYN_MAX_OFFSET)) {
8724 sdtr_accept = FALSE;
8725 ext_msg.req_ack_offset = ASC_SYN_MAX_OFFSET;
8727 if ((ext_msg.xfer_period <
8728 asc_dvc->sdtr_period_tbl[asc_dvc->
8729 host_init_sdtr_index])
8730 || (ext_msg.xfer_period >
8731 asc_dvc->sdtr_period_tbl[asc_dvc->
8733 sdtr_accept = FALSE;
8734 ext_msg.xfer_period =
8735 asc_dvc->sdtr_period_tbl[asc_dvc->
8736 host_init_sdtr_index];
8740 AscCalSDTRData(asc_dvc, ext_msg.xfer_period,
8741 ext_msg.req_ack_offset);
8742 if ((sdtr_data == 0xFF)) {
8744 q_cntl |= QC_MSG_OUT;
8745 asc_dvc->init_sdtr &= ~target_id;
8746 asc_dvc->sdtr_done &= ~target_id;
8747 AscSetChipSDTR(iop_base, asyn_sdtr,
8749 boardp->sdtr_data[tid_no] = asyn_sdtr;
8752 if (ext_msg.req_ack_offset == 0) {
8754 q_cntl &= ~QC_MSG_OUT;
8755 asc_dvc->init_sdtr &= ~target_id;
8756 asc_dvc->sdtr_done &= ~target_id;
8757 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
8759 if (sdtr_accept && (q_cntl & QC_MSG_OUT)) {
8761 q_cntl &= ~QC_MSG_OUT;
8762 asc_dvc->sdtr_done |= target_id;
8763 asc_dvc->init_sdtr |= target_id;
8764 asc_dvc->pci_fix_asyn_xfer &=
8767 AscCalSDTRData(asc_dvc,
8768 ext_msg.xfer_period,
8771 AscSetChipSDTR(iop_base, sdtr_data,
8773 boardp->sdtr_data[tid_no] = sdtr_data;
8776 q_cntl |= QC_MSG_OUT;
8777 AscMsgOutSDTR(asc_dvc,
8778 ext_msg.xfer_period,
8779 ext_msg.req_ack_offset);
8780 asc_dvc->pci_fix_asyn_xfer &=
8783 AscCalSDTRData(asc_dvc,
8784 ext_msg.xfer_period,
8787 AscSetChipSDTR(iop_base, sdtr_data,
8789 boardp->sdtr_data[tid_no] = sdtr_data;
8790 asc_dvc->sdtr_done |= target_id;
8791 asc_dvc->init_sdtr |= target_id;
8795 AscWriteLramByte(iop_base,
8796 (ushort)(halt_q_addr +
8797 (ushort)ASC_SCSIQ_B_CNTL),
8799 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
8801 } else if (ext_msg.msg_type == EXTENDED_MESSAGE &&
8802 ext_msg.msg_req == EXTENDED_WDTR &&
8803 ext_msg.msg_len == MS_WDTR_LEN) {
8805 ext_msg.wdtr_width = 0;
8806 AscMemWordCopyPtrToLram(iop_base,
8809 sizeof(EXT_MSG) >> 1);
8810 q_cntl |= QC_MSG_OUT;
8811 AscWriteLramByte(iop_base,
8812 (ushort)(halt_q_addr +
8813 (ushort)ASC_SCSIQ_B_CNTL),
8815 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
8819 ext_msg.msg_type = MESSAGE_REJECT;
8820 AscMemWordCopyPtrToLram(iop_base,
8823 sizeof(EXT_MSG) >> 1);
8824 q_cntl |= QC_MSG_OUT;
8825 AscWriteLramByte(iop_base,
8826 (ushort)(halt_q_addr +
8827 (ushort)ASC_SCSIQ_B_CNTL),
8829 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
8832 } else if (int_halt_code == ASC_HALT_CHK_CONDITION) {
8834 q_cntl |= QC_REQ_SENSE;
8836 if ((asc_dvc->init_sdtr & target_id) != 0) {
8838 asc_dvc->sdtr_done &= ~target_id;
8840 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
8841 q_cntl |= QC_MSG_OUT;
8842 AscMsgOutSDTR(asc_dvc,
8844 sdtr_period_tbl[(sdtr_data >> 4) &
8848 (uchar)(sdtr_data & (uchar)
8849 ASC_SYN_MAX_OFFSET));
8852 AscWriteLramByte(iop_base,
8853 (ushort)(halt_q_addr +
8854 (ushort)ASC_SCSIQ_B_CNTL), q_cntl);
8856 tag_code = AscReadLramByte(iop_base,
8857 (ushort)(halt_q_addr + (ushort)
8858 ASC_SCSIQ_B_TAG_CODE));
8860 if ((asc_dvc->pci_fix_asyn_xfer & target_id)
8861 && !(asc_dvc->pci_fix_asyn_xfer_always & target_id)
8864 tag_code |= (ASC_TAG_FLAG_DISABLE_DISCONNECT
8865 | ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX);
8868 AscWriteLramByte(iop_base,
8869 (ushort)(halt_q_addr +
8870 (ushort)ASC_SCSIQ_B_TAG_CODE),
8873 q_status = AscReadLramByte(iop_base,
8874 (ushort)(halt_q_addr + (ushort)
8875 ASC_SCSIQ_B_STATUS));
8876 q_status |= (QS_READY | QS_BUSY);
8877 AscWriteLramByte(iop_base,
8878 (ushort)(halt_q_addr +
8879 (ushort)ASC_SCSIQ_B_STATUS),
8882 scsi_busy = AscReadLramByte(iop_base, (ushort)ASCV_SCSIBUSY_B);
8883 scsi_busy &= ~target_id;
8884 AscWriteLramByte(iop_base, (ushort)ASCV_SCSIBUSY_B, scsi_busy);
8886 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
8888 } else if (int_halt_code == ASC_HALT_SDTR_REJECTED) {
8890 AscMemWordCopyPtrFromLram(iop_base,
8893 sizeof(EXT_MSG) >> 1);
8895 if ((out_msg.msg_type == EXTENDED_MESSAGE) &&
8896 (out_msg.msg_len == MS_SDTR_LEN) &&
8897 (out_msg.msg_req == EXTENDED_SDTR)) {
8899 asc_dvc->init_sdtr &= ~target_id;
8900 asc_dvc->sdtr_done &= ~target_id;
8901 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
8902 boardp->sdtr_data[tid_no] = asyn_sdtr;
8904 q_cntl &= ~QC_MSG_OUT;
8905 AscWriteLramByte(iop_base,
8906 (ushort)(halt_q_addr +
8907 (ushort)ASC_SCSIQ_B_CNTL), q_cntl);
8908 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
8910 } else if (int_halt_code == ASC_HALT_SS_QUEUE_FULL) {
8912 scsi_status = AscReadLramByte(iop_base,
8913 (ushort)((ushort)halt_q_addr +
8915 ASC_SCSIQ_SCSI_STATUS));
8917 AscReadLramByte(iop_base,
8918 (ushort)((ushort)ASC_QADR_BEG +
8919 (ushort)target_ix));
8920 if ((cur_dvc_qng > 0) && (asc_dvc->cur_dvc_qng[tid_no] > 0)) {
8922 scsi_busy = AscReadLramByte(iop_base,
8923 (ushort)ASCV_SCSIBUSY_B);
8924 scsi_busy |= target_id;
8925 AscWriteLramByte(iop_base,
8926 (ushort)ASCV_SCSIBUSY_B, scsi_busy);
8927 asc_dvc->queue_full_or_busy |= target_id;
8929 if (scsi_status == SAM_STAT_TASK_SET_FULL) {
8930 if (cur_dvc_qng > ASC_MIN_TAGGED_CMD) {
8932 asc_dvc->max_dvc_qng[tid_no] =
8935 AscWriteLramByte(iop_base,
8937 ASCV_MAX_DVC_QNG_BEG
8943 * Set the device queue depth to the
8944 * number of active requests when the
8945 * QUEUE FULL condition was encountered.
8947 boardp->queue_full |= target_id;
8948 boardp->queue_full_cnt[tid_no] =
8953 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
8956 #if CC_VERY_LONG_SG_LIST
8957 else if (int_halt_code == ASC_HALT_HOST_COPY_SG_LIST_TO_RISC) {
8961 uchar first_sg_wk_q_no;
8962 ASC_SCSI_Q *scsiq; /* Ptr to driver request. */
8963 ASC_SG_HEAD *sg_head; /* Ptr to driver SG request. */
8964 ASC_SG_LIST_Q scsi_sg_q; /* Structure written to queue. */
8965 ushort sg_list_dwords;
8966 ushort sg_entry_cnt;
8970 q_no = AscReadLramByte(iop_base, (ushort)ASCV_REQ_SG_LIST_QP);
8971 if (q_no == ASC_QLINK_END)
8974 q_addr = ASC_QNO_TO_QADDR(q_no);
8977 * Convert the request's SRB pointer to a host ASC_SCSI_REQ
8978 * structure pointer using a macro provided by the driver.
8979 * The ASC_SCSI_REQ pointer provides a pointer to the
8980 * host ASC_SG_HEAD structure.
8982 /* Read request's SRB pointer. */
8983 scsiq = (ASC_SCSI_Q *)
8984 ASC_SRB2SCSIQ(ASC_U32_TO_VADDR(AscReadLramDWord(iop_base,
8987 ASC_SCSIQ_D_SRBPTR))));
8990 * Get request's first and working SG queue.
8992 sg_wk_q_no = AscReadLramByte(iop_base,
8994 ASC_SCSIQ_B_SG_WK_QP));
8996 first_sg_wk_q_no = AscReadLramByte(iop_base,
8998 ASC_SCSIQ_B_FIRST_SG_WK_QP));
9001 * Reset request's working SG queue back to the
9004 AscWriteLramByte(iop_base,
9006 (ushort)ASC_SCSIQ_B_SG_WK_QP),
9009 sg_head = scsiq->sg_head;
9012 * Set sg_entry_cnt to the number of SG elements
9013 * that will be completed on this interrupt.
9015 * Note: The allocated SG queues contain ASC_MAX_SG_LIST - 1
9016 * SG elements. The data_cnt and data_addr fields which
9017 * add 1 to the SG element capacity are not used when
9018 * restarting SG handling after a halt.
9020 if (scsiq->remain_sg_entry_cnt > (ASC_MAX_SG_LIST - 1)) {
9021 sg_entry_cnt = ASC_MAX_SG_LIST - 1;
9024 * Keep track of remaining number of SG elements that
9025 * will need to be handled on the next interrupt.
9027 scsiq->remain_sg_entry_cnt -= (ASC_MAX_SG_LIST - 1);
9029 sg_entry_cnt = scsiq->remain_sg_entry_cnt;
9030 scsiq->remain_sg_entry_cnt = 0;
9034 * Copy SG elements into the list of allocated SG queues.
9036 * Last index completed is saved in scsiq->next_sg_index.
9038 next_qp = first_sg_wk_q_no;
9039 q_addr = ASC_QNO_TO_QADDR(next_qp);
9040 scsi_sg_q.sg_head_qp = q_no;
9041 scsi_sg_q.cntl = QCSG_SG_XFER_LIST;
9042 for (i = 0; i < sg_head->queue_cnt; i++) {
9043 scsi_sg_q.seq_no = i + 1;
9044 if (sg_entry_cnt > ASC_SG_LIST_PER_Q) {
9045 sg_list_dwords = (uchar)(ASC_SG_LIST_PER_Q * 2);
9046 sg_entry_cnt -= ASC_SG_LIST_PER_Q;
9048 * After very first SG queue RISC FW uses next
9049 * SG queue first element then checks sg_list_cnt
9050 * against zero and then decrements, so set
9051 * sg_list_cnt 1 less than number of SG elements
9054 scsi_sg_q.sg_list_cnt = ASC_SG_LIST_PER_Q - 1;
9055 scsi_sg_q.sg_cur_list_cnt =
9056 ASC_SG_LIST_PER_Q - 1;
9059 * This is the last SG queue in the list of
9060 * allocated SG queues. If there are more
9061 * SG elements than will fit in the allocated
9062 * queues, then set the QCSG_SG_XFER_MORE flag.
9064 if (scsiq->remain_sg_entry_cnt != 0) {
9065 scsi_sg_q.cntl |= QCSG_SG_XFER_MORE;
9067 scsi_sg_q.cntl |= QCSG_SG_XFER_END;
9069 /* equals sg_entry_cnt * 2 */
9070 sg_list_dwords = sg_entry_cnt << 1;
9071 scsi_sg_q.sg_list_cnt = sg_entry_cnt - 1;
9072 scsi_sg_q.sg_cur_list_cnt = sg_entry_cnt - 1;
9076 scsi_sg_q.q_no = next_qp;
9077 AscMemWordCopyPtrToLram(iop_base,
9078 q_addr + ASC_SCSIQ_SGHD_CPY_BEG,
9079 (uchar *)&scsi_sg_q,
9080 sizeof(ASC_SG_LIST_Q) >> 1);
9082 AscMemDWordCopyPtrToLram(iop_base,
9083 q_addr + ASC_SGQ_LIST_BEG,
9085 sg_list[scsiq->next_sg_index],
9088 scsiq->next_sg_index += ASC_SG_LIST_PER_Q;
9091 * If the just completed SG queue contained the
9092 * last SG element, then no more SG queues need
9095 if (scsi_sg_q.cntl & QCSG_SG_XFER_END) {
9099 next_qp = AscReadLramByte(iop_base,
9102 q_addr = ASC_QNO_TO_QADDR(next_qp);
9106 * Clear the halt condition so the RISC will be restarted
9109 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
9112 #endif /* CC_VERY_LONG_SG_LIST */
9118 * DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words)
9120 * Calling/Exit State:
9124 * Input an ASC_QDONE_INFO structure from the chip
9127 DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words)
9132 AscSetChipLramAddr(iop_base, s_addr);
9133 for (i = 0; i < 2 * words; i += 2) {
9137 word = inpw(iop_base + IOP_RAM_DATA);
9138 inbuf[i] = word & 0xff;
9139 inbuf[i + 1] = (word >> 8) & 0xff;
9141 ASC_DBG_PRT_HEX(2, "DvcGetQinfo", inbuf, 2 * words);
9145 _AscCopyLramScsiDoneQ(PortAddr iop_base,
9147 ASC_QDONE_INFO *scsiq, ASC_DCNT max_dma_count)
9152 DvcGetQinfo(iop_base,
9153 q_addr + ASC_SCSIQ_DONE_INFO_BEG,
9155 (sizeof(ASC_SCSIQ_2) + sizeof(ASC_SCSIQ_3)) / 2);
9157 _val = AscReadLramWord(iop_base,
9158 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_STATUS));
9159 scsiq->q_status = (uchar)_val;
9160 scsiq->q_no = (uchar)(_val >> 8);
9161 _val = AscReadLramWord(iop_base,
9162 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_CNTL));
9163 scsiq->cntl = (uchar)_val;
9164 sg_queue_cnt = (uchar)(_val >> 8);
9165 _val = AscReadLramWord(iop_base,
9167 (ushort)ASC_SCSIQ_B_SENSE_LEN));
9168 scsiq->sense_len = (uchar)_val;
9169 scsiq->extra_bytes = (uchar)(_val >> 8);
9172 * Read high word of remain bytes from alternate location.
9174 scsiq->remain_bytes = (((ADV_DCNT)AscReadLramWord(iop_base,
9177 ASC_SCSIQ_W_ALT_DC1)))
9180 * Read low word of remain bytes from original location.
9182 scsiq->remain_bytes += AscReadLramWord(iop_base,
9183 (ushort)(q_addr + (ushort)
9184 ASC_SCSIQ_DW_REMAIN_XFER_CNT));
9186 scsiq->remain_bytes &= max_dma_count;
9187 return sg_queue_cnt;
9191 * asc_isr_callback() - Second Level Interrupt Handler called by AscISR().
9193 * Interrupt callback function for the Narrow SCSI Asc Library.
9195 static void asc_isr_callback(ASC_DVC_VAR *asc_dvc_varp, ASC_QDONE_INFO *qdonep)
9197 struct asc_board *boardp;
9198 struct scsi_cmnd *scp;
9199 struct Scsi_Host *shost;
9201 ASC_DBG(1, "asc_dvc_varp 0x%p, qdonep 0x%p\n", asc_dvc_varp, qdonep);
9202 ASC_DBG_PRT_ASC_QDONE_INFO(2, qdonep);
9205 * Get the struct scsi_cmnd structure and Scsi_Host structure for the
9206 * command that has been completed.
9208 scp = (struct scsi_cmnd *)ASC_U32_TO_VADDR(qdonep->d2.srb_ptr);
9209 ASC_DBG(1, "scp 0x%p\n", scp);
9212 ASC_PRINT("asc_isr_callback: scp is NULL\n");
9215 ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len);
9217 shost = scp->device->host;
9218 ASC_STATS(shost, callback);
9219 ASC_DBG(1, "shost 0x%p\n", shost);
9221 boardp = shost_priv(shost);
9222 BUG_ON(asc_dvc_varp != &boardp->dvc_var.asc_dvc_var);
9225 * 'qdonep' contains the command's ending status.
9227 switch (qdonep->d3.done_stat) {
9229 ASC_DBG(2, "QD_NO_ERROR\n");
9233 * Check for an underrun condition.
9235 * If there was no error and an underrun condition, then
9236 * return the number of underrun bytes.
9238 if (scp->request_bufflen != 0 && qdonep->remain_bytes != 0 &&
9239 qdonep->remain_bytes <= scp->request_bufflen) {
9240 ASC_DBG(1, "underrun condition %u bytes\n",
9241 (unsigned)qdonep->remain_bytes);
9242 scp->resid = qdonep->remain_bytes;
9247 ASC_DBG(2, "QD_WITH_ERROR\n");
9248 switch (qdonep->d3.host_stat) {
9249 case QHSTA_NO_ERROR:
9250 if (qdonep->d3.scsi_stat == SAM_STAT_CHECK_CONDITION) {
9251 ASC_DBG(2, "SAM_STAT_CHECK_CONDITION\n");
9252 ASC_DBG_PRT_SENSE(2, scp->sense_buffer,
9253 sizeof(scp->sense_buffer));
9255 * Note: The 'status_byte()' macro used by
9256 * target drivers defined in scsi.h shifts the
9257 * status byte returned by host drivers right
9258 * by 1 bit. This is why target drivers also
9259 * use right shifted status byte definitions.
9260 * For instance target drivers use
9261 * CHECK_CONDITION, defined to 0x1, instead of
9262 * the SCSI defined check condition value of
9263 * 0x2. Host drivers are supposed to return
9264 * the status byte as it is defined by SCSI.
9266 scp->result = DRIVER_BYTE(DRIVER_SENSE) |
9267 STATUS_BYTE(qdonep->d3.scsi_stat);
9269 scp->result = STATUS_BYTE(qdonep->d3.scsi_stat);
9274 /* QHSTA error occurred */
9275 ASC_DBG(1, "host_stat 0x%x\n", qdonep->d3.host_stat);
9276 scp->result = HOST_BYTE(DID_BAD_TARGET);
9281 case QD_ABORTED_BY_HOST:
9282 ASC_DBG(1, "QD_ABORTED_BY_HOST\n");
9284 HOST_BYTE(DID_ABORT) | MSG_BYTE(qdonep->d3.
9286 STATUS_BYTE(qdonep->d3.scsi_stat);
9290 ASC_DBG(1, "done_stat 0x%x\n", qdonep->d3.done_stat);
9292 HOST_BYTE(DID_ERROR) | MSG_BYTE(qdonep->d3.
9294 STATUS_BYTE(qdonep->d3.scsi_stat);
9299 * If the 'init_tidmask' bit isn't already set for the target and the
9300 * current request finished normally, then set the bit for the target
9301 * to indicate that a device is present.
9303 if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 &&
9304 qdonep->d3.done_stat == QD_NO_ERROR &&
9305 qdonep->d3.host_stat == QHSTA_NO_ERROR) {
9306 boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id);
9312 static int AscIsrQDone(ASC_DVC_VAR *asc_dvc)
9321 ASC_SCSI_BIT_ID_TYPE scsi_busy;
9322 ASC_SCSI_BIT_ID_TYPE target_id;
9326 uchar cur_target_qng;
9327 ASC_QDONE_INFO scsiq_buf;
9328 ASC_QDONE_INFO *scsiq;
9331 iop_base = asc_dvc->iop_base;
9333 scsiq = (ASC_QDONE_INFO *)&scsiq_buf;
9334 done_q_tail = (uchar)AscGetVarDoneQTail(iop_base);
9335 q_addr = ASC_QNO_TO_QADDR(done_q_tail);
9336 next_qp = AscReadLramByte(iop_base,
9337 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_FWD));
9338 if (next_qp != ASC_QLINK_END) {
9339 AscPutVarDoneQTail(iop_base, next_qp);
9340 q_addr = ASC_QNO_TO_QADDR(next_qp);
9341 sg_queue_cnt = _AscCopyLramScsiDoneQ(iop_base, q_addr, scsiq,
9342 asc_dvc->max_dma_count);
9343 AscWriteLramByte(iop_base,
9345 (ushort)ASC_SCSIQ_B_STATUS),
9347 q_status & (uchar)~(QS_READY |
9349 tid_no = ASC_TIX_TO_TID(scsiq->d2.target_ix);
9350 target_id = ASC_TIX_TO_TARGET_ID(scsiq->d2.target_ix);
9351 if ((scsiq->cntl & QC_SG_HEAD) != 0) {
9353 sg_list_qp = next_qp;
9354 for (q_cnt = 0; q_cnt < sg_queue_cnt; q_cnt++) {
9355 sg_list_qp = AscReadLramByte(iop_base,
9359 sg_q_addr = ASC_QNO_TO_QADDR(sg_list_qp);
9360 if (sg_list_qp == ASC_QLINK_END) {
9361 AscSetLibErrorCode(asc_dvc,
9362 ASCQ_ERR_SG_Q_LINKS);
9363 scsiq->d3.done_stat = QD_WITH_ERROR;
9364 scsiq->d3.host_stat =
9365 QHSTA_D_QDONE_SG_LIST_CORRUPTED;
9366 goto FATAL_ERR_QDONE;
9368 AscWriteLramByte(iop_base,
9369 (ushort)(sg_q_addr + (ushort)
9370 ASC_SCSIQ_B_STATUS),
9373 n_q_used = sg_queue_cnt + 1;
9374 AscPutVarDoneQTail(iop_base, sg_list_qp);
9376 if (asc_dvc->queue_full_or_busy & target_id) {
9377 cur_target_qng = AscReadLramByte(iop_base,
9383 if (cur_target_qng < asc_dvc->max_dvc_qng[tid_no]) {
9384 scsi_busy = AscReadLramByte(iop_base, (ushort)
9386 scsi_busy &= ~target_id;
9387 AscWriteLramByte(iop_base,
9388 (ushort)ASCV_SCSIBUSY_B,
9390 asc_dvc->queue_full_or_busy &= ~target_id;
9393 if (asc_dvc->cur_total_qng >= n_q_used) {
9394 asc_dvc->cur_total_qng -= n_q_used;
9395 if (asc_dvc->cur_dvc_qng[tid_no] != 0) {
9396 asc_dvc->cur_dvc_qng[tid_no]--;
9399 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_CUR_QNG);
9400 scsiq->d3.done_stat = QD_WITH_ERROR;
9401 goto FATAL_ERR_QDONE;
9403 if ((scsiq->d2.srb_ptr == 0UL) ||
9404 ((scsiq->q_status & QS_ABORTED) != 0)) {
9406 } else if (scsiq->q_status == QS_DONE) {
9407 false_overrun = FALSE;
9408 if (scsiq->extra_bytes != 0) {
9409 scsiq->remain_bytes +=
9410 (ADV_DCNT)scsiq->extra_bytes;
9412 if (scsiq->d3.done_stat == QD_WITH_ERROR) {
9413 if (scsiq->d3.host_stat ==
9414 QHSTA_M_DATA_OVER_RUN) {
9416 cntl & (QC_DATA_IN | QC_DATA_OUT))
9418 scsiq->d3.done_stat =
9420 scsiq->d3.host_stat =
9422 } else if (false_overrun) {
9423 scsiq->d3.done_stat =
9425 scsiq->d3.host_stat =
9428 } else if (scsiq->d3.host_stat ==
9429 QHSTA_M_HUNG_REQ_SCSI_BUS_RESET) {
9430 AscStopChip(iop_base);
9431 AscSetChipControl(iop_base,
9432 (uchar)(CC_SCSI_RESET
9435 AscSetChipControl(iop_base, CC_HALT);
9436 AscSetChipStatus(iop_base,
9437 CIW_CLR_SCSI_RESET_INT);
9438 AscSetChipStatus(iop_base, 0);
9439 AscSetChipControl(iop_base, 0);
9442 if ((scsiq->cntl & QC_NO_CALLBACK) == 0) {
9443 asc_isr_callback(asc_dvc, scsiq);
9445 if ((AscReadLramByte(iop_base,
9446 (ushort)(q_addr + (ushort)
9449 asc_dvc->unit_not_ready &= ~target_id;
9450 if (scsiq->d3.done_stat != QD_NO_ERROR) {
9451 asc_dvc->start_motor &=
9458 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_Q_STATUS);
9460 if ((scsiq->cntl & QC_NO_CALLBACK) == 0) {
9461 asc_isr_callback(asc_dvc, scsiq);
9469 static int AscISR(ASC_DVC_VAR *asc_dvc)
9471 ASC_CS_TYPE chipstat;
9473 ushort saved_ram_addr;
9475 uchar saved_ctrl_reg;
9480 iop_base = asc_dvc->iop_base;
9481 int_pending = FALSE;
9483 if (AscIsIntPending(iop_base) == 0)
9486 if ((asc_dvc->init_state & ASC_INIT_STATE_END_LOAD_MC) == 0) {
9489 if (asc_dvc->in_critical_cnt != 0) {
9490 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_ON_CRITICAL);
9493 if (asc_dvc->is_in_int) {
9494 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_RE_ENTRY);
9497 asc_dvc->is_in_int = TRUE;
9498 ctrl_reg = AscGetChipControl(iop_base);
9499 saved_ctrl_reg = ctrl_reg & (~(CC_SCSI_RESET | CC_CHIP_RESET |
9500 CC_SINGLE_STEP | CC_DIAG | CC_TEST));
9501 chipstat = AscGetChipStatus(iop_base);
9502 if (chipstat & CSW_SCSI_RESET_LATCH) {
9503 if (!(asc_dvc->bus_type & (ASC_IS_VL | ASC_IS_EISA))) {
9506 asc_dvc->sdtr_done = 0;
9507 saved_ctrl_reg &= (uchar)(~CC_HALT);
9508 while ((AscGetChipStatus(iop_base) &
9509 CSW_SCSI_RESET_ACTIVE) && (i-- > 0)) {
9512 AscSetChipControl(iop_base, (CC_CHIP_RESET | CC_HALT));
9513 AscSetChipControl(iop_base, CC_HALT);
9514 AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT);
9515 AscSetChipStatus(iop_base, 0);
9516 chipstat = AscGetChipStatus(iop_base);
9519 saved_ram_addr = AscGetChipLramAddr(iop_base);
9520 host_flag = AscReadLramByte(iop_base,
9522 (uchar)(~ASC_HOST_FLAG_IN_ISR);
9523 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B,
9524 (uchar)(host_flag | (uchar)ASC_HOST_FLAG_IN_ISR));
9525 if ((chipstat & CSW_INT_PENDING) || (int_pending)) {
9526 AscAckInterrupt(iop_base);
9528 if ((chipstat & CSW_HALTED) && (ctrl_reg & CC_SINGLE_STEP)) {
9529 if (AscIsrChipHalted(asc_dvc) == ERR) {
9530 goto ISR_REPORT_QDONE_FATAL_ERROR;
9532 saved_ctrl_reg &= (uchar)(~CC_HALT);
9535 ISR_REPORT_QDONE_FATAL_ERROR:
9536 if ((asc_dvc->dvc_cntl & ASC_CNTL_INT_MULTI_Q) != 0) {
9538 AscIsrQDone(asc_dvc)) & 0x01) != 0) {
9543 AscIsrQDone(asc_dvc)) == 1) {
9546 } while (status == 0x11);
9548 if ((status & 0x80) != 0)
9552 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag);
9553 AscSetChipLramAddr(iop_base, saved_ram_addr);
9554 AscSetChipControl(iop_base, saved_ctrl_reg);
9555 asc_dvc->is_in_int = FALSE;
9562 * Reset the bus associated with the command 'scp'.
9564 * This function runs its own thread. Interrupts must be blocked but
9565 * sleeping is allowed and no locking other than for host structures is
9566 * required. Returns SUCCESS or FAILED.
9568 static int advansys_reset(struct scsi_cmnd *scp)
9570 struct Scsi_Host *shost = scp->device->host;
9571 struct asc_board *boardp = shost_priv(shost);
9572 unsigned long flags;
9576 ASC_DBG(1, "0x%p\n", scp);
9578 ASC_STATS(shost, reset);
9580 scmd_printk(KERN_INFO, scp, "SCSI bus reset started...\n");
9582 if (ASC_NARROW_BOARD(boardp)) {
9583 ASC_DVC_VAR *asc_dvc = &boardp->dvc_var.asc_dvc_var;
9585 /* Reset the chip and SCSI bus. */
9586 ASC_DBG(1, "before AscInitAsc1000Driver()\n");
9587 status = AscInitAsc1000Driver(asc_dvc);
9589 /* Refer to ASC_IERR_* defintions for meaning of 'err_code'. */
9590 if (asc_dvc->err_code) {
9591 scmd_printk(KERN_INFO, scp, "SCSI bus reset error: "
9592 "0x%x\n", asc_dvc->err_code);
9594 } else if (status) {
9595 scmd_printk(KERN_INFO, scp, "SCSI bus reset warning: "
9598 scmd_printk(KERN_INFO, scp, "SCSI bus reset "
9602 ASC_DBG(1, "after AscInitAsc1000Driver()\n");
9603 spin_lock_irqsave(shost->host_lock, flags);
9606 * If the suggest reset bus flags are set, then reset the bus.
9607 * Otherwise only reset the device.
9609 ADV_DVC_VAR *adv_dvc = &boardp->dvc_var.adv_dvc_var;
9612 * Reset the target's SCSI bus.
9614 ASC_DBG(1, "before AdvResetChipAndSB()\n");
9615 switch (AdvResetChipAndSB(adv_dvc)) {
9617 scmd_printk(KERN_INFO, scp, "SCSI bus reset "
9622 scmd_printk(KERN_INFO, scp, "SCSI bus reset error\n");
9626 spin_lock_irqsave(shost->host_lock, flags);
9630 /* Save the time of the most recently completed reset. */
9631 boardp->last_reset = jiffies;
9632 spin_unlock_irqrestore(shost->host_lock, flags);
9634 ASC_DBG(1, "ret %d\n", ret);
9640 * advansys_biosparam()
9642 * Translate disk drive geometry if the "BIOS greater than 1 GB"
9643 * support is enabled for a drive.
9645 * ip (information pointer) is an int array with the following definition:
9651 advansys_biosparam(struct scsi_device *sdev, struct block_device *bdev,
9652 sector_t capacity, int ip[])
9654 struct asc_board *boardp = shost_priv(sdev->host);
9656 ASC_DBG(1, "begin\n");
9657 ASC_STATS(sdev->host, biosparam);
9658 if (ASC_NARROW_BOARD(boardp)) {
9659 if ((boardp->dvc_var.asc_dvc_var.dvc_cntl &
9660 ASC_CNTL_BIOS_GT_1GB) && capacity > 0x200000) {
9668 if ((boardp->dvc_var.adv_dvc_var.bios_ctrl &
9669 BIOS_CTRL_EXTENDED_XLAT) && capacity > 0x200000) {
9677 ip[2] = (unsigned long)capacity / (ip[0] * ip[1]);
9678 ASC_DBG(1, "end\n");
9683 * First-level interrupt handler.
9685 * 'dev_id' is a pointer to the interrupting adapter's Scsi_Host.
9687 static irqreturn_t advansys_interrupt(int irq, void *dev_id)
9689 struct Scsi_Host *shost = dev_id;
9690 struct asc_board *boardp = shost_priv(shost);
9691 irqreturn_t result = IRQ_NONE;
9693 ASC_DBG(2, "boardp 0x%p\n", boardp);
9694 spin_lock(shost->host_lock);
9695 if (ASC_NARROW_BOARD(boardp)) {
9696 if (AscIsIntPending(shost->io_port)) {
9697 result = IRQ_HANDLED;
9698 ASC_STATS(shost, interrupt);
9699 ASC_DBG(1, "before AscISR()\n");
9700 AscISR(&boardp->dvc_var.asc_dvc_var);
9703 ASC_DBG(1, "before AdvISR()\n");
9704 if (AdvISR(&boardp->dvc_var.adv_dvc_var)) {
9705 result = IRQ_HANDLED;
9706 ASC_STATS(shost, interrupt);
9709 spin_unlock(shost->host_lock);
9711 ASC_DBG(1, "end\n");
9715 static int AscHostReqRiscHalt(PortAddr iop_base)
9719 uchar saved_stop_code;
9721 if (AscIsChipHalted(iop_base))
9723 saved_stop_code = AscReadLramByte(iop_base, ASCV_STOP_CODE_B);
9724 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B,
9725 ASC_STOP_HOST_REQ_RISC_HALT | ASC_STOP_REQ_RISC_STOP);
9727 if (AscIsChipHalted(iop_base)) {
9732 } while (count++ < 20);
9733 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, saved_stop_code);
9738 AscSetRunChipSynRegAtID(PortAddr iop_base, uchar tid_no, uchar sdtr_data)
9742 if (AscHostReqRiscHalt(iop_base)) {
9743 sta = AscSetChipSynRegAtID(iop_base, tid_no, sdtr_data);
9744 AscStartChip(iop_base);
9749 static void AscAsyncFix(ASC_DVC_VAR *asc_dvc, struct scsi_device *sdev)
9751 char type = sdev->type;
9752 ASC_SCSI_BIT_ID_TYPE tid_bits = 1 << sdev->id;
9754 if (!(asc_dvc->bug_fix_cntl & ASC_BUG_FIX_ASYN_USE_SYN))
9756 if (asc_dvc->init_sdtr & tid_bits)
9759 if ((type == TYPE_ROM) && (strncmp(sdev->vendor, "HP ", 3) == 0))
9760 asc_dvc->pci_fix_asyn_xfer_always |= tid_bits;
9762 asc_dvc->pci_fix_asyn_xfer |= tid_bits;
9763 if ((type == TYPE_PROCESSOR) || (type == TYPE_SCANNER) ||
9764 (type == TYPE_ROM) || (type == TYPE_TAPE))
9765 asc_dvc->pci_fix_asyn_xfer &= ~tid_bits;
9767 if (asc_dvc->pci_fix_asyn_xfer & tid_bits)
9768 AscSetRunChipSynRegAtID(asc_dvc->iop_base, sdev->id,
9769 ASYN_SDTR_DATA_FIX_PCI_REV_AB);
9773 advansys_narrow_slave_configure(struct scsi_device *sdev, ASC_DVC_VAR *asc_dvc)
9775 ASC_SCSI_BIT_ID_TYPE tid_bit = 1 << sdev->id;
9776 ASC_SCSI_BIT_ID_TYPE orig_use_tagged_qng = asc_dvc->use_tagged_qng;
9778 if (sdev->lun == 0) {
9779 ASC_SCSI_BIT_ID_TYPE orig_init_sdtr = asc_dvc->init_sdtr;
9780 if ((asc_dvc->cfg->sdtr_enable & tid_bit) && sdev->sdtr) {
9781 asc_dvc->init_sdtr |= tid_bit;
9783 asc_dvc->init_sdtr &= ~tid_bit;
9786 if (orig_init_sdtr != asc_dvc->init_sdtr)
9787 AscAsyncFix(asc_dvc, sdev);
9790 if (sdev->tagged_supported) {
9791 if (asc_dvc->cfg->cmd_qng_enabled & tid_bit) {
9792 if (sdev->lun == 0) {
9793 asc_dvc->cfg->can_tagged_qng |= tid_bit;
9794 asc_dvc->use_tagged_qng |= tid_bit;
9796 scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG,
9797 asc_dvc->max_dvc_qng[sdev->id]);
9800 if (sdev->lun == 0) {
9801 asc_dvc->cfg->can_tagged_qng &= ~tid_bit;
9802 asc_dvc->use_tagged_qng &= ~tid_bit;
9804 scsi_adjust_queue_depth(sdev, 0, sdev->host->cmd_per_lun);
9807 if ((sdev->lun == 0) &&
9808 (orig_use_tagged_qng != asc_dvc->use_tagged_qng)) {
9809 AscWriteLramByte(asc_dvc->iop_base, ASCV_DISC_ENABLE_B,
9810 asc_dvc->cfg->disc_enable);
9811 AscWriteLramByte(asc_dvc->iop_base, ASCV_USE_TAGGED_QNG_B,
9812 asc_dvc->use_tagged_qng);
9813 AscWriteLramByte(asc_dvc->iop_base, ASCV_CAN_TAGGED_QNG_B,
9814 asc_dvc->cfg->can_tagged_qng);
9816 asc_dvc->max_dvc_qng[sdev->id] =
9817 asc_dvc->cfg->max_tag_qng[sdev->id];
9818 AscWriteLramByte(asc_dvc->iop_base,
9819 (ushort)(ASCV_MAX_DVC_QNG_BEG + sdev->id),
9820 asc_dvc->max_dvc_qng[sdev->id]);
9827 * If the EEPROM enabled WDTR for the device and the device supports wide
9828 * bus (16 bit) transfers, then turn on the device's 'wdtr_able' bit and
9829 * write the new value to the microcode.
9832 advansys_wide_enable_wdtr(AdvPortAddr iop_base, unsigned short tidmask)
9834 unsigned short cfg_word;
9835 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, cfg_word);
9836 if ((cfg_word & tidmask) != 0)
9839 cfg_word |= tidmask;
9840 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, cfg_word);
9843 * Clear the microcode SDTR and WDTR negotiation done indicators for
9844 * the target to cause it to negotiate with the new setting set above.
9845 * WDTR when accepted causes the target to enter asynchronous mode, so
9846 * SDTR must be negotiated.
9848 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
9849 cfg_word &= ~tidmask;
9850 AdvWriteWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
9851 AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, cfg_word);
9852 cfg_word &= ~tidmask;
9853 AdvWriteWordLram(iop_base, ASC_MC_WDTR_DONE, cfg_word);
9857 * Synchronous Transfers
9859 * If the EEPROM enabled SDTR for the device and the device
9860 * supports synchronous transfers, then turn on the device's
9861 * 'sdtr_able' bit. Write the new value to the microcode.
9864 advansys_wide_enable_sdtr(AdvPortAddr iop_base, unsigned short tidmask)
9866 unsigned short cfg_word;
9867 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, cfg_word);
9868 if ((cfg_word & tidmask) != 0)
9871 cfg_word |= tidmask;
9872 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, cfg_word);
9875 * Clear the microcode "SDTR negotiation" done indicator for the
9876 * target to cause it to negotiate with the new setting set above.
9878 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
9879 cfg_word &= ~tidmask;
9880 AdvWriteWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
9884 * PPR (Parallel Protocol Request) Capable
9886 * If the device supports DT mode, then it must be PPR capable.
9887 * The PPR message will be used in place of the SDTR and WDTR
9888 * messages to negotiate synchronous speed and offset, transfer
9889 * width, and protocol options.
9891 static void advansys_wide_enable_ppr(ADV_DVC_VAR *adv_dvc,
9892 AdvPortAddr iop_base, unsigned short tidmask)
9894 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, adv_dvc->ppr_able);
9895 adv_dvc->ppr_able |= tidmask;
9896 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, adv_dvc->ppr_able);
9900 advansys_wide_slave_configure(struct scsi_device *sdev, ADV_DVC_VAR *adv_dvc)
9902 AdvPortAddr iop_base = adv_dvc->iop_base;
9903 unsigned short tidmask = 1 << sdev->id;
9905 if (sdev->lun == 0) {
9907 * Handle WDTR, SDTR, and Tag Queuing. If the feature
9908 * is enabled in the EEPROM and the device supports the
9909 * feature, then enable it in the microcode.
9912 if ((adv_dvc->wdtr_able & tidmask) && sdev->wdtr)
9913 advansys_wide_enable_wdtr(iop_base, tidmask);
9914 if ((adv_dvc->sdtr_able & tidmask) && sdev->sdtr)
9915 advansys_wide_enable_sdtr(iop_base, tidmask);
9916 if (adv_dvc->chip_type == ADV_CHIP_ASC38C1600 && sdev->ppr)
9917 advansys_wide_enable_ppr(adv_dvc, iop_base, tidmask);
9920 * Tag Queuing is disabled for the BIOS which runs in polled
9921 * mode and would see no benefit from Tag Queuing. Also by
9922 * disabling Tag Queuing in the BIOS devices with Tag Queuing
9923 * bugs will at least work with the BIOS.
9925 if ((adv_dvc->tagqng_able & tidmask) &&
9926 sdev->tagged_supported) {
9927 unsigned short cfg_word;
9928 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, cfg_word);
9929 cfg_word |= tidmask;
9930 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
9932 AdvWriteByteLram(iop_base,
9933 ASC_MC_NUMBER_OF_MAX_CMD + sdev->id,
9934 adv_dvc->max_dvc_qng);
9938 if ((adv_dvc->tagqng_able & tidmask) && sdev->tagged_supported) {
9939 scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG,
9940 adv_dvc->max_dvc_qng);
9942 scsi_adjust_queue_depth(sdev, 0, sdev->host->cmd_per_lun);
9947 * Set the number of commands to queue per device for the
9948 * specified host adapter.
9950 static int advansys_slave_configure(struct scsi_device *sdev)
9952 struct asc_board *boardp = shost_priv(sdev->host);
9954 if (ASC_NARROW_BOARD(boardp))
9955 advansys_narrow_slave_configure(sdev,
9956 &boardp->dvc_var.asc_dvc_var);
9958 advansys_wide_slave_configure(sdev,
9959 &boardp->dvc_var.adv_dvc_var);
9964 static int asc_build_req(struct asc_board *boardp, struct scsi_cmnd *scp,
9965 struct asc_scsi_q *asc_scsi_q)
9967 memset(asc_scsi_q, 0, sizeof(*asc_scsi_q));
9970 * Point the ASC_SCSI_Q to the 'struct scsi_cmnd'.
9972 asc_scsi_q->q2.srb_ptr = ASC_VADDR_TO_U32(scp);
9975 * Build the ASC_SCSI_Q request.
9977 asc_scsi_q->cdbptr = &scp->cmnd[0];
9978 asc_scsi_q->q2.cdb_len = scp->cmd_len;
9979 asc_scsi_q->q1.target_id = ASC_TID_TO_TARGET_ID(scp->device->id);
9980 asc_scsi_q->q1.target_lun = scp->device->lun;
9981 asc_scsi_q->q2.target_ix =
9982 ASC_TIDLUN_TO_IX(scp->device->id, scp->device->lun);
9983 asc_scsi_q->q1.sense_addr =
9984 cpu_to_le32(virt_to_bus(&scp->sense_buffer[0]));
9985 asc_scsi_q->q1.sense_len = sizeof(scp->sense_buffer);
9988 * If there are any outstanding requests for the current target,
9989 * then every 255th request send an ORDERED request. This heuristic
9990 * tries to retain the benefit of request sorting while preventing
9991 * request starvation. 255 is the max number of tags or pending commands
9992 * a device may have outstanding.
9994 * The request count is incremented below for every successfully
9998 if ((boardp->dvc_var.asc_dvc_var.cur_dvc_qng[scp->device->id] > 0) &&
9999 (boardp->reqcnt[scp->device->id] % 255) == 0) {
10000 asc_scsi_q->q2.tag_code = MSG_ORDERED_TAG;
10002 asc_scsi_q->q2.tag_code = MSG_SIMPLE_TAG;
10006 * Build ASC_SCSI_Q for a contiguous buffer or a scatter-gather
10009 if (scp->use_sg == 0) {
10011 * CDB request of single contiguous buffer.
10013 ASC_STATS(scp->device->host, cont_cnt);
10014 scp->SCp.dma_handle = scp->request_bufflen ?
10015 dma_map_single(boardp->dev, scp->request_buffer,
10016 scp->request_bufflen,
10017 scp->sc_data_direction) : 0;
10018 asc_scsi_q->q1.data_addr = cpu_to_le32(scp->SCp.dma_handle);
10019 asc_scsi_q->q1.data_cnt = cpu_to_le32(scp->request_bufflen);
10020 ASC_STATS_ADD(scp->device->host, cont_xfer,
10021 ASC_CEILING(scp->request_bufflen, 512));
10022 asc_scsi_q->q1.sg_queue_cnt = 0;
10023 asc_scsi_q->sg_head = NULL;
10026 * CDB scatter-gather request list.
10030 struct scatterlist *slp;
10031 struct asc_sg_head *asc_sg_head;
10033 slp = (struct scatterlist *)scp->request_buffer;
10034 use_sg = dma_map_sg(boardp->dev, slp, scp->use_sg,
10035 scp->sc_data_direction);
10037 if (use_sg > scp->device->host->sg_tablesize) {
10038 scmd_printk(KERN_ERR, scp, "use_sg %d > "
10039 "sg_tablesize %d\n", use_sg,
10040 scp->device->host->sg_tablesize);
10041 dma_unmap_sg(boardp->dev, slp, scp->use_sg,
10042 scp->sc_data_direction);
10043 scp->result = HOST_BYTE(DID_ERROR);
10047 ASC_STATS(scp->device->host, sg_cnt);
10049 asc_sg_head = kzalloc(sizeof(asc_scsi_q->sg_head) +
10050 use_sg * sizeof(struct asc_sg_list), GFP_ATOMIC);
10051 if (!asc_sg_head) {
10052 dma_unmap_sg(boardp->dev, slp, scp->use_sg,
10053 scp->sc_data_direction);
10054 scp->result = HOST_BYTE(DID_SOFT_ERROR);
10058 asc_scsi_q->q1.cntl |= QC_SG_HEAD;
10059 asc_scsi_q->sg_head = asc_sg_head;
10060 asc_scsi_q->q1.data_cnt = 0;
10061 asc_scsi_q->q1.data_addr = 0;
10062 /* This is a byte value, otherwise it would need to be swapped. */
10063 asc_sg_head->entry_cnt = asc_scsi_q->q1.sg_queue_cnt = use_sg;
10064 ASC_STATS_ADD(scp->device->host, sg_elem,
10065 asc_sg_head->entry_cnt);
10068 * Convert scatter-gather list into ASC_SG_HEAD list.
10070 for (sgcnt = 0; sgcnt < use_sg; sgcnt++, slp++) {
10071 asc_sg_head->sg_list[sgcnt].addr =
10072 cpu_to_le32(sg_dma_address(slp));
10073 asc_sg_head->sg_list[sgcnt].bytes =
10074 cpu_to_le32(sg_dma_len(slp));
10075 ASC_STATS_ADD(scp->device->host, sg_xfer,
10076 ASC_CEILING(sg_dma_len(slp), 512));
10080 ASC_DBG_PRT_ASC_SCSI_Q(2, asc_scsi_q);
10081 ASC_DBG_PRT_CDB(1, scp->cmnd, scp->cmd_len);
10083 return ASC_NOERROR;
10087 * Build scatter-gather list for Adv Library (Wide Board).
10089 * Additional ADV_SG_BLOCK structures will need to be allocated
10090 * if the total number of scatter-gather elements exceeds
10091 * NO_OF_SG_PER_BLOCK (15). The ADV_SG_BLOCK structures are
10092 * assumed to be physically contiguous.
10095 * ADV_SUCCESS(1) - SG List successfully created
10096 * ADV_ERROR(-1) - SG List creation failed
10099 adv_get_sglist(struct asc_board *boardp, adv_req_t *reqp, struct scsi_cmnd *scp,
10102 adv_sgblk_t *sgblkp;
10103 ADV_SCSI_REQ_Q *scsiqp;
10104 struct scatterlist *slp;
10106 ADV_SG_BLOCK *sg_block, *prev_sg_block;
10107 ADV_PADDR sg_block_paddr;
10110 scsiqp = (ADV_SCSI_REQ_Q *)ADV_32BALIGN(&reqp->scsi_req_q);
10111 slp = (struct scatterlist *)scp->request_buffer;
10112 sg_elem_cnt = use_sg;
10113 prev_sg_block = NULL;
10114 reqp->sgblkp = NULL;
10118 * Allocate a 'adv_sgblk_t' structure from the board free
10119 * list. One 'adv_sgblk_t' structure holds NO_OF_SG_PER_BLOCK
10120 * (15) scatter-gather elements.
10122 if ((sgblkp = boardp->adv_sgblkp) == NULL) {
10123 ASC_DBG(1, "no free adv_sgblk_t\n");
10124 ASC_STATS(scp->device->host, adv_build_nosg);
10127 * Allocation failed. Free 'adv_sgblk_t' structures
10128 * already allocated for the request.
10130 while ((sgblkp = reqp->sgblkp) != NULL) {
10131 /* Remove 'sgblkp' from the request list. */
10132 reqp->sgblkp = sgblkp->next_sgblkp;
10134 /* Add 'sgblkp' to the board free list. */
10135 sgblkp->next_sgblkp = boardp->adv_sgblkp;
10136 boardp->adv_sgblkp = sgblkp;
10141 /* Complete 'adv_sgblk_t' board allocation. */
10142 boardp->adv_sgblkp = sgblkp->next_sgblkp;
10143 sgblkp->next_sgblkp = NULL;
10146 * Get 8 byte aligned virtual and physical addresses
10147 * for the allocated ADV_SG_BLOCK structure.
10149 sg_block = (ADV_SG_BLOCK *)ADV_8BALIGN(&sgblkp->sg_block);
10150 sg_block_paddr = virt_to_bus(sg_block);
10153 * Check if this is the first 'adv_sgblk_t' for the
10156 if (reqp->sgblkp == NULL) {
10157 /* Request's first scatter-gather block. */
10158 reqp->sgblkp = sgblkp;
10161 * Set ADV_SCSI_REQ_T ADV_SG_BLOCK virtual and physical
10162 * address pointers.
10164 scsiqp->sg_list_ptr = sg_block;
10165 scsiqp->sg_real_addr = cpu_to_le32(sg_block_paddr);
10167 /* Request's second or later scatter-gather block. */
10168 sgblkp->next_sgblkp = reqp->sgblkp;
10169 reqp->sgblkp = sgblkp;
10172 * Point the previous ADV_SG_BLOCK structure to
10173 * the newly allocated ADV_SG_BLOCK structure.
10175 prev_sg_block->sg_ptr = cpu_to_le32(sg_block_paddr);
10178 for (i = 0; i < NO_OF_SG_PER_BLOCK; i++) {
10179 sg_block->sg_list[i].sg_addr =
10180 cpu_to_le32(sg_dma_address(slp));
10181 sg_block->sg_list[i].sg_count =
10182 cpu_to_le32(sg_dma_len(slp));
10183 ASC_STATS_ADD(scp->device->host, sg_xfer,
10184 ASC_CEILING(sg_dma_len(slp), 512));
10186 if (--sg_elem_cnt == 0) { /* Last ADV_SG_BLOCK and scatter-gather entry. */
10187 sg_block->sg_cnt = i + 1;
10188 sg_block->sg_ptr = 0L; /* Last ADV_SG_BLOCK in list. */
10189 return ADV_SUCCESS;
10193 sg_block->sg_cnt = NO_OF_SG_PER_BLOCK;
10194 prev_sg_block = sg_block;
10199 * Build a request structure for the Adv Library (Wide Board).
10201 * If an adv_req_t can not be allocated to issue the request,
10202 * then return ASC_BUSY. If an error occurs, then return ASC_ERROR.
10204 * Multi-byte fields in the ASC_SCSI_REQ_Q that are used by the
10205 * microcode for DMA addresses or math operations are byte swapped
10206 * to little-endian order.
10209 adv_build_req(struct asc_board *boardp, struct scsi_cmnd *scp,
10210 ADV_SCSI_REQ_Q **adv_scsiqpp)
10213 ADV_SCSI_REQ_Q *scsiqp;
10218 * Allocate an adv_req_t structure from the board to execute
10221 if (boardp->adv_reqp == NULL) {
10222 ASC_DBG(1, "no free adv_req_t\n");
10223 ASC_STATS(scp->device->host, adv_build_noreq);
10226 reqp = boardp->adv_reqp;
10227 boardp->adv_reqp = reqp->next_reqp;
10228 reqp->next_reqp = NULL;
10232 * Get 32-byte aligned ADV_SCSI_REQ_Q and ADV_SG_BLOCK pointers.
10234 scsiqp = (ADV_SCSI_REQ_Q *)ADV_32BALIGN(&reqp->scsi_req_q);
10237 * Initialize the structure.
10239 scsiqp->cntl = scsiqp->scsi_cntl = scsiqp->done_status = 0;
10242 * Set the ADV_SCSI_REQ_Q 'srb_ptr' to point to the adv_req_t structure.
10244 scsiqp->srb_ptr = ASC_VADDR_TO_U32(reqp);
10247 * Set the adv_req_t 'cmndp' to point to the struct scsi_cmnd structure.
10252 * Build the ADV_SCSI_REQ_Q request.
10255 /* Set CDB length and copy it to the request structure. */
10256 scsiqp->cdb_len = scp->cmd_len;
10257 /* Copy first 12 CDB bytes to cdb[]. */
10258 for (i = 0; i < scp->cmd_len && i < 12; i++) {
10259 scsiqp->cdb[i] = scp->cmnd[i];
10261 /* Copy last 4 CDB bytes, if present, to cdb16[]. */
10262 for (; i < scp->cmd_len; i++) {
10263 scsiqp->cdb16[i - 12] = scp->cmnd[i];
10266 scsiqp->target_id = scp->device->id;
10267 scsiqp->target_lun = scp->device->lun;
10269 scsiqp->sense_addr = cpu_to_le32(virt_to_bus(&scp->sense_buffer[0]));
10270 scsiqp->sense_len = sizeof(scp->sense_buffer);
10273 * Build ADV_SCSI_REQ_Q for a contiguous buffer or a scatter-gather
10277 scsiqp->data_cnt = cpu_to_le32(scp->request_bufflen);
10278 scsiqp->vdata_addr = scp->request_buffer;
10279 scsiqp->data_addr = cpu_to_le32(virt_to_bus(scp->request_buffer));
10281 if (scp->use_sg == 0) {
10283 * CDB request of single contiguous buffer.
10285 reqp->sgblkp = NULL;
10286 scsiqp->data_cnt = cpu_to_le32(scp->request_bufflen);
10287 if (scp->request_bufflen) {
10288 scsiqp->vdata_addr = scp->request_buffer;
10289 scp->SCp.dma_handle =
10290 dma_map_single(boardp->dev, scp->request_buffer,
10291 scp->request_bufflen,
10292 scp->sc_data_direction);
10294 scsiqp->vdata_addr = NULL;
10295 scp->SCp.dma_handle = 0;
10297 scsiqp->data_addr = cpu_to_le32(scp->SCp.dma_handle);
10298 scsiqp->sg_list_ptr = NULL;
10299 scsiqp->sg_real_addr = 0;
10300 ASC_STATS(scp->device->host, cont_cnt);
10301 ASC_STATS_ADD(scp->device->host, cont_xfer,
10302 ASC_CEILING(scp->request_bufflen, 512));
10305 * CDB scatter-gather request list.
10307 struct scatterlist *slp;
10310 slp = (struct scatterlist *)scp->request_buffer;
10311 use_sg = dma_map_sg(boardp->dev, slp, scp->use_sg,
10312 scp->sc_data_direction);
10314 if (use_sg > ADV_MAX_SG_LIST) {
10315 scmd_printk(KERN_ERR, scp, "use_sg %d > "
10316 "ADV_MAX_SG_LIST %d\n", use_sg,
10317 scp->device->host->sg_tablesize);
10318 dma_unmap_sg(boardp->dev, slp, scp->use_sg,
10319 scp->sc_data_direction);
10320 scp->result = HOST_BYTE(DID_ERROR);
10323 * Free the 'adv_req_t' structure by adding it back
10324 * to the board free list.
10326 reqp->next_reqp = boardp->adv_reqp;
10327 boardp->adv_reqp = reqp;
10332 ret = adv_get_sglist(boardp, reqp, scp, use_sg);
10333 if (ret != ADV_SUCCESS) {
10335 * Free the adv_req_t structure by adding it back to
10336 * the board free list.
10338 reqp->next_reqp = boardp->adv_reqp;
10339 boardp->adv_reqp = reqp;
10344 ASC_STATS(scp->device->host, sg_cnt);
10345 ASC_STATS_ADD(scp->device->host, sg_elem, use_sg);
10348 ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp);
10349 ASC_DBG_PRT_CDB(1, scp->cmnd, scp->cmd_len);
10351 *adv_scsiqpp = scsiqp;
10353 return ASC_NOERROR;
10356 static int AscSgListToQueue(int sg_list)
10360 n_sg_list_qs = ((sg_list - 1) / ASC_SG_LIST_PER_Q);
10361 if (((sg_list - 1) % ASC_SG_LIST_PER_Q) != 0)
10363 return n_sg_list_qs + 1;
10367 AscGetNumOfFreeQueue(ASC_DVC_VAR *asc_dvc, uchar target_ix, uchar n_qs)
10371 ASC_SCSI_BIT_ID_TYPE target_id;
10374 target_id = ASC_TIX_TO_TARGET_ID(target_ix);
10375 tid_no = ASC_TIX_TO_TID(target_ix);
10376 if ((asc_dvc->unit_not_ready & target_id) ||
10377 (asc_dvc->queue_full_or_busy & target_id)) {
10381 cur_used_qs = (uint) asc_dvc->cur_total_qng +
10382 (uint) asc_dvc->last_q_shortage + (uint) ASC_MIN_FREE_Q;
10384 cur_used_qs = (uint) asc_dvc->cur_total_qng +
10385 (uint) ASC_MIN_FREE_Q;
10387 if ((uint) (cur_used_qs + n_qs) <= (uint) asc_dvc->max_total_qng) {
10388 cur_free_qs = (uint) asc_dvc->max_total_qng - cur_used_qs;
10389 if (asc_dvc->cur_dvc_qng[tid_no] >=
10390 asc_dvc->max_dvc_qng[tid_no]) {
10393 return cur_free_qs;
10396 if ((n_qs > asc_dvc->last_q_shortage)
10397 && (n_qs <= (asc_dvc->max_total_qng - ASC_MIN_FREE_Q))) {
10398 asc_dvc->last_q_shortage = n_qs;
10404 static uchar AscAllocFreeQueue(PortAddr iop_base, uchar free_q_head)
10410 q_addr = ASC_QNO_TO_QADDR(free_q_head);
10411 q_status = (uchar)AscReadLramByte(iop_base,
10413 ASC_SCSIQ_B_STATUS));
10414 next_qp = AscReadLramByte(iop_base, (ushort)(q_addr + ASC_SCSIQ_B_FWD));
10415 if (((q_status & QS_READY) == 0) && (next_qp != ASC_QLINK_END))
10417 return ASC_QLINK_END;
10421 AscAllocMultipleFreeQueue(PortAddr iop_base, uchar free_q_head, uchar n_free_q)
10425 for (i = 0; i < n_free_q; i++) {
10426 free_q_head = AscAllocFreeQueue(iop_base, free_q_head);
10427 if (free_q_head == ASC_QLINK_END)
10430 return free_q_head;
10435 * DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words)
10437 * Calling/Exit State:
10441 * Output an ASC_SCSI_Q structure to the chip
10444 DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words)
10448 ASC_DBG_PRT_HEX(2, "DvcPutScsiQ", outbuf, 2 * words);
10449 AscSetChipLramAddr(iop_base, s_addr);
10450 for (i = 0; i < 2 * words; i += 2) {
10451 if (i == 4 || i == 20) {
10454 outpw(iop_base + IOP_RAM_DATA,
10455 ((ushort)outbuf[i + 1] << 8) | outbuf[i]);
10459 static int AscPutReadyQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar q_no)
10464 uchar syn_period_ix;
10468 iop_base = asc_dvc->iop_base;
10469 if (((asc_dvc->init_sdtr & scsiq->q1.target_id) != 0) &&
10470 ((asc_dvc->sdtr_done & scsiq->q1.target_id) == 0)) {
10471 tid_no = ASC_TIX_TO_TID(scsiq->q2.target_ix);
10472 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
10474 (sdtr_data >> 4) & (asc_dvc->max_sdtr_index - 1);
10475 syn_offset = sdtr_data & ASC_SYN_MAX_OFFSET;
10476 AscMsgOutSDTR(asc_dvc,
10477 asc_dvc->sdtr_period_tbl[syn_period_ix],
10479 scsiq->q1.cntl |= QC_MSG_OUT;
10481 q_addr = ASC_QNO_TO_QADDR(q_no);
10482 if ((scsiq->q1.target_id & asc_dvc->use_tagged_qng) == 0) {
10483 scsiq->q2.tag_code &= ~MSG_SIMPLE_TAG;
10485 scsiq->q1.status = QS_FREE;
10486 AscMemWordCopyPtrToLram(iop_base,
10487 q_addr + ASC_SCSIQ_CDB_BEG,
10488 (uchar *)scsiq->cdbptr, scsiq->q2.cdb_len >> 1);
10490 DvcPutScsiQ(iop_base,
10491 q_addr + ASC_SCSIQ_CPY_BEG,
10492 (uchar *)&scsiq->q1.cntl,
10493 ((sizeof(ASC_SCSIQ_1) + sizeof(ASC_SCSIQ_2)) / 2) - 1);
10494 AscWriteLramWord(iop_base,
10495 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_STATUS),
10496 (ushort)(((ushort)scsiq->q1.
10497 q_no << 8) | (ushort)QS_READY));
10502 AscPutReadySgListQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar q_no)
10506 ASC_SG_HEAD *sg_head;
10507 ASC_SG_LIST_Q scsi_sg_q;
10508 ASC_DCNT saved_data_addr;
10509 ASC_DCNT saved_data_cnt;
10511 ushort sg_list_dwords;
10513 ushort sg_entry_cnt;
10517 iop_base = asc_dvc->iop_base;
10518 sg_head = scsiq->sg_head;
10519 saved_data_addr = scsiq->q1.data_addr;
10520 saved_data_cnt = scsiq->q1.data_cnt;
10521 scsiq->q1.data_addr = (ASC_PADDR) sg_head->sg_list[0].addr;
10522 scsiq->q1.data_cnt = (ASC_DCNT) sg_head->sg_list[0].bytes;
10523 #if CC_VERY_LONG_SG_LIST
10525 * If sg_head->entry_cnt is greater than ASC_MAX_SG_LIST
10526 * then not all SG elements will fit in the allocated queues.
10527 * The rest of the SG elements will be copied when the RISC
10528 * completes the SG elements that fit and halts.
10530 if (sg_head->entry_cnt > ASC_MAX_SG_LIST) {
10532 * Set sg_entry_cnt to be the number of SG elements that
10533 * will fit in the allocated SG queues. It is minus 1, because
10534 * the first SG element is handled above. ASC_MAX_SG_LIST is
10535 * already inflated by 1 to account for this. For example it
10536 * may be 50 which is 1 + 7 queues * 7 SG elements.
10538 sg_entry_cnt = ASC_MAX_SG_LIST - 1;
10541 * Keep track of remaining number of SG elements that will
10542 * need to be handled from a_isr.c.
10544 scsiq->remain_sg_entry_cnt =
10545 sg_head->entry_cnt - ASC_MAX_SG_LIST;
10547 #endif /* CC_VERY_LONG_SG_LIST */
10549 * Set sg_entry_cnt to be the number of SG elements that
10550 * will fit in the allocated SG queues. It is minus 1, because
10551 * the first SG element is handled above.
10553 sg_entry_cnt = sg_head->entry_cnt - 1;
10554 #if CC_VERY_LONG_SG_LIST
10556 #endif /* CC_VERY_LONG_SG_LIST */
10557 if (sg_entry_cnt != 0) {
10558 scsiq->q1.cntl |= QC_SG_HEAD;
10559 q_addr = ASC_QNO_TO_QADDR(q_no);
10561 scsiq->q1.sg_queue_cnt = sg_head->queue_cnt;
10562 scsi_sg_q.sg_head_qp = q_no;
10563 scsi_sg_q.cntl = QCSG_SG_XFER_LIST;
10564 for (i = 0; i < sg_head->queue_cnt; i++) {
10565 scsi_sg_q.seq_no = i + 1;
10566 if (sg_entry_cnt > ASC_SG_LIST_PER_Q) {
10567 sg_list_dwords = (uchar)(ASC_SG_LIST_PER_Q * 2);
10568 sg_entry_cnt -= ASC_SG_LIST_PER_Q;
10570 scsi_sg_q.sg_list_cnt =
10572 scsi_sg_q.sg_cur_list_cnt =
10575 scsi_sg_q.sg_list_cnt =
10576 ASC_SG_LIST_PER_Q - 1;
10577 scsi_sg_q.sg_cur_list_cnt =
10578 ASC_SG_LIST_PER_Q - 1;
10581 #if CC_VERY_LONG_SG_LIST
10583 * This is the last SG queue in the list of
10584 * allocated SG queues. If there are more
10585 * SG elements than will fit in the allocated
10586 * queues, then set the QCSG_SG_XFER_MORE flag.
10588 if (sg_head->entry_cnt > ASC_MAX_SG_LIST) {
10589 scsi_sg_q.cntl |= QCSG_SG_XFER_MORE;
10591 #endif /* CC_VERY_LONG_SG_LIST */
10592 scsi_sg_q.cntl |= QCSG_SG_XFER_END;
10593 #if CC_VERY_LONG_SG_LIST
10595 #endif /* CC_VERY_LONG_SG_LIST */
10596 sg_list_dwords = sg_entry_cnt << 1;
10598 scsi_sg_q.sg_list_cnt = sg_entry_cnt;
10599 scsi_sg_q.sg_cur_list_cnt =
10602 scsi_sg_q.sg_list_cnt =
10604 scsi_sg_q.sg_cur_list_cnt =
10609 next_qp = AscReadLramByte(iop_base,
10612 scsi_sg_q.q_no = next_qp;
10613 q_addr = ASC_QNO_TO_QADDR(next_qp);
10614 AscMemWordCopyPtrToLram(iop_base,
10615 q_addr + ASC_SCSIQ_SGHD_CPY_BEG,
10616 (uchar *)&scsi_sg_q,
10617 sizeof(ASC_SG_LIST_Q) >> 1);
10618 AscMemDWordCopyPtrToLram(iop_base,
10619 q_addr + ASC_SGQ_LIST_BEG,
10620 (uchar *)&sg_head->
10623 sg_index += ASC_SG_LIST_PER_Q;
10624 scsiq->next_sg_index = sg_index;
10627 scsiq->q1.cntl &= ~QC_SG_HEAD;
10629 sta = AscPutReadyQueue(asc_dvc, scsiq, q_no);
10630 scsiq->q1.data_addr = saved_data_addr;
10631 scsiq->q1.data_cnt = saved_data_cnt;
10636 AscSendScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar n_q_required)
10645 iop_base = asc_dvc->iop_base;
10646 target_ix = scsiq->q2.target_ix;
10647 tid_no = ASC_TIX_TO_TID(target_ix);
10649 free_q_head = (uchar)AscGetVarFreeQHead(iop_base);
10650 if (n_q_required > 1) {
10651 next_qp = AscAllocMultipleFreeQueue(iop_base, free_q_head,
10652 (uchar)n_q_required);
10653 if (next_qp != ASC_QLINK_END) {
10654 asc_dvc->last_q_shortage = 0;
10655 scsiq->sg_head->queue_cnt = n_q_required - 1;
10656 scsiq->q1.q_no = free_q_head;
10657 sta = AscPutReadySgListQueue(asc_dvc, scsiq,
10660 } else if (n_q_required == 1) {
10661 next_qp = AscAllocFreeQueue(iop_base, free_q_head);
10662 if (next_qp != ASC_QLINK_END) {
10663 scsiq->q1.q_no = free_q_head;
10664 sta = AscPutReadyQueue(asc_dvc, scsiq, free_q_head);
10668 AscPutVarFreeQHead(iop_base, next_qp);
10669 asc_dvc->cur_total_qng += n_q_required;
10670 asc_dvc->cur_dvc_qng[tid_no]++;
10675 #define ASC_SYN_OFFSET_ONE_DISABLE_LIST 16
10676 static uchar _syn_offset_one_disable_cmd[ASC_SYN_OFFSET_ONE_DISABLE_LIST] = {
10695 static int AscExeScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq)
10700 int disable_syn_offset_one_fix;
10703 ushort sg_entry_cnt = 0;
10704 ushort sg_entry_cnt_minus_one = 0;
10711 ASC_SG_HEAD *sg_head;
10714 iop_base = asc_dvc->iop_base;
10715 sg_head = scsiq->sg_head;
10716 if (asc_dvc->err_code != 0)
10718 scsiq->q1.q_no = 0;
10719 if ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0) {
10720 scsiq->q1.extra_bytes = 0;
10723 target_ix = scsiq->q2.target_ix;
10724 tid_no = ASC_TIX_TO_TID(target_ix);
10726 if (scsiq->cdbptr[0] == REQUEST_SENSE) {
10727 if ((asc_dvc->init_sdtr & scsiq->q1.target_id) != 0) {
10728 asc_dvc->sdtr_done &= ~scsiq->q1.target_id;
10729 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
10730 AscMsgOutSDTR(asc_dvc,
10732 sdtr_period_tbl[(sdtr_data >> 4) &
10736 (uchar)(sdtr_data & (uchar)
10737 ASC_SYN_MAX_OFFSET));
10738 scsiq->q1.cntl |= (QC_MSG_OUT | QC_URGENT);
10741 if (asc_dvc->in_critical_cnt != 0) {
10742 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_CRITICAL_RE_ENTRY);
10745 asc_dvc->in_critical_cnt++;
10746 if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) {
10747 if ((sg_entry_cnt = sg_head->entry_cnt) == 0) {
10748 asc_dvc->in_critical_cnt--;
10751 #if !CC_VERY_LONG_SG_LIST
10752 if (sg_entry_cnt > ASC_MAX_SG_LIST) {
10753 asc_dvc->in_critical_cnt--;
10756 #endif /* !CC_VERY_LONG_SG_LIST */
10757 if (sg_entry_cnt == 1) {
10758 scsiq->q1.data_addr =
10759 (ADV_PADDR)sg_head->sg_list[0].addr;
10760 scsiq->q1.data_cnt =
10761 (ADV_DCNT)sg_head->sg_list[0].bytes;
10762 scsiq->q1.cntl &= ~(QC_SG_HEAD | QC_SG_SWAP_QUEUE);
10764 sg_entry_cnt_minus_one = sg_entry_cnt - 1;
10766 scsi_cmd = scsiq->cdbptr[0];
10767 disable_syn_offset_one_fix = FALSE;
10768 if ((asc_dvc->pci_fix_asyn_xfer & scsiq->q1.target_id) &&
10769 !(asc_dvc->pci_fix_asyn_xfer_always & scsiq->q1.target_id)) {
10770 if (scsiq->q1.cntl & QC_SG_HEAD) {
10772 for (i = 0; i < sg_entry_cnt; i++) {
10774 (ADV_DCNT)le32_to_cpu(sg_head->sg_list[i].
10778 data_cnt = le32_to_cpu(scsiq->q1.data_cnt);
10780 if (data_cnt != 0UL) {
10781 if (data_cnt < 512UL) {
10782 disable_syn_offset_one_fix = TRUE;
10784 for (i = 0; i < ASC_SYN_OFFSET_ONE_DISABLE_LIST;
10787 _syn_offset_one_disable_cmd[i];
10788 if (disable_cmd == 0xFF) {
10791 if (scsi_cmd == disable_cmd) {
10792 disable_syn_offset_one_fix =
10800 if (disable_syn_offset_one_fix) {
10801 scsiq->q2.tag_code &= ~MSG_SIMPLE_TAG;
10802 scsiq->q2.tag_code |= (ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX |
10803 ASC_TAG_FLAG_DISABLE_DISCONNECT);
10805 scsiq->q2.tag_code &= 0x27;
10807 if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) {
10808 if (asc_dvc->bug_fix_cntl) {
10809 if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) {
10810 if ((scsi_cmd == READ_6) ||
10811 (scsi_cmd == READ_10)) {
10813 (ADV_PADDR)le32_to_cpu(sg_head->
10815 [sg_entry_cnt_minus_one].
10817 (ADV_DCNT)le32_to_cpu(sg_head->
10819 [sg_entry_cnt_minus_one].
10822 (uchar)((ushort)addr & 0x0003);
10823 if ((extra_bytes != 0)
10827 ASC_TAG_FLAG_EXTRA_BYTES)
10829 scsiq->q2.tag_code |=
10830 ASC_TAG_FLAG_EXTRA_BYTES;
10831 scsiq->q1.extra_bytes =
10834 le32_to_cpu(sg_head->
10836 [sg_entry_cnt_minus_one].
10839 (ASC_DCNT) extra_bytes;
10842 [sg_entry_cnt_minus_one].
10844 cpu_to_le32(data_cnt);
10849 sg_head->entry_to_copy = sg_head->entry_cnt;
10850 #if CC_VERY_LONG_SG_LIST
10852 * Set the sg_entry_cnt to the maximum possible. The rest of
10853 * the SG elements will be copied when the RISC completes the
10854 * SG elements that fit and halts.
10856 if (sg_entry_cnt > ASC_MAX_SG_LIST) {
10857 sg_entry_cnt = ASC_MAX_SG_LIST;
10859 #endif /* CC_VERY_LONG_SG_LIST */
10860 n_q_required = AscSgListToQueue(sg_entry_cnt);
10861 if ((AscGetNumOfFreeQueue(asc_dvc, target_ix, n_q_required) >=
10862 (uint) n_q_required)
10863 || ((scsiq->q1.cntl & QC_URGENT) != 0)) {
10865 AscSendScsiQueue(asc_dvc, scsiq,
10866 n_q_required)) == 1) {
10867 asc_dvc->in_critical_cnt--;
10872 if (asc_dvc->bug_fix_cntl) {
10873 if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) {
10874 if ((scsi_cmd == READ_6) ||
10875 (scsi_cmd == READ_10)) {
10877 le32_to_cpu(scsiq->q1.data_addr) +
10878 le32_to_cpu(scsiq->q1.data_cnt);
10880 (uchar)((ushort)addr & 0x0003);
10881 if ((extra_bytes != 0)
10885 ASC_TAG_FLAG_EXTRA_BYTES)
10888 le32_to_cpu(scsiq->q1.
10890 if (((ushort)data_cnt & 0x01FF)
10892 scsiq->q2.tag_code |=
10893 ASC_TAG_FLAG_EXTRA_BYTES;
10894 data_cnt -= (ASC_DCNT)
10896 scsiq->q1.data_cnt =
10899 scsiq->q1.extra_bytes =
10907 if ((AscGetNumOfFreeQueue(asc_dvc, target_ix, 1) >= 1) ||
10908 ((scsiq->q1.cntl & QC_URGENT) != 0)) {
10909 if ((sta = AscSendScsiQueue(asc_dvc, scsiq,
10910 n_q_required)) == 1) {
10911 asc_dvc->in_critical_cnt--;
10916 asc_dvc->in_critical_cnt--;
10921 * AdvExeScsiQueue() - Send a request to the RISC microcode program.
10923 * Allocate a carrier structure, point the carrier to the ADV_SCSI_REQ_Q,
10924 * add the carrier to the ICQ (Initiator Command Queue), and tickle the
10925 * RISC to notify it a new command is ready to be executed.
10927 * If 'done_status' is not set to QD_DO_RETRY, then 'error_retry' will be
10928 * set to SCSI_MAX_RETRY.
10930 * Multi-byte fields in the ASC_SCSI_REQ_Q that are used by the microcode
10931 * for DMA addresses or math operations are byte swapped to little-endian
10935 * ADV_SUCCESS(1) - The request was successfully queued.
10936 * ADV_BUSY(0) - Resource unavailable; Retry again after pending
10937 * request completes.
10938 * ADV_ERROR(-1) - Invalid ADV_SCSI_REQ_Q request structure
10941 static int AdvExeScsiQueue(ADV_DVC_VAR *asc_dvc, ADV_SCSI_REQ_Q *scsiq)
10943 AdvPortAddr iop_base;
10945 ADV_PADDR req_paddr;
10946 ADV_CARR_T *new_carrp;
10949 * The ADV_SCSI_REQ_Q 'target_id' field should never exceed ADV_MAX_TID.
10951 if (scsiq->target_id > ADV_MAX_TID) {
10952 scsiq->host_status = QHSTA_M_INVALID_DEVICE;
10953 scsiq->done_status = QD_WITH_ERROR;
10957 iop_base = asc_dvc->iop_base;
10960 * Allocate a carrier ensuring at least one carrier always
10961 * remains on the freelist and initialize fields.
10963 if ((new_carrp = asc_dvc->carr_freelist) == NULL) {
10966 asc_dvc->carr_freelist = (ADV_CARR_T *)
10967 ADV_U32_TO_VADDR(le32_to_cpu(new_carrp->next_vpa));
10968 asc_dvc->carr_pending_cnt++;
10971 * Set the carrier to be a stopper by setting 'next_vpa'
10972 * to the stopper value. The current stopper will be changed
10973 * below to point to the new stopper.
10975 new_carrp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
10978 * Clear the ADV_SCSI_REQ_Q done flag.
10980 scsiq->a_flag &= ~ADV_SCSIQ_DONE;
10982 req_size = sizeof(ADV_SCSI_REQ_Q);
10983 req_paddr = DvcGetPhyAddr(asc_dvc, scsiq, (uchar *)scsiq,
10984 (ADV_SDCNT *)&req_size, ADV_IS_SCSIQ_FLAG);
10986 BUG_ON(req_paddr & 31);
10987 BUG_ON(req_size < sizeof(ADV_SCSI_REQ_Q));
10989 /* Wait for assertion before making little-endian */
10990 req_paddr = cpu_to_le32(req_paddr);
10992 /* Save virtual and physical address of ADV_SCSI_REQ_Q and carrier. */
10993 scsiq->scsiq_ptr = cpu_to_le32(ADV_VADDR_TO_U32(scsiq));
10994 scsiq->scsiq_rptr = req_paddr;
10996 scsiq->carr_va = cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->icq_sp));
10998 * Every ADV_CARR_T.carr_pa is byte swapped to little-endian
10999 * order during initialization.
11001 scsiq->carr_pa = asc_dvc->icq_sp->carr_pa;
11004 * Use the current stopper to send the ADV_SCSI_REQ_Q command to
11005 * the microcode. The newly allocated stopper will become the new
11008 asc_dvc->icq_sp->areq_vpa = req_paddr;
11011 * Set the 'next_vpa' pointer for the old stopper to be the
11012 * physical address of the new stopper. The RISC can only
11013 * follow physical addresses.
11015 asc_dvc->icq_sp->next_vpa = new_carrp->carr_pa;
11018 * Set the host adapter stopper pointer to point to the new carrier.
11020 asc_dvc->icq_sp = new_carrp;
11022 if (asc_dvc->chip_type == ADV_CHIP_ASC3550 ||
11023 asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
11025 * Tickle the RISC to tell it to read its Command Queue Head pointer.
11027 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_A);
11028 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
11030 * Clear the tickle value. In the ASC-3550 the RISC flag
11031 * command 'clr_tickle_a' does not work unless the host
11032 * value is cleared.
11034 AdvWriteByteRegister(iop_base, IOPB_TICKLE,
11037 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
11039 * Notify the RISC a carrier is ready by writing the physical
11040 * address of the new carrier stopper to the COMMA register.
11042 AdvWriteDWordRegister(iop_base, IOPDW_COMMA,
11043 le32_to_cpu(new_carrp->carr_pa));
11046 return ADV_SUCCESS;
11050 * Execute a single 'Scsi_Cmnd'.
11052 * The function 'done' is called when the request has been completed.
11056 * host - board controlling device
11057 * device - device to send command
11058 * target - target of device
11059 * lun - lun of device
11060 * cmd_len - length of SCSI CDB
11061 * cmnd - buffer for SCSI 8, 10, or 12 byte CDB
11062 * use_sg - if non-zero indicates scatter-gather request with use_sg elements
11064 * if (use_sg == 0) {
11065 * request_buffer - buffer address for request
11066 * request_bufflen - length of request buffer
11068 * request_buffer - pointer to scatterlist structure
11071 * sense_buffer - sense command buffer
11073 * result (4 bytes of an int):
11075 * 0 SCSI Status Byte Code
11076 * 1 SCSI One Byte Message Code
11077 * 2 Host Error Code
11078 * 3 Mid-Level Error Code
11080 * host driver fields:
11081 * SCp - Scsi_Pointer used for command processing status
11082 * scsi_done - used to save caller's done function
11083 * host_scribble - used for pointer to another struct scsi_cmnd
11085 * If this function returns ASC_NOERROR the request will be completed
11086 * from the interrupt handler.
11088 * If this function returns ASC_ERROR the host error code has been set,
11089 * and the called must call asc_scsi_done.
11091 * If ASC_BUSY is returned the request will be returned to the midlayer
11092 * and re-tried later.
11094 static int asc_execute_scsi_cmnd(struct scsi_cmnd *scp)
11097 struct asc_board *boardp = shost_priv(scp->device->host);
11099 ASC_DBG(1, "scp 0x%p\n", scp);
11101 if (ASC_NARROW_BOARD(boardp)) {
11102 ASC_DVC_VAR *asc_dvc = &boardp->dvc_var.asc_dvc_var;
11103 struct asc_scsi_q asc_scsi_q;
11105 /* asc_build_req() can not return ASC_BUSY. */
11106 ret = asc_build_req(boardp, scp, &asc_scsi_q);
11107 if (ret == ASC_ERROR) {
11108 ASC_STATS(scp->device->host, build_error);
11112 ret = AscExeScsiQueue(asc_dvc, &asc_scsi_q);
11113 kfree(asc_scsi_q.sg_head);
11114 err_code = asc_dvc->err_code;
11116 ADV_DVC_VAR *adv_dvc = &boardp->dvc_var.adv_dvc_var;
11117 ADV_SCSI_REQ_Q *adv_scsiqp;
11119 switch (adv_build_req(boardp, scp, &adv_scsiqp)) {
11121 ASC_DBG(3, "adv_build_req ASC_NOERROR\n");
11124 ASC_DBG(1, "adv_build_req ASC_BUSY\n");
11126 * The asc_stats fields 'adv_build_noreq' and
11127 * 'adv_build_nosg' count wide board busy conditions.
11128 * They are updated in adv_build_req and
11129 * adv_get_sglist, respectively.
11134 ASC_DBG(1, "adv_build_req ASC_ERROR\n");
11135 ASC_STATS(scp->device->host, build_error);
11139 ret = AdvExeScsiQueue(adv_dvc, adv_scsiqp);
11140 err_code = adv_dvc->err_code;
11145 ASC_STATS(scp->device->host, exe_noerror);
11147 * Increment monotonically increasing per device
11148 * successful request counter. Wrapping doesn't matter.
11150 boardp->reqcnt[scp->device->id]++;
11151 ASC_DBG(1, "ExeScsiQueue() ASC_NOERROR\n");
11154 ASC_STATS(scp->device->host, exe_busy);
11157 scmd_printk(KERN_ERR, scp, "ExeScsiQueue() ASC_ERROR, "
11158 "err_code 0x%x\n", err_code);
11159 ASC_STATS(scp->device->host, exe_error);
11160 scp->result = HOST_BYTE(DID_ERROR);
11163 scmd_printk(KERN_ERR, scp, "ExeScsiQueue() unknown, "
11164 "err_code 0x%x\n", err_code);
11165 ASC_STATS(scp->device->host, exe_unknown);
11166 scp->result = HOST_BYTE(DID_ERROR);
11170 ASC_DBG(1, "end\n");
11175 * advansys_queuecommand() - interrupt-driven I/O entrypoint.
11177 * This function always returns 0. Command return status is saved
11178 * in the 'scp' result field.
11181 advansys_queuecommand(struct scsi_cmnd *scp, void (*done)(struct scsi_cmnd *))
11183 struct Scsi_Host *shost = scp->device->host;
11184 int asc_res, result = 0;
11186 ASC_STATS(shost, queuecommand);
11187 scp->scsi_done = done;
11189 asc_res = asc_execute_scsi_cmnd(scp);
11195 result = SCSI_MLQUEUE_HOST_BUSY;
11199 asc_scsi_done(scp);
11206 static ushort __devinit AscGetEisaChipCfg(PortAddr iop_base)
11208 PortAddr eisa_cfg_iop = (PortAddr) ASC_GET_EISA_SLOT(iop_base) |
11209 (PortAddr) (ASC_EISA_CFG_IOP_MASK);
11210 return inpw(eisa_cfg_iop);
11214 * Return the BIOS address of the adapter at the specified
11215 * I/O port and with the specified bus type.
11217 static unsigned short __devinit
11218 AscGetChipBiosAddress(PortAddr iop_base, unsigned short bus_type)
11220 unsigned short cfg_lsw;
11221 unsigned short bios_addr;
11224 * The PCI BIOS is re-located by the motherboard BIOS. Because
11225 * of this the driver can not determine where a PCI BIOS is
11226 * loaded and executes.
11228 if (bus_type & ASC_IS_PCI)
11231 if ((bus_type & ASC_IS_EISA) != 0) {
11232 cfg_lsw = AscGetEisaChipCfg(iop_base);
11234 bios_addr = ASC_BIOS_MIN_ADDR + cfg_lsw * ASC_BIOS_BANK_SIZE;
11238 cfg_lsw = AscGetChipCfgLsw(iop_base);
11241 * ISA PnP uses the top bit as the 32K BIOS flag
11243 if (bus_type == ASC_IS_ISAPNP)
11245 bios_addr = ASC_BIOS_MIN_ADDR + (cfg_lsw >> 12) * ASC_BIOS_BANK_SIZE;
11249 static uchar __devinit AscSetChipScsiID(PortAddr iop_base, uchar new_host_id)
11253 if (AscGetChipScsiID(iop_base) == new_host_id) {
11254 return (new_host_id);
11256 cfg_lsw = AscGetChipCfgLsw(iop_base);
11258 cfg_lsw |= (ushort)((new_host_id & ASC_MAX_TID) << 8);
11259 AscSetChipCfgLsw(iop_base, cfg_lsw);
11260 return (AscGetChipScsiID(iop_base));
11263 static unsigned char __devinit AscGetChipScsiCtrl(PortAddr iop_base)
11267 AscSetBank(iop_base, 1);
11268 sc = inp(iop_base + IOP_REG_SC);
11269 AscSetBank(iop_base, 0);
11273 static unsigned char __devinit
11274 AscGetChipVersion(PortAddr iop_base, unsigned short bus_type)
11276 if (bus_type & ASC_IS_EISA) {
11278 unsigned char revision;
11279 eisa_iop = (PortAddr) ASC_GET_EISA_SLOT(iop_base) |
11280 (PortAddr) ASC_EISA_REV_IOP_MASK;
11281 revision = inp(eisa_iop);
11282 return ASC_CHIP_MIN_VER_EISA - 1 + revision;
11284 return AscGetChipVerNo(iop_base);
11288 static void __devinit AscEnableIsaDma(uchar dma_channel)
11290 if (dma_channel < 4) {
11291 outp(0x000B, (ushort)(0xC0 | dma_channel));
11292 outp(0x000A, dma_channel);
11293 } else if (dma_channel < 8) {
11294 outp(0x00D6, (ushort)(0xC0 | (dma_channel - 4)));
11295 outp(0x00D4, (ushort)(dma_channel - 4));
11298 #endif /* CONFIG_ISA */
11300 static int AscStopQueueExe(PortAddr iop_base)
11304 if (AscReadLramByte(iop_base, ASCV_STOP_CODE_B) == 0) {
11305 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B,
11306 ASC_STOP_REQ_RISC_STOP);
11308 if (AscReadLramByte(iop_base, ASCV_STOP_CODE_B) &
11309 ASC_STOP_ACK_RISC_STOP) {
11313 } while (count++ < 20);
11318 static ASC_DCNT __devinit AscGetMaxDmaCount(ushort bus_type)
11320 if (bus_type & ASC_IS_ISA)
11321 return ASC_MAX_ISA_DMA_COUNT;
11322 else if (bus_type & (ASC_IS_EISA | ASC_IS_VL))
11323 return ASC_MAX_VL_DMA_COUNT;
11324 return ASC_MAX_PCI_DMA_COUNT;
11328 static ushort __devinit AscGetIsaDmaChannel(PortAddr iop_base)
11332 channel = AscGetChipCfgLsw(iop_base) & 0x0003;
11333 if (channel == 0x03)
11335 else if (channel == 0x00)
11337 return (channel + 4);
11340 static ushort __devinit AscSetIsaDmaChannel(PortAddr iop_base, ushort dma_channel)
11345 if ((dma_channel >= 5) && (dma_channel <= 7)) {
11346 if (dma_channel == 7)
11349 value = dma_channel - 4;
11350 cfg_lsw = AscGetChipCfgLsw(iop_base) & 0xFFFC;
11352 AscSetChipCfgLsw(iop_base, cfg_lsw);
11353 return (AscGetIsaDmaChannel(iop_base));
11358 static uchar __devinit AscGetIsaDmaSpeed(PortAddr iop_base)
11362 AscSetBank(iop_base, 1);
11363 speed_value = AscReadChipDmaSpeed(iop_base);
11364 speed_value &= 0x07;
11365 AscSetBank(iop_base, 0);
11366 return speed_value;
11369 static uchar __devinit AscSetIsaDmaSpeed(PortAddr iop_base, uchar speed_value)
11371 speed_value &= 0x07;
11372 AscSetBank(iop_base, 1);
11373 AscWriteChipDmaSpeed(iop_base, speed_value);
11374 AscSetBank(iop_base, 0);
11375 return AscGetIsaDmaSpeed(iop_base);
11377 #endif /* CONFIG_ISA */
11379 static ushort __devinit AscInitAscDvcVar(ASC_DVC_VAR *asc_dvc)
11384 uchar chip_version;
11386 iop_base = asc_dvc->iop_base;
11388 asc_dvc->err_code = 0;
11389 if ((asc_dvc->bus_type &
11390 (ASC_IS_ISA | ASC_IS_PCI | ASC_IS_EISA | ASC_IS_VL)) == 0) {
11391 asc_dvc->err_code |= ASC_IERR_NO_BUS_TYPE;
11393 AscSetChipControl(iop_base, CC_HALT);
11394 AscSetChipStatus(iop_base, 0);
11395 asc_dvc->bug_fix_cntl = 0;
11396 asc_dvc->pci_fix_asyn_xfer = 0;
11397 asc_dvc->pci_fix_asyn_xfer_always = 0;
11398 /* asc_dvc->init_state initalized in AscInitGetConfig(). */
11399 asc_dvc->sdtr_done = 0;
11400 asc_dvc->cur_total_qng = 0;
11401 asc_dvc->is_in_int = 0;
11402 asc_dvc->in_critical_cnt = 0;
11403 asc_dvc->last_q_shortage = 0;
11404 asc_dvc->use_tagged_qng = 0;
11405 asc_dvc->no_scam = 0;
11406 asc_dvc->unit_not_ready = 0;
11407 asc_dvc->queue_full_or_busy = 0;
11408 asc_dvc->redo_scam = 0;
11410 asc_dvc->host_init_sdtr_index = 0;
11411 asc_dvc->cfg->can_tagged_qng = 0;
11412 asc_dvc->cfg->cmd_qng_enabled = 0;
11413 asc_dvc->dvc_cntl = ASC_DEF_DVC_CNTL;
11414 asc_dvc->init_sdtr = 0;
11415 asc_dvc->max_total_qng = ASC_DEF_MAX_TOTAL_QNG;
11416 asc_dvc->scsi_reset_wait = 3;
11417 asc_dvc->start_motor = ASC_SCSI_WIDTH_BIT_SET;
11418 asc_dvc->max_dma_count = AscGetMaxDmaCount(asc_dvc->bus_type);
11419 asc_dvc->cfg->sdtr_enable = ASC_SCSI_WIDTH_BIT_SET;
11420 asc_dvc->cfg->disc_enable = ASC_SCSI_WIDTH_BIT_SET;
11421 asc_dvc->cfg->chip_scsi_id = ASC_DEF_CHIP_SCSI_ID;
11422 chip_version = AscGetChipVersion(iop_base, asc_dvc->bus_type);
11423 asc_dvc->cfg->chip_version = chip_version;
11424 asc_dvc->sdtr_period_tbl[0] = SYN_XFER_NS_0;
11425 asc_dvc->sdtr_period_tbl[1] = SYN_XFER_NS_1;
11426 asc_dvc->sdtr_period_tbl[2] = SYN_XFER_NS_2;
11427 asc_dvc->sdtr_period_tbl[3] = SYN_XFER_NS_3;
11428 asc_dvc->sdtr_period_tbl[4] = SYN_XFER_NS_4;
11429 asc_dvc->sdtr_period_tbl[5] = SYN_XFER_NS_5;
11430 asc_dvc->sdtr_period_tbl[6] = SYN_XFER_NS_6;
11431 asc_dvc->sdtr_period_tbl[7] = SYN_XFER_NS_7;
11432 asc_dvc->max_sdtr_index = 7;
11433 if ((asc_dvc->bus_type & ASC_IS_PCI) &&
11434 (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3150)) {
11435 asc_dvc->bus_type = ASC_IS_PCI_ULTRA;
11436 asc_dvc->sdtr_period_tbl[0] = SYN_ULTRA_XFER_NS_0;
11437 asc_dvc->sdtr_period_tbl[1] = SYN_ULTRA_XFER_NS_1;
11438 asc_dvc->sdtr_period_tbl[2] = SYN_ULTRA_XFER_NS_2;
11439 asc_dvc->sdtr_period_tbl[3] = SYN_ULTRA_XFER_NS_3;
11440 asc_dvc->sdtr_period_tbl[4] = SYN_ULTRA_XFER_NS_4;
11441 asc_dvc->sdtr_period_tbl[5] = SYN_ULTRA_XFER_NS_5;
11442 asc_dvc->sdtr_period_tbl[6] = SYN_ULTRA_XFER_NS_6;
11443 asc_dvc->sdtr_period_tbl[7] = SYN_ULTRA_XFER_NS_7;
11444 asc_dvc->sdtr_period_tbl[8] = SYN_ULTRA_XFER_NS_8;
11445 asc_dvc->sdtr_period_tbl[9] = SYN_ULTRA_XFER_NS_9;
11446 asc_dvc->sdtr_period_tbl[10] = SYN_ULTRA_XFER_NS_10;
11447 asc_dvc->sdtr_period_tbl[11] = SYN_ULTRA_XFER_NS_11;
11448 asc_dvc->sdtr_period_tbl[12] = SYN_ULTRA_XFER_NS_12;
11449 asc_dvc->sdtr_period_tbl[13] = SYN_ULTRA_XFER_NS_13;
11450 asc_dvc->sdtr_period_tbl[14] = SYN_ULTRA_XFER_NS_14;
11451 asc_dvc->sdtr_period_tbl[15] = SYN_ULTRA_XFER_NS_15;
11452 asc_dvc->max_sdtr_index = 15;
11453 if (chip_version == ASC_CHIP_VER_PCI_ULTRA_3150) {
11454 AscSetExtraControl(iop_base,
11455 (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE));
11456 } else if (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3050) {
11457 AscSetExtraControl(iop_base,
11458 (SEC_ACTIVE_NEGATE |
11459 SEC_ENABLE_FILTER));
11462 if (asc_dvc->bus_type == ASC_IS_PCI) {
11463 AscSetExtraControl(iop_base,
11464 (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE));
11467 asc_dvc->cfg->isa_dma_speed = ASC_DEF_ISA_DMA_SPEED;
11469 if ((asc_dvc->bus_type & ASC_IS_ISA) != 0) {
11470 if (chip_version >= ASC_CHIP_MIN_VER_ISA_PNP) {
11471 AscSetChipIFC(iop_base, IFC_INIT_DEFAULT);
11472 asc_dvc->bus_type = ASC_IS_ISAPNP;
11474 asc_dvc->cfg->isa_dma_channel =
11475 (uchar)AscGetIsaDmaChannel(iop_base);
11477 #endif /* CONFIG_ISA */
11478 for (i = 0; i <= ASC_MAX_TID; i++) {
11479 asc_dvc->cur_dvc_qng[i] = 0;
11480 asc_dvc->max_dvc_qng[i] = ASC_MAX_SCSI1_QNG;
11481 asc_dvc->scsiq_busy_head[i] = (ASC_SCSI_Q *)0L;
11482 asc_dvc->scsiq_busy_tail[i] = (ASC_SCSI_Q *)0L;
11483 asc_dvc->cfg->max_tag_qng[i] = ASC_MAX_INRAM_TAG_QNG;
11488 static int __devinit AscWriteEEPCmdReg(PortAddr iop_base, uchar cmd_reg)
11492 for (retry = 0; retry < ASC_EEP_MAX_RETRY; retry++) {
11493 unsigned char read_back;
11494 AscSetChipEEPCmd(iop_base, cmd_reg);
11496 read_back = AscGetChipEEPCmd(iop_base);
11497 if (read_back == cmd_reg)
11503 static void __devinit AscWaitEEPRead(void)
11508 static ushort __devinit AscReadEEPWord(PortAddr iop_base, uchar addr)
11513 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_DISABLE);
11515 cmd_reg = addr | ASC_EEP_CMD_READ;
11516 AscWriteEEPCmdReg(iop_base, cmd_reg);
11518 read_wval = AscGetChipEEPData(iop_base);
11523 static ushort __devinit
11524 AscGetEEPConfig(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf, ushort bus_type)
11531 int uchar_end_in_config = ASC_EEP_MAX_DVC_ADDR - 2;
11534 wbuf = (ushort *)cfg_buf;
11536 /* Read two config words; Byte-swapping done by AscReadEEPWord(). */
11537 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
11538 *wbuf = AscReadEEPWord(iop_base, (uchar)s_addr);
11541 if (bus_type & ASC_IS_VL) {
11542 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
11543 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
11545 cfg_beg = ASC_EEP_DVC_CFG_BEG;
11546 cfg_end = ASC_EEP_MAX_DVC_ADDR;
11548 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
11549 wval = AscReadEEPWord(iop_base, (uchar)s_addr);
11550 if (s_addr <= uchar_end_in_config) {
11552 * Swap all char fields - must unswap bytes already swapped
11553 * by AscReadEEPWord().
11555 *wbuf = le16_to_cpu(wval);
11557 /* Don't swap word field at the end - cntl field. */
11560 sum += wval; /* Checksum treats all EEPROM data as words. */
11563 * Read the checksum word which will be compared against 'sum'
11564 * by the caller. Word field already swapped.
11566 *wbuf = AscReadEEPWord(iop_base, (uchar)s_addr);
11570 static int __devinit AscTestExternalLram(ASC_DVC_VAR *asc_dvc)
11577 iop_base = asc_dvc->iop_base;
11579 q_addr = ASC_QNO_TO_QADDR(241);
11580 saved_word = AscReadLramWord(iop_base, q_addr);
11581 AscSetChipLramAddr(iop_base, q_addr);
11582 AscSetChipLramData(iop_base, 0x55AA);
11584 AscSetChipLramAddr(iop_base, q_addr);
11585 if (AscGetChipLramData(iop_base) == 0x55AA) {
11587 AscWriteLramWord(iop_base, q_addr, saved_word);
11592 static void __devinit AscWaitEEPWrite(void)
11597 static int __devinit AscWriteEEPDataReg(PortAddr iop_base, ushort data_reg)
11604 AscSetChipEEPData(iop_base, data_reg);
11606 read_back = AscGetChipEEPData(iop_base);
11607 if (read_back == data_reg) {
11610 if (retry++ > ASC_EEP_MAX_RETRY) {
11616 static ushort __devinit
11617 AscWriteEEPWord(PortAddr iop_base, uchar addr, ushort word_val)
11621 read_wval = AscReadEEPWord(iop_base, addr);
11622 if (read_wval != word_val) {
11623 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_ABLE);
11625 AscWriteEEPDataReg(iop_base, word_val);
11627 AscWriteEEPCmdReg(iop_base,
11628 (uchar)((uchar)ASC_EEP_CMD_WRITE | addr));
11630 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_DISABLE);
11632 return (AscReadEEPWord(iop_base, addr));
11634 return (read_wval);
11637 static int __devinit
11638 AscSetEEPConfigOnce(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf, ushort bus_type)
11647 int uchar_end_in_config = ASC_EEP_MAX_DVC_ADDR - 2;
11649 wbuf = (ushort *)cfg_buf;
11652 /* Write two config words; AscWriteEEPWord() will swap bytes. */
11653 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
11655 if (*wbuf != AscWriteEEPWord(iop_base, (uchar)s_addr, *wbuf)) {
11659 if (bus_type & ASC_IS_VL) {
11660 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
11661 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
11663 cfg_beg = ASC_EEP_DVC_CFG_BEG;
11664 cfg_end = ASC_EEP_MAX_DVC_ADDR;
11666 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
11667 if (s_addr <= uchar_end_in_config) {
11669 * This is a char field. Swap char fields before they are
11670 * swapped again by AscWriteEEPWord().
11672 word = cpu_to_le16(*wbuf);
11674 AscWriteEEPWord(iop_base, (uchar)s_addr, word)) {
11678 /* Don't swap word field at the end - cntl field. */
11680 AscWriteEEPWord(iop_base, (uchar)s_addr, *wbuf)) {
11684 sum += *wbuf; /* Checksum calculated from word values. */
11686 /* Write checksum word. It will be swapped by AscWriteEEPWord(). */
11688 if (sum != AscWriteEEPWord(iop_base, (uchar)s_addr, sum)) {
11692 /* Read EEPROM back again. */
11693 wbuf = (ushort *)cfg_buf;
11695 * Read two config words; Byte-swapping done by AscReadEEPWord().
11697 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
11698 if (*wbuf != AscReadEEPWord(iop_base, (uchar)s_addr)) {
11702 if (bus_type & ASC_IS_VL) {
11703 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
11704 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
11706 cfg_beg = ASC_EEP_DVC_CFG_BEG;
11707 cfg_end = ASC_EEP_MAX_DVC_ADDR;
11709 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
11710 if (s_addr <= uchar_end_in_config) {
11712 * Swap all char fields. Must unswap bytes already swapped
11713 * by AscReadEEPWord().
11716 le16_to_cpu(AscReadEEPWord
11717 (iop_base, (uchar)s_addr));
11719 /* Don't swap word field at the end - cntl field. */
11720 word = AscReadEEPWord(iop_base, (uchar)s_addr);
11722 if (*wbuf != word) {
11726 /* Read checksum; Byte swapping not needed. */
11727 if (AscReadEEPWord(iop_base, (uchar)s_addr) != sum) {
11733 static int __devinit
11734 AscSetEEPConfig(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf, ushort bus_type)
11741 if ((n_error = AscSetEEPConfigOnce(iop_base, cfg_buf,
11745 if (++retry > ASC_EEP_MAX_RETRY) {
11752 static ushort __devinit AscInitFromEEP(ASC_DVC_VAR *asc_dvc)
11754 ASCEEP_CONFIG eep_config_buf;
11755 ASCEEP_CONFIG *eep_config;
11759 ushort cfg_msw, cfg_lsw;
11763 iop_base = asc_dvc->iop_base;
11765 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0x00FE);
11766 AscStopQueueExe(iop_base);
11767 if ((AscStopChip(iop_base) == FALSE) ||
11768 (AscGetChipScsiCtrl(iop_base) != 0)) {
11769 asc_dvc->init_state |= ASC_INIT_RESET_SCSI_DONE;
11770 AscResetChipAndScsiBus(asc_dvc);
11771 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
11773 if (AscIsChipHalted(iop_base) == FALSE) {
11774 asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP;
11775 return (warn_code);
11777 AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR);
11778 if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) {
11779 asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR;
11780 return (warn_code);
11782 eep_config = (ASCEEP_CONFIG *)&eep_config_buf;
11783 cfg_msw = AscGetChipCfgMsw(iop_base);
11784 cfg_lsw = AscGetChipCfgLsw(iop_base);
11785 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) {
11786 cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
11787 warn_code |= ASC_WARN_CFG_MSW_RECOVER;
11788 AscSetChipCfgMsw(iop_base, cfg_msw);
11790 chksum = AscGetEEPConfig(iop_base, eep_config, asc_dvc->bus_type);
11791 ASC_DBG(1, "chksum 0x%x\n", chksum);
11795 if (AscGetChipStatus(iop_base) & CSW_AUTO_CONFIG) {
11796 warn_code |= ASC_WARN_AUTO_CONFIG;
11797 if (asc_dvc->cfg->chip_version == 3) {
11798 if (eep_config->cfg_lsw != cfg_lsw) {
11799 warn_code |= ASC_WARN_EEPROM_RECOVER;
11800 eep_config->cfg_lsw =
11801 AscGetChipCfgLsw(iop_base);
11803 if (eep_config->cfg_msw != cfg_msw) {
11804 warn_code |= ASC_WARN_EEPROM_RECOVER;
11805 eep_config->cfg_msw =
11806 AscGetChipCfgMsw(iop_base);
11810 eep_config->cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
11811 eep_config->cfg_lsw |= ASC_CFG0_HOST_INT_ON;
11812 ASC_DBG(1, "eep_config->chksum 0x%x\n", eep_config->chksum);
11813 if (chksum != eep_config->chksum) {
11814 if (AscGetChipVersion(iop_base, asc_dvc->bus_type) ==
11815 ASC_CHIP_VER_PCI_ULTRA_3050) {
11816 ASC_DBG(1, "chksum error ignored; EEPROM-less board\n");
11817 eep_config->init_sdtr = 0xFF;
11818 eep_config->disc_enable = 0xFF;
11819 eep_config->start_motor = 0xFF;
11820 eep_config->use_cmd_qng = 0;
11821 eep_config->max_total_qng = 0xF0;
11822 eep_config->max_tag_qng = 0x20;
11823 eep_config->cntl = 0xBFFF;
11824 ASC_EEP_SET_CHIP_ID(eep_config, 7);
11825 eep_config->no_scam = 0;
11826 eep_config->adapter_info[0] = 0;
11827 eep_config->adapter_info[1] = 0;
11828 eep_config->adapter_info[2] = 0;
11829 eep_config->adapter_info[3] = 0;
11830 eep_config->adapter_info[4] = 0;
11831 /* Indicate EEPROM-less board. */
11832 eep_config->adapter_info[5] = 0xBB;
11835 ("AscInitFromEEP: EEPROM checksum error; Will try to re-write EEPROM.\n");
11837 warn_code |= ASC_WARN_EEPROM_CHKSUM;
11840 asc_dvc->cfg->sdtr_enable = eep_config->init_sdtr;
11841 asc_dvc->cfg->disc_enable = eep_config->disc_enable;
11842 asc_dvc->cfg->cmd_qng_enabled = eep_config->use_cmd_qng;
11843 asc_dvc->cfg->isa_dma_speed = ASC_EEP_GET_DMA_SPD(eep_config);
11844 asc_dvc->start_motor = eep_config->start_motor;
11845 asc_dvc->dvc_cntl = eep_config->cntl;
11846 asc_dvc->no_scam = eep_config->no_scam;
11847 asc_dvc->cfg->adapter_info[0] = eep_config->adapter_info[0];
11848 asc_dvc->cfg->adapter_info[1] = eep_config->adapter_info[1];
11849 asc_dvc->cfg->adapter_info[2] = eep_config->adapter_info[2];
11850 asc_dvc->cfg->adapter_info[3] = eep_config->adapter_info[3];
11851 asc_dvc->cfg->adapter_info[4] = eep_config->adapter_info[4];
11852 asc_dvc->cfg->adapter_info[5] = eep_config->adapter_info[5];
11853 if (!AscTestExternalLram(asc_dvc)) {
11854 if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) ==
11855 ASC_IS_PCI_ULTRA)) {
11856 eep_config->max_total_qng =
11857 ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG;
11858 eep_config->max_tag_qng =
11859 ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG;
11861 eep_config->cfg_msw |= 0x0800;
11863 AscSetChipCfgMsw(iop_base, cfg_msw);
11864 eep_config->max_total_qng = ASC_MAX_PCI_INRAM_TOTAL_QNG;
11865 eep_config->max_tag_qng = ASC_MAX_INRAM_TAG_QNG;
11869 if (eep_config->max_total_qng < ASC_MIN_TOTAL_QNG) {
11870 eep_config->max_total_qng = ASC_MIN_TOTAL_QNG;
11872 if (eep_config->max_total_qng > ASC_MAX_TOTAL_QNG) {
11873 eep_config->max_total_qng = ASC_MAX_TOTAL_QNG;
11875 if (eep_config->max_tag_qng > eep_config->max_total_qng) {
11876 eep_config->max_tag_qng = eep_config->max_total_qng;
11878 if (eep_config->max_tag_qng < ASC_MIN_TAG_Q_PER_DVC) {
11879 eep_config->max_tag_qng = ASC_MIN_TAG_Q_PER_DVC;
11881 asc_dvc->max_total_qng = eep_config->max_total_qng;
11882 if ((eep_config->use_cmd_qng & eep_config->disc_enable) !=
11883 eep_config->use_cmd_qng) {
11884 eep_config->disc_enable = eep_config->use_cmd_qng;
11885 warn_code |= ASC_WARN_CMD_QNG_CONFLICT;
11887 ASC_EEP_SET_CHIP_ID(eep_config,
11888 ASC_EEP_GET_CHIP_ID(eep_config) & ASC_MAX_TID);
11889 asc_dvc->cfg->chip_scsi_id = ASC_EEP_GET_CHIP_ID(eep_config);
11890 if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) &&
11891 !(asc_dvc->dvc_cntl & ASC_CNTL_SDTR_ENABLE_ULTRA)) {
11892 asc_dvc->host_init_sdtr_index = ASC_SDTR_ULTRA_PCI_10MB_INDEX;
11895 for (i = 0; i <= ASC_MAX_TID; i++) {
11896 asc_dvc->dos_int13_table[i] = eep_config->dos_int13_table[i];
11897 asc_dvc->cfg->max_tag_qng[i] = eep_config->max_tag_qng;
11898 asc_dvc->cfg->sdtr_period_offset[i] =
11899 (uchar)(ASC_DEF_SDTR_OFFSET |
11900 (asc_dvc->host_init_sdtr_index << 4));
11902 eep_config->cfg_msw = AscGetChipCfgMsw(iop_base);
11904 if ((i = AscSetEEPConfig(iop_base, eep_config,
11905 asc_dvc->bus_type)) != 0) {
11907 ("AscInitFromEEP: Failed to re-write EEPROM with %d errors.\n",
11911 ("AscInitFromEEP: Successfully re-wrote EEPROM.\n");
11914 return (warn_code);
11917 static int __devinit AscInitGetConfig(struct Scsi_Host *shost)
11919 struct asc_board *board = shost_priv(shost);
11920 ASC_DVC_VAR *asc_dvc = &board->dvc_var.asc_dvc_var;
11921 unsigned short warn_code = 0;
11923 asc_dvc->init_state = ASC_INIT_STATE_BEG_GET_CFG;
11924 if (asc_dvc->err_code != 0)
11925 return asc_dvc->err_code;
11927 if (AscFindSignature(asc_dvc->iop_base)) {
11928 warn_code |= AscInitAscDvcVar(asc_dvc);
11929 warn_code |= AscInitFromEEP(asc_dvc);
11930 asc_dvc->init_state |= ASC_INIT_STATE_END_GET_CFG;
11931 if (asc_dvc->scsi_reset_wait > ASC_MAX_SCSI_RESET_WAIT)
11932 asc_dvc->scsi_reset_wait = ASC_MAX_SCSI_RESET_WAIT;
11934 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
11937 switch (warn_code) {
11938 case 0: /* No error */
11940 case ASC_WARN_IO_PORT_ROTATE:
11941 shost_printk(KERN_WARNING, shost, "I/O port address "
11944 case ASC_WARN_AUTO_CONFIG:
11945 shost_printk(KERN_WARNING, shost, "I/O port increment switch "
11948 case ASC_WARN_EEPROM_CHKSUM:
11949 shost_printk(KERN_WARNING, shost, "EEPROM checksum error\n");
11951 case ASC_WARN_IRQ_MODIFIED:
11952 shost_printk(KERN_WARNING, shost, "IRQ modified\n");
11954 case ASC_WARN_CMD_QNG_CONFLICT:
11955 shost_printk(KERN_WARNING, shost, "tag queuing enabled w/o "
11959 shost_printk(KERN_WARNING, shost, "unknown warning: 0x%x\n",
11964 if (asc_dvc->err_code != 0)
11965 shost_printk(KERN_ERR, shost, "error 0x%x at init_state "
11966 "0x%x\n", asc_dvc->err_code, asc_dvc->init_state);
11968 return asc_dvc->err_code;
11971 static int __devinit AscInitSetConfig(struct pci_dev *pdev, struct Scsi_Host *shost)
11973 struct asc_board *board = shost_priv(shost);
11974 ASC_DVC_VAR *asc_dvc = &board->dvc_var.asc_dvc_var;
11975 PortAddr iop_base = asc_dvc->iop_base;
11976 unsigned short cfg_msw;
11977 unsigned short warn_code = 0;
11979 asc_dvc->init_state |= ASC_INIT_STATE_BEG_SET_CFG;
11980 if (asc_dvc->err_code != 0)
11981 return asc_dvc->err_code;
11982 if (!AscFindSignature(asc_dvc->iop_base)) {
11983 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
11984 return asc_dvc->err_code;
11987 cfg_msw = AscGetChipCfgMsw(iop_base);
11988 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) {
11989 cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
11990 warn_code |= ASC_WARN_CFG_MSW_RECOVER;
11991 AscSetChipCfgMsw(iop_base, cfg_msw);
11993 if ((asc_dvc->cfg->cmd_qng_enabled & asc_dvc->cfg->disc_enable) !=
11994 asc_dvc->cfg->cmd_qng_enabled) {
11995 asc_dvc->cfg->disc_enable = asc_dvc->cfg->cmd_qng_enabled;
11996 warn_code |= ASC_WARN_CMD_QNG_CONFLICT;
11998 if (AscGetChipStatus(iop_base) & CSW_AUTO_CONFIG) {
11999 warn_code |= ASC_WARN_AUTO_CONFIG;
12002 if (asc_dvc->bus_type & ASC_IS_PCI) {
12004 AscSetChipCfgMsw(iop_base, cfg_msw);
12005 if ((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) {
12007 if ((pdev->device == PCI_DEVICE_ID_ASP_1200A) ||
12008 (pdev->device == PCI_DEVICE_ID_ASP_ABP940)) {
12009 asc_dvc->bug_fix_cntl |= ASC_BUG_FIX_IF_NOT_DWB;
12010 asc_dvc->bug_fix_cntl |=
12011 ASC_BUG_FIX_ASYN_USE_SYN;
12015 #endif /* CONFIG_PCI */
12016 if (asc_dvc->bus_type == ASC_IS_ISAPNP) {
12017 if (AscGetChipVersion(iop_base, asc_dvc->bus_type)
12018 == ASC_CHIP_VER_ASYN_BUG) {
12019 asc_dvc->bug_fix_cntl |= ASC_BUG_FIX_ASYN_USE_SYN;
12022 if (AscSetChipScsiID(iop_base, asc_dvc->cfg->chip_scsi_id) !=
12023 asc_dvc->cfg->chip_scsi_id) {
12024 asc_dvc->err_code |= ASC_IERR_SET_SCSI_ID;
12027 if (asc_dvc->bus_type & ASC_IS_ISA) {
12028 AscSetIsaDmaChannel(iop_base, asc_dvc->cfg->isa_dma_channel);
12029 AscSetIsaDmaSpeed(iop_base, asc_dvc->cfg->isa_dma_speed);
12031 #endif /* CONFIG_ISA */
12033 asc_dvc->init_state |= ASC_INIT_STATE_END_SET_CFG;
12035 switch (warn_code) {
12036 case 0: /* No error. */
12038 case ASC_WARN_IO_PORT_ROTATE:
12039 shost_printk(KERN_WARNING, shost, "I/O port address "
12042 case ASC_WARN_AUTO_CONFIG:
12043 shost_printk(KERN_WARNING, shost, "I/O port increment switch "
12046 case ASC_WARN_EEPROM_CHKSUM:
12047 shost_printk(KERN_WARNING, shost, "EEPROM checksum error\n");
12049 case ASC_WARN_IRQ_MODIFIED:
12050 shost_printk(KERN_WARNING, shost, "IRQ modified\n");
12052 case ASC_WARN_CMD_QNG_CONFLICT:
12053 shost_printk(KERN_WARNING, shost, "tag queuing w/o "
12057 shost_printk(KERN_WARNING, shost, "unknown warning: 0x%x\n",
12062 if (asc_dvc->err_code != 0)
12063 shost_printk(KERN_ERR, shost, "error 0x%x at init_state "
12064 "0x%x\n", asc_dvc->err_code, asc_dvc->init_state);
12066 return asc_dvc->err_code;
12070 * EEPROM Configuration.
12072 * All drivers should use this structure to set the default EEPROM
12073 * configuration. The BIOS now uses this structure when it is built.
12074 * Additional structure information can be found in a_condor.h where
12075 * the structure is defined.
12077 * The *_Field_IsChar structs are needed to correct for endianness.
12078 * These values are read from the board 16 bits at a time directly
12079 * into the structs. Because some fields are char, the values will be
12080 * in the wrong order. The *_Field_IsChar tells when to flip the
12081 * bytes. Data read and written to PCI memory is automatically swapped
12082 * on big-endian platforms so char fields read as words are actually being
12083 * unswapped on big-endian platforms.
12085 static ADVEEP_3550_CONFIG Default_3550_EEPROM_Config __devinitdata = {
12086 ADV_EEPROM_BIOS_ENABLE, /* cfg_lsw */
12087 0x0000, /* cfg_msw */
12088 0xFFFF, /* disc_enable */
12089 0xFFFF, /* wdtr_able */
12090 0xFFFF, /* sdtr_able */
12091 0xFFFF, /* start_motor */
12092 0xFFFF, /* tagqng_able */
12093 0xFFFF, /* bios_scan */
12094 0, /* scam_tolerant */
12095 7, /* adapter_scsi_id */
12096 0, /* bios_boot_delay */
12097 3, /* scsi_reset_delay */
12098 0, /* bios_id_lun */
12099 0, /* termination */
12101 0xFFE7, /* bios_ctrl */
12102 0xFFFF, /* ultra_able */
12104 ASC_DEF_MAX_HOST_QNG, /* max_host_qng */
12105 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
12108 0, /* serial_number_word1 */
12109 0, /* serial_number_word2 */
12110 0, /* serial_number_word3 */
12112 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
12113 , /* oem_name[16] */
12114 0, /* dvc_err_code */
12115 0, /* adv_err_code */
12116 0, /* adv_err_addr */
12117 0, /* saved_dvc_err_code */
12118 0, /* saved_adv_err_code */
12119 0, /* saved_adv_err_addr */
12123 static ADVEEP_3550_CONFIG ADVEEP_3550_Config_Field_IsChar __devinitdata = {
12126 0, /* -disc_enable */
12129 0, /* start_motor */
12130 0, /* tagqng_able */
12132 0, /* scam_tolerant */
12133 1, /* adapter_scsi_id */
12134 1, /* bios_boot_delay */
12135 1, /* scsi_reset_delay */
12136 1, /* bios_id_lun */
12137 1, /* termination */
12140 0, /* ultra_able */
12142 1, /* max_host_qng */
12143 1, /* max_dvc_qng */
12146 0, /* serial_number_word1 */
12147 0, /* serial_number_word2 */
12148 0, /* serial_number_word3 */
12150 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
12151 , /* oem_name[16] */
12152 0, /* dvc_err_code */
12153 0, /* adv_err_code */
12154 0, /* adv_err_addr */
12155 0, /* saved_dvc_err_code */
12156 0, /* saved_adv_err_code */
12157 0, /* saved_adv_err_addr */
12161 static ADVEEP_38C0800_CONFIG Default_38C0800_EEPROM_Config __devinitdata = {
12162 ADV_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
12163 0x0000, /* 01 cfg_msw */
12164 0xFFFF, /* 02 disc_enable */
12165 0xFFFF, /* 03 wdtr_able */
12166 0x4444, /* 04 sdtr_speed1 */
12167 0xFFFF, /* 05 start_motor */
12168 0xFFFF, /* 06 tagqng_able */
12169 0xFFFF, /* 07 bios_scan */
12170 0, /* 08 scam_tolerant */
12171 7, /* 09 adapter_scsi_id */
12172 0, /* bios_boot_delay */
12173 3, /* 10 scsi_reset_delay */
12174 0, /* bios_id_lun */
12175 0, /* 11 termination_se */
12176 0, /* termination_lvd */
12177 0xFFE7, /* 12 bios_ctrl */
12178 0x4444, /* 13 sdtr_speed2 */
12179 0x4444, /* 14 sdtr_speed3 */
12180 ASC_DEF_MAX_HOST_QNG, /* 15 max_host_qng */
12181 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
12182 0, /* 16 dvc_cntl */
12183 0x4444, /* 17 sdtr_speed4 */
12184 0, /* 18 serial_number_word1 */
12185 0, /* 19 serial_number_word2 */
12186 0, /* 20 serial_number_word3 */
12187 0, /* 21 check_sum */
12188 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
12189 , /* 22-29 oem_name[16] */
12190 0, /* 30 dvc_err_code */
12191 0, /* 31 adv_err_code */
12192 0, /* 32 adv_err_addr */
12193 0, /* 33 saved_dvc_err_code */
12194 0, /* 34 saved_adv_err_code */
12195 0, /* 35 saved_adv_err_addr */
12196 0, /* 36 reserved */
12197 0, /* 37 reserved */
12198 0, /* 38 reserved */
12199 0, /* 39 reserved */
12200 0, /* 40 reserved */
12201 0, /* 41 reserved */
12202 0, /* 42 reserved */
12203 0, /* 43 reserved */
12204 0, /* 44 reserved */
12205 0, /* 45 reserved */
12206 0, /* 46 reserved */
12207 0, /* 47 reserved */
12208 0, /* 48 reserved */
12209 0, /* 49 reserved */
12210 0, /* 50 reserved */
12211 0, /* 51 reserved */
12212 0, /* 52 reserved */
12213 0, /* 53 reserved */
12214 0, /* 54 reserved */
12215 0, /* 55 reserved */
12216 0, /* 56 cisptr_lsw */
12217 0, /* 57 cisprt_msw */
12218 PCI_VENDOR_ID_ASP, /* 58 subsysvid */
12219 PCI_DEVICE_ID_38C0800_REV1, /* 59 subsysid */
12220 0, /* 60 reserved */
12221 0, /* 61 reserved */
12222 0, /* 62 reserved */
12223 0 /* 63 reserved */
12226 static ADVEEP_38C0800_CONFIG ADVEEP_38C0800_Config_Field_IsChar __devinitdata = {
12227 0, /* 00 cfg_lsw */
12228 0, /* 01 cfg_msw */
12229 0, /* 02 disc_enable */
12230 0, /* 03 wdtr_able */
12231 0, /* 04 sdtr_speed1 */
12232 0, /* 05 start_motor */
12233 0, /* 06 tagqng_able */
12234 0, /* 07 bios_scan */
12235 0, /* 08 scam_tolerant */
12236 1, /* 09 adapter_scsi_id */
12237 1, /* bios_boot_delay */
12238 1, /* 10 scsi_reset_delay */
12239 1, /* bios_id_lun */
12240 1, /* 11 termination_se */
12241 1, /* termination_lvd */
12242 0, /* 12 bios_ctrl */
12243 0, /* 13 sdtr_speed2 */
12244 0, /* 14 sdtr_speed3 */
12245 1, /* 15 max_host_qng */
12246 1, /* max_dvc_qng */
12247 0, /* 16 dvc_cntl */
12248 0, /* 17 sdtr_speed4 */
12249 0, /* 18 serial_number_word1 */
12250 0, /* 19 serial_number_word2 */
12251 0, /* 20 serial_number_word3 */
12252 0, /* 21 check_sum */
12253 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
12254 , /* 22-29 oem_name[16] */
12255 0, /* 30 dvc_err_code */
12256 0, /* 31 adv_err_code */
12257 0, /* 32 adv_err_addr */
12258 0, /* 33 saved_dvc_err_code */
12259 0, /* 34 saved_adv_err_code */
12260 0, /* 35 saved_adv_err_addr */
12261 0, /* 36 reserved */
12262 0, /* 37 reserved */
12263 0, /* 38 reserved */
12264 0, /* 39 reserved */
12265 0, /* 40 reserved */
12266 0, /* 41 reserved */
12267 0, /* 42 reserved */
12268 0, /* 43 reserved */
12269 0, /* 44 reserved */
12270 0, /* 45 reserved */
12271 0, /* 46 reserved */
12272 0, /* 47 reserved */
12273 0, /* 48 reserved */
12274 0, /* 49 reserved */
12275 0, /* 50 reserved */
12276 0, /* 51 reserved */
12277 0, /* 52 reserved */
12278 0, /* 53 reserved */
12279 0, /* 54 reserved */
12280 0, /* 55 reserved */
12281 0, /* 56 cisptr_lsw */
12282 0, /* 57 cisprt_msw */
12283 0, /* 58 subsysvid */
12284 0, /* 59 subsysid */
12285 0, /* 60 reserved */
12286 0, /* 61 reserved */
12287 0, /* 62 reserved */
12288 0 /* 63 reserved */
12291 static ADVEEP_38C1600_CONFIG Default_38C1600_EEPROM_Config __devinitdata = {
12292 ADV_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
12293 0x0000, /* 01 cfg_msw */
12294 0xFFFF, /* 02 disc_enable */
12295 0xFFFF, /* 03 wdtr_able */
12296 0x5555, /* 04 sdtr_speed1 */
12297 0xFFFF, /* 05 start_motor */
12298 0xFFFF, /* 06 tagqng_able */
12299 0xFFFF, /* 07 bios_scan */
12300 0, /* 08 scam_tolerant */
12301 7, /* 09 adapter_scsi_id */
12302 0, /* bios_boot_delay */
12303 3, /* 10 scsi_reset_delay */
12304 0, /* bios_id_lun */
12305 0, /* 11 termination_se */
12306 0, /* termination_lvd */
12307 0xFFE7, /* 12 bios_ctrl */
12308 0x5555, /* 13 sdtr_speed2 */
12309 0x5555, /* 14 sdtr_speed3 */
12310 ASC_DEF_MAX_HOST_QNG, /* 15 max_host_qng */
12311 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
12312 0, /* 16 dvc_cntl */
12313 0x5555, /* 17 sdtr_speed4 */
12314 0, /* 18 serial_number_word1 */
12315 0, /* 19 serial_number_word2 */
12316 0, /* 20 serial_number_word3 */
12317 0, /* 21 check_sum */
12318 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
12319 , /* 22-29 oem_name[16] */
12320 0, /* 30 dvc_err_code */
12321 0, /* 31 adv_err_code */
12322 0, /* 32 adv_err_addr */
12323 0, /* 33 saved_dvc_err_code */
12324 0, /* 34 saved_adv_err_code */
12325 0, /* 35 saved_adv_err_addr */
12326 0, /* 36 reserved */
12327 0, /* 37 reserved */
12328 0, /* 38 reserved */
12329 0, /* 39 reserved */
12330 0, /* 40 reserved */
12331 0, /* 41 reserved */
12332 0, /* 42 reserved */
12333 0, /* 43 reserved */
12334 0, /* 44 reserved */
12335 0, /* 45 reserved */
12336 0, /* 46 reserved */
12337 0, /* 47 reserved */
12338 0, /* 48 reserved */
12339 0, /* 49 reserved */
12340 0, /* 50 reserved */
12341 0, /* 51 reserved */
12342 0, /* 52 reserved */
12343 0, /* 53 reserved */
12344 0, /* 54 reserved */
12345 0, /* 55 reserved */
12346 0, /* 56 cisptr_lsw */
12347 0, /* 57 cisprt_msw */
12348 PCI_VENDOR_ID_ASP, /* 58 subsysvid */
12349 PCI_DEVICE_ID_38C1600_REV1, /* 59 subsysid */
12350 0, /* 60 reserved */
12351 0, /* 61 reserved */
12352 0, /* 62 reserved */
12353 0 /* 63 reserved */
12356 static ADVEEP_38C1600_CONFIG ADVEEP_38C1600_Config_Field_IsChar __devinitdata = {
12357 0, /* 00 cfg_lsw */
12358 0, /* 01 cfg_msw */
12359 0, /* 02 disc_enable */
12360 0, /* 03 wdtr_able */
12361 0, /* 04 sdtr_speed1 */
12362 0, /* 05 start_motor */
12363 0, /* 06 tagqng_able */
12364 0, /* 07 bios_scan */
12365 0, /* 08 scam_tolerant */
12366 1, /* 09 adapter_scsi_id */
12367 1, /* bios_boot_delay */
12368 1, /* 10 scsi_reset_delay */
12369 1, /* bios_id_lun */
12370 1, /* 11 termination_se */
12371 1, /* termination_lvd */
12372 0, /* 12 bios_ctrl */
12373 0, /* 13 sdtr_speed2 */
12374 0, /* 14 sdtr_speed3 */
12375 1, /* 15 max_host_qng */
12376 1, /* max_dvc_qng */
12377 0, /* 16 dvc_cntl */
12378 0, /* 17 sdtr_speed4 */
12379 0, /* 18 serial_number_word1 */
12380 0, /* 19 serial_number_word2 */
12381 0, /* 20 serial_number_word3 */
12382 0, /* 21 check_sum */
12383 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
12384 , /* 22-29 oem_name[16] */
12385 0, /* 30 dvc_err_code */
12386 0, /* 31 adv_err_code */
12387 0, /* 32 adv_err_addr */
12388 0, /* 33 saved_dvc_err_code */
12389 0, /* 34 saved_adv_err_code */
12390 0, /* 35 saved_adv_err_addr */
12391 0, /* 36 reserved */
12392 0, /* 37 reserved */
12393 0, /* 38 reserved */
12394 0, /* 39 reserved */
12395 0, /* 40 reserved */
12396 0, /* 41 reserved */
12397 0, /* 42 reserved */
12398 0, /* 43 reserved */
12399 0, /* 44 reserved */
12400 0, /* 45 reserved */
12401 0, /* 46 reserved */
12402 0, /* 47 reserved */
12403 0, /* 48 reserved */
12404 0, /* 49 reserved */
12405 0, /* 50 reserved */
12406 0, /* 51 reserved */
12407 0, /* 52 reserved */
12408 0, /* 53 reserved */
12409 0, /* 54 reserved */
12410 0, /* 55 reserved */
12411 0, /* 56 cisptr_lsw */
12412 0, /* 57 cisprt_msw */
12413 0, /* 58 subsysvid */
12414 0, /* 59 subsysid */
12415 0, /* 60 reserved */
12416 0, /* 61 reserved */
12417 0, /* 62 reserved */
12418 0 /* 63 reserved */
12423 * Wait for EEPROM command to complete
12425 static void __devinit AdvWaitEEPCmd(AdvPortAddr iop_base)
12429 for (eep_delay_ms = 0; eep_delay_ms < ADV_EEP_DELAY_MS; eep_delay_ms++) {
12430 if (AdvReadWordRegister(iop_base, IOPW_EE_CMD) &
12431 ASC_EEP_CMD_DONE) {
12436 if ((AdvReadWordRegister(iop_base, IOPW_EE_CMD) & ASC_EEP_CMD_DONE) ==
12442 * Read the EEPROM from specified location
12444 static ushort __devinit AdvReadEEPWord(AdvPortAddr iop_base, int eep_word_addr)
12446 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
12447 ASC_EEP_CMD_READ | eep_word_addr);
12448 AdvWaitEEPCmd(iop_base);
12449 return AdvReadWordRegister(iop_base, IOPW_EE_DATA);
12453 * Write the EEPROM from 'cfg_buf'.
12456 AdvSet3550EEPConfig(AdvPortAddr iop_base, ADVEEP_3550_CONFIG *cfg_buf)
12459 ushort addr, chksum;
12460 ushort *charfields;
12462 wbuf = (ushort *)cfg_buf;
12463 charfields = (ushort *)&ADVEEP_3550_Config_Field_IsChar;
12466 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
12467 AdvWaitEEPCmd(iop_base);
12470 * Write EEPROM from word 0 to word 20.
12472 for (addr = ADV_EEP_DVC_CFG_BEGIN;
12473 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
12476 if (*charfields++) {
12477 word = cpu_to_le16(*wbuf);
12481 chksum += *wbuf; /* Checksum is calculated from word values. */
12482 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
12483 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
12484 ASC_EEP_CMD_WRITE | addr);
12485 AdvWaitEEPCmd(iop_base);
12486 mdelay(ADV_EEP_DELAY_MS);
12490 * Write EEPROM checksum at word 21.
12492 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
12493 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
12494 AdvWaitEEPCmd(iop_base);
12499 * Write EEPROM OEM name at words 22 to 29.
12501 for (addr = ADV_EEP_DVC_CTL_BEGIN;
12502 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
12505 if (*charfields++) {
12506 word = cpu_to_le16(*wbuf);
12510 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
12511 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
12512 ASC_EEP_CMD_WRITE | addr);
12513 AdvWaitEEPCmd(iop_base);
12515 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
12516 AdvWaitEEPCmd(iop_base);
12520 * Write the EEPROM from 'cfg_buf'.
12523 AdvSet38C0800EEPConfig(AdvPortAddr iop_base, ADVEEP_38C0800_CONFIG *cfg_buf)
12526 ushort *charfields;
12527 ushort addr, chksum;
12529 wbuf = (ushort *)cfg_buf;
12530 charfields = (ushort *)&ADVEEP_38C0800_Config_Field_IsChar;
12533 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
12534 AdvWaitEEPCmd(iop_base);
12537 * Write EEPROM from word 0 to word 20.
12539 for (addr = ADV_EEP_DVC_CFG_BEGIN;
12540 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
12543 if (*charfields++) {
12544 word = cpu_to_le16(*wbuf);
12548 chksum += *wbuf; /* Checksum is calculated from word values. */
12549 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
12550 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
12551 ASC_EEP_CMD_WRITE | addr);
12552 AdvWaitEEPCmd(iop_base);
12553 mdelay(ADV_EEP_DELAY_MS);
12557 * Write EEPROM checksum at word 21.
12559 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
12560 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
12561 AdvWaitEEPCmd(iop_base);
12566 * Write EEPROM OEM name at words 22 to 29.
12568 for (addr = ADV_EEP_DVC_CTL_BEGIN;
12569 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
12572 if (*charfields++) {
12573 word = cpu_to_le16(*wbuf);
12577 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
12578 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
12579 ASC_EEP_CMD_WRITE | addr);
12580 AdvWaitEEPCmd(iop_base);
12582 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
12583 AdvWaitEEPCmd(iop_base);
12587 * Write the EEPROM from 'cfg_buf'.
12590 AdvSet38C1600EEPConfig(AdvPortAddr iop_base, ADVEEP_38C1600_CONFIG *cfg_buf)
12593 ushort *charfields;
12594 ushort addr, chksum;
12596 wbuf = (ushort *)cfg_buf;
12597 charfields = (ushort *)&ADVEEP_38C1600_Config_Field_IsChar;
12600 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
12601 AdvWaitEEPCmd(iop_base);
12604 * Write EEPROM from word 0 to word 20.
12606 for (addr = ADV_EEP_DVC_CFG_BEGIN;
12607 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
12610 if (*charfields++) {
12611 word = cpu_to_le16(*wbuf);
12615 chksum += *wbuf; /* Checksum is calculated from word values. */
12616 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
12617 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
12618 ASC_EEP_CMD_WRITE | addr);
12619 AdvWaitEEPCmd(iop_base);
12620 mdelay(ADV_EEP_DELAY_MS);
12624 * Write EEPROM checksum at word 21.
12626 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
12627 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
12628 AdvWaitEEPCmd(iop_base);
12633 * Write EEPROM OEM name at words 22 to 29.
12635 for (addr = ADV_EEP_DVC_CTL_BEGIN;
12636 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
12639 if (*charfields++) {
12640 word = cpu_to_le16(*wbuf);
12644 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
12645 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
12646 ASC_EEP_CMD_WRITE | addr);
12647 AdvWaitEEPCmd(iop_base);
12649 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
12650 AdvWaitEEPCmd(iop_base);
12654 * Read EEPROM configuration into the specified buffer.
12656 * Return a checksum based on the EEPROM configuration read.
12658 static ushort __devinit
12659 AdvGet3550EEPConfig(AdvPortAddr iop_base, ADVEEP_3550_CONFIG *cfg_buf)
12661 ushort wval, chksum;
12664 ushort *charfields;
12666 charfields = (ushort *)&ADVEEP_3550_Config_Field_IsChar;
12667 wbuf = (ushort *)cfg_buf;
12670 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
12671 eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
12672 wval = AdvReadEEPWord(iop_base, eep_addr);
12673 chksum += wval; /* Checksum is calculated from word values. */
12674 if (*charfields++) {
12675 *wbuf = le16_to_cpu(wval);
12680 /* Read checksum word. */
12681 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
12685 /* Read rest of EEPROM not covered by the checksum. */
12686 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
12687 eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
12688 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
12689 if (*charfields++) {
12690 *wbuf = le16_to_cpu(*wbuf);
12697 * Read EEPROM configuration into the specified buffer.
12699 * Return a checksum based on the EEPROM configuration read.
12701 static ushort __devinit
12702 AdvGet38C0800EEPConfig(AdvPortAddr iop_base, ADVEEP_38C0800_CONFIG *cfg_buf)
12704 ushort wval, chksum;
12707 ushort *charfields;
12709 charfields = (ushort *)&ADVEEP_38C0800_Config_Field_IsChar;
12710 wbuf = (ushort *)cfg_buf;
12713 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
12714 eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
12715 wval = AdvReadEEPWord(iop_base, eep_addr);
12716 chksum += wval; /* Checksum is calculated from word values. */
12717 if (*charfields++) {
12718 *wbuf = le16_to_cpu(wval);
12723 /* Read checksum word. */
12724 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
12728 /* Read rest of EEPROM not covered by the checksum. */
12729 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
12730 eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
12731 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
12732 if (*charfields++) {
12733 *wbuf = le16_to_cpu(*wbuf);
12740 * Read EEPROM configuration into the specified buffer.
12742 * Return a checksum based on the EEPROM configuration read.
12744 static ushort __devinit
12745 AdvGet38C1600EEPConfig(AdvPortAddr iop_base, ADVEEP_38C1600_CONFIG *cfg_buf)
12747 ushort wval, chksum;
12750 ushort *charfields;
12752 charfields = (ushort *)&ADVEEP_38C1600_Config_Field_IsChar;
12753 wbuf = (ushort *)cfg_buf;
12756 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
12757 eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
12758 wval = AdvReadEEPWord(iop_base, eep_addr);
12759 chksum += wval; /* Checksum is calculated from word values. */
12760 if (*charfields++) {
12761 *wbuf = le16_to_cpu(wval);
12766 /* Read checksum word. */
12767 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
12771 /* Read rest of EEPROM not covered by the checksum. */
12772 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
12773 eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
12774 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
12775 if (*charfields++) {
12776 *wbuf = le16_to_cpu(*wbuf);
12783 * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and
12784 * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while
12785 * all of this is done.
12787 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
12789 * For a non-fatal error return a warning code. If there are no warnings
12790 * then 0 is returned.
12792 * Note: Chip is stopped on entry.
12794 static int __devinit AdvInitFrom3550EEP(ADV_DVC_VAR *asc_dvc)
12796 AdvPortAddr iop_base;
12798 ADVEEP_3550_CONFIG eep_config;
12800 iop_base = asc_dvc->iop_base;
12805 * Read the board's EEPROM configuration.
12807 * Set default values if a bad checksum is found.
12809 if (AdvGet3550EEPConfig(iop_base, &eep_config) != eep_config.check_sum) {
12810 warn_code |= ASC_WARN_EEPROM_CHKSUM;
12813 * Set EEPROM default values.
12815 memcpy(&eep_config, &Default_3550_EEPROM_Config,
12816 sizeof(ADVEEP_3550_CONFIG));
12819 * Assume the 6 byte board serial number that was read from
12820 * EEPROM is correct even if the EEPROM checksum failed.
12822 eep_config.serial_number_word3 =
12823 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
12825 eep_config.serial_number_word2 =
12826 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
12828 eep_config.serial_number_word1 =
12829 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
12831 AdvSet3550EEPConfig(iop_base, &eep_config);
12834 * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the
12835 * EEPROM configuration that was read.
12837 * This is the mapping of EEPROM fields to Adv Library fields.
12839 asc_dvc->wdtr_able = eep_config.wdtr_able;
12840 asc_dvc->sdtr_able = eep_config.sdtr_able;
12841 asc_dvc->ultra_able = eep_config.ultra_able;
12842 asc_dvc->tagqng_able = eep_config.tagqng_able;
12843 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
12844 asc_dvc->max_host_qng = eep_config.max_host_qng;
12845 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
12846 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ADV_MAX_TID);
12847 asc_dvc->start_motor = eep_config.start_motor;
12848 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
12849 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
12850 asc_dvc->no_scam = eep_config.scam_tolerant;
12851 asc_dvc->cfg->serial1 = eep_config.serial_number_word1;
12852 asc_dvc->cfg->serial2 = eep_config.serial_number_word2;
12853 asc_dvc->cfg->serial3 = eep_config.serial_number_word3;
12856 * Set the host maximum queuing (max. 253, min. 16) and the per device
12857 * maximum queuing (max. 63, min. 4).
12859 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
12860 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
12861 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
12862 /* If the value is zero, assume it is uninitialized. */
12863 if (eep_config.max_host_qng == 0) {
12864 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
12866 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
12870 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
12871 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
12872 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
12873 /* If the value is zero, assume it is uninitialized. */
12874 if (eep_config.max_dvc_qng == 0) {
12875 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
12877 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
12882 * If 'max_dvc_qng' is greater than 'max_host_qng', then
12883 * set 'max_dvc_qng' to 'max_host_qng'.
12885 if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
12886 eep_config.max_dvc_qng = eep_config.max_host_qng;
12890 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng'
12891 * values based on possibly adjusted EEPROM values.
12893 asc_dvc->max_host_qng = eep_config.max_host_qng;
12894 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
12897 * If the EEPROM 'termination' field is set to automatic (0), then set
12898 * the ADV_DVC_CFG 'termination' field to automatic also.
12900 * If the termination is specified with a non-zero 'termination'
12901 * value check that a legal value is set and set the ADV_DVC_CFG
12902 * 'termination' field appropriately.
12904 if (eep_config.termination == 0) {
12905 asc_dvc->cfg->termination = 0; /* auto termination */
12907 /* Enable manual control with low off / high off. */
12908 if (eep_config.termination == 1) {
12909 asc_dvc->cfg->termination = TERM_CTL_SEL;
12911 /* Enable manual control with low off / high on. */
12912 } else if (eep_config.termination == 2) {
12913 asc_dvc->cfg->termination = TERM_CTL_SEL | TERM_CTL_H;
12915 /* Enable manual control with low on / high on. */
12916 } else if (eep_config.termination == 3) {
12917 asc_dvc->cfg->termination =
12918 TERM_CTL_SEL | TERM_CTL_H | TERM_CTL_L;
12921 * The EEPROM 'termination' field contains a bad value. Use
12922 * automatic termination instead.
12924 asc_dvc->cfg->termination = 0;
12925 warn_code |= ASC_WARN_EEPROM_TERMINATION;
12933 * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and
12934 * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while
12935 * all of this is done.
12937 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
12939 * For a non-fatal error return a warning code. If there are no warnings
12940 * then 0 is returned.
12942 * Note: Chip is stopped on entry.
12944 static int __devinit AdvInitFrom38C0800EEP(ADV_DVC_VAR *asc_dvc)
12946 AdvPortAddr iop_base;
12948 ADVEEP_38C0800_CONFIG eep_config;
12949 uchar tid, termination;
12950 ushort sdtr_speed = 0;
12952 iop_base = asc_dvc->iop_base;
12957 * Read the board's EEPROM configuration.
12959 * Set default values if a bad checksum is found.
12961 if (AdvGet38C0800EEPConfig(iop_base, &eep_config) !=
12962 eep_config.check_sum) {
12963 warn_code |= ASC_WARN_EEPROM_CHKSUM;
12966 * Set EEPROM default values.
12968 memcpy(&eep_config, &Default_38C0800_EEPROM_Config,
12969 sizeof(ADVEEP_38C0800_CONFIG));
12972 * Assume the 6 byte board serial number that was read from
12973 * EEPROM is correct even if the EEPROM checksum failed.
12975 eep_config.serial_number_word3 =
12976 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
12978 eep_config.serial_number_word2 =
12979 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
12981 eep_config.serial_number_word1 =
12982 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
12984 AdvSet38C0800EEPConfig(iop_base, &eep_config);
12987 * Set ADV_DVC_VAR and ADV_DVC_CFG variables from the
12988 * EEPROM configuration that was read.
12990 * This is the mapping of EEPROM fields to Adv Library fields.
12992 asc_dvc->wdtr_able = eep_config.wdtr_able;
12993 asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1;
12994 asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2;
12995 asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3;
12996 asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4;
12997 asc_dvc->tagqng_able = eep_config.tagqng_able;
12998 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
12999 asc_dvc->max_host_qng = eep_config.max_host_qng;
13000 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
13001 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ADV_MAX_TID);
13002 asc_dvc->start_motor = eep_config.start_motor;
13003 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
13004 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
13005 asc_dvc->no_scam = eep_config.scam_tolerant;
13006 asc_dvc->cfg->serial1 = eep_config.serial_number_word1;
13007 asc_dvc->cfg->serial2 = eep_config.serial_number_word2;
13008 asc_dvc->cfg->serial3 = eep_config.serial_number_word3;
13011 * For every Target ID if any of its 'sdtr_speed[1234]' bits
13012 * are set, then set an 'sdtr_able' bit for it.
13014 asc_dvc->sdtr_able = 0;
13015 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
13017 sdtr_speed = asc_dvc->sdtr_speed1;
13018 } else if (tid == 4) {
13019 sdtr_speed = asc_dvc->sdtr_speed2;
13020 } else if (tid == 8) {
13021 sdtr_speed = asc_dvc->sdtr_speed3;
13022 } else if (tid == 12) {
13023 sdtr_speed = asc_dvc->sdtr_speed4;
13025 if (sdtr_speed & ADV_MAX_TID) {
13026 asc_dvc->sdtr_able |= (1 << tid);
13032 * Set the host maximum queuing (max. 253, min. 16) and the per device
13033 * maximum queuing (max. 63, min. 4).
13035 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
13036 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
13037 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
13038 /* If the value is zero, assume it is uninitialized. */
13039 if (eep_config.max_host_qng == 0) {
13040 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
13042 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
13046 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
13047 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
13048 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
13049 /* If the value is zero, assume it is uninitialized. */
13050 if (eep_config.max_dvc_qng == 0) {
13051 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
13053 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
13058 * If 'max_dvc_qng' is greater than 'max_host_qng', then
13059 * set 'max_dvc_qng' to 'max_host_qng'.
13061 if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
13062 eep_config.max_dvc_qng = eep_config.max_host_qng;
13066 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng'
13067 * values based on possibly adjusted EEPROM values.
13069 asc_dvc->max_host_qng = eep_config.max_host_qng;
13070 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
13073 * If the EEPROM 'termination' field is set to automatic (0), then set
13074 * the ADV_DVC_CFG 'termination' field to automatic also.
13076 * If the termination is specified with a non-zero 'termination'
13077 * value check that a legal value is set and set the ADV_DVC_CFG
13078 * 'termination' field appropriately.
13080 if (eep_config.termination_se == 0) {
13081 termination = 0; /* auto termination for SE */
13083 /* Enable manual control with low off / high off. */
13084 if (eep_config.termination_se == 1) {
13087 /* Enable manual control with low off / high on. */
13088 } else if (eep_config.termination_se == 2) {
13089 termination = TERM_SE_HI;
13091 /* Enable manual control with low on / high on. */
13092 } else if (eep_config.termination_se == 3) {
13093 termination = TERM_SE;
13096 * The EEPROM 'termination_se' field contains a bad value.
13097 * Use automatic termination instead.
13100 warn_code |= ASC_WARN_EEPROM_TERMINATION;
13104 if (eep_config.termination_lvd == 0) {
13105 asc_dvc->cfg->termination = termination; /* auto termination for LVD */
13107 /* Enable manual control with low off / high off. */
13108 if (eep_config.termination_lvd == 1) {
13109 asc_dvc->cfg->termination = termination;
13111 /* Enable manual control with low off / high on. */
13112 } else if (eep_config.termination_lvd == 2) {
13113 asc_dvc->cfg->termination = termination | TERM_LVD_HI;
13115 /* Enable manual control with low on / high on. */
13116 } else if (eep_config.termination_lvd == 3) {
13117 asc_dvc->cfg->termination = termination | TERM_LVD;
13120 * The EEPROM 'termination_lvd' field contains a bad value.
13121 * Use automatic termination instead.
13123 asc_dvc->cfg->termination = termination;
13124 warn_code |= ASC_WARN_EEPROM_TERMINATION;
13132 * Read the board's EEPROM configuration. Set fields in ASC_DVC_VAR and
13133 * ASC_DVC_CFG based on the EEPROM settings. The chip is stopped while
13134 * all of this is done.
13136 * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR.
13138 * For a non-fatal error return a warning code. If there are no warnings
13139 * then 0 is returned.
13141 * Note: Chip is stopped on entry.
13143 static int __devinit AdvInitFrom38C1600EEP(ADV_DVC_VAR *asc_dvc)
13145 AdvPortAddr iop_base;
13147 ADVEEP_38C1600_CONFIG eep_config;
13148 uchar tid, termination;
13149 ushort sdtr_speed = 0;
13151 iop_base = asc_dvc->iop_base;
13156 * Read the board's EEPROM configuration.
13158 * Set default values if a bad checksum is found.
13160 if (AdvGet38C1600EEPConfig(iop_base, &eep_config) !=
13161 eep_config.check_sum) {
13162 struct pci_dev *pdev = adv_dvc_to_pdev(asc_dvc);
13163 warn_code |= ASC_WARN_EEPROM_CHKSUM;
13166 * Set EEPROM default values.
13168 memcpy(&eep_config, &Default_38C1600_EEPROM_Config,
13169 sizeof(ADVEEP_38C1600_CONFIG));
13171 if (PCI_FUNC(pdev->devfn) != 0) {
13174 * Disable Bit 14 (BIOS_ENABLE) to fix SPARC Ultra 60
13175 * and old Mac system booting problem. The Expansion
13176 * ROM must be disabled in Function 1 for these systems
13178 eep_config.cfg_lsw &= ~ADV_EEPROM_BIOS_ENABLE;
13180 * Clear the INTAB (bit 11) if the GPIO 0 input
13181 * indicates the Function 1 interrupt line is wired
13184 * Set/Clear Bit 11 (INTAB) from the GPIO bit 0 input:
13185 * 1 - Function 1 interrupt line wired to INT A.
13186 * 0 - Function 1 interrupt line wired to INT B.
13188 * Note: Function 0 is always wired to INTA.
13189 * Put all 5 GPIO bits in input mode and then read
13190 * their input values.
13192 AdvWriteByteRegister(iop_base, IOPB_GPIO_CNTL, 0);
13193 ints = AdvReadByteRegister(iop_base, IOPB_GPIO_DATA);
13194 if ((ints & 0x01) == 0)
13195 eep_config.cfg_lsw &= ~ADV_EEPROM_INTAB;
13199 * Assume the 6 byte board serial number that was read from
13200 * EEPROM is correct even if the EEPROM checksum failed.
13202 eep_config.serial_number_word3 =
13203 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
13204 eep_config.serial_number_word2 =
13205 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
13206 eep_config.serial_number_word1 =
13207 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
13209 AdvSet38C1600EEPConfig(iop_base, &eep_config);
13213 * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the
13214 * EEPROM configuration that was read.
13216 * This is the mapping of EEPROM fields to Adv Library fields.
13218 asc_dvc->wdtr_able = eep_config.wdtr_able;
13219 asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1;
13220 asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2;
13221 asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3;
13222 asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4;
13223 asc_dvc->ppr_able = 0;
13224 asc_dvc->tagqng_able = eep_config.tagqng_able;
13225 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
13226 asc_dvc->max_host_qng = eep_config.max_host_qng;
13227 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
13228 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ASC_MAX_TID);
13229 asc_dvc->start_motor = eep_config.start_motor;
13230 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
13231 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
13232 asc_dvc->no_scam = eep_config.scam_tolerant;
13235 * For every Target ID if any of its 'sdtr_speed[1234]' bits
13236 * are set, then set an 'sdtr_able' bit for it.
13238 asc_dvc->sdtr_able = 0;
13239 for (tid = 0; tid <= ASC_MAX_TID; tid++) {
13241 sdtr_speed = asc_dvc->sdtr_speed1;
13242 } else if (tid == 4) {
13243 sdtr_speed = asc_dvc->sdtr_speed2;
13244 } else if (tid == 8) {
13245 sdtr_speed = asc_dvc->sdtr_speed3;
13246 } else if (tid == 12) {
13247 sdtr_speed = asc_dvc->sdtr_speed4;
13249 if (sdtr_speed & ASC_MAX_TID) {
13250 asc_dvc->sdtr_able |= (1 << tid);
13256 * Set the host maximum queuing (max. 253, min. 16) and the per device
13257 * maximum queuing (max. 63, min. 4).
13259 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
13260 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
13261 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
13262 /* If the value is zero, assume it is uninitialized. */
13263 if (eep_config.max_host_qng == 0) {
13264 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
13266 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
13270 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
13271 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
13272 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
13273 /* If the value is zero, assume it is uninitialized. */
13274 if (eep_config.max_dvc_qng == 0) {
13275 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
13277 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
13282 * If 'max_dvc_qng' is greater than 'max_host_qng', then
13283 * set 'max_dvc_qng' to 'max_host_qng'.
13285 if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
13286 eep_config.max_dvc_qng = eep_config.max_host_qng;
13290 * Set ASC_DVC_VAR 'max_host_qng' and ASC_DVC_VAR 'max_dvc_qng'
13291 * values based on possibly adjusted EEPROM values.
13293 asc_dvc->max_host_qng = eep_config.max_host_qng;
13294 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
13297 * If the EEPROM 'termination' field is set to automatic (0), then set
13298 * the ASC_DVC_CFG 'termination' field to automatic also.
13300 * If the termination is specified with a non-zero 'termination'
13301 * value check that a legal value is set and set the ASC_DVC_CFG
13302 * 'termination' field appropriately.
13304 if (eep_config.termination_se == 0) {
13305 termination = 0; /* auto termination for SE */
13307 /* Enable manual control with low off / high off. */
13308 if (eep_config.termination_se == 1) {
13311 /* Enable manual control with low off / high on. */
13312 } else if (eep_config.termination_se == 2) {
13313 termination = TERM_SE_HI;
13315 /* Enable manual control with low on / high on. */
13316 } else if (eep_config.termination_se == 3) {
13317 termination = TERM_SE;
13320 * The EEPROM 'termination_se' field contains a bad value.
13321 * Use automatic termination instead.
13324 warn_code |= ASC_WARN_EEPROM_TERMINATION;
13328 if (eep_config.termination_lvd == 0) {
13329 asc_dvc->cfg->termination = termination; /* auto termination for LVD */
13331 /* Enable manual control with low off / high off. */
13332 if (eep_config.termination_lvd == 1) {
13333 asc_dvc->cfg->termination = termination;
13335 /* Enable manual control with low off / high on. */
13336 } else if (eep_config.termination_lvd == 2) {
13337 asc_dvc->cfg->termination = termination | TERM_LVD_HI;
13339 /* Enable manual control with low on / high on. */
13340 } else if (eep_config.termination_lvd == 3) {
13341 asc_dvc->cfg->termination = termination | TERM_LVD;
13344 * The EEPROM 'termination_lvd' field contains a bad value.
13345 * Use automatic termination instead.
13347 asc_dvc->cfg->termination = termination;
13348 warn_code |= ASC_WARN_EEPROM_TERMINATION;
13356 * Initialize the ADV_DVC_VAR structure.
13358 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
13360 * For a non-fatal error return a warning code. If there are no warnings
13361 * then 0 is returned.
13363 static int __devinit
13364 AdvInitGetConfig(struct pci_dev *pdev, struct Scsi_Host *shost)
13366 struct asc_board *board = shost_priv(shost);
13367 ADV_DVC_VAR *asc_dvc = &board->dvc_var.adv_dvc_var;
13368 unsigned short warn_code = 0;
13369 AdvPortAddr iop_base = asc_dvc->iop_base;
13373 asc_dvc->err_code = 0;
13376 * Save the state of the PCI Configuration Command Register
13377 * "Parity Error Response Control" Bit. If the bit is clear (0),
13378 * in AdvInitAsc3550/38C0800Driver() tell the microcode to ignore
13379 * DMA parity errors.
13381 asc_dvc->cfg->control_flag = 0;
13382 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
13383 if ((cmd & PCI_COMMAND_PARITY) == 0)
13384 asc_dvc->cfg->control_flag |= CONTROL_FLAG_IGNORE_PERR;
13386 asc_dvc->cfg->chip_version =
13387 AdvGetChipVersion(iop_base, asc_dvc->bus_type);
13389 ASC_DBG(1, "iopb_chip_id_1: 0x%x 0x%x\n",
13390 (ushort)AdvReadByteRegister(iop_base, IOPB_CHIP_ID_1),
13391 (ushort)ADV_CHIP_ID_BYTE);
13393 ASC_DBG(1, "iopw_chip_id_0: 0x%x 0x%x\n",
13394 (ushort)AdvReadWordRegister(iop_base, IOPW_CHIP_ID_0),
13395 (ushort)ADV_CHIP_ID_WORD);
13398 * Reset the chip to start and allow register writes.
13400 if (AdvFindSignature(iop_base) == 0) {
13401 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
13405 * The caller must set 'chip_type' to a valid setting.
13407 if (asc_dvc->chip_type != ADV_CHIP_ASC3550 &&
13408 asc_dvc->chip_type != ADV_CHIP_ASC38C0800 &&
13409 asc_dvc->chip_type != ADV_CHIP_ASC38C1600) {
13410 asc_dvc->err_code |= ASC_IERR_BAD_CHIPTYPE;
13417 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
13418 ADV_CTRL_REG_CMD_RESET);
13420 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
13421 ADV_CTRL_REG_CMD_WR_IO_REG);
13423 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
13424 status = AdvInitFrom38C1600EEP(asc_dvc);
13425 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
13426 status = AdvInitFrom38C0800EEP(asc_dvc);
13428 status = AdvInitFrom3550EEP(asc_dvc);
13430 warn_code |= status;
13433 if (warn_code != 0)
13434 shost_printk(KERN_WARNING, shost, "warning: 0x%x\n", warn_code);
13436 if (asc_dvc->err_code)
13437 shost_printk(KERN_ERR, shost, "error code 0x%x\n",
13438 asc_dvc->err_code);
13440 return asc_dvc->err_code;
13444 static struct scsi_host_template advansys_template = {
13445 .proc_name = DRV_NAME,
13446 #ifdef CONFIG_PROC_FS
13447 .proc_info = advansys_proc_info,
13450 .info = advansys_info,
13451 .queuecommand = advansys_queuecommand,
13452 .eh_bus_reset_handler = advansys_reset,
13453 .bios_param = advansys_biosparam,
13454 .slave_configure = advansys_slave_configure,
13456 * Because the driver may control an ISA adapter 'unchecked_isa_dma'
13457 * must be set. The flag will be cleared in advansys_board_found
13458 * for non-ISA adapters.
13460 .unchecked_isa_dma = 1,
13462 * All adapters controlled by this driver are capable of large
13463 * scatter-gather lists. According to the mid-level SCSI documentation
13464 * this obviates any performance gain provided by setting
13465 * 'use_clustering'. But empirically while CPU utilization is increased
13466 * by enabling clustering, I/O throughput increases as well.
13468 .use_clustering = ENABLE_CLUSTERING,
13471 static int __devinit advansys_wide_init_chip(struct Scsi_Host *shost)
13473 struct asc_board *board = shost_priv(shost);
13474 struct adv_dvc_var *adv_dvc = &board->dvc_var.adv_dvc_var;
13476 adv_req_t *reqp = NULL;
13479 int warn_code, err_code;
13482 * Allocate buffer carrier structures. The total size
13483 * is about 4 KB, so allocate all at once.
13485 board->carrp = kmalloc(ADV_CARRIER_BUFSIZE, GFP_KERNEL);
13486 ASC_DBG(1, "carrp 0x%p\n", board->carrp);
13489 goto kmalloc_failed;
13492 * Allocate up to 'max_host_qng' request structures for the Wide
13493 * board. The total size is about 16 KB, so allocate all at once.
13494 * If the allocation fails decrement and try again.
13496 for (req_cnt = adv_dvc->max_host_qng; req_cnt > 0; req_cnt--) {
13497 reqp = kmalloc(sizeof(adv_req_t) * req_cnt, GFP_KERNEL);
13499 ASC_DBG(1, "reqp 0x%p, req_cnt %d, bytes %lu\n", reqp, req_cnt,
13500 (ulong)sizeof(adv_req_t) * req_cnt);
13507 goto kmalloc_failed;
13509 board->orig_reqp = reqp;
13512 * Allocate up to ADV_TOT_SG_BLOCK request structures for
13513 * the Wide board. Each structure is about 136 bytes.
13515 board->adv_sgblkp = NULL;
13516 for (sg_cnt = 0; sg_cnt < ADV_TOT_SG_BLOCK; sg_cnt++) {
13517 sgp = kmalloc(sizeof(adv_sgblk_t), GFP_KERNEL);
13522 sgp->next_sgblkp = board->adv_sgblkp;
13523 board->adv_sgblkp = sgp;
13527 ASC_DBG(1, "sg_cnt %d * %u = %u bytes\n", sg_cnt, sizeof(adv_sgblk_t),
13528 (unsigned)(sizeof(adv_sgblk_t) * sg_cnt));
13530 if (!board->adv_sgblkp)
13531 goto kmalloc_failed;
13533 adv_dvc->carrier_buf = board->carrp;
13536 * Point 'adv_reqp' to the request structures and
13537 * link them together.
13540 reqp[req_cnt].next_reqp = NULL;
13541 for (; req_cnt > 0; req_cnt--) {
13542 reqp[req_cnt - 1].next_reqp = &reqp[req_cnt];
13544 board->adv_reqp = &reqp[0];
13546 if (adv_dvc->chip_type == ADV_CHIP_ASC3550) {
13547 ASC_DBG(2, "AdvInitAsc3550Driver()\n");
13548 warn_code = AdvInitAsc3550Driver(adv_dvc);
13549 } else if (adv_dvc->chip_type == ADV_CHIP_ASC38C0800) {
13550 ASC_DBG(2, "AdvInitAsc38C0800Driver()\n");
13551 warn_code = AdvInitAsc38C0800Driver(adv_dvc);
13553 ASC_DBG(2, "AdvInitAsc38C1600Driver()\n");
13554 warn_code = AdvInitAsc38C1600Driver(adv_dvc);
13556 err_code = adv_dvc->err_code;
13558 if (warn_code || err_code) {
13559 shost_printk(KERN_WARNING, shost, "error: warn 0x%x, error "
13560 "0x%x\n", warn_code, err_code);
13566 shost_printk(KERN_ERR, shost, "error: kmalloc() failed\n");
13567 err_code = ADV_ERROR;
13572 static void advansys_wide_free_mem(struct asc_board *boardp)
13574 kfree(boardp->carrp);
13575 boardp->carrp = NULL;
13576 kfree(boardp->orig_reqp);
13577 boardp->orig_reqp = boardp->adv_reqp = NULL;
13578 while (boardp->adv_sgblkp) {
13579 adv_sgblk_t *sgp = boardp->adv_sgblkp;
13580 boardp->adv_sgblkp = sgp->next_sgblkp;
13585 static int __devinit advansys_board_found(struct Scsi_Host *shost,
13586 unsigned int iop, int bus_type)
13588 struct pci_dev *pdev;
13589 struct asc_board *boardp = shost_priv(shost);
13590 ASC_DVC_VAR *asc_dvc_varp = NULL;
13591 ADV_DVC_VAR *adv_dvc_varp = NULL;
13592 int share_irq, warn_code, ret;
13594 pdev = (bus_type == ASC_IS_PCI) ? to_pci_dev(boardp->dev) : NULL;
13596 if (ASC_NARROW_BOARD(boardp)) {
13597 ASC_DBG(1, "narrow board\n");
13598 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
13599 asc_dvc_varp->bus_type = bus_type;
13600 asc_dvc_varp->drv_ptr = boardp;
13601 asc_dvc_varp->cfg = &boardp->dvc_cfg.asc_dvc_cfg;
13602 asc_dvc_varp->cfg->overrun_buf = &overrun_buf[0];
13603 asc_dvc_varp->iop_base = iop;
13606 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
13607 adv_dvc_varp->drv_ptr = boardp;
13608 adv_dvc_varp->cfg = &boardp->dvc_cfg.adv_dvc_cfg;
13609 if (pdev->device == PCI_DEVICE_ID_ASP_ABP940UW) {
13610 ASC_DBG(1, "wide board ASC-3550\n");
13611 adv_dvc_varp->chip_type = ADV_CHIP_ASC3550;
13612 } else if (pdev->device == PCI_DEVICE_ID_38C0800_REV1) {
13613 ASC_DBG(1, "wide board ASC-38C0800\n");
13614 adv_dvc_varp->chip_type = ADV_CHIP_ASC38C0800;
13616 ASC_DBG(1, "wide board ASC-38C1600\n");
13617 adv_dvc_varp->chip_type = ADV_CHIP_ASC38C1600;
13620 boardp->asc_n_io_port = pci_resource_len(pdev, 1);
13621 boardp->ioremap_addr = ioremap(pci_resource_start(pdev, 1),
13622 boardp->asc_n_io_port);
13623 if (!boardp->ioremap_addr) {
13624 shost_printk(KERN_ERR, shost, "ioremap(%x, %d) "
13626 pci_resource_start(pdev, 1),
13627 boardp->asc_n_io_port);
13631 adv_dvc_varp->iop_base = (AdvPortAddr)boardp->ioremap_addr;
13632 ASC_DBG(1, "iop_base: 0x%p\n", adv_dvc_varp->iop_base);
13635 * Even though it isn't used to access wide boards, other
13636 * than for the debug line below, save I/O Port address so
13637 * that it can be reported.
13639 boardp->ioport = iop;
13641 ASC_DBG(1, "iopb_chip_id_1 0x%x, iopw_chip_id_0 0x%x\n",
13642 (ushort)inp(iop + 1), (ushort)inpw(iop));
13643 #endif /* CONFIG_PCI */
13646 #ifdef CONFIG_PROC_FS
13648 * Allocate buffer for printing information from
13649 * /proc/scsi/advansys/[0...].
13651 boardp->prtbuf = kmalloc(ASC_PRTBUF_SIZE, GFP_KERNEL);
13652 if (!boardp->prtbuf) {
13653 shost_printk(KERN_ERR, shost, "kmalloc(%d) returned NULL\n",
13658 #endif /* CONFIG_PROC_FS */
13660 if (ASC_NARROW_BOARD(boardp)) {
13662 * Set the board bus type and PCI IRQ before
13663 * calling AscInitGetConfig().
13665 switch (asc_dvc_varp->bus_type) {
13668 shost->unchecked_isa_dma = TRUE;
13672 shost->unchecked_isa_dma = FALSE;
13676 shost->unchecked_isa_dma = FALSE;
13677 share_irq = IRQF_SHARED;
13679 #endif /* CONFIG_ISA */
13682 shost->unchecked_isa_dma = FALSE;
13683 share_irq = IRQF_SHARED;
13685 #endif /* CONFIG_PCI */
13687 shost_printk(KERN_ERR, shost, "unknown adapter type: "
13688 "%d\n", asc_dvc_varp->bus_type);
13689 shost->unchecked_isa_dma = TRUE;
13695 * NOTE: AscInitGetConfig() may change the board's
13696 * bus_type value. The bus_type value should no
13697 * longer be used. If the bus_type field must be
13698 * referenced only use the bit-wise AND operator "&".
13700 ASC_DBG(2, "AscInitGetConfig()\n");
13701 ret = AscInitGetConfig(shost) ? -ENODEV : 0;
13705 * For Wide boards set PCI information before calling
13706 * AdvInitGetConfig().
13708 shost->unchecked_isa_dma = FALSE;
13709 share_irq = IRQF_SHARED;
13710 ASC_DBG(2, "AdvInitGetConfig()\n");
13712 ret = AdvInitGetConfig(pdev, shost) ? -ENODEV : 0;
13713 #endif /* CONFIG_PCI */
13717 goto err_free_proc;
13720 * Save the EEPROM configuration so that it can be displayed
13721 * from /proc/scsi/advansys/[0...].
13723 if (ASC_NARROW_BOARD(boardp)) {
13728 * Set the adapter's target id bit in the 'init_tidmask' field.
13730 boardp->init_tidmask |=
13731 ADV_TID_TO_TIDMASK(asc_dvc_varp->cfg->chip_scsi_id);
13734 * Save EEPROM settings for the board.
13736 ep = &boardp->eep_config.asc_eep;
13738 ep->init_sdtr = asc_dvc_varp->cfg->sdtr_enable;
13739 ep->disc_enable = asc_dvc_varp->cfg->disc_enable;
13740 ep->use_cmd_qng = asc_dvc_varp->cfg->cmd_qng_enabled;
13741 ASC_EEP_SET_DMA_SPD(ep, asc_dvc_varp->cfg->isa_dma_speed);
13742 ep->start_motor = asc_dvc_varp->start_motor;
13743 ep->cntl = asc_dvc_varp->dvc_cntl;
13744 ep->no_scam = asc_dvc_varp->no_scam;
13745 ep->max_total_qng = asc_dvc_varp->max_total_qng;
13746 ASC_EEP_SET_CHIP_ID(ep, asc_dvc_varp->cfg->chip_scsi_id);
13747 /* 'max_tag_qng' is set to the same value for every device. */
13748 ep->max_tag_qng = asc_dvc_varp->cfg->max_tag_qng[0];
13749 ep->adapter_info[0] = asc_dvc_varp->cfg->adapter_info[0];
13750 ep->adapter_info[1] = asc_dvc_varp->cfg->adapter_info[1];
13751 ep->adapter_info[2] = asc_dvc_varp->cfg->adapter_info[2];
13752 ep->adapter_info[3] = asc_dvc_varp->cfg->adapter_info[3];
13753 ep->adapter_info[4] = asc_dvc_varp->cfg->adapter_info[4];
13754 ep->adapter_info[5] = asc_dvc_varp->cfg->adapter_info[5];
13757 * Modify board configuration.
13759 ASC_DBG(2, "AscInitSetConfig()\n");
13760 ret = AscInitSetConfig(pdev, shost) ? -ENODEV : 0;
13762 goto err_free_proc;
13764 ADVEEP_3550_CONFIG *ep_3550;
13765 ADVEEP_38C0800_CONFIG *ep_38C0800;
13766 ADVEEP_38C1600_CONFIG *ep_38C1600;
13769 * Save Wide EEP Configuration Information.
13771 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
13772 ep_3550 = &boardp->eep_config.adv_3550_eep;
13774 ep_3550->adapter_scsi_id = adv_dvc_varp->chip_scsi_id;
13775 ep_3550->max_host_qng = adv_dvc_varp->max_host_qng;
13776 ep_3550->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
13777 ep_3550->termination = adv_dvc_varp->cfg->termination;
13778 ep_3550->disc_enable = adv_dvc_varp->cfg->disc_enable;
13779 ep_3550->bios_ctrl = adv_dvc_varp->bios_ctrl;
13780 ep_3550->wdtr_able = adv_dvc_varp->wdtr_able;
13781 ep_3550->sdtr_able = adv_dvc_varp->sdtr_able;
13782 ep_3550->ultra_able = adv_dvc_varp->ultra_able;
13783 ep_3550->tagqng_able = adv_dvc_varp->tagqng_able;
13784 ep_3550->start_motor = adv_dvc_varp->start_motor;
13785 ep_3550->scsi_reset_delay =
13786 adv_dvc_varp->scsi_reset_wait;
13787 ep_3550->serial_number_word1 =
13788 adv_dvc_varp->cfg->serial1;
13789 ep_3550->serial_number_word2 =
13790 adv_dvc_varp->cfg->serial2;
13791 ep_3550->serial_number_word3 =
13792 adv_dvc_varp->cfg->serial3;
13793 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
13794 ep_38C0800 = &boardp->eep_config.adv_38C0800_eep;
13796 ep_38C0800->adapter_scsi_id =
13797 adv_dvc_varp->chip_scsi_id;
13798 ep_38C0800->max_host_qng = adv_dvc_varp->max_host_qng;
13799 ep_38C0800->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
13800 ep_38C0800->termination_lvd =
13801 adv_dvc_varp->cfg->termination;
13802 ep_38C0800->disc_enable =
13803 adv_dvc_varp->cfg->disc_enable;
13804 ep_38C0800->bios_ctrl = adv_dvc_varp->bios_ctrl;
13805 ep_38C0800->wdtr_able = adv_dvc_varp->wdtr_able;
13806 ep_38C0800->tagqng_able = adv_dvc_varp->tagqng_able;
13807 ep_38C0800->sdtr_speed1 = adv_dvc_varp->sdtr_speed1;
13808 ep_38C0800->sdtr_speed2 = adv_dvc_varp->sdtr_speed2;
13809 ep_38C0800->sdtr_speed3 = adv_dvc_varp->sdtr_speed3;
13810 ep_38C0800->sdtr_speed4 = adv_dvc_varp->sdtr_speed4;
13811 ep_38C0800->tagqng_able = adv_dvc_varp->tagqng_able;
13812 ep_38C0800->start_motor = adv_dvc_varp->start_motor;
13813 ep_38C0800->scsi_reset_delay =
13814 adv_dvc_varp->scsi_reset_wait;
13815 ep_38C0800->serial_number_word1 =
13816 adv_dvc_varp->cfg->serial1;
13817 ep_38C0800->serial_number_word2 =
13818 adv_dvc_varp->cfg->serial2;
13819 ep_38C0800->serial_number_word3 =
13820 adv_dvc_varp->cfg->serial3;
13822 ep_38C1600 = &boardp->eep_config.adv_38C1600_eep;
13824 ep_38C1600->adapter_scsi_id =
13825 adv_dvc_varp->chip_scsi_id;
13826 ep_38C1600->max_host_qng = adv_dvc_varp->max_host_qng;
13827 ep_38C1600->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
13828 ep_38C1600->termination_lvd =
13829 adv_dvc_varp->cfg->termination;
13830 ep_38C1600->disc_enable =
13831 adv_dvc_varp->cfg->disc_enable;
13832 ep_38C1600->bios_ctrl = adv_dvc_varp->bios_ctrl;
13833 ep_38C1600->wdtr_able = adv_dvc_varp->wdtr_able;
13834 ep_38C1600->tagqng_able = adv_dvc_varp->tagqng_able;
13835 ep_38C1600->sdtr_speed1 = adv_dvc_varp->sdtr_speed1;
13836 ep_38C1600->sdtr_speed2 = adv_dvc_varp->sdtr_speed2;
13837 ep_38C1600->sdtr_speed3 = adv_dvc_varp->sdtr_speed3;
13838 ep_38C1600->sdtr_speed4 = adv_dvc_varp->sdtr_speed4;
13839 ep_38C1600->tagqng_able = adv_dvc_varp->tagqng_able;
13840 ep_38C1600->start_motor = adv_dvc_varp->start_motor;
13841 ep_38C1600->scsi_reset_delay =
13842 adv_dvc_varp->scsi_reset_wait;
13843 ep_38C1600->serial_number_word1 =
13844 adv_dvc_varp->cfg->serial1;
13845 ep_38C1600->serial_number_word2 =
13846 adv_dvc_varp->cfg->serial2;
13847 ep_38C1600->serial_number_word3 =
13848 adv_dvc_varp->cfg->serial3;
13852 * Set the adapter's target id bit in the 'init_tidmask' field.
13854 boardp->init_tidmask |=
13855 ADV_TID_TO_TIDMASK(adv_dvc_varp->chip_scsi_id);
13859 * Channels are numbered beginning with 0. For AdvanSys one host
13860 * structure supports one channel. Multi-channel boards have a
13861 * separate host structure for each channel.
13863 shost->max_channel = 0;
13864 if (ASC_NARROW_BOARD(boardp)) {
13865 shost->max_id = ASC_MAX_TID + 1;
13866 shost->max_lun = ASC_MAX_LUN + 1;
13867 shost->max_cmd_len = ASC_MAX_CDB_LEN;
13869 shost->io_port = asc_dvc_varp->iop_base;
13870 boardp->asc_n_io_port = ASC_IOADR_GAP;
13871 shost->this_id = asc_dvc_varp->cfg->chip_scsi_id;
13873 /* Set maximum number of queues the adapter can handle. */
13874 shost->can_queue = asc_dvc_varp->max_total_qng;
13876 shost->max_id = ADV_MAX_TID + 1;
13877 shost->max_lun = ADV_MAX_LUN + 1;
13878 shost->max_cmd_len = ADV_MAX_CDB_LEN;
13881 * Save the I/O Port address and length even though
13882 * I/O ports are not used to access Wide boards.
13883 * Instead the Wide boards are accessed with
13884 * PCI Memory Mapped I/O.
13886 shost->io_port = iop;
13888 shost->this_id = adv_dvc_varp->chip_scsi_id;
13890 /* Set maximum number of queues the adapter can handle. */
13891 shost->can_queue = adv_dvc_varp->max_host_qng;
13895 * Following v1.3.89, 'cmd_per_lun' is no longer needed
13896 * and should be set to zero.
13898 * But because of a bug introduced in v1.3.89 if the driver is
13899 * compiled as a module and 'cmd_per_lun' is zero, the Mid-Level
13900 * SCSI function 'allocate_device' will panic. To allow the driver
13901 * to work as a module in these kernels set 'cmd_per_lun' to 1.
13903 * Note: This is wrong. cmd_per_lun should be set to the depth
13904 * you want on untagged devices always.
13907 shost->cmd_per_lun = 1;
13909 shost->cmd_per_lun = 0;
13913 * Set the maximum number of scatter-gather elements the
13914 * adapter can handle.
13916 if (ASC_NARROW_BOARD(boardp)) {
13918 * Allow two commands with 'sg_tablesize' scatter-gather
13919 * elements to be executed simultaneously. This value is
13920 * the theoretical hardware limit. It may be decreased
13923 shost->sg_tablesize =
13924 (((asc_dvc_varp->max_total_qng - 2) / 2) *
13925 ASC_SG_LIST_PER_Q) + 1;
13927 shost->sg_tablesize = ADV_MAX_SG_LIST;
13931 * The value of 'sg_tablesize' can not exceed the SCSI
13932 * mid-level driver definition of SG_ALL. SG_ALL also
13933 * must not be exceeded, because it is used to define the
13934 * size of the scatter-gather table in 'struct asc_sg_head'.
13936 if (shost->sg_tablesize > SG_ALL) {
13937 shost->sg_tablesize = SG_ALL;
13940 ASC_DBG(1, "sg_tablesize: %d\n", shost->sg_tablesize);
13942 /* BIOS start address. */
13943 if (ASC_NARROW_BOARD(boardp)) {
13944 shost->base = AscGetChipBiosAddress(asc_dvc_varp->iop_base,
13945 asc_dvc_varp->bus_type);
13948 * Fill-in BIOS board variables. The Wide BIOS saves
13949 * information in LRAM that is used by the driver.
13951 AdvReadWordLram(adv_dvc_varp->iop_base,
13952 BIOS_SIGNATURE, boardp->bios_signature);
13953 AdvReadWordLram(adv_dvc_varp->iop_base,
13954 BIOS_VERSION, boardp->bios_version);
13955 AdvReadWordLram(adv_dvc_varp->iop_base,
13956 BIOS_CODESEG, boardp->bios_codeseg);
13957 AdvReadWordLram(adv_dvc_varp->iop_base,
13958 BIOS_CODELEN, boardp->bios_codelen);
13960 ASC_DBG(1, "bios_signature 0x%x, bios_version 0x%x\n",
13961 boardp->bios_signature, boardp->bios_version);
13963 ASC_DBG(1, "bios_codeseg 0x%x, bios_codelen 0x%x\n",
13964 boardp->bios_codeseg, boardp->bios_codelen);
13967 * If the BIOS saved a valid signature, then fill in
13968 * the BIOS code segment base address.
13970 if (boardp->bios_signature == 0x55AA) {
13972 * Convert x86 realmode code segment to a linear
13973 * address by shifting left 4.
13975 shost->base = ((ulong)boardp->bios_codeseg << 4);
13982 * Register Board Resources - I/O Port, DMA, IRQ
13985 /* Register DMA Channel for Narrow boards. */
13986 shost->dma_channel = NO_ISA_DMA; /* Default to no ISA DMA. */
13988 if (ASC_NARROW_BOARD(boardp)) {
13989 /* Register DMA channel for ISA bus. */
13990 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
13991 shost->dma_channel = asc_dvc_varp->cfg->isa_dma_channel;
13992 ret = request_dma(shost->dma_channel, DRV_NAME);
13994 shost_printk(KERN_ERR, shost, "request_dma() "
13996 shost->dma_channel, ret);
13997 goto err_free_proc;
13999 AscEnableIsaDma(shost->dma_channel);
14002 #endif /* CONFIG_ISA */
14004 /* Register IRQ Number. */
14005 ASC_DBG(2, "request_irq(%d, %p)\n", boardp->irq, shost);
14007 ret = request_irq(boardp->irq, advansys_interrupt, share_irq,
14011 if (ret == -EBUSY) {
14012 shost_printk(KERN_ERR, shost, "request_irq(): IRQ 0x%x "
14013 "already in use\n", boardp->irq);
14014 } else if (ret == -EINVAL) {
14015 shost_printk(KERN_ERR, shost, "request_irq(): IRQ 0x%x "
14016 "not valid\n", boardp->irq);
14018 shost_printk(KERN_ERR, shost, "request_irq(): IRQ 0x%x "
14019 "failed with %d\n", boardp->irq, ret);
14025 * Initialize board RISC chip and enable interrupts.
14027 if (ASC_NARROW_BOARD(boardp)) {
14028 ASC_DBG(2, "AscInitAsc1000Driver()\n");
14029 warn_code = AscInitAsc1000Driver(asc_dvc_varp);
14031 if (warn_code || asc_dvc_varp->err_code) {
14032 shost_printk(KERN_ERR, shost, "error: init_state 0x%x, "
14033 "warn 0x%x, error 0x%x\n",
14034 asc_dvc_varp->init_state, warn_code,
14035 asc_dvc_varp->err_code);
14036 if (asc_dvc_varp->err_code)
14040 if (advansys_wide_init_chip(shost))
14045 goto err_free_wide_mem;
14047 ASC_DBG_PRT_SCSI_HOST(2, shost);
14049 ret = scsi_add_host(shost, boardp->dev);
14051 goto err_free_wide_mem;
14053 scsi_scan_host(shost);
14057 advansys_wide_free_mem(boardp);
14058 free_irq(boardp->irq, shost);
14060 if (shost->dma_channel != NO_ISA_DMA)
14061 free_dma(shost->dma_channel);
14063 kfree(boardp->prtbuf);
14065 if (boardp->ioremap_addr)
14066 iounmap(boardp->ioremap_addr);
14072 * advansys_release()
14074 * Release resources allocated for a single AdvanSys adapter.
14076 static int advansys_release(struct Scsi_Host *shost)
14078 struct asc_board *boardp = shost_priv(shost);
14079 ASC_DBG(1, "begin\n");
14080 scsi_remove_host(shost);
14081 free_irq(boardp->irq, shost);
14082 if (shost->dma_channel != NO_ISA_DMA) {
14083 ASC_DBG(1, "free_dma()\n");
14084 free_dma(shost->dma_channel);
14086 if (!ASC_NARROW_BOARD(boardp)) {
14087 iounmap(boardp->ioremap_addr);
14088 advansys_wide_free_mem(boardp);
14090 kfree(boardp->prtbuf);
14091 scsi_host_put(shost);
14092 ASC_DBG(1, "end\n");
14096 #define ASC_IOADR_TABLE_MAX_IX 11
14098 static PortAddr _asc_def_iop_base[ASC_IOADR_TABLE_MAX_IX] __devinitdata = {
14099 0x100, 0x0110, 0x120, 0x0130, 0x140, 0x0150, 0x0190,
14100 0x0210, 0x0230, 0x0250, 0x0330
14104 * The ISA IRQ number is found in bits 2 and 3 of the CfgLsw. It decodes as:
14110 static unsigned int __devinit advansys_isa_irq_no(PortAddr iop_base)
14112 unsigned short cfg_lsw = AscGetChipCfgLsw(iop_base);
14113 unsigned int chip_irq = ((cfg_lsw >> 2) & 0x03) + 10;
14114 if (chip_irq == 13)
14119 static int __devinit advansys_isa_probe(struct device *dev, unsigned int id)
14122 PortAddr iop_base = _asc_def_iop_base[id];
14123 struct Scsi_Host *shost;
14124 struct asc_board *board;
14126 if (!request_region(iop_base, ASC_IOADR_GAP, DRV_NAME)) {
14127 ASC_DBG(1, "I/O port 0x%x busy\n", iop_base);
14130 ASC_DBG(1, "probing I/O port 0x%x\n", iop_base);
14131 if (!AscFindSignature(iop_base))
14132 goto release_region;
14133 if (!(AscGetChipVersion(iop_base, ASC_IS_ISA) & ASC_CHIP_VER_ISA_BIT))
14134 goto release_region;
14137 shost = scsi_host_alloc(&advansys_template, sizeof(*board));
14139 goto release_region;
14141 board = shost_priv(shost);
14142 board->irq = advansys_isa_irq_no(iop_base);
14145 err = advansys_board_found(shost, iop_base, ASC_IS_ISA);
14149 dev_set_drvdata(dev, shost);
14153 scsi_host_put(shost);
14155 release_region(iop_base, ASC_IOADR_GAP);
14159 static int __devexit advansys_isa_remove(struct device *dev, unsigned int id)
14161 int ioport = _asc_def_iop_base[id];
14162 advansys_release(dev_get_drvdata(dev));
14163 release_region(ioport, ASC_IOADR_GAP);
14167 static struct isa_driver advansys_isa_driver = {
14168 .probe = advansys_isa_probe,
14169 .remove = __devexit_p(advansys_isa_remove),
14171 .owner = THIS_MODULE,
14177 * The VLB IRQ number is found in bits 2 to 4 of the CfgLsw. It decodes as:
14187 static unsigned int __devinit advansys_vlb_irq_no(PortAddr iop_base)
14189 unsigned short cfg_lsw = AscGetChipCfgLsw(iop_base);
14190 unsigned int chip_irq = ((cfg_lsw >> 2) & 0x07) + 9;
14191 if ((chip_irq < 10) || (chip_irq == 13) || (chip_irq > 15))
14196 static int __devinit advansys_vlb_probe(struct device *dev, unsigned int id)
14199 PortAddr iop_base = _asc_def_iop_base[id];
14200 struct Scsi_Host *shost;
14201 struct asc_board *board;
14203 if (!request_region(iop_base, ASC_IOADR_GAP, DRV_NAME)) {
14204 ASC_DBG(1, "I/O port 0x%x busy\n", iop_base);
14207 ASC_DBG(1, "probing I/O port 0x%x\n", iop_base);
14208 if (!AscFindSignature(iop_base))
14209 goto release_region;
14211 * I don't think this condition can actually happen, but the old
14212 * driver did it, and the chances of finding a VLB setup in 2007
14213 * to do testing with is slight to none.
14215 if (AscGetChipVersion(iop_base, ASC_IS_VL) > ASC_CHIP_MAX_VER_VL)
14216 goto release_region;
14219 shost = scsi_host_alloc(&advansys_template, sizeof(*board));
14221 goto release_region;
14223 board = shost_priv(shost);
14224 board->irq = advansys_vlb_irq_no(iop_base);
14227 err = advansys_board_found(shost, iop_base, ASC_IS_VL);
14231 dev_set_drvdata(dev, shost);
14235 scsi_host_put(shost);
14237 release_region(iop_base, ASC_IOADR_GAP);
14241 static struct isa_driver advansys_vlb_driver = {
14242 .probe = advansys_vlb_probe,
14243 .remove = __devexit_p(advansys_isa_remove),
14245 .owner = THIS_MODULE,
14246 .name = "advansys_vlb",
14250 static struct eisa_device_id advansys_eisa_table[] __devinitdata = {
14256 MODULE_DEVICE_TABLE(eisa, advansys_eisa_table);
14259 * EISA is a little more tricky than PCI; each EISA device may have two
14260 * channels, and this driver is written to make each channel its own Scsi_Host
14262 struct eisa_scsi_data {
14263 struct Scsi_Host *host[2];
14267 * The EISA IRQ number is found in bits 8 to 10 of the CfgLsw. It decodes as:
14277 static unsigned int __devinit advansys_eisa_irq_no(struct eisa_device *edev)
14279 unsigned short cfg_lsw = inw(edev->base_addr + 0xc86);
14280 unsigned int chip_irq = ((cfg_lsw >> 8) & 0x07) + 10;
14281 if ((chip_irq == 13) || (chip_irq > 15))
14286 static int __devinit advansys_eisa_probe(struct device *dev)
14288 int i, ioport, irq = 0;
14290 struct eisa_device *edev = to_eisa_device(dev);
14291 struct eisa_scsi_data *data;
14294 data = kzalloc(sizeof(*data), GFP_KERNEL);
14297 ioport = edev->base_addr + 0xc30;
14300 for (i = 0; i < 2; i++, ioport += 0x20) {
14301 struct asc_board *board;
14302 struct Scsi_Host *shost;
14303 if (!request_region(ioport, ASC_IOADR_GAP, DRV_NAME)) {
14304 printk(KERN_WARNING "Region %x-%x busy\n", ioport,
14305 ioport + ASC_IOADR_GAP - 1);
14308 if (!AscFindSignature(ioport)) {
14309 release_region(ioport, ASC_IOADR_GAP);
14314 * I don't know why we need to do this for EISA chips, but
14315 * not for any others. It looks to be equivalent to
14316 * AscGetChipCfgMsw, but I may have overlooked something,
14317 * so I'm not converting it until I get an EISA board to
14323 irq = advansys_eisa_irq_no(edev);
14326 shost = scsi_host_alloc(&advansys_template, sizeof(*board));
14328 goto release_region;
14330 board = shost_priv(shost);
14334 err = advansys_board_found(shost, ioport, ASC_IS_EISA);
14336 data->host[i] = shost;
14340 scsi_host_put(shost);
14342 release_region(ioport, ASC_IOADR_GAP);
14348 dev_set_drvdata(dev, data);
14352 kfree(data->host[0]);
14353 kfree(data->host[1]);
14359 static __devexit int advansys_eisa_remove(struct device *dev)
14362 struct eisa_scsi_data *data = dev_get_drvdata(dev);
14364 for (i = 0; i < 2; i++) {
14366 struct Scsi_Host *shost = data->host[i];
14369 ioport = shost->io_port;
14370 advansys_release(shost);
14371 release_region(ioport, ASC_IOADR_GAP);
14378 static struct eisa_driver advansys_eisa_driver = {
14379 .id_table = advansys_eisa_table,
14382 .probe = advansys_eisa_probe,
14383 .remove = __devexit_p(advansys_eisa_remove),
14387 /* PCI Devices supported by this driver */
14388 static struct pci_device_id advansys_pci_tbl[] __devinitdata = {
14389 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_1200A,
14390 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
14391 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940,
14392 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
14393 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940U,
14394 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
14395 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940UW,
14396 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
14397 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_38C0800_REV1,
14398 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
14399 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_38C1600_REV1,
14400 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
14404 MODULE_DEVICE_TABLE(pci, advansys_pci_tbl);
14406 static void __devinit advansys_set_latency(struct pci_dev *pdev)
14408 if ((pdev->device == PCI_DEVICE_ID_ASP_1200A) ||
14409 (pdev->device == PCI_DEVICE_ID_ASP_ABP940)) {
14410 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0);
14413 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &latency);
14414 if (latency < 0x20)
14415 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x20);
14419 static int __devinit
14420 advansys_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
14423 struct Scsi_Host *shost;
14424 struct asc_board *board;
14426 err = pci_enable_device(pdev);
14429 err = pci_request_regions(pdev, DRV_NAME);
14431 goto disable_device;
14432 pci_set_master(pdev);
14433 advansys_set_latency(pdev);
14436 if (pci_resource_len(pdev, 0) == 0)
14437 goto release_region;
14439 ioport = pci_resource_start(pdev, 0);
14442 shost = scsi_host_alloc(&advansys_template, sizeof(*board));
14444 goto release_region;
14446 board = shost_priv(shost);
14447 board->irq = pdev->irq;
14448 board->dev = &pdev->dev;
14450 if (pdev->device == PCI_DEVICE_ID_ASP_ABP940UW ||
14451 pdev->device == PCI_DEVICE_ID_38C0800_REV1 ||
14452 pdev->device == PCI_DEVICE_ID_38C1600_REV1) {
14453 board->flags |= ASC_IS_WIDE_BOARD;
14456 err = advansys_board_found(shost, ioport, ASC_IS_PCI);
14460 pci_set_drvdata(pdev, shost);
14464 scsi_host_put(shost);
14466 pci_release_regions(pdev);
14468 pci_disable_device(pdev);
14473 static void __devexit advansys_pci_remove(struct pci_dev *pdev)
14475 advansys_release(pci_get_drvdata(pdev));
14476 pci_release_regions(pdev);
14477 pci_disable_device(pdev);
14480 static struct pci_driver advansys_pci_driver = {
14482 .id_table = advansys_pci_tbl,
14483 .probe = advansys_pci_probe,
14484 .remove = __devexit_p(advansys_pci_remove),
14487 static int __init advansys_init(void)
14491 error = isa_register_driver(&advansys_isa_driver,
14492 ASC_IOADR_TABLE_MAX_IX);
14496 error = isa_register_driver(&advansys_vlb_driver,
14497 ASC_IOADR_TABLE_MAX_IX);
14499 goto unregister_isa;
14501 error = eisa_driver_register(&advansys_eisa_driver);
14503 goto unregister_vlb;
14505 error = pci_register_driver(&advansys_pci_driver);
14507 goto unregister_eisa;
14512 eisa_driver_unregister(&advansys_eisa_driver);
14514 isa_unregister_driver(&advansys_vlb_driver);
14516 isa_unregister_driver(&advansys_isa_driver);
14521 static void __exit advansys_exit(void)
14523 pci_unregister_driver(&advansys_pci_driver);
14524 eisa_driver_unregister(&advansys_eisa_driver);
14525 isa_unregister_driver(&advansys_vlb_driver);
14526 isa_unregister_driver(&advansys_isa_driver);
14529 module_init(advansys_init);
14530 module_exit(advansys_exit);
14532 MODULE_LICENSE("GPL");