2 * ahci.c - AHCI SATA support
4 * Copyright 2004 Red Hat, Inc.
6 * The contents of this file are subject to the Open
7 * Software License version 1.1 that can be found at
8 * http://www.opensource.org/licenses/osl-1.1.txt and is included herein
11 * Alternatively, the contents of this file may be used under the terms
12 * of the GNU General Public License version 2 (the "GPL") as distributed
13 * in the kernel source COPYING file, in which case the provisions of
14 * the GPL are applicable instead of the above. If you wish to allow
15 * the use of your version of this file only under the terms of the
16 * GPL and not to allow others to use your version of this file under
17 * the OSL, indicate your decision by deleting the provisions above and
18 * replace them with the notice and other provisions required by the GPL.
19 * If you do not delete the provisions above, a recipient may use your
20 * version of this file under either the OSL or the GPL.
22 * Version 1.0 of the AHCI specification:
23 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/pci.h>
30 #include <linux/init.h>
31 #include <linux/blkdev.h>
32 #include <linux/delay.h>
33 #include <linux/interrupt.h>
34 #include <linux/sched.h>
35 #include <linux/dma-mapping.h>
37 #include <scsi/scsi_host.h>
38 #include <linux/libata.h>
41 #define DRV_NAME "ahci"
42 #define DRV_VERSION "1.01"
47 AHCI_MAX_SG = 168, /* hardware max is 64K */
48 AHCI_DMA_BOUNDARY = 0xffffffff,
49 AHCI_USE_CLUSTERING = 0,
50 AHCI_CMD_SLOT_SZ = 32 * 32,
52 AHCI_CMD_TBL_HDR = 0x80,
53 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR + (AHCI_MAX_SG * 16),
54 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_SZ +
56 AHCI_IRQ_ON_SG = (1 << 31),
57 AHCI_CMD_ATAPI = (1 << 5),
58 AHCI_CMD_WRITE = (1 << 6),
60 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
64 /* global controller registers */
65 HOST_CAP = 0x00, /* host capabilities */
66 HOST_CTL = 0x04, /* global host control */
67 HOST_IRQ_STAT = 0x08, /* interrupt status */
68 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
69 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
72 HOST_RESET = (1 << 0), /* reset controller; self-clear */
73 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
74 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
77 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
79 /* registers for each SATA port */
80 PORT_LST_ADDR = 0x00, /* command list DMA addr */
81 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
82 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
83 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
84 PORT_IRQ_STAT = 0x10, /* interrupt status */
85 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
86 PORT_CMD = 0x18, /* port command */
87 PORT_TFDATA = 0x20, /* taskfile data */
88 PORT_SIG = 0x24, /* device TF signature */
89 PORT_CMD_ISSUE = 0x38, /* command issue */
90 PORT_SCR = 0x28, /* SATA phy register block */
91 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
92 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
93 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
94 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
96 /* PORT_IRQ_{STAT,MASK} bits */
97 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
98 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
99 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
100 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
101 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
102 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
103 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
104 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
106 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
107 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
108 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
109 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
110 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
111 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
112 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
113 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
114 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
116 PORT_IRQ_FATAL = PORT_IRQ_TF_ERR |
118 PORT_IRQ_HBUS_DATA_ERR |
120 DEF_PORT_IRQ = PORT_IRQ_FATAL | PORT_IRQ_PHYRDY |
121 PORT_IRQ_CONNECT | PORT_IRQ_SG_DONE |
122 PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_FIS |
123 PORT_IRQ_DMAS_FIS | PORT_IRQ_PIOS_FIS |
124 PORT_IRQ_D2H_REG_FIS,
127 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
128 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
129 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
130 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
131 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
132 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
134 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
135 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
136 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
138 /* hpriv->flags bits */
139 AHCI_FLAG_MSI = (1 << 0),
142 struct ahci_cmd_hdr {
157 struct ahci_host_priv {
159 u32 cap; /* cache of HOST_CAP register */
160 u32 port_map; /* cache of HOST_PORTS_IMPL reg */
163 struct ahci_port_priv {
164 struct ahci_cmd_hdr *cmd_slot;
165 dma_addr_t cmd_slot_dma;
167 dma_addr_t cmd_tbl_dma;
168 struct ahci_sg *cmd_tbl_sg;
170 dma_addr_t rx_fis_dma;
173 static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg);
174 static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
175 static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
176 static int ahci_qc_issue(struct ata_queued_cmd *qc);
177 static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
178 static void ahci_phy_reset(struct ata_port *ap);
179 static void ahci_irq_clear(struct ata_port *ap);
180 static void ahci_eng_timeout(struct ata_port *ap);
181 static int ahci_port_start(struct ata_port *ap);
182 static void ahci_port_stop(struct ata_port *ap);
183 static void ahci_host_stop(struct ata_host_set *host_set);
184 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
185 static void ahci_qc_prep(struct ata_queued_cmd *qc);
186 static u8 ahci_check_status(struct ata_port *ap);
187 static u8 ahci_check_err(struct ata_port *ap);
188 static inline int ahci_host_intr(struct ata_port *ap, struct ata_queued_cmd *qc);
189 static void ahci_remove_one (struct pci_dev *pdev);
191 static Scsi_Host_Template ahci_sht = {
192 .module = THIS_MODULE,
194 .ioctl = ata_scsi_ioctl,
195 .queuecommand = ata_scsi_queuecmd,
196 .eh_strategy_handler = ata_scsi_error,
197 .can_queue = ATA_DEF_QUEUE,
198 .this_id = ATA_SHT_THIS_ID,
199 .sg_tablesize = AHCI_MAX_SG,
200 .max_sectors = ATA_MAX_SECTORS,
201 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
202 .emulated = ATA_SHT_EMULATED,
203 .use_clustering = AHCI_USE_CLUSTERING,
204 .proc_name = DRV_NAME,
205 .dma_boundary = AHCI_DMA_BOUNDARY,
206 .slave_configure = ata_scsi_slave_config,
207 .bios_param = ata_std_bios_param,
211 static struct ata_port_operations ahci_ops = {
212 .port_disable = ata_port_disable,
214 .check_status = ahci_check_status,
215 .check_altstatus = ahci_check_status,
216 .check_err = ahci_check_err,
217 .dev_select = ata_noop_dev_select,
219 .tf_read = ahci_tf_read,
221 .phy_reset = ahci_phy_reset,
223 .qc_prep = ahci_qc_prep,
224 .qc_issue = ahci_qc_issue,
226 .eng_timeout = ahci_eng_timeout,
228 .irq_handler = ahci_interrupt,
229 .irq_clear = ahci_irq_clear,
231 .scr_read = ahci_scr_read,
232 .scr_write = ahci_scr_write,
234 .port_start = ahci_port_start,
235 .port_stop = ahci_port_stop,
236 .host_stop = ahci_host_stop,
239 static struct ata_port_info ahci_port_info[] = {
243 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
244 ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO |
246 .pio_mask = 0x03, /* pio3-4 */
247 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
248 .port_ops = &ahci_ops,
252 static struct pci_device_id ahci_pci_tbl[] = {
253 { PCI_VENDOR_ID_INTEL, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
254 board_ahci }, /* ICH6 */
255 { PCI_VENDOR_ID_INTEL, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
256 board_ahci }, /* ICH6M */
257 { PCI_VENDOR_ID_INTEL, 0x27c1, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
258 board_ahci }, /* ICH7 */
259 { PCI_VENDOR_ID_INTEL, 0x27c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
260 board_ahci }, /* ICH7M */
261 { PCI_VENDOR_ID_INTEL, 0x27c3, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
262 board_ahci }, /* ICH7R */
263 { PCI_VENDOR_ID_AL, 0x5288, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
264 board_ahci }, /* ULi M5288 */
265 { PCI_VENDOR_ID_INTEL, 0x2681, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
266 board_ahci }, /* ESB2 */
267 { PCI_VENDOR_ID_INTEL, 0x2682, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
268 board_ahci }, /* ESB2 */
269 { PCI_VENDOR_ID_INTEL, 0x2683, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
270 board_ahci }, /* ESB2 */
271 { } /* terminate list */
275 static struct pci_driver ahci_pci_driver = {
277 .id_table = ahci_pci_tbl,
278 .probe = ahci_init_one,
279 .remove = ahci_remove_one,
283 static inline unsigned long ahci_port_base_ul (unsigned long base, unsigned int port)
285 return base + 0x100 + (port * 0x80);
288 static inline void *ahci_port_base (void *base, unsigned int port)
290 return (void *) ahci_port_base_ul((unsigned long)base, port);
293 static void ahci_host_stop(struct ata_host_set *host_set)
295 struct ahci_host_priv *hpriv = host_set->private_data;
298 ata_host_stop(host_set);
301 static int ahci_port_start(struct ata_port *ap)
303 struct device *dev = ap->host_set->dev;
304 struct ahci_host_priv *hpriv = ap->host_set->private_data;
305 struct ahci_port_priv *pp;
307 void *mem, *mmio = ap->host_set->mmio_base;
308 void *port_mmio = ahci_port_base(mmio, ap->port_no);
311 rc = ata_port_start(ap);
315 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
320 memset(pp, 0, sizeof(*pp));
322 mem = dma_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma, GFP_KERNEL);
327 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
330 * First item in chunk of DMA memory: 32-slot command table,
331 * 32 bytes each in size
334 pp->cmd_slot_dma = mem_dma;
336 mem += AHCI_CMD_SLOT_SZ;
337 mem_dma += AHCI_CMD_SLOT_SZ;
340 * Second item: Received-FIS area
343 pp->rx_fis_dma = mem_dma;
345 mem += AHCI_RX_FIS_SZ;
346 mem_dma += AHCI_RX_FIS_SZ;
349 * Third item: data area for storing a single command
350 * and its scatter-gather table
353 pp->cmd_tbl_dma = mem_dma;
355 pp->cmd_tbl_sg = mem + AHCI_CMD_TBL_HDR;
357 ap->private_data = pp;
359 if (hpriv->cap & HOST_CAP_64)
360 writel((pp->cmd_slot_dma >> 16) >> 16, port_mmio + PORT_LST_ADDR_HI);
361 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
362 readl(port_mmio + PORT_LST_ADDR); /* flush */
364 if (hpriv->cap & HOST_CAP_64)
365 writel((pp->rx_fis_dma >> 16) >> 16, port_mmio + PORT_FIS_ADDR_HI);
366 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
367 readl(port_mmio + PORT_FIS_ADDR); /* flush */
369 writel(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
370 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
371 PORT_CMD_START, port_mmio + PORT_CMD);
372 readl(port_mmio + PORT_CMD); /* flush */
384 static void ahci_port_stop(struct ata_port *ap)
386 struct device *dev = ap->host_set->dev;
387 struct ahci_port_priv *pp = ap->private_data;
388 void *mmio = ap->host_set->mmio_base;
389 void *port_mmio = ahci_port_base(mmio, ap->port_no);
392 tmp = readl(port_mmio + PORT_CMD);
393 tmp &= ~(PORT_CMD_START | PORT_CMD_FIS_RX);
394 writel(tmp, port_mmio + PORT_CMD);
395 readl(port_mmio + PORT_CMD); /* flush */
397 /* spec says 500 msecs for each PORT_CMD_{START,FIS_RX} bit, so
398 * this is slightly incorrect.
402 ap->private_data = NULL;
403 dma_free_coherent(dev, AHCI_PORT_PRIV_DMA_SZ,
404 pp->cmd_slot, pp->cmd_slot_dma);
409 static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in)
414 case SCR_STATUS: sc_reg = 0; break;
415 case SCR_CONTROL: sc_reg = 1; break;
416 case SCR_ERROR: sc_reg = 2; break;
417 case SCR_ACTIVE: sc_reg = 3; break;
422 return readl((void *) ap->ioaddr.scr_addr + (sc_reg * 4));
426 static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in,
432 case SCR_STATUS: sc_reg = 0; break;
433 case SCR_CONTROL: sc_reg = 1; break;
434 case SCR_ERROR: sc_reg = 2; break;
435 case SCR_ACTIVE: sc_reg = 3; break;
440 writel(val, (void *) ap->ioaddr.scr_addr + (sc_reg * 4));
443 static void ahci_phy_reset(struct ata_port *ap)
445 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
446 struct ata_taskfile tf;
447 struct ata_device *dev = &ap->device[0];
450 __sata_phy_reset(ap);
452 if (ap->flags & ATA_FLAG_PORT_DISABLED)
455 tmp = readl(port_mmio + PORT_SIG);
456 tf.lbah = (tmp >> 24) & 0xff;
457 tf.lbam = (tmp >> 16) & 0xff;
458 tf.lbal = (tmp >> 8) & 0xff;
459 tf.nsect = (tmp) & 0xff;
461 dev->class = ata_dev_classify(&tf);
462 if (!ata_dev_present(dev))
463 ata_port_disable(ap);
466 static u8 ahci_check_status(struct ata_port *ap)
468 void *mmio = (void *) ap->ioaddr.cmd_addr;
470 return readl(mmio + PORT_TFDATA) & 0xFF;
473 static u8 ahci_check_err(struct ata_port *ap)
475 void *mmio = (void *) ap->ioaddr.cmd_addr;
477 return (readl(mmio + PORT_TFDATA) >> 8) & 0xFF;
480 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
482 struct ahci_port_priv *pp = ap->private_data;
483 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
485 ata_tf_from_fis(d2h_fis, tf);
488 static void ahci_fill_sg(struct ata_queued_cmd *qc)
490 struct ahci_port_priv *pp = qc->ap->private_data;
496 * Next, the S/G list.
498 for (i = 0; i < qc->n_elem; i++) {
502 addr = sg_dma_address(&qc->sg[i]);
503 sg_len = sg_dma_len(&qc->sg[i]);
505 pp->cmd_tbl_sg[i].addr = cpu_to_le32(addr & 0xffffffff);
506 pp->cmd_tbl_sg[i].addr_hi = cpu_to_le32((addr >> 16) >> 16);
507 pp->cmd_tbl_sg[i].flags_size = cpu_to_le32(sg_len - 1);
511 static void ahci_qc_prep(struct ata_queued_cmd *qc)
513 struct ahci_port_priv *pp = qc->ap->private_data;
515 const u32 cmd_fis_len = 5; /* five dwords */
518 * Fill in command slot information (currently only one slot,
519 * slot 0, is currently since we don't do queueing)
522 opts = (qc->n_elem << 16) | cmd_fis_len;
523 if (qc->tf.flags & ATA_TFLAG_WRITE)
524 opts |= AHCI_CMD_WRITE;
526 switch (qc->tf.protocol) {
528 case ATA_PROT_ATAPI_NODATA:
529 case ATA_PROT_ATAPI_DMA:
530 opts |= AHCI_CMD_ATAPI;
538 pp->cmd_slot[0].opts = cpu_to_le32(opts);
539 pp->cmd_slot[0].status = 0;
540 pp->cmd_slot[0].tbl_addr = cpu_to_le32(pp->cmd_tbl_dma & 0xffffffff);
541 pp->cmd_slot[0].tbl_addr_hi = cpu_to_le32((pp->cmd_tbl_dma >> 16) >> 16);
544 * Fill in command table information. First, the header,
545 * a SATA Register - Host to Device command FIS.
547 ata_tf_to_fis(&qc->tf, pp->cmd_tbl, 0);
549 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
555 static void ahci_intr_error(struct ata_port *ap, u32 irq_stat)
557 void *mmio = ap->host_set->mmio_base;
558 void *port_mmio = ahci_port_base(mmio, ap->port_no);
563 tmp = readl(port_mmio + PORT_CMD);
564 tmp &= ~PORT_CMD_START;
565 writel(tmp, port_mmio + PORT_CMD);
567 /* wait for engine to stop. TODO: this could be
568 * as long as 500 msec
572 tmp = readl(port_mmio + PORT_CMD);
573 if ((tmp & PORT_CMD_LIST_ON) == 0)
578 /* clear SATA phy error, if any */
579 tmp = readl(port_mmio + PORT_SCR_ERR);
580 writel(tmp, port_mmio + PORT_SCR_ERR);
582 /* if DRQ/BSY is set, device needs to be reset.
583 * if so, issue COMRESET
585 tmp = readl(port_mmio + PORT_TFDATA);
586 if (tmp & (ATA_BUSY | ATA_DRQ)) {
587 writel(0x301, port_mmio + PORT_SCR_CTL);
588 readl(port_mmio + PORT_SCR_CTL); /* flush */
590 writel(0x300, port_mmio + PORT_SCR_CTL);
591 readl(port_mmio + PORT_SCR_CTL); /* flush */
595 tmp = readl(port_mmio + PORT_CMD);
596 tmp |= PORT_CMD_START;
597 writel(tmp, port_mmio + PORT_CMD);
598 readl(port_mmio + PORT_CMD); /* flush */
600 printk(KERN_WARNING "ata%u: error occurred, port reset\n", ap->id);
603 static void ahci_eng_timeout(struct ata_port *ap)
605 void *mmio = ap->host_set->mmio_base;
606 void *port_mmio = ahci_port_base(mmio, ap->port_no);
607 struct ata_queued_cmd *qc;
611 ahci_intr_error(ap, readl(port_mmio + PORT_IRQ_STAT));
613 qc = ata_qc_from_tag(ap, ap->active_tag);
615 printk(KERN_ERR "ata%u: BUG: timeout without command\n",
618 /* hack alert! We cannot use the supplied completion
619 * function from inside the ->eh_strategy_handler() thread.
620 * libata is the only user of ->eh_strategy_handler() in
621 * any kernel, so the default scsi_done() assumes it is
622 * not being called from the SCSI EH.
624 qc->scsidone = scsi_finish_command;
625 ata_qc_complete(qc, ATA_ERR);
630 static inline int ahci_host_intr(struct ata_port *ap, struct ata_queued_cmd *qc)
632 void *mmio = ap->host_set->mmio_base;
633 void *port_mmio = ahci_port_base(mmio, ap->port_no);
634 u32 status, serr, ci;
636 serr = readl(port_mmio + PORT_SCR_ERR);
637 writel(serr, port_mmio + PORT_SCR_ERR);
639 status = readl(port_mmio + PORT_IRQ_STAT);
640 writel(status, port_mmio + PORT_IRQ_STAT);
642 ci = readl(port_mmio + PORT_CMD_ISSUE);
643 if (likely((ci & 0x1) == 0)) {
645 ata_qc_complete(qc, 0);
650 if (status & PORT_IRQ_FATAL) {
651 ahci_intr_error(ap, status);
653 ata_qc_complete(qc, ATA_ERR);
659 static void ahci_irq_clear(struct ata_port *ap)
664 static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
666 struct ata_host_set *host_set = dev_instance;
667 struct ahci_host_priv *hpriv;
668 unsigned int i, handled = 0;
670 u32 irq_stat, irq_ack = 0;
674 hpriv = host_set->private_data;
675 mmio = host_set->mmio_base;
677 /* sigh. 0xffffffff is a valid return from h/w */
678 irq_stat = readl(mmio + HOST_IRQ_STAT);
679 irq_stat &= hpriv->port_map;
683 spin_lock(&host_set->lock);
685 for (i = 0; i < host_set->n_ports; i++) {
689 VPRINTK("port %u\n", i);
690 ap = host_set->ports[i];
691 tmp = irq_stat & (1 << i);
693 struct ata_queued_cmd *qc;
694 qc = ata_qc_from_tag(ap, ap->active_tag);
695 if (ahci_host_intr(ap, qc))
701 writel(irq_ack, mmio + HOST_IRQ_STAT);
705 spin_unlock(&host_set->lock);
709 return IRQ_RETVAL(handled);
712 static int ahci_qc_issue(struct ata_queued_cmd *qc)
714 struct ata_port *ap = qc->ap;
715 void *port_mmio = (void *) ap->ioaddr.cmd_addr;
717 writel(1, port_mmio + PORT_SCR_ACT);
718 readl(port_mmio + PORT_SCR_ACT); /* flush */
720 writel(1, port_mmio + PORT_CMD_ISSUE);
721 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
726 static void ahci_setup_port(struct ata_ioports *port, unsigned long base,
727 unsigned int port_idx)
729 VPRINTK("ENTER, base==0x%lx, port_idx %u\n", base, port_idx);
730 base = ahci_port_base_ul(base, port_idx);
731 VPRINTK("base now==0x%lx\n", base);
733 port->cmd_addr = base;
734 port->scr_addr = base + PORT_SCR;
739 static int ahci_host_init(struct ata_probe_ent *probe_ent)
741 struct ahci_host_priv *hpriv = probe_ent->private_data;
742 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
743 void __iomem *mmio = probe_ent->mmio_base;
746 unsigned int i, j, using_dac;
748 void __iomem *port_mmio;
750 cap_save = readl(mmio + HOST_CAP);
751 cap_save &= ( (1<<28) | (1<<17) );
752 cap_save |= (1 << 27);
754 /* global controller reset */
755 tmp = readl(mmio + HOST_CTL);
756 if ((tmp & HOST_RESET) == 0) {
757 writel(tmp | HOST_RESET, mmio + HOST_CTL);
758 readl(mmio + HOST_CTL); /* flush */
761 /* reset must complete within 1 second, or
762 * the hardware should be considered fried.
766 tmp = readl(mmio + HOST_CTL);
767 if (tmp & HOST_RESET) {
768 printk(KERN_ERR DRV_NAME "(%s): controller reset failed (0x%x)\n",
769 pci_name(pdev), tmp);
773 writel(HOST_AHCI_EN, mmio + HOST_CTL);
774 (void) readl(mmio + HOST_CTL); /* flush */
775 writel(cap_save, mmio + HOST_CAP);
776 writel(0xf, mmio + HOST_PORTS_IMPL);
777 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
779 pci_read_config_word(pdev, 0x92, &tmp16);
781 pci_write_config_word(pdev, 0x92, tmp16);
783 hpriv->cap = readl(mmio + HOST_CAP);
784 hpriv->port_map = readl(mmio + HOST_PORTS_IMPL);
785 probe_ent->n_ports = (hpriv->cap & 0x1f) + 1;
787 VPRINTK("cap 0x%x port_map 0x%x n_ports %d\n",
788 hpriv->cap, hpriv->port_map, probe_ent->n_ports);
790 using_dac = hpriv->cap & HOST_CAP_64;
792 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
793 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
795 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
797 printk(KERN_ERR DRV_NAME "(%s): 64-bit DMA enable failed\n",
803 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
805 printk(KERN_ERR DRV_NAME "(%s): 32-bit DMA enable failed\n",
809 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
811 printk(KERN_ERR DRV_NAME "(%s): 32-bit consistent DMA enable failed\n",
817 for (i = 0; i < probe_ent->n_ports; i++) {
818 #if 0 /* BIOSen initialize this incorrectly */
819 if (!(hpriv->port_map & (1 << i)))
823 port_mmio = ahci_port_base(mmio, i);
824 VPRINTK("mmio %p port_mmio %p\n", mmio, port_mmio);
826 ahci_setup_port(&probe_ent->port[i],
827 (unsigned long) mmio, i);
829 /* make sure port is not active */
830 tmp = readl(port_mmio + PORT_CMD);
831 VPRINTK("PORT_CMD 0x%x\n", tmp);
832 if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
833 PORT_CMD_FIS_RX | PORT_CMD_START)) {
834 tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
835 PORT_CMD_FIS_RX | PORT_CMD_START);
836 writel(tmp, port_mmio + PORT_CMD);
837 readl(port_mmio + PORT_CMD); /* flush */
839 /* spec says 500 msecs for each bit, so
840 * this is slightly incorrect.
845 writel(PORT_CMD_SPIN_UP, port_mmio + PORT_CMD);
850 tmp = readl(port_mmio + PORT_SCR_STAT);
851 if ((tmp & 0xf) == 0x3)
856 tmp = readl(port_mmio + PORT_SCR_ERR);
857 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
858 writel(tmp, port_mmio + PORT_SCR_ERR);
860 /* ack any pending irq events for this port */
861 tmp = readl(port_mmio + PORT_IRQ_STAT);
862 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
864 writel(tmp, port_mmio + PORT_IRQ_STAT);
866 writel(1 << i, mmio + HOST_IRQ_STAT);
868 /* set irq mask (enables interrupts) */
869 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
872 tmp = readl(mmio + HOST_CTL);
873 VPRINTK("HOST_CTL 0x%x\n", tmp);
874 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
875 tmp = readl(mmio + HOST_CTL);
876 VPRINTK("HOST_CTL 0x%x\n", tmp);
878 pci_set_master(pdev);
883 /* move to PCI layer, integrate w/ MSI stuff */
884 static void pci_intx(struct pci_dev *pdev, int enable)
886 u16 pci_command, new;
888 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
891 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
893 new = pci_command | PCI_COMMAND_INTX_DISABLE;
895 if (new != pci_command)
896 pci_write_config_word(pdev, PCI_COMMAND, pci_command);
899 static void ahci_print_info(struct ata_probe_ent *probe_ent)
901 struct ahci_host_priv *hpriv = probe_ent->private_data;
902 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
903 void *mmio = probe_ent->mmio_base;
904 u32 vers, cap, impl, speed;
909 vers = readl(mmio + HOST_VERSION);
911 impl = hpriv->port_map;
913 speed = (cap >> 20) & 0xf;
921 pci_read_config_word(pdev, 0x0a, &cc);
924 else if (cc == 0x0106)
926 else if (cc == 0x0104)
931 printk(KERN_INFO DRV_NAME "(%s) AHCI %02x%02x.%02x%02x "
932 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
941 ((cap >> 8) & 0x1f) + 1,
947 printk(KERN_INFO DRV_NAME "(%s) flags: "
953 cap & (1 << 31) ? "64bit " : "",
954 cap & (1 << 30) ? "ncq " : "",
955 cap & (1 << 28) ? "ilck " : "",
956 cap & (1 << 27) ? "stag " : "",
957 cap & (1 << 26) ? "pm " : "",
958 cap & (1 << 25) ? "led " : "",
960 cap & (1 << 24) ? "clo " : "",
961 cap & (1 << 19) ? "nz " : "",
962 cap & (1 << 18) ? "only " : "",
963 cap & (1 << 17) ? "pmp " : "",
964 cap & (1 << 15) ? "pio " : "",
965 cap & (1 << 14) ? "slum " : "",
966 cap & (1 << 13) ? "part " : ""
970 static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
972 static int printed_version;
973 struct ata_probe_ent *probe_ent = NULL;
974 struct ahci_host_priv *hpriv;
977 unsigned int board_idx = (unsigned int) ent->driver_data;
978 int have_msi, pci_dev_busy = 0;
983 if (!printed_version++)
984 printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
986 rc = pci_enable_device(pdev);
990 rc = pci_request_regions(pdev, DRV_NAME);
996 if (pci_enable_msi(pdev) == 0)
1003 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
1004 if (probe_ent == NULL) {
1009 memset(probe_ent, 0, sizeof(*probe_ent));
1010 probe_ent->dev = pci_dev_to_dev(pdev);
1011 INIT_LIST_HEAD(&probe_ent->node);
1013 mmio_base = ioremap(pci_resource_start(pdev, AHCI_PCI_BAR),
1014 pci_resource_len(pdev, AHCI_PCI_BAR));
1015 if (mmio_base == NULL) {
1017 goto err_out_free_ent;
1019 base = (unsigned long) mmio_base;
1021 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
1024 goto err_out_iounmap;
1026 memset(hpriv, 0, sizeof(*hpriv));
1028 probe_ent->sht = ahci_port_info[board_idx].sht;
1029 probe_ent->host_flags = ahci_port_info[board_idx].host_flags;
1030 probe_ent->pio_mask = ahci_port_info[board_idx].pio_mask;
1031 probe_ent->udma_mask = ahci_port_info[board_idx].udma_mask;
1032 probe_ent->port_ops = ahci_port_info[board_idx].port_ops;
1034 probe_ent->irq = pdev->irq;
1035 probe_ent->irq_flags = SA_SHIRQ;
1036 probe_ent->mmio_base = mmio_base;
1037 probe_ent->private_data = hpriv;
1040 hpriv->flags |= AHCI_FLAG_MSI;
1042 /* initialize adapter */
1043 rc = ahci_host_init(probe_ent);
1047 ahci_print_info(probe_ent);
1049 /* FIXME: check ata_device_add return value */
1050 ata_device_add(probe_ent);
1063 pci_disable_msi(pdev);
1066 pci_release_regions(pdev);
1069 pci_disable_device(pdev);
1073 static void ahci_remove_one (struct pci_dev *pdev)
1075 struct device *dev = pci_dev_to_dev(pdev);
1076 struct ata_host_set *host_set = dev_get_drvdata(dev);
1077 struct ahci_host_priv *hpriv = host_set->private_data;
1078 struct ata_port *ap;
1082 for (i = 0; i < host_set->n_ports; i++) {
1083 ap = host_set->ports[i];
1085 scsi_remove_host(ap->host);
1088 have_msi = hpriv->flags & AHCI_FLAG_MSI;
1089 free_irq(host_set->irq, host_set);
1091 for (i = 0; i < host_set->n_ports; i++) {
1092 ap = host_set->ports[i];
1094 ata_scsi_release(ap->host);
1095 scsi_host_put(ap->host);
1098 host_set->ops->host_stop(host_set);
1102 pci_disable_msi(pdev);
1105 pci_release_regions(pdev);
1106 pci_disable_device(pdev);
1107 dev_set_drvdata(dev, NULL);
1110 static int __init ahci_init(void)
1112 return pci_module_init(&ahci_pci_driver);
1116 static void __exit ahci_exit(void)
1118 pci_unregister_driver(&ahci_pci_driver);
1122 MODULE_AUTHOR("Jeff Garzik");
1123 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1124 MODULE_LICENSE("GPL");
1125 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1127 module_init(ahci_init);
1128 module_exit(ahci_exit);