2 * ahci.c - AHCI SATA support
4 * Copyright 2004 Red Hat, Inc.
6 * The contents of this file are subject to the Open
7 * Software License version 1.1 that can be found at
8 * http://www.opensource.org/licenses/osl-1.1.txt and is included herein
11 * Alternatively, the contents of this file may be used under the terms
12 * of the GNU General Public License version 2 (the "GPL") as distributed
13 * in the kernel source COPYING file, in which case the provisions of
14 * the GPL are applicable instead of the above. If you wish to allow
15 * the use of your version of this file only under the terms of the
16 * GPL and not to allow others to use your version of this file under
17 * the OSL, indicate your decision by deleting the provisions above and
18 * replace them with the notice and other provisions required by the GPL.
19 * If you do not delete the provisions above, a recipient may use your
20 * version of this file under either the OSL or the GPL.
22 * Version 1.0 of the AHCI specification:
23 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/pci.h>
30 #include <linux/init.h>
31 #include <linux/blkdev.h>
32 #include <linux/delay.h>
33 #include <linux/interrupt.h>
34 #include <linux/sched.h>
36 #include <scsi/scsi_host.h>
37 #include <linux/libata.h>
40 #define DRV_NAME "ahci"
41 #define DRV_VERSION "1.00"
46 AHCI_MAX_SG = 168, /* hardware max is 64K */
47 AHCI_DMA_BOUNDARY = 0xffffffff,
48 AHCI_USE_CLUSTERING = 0,
49 AHCI_CMD_SLOT_SZ = 32 * 32,
51 AHCI_CMD_TBL_HDR = 0x80,
52 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR + (AHCI_MAX_SG * 16),
53 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_SZ +
55 AHCI_IRQ_ON_SG = (1 << 31),
56 AHCI_CMD_ATAPI = (1 << 5),
57 AHCI_CMD_WRITE = (1 << 6),
59 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
63 /* global controller registers */
64 HOST_CAP = 0x00, /* host capabilities */
65 HOST_CTL = 0x04, /* global host control */
66 HOST_IRQ_STAT = 0x08, /* interrupt status */
67 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
68 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
71 HOST_RESET = (1 << 0), /* reset controller; self-clear */
72 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
73 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
76 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
78 /* registers for each SATA port */
79 PORT_LST_ADDR = 0x00, /* command list DMA addr */
80 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
81 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
82 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
83 PORT_IRQ_STAT = 0x10, /* interrupt status */
84 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
85 PORT_CMD = 0x18, /* port command */
86 PORT_TFDATA = 0x20, /* taskfile data */
87 PORT_SIG = 0x24, /* device TF signature */
88 PORT_CMD_ISSUE = 0x38, /* command issue */
89 PORT_SCR = 0x28, /* SATA phy register block */
90 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
91 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
92 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
93 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
95 /* PORT_IRQ_{STAT,MASK} bits */
96 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
97 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
98 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
99 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
100 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
101 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
102 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
103 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
105 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
106 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
107 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
108 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
109 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
110 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
111 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
112 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
113 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
115 PORT_IRQ_FATAL = PORT_IRQ_TF_ERR |
117 PORT_IRQ_HBUS_DATA_ERR |
119 DEF_PORT_IRQ = PORT_IRQ_FATAL | PORT_IRQ_PHYRDY |
120 PORT_IRQ_CONNECT | PORT_IRQ_SG_DONE |
121 PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_FIS |
122 PORT_IRQ_DMAS_FIS | PORT_IRQ_PIOS_FIS |
123 PORT_IRQ_D2H_REG_FIS,
126 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
127 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
128 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
129 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
130 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
131 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
133 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
134 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
135 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
138 struct ahci_cmd_hdr {
153 struct ahci_host_priv {
155 unsigned int have_msi; /* is PCI MSI enabled? */
156 u32 cap; /* cache of HOST_CAP register */
157 u32 port_map; /* cache of HOST_PORTS_IMPL reg */
160 struct ahci_port_priv {
161 struct ahci_cmd_hdr *cmd_slot;
162 dma_addr_t cmd_slot_dma;
164 dma_addr_t cmd_tbl_dma;
165 struct ahci_sg *cmd_tbl_sg;
167 dma_addr_t rx_fis_dma;
170 static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg);
171 static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
172 static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
173 static int ahci_qc_issue(struct ata_queued_cmd *qc);
174 static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
175 static void ahci_phy_reset(struct ata_port *ap);
176 static void ahci_irq_clear(struct ata_port *ap);
177 static void ahci_eng_timeout(struct ata_port *ap);
178 static int ahci_port_start(struct ata_port *ap);
179 static void ahci_port_stop(struct ata_port *ap);
180 static void ahci_host_stop(struct ata_host_set *host_set);
181 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
182 static void ahci_qc_prep(struct ata_queued_cmd *qc);
183 static u8 ahci_check_status(struct ata_port *ap);
184 static u8 ahci_check_err(struct ata_port *ap);
185 static inline int ahci_host_intr(struct ata_port *ap, struct ata_queued_cmd *qc);
186 static void ahci_remove_one (struct pci_dev *pdev);
188 static Scsi_Host_Template ahci_sht = {
189 .module = THIS_MODULE,
191 .ioctl = ata_scsi_ioctl,
192 .queuecommand = ata_scsi_queuecmd,
193 .eh_strategy_handler = ata_scsi_error,
194 .can_queue = ATA_DEF_QUEUE,
195 .this_id = ATA_SHT_THIS_ID,
196 .sg_tablesize = AHCI_MAX_SG,
197 .max_sectors = ATA_MAX_SECTORS,
198 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
199 .emulated = ATA_SHT_EMULATED,
200 .use_clustering = AHCI_USE_CLUSTERING,
201 .proc_name = DRV_NAME,
202 .dma_boundary = AHCI_DMA_BOUNDARY,
203 .slave_configure = ata_scsi_slave_config,
204 .bios_param = ata_std_bios_param,
208 static struct ata_port_operations ahci_ops = {
209 .port_disable = ata_port_disable,
211 .check_status = ahci_check_status,
212 .check_altstatus = ahci_check_status,
213 .check_err = ahci_check_err,
214 .dev_select = ata_noop_dev_select,
216 .tf_read = ahci_tf_read,
218 .phy_reset = ahci_phy_reset,
220 .qc_prep = ahci_qc_prep,
221 .qc_issue = ahci_qc_issue,
223 .eng_timeout = ahci_eng_timeout,
225 .irq_handler = ahci_interrupt,
226 .irq_clear = ahci_irq_clear,
228 .scr_read = ahci_scr_read,
229 .scr_write = ahci_scr_write,
231 .port_start = ahci_port_start,
232 .port_stop = ahci_port_stop,
233 .host_stop = ahci_host_stop,
236 static struct ata_port_info ahci_port_info[] = {
240 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
241 ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO |
243 .pio_mask = 0x03, /* pio3-4 */
244 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
245 .port_ops = &ahci_ops,
249 static struct pci_device_id ahci_pci_tbl[] = {
250 { PCI_VENDOR_ID_INTEL, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
251 board_ahci }, /* ICH6 */
252 { PCI_VENDOR_ID_INTEL, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
253 board_ahci }, /* ICH6M */
254 { PCI_VENDOR_ID_INTEL, 0x27c1, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
255 board_ahci }, /* ICH7 */
256 { PCI_VENDOR_ID_INTEL, 0x27c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
257 board_ahci }, /* ICH7M */
258 { PCI_VENDOR_ID_INTEL, 0x27c3, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
259 board_ahci }, /* ICH7R */
260 { PCI_VENDOR_ID_AL, 0x5288, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
261 board_ahci }, /* ULi M5288 */
262 { PCI_VENDOR_ID_INTEL, 0x2681, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
263 board_ahci }, /* ESB2 */
264 { PCI_VENDOR_ID_INTEL, 0x2682, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
265 board_ahci }, /* ESB2 */
266 { PCI_VENDOR_ID_INTEL, 0x2683, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
267 board_ahci }, /* ESB2 */
268 { } /* terminate list */
272 static struct pci_driver ahci_pci_driver = {
274 .id_table = ahci_pci_tbl,
275 .probe = ahci_init_one,
276 .remove = ahci_remove_one,
280 static inline unsigned long ahci_port_base_ul (unsigned long base, unsigned int port)
282 return base + 0x100 + (port * 0x80);
285 static inline void *ahci_port_base (void *base, unsigned int port)
287 return (void *) ahci_port_base_ul((unsigned long)base, port);
290 static void ahci_host_stop(struct ata_host_set *host_set)
292 struct ahci_host_priv *hpriv = host_set->private_data;
296 static int ahci_port_start(struct ata_port *ap)
298 struct device *dev = ap->host_set->dev;
299 struct ahci_host_priv *hpriv = ap->host_set->private_data;
300 struct ahci_port_priv *pp;
302 void *mem, *mmio = ap->host_set->mmio_base;
303 void *port_mmio = ahci_port_base(mmio, ap->port_no);
306 rc = ata_port_start(ap);
310 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
315 memset(pp, 0, sizeof(*pp));
317 mem = dma_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma, GFP_KERNEL);
322 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
325 * First item in chunk of DMA memory: 32-slot command table,
326 * 32 bytes each in size
329 pp->cmd_slot_dma = mem_dma;
331 mem += AHCI_CMD_SLOT_SZ;
332 mem_dma += AHCI_CMD_SLOT_SZ;
335 * Second item: Received-FIS area
338 pp->rx_fis_dma = mem_dma;
340 mem += AHCI_RX_FIS_SZ;
341 mem_dma += AHCI_RX_FIS_SZ;
344 * Third item: data area for storing a single command
345 * and its scatter-gather table
348 pp->cmd_tbl_dma = mem_dma;
350 pp->cmd_tbl_sg = mem + AHCI_CMD_TBL_HDR;
352 ap->private_data = pp;
354 if (hpriv->cap & HOST_CAP_64)
355 writel((pp->cmd_slot_dma >> 16) >> 16, port_mmio + PORT_LST_ADDR_HI);
356 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
357 readl(port_mmio + PORT_LST_ADDR); /* flush */
359 if (hpriv->cap & HOST_CAP_64)
360 writel((pp->rx_fis_dma >> 16) >> 16, port_mmio + PORT_FIS_ADDR_HI);
361 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
362 readl(port_mmio + PORT_FIS_ADDR); /* flush */
364 writel(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
365 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
366 PORT_CMD_START, port_mmio + PORT_CMD);
367 readl(port_mmio + PORT_CMD); /* flush */
379 static void ahci_port_stop(struct ata_port *ap)
381 struct device *dev = ap->host_set->dev;
382 struct ahci_port_priv *pp = ap->private_data;
383 void *mmio = ap->host_set->mmio_base;
384 void *port_mmio = ahci_port_base(mmio, ap->port_no);
387 tmp = readl(port_mmio + PORT_CMD);
388 tmp &= ~(PORT_CMD_START | PORT_CMD_FIS_RX);
389 writel(tmp, port_mmio + PORT_CMD);
390 readl(port_mmio + PORT_CMD); /* flush */
392 /* spec says 500 msecs for each PORT_CMD_{START,FIS_RX} bit, so
393 * this is slightly incorrect.
397 ap->private_data = NULL;
398 dma_free_coherent(dev, AHCI_PORT_PRIV_DMA_SZ,
399 pp->cmd_slot, pp->cmd_slot_dma);
404 static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in)
409 case SCR_STATUS: sc_reg = 0; break;
410 case SCR_CONTROL: sc_reg = 1; break;
411 case SCR_ERROR: sc_reg = 2; break;
412 case SCR_ACTIVE: sc_reg = 3; break;
417 return readl((void *) ap->ioaddr.scr_addr + (sc_reg * 4));
421 static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in,
427 case SCR_STATUS: sc_reg = 0; break;
428 case SCR_CONTROL: sc_reg = 1; break;
429 case SCR_ERROR: sc_reg = 2; break;
430 case SCR_ACTIVE: sc_reg = 3; break;
435 writel(val, (void *) ap->ioaddr.scr_addr + (sc_reg * 4));
438 static void ahci_phy_reset(struct ata_port *ap)
440 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
441 struct ata_taskfile tf;
442 struct ata_device *dev = &ap->device[0];
445 __sata_phy_reset(ap);
447 if (ap->flags & ATA_FLAG_PORT_DISABLED)
450 tmp = readl(port_mmio + PORT_SIG);
451 tf.lbah = (tmp >> 24) & 0xff;
452 tf.lbam = (tmp >> 16) & 0xff;
453 tf.lbal = (tmp >> 8) & 0xff;
454 tf.nsect = (tmp) & 0xff;
456 dev->class = ata_dev_classify(&tf);
457 if (!ata_dev_present(dev))
458 ata_port_disable(ap);
461 static u8 ahci_check_status(struct ata_port *ap)
463 void *mmio = (void *) ap->ioaddr.cmd_addr;
465 return readl(mmio + PORT_TFDATA) & 0xFF;
468 static u8 ahci_check_err(struct ata_port *ap)
470 void *mmio = (void *) ap->ioaddr.cmd_addr;
472 return (readl(mmio + PORT_TFDATA) >> 8) & 0xFF;
475 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
477 struct ahci_port_priv *pp = ap->private_data;
478 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
480 ata_tf_from_fis(d2h_fis, tf);
483 static void ahci_fill_sg(struct ata_queued_cmd *qc)
485 struct ahci_port_priv *pp = qc->ap->private_data;
491 * Next, the S/G list.
493 for (i = 0; i < qc->n_elem; i++) {
497 addr = sg_dma_address(&qc->sg[i]);
498 sg_len = sg_dma_len(&qc->sg[i]);
500 pp->cmd_tbl_sg[i].addr = cpu_to_le32(addr & 0xffffffff);
501 pp->cmd_tbl_sg[i].addr_hi = cpu_to_le32((addr >> 16) >> 16);
502 pp->cmd_tbl_sg[i].flags_size = cpu_to_le32(sg_len - 1);
506 static void ahci_qc_prep(struct ata_queued_cmd *qc)
508 struct ahci_port_priv *pp = qc->ap->private_data;
510 const u32 cmd_fis_len = 5; /* five dwords */
513 * Fill in command slot information (currently only one slot,
514 * slot 0, is currently since we don't do queueing)
517 opts = (qc->n_elem << 16) | cmd_fis_len;
518 if (qc->tf.flags & ATA_TFLAG_WRITE)
519 opts |= AHCI_CMD_WRITE;
521 switch (qc->tf.protocol) {
523 case ATA_PROT_ATAPI_NODATA:
524 case ATA_PROT_ATAPI_DMA:
525 opts |= AHCI_CMD_ATAPI;
533 pp->cmd_slot[0].opts = cpu_to_le32(opts);
534 pp->cmd_slot[0].status = 0;
535 pp->cmd_slot[0].tbl_addr = cpu_to_le32(pp->cmd_tbl_dma & 0xffffffff);
536 pp->cmd_slot[0].tbl_addr_hi = cpu_to_le32((pp->cmd_tbl_dma >> 16) >> 16);
539 * Fill in command table information. First, the header,
540 * a SATA Register - Host to Device command FIS.
542 ata_tf_to_fis(&qc->tf, pp->cmd_tbl, 0);
544 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
550 static void ahci_intr_error(struct ata_port *ap, u32 irq_stat)
552 void *mmio = ap->host_set->mmio_base;
553 void *port_mmio = ahci_port_base(mmio, ap->port_no);
558 tmp = readl(port_mmio + PORT_CMD);
559 tmp &= ~PORT_CMD_START;
560 writel(tmp, port_mmio + PORT_CMD);
562 /* wait for engine to stop. TODO: this could be
563 * as long as 500 msec
567 tmp = readl(port_mmio + PORT_CMD);
568 if ((tmp & PORT_CMD_LIST_ON) == 0)
573 /* clear SATA phy error, if any */
574 tmp = readl(port_mmio + PORT_SCR_ERR);
575 writel(tmp, port_mmio + PORT_SCR_ERR);
577 /* if DRQ/BSY is set, device needs to be reset.
578 * if so, issue COMRESET
580 tmp = readl(port_mmio + PORT_TFDATA);
581 if (tmp & (ATA_BUSY | ATA_DRQ)) {
582 writel(0x301, port_mmio + PORT_SCR_CTL);
583 readl(port_mmio + PORT_SCR_CTL); /* flush */
585 writel(0x300, port_mmio + PORT_SCR_CTL);
586 readl(port_mmio + PORT_SCR_CTL); /* flush */
590 tmp = readl(port_mmio + PORT_CMD);
591 tmp |= PORT_CMD_START;
592 writel(tmp, port_mmio + PORT_CMD);
593 readl(port_mmio + PORT_CMD); /* flush */
595 printk(KERN_WARNING "ata%u: error occurred, port reset\n", ap->id);
598 static void ahci_eng_timeout(struct ata_port *ap)
600 void *mmio = ap->host_set->mmio_base;
601 void *port_mmio = ahci_port_base(mmio, ap->port_no);
602 struct ata_queued_cmd *qc;
606 ahci_intr_error(ap, readl(port_mmio + PORT_IRQ_STAT));
608 qc = ata_qc_from_tag(ap, ap->active_tag);
610 printk(KERN_ERR "ata%u: BUG: timeout without command\n",
613 /* hack alert! We cannot use the supplied completion
614 * function from inside the ->eh_strategy_handler() thread.
615 * libata is the only user of ->eh_strategy_handler() in
616 * any kernel, so the default scsi_done() assumes it is
617 * not being called from the SCSI EH.
619 qc->scsidone = scsi_finish_command;
620 ata_qc_complete(qc, ATA_ERR);
625 static inline int ahci_host_intr(struct ata_port *ap, struct ata_queued_cmd *qc)
627 void *mmio = ap->host_set->mmio_base;
628 void *port_mmio = ahci_port_base(mmio, ap->port_no);
629 u32 status, serr, ci;
631 serr = readl(port_mmio + PORT_SCR_ERR);
632 writel(serr, port_mmio + PORT_SCR_ERR);
634 status = readl(port_mmio + PORT_IRQ_STAT);
635 writel(status, port_mmio + PORT_IRQ_STAT);
637 ci = readl(port_mmio + PORT_CMD_ISSUE);
638 if (likely((ci & 0x1) == 0)) {
640 ata_qc_complete(qc, 0);
645 if (status & PORT_IRQ_FATAL) {
646 ahci_intr_error(ap, status);
648 ata_qc_complete(qc, ATA_ERR);
654 static void ahci_irq_clear(struct ata_port *ap)
659 static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
661 struct ata_host_set *host_set = dev_instance;
662 struct ahci_host_priv *hpriv;
663 unsigned int i, handled = 0;
665 u32 irq_stat, irq_ack = 0;
669 hpriv = host_set->private_data;
670 mmio = host_set->mmio_base;
672 /* sigh. 0xffffffff is a valid return from h/w */
673 irq_stat = readl(mmio + HOST_IRQ_STAT);
674 irq_stat &= hpriv->port_map;
678 spin_lock(&host_set->lock);
680 for (i = 0; i < host_set->n_ports; i++) {
684 VPRINTK("port %u\n", i);
685 ap = host_set->ports[i];
686 tmp = irq_stat & (1 << i);
688 struct ata_queued_cmd *qc;
689 qc = ata_qc_from_tag(ap, ap->active_tag);
690 if (ahci_host_intr(ap, qc))
696 writel(irq_ack, mmio + HOST_IRQ_STAT);
700 spin_unlock(&host_set->lock);
704 return IRQ_RETVAL(handled);
707 static int ahci_qc_issue(struct ata_queued_cmd *qc)
709 struct ata_port *ap = qc->ap;
710 void *port_mmio = (void *) ap->ioaddr.cmd_addr;
712 writel(1, port_mmio + PORT_SCR_ACT);
713 readl(port_mmio + PORT_SCR_ACT); /* flush */
715 writel(1, port_mmio + PORT_CMD_ISSUE);
716 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
721 static void ahci_setup_port(struct ata_ioports *port, unsigned long base,
722 unsigned int port_idx)
724 VPRINTK("ENTER, base==0x%lx, port_idx %u\n", base, port_idx);
725 base = ahci_port_base_ul(base, port_idx);
726 VPRINTK("base now==0x%lx\n", base);
728 port->cmd_addr = base;
729 port->scr_addr = base + PORT_SCR;
734 static int ahci_host_init(struct ata_probe_ent *probe_ent)
736 struct ahci_host_priv *hpriv = probe_ent->private_data;
737 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
738 void __iomem *mmio = probe_ent->mmio_base;
741 unsigned int i, j, using_dac;
743 void __iomem *port_mmio;
745 cap_save = readl(mmio + HOST_CAP);
746 cap_save &= ( (1<<28) | (1<<17) );
747 cap_save |= (1 << 27);
749 /* global controller reset */
750 tmp = readl(mmio + HOST_CTL);
751 if ((tmp & HOST_RESET) == 0) {
752 writel(tmp | HOST_RESET, mmio + HOST_CTL);
753 readl(mmio + HOST_CTL); /* flush */
756 /* reset must complete within 1 second, or
757 * the hardware should be considered fried.
761 tmp = readl(mmio + HOST_CTL);
762 if (tmp & HOST_RESET) {
763 printk(KERN_ERR DRV_NAME "(%s): controller reset failed (0x%x)\n",
764 pci_name(pdev), tmp);
768 writel(HOST_AHCI_EN, mmio + HOST_CTL);
769 (void) readl(mmio + HOST_CTL); /* flush */
770 writel(cap_save, mmio + HOST_CAP);
771 writel(0xf, mmio + HOST_PORTS_IMPL);
772 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
774 pci_read_config_word(pdev, 0x92, &tmp16);
776 pci_write_config_word(pdev, 0x92, tmp16);
778 hpriv->cap = readl(mmio + HOST_CAP);
779 hpriv->port_map = readl(mmio + HOST_PORTS_IMPL);
780 probe_ent->n_ports = (hpriv->cap & 0x1f) + 1;
782 VPRINTK("cap 0x%x port_map 0x%x n_ports %d\n",
783 hpriv->cap, hpriv->port_map, probe_ent->n_ports);
785 using_dac = hpriv->cap & HOST_CAP_64;
787 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
788 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
790 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
792 printk(KERN_ERR DRV_NAME "(%s): 64-bit DMA enable failed\n",
798 hpriv->flags |= HOST_CAP_64;
800 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
802 printk(KERN_ERR DRV_NAME "(%s): 32-bit DMA enable failed\n",
806 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
808 printk(KERN_ERR DRV_NAME "(%s): 32-bit consistent DMA enable failed\n",
814 for (i = 0; i < probe_ent->n_ports; i++) {
815 #if 0 /* BIOSen initialize this incorrectly */
816 if (!(hpriv->port_map & (1 << i)))
820 port_mmio = ahci_port_base(mmio, i);
821 VPRINTK("mmio %p port_mmio %p\n", mmio, port_mmio);
823 ahci_setup_port(&probe_ent->port[i],
824 (unsigned long) mmio, i);
826 /* make sure port is not active */
827 tmp = readl(port_mmio + PORT_CMD);
828 VPRINTK("PORT_CMD 0x%x\n", tmp);
829 if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
830 PORT_CMD_FIS_RX | PORT_CMD_START)) {
831 tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
832 PORT_CMD_FIS_RX | PORT_CMD_START);
833 writel(tmp, port_mmio + PORT_CMD);
834 readl(port_mmio + PORT_CMD); /* flush */
836 /* spec says 500 msecs for each bit, so
837 * this is slightly incorrect.
842 writel(PORT_CMD_SPIN_UP, port_mmio + PORT_CMD);
847 tmp = readl(port_mmio + PORT_SCR_STAT);
848 if ((tmp & 0xf) == 0x3)
853 tmp = readl(port_mmio + PORT_SCR_ERR);
854 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
855 writel(tmp, port_mmio + PORT_SCR_ERR);
857 /* ack any pending irq events for this port */
858 tmp = readl(port_mmio + PORT_IRQ_STAT);
859 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
861 writel(tmp, port_mmio + PORT_IRQ_STAT);
863 writel(1 << i, mmio + HOST_IRQ_STAT);
865 /* set irq mask (enables interrupts) */
866 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
869 tmp = readl(mmio + HOST_CTL);
870 VPRINTK("HOST_CTL 0x%x\n", tmp);
871 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
872 tmp = readl(mmio + HOST_CTL);
873 VPRINTK("HOST_CTL 0x%x\n", tmp);
875 pci_set_master(pdev);
880 /* move to PCI layer, integrate w/ MSI stuff */
881 static void pci_intx(struct pci_dev *pdev, int enable)
883 u16 pci_command, new;
885 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
888 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
890 new = pci_command | PCI_COMMAND_INTX_DISABLE;
892 if (new != pci_command)
893 pci_write_config_word(pdev, PCI_COMMAND, pci_command);
896 static void ahci_print_info(struct ata_probe_ent *probe_ent)
898 struct ahci_host_priv *hpriv = probe_ent->private_data;
899 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
900 void *mmio = probe_ent->mmio_base;
901 u32 vers, cap, impl, speed;
906 vers = readl(mmio + HOST_VERSION);
908 impl = hpriv->port_map;
910 speed = (cap >> 20) & 0xf;
918 pci_read_config_word(pdev, 0x0a, &cc);
921 else if (cc == 0x0106)
923 else if (cc == 0x0104)
928 printk(KERN_INFO DRV_NAME "(%s) AHCI %02x%02x.%02x%02x "
929 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
938 ((cap >> 8) & 0x1f) + 1,
944 printk(KERN_INFO DRV_NAME "(%s) flags: "
950 cap & (1 << 31) ? "64bit " : "",
951 cap & (1 << 30) ? "ncq " : "",
952 cap & (1 << 28) ? "ilck " : "",
953 cap & (1 << 27) ? "stag " : "",
954 cap & (1 << 26) ? "pm " : "",
955 cap & (1 << 25) ? "led " : "",
957 cap & (1 << 24) ? "clo " : "",
958 cap & (1 << 19) ? "nz " : "",
959 cap & (1 << 18) ? "only " : "",
960 cap & (1 << 17) ? "pmp " : "",
961 cap & (1 << 15) ? "pio " : "",
962 cap & (1 << 14) ? "slum " : "",
963 cap & (1 << 13) ? "part " : ""
967 static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
969 static int printed_version;
970 struct ata_probe_ent *probe_ent = NULL;
971 struct ahci_host_priv *hpriv;
974 unsigned int board_idx = (unsigned int) ent->driver_data;
975 int have_msi, pci_dev_busy = 0;
980 if (!printed_version++)
981 printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
983 rc = pci_enable_device(pdev);
987 rc = pci_request_regions(pdev, DRV_NAME);
993 if (pci_enable_msi(pdev) == 0)
1000 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
1001 if (probe_ent == NULL) {
1006 memset(probe_ent, 0, sizeof(*probe_ent));
1007 probe_ent->dev = pci_dev_to_dev(pdev);
1008 INIT_LIST_HEAD(&probe_ent->node);
1010 mmio_base = ioremap(pci_resource_start(pdev, AHCI_PCI_BAR),
1011 pci_resource_len(pdev, AHCI_PCI_BAR));
1012 if (mmio_base == NULL) {
1014 goto err_out_free_ent;
1016 base = (unsigned long) mmio_base;
1018 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
1021 goto err_out_iounmap;
1023 memset(hpriv, 0, sizeof(*hpriv));
1025 probe_ent->sht = ahci_port_info[board_idx].sht;
1026 probe_ent->host_flags = ahci_port_info[board_idx].host_flags;
1027 probe_ent->pio_mask = ahci_port_info[board_idx].pio_mask;
1028 probe_ent->udma_mask = ahci_port_info[board_idx].udma_mask;
1029 probe_ent->port_ops = ahci_port_info[board_idx].port_ops;
1031 probe_ent->irq = pdev->irq;
1032 probe_ent->irq_flags = SA_SHIRQ;
1033 probe_ent->mmio_base = mmio_base;
1034 probe_ent->private_data = hpriv;
1036 hpriv->have_msi = have_msi;
1038 /* initialize adapter */
1039 rc = ahci_host_init(probe_ent);
1043 ahci_print_info(probe_ent);
1045 /* FIXME: check ata_device_add return value */
1046 ata_device_add(probe_ent);
1059 pci_disable_msi(pdev);
1062 pci_release_regions(pdev);
1065 pci_disable_device(pdev);
1069 static void ahci_remove_one (struct pci_dev *pdev)
1071 struct device *dev = pci_dev_to_dev(pdev);
1072 struct ata_host_set *host_set = dev_get_drvdata(dev);
1073 struct ahci_host_priv *hpriv = host_set->private_data;
1074 struct ata_port *ap;
1078 for (i = 0; i < host_set->n_ports; i++) {
1079 ap = host_set->ports[i];
1081 scsi_remove_host(ap->host);
1084 have_msi = hpriv->have_msi;
1085 free_irq(host_set->irq, host_set);
1086 host_set->ops->host_stop(host_set);
1087 iounmap(host_set->mmio_base);
1089 for (i = 0; i < host_set->n_ports; i++) {
1090 ap = host_set->ports[i];
1092 ata_scsi_release(ap->host);
1093 scsi_host_put(ap->host);
1097 pci_disable_msi(pdev);
1100 pci_release_regions(pdev);
1102 pci_disable_device(pdev);
1103 dev_set_drvdata(dev, NULL);
1106 static int __init ahci_init(void)
1108 return pci_module_init(&ahci_pci_driver);
1112 static void __exit ahci_exit(void)
1114 pci_unregister_driver(&ahci_pci_driver);
1118 MODULE_AUTHOR("Jeff Garzik");
1119 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1120 MODULE_LICENSE("GPL");
1121 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1123 module_init(ahci_init);
1124 module_exit(ahci_exit);