drivers/scsi/aic7xxx/aic79xx_pci.c

   1 /*
   2  * Product specific probe and attach routines for:
   3  *      aic7901 and aic7902 SCSI controllers
   4  *
   5  * Copyright (c) 1994-2001 Justin T. Gibbs.
   6  * Copyright (c) 2000-2002 Adaptec Inc.
   7  * All rights reserved.
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions, and the following disclaimer,
  14  *    without modification.
  15  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  16  *    substantially similar to the "NO WARRANTY" disclaimer below
  17  *    ("Disclaimer") and any redistribution must be conditioned upon
  18  *    including a substantially similar Disclaimer requirement for further
  19  *    binary redistribution.
  20  * 3. Neither the names of the above-listed copyright holders nor the names
  21  *    of any contributors may be used to endorse or promote products derived
  22  *    from this software without specific prior written permission.
  23  *
  24  * Alternatively, this software may be distributed under the terms of the
  25  * GNU General Public License ("GPL") version 2 as published by the Free
  26  * Software Foundation.
  27  *
  28  * NO WARRANTY
  29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
  32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  33  * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  34  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  35  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  36  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  37  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  38  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  39  * POSSIBILITY OF SUCH DAMAGES.
  40  *
  41  * $Id: //depot/aic7xxx/aic7xxx/aic79xx_pci.c#92 $
  42  */
  43
  44 #ifdef __linux__
  45 #include "aic79xx_osm.h"
  46 #include "aic79xx_inline.h"
  47 #else
  48 #include <dev/aic7xxx/aic79xx_osm.h>
  49 #include <dev/aic7xxx/aic79xx_inline.h>
  50 #endif
  51
  52 #include "aic79xx_pci.h"
  53
  54 static inline uint64_t
  55 ahd_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor)
  56 {
  57         uint64_t id;
  58
  59         id = subvendor
  60            | (subdevice << 16)
  61            | ((uint64_t)vendor << 32)
  62            | ((uint64_t)device << 48);
  63
  64         return (id);
  65 }
  66
  67 #define ID_AIC7902_PCI_REV_A4           0x3
  68 #define ID_AIC7902_PCI_REV_B0           0x10
  69 #define SUBID_HP                        0x0E11
  70
  71 #define DEVID_9005_HOSTRAID(id) ((id) & 0x80)
  72
  73 #define DEVID_9005_TYPE(id) ((id) & 0xF)
  74 #define         DEVID_9005_TYPE_HBA             0x0     /* Standard Card */
  75 #define         DEVID_9005_TYPE_HBA_2EXT        0x1     /* 2 External Ports */
  76 #define         DEVID_9005_TYPE_IROC            0x8     /* Raid(0,1,10) Card */
  77 #define         DEVID_9005_TYPE_MB              0xF     /* On Motherboard */
  78
  79 #define DEVID_9005_MFUNC(id) ((id) & 0x10)
  80
  81 #define DEVID_9005_PACKETIZED(id) ((id) & 0x8000)
  82
  83 #define SUBID_9005_TYPE(id) ((id) & 0xF)
  84 #define         SUBID_9005_TYPE_HBA             0x0     /* Standard Card */
  85 #define         SUBID_9005_TYPE_MB              0xF     /* On Motherboard */
  86
  87 #define SUBID_9005_AUTOTERM(id) (((id) & 0x10) == 0)
  88
  89 #define SUBID_9005_LEGACYCONN_FUNC(id) ((id) & 0x20)
  90
  91 #define SUBID_9005_SEEPTYPE(id) (((id) & 0x0C0) >> 6)
  92 #define         SUBID_9005_SEEPTYPE_NONE        0x0
  93 #define         SUBID_9005_SEEPTYPE_4K          0x1
  94
  95 static ahd_device_setup_t ahd_aic7901_setup;
  96 static ahd_device_setup_t ahd_aic7901A_setup;
  97 static ahd_device_setup_t ahd_aic7902_setup;
  98 static ahd_device_setup_t ahd_aic790X_setup;
  99
 100 static const struct ahd_pci_identity ahd_pci_ident_table[] =
 101 {
 102         /* aic7901 based controllers */
 103         {
 104                 ID_AHA_29320A,
 105                 ID_ALL_MASK,
 106                 "Adaptec 29320A Ultra320 SCSI adapter",
 107                 ahd_aic7901_setup
 108         },
 109         {
 110                 ID_AHA_29320ALP,
 111                 ID_ALL_MASK,
 112                 "Adaptec 29320ALP PCIx Ultra320 SCSI adapter",
 113                 ahd_aic7901_setup
 114         },
 115         {
 116                 ID_AHA_29320LPE,
 117                 ID_ALL_MASK,
 118                 "Adaptec 29320LPE PCIe Ultra320 SCSI adapter",
 119                 ahd_aic7901_setup
 120         },
 121         /* aic7901A based controllers */
 122         {
 123                 ID_AHA_29320LP,
 124                 ID_ALL_MASK,
 125                 "Adaptec 29320LP Ultra320 SCSI adapter",
 126                 ahd_aic7901A_setup
 127         },
 128         /* aic7902 based controllers */
 129         {
 130                 ID_AHA_29320,
 131                 ID_ALL_MASK,
 132                 "Adaptec 29320 Ultra320 SCSI adapter",
 133                 ahd_aic7902_setup
 134         },
 135         {
 136                 ID_AHA_29320B,
 137                 ID_ALL_MASK,
 138                 "Adaptec 29320B Ultra320 SCSI adapter",
 139                 ahd_aic7902_setup
 140         },
 141         {
 142                 ID_AHA_39320,
 143                 ID_ALL_MASK,
 144                 "Adaptec 39320 Ultra320 SCSI adapter",
 145                 ahd_aic7902_setup
 146         },
 147         {
 148                 ID_AHA_39320_B,
 149                 ID_ALL_MASK,
 150                 "Adaptec 39320 Ultra320 SCSI adapter",
 151                 ahd_aic7902_setup
 152         },
 153         {
 154                 ID_AHA_39320_B_DELL,
 155                 ID_ALL_MASK,
 156                 "Adaptec (Dell OEM) 39320 Ultra320 SCSI adapter",
 157                 ahd_aic7902_setup
 158         },
 159         {
 160                 ID_AHA_39320A,
 161                 ID_ALL_MASK,
 162                 "Adaptec 39320A Ultra320 SCSI adapter",
 163                 ahd_aic7902_setup
 164         },
 165         {
 166                 ID_AHA_39320D,
 167                 ID_ALL_MASK,
 168                 "Adaptec 39320D Ultra320 SCSI adapter",
 169                 ahd_aic7902_setup
 170         },
 171         {
 172                 ID_AHA_39320D_HP,
 173                 ID_ALL_MASK,
 174                 "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter",
 175                 ahd_aic7902_setup
 176         },
 177         {
 178                 ID_AHA_39320D_B,
 179                 ID_ALL_MASK,
 180                 "Adaptec 39320D Ultra320 SCSI adapter",
 181                 ahd_aic7902_setup
 182         },
 183         {
 184                 ID_AHA_39320D_B_HP,
 185                 ID_ALL_MASK,
 186                 "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter",
 187                 ahd_aic7902_setup
 188         },
 189         /* Generic chip probes for devices we don't know 'exactly' */
 190         {
 191                 ID_AIC7901 & ID_9005_GENERIC_MASK,
 192                 ID_9005_GENERIC_MASK,
 193                 "Adaptec AIC7901 Ultra320 SCSI adapter",
 194                 ahd_aic7901_setup
 195         },
 196         {
 197                 ID_AIC7901A & ID_DEV_VENDOR_MASK,
 198                 ID_DEV_VENDOR_MASK,
 199                 "Adaptec AIC7901A Ultra320 SCSI adapter",
 200                 ahd_aic7901A_setup
 201         },
 202         {
 203                 ID_AIC7902 & ID_9005_GENERIC_MASK,
 204                 ID_9005_GENERIC_MASK,
 205                 "Adaptec AIC7902 Ultra320 SCSI adapter",
 206                 ahd_aic7902_setup
 207         }
 208 };
 209
 210 static const u_int ahd_num_pci_devs = ARRAY_SIZE(ahd_pci_ident_table);
 211
 212 #define DEVCONFIG               0x40
 213 #define         PCIXINITPAT     0x0000E000ul
 214 #define                 PCIXINIT_PCI33_66       0x0000E000ul
 215 #define                 PCIXINIT_PCIX50_66      0x0000C000ul
 216 #define                 PCIXINIT_PCIX66_100     0x0000A000ul
 217 #define                 PCIXINIT_PCIX100_133    0x00008000ul
 218 #define PCI_BUS_MODES_INDEX(devconfig)  \
 219         (((devconfig) & PCIXINITPAT) >> 13)
 220 static const char *pci_bus_modes[] =
 221 {
 222         "PCI bus mode unknown",
 223         "PCI bus mode unknown",
 224         "PCI bus mode unknown",
 225         "PCI bus mode unknown",
 226         "PCI-X 101-133MHz",
 227         "PCI-X 67-100MHz",
 228         "PCI-X 50-66MHz",
 229         "PCI 33 or 66MHz"
 230 };
 231
 232 #define         TESTMODE        0x00000800ul
 233 #define         IRDY_RST        0x00000200ul
 234 #define         FRAME_RST       0x00000100ul
 235 #define         PCI64BIT        0x00000080ul
 236 #define         MRDCEN          0x00000040ul
 237 #define         ENDIANSEL       0x00000020ul
 238 #define         MIXQWENDIANEN   0x00000008ul
 239 #define         DACEN           0x00000004ul
 240 #define         STPWLEVEL       0x00000002ul
 241 #define         QWENDIANSEL     0x00000001ul
 242
 243 #define DEVCONFIG1              0x44
 244 #define         PREQDIS         0x01
 245
 246 #define CSIZE_LATTIME           0x0c
 247 #define         CACHESIZE       0x000000fful
 248 #define         LATTIME         0x0000ff00ul
 249
 250 static int      ahd_check_extport(struct ahd_softc *ahd);
 251 static void     ahd_configure_termination(struct ahd_softc *ahd,
 252                                           u_int adapter_control);
 253 static void     ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat);
 254 static void     ahd_pci_intr(struct ahd_softc *ahd);
 255
 256 const struct ahd_pci_identity *
 257 ahd_find_pci_device(ahd_dev_softc_t pci)
 258 {
 259         uint64_t  full_id;
 260         uint16_t  device;
 261         uint16_t  vendor;
 262         uint16_t  subdevice;
 263         uint16_t  subvendor;
 264         const struct ahd_pci_identity *entry;
 265         u_int     i;
 266
 267         vendor = ahd_pci_read_config(pci, PCIR_DEVVENDOR, /*bytes*/2);
 268         device = ahd_pci_read_config(pci, PCIR_DEVICE, /*bytes*/2);
 269         subvendor = ahd_pci_read_config(pci, PCIR_SUBVEND_0, /*bytes*/2);
 270         subdevice = ahd_pci_read_config(pci, PCIR_SUBDEV_0, /*bytes*/2);
 271         full_id = ahd_compose_id(device,
 272                                  vendor,
 273                                  subdevice,
 274                                  subvendor);
 275
 276         /*
 277          * Controllers, mask out the IROC/HostRAID bit
 278          */
 279
 280         full_id &= ID_ALL_IROC_MASK;
 281
 282         for (i = 0; i < ahd_num_pci_devs; i++) {
 283                 entry = &ahd_pci_ident_table[i];
 284                 if (entry->full_id == (full_id & entry->id_mask)) {
 285                         /* Honor exclusion entries. */
 286                         if (entry->name == NULL)
 287                                 return (NULL);
 288                         return (entry);
 289                 }
 290         }
 291         return (NULL);
 292 }
 293
 294 int
 295 ahd_pci_config(struct ahd_softc *ahd, const struct ahd_pci_identity *entry)
 296 {
 297         struct scb_data *shared_scb_data;
 298         u_int            command;
 299         uint32_t         devconfig;
 300         uint16_t         subvendor;
 301         int              error;
 302
 303         shared_scb_data = NULL;
 304         ahd->description = entry->name;
 305         /*
 306          * Record if this is an HP board.
 307          */
 308         subvendor = ahd_pci_read_config(ahd->dev_softc,
 309                                         PCIR_SUBVEND_0, /*bytes*/2);
 310         if (subvendor == SUBID_HP)
 311                 ahd->flags |= AHD_HP_BOARD;
 312
 313         error = entry->setup(ahd);
 314         if (error != 0)
 315                 return (error);
 316
 317         devconfig = ahd_pci_read_config(ahd->dev_softc, DEVCONFIG, /*bytes*/4);
 318         if ((devconfig & PCIXINITPAT) == PCIXINIT_PCI33_66) {
 319                 ahd->chip |= AHD_PCI;
 320                 /* Disable PCIX workarounds when running in PCI mode. */
 321                 ahd->bugs &= ~AHD_PCIX_BUG_MASK;
 322         } else {
 323                 ahd->chip |= AHD_PCIX;
 324         }
 325         ahd->bus_description = pci_bus_modes[PCI_BUS_MODES_INDEX(devconfig)];
 326
 327         ahd_power_state_change(ahd, AHD_POWER_STATE_D0);
 328
 329         error = ahd_pci_map_registers(ahd);
 330         if (error != 0)
 331                 return (error);
 332
 333         /*
 334          * If we need to support high memory, enable dual
 335          * address cycles.  This bit must be set to enable
 336          * high address bit generation even if we are on a
 337          * 64bit bus (PCI64BIT set in devconfig).
 338          */
 339         if ((ahd->flags & (AHD_39BIT_ADDRESSING|AHD_64BIT_ADDRESSING)) != 0) {
 340                 if (bootverbose)
 341                         printk("%s: Enabling 39Bit Addressing\n",
 342                                ahd_name(ahd));
 343                 devconfig = ahd_pci_read_config(ahd->dev_softc,
 344                                                 DEVCONFIG, /*bytes*/4);
 345                 devconfig |= DACEN;
 346                 ahd_pci_write_config(ahd->dev_softc, DEVCONFIG,
 347                                      devconfig, /*bytes*/4);
 348         }
 349
 350         /* Ensure busmastering is enabled */
 351         command = ahd_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/2);
 352         command |= PCIM_CMD_BUSMASTEREN;
 353         ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND, command, /*bytes*/2);
 354
 355         error = ahd_softc_init(ahd);
 356         if (error != 0)
 357                 return (error);
 358
 359         ahd->bus_intr = ahd_pci_intr;
 360
 361         error = ahd_reset(ahd, /*reinit*/FALSE);
 362         if (error != 0)
 363                 return (ENXIO);
 364
 365         ahd->pci_cachesize =
 366             ahd_pci_read_config(ahd->dev_softc, CSIZE_LATTIME,
 367                                 /*bytes*/1) & CACHESIZE;
 368         ahd->pci_cachesize *= 4;
 369
 370         ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
 371         /* See if we have a SEEPROM and perform auto-term */
 372         error = ahd_check_extport(ahd);
 373         if (error != 0)
 374                 return (error);
 375
 376         /* Core initialization */
 377         error = ahd_init(ahd);
 378         if (error != 0)
 379                 return (error);
 380         ahd->init_level++;
 381
 382         /*
 383          * Allow interrupts now that we are completely setup.
 384          */
 385         return ahd_pci_map_int(ahd);
 386 }
 387
 388 #ifdef CONFIG_PM
 389 void
 390 ahd_pci_suspend(struct ahd_softc *ahd)
 391 {
 392         /*
 393          * Save chip register configuration data for chip resets
 394          * that occur during runtime and resume events.
 395          */
 396         ahd->suspend_state.pci_state.devconfig =
 397             ahd_pci_read_config(ahd->dev_softc, DEVCONFIG, /*bytes*/4);
 398         ahd->suspend_state.pci_state.command =
 399             ahd_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/1);
 400         ahd->suspend_state.pci_state.csize_lattime =
 401             ahd_pci_read_config(ahd->dev_softc, CSIZE_LATTIME, /*bytes*/1);
 402
 403 }
 404
 405 void
 406 ahd_pci_resume(struct ahd_softc *ahd)
 407 {
 408         ahd_pci_write_config(ahd->dev_softc, DEVCONFIG,
 409                              ahd->suspend_state.pci_state.devconfig, /*bytes*/4);
 410         ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND,
 411                              ahd->suspend_state.pci_state.command, /*bytes*/1);
 412         ahd_pci_write_config(ahd->dev_softc, CSIZE_LATTIME,
 413                              ahd->suspend_state.pci_state.csize_lattime, /*bytes*/1);
 414 }
 415 #endif
 416
 417 /*
 418  * Perform some simple tests that should catch situations where
 419  * our registers are invalidly mapped.
 420  */
 421 int
 422 ahd_pci_test_register_access(struct ahd_softc *ahd)
 423 {
 424         uint32_t cmd;
 425         u_int    targpcistat;
 426         u_int    pci_status1;
 427         int      error;
 428         uint8_t  hcntrl;
 429
 430         error = EIO;
 431
 432         /*
 433          * Enable PCI error interrupt status, but suppress NMIs
 434          * generated by SERR raised due to target aborts.
 435          */
 436         cmd = ahd_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/2);
 437         ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND,
 438                              cmd & ~PCIM_CMD_SERRESPEN, /*bytes*/2);
 439
 440         /*
 441          * First a simple test to see if any
 442          * registers can be read.  Reading
 443          * HCNTRL has no side effects and has
 444          * at least one bit that is guaranteed to
 445          * be zero so it is a good register to
 446          * use for this test.
 447          */
 448         hcntrl = ahd_inb(ahd, HCNTRL);
 449         if (hcntrl == 0xFF)
 450                 goto fail;
 451
 452         /*
 453          * Next create a situation where write combining
 454          * or read prefetching could be initiated by the
 455          * CPU or host bridge.  Our device does not support
 456          * either, so look for data corruption and/or flaged
 457          * PCI errors.  First pause without causing another
 458          * chip reset.
 459          */
 460         hcntrl &= ~CHIPRST;
 461         ahd_outb(ahd, HCNTRL, hcntrl|PAUSE);
 462         while (ahd_is_paused(ahd) == 0)
 463                 ;
 464
 465         /* Clear any PCI errors that occurred before our driver attached. */
 466         ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
 467         targpcistat = ahd_inb(ahd, TARGPCISTAT);
 468         ahd_outb(ahd, TARGPCISTAT, targpcistat);
 469         pci_status1 = ahd_pci_read_config(ahd->dev_softc,
 470                                           PCIR_STATUS + 1, /*bytes*/1);
 471         ahd_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1,
 472                              pci_status1, /*bytes*/1);
 473         ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
 474         ahd_outb(ahd, CLRINT, CLRPCIINT);
 475
 476         ahd_outb(ahd, SEQCTL0, PERRORDIS);
 477         ahd_outl(ahd, SRAM_BASE, 0x5aa555aa);
 478         if (ahd_inl(ahd, SRAM_BASE) != 0x5aa555aa)
 479                 goto fail;
 480
 481         if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) {
 482                 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
 483                 targpcistat = ahd_inb(ahd, TARGPCISTAT);
 484                 if ((targpcistat & STA) != 0)
 485                         goto fail;
 486         }
 487
 488         error = 0;
 489
 490 fail:
 491         if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) {
 492
 493                 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
 494                 targpcistat = ahd_inb(ahd, TARGPCISTAT);
 495
 496                 /* Silently clear any latched errors. */
 497                 ahd_outb(ahd, TARGPCISTAT, targpcistat);
 498                 pci_status1 = ahd_pci_read_config(ahd->dev_softc,
 499                                                   PCIR_STATUS + 1, /*bytes*/1);
 500                 ahd_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1,
 501                                      pci_status1, /*bytes*/1);
 502                 ahd_outb(ahd, CLRINT, CLRPCIINT);
 503         }
 504         ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS);
 505         ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND, cmd, /*bytes*/2);
 506         return (error);
 507 }
 508
 509 /*
 510  * Check the external port logic for a serial eeprom
 511  * and termination/cable detection contrls.
 512  */
 513 static int
 514 ahd_check_extport(struct ahd_softc *ahd)
 515 {
 516         struct  vpd_config vpd;
 517         struct  seeprom_config *sc;
 518         u_int   adapter_control;
 519         int     have_seeprom;
 520         int     error;
 521
 522         sc = ahd->seep_config;
 523         have_seeprom = ahd_acquire_seeprom(ahd);
 524         if (have_seeprom) {
 525                 u_int start_addr;
 526
 527                 /*
 528                  * Fetch VPD for this function and parse it.
 529                  */
 530                 if (bootverbose)
 531                         printk("%s: Reading VPD from SEEPROM...",
 532                                ahd_name(ahd));
 533
 534                 /* Address is always in units of 16bit words */
 535                 start_addr = ((2 * sizeof(*sc))
 536                             + (sizeof(vpd) * (ahd->channel - 'A'))) / 2;
 537
 538                 error = ahd_read_seeprom(ahd, (uint16_t *)&vpd,
 539                                          start_addr, sizeof(vpd)/2,
 540                                          /*bytestream*/TRUE);
 541                 if (error == 0)
 542                         error = ahd_parse_vpddata(ahd, &vpd);
 543                 if (bootverbose)
 544                         printk("%s: VPD parsing %s\n",
 545                                ahd_name(ahd),
 546                                error == 0 ? "successful" : "failed");
 547
 548                 if (bootverbose)
 549                         printk("%s: Reading SEEPROM...", ahd_name(ahd));
 550
 551                 /* Address is always in units of 16bit words */
 552                 start_addr = (sizeof(*sc) / 2) * (ahd->channel - 'A');
 553
 554                 error = ahd_read_seeprom(ahd, (uint16_t *)sc,
 555                                          start_addr, sizeof(*sc)/2,
 556                                          /*bytestream*/FALSE);
 557
 558                 if (error != 0) {
 559                         printk("Unable to read SEEPROM\n");
 560                         have_seeprom = 0;
 561                 } else {
 562                         have_seeprom = ahd_verify_cksum(sc);
 563
 564                         if (bootverbose) {
 565                                 if (have_seeprom == 0)
 566                                         printk ("checksum error\n");
 567                                 else
 568                                         printk ("done.\n");
 569                         }
 570                 }
 571                 ahd_release_seeprom(ahd);
 572         }
 573
 574         if (!have_seeprom) {
 575                 u_int     nvram_scb;
 576
 577                 /*
 578                  * Pull scratch ram settings and treat them as
 579                  * if they are the contents of an seeprom if
 580                  * the 'ADPT', 'BIOS', or 'ASPI' signature is found
 581                  * in SCB 0xFF.  We manually compose the data as 16bit
 582                  * values to avoid endian issues.
 583                  */
 584                 ahd_set_scbptr(ahd, 0xFF);
 585                 nvram_scb = ahd_inb_scbram(ahd, SCB_BASE + NVRAM_SCB_OFFSET);
 586                 if (nvram_scb != 0xFF
 587                  && ((ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A'
 588                    && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'D'
 589                    && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P'
 590                    && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'T')
 591                   || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'B'
 592                    && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'I'
 593                    && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'O'
 594                    && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'S')
 595                   || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A'
 596                    && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'S'
 597                    && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P'
 598                    && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'I'))) {
 599                         uint16_t *sc_data;
 600                         int       i;
 601
 602                         ahd_set_scbptr(ahd, nvram_scb);
 603                         sc_data = (uint16_t *)sc;
 604                         for (i = 0; i < 64; i += 2)
 605                                 *sc_data++ = ahd_inw_scbram(ahd, SCB_BASE+i);
 606                         have_seeprom = ahd_verify_cksum(sc);
 607                         if (have_seeprom)
 608                                 ahd->flags |= AHD_SCB_CONFIG_USED;
 609                 }
 610         }
 611
 612 #ifdef AHD_DEBUG
 613         if (have_seeprom != 0
 614          && (ahd_debug & AHD_DUMP_SEEPROM) != 0) {
 615                 uint16_t *sc_data;
 616                 int       i;
 617
 618                 printk("%s: Seeprom Contents:", ahd_name(ahd));
 619                 sc_data = (uint16_t *)sc;
 620                 for (i = 0; i < (sizeof(*sc)); i += 2)
 621                         printk("\n\t0x%.4x", sc_data[i]);
 622                 printk("\n");
 623         }
 624 #endif
 625
 626         if (!have_seeprom) {
 627                 if (bootverbose)
 628                         printk("%s: No SEEPROM available.\n", ahd_name(ahd));
 629                 ahd->flags |= AHD_USEDEFAULTS;
 630                 error = ahd_default_config(ahd);
 631                 adapter_control = CFAUTOTERM|CFSEAUTOTERM;
 632                 kfree(ahd->seep_config);
 633                 ahd->seep_config = NULL;
 634         } else {
 635                 error = ahd_parse_cfgdata(ahd, sc);
 636                 adapter_control = sc->adapter_control;
 637         }
 638         if (error != 0)
 639                 return (error);
 640
 641         ahd_configure_termination(ahd, adapter_control);
 642
 643         return (0);
 644 }
 645
 646 static void
 647 ahd_configure_termination(struct ahd_softc *ahd, u_int adapter_control)
 648 {
 649         int      error;
 650         u_int    sxfrctl1;
 651         uint8_t  termctl;
 652         uint32_t devconfig;
 653
 654         devconfig = ahd_pci_read_config(ahd->dev_softc, DEVCONFIG, /*bytes*/4);
 655         devconfig &= ~STPWLEVEL;
 656         if ((ahd->flags & AHD_STPWLEVEL_A) != 0)
 657                 devconfig |= STPWLEVEL;
 658         if (bootverbose)
 659                 printk("%s: STPWLEVEL is %s\n",
 660                        ahd_name(ahd), (devconfig & STPWLEVEL) ? "on" : "off");
 661         ahd_pci_write_config(ahd->dev_softc, DEVCONFIG, devconfig, /*bytes*/4);
 662
 663         /* Make sure current sensing is off. */
 664         if ((ahd->flags & AHD_CURRENT_SENSING) != 0) {
 665                 (void)ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 0);
 666         }
 667
 668         /*
 669          * Read to sense.  Write to set.
 670          */
 671         error = ahd_read_flexport(ahd, FLXADDR_TERMCTL, &termctl);
 672         if ((adapter_control & CFAUTOTERM) == 0) {
 673                 if (bootverbose)
 674                         printk("%s: Manual Primary Termination\n",
 675                                ahd_name(ahd));
 676                 termctl &= ~(FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH);
 677                 if ((adapter_control & CFSTERM) != 0)
 678                         termctl |= FLX_TERMCTL_ENPRILOW;
 679                 if ((adapter_control & CFWSTERM) != 0)
 680                         termctl |= FLX_TERMCTL_ENPRIHIGH;
 681         } else if (error != 0) {
 682                 printk("%s: Primary Auto-Term Sensing failed! "
 683                        "Using Defaults.\n", ahd_name(ahd));
 684                 termctl = FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH;
 685         }
 686
 687         if ((adapter_control & CFSEAUTOTERM) == 0) {
 688                 if (bootverbose)
 689                         printk("%s: Manual Secondary Termination\n",
 690                                ahd_name(ahd));
 691                 termctl &= ~(FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH);
 692                 if ((adapter_control & CFSELOWTERM) != 0)
 693                         termctl |= FLX_TERMCTL_ENSECLOW;
 694                 if ((adapter_control & CFSEHIGHTERM) != 0)
 695                         termctl |= FLX_TERMCTL_ENSECHIGH;
 696         } else if (error != 0) {
 697                 printk("%s: Secondary Auto-Term Sensing failed! "
 698                        "Using Defaults.\n", ahd_name(ahd));
 699                 termctl |= FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH;
 700         }
 701
 702         /*
 703          * Now set the termination based on what we found.
 704          */
 705         sxfrctl1 = ahd_inb(ahd, SXFRCTL1) & ~STPWEN;
 706         ahd->flags &= ~AHD_TERM_ENB_A;
 707         if ((termctl & FLX_TERMCTL_ENPRILOW) != 0) {
 708                 ahd->flags |= AHD_TERM_ENB_A;
 709                 sxfrctl1 |= STPWEN;
 710         }
 711         /* Must set the latch once in order to be effective. */
 712         ahd_outb(ahd, SXFRCTL1, sxfrctl1|STPWEN);
 713         ahd_outb(ahd, SXFRCTL1, sxfrctl1);
 714
 715         error = ahd_write_flexport(ahd, FLXADDR_TERMCTL, termctl);
 716         if (error != 0) {
 717                 printk("%s: Unable to set termination settings!\n",
 718                        ahd_name(ahd));
 719         } else if (bootverbose) {
 720                 printk("%s: Primary High byte termination %sabled\n",
 721                        ahd_name(ahd),
 722                        (termctl & FLX_TERMCTL_ENPRIHIGH) ? "En" : "Dis");
 723
 724                 printk("%s: Primary Low byte termination %sabled\n",
 725                        ahd_name(ahd),
 726                        (termctl & FLX_TERMCTL_ENPRILOW) ? "En" : "Dis");
 727
 728                 printk("%s: Secondary High byte termination %sabled\n",
 729                        ahd_name(ahd),
 730                        (termctl & FLX_TERMCTL_ENSECHIGH) ? "En" : "Dis");
 731
 732                 printk("%s: Secondary Low byte termination %sabled\n",
 733                        ahd_name(ahd),
 734                        (termctl & FLX_TERMCTL_ENSECLOW) ? "En" : "Dis");
 735         }
 736         return;
 737 }
 738
 739 #define DPE     0x80
 740 #define SSE     0x40
 741 #define RMA     0x20
 742 #define RTA     0x10
 743 #define STA     0x08
 744 #define DPR     0x01
 745
 746 static const char *split_status_source[] =
 747 {
 748         "DFF0",
 749         "DFF1",
 750         "OVLY",
 751         "CMC",
 752 };
 753
 754 static const char *pci_status_source[] =
 755 {
 756         "DFF0",
 757         "DFF1",
 758         "SG",
 759         "CMC",
 760         "OVLY",
 761         "NONE",
 762         "MSI",
 763         "TARG"
 764 };
 765
 766 static const char *split_status_strings[] =
 767 {
 768         "%s: Received split response in %s.\n",
 769         "%s: Received split completion error message in %s\n",
 770         "%s: Receive overrun in %s\n",
 771         "%s: Count not complete in %s\n",
 772         "%s: Split completion data bucket in %s\n",
 773         "%s: Split completion address error in %s\n",
 774         "%s: Split completion byte count error in %s\n",
 775         "%s: Signaled Target-abort to early terminate a split in %s\n"
 776 };
 777
 778 static const char *pci_status_strings[] =
 779 {
 780         "%s: Data Parity Error has been reported via PERR# in %s\n",
 781         "%s: Target initial wait state error in %s\n",
 782         "%s: Split completion read data parity error in %s\n",
 783         "%s: Split completion address attribute parity error in %s\n",
 784         "%s: Received a Target Abort in %s\n",
 785         "%s: Received a Master Abort in %s\n",
 786         "%s: Signal System Error Detected in %s\n",
 787         "%s: Address or Write Phase Parity Error Detected in %s.\n"
 788 };
 789
 790 static void
 791 ahd_pci_intr(struct ahd_softc *ahd)
 792 {
 793         uint8_t         pci_status[8];
 794         ahd_mode_state  saved_modes;
 795         u_int           pci_status1;
 796         u_int           intstat;
 797         u_int           i;
 798         u_int           reg;
 799
 800         intstat = ahd_inb(ahd, INTSTAT);
 801
 802         if ((intstat & SPLTINT) != 0)
 803                 ahd_pci_split_intr(ahd, intstat);
 804
 805         if ((intstat & PCIINT) == 0)
 806                 return;
 807
 808         printk("%s: PCI error Interrupt\n", ahd_name(ahd));
 809         saved_modes = ahd_save_modes(ahd);
 810         ahd_dump_card_state(ahd);
 811         ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
 812         for (i = 0, reg = DF0PCISTAT; i < 8; i++, reg++) {
 813
 814                 if (i == 5)
 815                         continue;
 816                 pci_status[i] = ahd_inb(ahd, reg);
 817                 /* Clear latched errors.  So our interrupt deasserts. */
 818                 ahd_outb(ahd, reg, pci_status[i]);
 819         }
 820
 821         for (i = 0; i < 8; i++) {
 822                 u_int bit;
 823
 824                 if (i == 5)
 825                         continue;
 826
 827                 for (bit = 0; bit < 8; bit++) {
 828
 829                         if ((pci_status[i] & (0x1 << bit)) != 0) {
 830                                 const char *s;
 831
 832                                 s = pci_status_strings[bit];
 833                                 if (i == 7/*TARG*/ && bit == 3)
 834                                         s = "%s: Signaled Target Abort\n";
 835                                 printk(s, ahd_name(ahd), pci_status_source[i]);
 836                         }
 837                 }
 838         }
 839         pci_status1 = ahd_pci_read_config(ahd->dev_softc,
 840                                           PCIR_STATUS + 1, /*bytes*/1);
 841         ahd_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1,
 842                              pci_status1, /*bytes*/1);
 843         ahd_restore_modes(ahd, saved_modes);
 844         ahd_outb(ahd, CLRINT, CLRPCIINT);
 845         ahd_unpause(ahd);
 846 }
 847
 848 static void
 849 ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat)
 850 {
 851         uint8_t         split_status[4];
 852         uint8_t         split_status1[4];
 853         uint8_t         sg_split_status[2];
 854         uint8_t         sg_split_status1[2];
 855         ahd_mode_state  saved_modes;
 856         u_int           i;
 857         uint16_t        pcix_status;
 858
 859         /*
 860          * Check for splits in all modes.  Modes 0 and 1
 861          * additionally have SG engine splits to look at.
 862          */
 863         pcix_status = ahd_pci_read_config(ahd->dev_softc, PCIXR_STATUS,
 864                                           /*bytes*/2);
 865         printk("%s: PCI Split Interrupt - PCI-X status = 0x%x\n",
 866                ahd_name(ahd), pcix_status);
 867         saved_modes = ahd_save_modes(ahd);
 868         for (i = 0; i < 4; i++) {
 869                 ahd_set_modes(ahd, i, i);
 870
 871                 split_status[i] = ahd_inb(ahd, DCHSPLTSTAT0);
 872                 split_status1[i] = ahd_inb(ahd, DCHSPLTSTAT1);
 873                 /* Clear latched errors.  So our interrupt deasserts. */
 874                 ahd_outb(ahd, DCHSPLTSTAT0, split_status[i]);
 875                 ahd_outb(ahd, DCHSPLTSTAT1, split_status1[i]);
 876                 if (i > 1)
 877                         continue;
 878                 sg_split_status[i] = ahd_inb(ahd, SGSPLTSTAT0);
 879                 sg_split_status1[i] = ahd_inb(ahd, SGSPLTSTAT1);
 880                 /* Clear latched errors.  So our interrupt deasserts. */
 881                 ahd_outb(ahd, SGSPLTSTAT0, sg_split_status[i]);
 882                 ahd_outb(ahd, SGSPLTSTAT1, sg_split_status1[i]);
 883         }
 884
 885         for (i = 0; i < 4; i++) {
 886                 u_int bit;
 887
 888                 for (bit = 0; bit < 8; bit++) {
 889
 890                         if ((split_status[i] & (0x1 << bit)) != 0)
 891                                 printk(split_status_strings[bit], ahd_name(ahd),
 892                                        split_status_source[i]);
 893
 894                         if (i > 1)
 895                                 continue;
 896
 897                         if ((sg_split_status[i] & (0x1 << bit)) != 0)
 898                                 printk(split_status_strings[bit], ahd_name(ahd), "SG");
 899                 }
 900         }
 901         /*
 902          * Clear PCI-X status bits.
 903          */
 904         ahd_pci_write_config(ahd->dev_softc, PCIXR_STATUS,
 905                              pcix_status, /*bytes*/2);
 906         ahd_outb(ahd, CLRINT, CLRSPLTINT);
 907         ahd_restore_modes(ahd, saved_modes);
 908 }
 909
 910 static int
 911 ahd_aic7901_setup(struct ahd_softc *ahd)
 912 {
 913
 914         ahd->chip = AHD_AIC7901;
 915         ahd->features = AHD_AIC7901_FE;
 916         return (ahd_aic790X_setup(ahd));
 917 }
 918
 919 static int
 920 ahd_aic7901A_setup(struct ahd_softc *ahd)
 921 {
 922
 923         ahd->chip = AHD_AIC7901A;
 924         ahd->features = AHD_AIC7901A_FE;
 925         return (ahd_aic790X_setup(ahd));
 926 }
 927
 928 static int
 929 ahd_aic7902_setup(struct ahd_softc *ahd)
 930 {
 931         ahd->chip = AHD_AIC7902;
 932         ahd->features = AHD_AIC7902_FE;
 933         return (ahd_aic790X_setup(ahd));
 934 }
 935
 936 static int
 937 ahd_aic790X_setup(struct ahd_softc *ahd)
 938 {
 939         ahd_dev_softc_t pci;
 940         u_int rev;
 941
 942         pci = ahd->dev_softc;
 943         rev = ahd_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
 944         if (rev < ID_AIC7902_PCI_REV_A4) {
 945                 printk("%s: Unable to attach to unsupported chip revision %d\n",
 946                        ahd_name(ahd), rev);
 947                 ahd_pci_write_config(pci, PCIR_COMMAND, 0, /*bytes*/2);
 948                 return (ENXIO);
 949         }
 950         ahd->channel = ahd_get_pci_function(pci) + 'A';
 951         if (rev < ID_AIC7902_PCI_REV_B0) {
 952                 /*
 953                  * Enable A series workarounds.
 954                  */
 955                 ahd->bugs |= AHD_SENT_SCB_UPDATE_BUG|AHD_ABORT_LQI_BUG
 956                           |  AHD_PKT_BITBUCKET_BUG|AHD_LONG_SETIMO_BUG
 957                           |  AHD_NLQICRC_DELAYED_BUG|AHD_SCSIRST_BUG
 958                           |  AHD_LQO_ATNO_BUG|AHD_AUTOFLUSH_BUG
 959                           |  AHD_CLRLQO_AUTOCLR_BUG|AHD_PCIX_MMAPIO_BUG
 960                           |  AHD_PCIX_CHIPRST_BUG|AHD_PCIX_SCBRAM_RD_BUG
 961                           |  AHD_PKTIZED_STATUS_BUG|AHD_PKT_LUN_BUG
 962                           |  AHD_MDFF_WSCBPTR_BUG|AHD_REG_SLOW_SETTLE_BUG
 963                           |  AHD_SET_MODE_BUG|AHD_BUSFREEREV_BUG
 964                           |  AHD_NONPACKFIFO_BUG|AHD_PACED_NEGTABLE_BUG
 965                           |  AHD_FAINT_LED_BUG;
 966
 967                 /*
 968                  * IO Cell parameter setup.
 969                  */
 970                 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29);
 971
 972                 if ((ahd->flags & AHD_HP_BOARD) == 0)
 973                         AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVA);
 974         } else {
 975                 /* This is revision B and newer. */
 976                 extern uint32_t aic79xx_slowcrc;
 977                 u_int devconfig1;
 978
 979                 ahd->features |= AHD_RTI|AHD_NEW_IOCELL_OPTS
 980                               |  AHD_NEW_DFCNTRL_OPTS|AHD_FAST_CDB_DELIVERY
 981                               |  AHD_BUSFREEREV_BUG;
 982                 ahd->bugs |= AHD_LQOOVERRUN_BUG|AHD_EARLY_REQ_BUG;
 983
 984                 /* If the user requested that the SLOWCRC bit to be set. */
 985                 if (aic79xx_slowcrc)
 986                         ahd->features |= AHD_AIC79XXB_SLOWCRC;
 987
 988                 /*
 989                  * Some issues have been resolved in the 7901B.
 990                  */
 991                 if ((ahd->features & AHD_MULTI_FUNC) != 0)
 992                         ahd->bugs |= AHD_INTCOLLISION_BUG|AHD_ABORT_LQI_BUG;
 993
 994                 /*
 995                  * IO Cell parameter setup.
 996                  */
 997                 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29);
 998                 AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVB);
 999                 AHD_SET_AMPLITUDE(ahd, AHD_AMPLITUDE_DEF);
1000
1001                 /*
1002                  * Set the PREQDIS bit for H2B which disables some workaround
1003                  * that doesn't work on regular PCI busses.
1004                  * XXX - Find out exactly what this does from the hardware
1005                  *       folks!
1006                  */
1007                 devconfig1 = ahd_pci_read_config(pci, DEVCONFIG1, /*bytes*/1);
1008                 ahd_pci_write_config(pci, DEVCONFIG1,
1009                                      devconfig1|PREQDIS, /*bytes*/1);
1010                 devconfig1 = ahd_pci_read_config(pci, DEVCONFIG1, /*bytes*/1);
1011         }
1012
1013         return (0);
1014 }