2 * Copyright (C) 2005 - 2015 Avago Technologies
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
10 * Written by: Jayamohan Kallickal (jayamohan.kallickal@avagotech.com)
12 * Contact Information:
13 * linux-drivers@avagotech.com
17 * Costa Mesa, CA 92626
20 #ifndef _BEISCSI_MAIN_
21 #define _BEISCSI_MAIN_
23 #include <linux/kernel.h>
24 #include <linux/pci.h>
25 #include <linux/if_ether.h>
27 #include <linux/ctype.h>
28 #include <linux/module.h>
29 #include <linux/aer.h>
30 #include <scsi/scsi.h>
31 #include <scsi/scsi_cmnd.h>
32 #include <scsi/scsi_device.h>
33 #include <scsi/scsi_host.h>
34 #include <scsi/iscsi_proto.h>
35 #include <scsi/libiscsi.h>
36 #include <scsi/scsi_transport_iscsi.h>
38 #define DRV_NAME "be2iscsi"
39 #define BUILD_STR "10.4.114.0"
40 #define BE_NAME "Avago Technologies OneConnect" \
41 "Open-iSCSI Driver version" BUILD_STR
42 #define DRV_DESC BE_NAME " " "Driver"
44 #define BE_VENDOR_ID 0x19A2
45 #define ELX_VENDOR_ID 0x10DF
46 /* DEVICE ID's for BE2 */
47 #define BE_DEVICE_ID1 0x212
48 #define OC_DEVICE_ID1 0x702
49 #define OC_DEVICE_ID2 0x703
51 /* DEVICE ID's for BE3 */
52 #define BE_DEVICE_ID2 0x222
53 #define OC_DEVICE_ID3 0x712
55 /* DEVICE ID for SKH */
56 #define OC_SKH_ID1 0x722
58 #define BE2_IO_DEPTH 1024
59 #define BE2_MAX_SESSIONS 256
60 #define BE2_CMDS_PER_CXN 128
62 #define BE2_NOPOUT_REQ 16
64 #define BE2_DEFPDU_HDR_SZ 64
65 #define BE2_DEFPDU_DATA_SZ 8192
68 #define BEISCSI_MAX_NUM_CPUS 7
70 #define BEISCSI_VER_STRLEN 32
72 #define BEISCSI_SGLIST_ELEMENTS 30
74 #define BEISCSI_CMD_PER_LUN 128 /* scsi_host->cmd_per_lun */
75 #define BEISCSI_MAX_SECTORS 1024 /* scsi_host->max_sectors */
76 #define BEISCSI_TEMPLATE_HDR_PER_CXN_SIZE 128 /* Template size per cxn */
78 #define BEISCSI_MAX_CMD_LEN 16 /* scsi_host->max_cmd_len */
79 #define BEISCSI_NUM_MAX_LUN 256 /* scsi_host->max_lun */
80 #define BEISCSI_NUM_DEVICES_SUPPORTED 0x01
81 #define BEISCSI_MAX_FRAGS_INIT 192
82 #define BE_NUM_MSIX_ENTRIES 1
84 #define MPU_EP_CONTROL 0
85 #define MPU_EP_SEMAPHORE 0xac
86 #define BE2_SOFT_RESET 0x5c
87 #define BE2_PCI_ONLINE0 0xb0
88 #define BE2_PCI_ONLINE1 0xb4
89 #define BE2_SET_RESET 0x80
90 #define BE2_MPU_IRAM_ONLINE 0x00000080
92 #define BE_SENSE_INFO_SIZE 258
93 #define BE_ISCSI_PDU_HEADER_SIZE 64
94 #define BE_MIN_MEM_SIZE 16384
95 #define MAX_CMD_SZ 65536
96 #define IIOC_SCSI_DATA 0x05 /* Write Operation */
98 #define INVALID_SESS_HANDLE 0xFFFFFFFF
103 #define BE_ADAPTER_LINK_UP 0x001
104 #define BE_ADAPTER_LINK_DOWN 0x002
105 #define BE_ADAPTER_PCI_ERR 0x004
106 #define BE_ADAPTER_STATE_SHUTDOWN 0x008
107 #define BE_ADAPTER_CHECK_BOOT 0x010
110 #define BEISCSI_CLEAN_UNLOAD 0x01
111 #define BEISCSI_EEH_UNLOAD 0x02
113 * hardware needs the async PDU buffers to be posted in multiples of 8
114 * So have atleast 8 of them by default
117 #define HWI_GET_ASYNC_PDU_CTX(phwi, ulp_num) \
118 (phwi->phwi_ctxt->pasync_ctx[ulp_num])
120 /********* Memory BAR register ************/
121 #define PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET 0xfc
123 * Host Interrupt Enable, if set interrupts are enabled although "PCI Interrupt
124 * Disable" may still globally block interrupts in addition to individual
125 * interrupt masks; a mechanism for the device driver to block all interrupts
126 * atomically without having to arbitrate for the PCI Interrupt Disable bit
129 #define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK (1 << 29) /* bit 29 */
131 /********* ISR0 Register offset **********/
132 #define CEV_ISR0_OFFSET 0xC18
133 #define CEV_ISR_SIZE 4
136 * Macros for reading/writing a protection domain or CSR registers
140 #define DB_TXULP0_OFFSET 0x40
141 #define DB_RXULP0_OFFSET 0xA0
142 /********* Event Q door bell *************/
143 #define DB_EQ_OFFSET DB_CQ_OFFSET
144 #define DB_EQ_RING_ID_LOW_MASK 0x1FF /* bits 0 - 8 */
145 /* Clear the interrupt for this eq */
146 #define DB_EQ_CLR_SHIFT (9) /* bit 9 */
148 #define DB_EQ_EVNT_SHIFT (10) /* bit 10 */
149 /* Higher Order EQ_ID bit */
150 #define DB_EQ_RING_ID_HIGH_MASK 0x1F /* bits 11 - 15 */
151 #define DB_EQ_HIGH_SET_SHIFT 11
152 #define DB_EQ_HIGH_FEILD_SHIFT 9
153 /* Number of event entries processed */
154 #define DB_EQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
156 #define DB_EQ_REARM_SHIFT (29) /* bit 29 */
158 /********* Compl Q door bell *************/
159 #define DB_CQ_OFFSET 0x120
160 #define DB_CQ_RING_ID_LOW_MASK 0x3FF /* bits 0 - 9 */
161 /* Higher Order CQ_ID bit */
162 #define DB_CQ_RING_ID_HIGH_MASK 0x1F /* bits 11 - 15 */
163 #define DB_CQ_HIGH_SET_SHIFT 11
164 #define DB_CQ_HIGH_FEILD_SHIFT 10
166 /* Number of event entries processed */
167 #define DB_CQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
169 #define DB_CQ_REARM_SHIFT (29) /* bit 29 */
171 #define GET_HWI_CONTROLLER_WS(pc) (pc->phwi_ctrlr)
172 #define HWI_GET_DEF_BUFQ_ID(pc, ulp_num) (((struct hwi_controller *)\
173 (GET_HWI_CONTROLLER_WS(pc)))->default_pdu_data[ulp_num].id)
174 #define HWI_GET_DEF_HDRQ_ID(pc, ulp_num) (((struct hwi_controller *)\
175 (GET_HWI_CONTROLLER_WS(pc)))->default_pdu_hdr[ulp_num].id)
177 #define PAGES_REQUIRED(x) \
178 ((x < PAGE_SIZE) ? 1 : ((x + PAGE_SIZE - 1) / PAGE_SIZE))
180 #define BEISCSI_MSI_NAME 20 /* size of msi_name string */
182 #define MEM_DESCR_OFFSET 8
183 #define BEISCSI_DEFQ_HDR 1
184 #define BEISCSI_DEFQ_DATA 0
186 HWI_MEM_ADDN_CONTEXT,
191 HWI_MEM_TEMPLATE_HDR_ULP0,
192 HWI_MEM_ASYNC_HEADER_BUF_ULP0, /* 6 */
193 HWI_MEM_ASYNC_DATA_BUF_ULP0,
194 HWI_MEM_ASYNC_HEADER_RING_ULP0,
195 HWI_MEM_ASYNC_DATA_RING_ULP0,
196 HWI_MEM_ASYNC_HEADER_HANDLE_ULP0,
197 HWI_MEM_ASYNC_DATA_HANDLE_ULP0, /* 11 */
198 HWI_MEM_ASYNC_PDU_CONTEXT_ULP0,
199 HWI_MEM_TEMPLATE_HDR_ULP1,
200 HWI_MEM_ASYNC_HEADER_BUF_ULP1, /* 14 */
201 HWI_MEM_ASYNC_DATA_BUF_ULP1,
202 HWI_MEM_ASYNC_HEADER_RING_ULP1,
203 HWI_MEM_ASYNC_DATA_RING_ULP1,
204 HWI_MEM_ASYNC_HEADER_HANDLE_ULP1,
205 HWI_MEM_ASYNC_DATA_HANDLE_ULP1, /* 19 */
206 HWI_MEM_ASYNC_PDU_CONTEXT_ULP1,
207 ISCSI_MEM_GLOBAL_HEADER,
211 struct be_bus_address32 {
212 unsigned int address_lo;
213 unsigned int address_hi;
216 struct be_bus_address64 {
217 unsigned long long address;
220 struct be_bus_address {
222 struct be_bus_address32 a32;
223 struct be_bus_address64 a64;
228 struct be_bus_address bus_address; /* Bus address of location */
229 void *virtual_address; /* virtual address to the location */
230 unsigned int size; /* Size required by memory block */
233 struct be_mem_descriptor {
234 unsigned int index; /* Index of this memory parameter */
235 unsigned int category; /* type indicates cached/non-cached */
236 unsigned int num_elements; /* number of elements in this
239 unsigned int alignment_mask; /* Alignment mask for this block */
240 unsigned int size_in_bytes; /* Size required by memory block */
241 struct mem_array *mem_array;
245 unsigned int sgl_index;
248 struct iscsi_task *task;
249 struct iscsi_sge *pfrag;
252 struct hba_parameters {
253 unsigned int ios_per_ctrl;
254 unsigned int cxns_per_ctrl;
255 unsigned int asyncpdus_per_ctrl;
256 unsigned int icds_per_ctrl;
257 unsigned int num_sge_per_io;
258 unsigned int defpdu_hdr_sz;
259 unsigned int defpdu_data_sz;
260 unsigned int num_cq_entries;
261 unsigned int num_eq_entries;
262 unsigned int wrbs_per_cxn;
263 unsigned int crashmode;
264 unsigned int hba_num;
266 unsigned int mgmt_ws_sz;
267 unsigned int hwi_ws_sz;
272 unsigned int dbg_flags;
273 unsigned int num_cxn;
275 unsigned int eq_timer;
277 * These are calculated from other params. They're here
280 unsigned int num_mcc_pages;
281 unsigned int num_mcc_cq_pages;
282 unsigned int num_cq_pages;
283 unsigned int num_eq_pages;
285 unsigned int num_async_pdu_buf_pages;
286 unsigned int num_async_pdu_buf_sgl_pages;
287 unsigned int num_async_pdu_buf_cq_pages;
289 unsigned int num_async_pdu_hdr_pages;
290 unsigned int num_async_pdu_hdr_sgl_pages;
291 unsigned int num_async_pdu_hdr_cq_pages;
293 unsigned int num_sge;
296 struct invalidate_command_table {
301 #define BEISCSI_GET_ULP_FROM_CRI(phwi_ctrlr, cri) \
302 (phwi_ctrlr->wrb_context[cri].ulp_num)
303 struct hwi_wrb_context {
304 struct list_head wrb_handle_list;
305 struct list_head wrb_handle_drvr_list;
306 struct wrb_handle **pwrb_handle_base;
307 struct wrb_handle **pwrb_handle_basestd;
308 struct iscsi_wrb *plast_wrb;
309 unsigned short alloc_index;
310 unsigned short free_index;
311 unsigned short wrb_handles_available;
313 uint8_t ulp_num; /* ULP to which CID binded */
314 uint16_t register_set;
315 uint16_t doorbell_format;
316 uint32_t doorbell_offset;
319 struct ulp_cid_info {
320 unsigned short *cid_array;
321 unsigned short avlbl_cids;
322 unsigned short cid_alloc;
323 unsigned short cid_free;
327 #define chip_be2(phba) (phba->generation == BE_GEN2)
328 #define chip_be3_r(phba) (phba->generation == BE_GEN3)
329 #define is_chip_be2_be3r(phba) (chip_be3_r(phba) || (chip_be2(phba)))
331 #define BEISCSI_ULP0 0
332 #define BEISCSI_ULP1 1
333 #define BEISCSI_ULP_COUNT 2
334 #define BEISCSI_ULP0_LOADED 0x01
335 #define BEISCSI_ULP1_LOADED 0x02
337 #define BEISCSI_ULP_AVLBL_CID(phba, ulp_num) \
338 (((struct ulp_cid_info *)phba->cid_array_info[ulp_num])->avlbl_cids)
339 #define BEISCSI_ULP0_AVLBL_CID(phba) \
340 BEISCSI_ULP_AVLBL_CID(phba, BEISCSI_ULP0)
341 #define BEISCSI_ULP1_AVLBL_CID(phba) \
342 BEISCSI_ULP_AVLBL_CID(phba, BEISCSI_ULP1)
345 struct hba_parameters params;
346 struct hwi_controller *phwi_ctrlr;
347 unsigned int mem_req[SE_MEM_MAX];
348 /* PCI BAR mapped addresses */
349 u8 __iomem *csr_va; /* CSR */
350 u8 __iomem *db_va; /* Door Bell */
351 u8 __iomem *pci_va; /* PCI Config */
352 struct be_bus_address csr_pa; /* CSR */
353 struct be_bus_address db_pa; /* CSR */
354 struct be_bus_address pci_pa; /* CSR */
355 /* PCI representation of our HBA */
356 struct pci_dev *pcidev;
357 unsigned short asic_revision;
358 unsigned int num_cpus;
359 unsigned int nxt_cqid;
360 struct msix_entry msix_entries[MAX_CPUS];
361 char *msi_name[MAX_CPUS];
363 struct be_mem_descriptor *init_mem;
365 unsigned short io_sgl_alloc_index;
366 unsigned short io_sgl_free_index;
367 unsigned short io_sgl_hndl_avbl;
368 struct sgl_handle **io_sgl_hndl_base;
369 struct sgl_handle **sgl_hndl_array;
371 unsigned short eh_sgl_alloc_index;
372 unsigned short eh_sgl_free_index;
373 unsigned short eh_sgl_hndl_avbl;
374 struct sgl_handle **eh_sgl_hndl_base;
375 spinlock_t io_sgl_lock;
376 spinlock_t mgmt_sgl_lock;
378 spinlock_t async_pdu_lock;
380 struct list_head hba_queue;
381 #define BE_MAX_SESSION 2048
382 #define BE_SET_CID_TO_CRI(cri_index, cid) \
383 (phba->cid_to_cri_map[cid] = cri_index)
384 #define BE_GET_CRI_FROM_CID(cid) (phba->cid_to_cri_map[cid])
385 unsigned short cid_to_cri_map[BE_MAX_SESSION];
386 struct ulp_cid_info *cid_array_info[BEISCSI_ULP_COUNT];
387 struct iscsi_endpoint **ep_array;
388 struct beiscsi_conn **conn_table;
389 struct iscsi_boot_kset *boot_kset;
390 struct Scsi_Host *shost;
391 struct iscsi_iface *ipv4_iface;
392 struct iscsi_iface *ipv6_iface;
395 * group together since they are used most frequently
396 * for cid to cri conversion
398 unsigned int phys_port;
399 unsigned int eqid_count;
400 unsigned int cqid_count;
401 unsigned int iscsi_cid_start[BEISCSI_ULP_COUNT];
402 #define BEISCSI_GET_CID_COUNT(phba, ulp_num) \
403 (phba->fw_config.iscsi_cid_count[ulp_num])
404 unsigned int iscsi_cid_count[BEISCSI_ULP_COUNT];
405 unsigned int iscsi_icd_count[BEISCSI_ULP_COUNT];
406 unsigned int iscsi_icd_start[BEISCSI_ULP_COUNT];
407 unsigned int iscsi_chain_start[BEISCSI_ULP_COUNT];
408 unsigned int iscsi_chain_count[BEISCSI_ULP_COUNT];
410 unsigned short iscsi_features;
411 uint16_t dual_ulp_aware;
412 unsigned long ulp_supported;
418 struct delayed_work beiscsi_hw_check_task;
421 u8 mac_address[ETH_ALEN];
422 char fw_ver_str[BEISCSI_VER_STRLEN];
424 struct workqueue_struct *wq; /* The actuak work queue */
425 struct be_ctrl_info ctrl;
426 unsigned int generation;
427 unsigned int interface_handle;
428 struct mgmt_session_info boot_sess;
429 struct invalidate_command_table inv_tbl[128];
431 struct be_aic_obj aic_obj[MAX_CPUS];
432 unsigned int attr_log_enable;
433 int (*iotask_fn)(struct iscsi_task *,
434 struct scatterlist *sg,
435 uint32_t num_sg, uint32_t xferlen,
439 struct beiscsi_session {
440 struct pci_pool *bhs_pool;
444 * struct beiscsi_conn - iscsi connection structure
446 struct beiscsi_conn {
447 struct iscsi_conn *conn;
448 struct beiscsi_hba *phba;
451 u32 beiscsi_conn_cid;
452 struct beiscsi_endpoint *ep;
453 unsigned short login_in_progress;
454 struct wrb_handle *plogin_wrb_handle;
455 struct sgl_handle *plogin_sgl_handle;
456 struct beiscsi_session *beiscsi_sess;
457 struct iscsi_task *task;
460 /* This structure is used by the chip */
461 struct pdu_data_out {
465 * Pseudo amap definition in which each bit of the actual structure is defined
466 * as a byte: used to calculate offset/shift/mask of each field
468 struct amap_pdu_data_out {
469 u8 opcode[6]; /* opcode */
470 u8 rsvd0[2]; /* should be 0 */
472 u8 final_bit; /* F bit */
474 u8 ahs_length[8]; /* no AHS */
476 u8 data_len_lo[16]; /* DataSegmentLength */
478 u8 itt[32]; /* ITT; initiator task tag */
479 u8 ttt[32]; /* TTT; valid for R2T or 0xffffffff */
484 u8 buffer_offset[32];
489 struct iscsi_scsi_req iscsi_hdr;
490 unsigned char pad1[16];
491 struct pdu_data_out iscsi_data_pdu;
492 unsigned char pad2[BE_SENSE_INFO_SIZE -
493 sizeof(struct pdu_data_out)];
496 struct beiscsi_io_task {
497 struct wrb_handle *pwrb_handle;
498 struct sgl_handle *psgl_handle;
499 struct beiscsi_conn *conn;
500 struct scsi_cmnd *scsi_cmnd;
504 unsigned short header_len;
506 struct be_cmd_bhs *cmd_bhs;
507 struct be_bus_address bhs_pa;
508 unsigned short bhs_len;
509 dma_addr_t mtask_addr;
510 uint32_t mtask_data_count;
514 struct be_nonio_bhs {
515 struct iscsi_hdr iscsi_hdr;
516 unsigned char pad1[16];
517 struct pdu_data_out iscsi_data_pdu;
518 unsigned char pad2[BE_SENSE_INFO_SIZE -
519 sizeof(struct pdu_data_out)];
522 struct be_status_bhs {
523 struct iscsi_scsi_req iscsi_hdr;
524 unsigned char pad1[16];
526 * The plus 2 below is to hold the sense info length that gets
529 unsigned char sense_info[BE_SENSE_INFO_SIZE];
537 * Pseudo amap definition in which each bit of the actual structure is defined
538 * as a byte: used to calculate offset/shift/mask of each field
540 struct amap_iscsi_sge {
543 u8 sge_offset[22]; /* DWORD 2 */
544 u8 rsvd0[9]; /* DWORD 2 */
545 u8 last_sge; /* DWORD 2 */
546 u8 len[17]; /* DWORD 3 */
547 u8 rsvd1[15]; /* DWORD 3 */
550 struct beiscsi_offload_params {
554 #define OFFLD_PARAMS_ERL 0x00000003
555 #define OFFLD_PARAMS_DDE 0x00000004
556 #define OFFLD_PARAMS_HDE 0x00000008
557 #define OFFLD_PARAMS_IR2T 0x00000010
558 #define OFFLD_PARAMS_IMD 0x00000020
559 #define OFFLD_PARAMS_DATA_SEQ_INORDER 0x00000040
560 #define OFFLD_PARAMS_PDU_SEQ_INORDER 0x00000080
561 #define OFFLD_PARAMS_MAX_R2T 0x00FFFF00
564 * Pseudo amap definition in which each bit of the actual structure is defined
565 * as a byte: used to calculate offset/shift/mask of each field
567 struct amap_beiscsi_offload_params {
568 u8 max_burst_length[32];
569 u8 max_send_data_segment_length[32];
570 u8 first_burst_length[32];
576 u8 data_seq_inorder[1];
577 u8 pdu_seq_inorder[1];
581 u8 max_recv_data_segment_length[32];
584 /* void hwi_complete_drvr_msgs(struct beiscsi_conn *beiscsi_conn,
585 struct beiscsi_hba *phba, struct sol_cqe *psol);*/
587 struct async_pdu_handle {
588 struct list_head link;
589 struct be_bus_address pa;
591 unsigned int consumed;
593 unsigned char is_header;
595 unsigned long buffer_len;
598 struct hwi_async_entry {
600 unsigned char hdr_received;
601 unsigned char hdr_len;
602 unsigned short bytes_received;
603 unsigned int bytes_needed;
604 struct list_head list;
607 struct list_head header_busy_list;
608 struct list_head data_busy_list;
611 struct hwi_async_pdu_context {
613 struct be_bus_address pa_base;
616 struct async_pdu_handle *handle_base;
618 unsigned int host_write_ptr;
619 unsigned int ep_read_ptr;
620 unsigned int writables;
622 unsigned int free_entries;
623 unsigned int busy_entries;
625 struct list_head free_list;
629 struct be_bus_address pa_base;
632 struct async_pdu_handle *handle_base;
634 unsigned int host_write_ptr;
635 unsigned int ep_read_ptr;
636 unsigned int writables;
638 unsigned int free_entries;
639 unsigned int busy_entries;
640 struct list_head free_list;
643 unsigned int buffer_size;
644 unsigned int num_entries;
645 #define BE_GET_ASYNC_CRI_FROM_CID(cid) (pasync_ctx->cid_to_async_cri_map[cid])
646 unsigned short cid_to_async_cri_map[BE_MAX_SESSION];
648 * This is a varying size list! Do not add anything
651 struct hwi_async_entry *async_entry;
654 #define PDUCQE_CODE_MASK 0x0000003F
655 #define PDUCQE_DPL_MASK 0xFFFF0000
656 #define PDUCQE_INDEX_MASK 0x0000FFFF
658 struct i_t_dpdu_cqe {
663 * Pseudo amap definition in which each bit of the actual structure is defined
664 * as a byte: used to calculate offset/shift/mask of each field
666 struct amap_i_t_dpdu_cqe {
679 struct amap_i_t_dpdu_cqe_v2 {
680 u8 db_addr_hi[32]; /* DWORD 0 */
681 u8 db_addr_lo[32]; /* DWORD 1 */
682 u8 code[6]; /* DWORD 2 */
683 u8 num_cons; /* DWORD 2*/
684 u8 rsvd0[8]; /* DWORD 2 */
685 u8 dpl[17]; /* DWORD 2 */
686 u8 index[16]; /* DWORD 3 */
687 u8 cid[13]; /* DWORD 3 */
688 u8 rsvd1; /* DWORD 3 */
689 u8 final; /* DWORD 3 */
690 u8 valid; /* DWORD 3 */
693 #define CQE_VALID_MASK 0x80000000
694 #define CQE_CODE_MASK 0x0000003F
695 #define CQE_CID_MASK 0x0000FFC0
697 #define EQE_VALID_MASK 0x00000001
698 #define EQE_MAJORCODE_MASK 0x0000000E
699 #define EQE_RESID_MASK 0xFFFF0000
706 * Pseudo amap definition in which each bit of the actual structure is defined
707 * as a byte: used to calculate offset/shift/mask of each field
709 struct amap_eq_entry {
710 u8 valid; /* DWORD 0 */
711 u8 major_code[3]; /* DWORD 0 */
712 u8 minor_code[12]; /* DWORD 0 */
713 u8 resource_id[16]; /* DWORD 0 */
722 * Pseudo amap definition in which each bit of the actual structure is defined
723 * as a byte: used to calculate offset/shift/mask of each field
734 void beiscsi_process_eq(struct beiscsi_hba *phba);
740 #define WRB_TYPE_MASK 0xF0000000
741 #define SKH_WRB_TYPE_OFFSET 27
742 #define BE_WRB_TYPE_OFFSET 28
744 #define ADAPTER_SET_WRB_TYPE(pwrb, wrb_type, type_offset) \
745 (pwrb->dw[0] |= (wrb_type << type_offset))
748 * Pseudo amap definition in which each bit of the actual structure is defined
749 * as a byte: used to calculate offset/shift/mask of each field
751 struct amap_iscsi_wrb {
752 u8 lun[14]; /* DWORD 0 */
754 u8 invld; /* DWORD 0 */
755 u8 wrb_idx[8]; /* DWORD 0 */
756 u8 dsp; /* DWORD 0 */
757 u8 dmsg; /* DWORD 0 */
758 u8 undr_run; /* DWORD 0 */
759 u8 over_run; /* DWORD 0 */
760 u8 type[4]; /* DWORD 0 */
761 u8 ptr2nextwrb[8]; /* DWORD 1 */
762 u8 r2t_exp_dtl[24]; /* DWORD 1 */
763 u8 sgl_icd_idx[12]; /* DWORD 2 */
764 u8 rsvd0[20]; /* DWORD 2 */
765 u8 exp_data_sn[32]; /* DWORD 3 */
766 u8 iscsi_bhs_addr_hi[32]; /* DWORD 4 */
767 u8 iscsi_bhs_addr_lo[32]; /* DWORD 5 */
768 u8 cmdsn_itt[32]; /* DWORD 6 */
769 u8 dif_ref_tag[32]; /* DWORD 7 */
770 u8 sge0_addr_hi[32]; /* DWORD 8 */
771 u8 sge0_addr_lo[32]; /* DWORD 9 */
772 u8 sge0_offset[22]; /* DWORD 10 */
773 u8 pbs; /* DWORD 10 */
774 u8 dif_mode[2]; /* DWORD 10 */
775 u8 rsvd1[6]; /* DWORD 10 */
776 u8 sge0_last; /* DWORD 10 */
777 u8 sge0_len[17]; /* DWORD 11 */
778 u8 dif_meta_tag[14]; /* DWORD 11 */
779 u8 sge0_in_ddr; /* DWORD 11 */
780 u8 sge1_addr_hi[32]; /* DWORD 12 */
781 u8 sge1_addr_lo[32]; /* DWORD 13 */
782 u8 sge1_r2t_offset[22]; /* DWORD 14 */
783 u8 rsvd2[9]; /* DWORD 14 */
784 u8 sge1_last; /* DWORD 14 */
785 u8 sge1_len[17]; /* DWORD 15 */
786 u8 ref_sgl_icd_idx[12]; /* DWORD 15 */
787 u8 rsvd3[2]; /* DWORD 15 */
788 u8 sge1_in_ddr; /* DWORD 15 */
792 struct amap_iscsi_wrb_v2 {
793 u8 r2t_exp_dtl[25]; /* DWORD 0 */
794 u8 rsvd0[2]; /* DWORD 0*/
795 u8 type[5]; /* DWORD 0 */
796 u8 ptr2nextwrb[8]; /* DWORD 1 */
797 u8 wrb_idx[8]; /* DWORD 1 */
798 u8 lun[16]; /* DWORD 1 */
799 u8 sgl_idx[16]; /* DWORD 2 */
800 u8 ref_sgl_icd_idx[16]; /* DWORD 2 */
801 u8 exp_data_sn[32]; /* DWORD 3 */
802 u8 iscsi_bhs_addr_hi[32]; /* DWORD 4 */
803 u8 iscsi_bhs_addr_lo[32]; /* DWORD 5 */
804 u8 cq_id[16]; /* DWORD 6 */
805 u8 rsvd1[16]; /* DWORD 6 */
806 u8 cmdsn_itt[32]; /* DWORD 7 */
807 u8 sge0_addr_hi[32]; /* DWORD 8 */
808 u8 sge0_addr_lo[32]; /* DWORD 9 */
809 u8 sge0_offset[24]; /* DWORD 10 */
810 u8 rsvd2[7]; /* DWORD 10 */
811 u8 sge0_last; /* DWORD 10 */
812 u8 sge0_len[17]; /* DWORD 11 */
813 u8 rsvd3[7]; /* DWORD 11 */
814 u8 diff_enbl; /* DWORD 11 */
815 u8 u_run; /* DWORD 11 */
816 u8 o_run; /* DWORD 11 */
817 u8 invalid; /* DWORD 11 */
818 u8 dsp; /* DWORD 11 */
819 u8 dmsg; /* DWORD 11 */
820 u8 rsvd4; /* DWORD 11 */
821 u8 lt; /* DWORD 11 */
822 u8 sge1_addr_hi[32]; /* DWORD 12 */
823 u8 sge1_addr_lo[32]; /* DWORD 13 */
824 u8 sge1_r2t_offset[24]; /* DWORD 14 */
825 u8 rsvd5[7]; /* DWORD 14 */
826 u8 sge1_last; /* DWORD 14 */
827 u8 sge1_len[17]; /* DWORD 15 */
828 u8 rsvd6[15]; /* DWORD 15 */
832 struct wrb_handle *alloc_wrb_handle(struct beiscsi_hba *phba, unsigned int cid);
834 free_mgmt_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle);
836 void beiscsi_process_all_cqs(struct work_struct *work);
837 void beiscsi_free_mgmt_task_handles(struct beiscsi_conn *beiscsi_conn,
838 struct iscsi_task *task);
840 void hwi_ring_cq_db(struct beiscsi_hba *phba,
841 unsigned int id, unsigned int num_processed,
842 unsigned char rearm, unsigned char event);
844 unsigned int beiscsi_process_cq(struct be_eq_obj *pbe_eq);
846 static inline bool beiscsi_error(struct beiscsi_hba *phba)
848 return phba->ue_detected || phba->fw_timeout;
856 * Pseudo amap definition in which each bit of the actual structure is defined
857 * as a byte: used to calculate offset/shift/mask of each field
859 struct amap_pdu_nop_out {
860 u8 opcode[6]; /* opcode 0x00 */
861 u8 i_bit; /* I Bit */
862 u8 x_bit; /* reserved; should be 0 */
863 u8 fp_bit_filler1[7];
864 u8 f_bit; /* always 1 */
866 u8 ahs_length[8]; /* no AHS */
868 u8 data_len_lo[16]; /* DataSegmentLength */
870 u8 itt[32]; /* initiator id for ping or 0xffffffff */
871 u8 ttt[32]; /* target id for ping or 0xffffffff */
877 #define PDUBASE_OPCODE_MASK 0x0000003F
878 #define PDUBASE_DATALENHI_MASK 0x0000FF00
879 #define PDUBASE_DATALENLO_MASK 0xFFFF0000
886 * Pseudo amap definition in which each bit of the actual structure is defined
887 * as a byte: used to calculate offset/shift/mask of each field
889 struct amap_pdu_base {
891 u8 i_bit; /* immediate bit */
892 u8 x_bit; /* reserved, always 0 */
893 u8 reserved1[24]; /* opcode-specific fields */
894 u8 ahs_length[8]; /* length units is 4 byte words */
896 u8 data_len_lo[16]; /* DatasegmentLength */
897 u8 lun[64]; /* lun or opcode-specific fields */
898 u8 itt[32]; /* initiator task tag */
902 struct iscsi_target_context_update_wrb {
907 * Pseudo amap definition in which each bit of the actual structure is defined
908 * as a byte: used to calculate offset/shift/mask of each field
910 #define BE_TGT_CTX_UPDT_CMD 0x07
911 struct amap_iscsi_target_context_update_wrb {
912 u8 lun[14]; /* DWORD 0 */
914 u8 invld; /* DWORD 0 */
915 u8 wrb_idx[8]; /* DWORD 0 */
916 u8 dsp; /* DWORD 0 */
917 u8 dmsg; /* DWORD 0 */
918 u8 undr_run; /* DWORD 0 */
919 u8 over_run; /* DWORD 0 */
920 u8 type[4]; /* DWORD 0 */
921 u8 ptr2nextwrb[8]; /* DWORD 1 */
922 u8 max_burst_length[19]; /* DWORD 1 */
923 u8 rsvd0[5]; /* DWORD 1 */
924 u8 rsvd1[15]; /* DWORD 2 */
925 u8 max_send_data_segment_length[17]; /* DWORD 2 */
926 u8 first_burst_length[14]; /* DWORD 3 */
927 u8 rsvd2[2]; /* DWORD 3 */
928 u8 tx_wrbindex_drv_msg[8]; /* DWORD 3 */
929 u8 rsvd3[5]; /* DWORD 3 */
930 u8 session_state[3]; /* DWORD 3 */
931 u8 rsvd4[16]; /* DWORD 4 */
932 u8 tx_jumbo; /* DWORD 4 */
933 u8 hde; /* DWORD 4 */
934 u8 dde; /* DWORD 4 */
935 u8 erl[2]; /* DWORD 4 */
936 u8 domain_id[5]; /* DWORD 4 */
937 u8 mode; /* DWORD 4 */
938 u8 imd; /* DWORD 4 */
939 u8 ir2t; /* DWORD 4 */
940 u8 notpredblq[2]; /* DWORD 4 */
941 u8 compltonack; /* DWORD 4 */
942 u8 stat_sn[32]; /* DWORD 5 */
943 u8 pad_buffer_addr_hi[32]; /* DWORD 6 */
944 u8 pad_buffer_addr_lo[32]; /* DWORD 7 */
945 u8 pad_addr_hi[32]; /* DWORD 8 */
946 u8 pad_addr_lo[32]; /* DWORD 9 */
947 u8 rsvd5[32]; /* DWORD 10 */
948 u8 rsvd6[32]; /* DWORD 11 */
949 u8 rsvd7[32]; /* DWORD 12 */
950 u8 rsvd8[32]; /* DWORD 13 */
951 u8 rsvd9[32]; /* DWORD 14 */
952 u8 rsvd10[32]; /* DWORD 15 */
956 #define BEISCSI_MAX_RECV_DATASEG_LEN (64 * 1024)
957 #define BEISCSI_MAX_CXNS 1
958 struct amap_iscsi_target_context_update_wrb_v2 {
959 u8 max_burst_length[24]; /* DWORD 0 */
960 u8 rsvd0[3]; /* DWORD 0 */
961 u8 type[5]; /* DWORD 0 */
962 u8 ptr2nextwrb[8]; /* DWORD 1 */
963 u8 wrb_idx[8]; /* DWORD 1 */
964 u8 rsvd1[16]; /* DWORD 1 */
965 u8 max_send_data_segment_length[24]; /* DWORD 2 */
966 u8 rsvd2[8]; /* DWORD 2 */
967 u8 first_burst_length[24]; /* DWORD 3 */
968 u8 rsvd3[8]; /* DOWRD 3 */
969 u8 max_r2t[16]; /* DWORD 4 */
970 u8 rsvd4; /* DWORD 4 */
971 u8 hde; /* DWORD 4 */
972 u8 dde; /* DWORD 4 */
973 u8 erl[2]; /* DWORD 4 */
974 u8 rsvd5[6]; /* DWORD 4 */
975 u8 imd; /* DWORD 4 */
976 u8 ir2t; /* DWORD 4 */
977 u8 rsvd6[3]; /* DWORD 4 */
978 u8 stat_sn[32]; /* DWORD 5 */
979 u8 rsvd7[32]; /* DWORD 6 */
980 u8 rsvd8[32]; /* DWORD 7 */
981 u8 max_recv_dataseg_len[24]; /* DWORD 8 */
982 u8 rsvd9[8]; /* DWORD 8 */
983 u8 rsvd10[32]; /* DWORD 9 */
984 u8 rsvd11[32]; /* DWORD 10 */
985 u8 max_cxns[16]; /* DWORD 11 */
986 u8 rsvd12[11]; /* DWORD 11*/
987 u8 invld; /* DWORD 11 */
988 u8 rsvd13;/* DWORD 11*/
989 u8 dmsg; /* DWORD 11 */
990 u8 data_seq_inorder; /* DWORD 11 */
991 u8 pdu_seq_inorder; /* DWORD 11 */
992 u8 rsvd14[32]; /*DWORD 12 */
993 u8 rsvd15[32]; /* DWORD 13 */
994 u8 rsvd16[32]; /* DWORD 14 */
995 u8 rsvd17[32]; /* DWORD 15 */
1000 u32 pages; /* queue size in pages */
1001 u32 id; /* queue id assigned by beklib */
1002 u32 num; /* number of elements in queue */
1003 u32 cidx; /* consumer index */
1004 u32 pidx; /* producer index -- not used by most rings */
1005 u32 item_size; /* size in bytes of one object */
1006 u8 ulp_num; /* ULP to which CID binded */
1008 u16 doorbell_format;
1009 u32 doorbell_offset;
1011 void *va; /* The virtual address of the ring. This
1012 * should be last to allow 32 & 64 bit debugger
1013 * extensions to work.
1017 struct hwi_controller {
1018 struct list_head io_sgl_list;
1019 struct list_head eh_sgl_list;
1020 struct sgl_handle *psgl_handle_base;
1021 unsigned int wrb_mem_index;
1023 struct hwi_wrb_context *wrb_context;
1024 struct mcc_wrb *pmcc_wrb_base;
1025 struct be_ring default_pdu_hdr[BEISCSI_ULP_COUNT];
1026 struct be_ring default_pdu_data[BEISCSI_ULP_COUNT];
1027 struct hwi_context_memory *phwi_ctxt;
1030 enum hwh_type_enum {
1032 HWH_TYPE_LOGOUT = 2,
1036 HWH_TYPE_LOGIN = 11,
1037 HWH_TYPE_INVALID = 0xFFFFFFFF
1041 enum hwh_type_enum type;
1042 unsigned short wrb_index;
1043 unsigned short nxt_wrb_index;
1045 struct iscsi_task *pio_handle;
1046 struct iscsi_wrb *pwrb;
1049 struct hwi_context_memory {
1050 /* Adaptive interrupt coalescing (AIC) info */
1051 u16 min_eqd; /* in usecs */
1052 u16 max_eqd; /* in usecs */
1053 u16 cur_eqd; /* in usecs */
1054 struct be_eq_obj be_eq[MAX_CPUS];
1055 struct be_queue_info be_cq[MAX_CPUS - 1];
1057 struct be_queue_info *be_wrbq;
1058 struct be_queue_info be_def_hdrq[BEISCSI_ULP_COUNT];
1059 struct be_queue_info be_def_dataq[BEISCSI_ULP_COUNT];
1060 struct hwi_async_pdu_context *pasync_ctx[BEISCSI_ULP_COUNT];
1063 /* Logging related definitions */
1064 #define BEISCSI_LOG_INIT 0x0001 /* Initialization events */
1065 #define BEISCSI_LOG_MBOX 0x0002 /* Mailbox Events */
1066 #define BEISCSI_LOG_MISC 0x0004 /* Miscllaneous Events */
1067 #define BEISCSI_LOG_EH 0x0008 /* Error Handler */
1068 #define BEISCSI_LOG_IO 0x0010 /* IO Code Path */
1069 #define BEISCSI_LOG_CONFIG 0x0020 /* CONFIG Code Path */
1070 #define BEISCSI_LOG_ISCSI 0x0040 /* SCSI/iSCSI Protocol related Logs */
1072 #define beiscsi_log(phba, level, mask, fmt, arg...) \
1074 uint32_t log_value = phba->attr_log_enable; \
1075 if (((mask) & log_value) || (level[1] <= '3')) \
1076 shost_printk(level, phba->shost, \
1077 fmt, __LINE__, ##arg); \