2 * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
6 * Linux driver for Brocade Fibre Channel Host Bus Adapter.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License (GPL) Version 2 as
10 * published by the Free Software Foundation
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
19 #include "bfa_modules.h"
20 #include "bfi_ctreg.h"
22 BFA_TRC_FILE(HAL, IOCFC_CT);
24 static u32 __ct_msix_err_vec_reg[] = {
25 HOST_MSIX_ERR_INDEX_FN0,
26 HOST_MSIX_ERR_INDEX_FN1,
27 HOST_MSIX_ERR_INDEX_FN2,
28 HOST_MSIX_ERR_INDEX_FN3,
32 bfa_hwct_msix_lpu_err_set(struct bfa_s *bfa, bfa_boolean_t msix, int vec)
34 int fn = bfa_ioc_pcifn(&bfa->ioc);
35 void __iomem *kva = bfa_ioc_bar0(&bfa->ioc);
38 writel(vec, kva + __ct_msix_err_vec_reg[fn]);
40 writel(0, kva + __ct_msix_err_vec_reg[fn]);
44 * Dummy interrupt handler for handling spurious interrupt during chip-reinit.
47 bfa_hwct_msix_dummy(struct bfa_s *bfa, int vec)
52 bfa_hwct_reginit(struct bfa_s *bfa)
54 struct bfa_iocfc_regs_s *bfa_regs = &bfa->iocfc.bfa_regs;
55 void __iomem *kva = bfa_ioc_bar0(&bfa->ioc);
56 int i, q, fn = bfa_ioc_pcifn(&bfa->ioc);
59 bfa_regs->intr_status = (kva + HOSTFN0_INT_STATUS);
60 bfa_regs->intr_mask = (kva + HOSTFN0_INT_MSK);
62 bfa_regs->intr_status = (kva + HOSTFN1_INT_STATUS);
63 bfa_regs->intr_mask = (kva + HOSTFN1_INT_MSK);
66 for (i = 0; i < BFI_IOC_MAX_CQS; i++) {
71 bfa_regs->cpe_q_pi[i] = (kva + CPE_PI_PTR_Q(q << 5));
72 bfa_regs->cpe_q_ci[i] = (kva + CPE_CI_PTR_Q(q << 5));
73 bfa_regs->cpe_q_depth[i] = (kva + CPE_DEPTH_Q(q << 5));
74 bfa_regs->cpe_q_ctrl[i] = (kva + CPE_QCTRL_Q(q << 5));
80 bfa_regs->rme_q_pi[i] = (kva + RME_PI_PTR_Q(q << 5));
81 bfa_regs->rme_q_ci[i] = (kva + RME_CI_PTR_Q(q << 5));
82 bfa_regs->rme_q_depth[i] = (kva + RME_DEPTH_Q(q << 5));
83 bfa_regs->rme_q_ctrl[i] = (kva + RME_QCTRL_Q(q << 5));
88 bfa_hwct_reqq_ack(struct bfa_s *bfa, int reqq)
92 r32 = readl(bfa->iocfc.bfa_regs.cpe_q_ctrl[reqq]);
93 writel(r32, bfa->iocfc.bfa_regs.cpe_q_ctrl[reqq]);
97 bfa_hwct_rspq_ack(struct bfa_s *bfa, int rspq)
101 r32 = readl(bfa->iocfc.bfa_regs.rme_q_ctrl[rspq]);
102 writel(r32, bfa->iocfc.bfa_regs.rme_q_ctrl[rspq]);
106 bfa_hwct_msix_getvecs(struct bfa_s *bfa, u32 *msix_vecs_bmap,
107 u32 *num_vecs, u32 *max_vec_bit)
109 *msix_vecs_bmap = (1 << BFA_MSIX_CT_MAX) - 1;
110 *max_vec_bit = (1 << (BFA_MSIX_CT_MAX - 1));
111 *num_vecs = BFA_MSIX_CT_MAX;
115 * Setup MSI-X vector for catapult
118 bfa_hwct_msix_init(struct bfa_s *bfa, int nvecs)
120 WARN_ON((nvecs != 1) && (nvecs != BFA_MSIX_CT_MAX));
123 bfa->msix.nvecs = nvecs;
124 bfa_hwct_msix_uninstall(bfa);
128 bfa_hwct_msix_install(struct bfa_s *bfa)
132 if (bfa->msix.nvecs == 0)
135 if (bfa->msix.nvecs == 1) {
136 for (i = 0; i < BFA_MSIX_CT_MAX; i++)
137 bfa->msix.handler[i] = bfa_msix_all;
141 for (i = BFA_MSIX_CPE_Q0; i <= BFA_MSIX_CPE_Q3; i++)
142 bfa->msix.handler[i] = bfa_msix_reqq;
144 for (; i <= BFA_MSIX_RME_Q3; i++)
145 bfa->msix.handler[i] = bfa_msix_rspq;
147 WARN_ON(i != BFA_MSIX_LPU_ERR);
148 bfa->msix.handler[BFA_MSIX_LPU_ERR] = bfa_msix_lpu_err;
152 bfa_hwct_msix_uninstall(struct bfa_s *bfa)
156 for (i = 0; i < BFA_MSIX_CT_MAX; i++)
157 bfa->msix.handler[i] = bfa_hwct_msix_dummy;
161 * Enable MSI-X vectors
164 bfa_hwct_isr_mode_set(struct bfa_s *bfa, bfa_boolean_t msix)
167 bfa_hwct_msix_lpu_err_set(bfa, msix, BFA_MSIX_LPU_ERR);
168 bfa_ioc_isr_mode_set(&bfa->ioc, msix);
172 bfa_hwct_msix_get_rme_range(struct bfa_s *bfa, u32 *start, u32 *end)
174 *start = BFA_MSIX_RME_Q0;
175 *end = BFA_MSIX_RME_Q3;