2 * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
6 * Linux driver for Brocade Fibre Channel Host Bus Adapter.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License (GPL) Version 2 as
10 * published by the Free Software Foundation
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
18 #include "bfa_modules.h"
19 #include "bfi_ctreg.h"
21 BFA_TRC_FILE(HAL, IOCFC_CT);
23 static u32 __ct_msix_err_vec_reg[] = {
24 HOST_MSIX_ERR_INDEX_FN0,
25 HOST_MSIX_ERR_INDEX_FN1,
26 HOST_MSIX_ERR_INDEX_FN2,
27 HOST_MSIX_ERR_INDEX_FN3,
31 bfa_hwct_msix_lpu_err_set(struct bfa_s *bfa, bfa_boolean_t msix, int vec)
33 int fn = bfa_ioc_pcifn(&bfa->ioc);
34 bfa_os_addr_t kva = bfa_ioc_bar0(&bfa->ioc);
37 bfa_reg_write(kva + __ct_msix_err_vec_reg[fn], vec);
39 bfa_reg_write(kva + __ct_msix_err_vec_reg[fn], 0);
43 * Dummy interrupt handler for handling spurious interrupt during chip-reinit.
46 bfa_hwct_msix_dummy(struct bfa_s *bfa, int vec)
51 bfa_hwct_reginit(struct bfa_s *bfa)
53 struct bfa_iocfc_regs_s *bfa_regs = &bfa->iocfc.bfa_regs;
54 bfa_os_addr_t kva = bfa_ioc_bar0(&bfa->ioc);
55 int i, q, fn = bfa_ioc_pcifn(&bfa->ioc);
58 bfa_regs->intr_status = (kva + HOSTFN0_INT_STATUS);
59 bfa_regs->intr_mask = (kva + HOSTFN0_INT_MSK);
61 bfa_regs->intr_status = (kva + HOSTFN1_INT_STATUS);
62 bfa_regs->intr_mask = (kva + HOSTFN1_INT_MSK);
65 for (i = 0; i < BFI_IOC_MAX_CQS; i++) {
70 bfa_regs->cpe_q_pi[i] = (kva + CPE_PI_PTR_Q(q << 5));
71 bfa_regs->cpe_q_ci[i] = (kva + CPE_CI_PTR_Q(q << 5));
72 bfa_regs->cpe_q_depth[i] = (kva + CPE_DEPTH_Q(q << 5));
73 bfa_regs->cpe_q_ctrl[i] = (kva + CPE_QCTRL_Q(q << 5));
79 bfa_regs->rme_q_pi[i] = (kva + RME_PI_PTR_Q(q << 5));
80 bfa_regs->rme_q_ci[i] = (kva + RME_CI_PTR_Q(q << 5));
81 bfa_regs->rme_q_depth[i] = (kva + RME_DEPTH_Q(q << 5));
82 bfa_regs->rme_q_ctrl[i] = (kva + RME_QCTRL_Q(q << 5));
87 bfa_hwct_reqq_ack(struct bfa_s *bfa, int reqq)
91 r32 = bfa_reg_read(bfa->iocfc.bfa_regs.cpe_q_ctrl[reqq]);
92 bfa_reg_write(bfa->iocfc.bfa_regs.cpe_q_ctrl[reqq], r32);
96 bfa_hwct_rspq_ack(struct bfa_s *bfa, int rspq)
100 r32 = bfa_reg_read(bfa->iocfc.bfa_regs.rme_q_ctrl[rspq]);
101 bfa_reg_write(bfa->iocfc.bfa_regs.rme_q_ctrl[rspq], r32);
105 bfa_hwct_msix_getvecs(struct bfa_s *bfa, u32 *msix_vecs_bmap,
106 u32 *num_vecs, u32 *max_vec_bit)
108 *msix_vecs_bmap = (1 << BFA_MSIX_CT_MAX) - 1;
109 *max_vec_bit = (1 << (BFA_MSIX_CT_MAX - 1));
110 *num_vecs = BFA_MSIX_CT_MAX;
114 * Setup MSI-X vector for catapult
117 bfa_hwct_msix_init(struct bfa_s *bfa, int nvecs)
119 bfa_assert((nvecs == 1) || (nvecs == BFA_MSIX_CT_MAX));
122 bfa->msix.nvecs = nvecs;
123 bfa_hwct_msix_uninstall(bfa);
127 bfa_hwct_msix_install(struct bfa_s *bfa)
131 if (bfa->msix.nvecs == 0)
134 if (bfa->msix.nvecs == 1) {
135 for (i = 0; i < BFA_MSIX_CT_MAX; i++)
136 bfa->msix.handler[i] = bfa_msix_all;
140 for (i = BFA_MSIX_CPE_Q0; i <= BFA_MSIX_CPE_Q3; i++)
141 bfa->msix.handler[i] = bfa_msix_reqq;
143 for (; i <= BFA_MSIX_RME_Q3; i++)
144 bfa->msix.handler[i] = bfa_msix_rspq;
146 bfa_assert(i == BFA_MSIX_LPU_ERR);
147 bfa->msix.handler[BFA_MSIX_LPU_ERR] = bfa_msix_lpu_err;
151 bfa_hwct_msix_uninstall(struct bfa_s *bfa)
155 for (i = 0; i < BFA_MSIX_CT_MAX; i++)
156 bfa->msix.handler[i] = bfa_hwct_msix_dummy;
160 * Enable MSI-X vectors
163 bfa_hwct_isr_mode_set(struct bfa_s *bfa, bfa_boolean_t msix)
166 bfa_hwct_msix_lpu_err_set(bfa, msix, BFA_MSIX_LPU_ERR);
167 bfa_ioc_isr_mode_set(&bfa->ioc, msix);
171 bfa_hwct_msix_get_rme_range(struct bfa_s *bfa, u32 *start, u32 *end)
173 *start = BFA_MSIX_RME_Q0;
174 *end = BFA_MSIX_RME_Q3;