1 /************************************************************************
3 * ICP vortex GmbH: GDT ISA/EISA/PCI Disk Array Controllers *
4 * Intel Corporation: Storage RAID Controllers *
7 * Copyright (C) 1995-06 ICP vortex GmbH, Achim Leubner *
8 * Copyright (C) 2002-04 Intel Corporation *
9 * Copyright (C) 2003-06 Adaptec Inc. *
10 * <achim_leubner@adaptec.com> *
13 * Boji Tony Kannanthanam <boji.t.kannanthanam@intel.com> *
14 * Johannes Dinner <johannes_dinner@adaptec.com> *
16 * This program is free software; you can redistribute it and/or modify *
17 * it under the terms of the GNU General Public License as published *
18 * by the Free Software Foundation; either version 2 of the License, *
19 * or (at your option) any later version. *
21 * This program is distributed in the hope that it will be useful, *
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
24 * GNU General Public License for more details. *
26 * You should have received a copy of the GNU General Public License *
27 * along with this kernel; if not, write to the Free Software *
28 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. *
30 * Linux kernel 2.6.x supported *
32 ************************************************************************/
34 /* All GDT Disk Array Controllers are fully supported by this driver.
35 * This includes the PCI/EISA/ISA SCSI Disk Array Controllers and the
36 * PCI Fibre Channel Disk Array Controllers. See gdth.h for a complete
37 * list of all controller types.
39 * If you have one or more GDT3000/3020 EISA controllers with
40 * controller BIOS disabled, you have to set the IRQ values with the
41 * command line option "gdth=irq1,irq2,...", where the irq1,irq2,... are
42 * the IRQ values for the EISA controllers.
44 * After the optional list of IRQ values, other possible
45 * command line options are:
46 * disable:Y disable driver
47 * disable:N enable driver
48 * reserve_mode:0 reserve no drives for the raw service
49 * reserve_mode:1 reserve all not init., removable drives
50 * reserve_mode:2 reserve all not init. drives
51 * reserve_list:h,b,t,l,h,b,t,l,... reserve particular drive(s) with
52 * h- controller no., b- channel no.,
53 * t- target ID, l- LUN
54 * reverse_scan:Y reverse scan order for PCI controllers
55 * reverse_scan:N scan PCI controllers like BIOS
56 * max_ids:x x - target ID count per channel (1..MAXID)
57 * rescan:Y rescan all channels/IDs
58 * rescan:N use all devices found until now
59 * hdr_channel:x x - number of virtual bus for host drives
60 * shared_access:Y disable driver reserve/release protocol to
61 * access a shared resource from several nodes,
62 * appropriate controller firmware required
63 * shared_access:N enable driver reserve/release protocol
64 * probe_eisa_isa:Y scan for EISA/ISA controllers
65 * probe_eisa_isa:N do not scan for EISA/ISA controllers
66 * force_dma32:Y use only 32 bit DMA mode
67 * force_dma32:N use 64 bit DMA mode, if supported
69 * The default values are: "gdth=disable:N,reserve_mode:1,reverse_scan:N,
70 * max_ids:127,rescan:N,hdr_channel:0,
71 * shared_access:Y,probe_eisa_isa:N,force_dma32:N".
72 * Here is another example: "gdth=reserve_list:0,1,2,0,0,1,3,0,rescan:Y".
74 * When loading the gdth driver as a module, the same options are available.
75 * You can set the IRQs with "IRQ=...". However, the syntax to specify the
76 * options changes slightly. You must replace all ',' between options
77 * with ' ' and all ':' with '=' and you must use
78 * '1' in place of 'Y' and '0' in place of 'N'.
80 * Default: "modprobe gdth disable=0 reserve_mode=1 reverse_scan=0
81 * max_ids=127 rescan=0 hdr_channel=0 shared_access=0
82 * probe_eisa_isa=0 force_dma32=0"
83 * The other example: "modprobe gdth reserve_list=0,1,2,0,0,1,3,0 rescan=1".
86 /* The meaning of the Scsi_Pointer members in this driver is as follows:
88 * this_residual: unused
91 * buffers_residual: unused
94 * have_data_in: unused
95 * sent_command: unused
100 /* interrupt coalescing */
101 /* #define INT_COAL */
104 #define GDTH_STATISTICS
106 #include <linux/module.h>
108 #include <linux/version.h>
109 #include <linux/kernel.h>
110 #include <linux/types.h>
111 #include <linux/pci.h>
112 #include <linux/string.h>
113 #include <linux/ctype.h>
114 #include <linux/ioport.h>
115 #include <linux/delay.h>
116 #include <linux/interrupt.h>
117 #include <linux/in.h>
118 #include <linux/proc_fs.h>
119 #include <linux/time.h>
120 #include <linux/timer.h>
121 #include <linux/dma-mapping.h>
122 #include <linux/list.h>
123 #include <linux/mutex.h>
124 #include <linux/slab.h>
127 #include <linux/mc146818rtc.h>
129 #include <linux/reboot.h>
133 #include <asm/uaccess.h>
134 #include <linux/spinlock.h>
135 #include <linux/blkdev.h>
136 #include <linux/scatterlist.h>
139 #include <scsi/scsi_host.h>
142 static DEFINE_MUTEX(gdth_mutex);
143 static void gdth_delay(int milliseconds);
144 static void gdth_eval_mapping(u32 size, u32 *cyls, int *heads, int *secs);
145 static irqreturn_t gdth_interrupt(int irq, void *dev_id);
146 static irqreturn_t __gdth_interrupt(gdth_ha_str *ha,
147 int gdth_from_wait, int* pIndex);
148 static int gdth_sync_event(gdth_ha_str *ha, int service, u8 index,
150 static int gdth_async_event(gdth_ha_str *ha);
151 static void gdth_log_event(gdth_evt_data *dvr, char *buffer);
153 static void gdth_putq(gdth_ha_str *ha, Scsi_Cmnd *scp, u8 priority);
154 static void gdth_next(gdth_ha_str *ha);
155 static int gdth_fill_raw_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp, u8 b);
156 static int gdth_special_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp);
157 static gdth_evt_str *gdth_store_event(gdth_ha_str *ha, u16 source,
158 u16 idx, gdth_evt_data *evt);
159 static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr);
160 static void gdth_readapp_event(gdth_ha_str *ha, u8 application,
162 static void gdth_clear_events(void);
164 static void gdth_copy_internal_data(gdth_ha_str *ha, Scsi_Cmnd *scp,
165 char *buffer, u16 count);
166 static int gdth_internal_cache_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp);
167 static int gdth_fill_cache_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp, u16 hdrive);
169 static void gdth_enable_int(gdth_ha_str *ha);
170 static int gdth_test_busy(gdth_ha_str *ha);
171 static int gdth_get_cmd_index(gdth_ha_str *ha);
172 static void gdth_release_event(gdth_ha_str *ha);
173 static int gdth_wait(gdth_ha_str *ha, int index,u32 time);
174 static int gdth_internal_cmd(gdth_ha_str *ha, u8 service, u16 opcode,
175 u32 p1, u64 p2,u64 p3);
176 static int gdth_search_drives(gdth_ha_str *ha);
177 static int gdth_analyse_hdrive(gdth_ha_str *ha, u16 hdrive);
179 static const char *gdth_ctr_name(gdth_ha_str *ha);
181 static int gdth_open(struct inode *inode, struct file *filep);
182 static int gdth_close(struct inode *inode, struct file *filep);
183 static long gdth_unlocked_ioctl(struct file *filep, unsigned int cmd,
186 static void gdth_flush(gdth_ha_str *ha);
187 static int gdth_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
188 static int __gdth_queuecommand(gdth_ha_str *ha, struct scsi_cmnd *scp,
189 struct gdth_cmndinfo *cmndinfo);
190 static void gdth_scsi_done(struct scsi_cmnd *scp);
193 static u8 DebugState = DEBUG_GDTH;
196 #define MAX_SERBUF 160
197 static void ser_init(void);
198 static void ser_puts(char *str);
199 static void ser_putc(char c);
200 static int ser_printk(const char *fmt, ...);
201 static char strbuf[MAX_SERBUF+1];
203 #define COM_BASE 0x2f8
205 #define COM_BASE 0x3f8
207 static void ser_init()
209 unsigned port=COM_BASE;
213 /* 19200 Baud, if 9600: outb(12,port) */
223 static void ser_puts(char *str)
228 for (ptr=str;*ptr;++ptr)
232 static void ser_putc(char c)
234 unsigned port=COM_BASE;
236 while ((inb(port+5) & 0x20)==0);
240 while ((inb(port+5) & 0x20)==0);
245 static int ser_printk(const char *fmt, ...)
251 i = vsprintf(strbuf,fmt,args);
257 #define TRACE(a) {if (DebugState==1) {ser_printk a;}}
258 #define TRACE2(a) {if (DebugState==1 || DebugState==2) {ser_printk a;}}
259 #define TRACE3(a) {if (DebugState!=0) {ser_printk a;}}
261 #else /* !__SERIAL__ */
262 #define TRACE(a) {if (DebugState==1) {printk a;}}
263 #define TRACE2(a) {if (DebugState==1 || DebugState==2) {printk a;}}
264 #define TRACE3(a) {if (DebugState!=0) {printk a;}}
273 #ifdef GDTH_STATISTICS
274 static u32 max_rq=0, max_index=0, max_sg=0;
276 static u32 max_int_coal=0;
278 static u32 act_ints=0, act_ios=0, act_stats=0, act_rq=0;
279 static struct timer_list gdth_timer;
282 #define PTR2USHORT(a) (u16)(unsigned long)(a)
283 #define GDTOFFSOF(a,b) (size_t)&(((a*)0)->b)
284 #define INDEX_OK(i,t) ((i)<ARRAY_SIZE(t))
286 #define BUS_L2P(a,b) ((b)>(a)->virt_bus ? (b-1):(b))
289 static u8 gdth_drq_tab[4] = {5,6,7,7}; /* DRQ table */
291 #if defined(CONFIG_EISA) || defined(CONFIG_ISA)
292 static u8 gdth_irq_tab[6] = {0,10,11,12,14,0}; /* IRQ table */
294 static u8 gdth_polling; /* polling if TRUE */
295 static int gdth_ctr_count = 0; /* controller count */
296 static LIST_HEAD(gdth_instances); /* controller list */
297 static u8 gdth_write_through = FALSE; /* write through */
298 static gdth_evt_str ebuffer[MAX_EVENTS]; /* event buffer */
303 #define DIN 1 /* IN data direction */
304 #define DOU 2 /* OUT data direction */
305 #define DNO DIN /* no data transfer */
306 #define DUN DIN /* unknown data direction */
307 static u8 gdth_direction_tab[0x100] = {
308 DNO,DNO,DIN,DIN,DOU,DIN,DIN,DOU,DIN,DUN,DOU,DOU,DUN,DUN,DUN,DIN,
309 DNO,DIN,DIN,DOU,DIN,DOU,DNO,DNO,DOU,DNO,DIN,DNO,DIN,DOU,DNO,DUN,
310 DIN,DUN,DIN,DUN,DOU,DIN,DUN,DUN,DIN,DIN,DOU,DNO,DUN,DIN,DOU,DOU,
311 DOU,DOU,DOU,DNO,DIN,DNO,DNO,DIN,DOU,DOU,DOU,DOU,DIN,DOU,DIN,DOU,
312 DOU,DOU,DIN,DIN,DIN,DNO,DUN,DNO,DNO,DNO,DUN,DNO,DOU,DIN,DUN,DUN,
313 DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DIN,DUN,DUN,DUN,DUN,DUN,
314 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
315 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
316 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,
317 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN,
318 DUN,DUN,DUN,DUN,DUN,DNO,DNO,DUN,DIN,DNO,DOU,DUN,DNO,DUN,DOU,DOU,
319 DOU,DOU,DOU,DNO,DUN,DIN,DOU,DIN,DIN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
320 DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
321 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
322 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,
323 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN
326 /* LILO and modprobe/insmod parameters */
327 /* IRQ list for GDT3000/3020 EISA controllers */
328 static int irq[MAXHA] __initdata =
329 {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
330 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
331 /* disable driver flag */
332 static int disable __initdata = 0;
334 static int reserve_mode = 1;
336 static int reserve_list[MAX_RES_ARGS] =
337 {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
338 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
339 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
340 /* scan order for PCI controllers */
341 static int reverse_scan = 0;
342 /* virtual channel for the host drives */
343 static int hdr_channel = 0;
344 /* max. IDs per channel */
345 static int max_ids = MAXID;
347 static int rescan = 0;
349 static int shared_access = 1;
350 /* enable support for EISA and ISA controllers */
351 static int probe_eisa_isa = 0;
352 /* 64 bit DMA mode, support for drives > 2 TB, if force_dma32 = 0 */
353 static int force_dma32 = 0;
355 /* parameters for modprobe/insmod */
356 module_param_array(irq, int, NULL, 0);
357 module_param(disable, int, 0);
358 module_param(reserve_mode, int, 0);
359 module_param_array(reserve_list, int, NULL, 0);
360 module_param(reverse_scan, int, 0);
361 module_param(hdr_channel, int, 0);
362 module_param(max_ids, int, 0);
363 module_param(rescan, int, 0);
364 module_param(shared_access, int, 0);
365 module_param(probe_eisa_isa, int, 0);
366 module_param(force_dma32, int, 0);
367 MODULE_AUTHOR("Achim Leubner");
368 MODULE_LICENSE("GPL");
370 /* ioctl interface */
371 static const struct file_operations gdth_fops = {
372 .unlocked_ioctl = gdth_unlocked_ioctl,
374 .release = gdth_close,
375 .llseek = noop_llseek,
378 #include "gdth_proc.h"
379 #include "gdth_proc.c"
381 static gdth_ha_str *gdth_find_ha(int hanum)
385 list_for_each_entry(ha, &gdth_instances, list)
386 if (hanum == ha->hanum)
392 static struct gdth_cmndinfo *gdth_get_cmndinfo(gdth_ha_str *ha)
394 struct gdth_cmndinfo *priv = NULL;
398 spin_lock_irqsave(&ha->smp_lock, flags);
400 for (i=0; i<GDTH_MAXCMDS; ++i) {
401 if (ha->cmndinfo[i].index == 0) {
402 priv = &ha->cmndinfo[i];
403 memset(priv, 0, sizeof(*priv));
409 spin_unlock_irqrestore(&ha->smp_lock, flags);
414 static void gdth_put_cmndinfo(struct gdth_cmndinfo *priv)
420 static void gdth_delay(int milliseconds)
422 if (milliseconds == 0) {
425 mdelay(milliseconds);
429 static void gdth_scsi_done(struct scsi_cmnd *scp)
431 struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
432 int internal_command = cmndinfo->internal_command;
434 TRACE2(("gdth_scsi_done()\n"));
436 gdth_put_cmndinfo(cmndinfo);
437 scp->host_scribble = NULL;
439 if (internal_command)
440 complete((struct completion *)scp->request);
445 int __gdth_execute(struct scsi_device *sdev, gdth_cmd_str *gdtcmd, char *cmnd,
446 int timeout, u32 *info)
448 gdth_ha_str *ha = shost_priv(sdev->host);
450 struct gdth_cmndinfo cmndinfo;
451 DECLARE_COMPLETION_ONSTACK(wait);
454 scp = kzalloc(sizeof(*scp), GFP_KERNEL);
458 scp->sense_buffer = kzalloc(SCSI_SENSE_BUFFERSIZE, GFP_KERNEL);
459 if (!scp->sense_buffer) {
465 memset(&cmndinfo, 0, sizeof(cmndinfo));
467 /* use request field to save the ptr. to completion struct. */
468 scp->request = (struct request *)&wait;
471 cmndinfo.priority = IOCTL_PRI;
472 cmndinfo.internal_cmd_str = gdtcmd;
473 cmndinfo.internal_command = 1;
475 TRACE(("__gdth_execute() cmd 0x%x\n", scp->cmnd[0]));
476 __gdth_queuecommand(ha, scp, &cmndinfo);
478 wait_for_completion(&wait);
480 rval = cmndinfo.status;
482 *info = cmndinfo.info;
483 kfree(scp->sense_buffer);
488 int gdth_execute(struct Scsi_Host *shost, gdth_cmd_str *gdtcmd, char *cmnd,
489 int timeout, u32 *info)
491 struct scsi_device *sdev = scsi_get_host_dev(shost);
492 int rval = __gdth_execute(sdev, gdtcmd, cmnd, timeout, info);
494 scsi_free_host_dev(sdev);
498 static void gdth_eval_mapping(u32 size, u32 *cyls, int *heads, int *secs)
500 *cyls = size /HEADS/SECS;
501 if (*cyls <= MAXCYLS) {
504 } else { /* too high for 64*32 */
505 *cyls = size /MEDHEADS/MEDSECS;
506 if (*cyls <= MAXCYLS) {
509 } else { /* too high for 127*63 */
510 *cyls = size /BIGHEADS/BIGSECS;
517 /* controller search and initialization functions */
519 static int __init gdth_search_eisa(u16 eisa_adr)
523 TRACE(("gdth_search_eisa() adr. %x\n",eisa_adr));
524 id = inl(eisa_adr+ID0REG);
525 if (id == GDT3A_ID || id == GDT3B_ID) { /* GDT3000A or GDT3000B */
526 if ((inb(eisa_adr+EISAREG) & 8) == 0)
527 return 0; /* not EISA configured */
530 if (id == GDT3_ID) /* GDT3000 */
535 #endif /* CONFIG_EISA */
538 static int __init gdth_search_isa(u32 bios_adr)
543 TRACE(("gdth_search_isa() bios adr. %x\n",bios_adr));
544 if ((addr = ioremap(bios_adr+BIOS_ID_OFFS, sizeof(u32))) != NULL) {
547 if (id == GDT2_ID) /* GDT2000 */
552 #endif /* CONFIG_ISA */
556 static bool gdth_search_vortex(u16 device)
558 if (device <= PCI_DEVICE_ID_VORTEX_GDT6555)
560 if (device >= PCI_DEVICE_ID_VORTEX_GDT6x17RP &&
561 device <= PCI_DEVICE_ID_VORTEX_GDTMAXRP)
563 if (device == PCI_DEVICE_ID_VORTEX_GDTNEWRX ||
564 device == PCI_DEVICE_ID_VORTEX_GDTNEWRX2)
569 static int gdth_pci_probe_one(gdth_pci_str *pcistr, gdth_ha_str **ha_out);
570 static int gdth_pci_init_one(struct pci_dev *pdev,
571 const struct pci_device_id *ent);
572 static void gdth_pci_remove_one(struct pci_dev *pdev);
573 static void gdth_remove_one(gdth_ha_str *ha);
575 /* Vortex only makes RAID controllers.
576 * We do not really want to specify all 550 ids here, so wildcard match.
578 static const struct pci_device_id gdthtable[] = {
579 { PCI_VDEVICE(VORTEX, PCI_ANY_ID) },
580 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SRC) },
581 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SRC_XSCALE) },
582 { } /* terminate list */
584 MODULE_DEVICE_TABLE(pci, gdthtable);
586 static struct pci_driver gdth_pci_driver = {
588 .id_table = gdthtable,
589 .probe = gdth_pci_init_one,
590 .remove = gdth_pci_remove_one,
593 static void gdth_pci_remove_one(struct pci_dev *pdev)
595 gdth_ha_str *ha = pci_get_drvdata(pdev);
600 pci_disable_device(pdev);
603 static int gdth_pci_init_one(struct pci_dev *pdev,
604 const struct pci_device_id *ent)
606 u16 vendor = pdev->vendor;
607 u16 device = pdev->device;
608 unsigned long base0, base1, base2;
610 gdth_pci_str gdth_pcistr;
611 gdth_ha_str *ha = NULL;
613 TRACE(("gdth_search_dev() cnt %d vendor %x device %x\n",
614 gdth_ctr_count, vendor, device));
616 memset(&gdth_pcistr, 0, sizeof(gdth_pcistr));
618 if (vendor == PCI_VENDOR_ID_VORTEX && !gdth_search_vortex(device))
621 rc = pci_enable_device(pdev);
625 if (gdth_ctr_count >= MAXHA)
628 /* GDT PCI controller found, resources are already in pdev */
629 gdth_pcistr.pdev = pdev;
630 base0 = pci_resource_flags(pdev, 0);
631 base1 = pci_resource_flags(pdev, 1);
632 base2 = pci_resource_flags(pdev, 2);
633 if (device <= PCI_DEVICE_ID_VORTEX_GDT6000B || /* GDT6000/B */
634 device >= PCI_DEVICE_ID_VORTEX_GDT6x17RP) { /* MPR */
635 if (!(base0 & IORESOURCE_MEM))
637 gdth_pcistr.dpmem = pci_resource_start(pdev, 0);
638 } else { /* GDT6110, GDT6120, .. */
639 if (!(base0 & IORESOURCE_MEM) ||
640 !(base2 & IORESOURCE_MEM) ||
641 !(base1 & IORESOURCE_IO))
643 gdth_pcistr.dpmem = pci_resource_start(pdev, 2);
644 gdth_pcistr.io = pci_resource_start(pdev, 1);
646 TRACE2(("Controller found at %d/%d, irq %d, dpmem 0x%lx\n",
647 gdth_pcistr.pdev->bus->number,
648 PCI_SLOT(gdth_pcistr.pdev->devfn),
652 rc = gdth_pci_probe_one(&gdth_pcistr, &ha);
658 #endif /* CONFIG_PCI */
661 static int __init gdth_init_eisa(u16 eisa_adr,gdth_ha_str *ha)
664 u8 prot_ver,eisacf,i,irq_found;
666 TRACE(("gdth_init_eisa() adr. %x\n",eisa_adr));
668 /* disable board interrupts, deinitialize services */
669 outb(0xff,eisa_adr+EDOORREG);
670 outb(0x00,eisa_adr+EDENABREG);
671 outb(0x00,eisa_adr+EINTENABREG);
673 outb(0xff,eisa_adr+LDOORREG);
674 retries = INIT_RETRIES;
676 while (inb(eisa_adr+EDOORREG) != 0xff) {
677 if (--retries == 0) {
678 printk("GDT-EISA: Initialization error (DEINIT failed)\n");
682 TRACE2(("wait for DEINIT: retries=%d\n",retries));
684 prot_ver = inb(eisa_adr+MAILBOXREG);
685 outb(0xff,eisa_adr+EDOORREG);
686 if (prot_ver != PROTOCOL_VERSION) {
687 printk("GDT-EISA: Illegal protocol version\n");
691 ha->brd_phys = (u32)eisa_adr >> 12;
693 outl(0,eisa_adr+MAILBOXREG);
694 outl(0,eisa_adr+MAILBOXREG+4);
695 outl(0,eisa_adr+MAILBOXREG+8);
696 outl(0,eisa_adr+MAILBOXREG+12);
699 if ((id = inl(eisa_adr+ID0REG)) == GDT3_ID) {
700 ha->oem_id = OEM_ID_ICP;
703 outl(1,eisa_adr+MAILBOXREG+8);
704 outb(0xfe,eisa_adr+LDOORREG);
705 retries = INIT_RETRIES;
707 while (inb(eisa_adr+EDOORREG) != 0xfe) {
708 if (--retries == 0) {
709 printk("GDT-EISA: Initialization error (get IRQ failed)\n");
714 ha->irq = inb(eisa_adr+MAILBOXREG);
715 outb(0xff,eisa_adr+EDOORREG);
716 TRACE2(("GDT3000/3020: IRQ=%d\n",ha->irq));
717 /* check the result */
719 TRACE2(("Unknown IRQ, use IRQ table from cmd line !\n"));
720 for (i = 0, irq_found = FALSE;
721 i < MAXHA && irq[i] != 0xff; ++i) {
722 if (irq[i]==10 || irq[i]==11 || irq[i]==12 || irq[i]==14) {
730 printk("GDT-EISA: Can not detect controller IRQ,\n");
731 printk("Use IRQ setting from command line (IRQ = %d)\n",
734 printk("GDT-EISA: Initialization error (unknown IRQ), Enable\n");
735 printk("the controller BIOS or use command line parameters\n");
740 eisacf = inb(eisa_adr+EISAREG) & 7;
741 if (eisacf > 4) /* level triggered */
743 ha->irq = gdth_irq_tab[eisacf];
744 ha->oem_id = OEM_ID_ICP;
749 ha->dma64_support = 0;
752 #endif /* CONFIG_EISA */
755 static int __init gdth_init_isa(u32 bios_adr,gdth_ha_str *ha)
757 register gdt2_dpram_str __iomem *dp2_ptr;
762 TRACE(("gdth_init_isa() bios adr. %x\n",bios_adr));
764 ha->brd = ioremap(bios_adr, sizeof(gdt2_dpram_str));
765 if (ha->brd == NULL) {
766 printk("GDT-ISA: Initialization error (DPMEM remap error)\n");
770 writeb(1, &dp2_ptr->io.memlock); /* switch off write protection */
771 /* reset interface area */
772 memset_io(&dp2_ptr->u, 0, sizeof(dp2_ptr->u));
773 if (readl(&dp2_ptr->u) != 0) {
774 printk("GDT-ISA: Initialization error (DPMEM write error)\n");
779 /* disable board interrupts, read DRQ and IRQ */
780 writeb(0xff, &dp2_ptr->io.irqdel);
781 writeb(0x00, &dp2_ptr->io.irqen);
782 writeb(0x00, &dp2_ptr->u.ic.S_Status);
783 writeb(0x00, &dp2_ptr->u.ic.Cmd_Index);
785 irq_drq = readb(&dp2_ptr->io.rq);
786 for (i=0; i<3; ++i) {
787 if ((irq_drq & 1)==0)
791 ha->drq = gdth_drq_tab[i];
793 irq_drq = readb(&dp2_ptr->io.rq) >> 3;
794 for (i=1; i<5; ++i) {
795 if ((irq_drq & 1)==0)
799 ha->irq = gdth_irq_tab[i];
801 /* deinitialize services */
802 writel(bios_adr, &dp2_ptr->u.ic.S_Info[0]);
803 writeb(0xff, &dp2_ptr->u.ic.S_Cmd_Indx);
804 writeb(0, &dp2_ptr->io.event);
805 retries = INIT_RETRIES;
807 while (readb(&dp2_ptr->u.ic.S_Status) != 0xff) {
808 if (--retries == 0) {
809 printk("GDT-ISA: Initialization error (DEINIT failed)\n");
815 prot_ver = (u8)readl(&dp2_ptr->u.ic.S_Info[0]);
816 writeb(0, &dp2_ptr->u.ic.Status);
817 writeb(0xff, &dp2_ptr->io.irqdel);
818 if (prot_ver != PROTOCOL_VERSION) {
819 printk("GDT-ISA: Illegal protocol version\n");
824 ha->oem_id = OEM_ID_ICP;
826 ha->ic_all_size = sizeof(dp2_ptr->u);
828 ha->brd_phys = bios_adr >> 4;
830 /* special request to controller BIOS */
831 writel(0x00, &dp2_ptr->u.ic.S_Info[0]);
832 writel(0x00, &dp2_ptr->u.ic.S_Info[1]);
833 writel(0x01, &dp2_ptr->u.ic.S_Info[2]);
834 writel(0x00, &dp2_ptr->u.ic.S_Info[3]);
835 writeb(0xfe, &dp2_ptr->u.ic.S_Cmd_Indx);
836 writeb(0, &dp2_ptr->io.event);
837 retries = INIT_RETRIES;
839 while (readb(&dp2_ptr->u.ic.S_Status) != 0xfe) {
840 if (--retries == 0) {
841 printk("GDT-ISA: Initialization error\n");
847 writeb(0, &dp2_ptr->u.ic.Status);
848 writeb(0xff, &dp2_ptr->io.irqdel);
850 ha->dma64_support = 0;
853 #endif /* CONFIG_ISA */
856 static int gdth_init_pci(struct pci_dev *pdev, gdth_pci_str *pcistr,
859 register gdt6_dpram_str __iomem *dp6_ptr;
860 register gdt6c_dpram_str __iomem *dp6c_ptr;
861 register gdt6m_dpram_str __iomem *dp6m_ptr;
865 int i, found = FALSE;
867 TRACE(("gdth_init_pci()\n"));
869 if (pdev->vendor == PCI_VENDOR_ID_INTEL)
870 ha->oem_id = OEM_ID_INTEL;
872 ha->oem_id = OEM_ID_ICP;
873 ha->brd_phys = (pdev->bus->number << 8) | (pdev->devfn & 0xf8);
874 ha->stype = (u32)pdev->device;
878 if (ha->pdev->device <= PCI_DEVICE_ID_VORTEX_GDT6000B) { /* GDT6000/B */
879 TRACE2(("init_pci() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq));
880 ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6_dpram_str));
881 if (ha->brd == NULL) {
882 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
885 /* check and reset interface area */
887 writel(DPMEM_MAGIC, &dp6_ptr->u);
888 if (readl(&dp6_ptr->u) != DPMEM_MAGIC) {
889 printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
892 for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
894 ha->brd = ioremap(i, sizeof(u16));
895 if (ha->brd == NULL) {
896 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
899 if (readw(ha->brd) != 0xffff) {
900 TRACE2(("init_pci_old() address 0x%x busy\n", i));
904 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, i);
905 ha->brd = ioremap(i, sizeof(gdt6_dpram_str));
906 if (ha->brd == NULL) {
907 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
911 writel(DPMEM_MAGIC, &dp6_ptr->u);
912 if (readl(&dp6_ptr->u) == DPMEM_MAGIC) {
913 printk("GDT-PCI: Use free address at 0x%x\n", i);
919 printk("GDT-PCI: No free address found!\n");
924 memset_io(&dp6_ptr->u, 0, sizeof(dp6_ptr->u));
925 if (readl(&dp6_ptr->u) != 0) {
926 printk("GDT-PCI: Initialization error (DPMEM write error)\n");
931 /* disable board interrupts, deinit services */
932 writeb(0xff, &dp6_ptr->io.irqdel);
933 writeb(0x00, &dp6_ptr->io.irqen);
934 writeb(0x00, &dp6_ptr->u.ic.S_Status);
935 writeb(0x00, &dp6_ptr->u.ic.Cmd_Index);
937 writel(pcistr->dpmem, &dp6_ptr->u.ic.S_Info[0]);
938 writeb(0xff, &dp6_ptr->u.ic.S_Cmd_Indx);
939 writeb(0, &dp6_ptr->io.event);
940 retries = INIT_RETRIES;
942 while (readb(&dp6_ptr->u.ic.S_Status) != 0xff) {
943 if (--retries == 0) {
944 printk("GDT-PCI: Initialization error (DEINIT failed)\n");
950 prot_ver = (u8)readl(&dp6_ptr->u.ic.S_Info[0]);
951 writeb(0, &dp6_ptr->u.ic.S_Status);
952 writeb(0xff, &dp6_ptr->io.irqdel);
953 if (prot_ver != PROTOCOL_VERSION) {
954 printk("GDT-PCI: Illegal protocol version\n");
960 ha->ic_all_size = sizeof(dp6_ptr->u);
962 /* special command to controller BIOS */
963 writel(0x00, &dp6_ptr->u.ic.S_Info[0]);
964 writel(0x00, &dp6_ptr->u.ic.S_Info[1]);
965 writel(0x00, &dp6_ptr->u.ic.S_Info[2]);
966 writel(0x00, &dp6_ptr->u.ic.S_Info[3]);
967 writeb(0xfe, &dp6_ptr->u.ic.S_Cmd_Indx);
968 writeb(0, &dp6_ptr->io.event);
969 retries = INIT_RETRIES;
971 while (readb(&dp6_ptr->u.ic.S_Status) != 0xfe) {
972 if (--retries == 0) {
973 printk("GDT-PCI: Initialization error\n");
979 writeb(0, &dp6_ptr->u.ic.S_Status);
980 writeb(0xff, &dp6_ptr->io.irqdel);
982 ha->dma64_support = 0;
984 } else if (ha->pdev->device <= PCI_DEVICE_ID_VORTEX_GDT6555) { /* GDT6110, ... */
985 ha->plx = (gdt6c_plx_regs *)pcistr->io;
986 TRACE2(("init_pci_new() dpmem %lx irq %d\n",
987 pcistr->dpmem,ha->irq));
988 ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6c_dpram_str));
989 if (ha->brd == NULL) {
990 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
994 /* check and reset interface area */
996 writel(DPMEM_MAGIC, &dp6c_ptr->u);
997 if (readl(&dp6c_ptr->u) != DPMEM_MAGIC) {
998 printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
1001 for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
1003 ha->brd = ioremap(i, sizeof(u16));
1004 if (ha->brd == NULL) {
1005 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1008 if (readw(ha->brd) != 0xffff) {
1009 TRACE2(("init_pci_plx() address 0x%x busy\n", i));
1013 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_2, i);
1014 ha->brd = ioremap(i, sizeof(gdt6c_dpram_str));
1015 if (ha->brd == NULL) {
1016 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1020 writel(DPMEM_MAGIC, &dp6c_ptr->u);
1021 if (readl(&dp6c_ptr->u) == DPMEM_MAGIC) {
1022 printk("GDT-PCI: Use free address at 0x%x\n", i);
1028 printk("GDT-PCI: No free address found!\n");
1033 memset_io(&dp6c_ptr->u, 0, sizeof(dp6c_ptr->u));
1034 if (readl(&dp6c_ptr->u) != 0) {
1035 printk("GDT-PCI: Initialization error (DPMEM write error)\n");
1040 /* disable board interrupts, deinit services */
1041 outb(0x00,PTR2USHORT(&ha->plx->control1));
1042 outb(0xff,PTR2USHORT(&ha->plx->edoor_reg));
1044 writeb(0x00, &dp6c_ptr->u.ic.S_Status);
1045 writeb(0x00, &dp6c_ptr->u.ic.Cmd_Index);
1047 writel(pcistr->dpmem, &dp6c_ptr->u.ic.S_Info[0]);
1048 writeb(0xff, &dp6c_ptr->u.ic.S_Cmd_Indx);
1050 outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
1052 retries = INIT_RETRIES;
1054 while (readb(&dp6c_ptr->u.ic.S_Status) != 0xff) {
1055 if (--retries == 0) {
1056 printk("GDT-PCI: Initialization error (DEINIT failed)\n");
1062 prot_ver = (u8)readl(&dp6c_ptr->u.ic.S_Info[0]);
1063 writeb(0, &dp6c_ptr->u.ic.Status);
1064 if (prot_ver != PROTOCOL_VERSION) {
1065 printk("GDT-PCI: Illegal protocol version\n");
1070 ha->type = GDT_PCINEW;
1071 ha->ic_all_size = sizeof(dp6c_ptr->u);
1073 /* special command to controller BIOS */
1074 writel(0x00, &dp6c_ptr->u.ic.S_Info[0]);
1075 writel(0x00, &dp6c_ptr->u.ic.S_Info[1]);
1076 writel(0x00, &dp6c_ptr->u.ic.S_Info[2]);
1077 writel(0x00, &dp6c_ptr->u.ic.S_Info[3]);
1078 writeb(0xfe, &dp6c_ptr->u.ic.S_Cmd_Indx);
1080 outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
1082 retries = INIT_RETRIES;
1084 while (readb(&dp6c_ptr->u.ic.S_Status) != 0xfe) {
1085 if (--retries == 0) {
1086 printk("GDT-PCI: Initialization error\n");
1092 writeb(0, &dp6c_ptr->u.ic.S_Status);
1094 ha->dma64_support = 0;
1097 TRACE2(("init_pci_mpr() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq));
1098 ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6m_dpram_str));
1099 if (ha->brd == NULL) {
1100 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1104 /* manipulate config. space to enable DPMEM, start RP controller */
1105 pci_read_config_word(pdev, PCI_COMMAND, &command);
1107 pci_write_config_word(pdev, PCI_COMMAND, command);
1112 /* Ensure that it is safe to access the non HW portions of DPMEM.
1113 * Aditional check needed for Xscale based RAID controllers */
1114 while( ((int)readb(&dp6m_ptr->i960r.sema0_reg) ) & 3 )
1117 /* check and reset interface area */
1118 writel(DPMEM_MAGIC, &dp6m_ptr->u);
1119 if (readl(&dp6m_ptr->u) != DPMEM_MAGIC) {
1120 printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
1123 for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
1125 ha->brd = ioremap(i, sizeof(u16));
1126 if (ha->brd == NULL) {
1127 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1130 if (readw(ha->brd) != 0xffff) {
1131 TRACE2(("init_pci_mpr() address 0x%x busy\n", i));
1135 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, i);
1136 ha->brd = ioremap(i, sizeof(gdt6m_dpram_str));
1137 if (ha->brd == NULL) {
1138 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1142 writel(DPMEM_MAGIC, &dp6m_ptr->u);
1143 if (readl(&dp6m_ptr->u) == DPMEM_MAGIC) {
1144 printk("GDT-PCI: Use free address at 0x%x\n", i);
1150 printk("GDT-PCI: No free address found!\n");
1155 memset_io(&dp6m_ptr->u, 0, sizeof(dp6m_ptr->u));
1157 /* disable board interrupts, deinit services */
1158 writeb(readb(&dp6m_ptr->i960r.edoor_en_reg) | 4,
1159 &dp6m_ptr->i960r.edoor_en_reg);
1160 writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
1161 writeb(0x00, &dp6m_ptr->u.ic.S_Status);
1162 writeb(0x00, &dp6m_ptr->u.ic.Cmd_Index);
1164 writel(pcistr->dpmem, &dp6m_ptr->u.ic.S_Info[0]);
1165 writeb(0xff, &dp6m_ptr->u.ic.S_Cmd_Indx);
1166 writeb(1, &dp6m_ptr->i960r.ldoor_reg);
1167 retries = INIT_RETRIES;
1169 while (readb(&dp6m_ptr->u.ic.S_Status) != 0xff) {
1170 if (--retries == 0) {
1171 printk("GDT-PCI: Initialization error (DEINIT failed)\n");
1177 prot_ver = (u8)readl(&dp6m_ptr->u.ic.S_Info[0]);
1178 writeb(0, &dp6m_ptr->u.ic.S_Status);
1179 if (prot_ver != PROTOCOL_VERSION) {
1180 printk("GDT-PCI: Illegal protocol version\n");
1185 ha->type = GDT_PCIMPR;
1186 ha->ic_all_size = sizeof(dp6m_ptr->u);
1188 /* special command to controller BIOS */
1189 writel(0x00, &dp6m_ptr->u.ic.S_Info[0]);
1190 writel(0x00, &dp6m_ptr->u.ic.S_Info[1]);
1191 writel(0x00, &dp6m_ptr->u.ic.S_Info[2]);
1192 writel(0x00, &dp6m_ptr->u.ic.S_Info[3]);
1193 writeb(0xfe, &dp6m_ptr->u.ic.S_Cmd_Indx);
1194 writeb(1, &dp6m_ptr->i960r.ldoor_reg);
1195 retries = INIT_RETRIES;
1197 while (readb(&dp6m_ptr->u.ic.S_Status) != 0xfe) {
1198 if (--retries == 0) {
1199 printk("GDT-PCI: Initialization error\n");
1205 writeb(0, &dp6m_ptr->u.ic.S_Status);
1207 /* read FW version to detect 64-bit DMA support */
1208 writeb(0xfd, &dp6m_ptr->u.ic.S_Cmd_Indx);
1209 writeb(1, &dp6m_ptr->i960r.ldoor_reg);
1210 retries = INIT_RETRIES;
1212 while (readb(&dp6m_ptr->u.ic.S_Status) != 0xfd) {
1213 if (--retries == 0) {
1214 printk("GDT-PCI: Initialization error (DEINIT failed)\n");
1220 prot_ver = (u8)(readl(&dp6m_ptr->u.ic.S_Info[0]) >> 16);
1221 writeb(0, &dp6m_ptr->u.ic.S_Status);
1222 if (prot_ver < 0x2b) /* FW < x.43: no 64-bit DMA support */
1223 ha->dma64_support = 0;
1225 ha->dma64_support = 1;
1230 #endif /* CONFIG_PCI */
1232 /* controller protocol functions */
1234 static void gdth_enable_int(gdth_ha_str *ha)
1236 unsigned long flags;
1237 gdt2_dpram_str __iomem *dp2_ptr;
1238 gdt6_dpram_str __iomem *dp6_ptr;
1239 gdt6m_dpram_str __iomem *dp6m_ptr;
1241 TRACE(("gdth_enable_int() hanum %d\n",ha->hanum));
1242 spin_lock_irqsave(&ha->smp_lock, flags);
1244 if (ha->type == GDT_EISA) {
1245 outb(0xff, ha->bmic + EDOORREG);
1246 outb(0xff, ha->bmic + EDENABREG);
1247 outb(0x01, ha->bmic + EINTENABREG);
1248 } else if (ha->type == GDT_ISA) {
1250 writeb(1, &dp2_ptr->io.irqdel);
1251 writeb(0, &dp2_ptr->u.ic.Cmd_Index);
1252 writeb(1, &dp2_ptr->io.irqen);
1253 } else if (ha->type == GDT_PCI) {
1255 writeb(1, &dp6_ptr->io.irqdel);
1256 writeb(0, &dp6_ptr->u.ic.Cmd_Index);
1257 writeb(1, &dp6_ptr->io.irqen);
1258 } else if (ha->type == GDT_PCINEW) {
1259 outb(0xff, PTR2USHORT(&ha->plx->edoor_reg));
1260 outb(0x03, PTR2USHORT(&ha->plx->control1));
1261 } else if (ha->type == GDT_PCIMPR) {
1263 writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
1264 writeb(readb(&dp6m_ptr->i960r.edoor_en_reg) & ~4,
1265 &dp6m_ptr->i960r.edoor_en_reg);
1267 spin_unlock_irqrestore(&ha->smp_lock, flags);
1270 /* return IStatus if interrupt was from this card else 0 */
1271 static u8 gdth_get_status(gdth_ha_str *ha)
1275 TRACE(("gdth_get_status() irq %d ctr_count %d\n", ha->irq, gdth_ctr_count));
1277 if (ha->type == GDT_EISA)
1278 IStatus = inb((u16)ha->bmic + EDOORREG);
1279 else if (ha->type == GDT_ISA)
1281 readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
1282 else if (ha->type == GDT_PCI)
1284 readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
1285 else if (ha->type == GDT_PCINEW)
1286 IStatus = inb(PTR2USHORT(&ha->plx->edoor_reg));
1287 else if (ha->type == GDT_PCIMPR)
1289 readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.edoor_reg);
1294 static int gdth_test_busy(gdth_ha_str *ha)
1296 register int gdtsema0 = 0;
1298 TRACE(("gdth_test_busy() hanum %d\n", ha->hanum));
1300 if (ha->type == GDT_EISA)
1301 gdtsema0 = (int)inb(ha->bmic + SEMA0REG);
1302 else if (ha->type == GDT_ISA)
1303 gdtsema0 = (int)readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
1304 else if (ha->type == GDT_PCI)
1305 gdtsema0 = (int)readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
1306 else if (ha->type == GDT_PCINEW)
1307 gdtsema0 = (int)inb(PTR2USHORT(&ha->plx->sema0_reg));
1308 else if (ha->type == GDT_PCIMPR)
1310 (int)readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg);
1312 return (gdtsema0 & 1);
1316 static int gdth_get_cmd_index(gdth_ha_str *ha)
1320 TRACE(("gdth_get_cmd_index() hanum %d\n", ha->hanum));
1322 for (i=0; i<GDTH_MAXCMDS; ++i) {
1323 if (ha->cmd_tab[i].cmnd == UNUSED_CMND) {
1324 ha->cmd_tab[i].cmnd = ha->pccb->RequestBuffer;
1325 ha->cmd_tab[i].service = ha->pccb->Service;
1326 ha->pccb->CommandIndex = (u32)i+2;
1334 static void gdth_set_sema0(gdth_ha_str *ha)
1336 TRACE(("gdth_set_sema0() hanum %d\n", ha->hanum));
1338 if (ha->type == GDT_EISA) {
1339 outb(1, ha->bmic + SEMA0REG);
1340 } else if (ha->type == GDT_ISA) {
1341 writeb(1, &((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
1342 } else if (ha->type == GDT_PCI) {
1343 writeb(1, &((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
1344 } else if (ha->type == GDT_PCINEW) {
1345 outb(1, PTR2USHORT(&ha->plx->sema0_reg));
1346 } else if (ha->type == GDT_PCIMPR) {
1347 writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg);
1352 static void gdth_copy_command(gdth_ha_str *ha)
1354 register gdth_cmd_str *cmd_ptr;
1355 register gdt6m_dpram_str __iomem *dp6m_ptr;
1356 register gdt6c_dpram_str __iomem *dp6c_ptr;
1357 gdt6_dpram_str __iomem *dp6_ptr;
1358 gdt2_dpram_str __iomem *dp2_ptr;
1359 u16 cp_count,dp_offset,cmd_no;
1361 TRACE(("gdth_copy_command() hanum %d\n", ha->hanum));
1363 cp_count = ha->cmd_len;
1364 dp_offset= ha->cmd_offs_dpmem;
1365 cmd_no = ha->cmd_cnt;
1369 if (ha->type == GDT_EISA)
1370 return; /* no DPMEM, no copy */
1372 /* set cpcount dword aligned */
1374 cp_count += (4 - (cp_count & 3));
1376 ha->cmd_offs_dpmem += cp_count;
1378 /* set offset and service, copy command to DPMEM */
1379 if (ha->type == GDT_ISA) {
1381 writew(dp_offset + DPMEM_COMMAND_OFFSET,
1382 &dp2_ptr->u.ic.comm_queue[cmd_no].offset);
1383 writew((u16)cmd_ptr->Service,
1384 &dp2_ptr->u.ic.comm_queue[cmd_no].serv_id);
1385 memcpy_toio(&dp2_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
1386 } else if (ha->type == GDT_PCI) {
1388 writew(dp_offset + DPMEM_COMMAND_OFFSET,
1389 &dp6_ptr->u.ic.comm_queue[cmd_no].offset);
1390 writew((u16)cmd_ptr->Service,
1391 &dp6_ptr->u.ic.comm_queue[cmd_no].serv_id);
1392 memcpy_toio(&dp6_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
1393 } else if (ha->type == GDT_PCINEW) {
1395 writew(dp_offset + DPMEM_COMMAND_OFFSET,
1396 &dp6c_ptr->u.ic.comm_queue[cmd_no].offset);
1397 writew((u16)cmd_ptr->Service,
1398 &dp6c_ptr->u.ic.comm_queue[cmd_no].serv_id);
1399 memcpy_toio(&dp6c_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
1400 } else if (ha->type == GDT_PCIMPR) {
1402 writew(dp_offset + DPMEM_COMMAND_OFFSET,
1403 &dp6m_ptr->u.ic.comm_queue[cmd_no].offset);
1404 writew((u16)cmd_ptr->Service,
1405 &dp6m_ptr->u.ic.comm_queue[cmd_no].serv_id);
1406 memcpy_toio(&dp6m_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
1411 static void gdth_release_event(gdth_ha_str *ha)
1413 TRACE(("gdth_release_event() hanum %d\n", ha->hanum));
1415 #ifdef GDTH_STATISTICS
1418 for (i=0,j=0; j<GDTH_MAXCMDS; ++j) {
1419 if (ha->cmd_tab[j].cmnd != UNUSED_CMND)
1422 if (max_index < i) {
1424 TRACE3(("GDT: max_index = %d\n",(u16)i));
1429 if (ha->pccb->OpCode == GDT_INIT)
1430 ha->pccb->Service |= 0x80;
1432 if (ha->type == GDT_EISA) {
1433 if (ha->pccb->OpCode == GDT_INIT) /* store DMA buffer */
1434 outl(ha->ccb_phys, ha->bmic + MAILBOXREG);
1435 outb(ha->pccb->Service, ha->bmic + LDOORREG);
1436 } else if (ha->type == GDT_ISA) {
1437 writeb(0, &((gdt2_dpram_str __iomem *)ha->brd)->io.event);
1438 } else if (ha->type == GDT_PCI) {
1439 writeb(0, &((gdt6_dpram_str __iomem *)ha->brd)->io.event);
1440 } else if (ha->type == GDT_PCINEW) {
1441 outb(1, PTR2USHORT(&ha->plx->ldoor_reg));
1442 } else if (ha->type == GDT_PCIMPR) {
1443 writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.ldoor_reg);
1447 static int gdth_wait(gdth_ha_str *ha, int index, u32 time)
1449 int answer_found = FALSE;
1452 TRACE(("gdth_wait() hanum %d index %d time %d\n", ha->hanum, index, time));
1455 return 1; /* no wait required */
1458 __gdth_interrupt(ha, true, &wait_index);
1459 if (wait_index == index) {
1460 answer_found = TRUE;
1466 while (gdth_test_busy(ha))
1469 return (answer_found);
1473 static int gdth_internal_cmd(gdth_ha_str *ha, u8 service, u16 opcode,
1474 u32 p1, u64 p2, u64 p3)
1476 register gdth_cmd_str *cmd_ptr;
1479 TRACE2(("gdth_internal_cmd() service %d opcode %d\n",service,opcode));
1482 memset((char*)cmd_ptr,0,sizeof(gdth_cmd_str));
1485 for (retries = INIT_RETRIES;;) {
1486 cmd_ptr->Service = service;
1487 cmd_ptr->RequestBuffer = INTERNAL_CMND;
1488 if (!(index=gdth_get_cmd_index(ha))) {
1489 TRACE(("GDT: No free command index found\n"));
1493 cmd_ptr->OpCode = opcode;
1494 cmd_ptr->BoardNode = LOCALBOARD;
1495 if (service == CACHESERVICE) {
1496 if (opcode == GDT_IOCTL) {
1497 cmd_ptr->u.ioctl.subfunc = p1;
1498 cmd_ptr->u.ioctl.channel = (u32)p2;
1499 cmd_ptr->u.ioctl.param_size = (u16)p3;
1500 cmd_ptr->u.ioctl.p_param = ha->scratch_phys;
1502 if (ha->cache_feat & GDT_64BIT) {
1503 cmd_ptr->u.cache64.DeviceNo = (u16)p1;
1504 cmd_ptr->u.cache64.BlockNo = p2;
1506 cmd_ptr->u.cache.DeviceNo = (u16)p1;
1507 cmd_ptr->u.cache.BlockNo = (u32)p2;
1510 } else if (service == SCSIRAWSERVICE) {
1511 if (ha->raw_feat & GDT_64BIT) {
1512 cmd_ptr->u.raw64.direction = p1;
1513 cmd_ptr->u.raw64.bus = (u8)p2;
1514 cmd_ptr->u.raw64.target = (u8)p3;
1515 cmd_ptr->u.raw64.lun = (u8)(p3 >> 8);
1517 cmd_ptr->u.raw.direction = p1;
1518 cmd_ptr->u.raw.bus = (u8)p2;
1519 cmd_ptr->u.raw.target = (u8)p3;
1520 cmd_ptr->u.raw.lun = (u8)(p3 >> 8);
1522 } else if (service == SCREENSERVICE) {
1523 if (opcode == GDT_REALTIME) {
1524 *(u32 *)&cmd_ptr->u.screen.su.data[0] = p1;
1525 *(u32 *)&cmd_ptr->u.screen.su.data[4] = (u32)p2;
1526 *(u32 *)&cmd_ptr->u.screen.su.data[8] = (u32)p3;
1529 ha->cmd_len = sizeof(gdth_cmd_str);
1530 ha->cmd_offs_dpmem = 0;
1532 gdth_copy_command(ha);
1533 gdth_release_event(ha);
1535 if (!gdth_wait(ha, index, INIT_TIMEOUT)) {
1536 printk("GDT: Initialization error (timeout service %d)\n",service);
1539 if (ha->status != S_BSY || --retries == 0)
1544 return (ha->status != S_OK ? 0:1);
1548 /* search for devices */
1550 static int gdth_search_drives(gdth_ha_str *ha)
1554 u32 bus_no, drv_cnt, drv_no, j;
1555 gdth_getch_str *chn;
1556 gdth_drlist_str *drl;
1557 gdth_iochan_str *ioc;
1558 gdth_raw_iochan_str *iocr;
1559 gdth_arcdl_str *alst;
1560 gdth_alist_str *alst2;
1561 gdth_oem_str_ioctl *oemstr;
1563 gdth_perf_modes *pmod;
1568 unsigned long flags;
1571 TRACE(("gdth_search_drives() hanum %d\n", ha->hanum));
1574 /* initialize controller services, at first: screen service */
1575 ha->screen_feat = 0;
1577 ok = gdth_internal_cmd(ha, SCREENSERVICE, GDT_X_INIT_SCR, 0, 0, 0);
1579 ha->screen_feat = GDT_64BIT;
1581 if (force_dma32 || (!ok && ha->status == (u16)S_NOFUNC))
1582 ok = gdth_internal_cmd(ha, SCREENSERVICE, GDT_INIT, 0, 0, 0);
1584 printk("GDT-HA %d: Initialization error screen service (code %d)\n",
1585 ha->hanum, ha->status);
1588 TRACE2(("gdth_search_drives(): SCREENSERVICE initialized\n"));
1591 /* read realtime clock info, send to controller */
1592 /* 1. wait for the falling edge of update flag */
1593 spin_lock_irqsave(&rtc_lock, flags);
1594 for (j = 0; j < 1000000; ++j)
1595 if (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP)
1597 for (j = 0; j < 1000000; ++j)
1598 if (!(CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP))
1602 for (j = 0; j < 12; ++j)
1603 rtc[j] = CMOS_READ(j);
1604 } while (rtc[0] != CMOS_READ(0));
1605 spin_unlock_irqrestore(&rtc_lock, flags);
1606 TRACE2(("gdth_search_drives(): RTC: %x/%x/%x\n",*(u32 *)&rtc[0],
1607 *(u32 *)&rtc[4], *(u32 *)&rtc[8]));
1608 /* 3. send to controller firmware */
1609 gdth_internal_cmd(ha, SCREENSERVICE, GDT_REALTIME, *(u32 *)&rtc[0],
1610 *(u32 *)&rtc[4], *(u32 *)&rtc[8]);
1613 /* unfreeze all IOs */
1614 gdth_internal_cmd(ha, CACHESERVICE, GDT_UNFREEZE_IO, 0, 0, 0);
1616 /* initialize cache service */
1619 ok = gdth_internal_cmd(ha, CACHESERVICE, GDT_X_INIT_HOST, LINUX_OS,
1622 ha->cache_feat = GDT_64BIT;
1624 if (force_dma32 || (!ok && ha->status == (u16)S_NOFUNC))
1625 ok = gdth_internal_cmd(ha, CACHESERVICE, GDT_INIT, LINUX_OS, 0, 0);
1627 printk("GDT-HA %d: Initialization error cache service (code %d)\n",
1628 ha->hanum, ha->status);
1631 TRACE2(("gdth_search_drives(): CACHESERVICE initialized\n"));
1632 cdev_cnt = (u16)ha->info;
1633 ha->fw_vers = ha->service;
1636 if (ha->type == GDT_PCIMPR) {
1637 /* set perf. modes */
1638 pmod = (gdth_perf_modes *)ha->pscratch;
1640 pmod->st_mode = 1; /* enable one status buffer */
1641 *((u64 *)&pmod->st_buff_addr1) = ha->coal_stat_phys;
1642 pmod->st_buff_indx1 = COALINDEX;
1643 pmod->st_buff_addr2 = 0;
1644 pmod->st_buff_u_addr2 = 0;
1645 pmod->st_buff_indx2 = 0;
1646 pmod->st_buff_size = sizeof(gdth_coal_status) * MAXOFFSETS;
1647 pmod->cmd_mode = 0; // disable all cmd buffers
1648 pmod->cmd_buff_addr1 = 0;
1649 pmod->cmd_buff_u_addr1 = 0;
1650 pmod->cmd_buff_indx1 = 0;
1651 pmod->cmd_buff_addr2 = 0;
1652 pmod->cmd_buff_u_addr2 = 0;
1653 pmod->cmd_buff_indx2 = 0;
1654 pmod->cmd_buff_size = 0;
1655 pmod->reserved1 = 0;
1656 pmod->reserved2 = 0;
1657 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, SET_PERF_MODES,
1658 INVALID_CHANNEL,sizeof(gdth_perf_modes))) {
1659 printk("GDT-HA %d: Interrupt coalescing activated\n", ha->hanum);
1664 /* detect number of buses - try new IOCTL */
1665 iocr = (gdth_raw_iochan_str *)ha->pscratch;
1666 iocr->hdr.version = 0xffffffff;
1667 iocr->hdr.list_entries = MAXBUS;
1668 iocr->hdr.first_chan = 0;
1669 iocr->hdr.last_chan = MAXBUS-1;
1670 iocr->hdr.list_offset = GDTOFFSOF(gdth_raw_iochan_str, list[0]);
1671 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, IOCHAN_RAW_DESC,
1672 INVALID_CHANNEL,sizeof(gdth_raw_iochan_str))) {
1673 TRACE2(("IOCHAN_RAW_DESC supported!\n"));
1674 ha->bus_cnt = iocr->hdr.chan_count;
1675 for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
1676 if (iocr->list[bus_no].proc_id < MAXID)
1677 ha->bus_id[bus_no] = iocr->list[bus_no].proc_id;
1679 ha->bus_id[bus_no] = 0xff;
1683 chn = (gdth_getch_str *)ha->pscratch;
1684 for (bus_no = 0; bus_no < MAXBUS; ++bus_no) {
1685 chn->channel_no = bus_no;
1686 if (!gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
1687 SCSI_CHAN_CNT | L_CTRL_PATTERN,
1688 IO_CHANNEL | INVALID_CHANNEL,
1689 sizeof(gdth_getch_str))) {
1691 printk("GDT-HA %d: Error detecting channel count (0x%x)\n",
1692 ha->hanum, ha->status);
1697 if (chn->siop_id < MAXID)
1698 ha->bus_id[bus_no] = chn->siop_id;
1700 ha->bus_id[bus_no] = 0xff;
1702 ha->bus_cnt = (u8)bus_no;
1704 TRACE2(("gdth_search_drives() %d channels\n",ha->bus_cnt));
1706 /* read cache configuration */
1707 if (!gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, CACHE_INFO,
1708 INVALID_CHANNEL,sizeof(gdth_cinfo_str))) {
1709 printk("GDT-HA %d: Initialization error cache service (code %d)\n",
1710 ha->hanum, ha->status);
1713 ha->cpar = ((gdth_cinfo_str *)ha->pscratch)->cpar;
1714 TRACE2(("gdth_search_drives() cinfo: vs %x sta %d str %d dw %d b %d\n",
1715 ha->cpar.version,ha->cpar.state,ha->cpar.strategy,
1716 ha->cpar.write_back,ha->cpar.block_size));
1718 /* read board info and features */
1719 ha->more_proc = FALSE;
1720 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, BOARD_INFO,
1721 INVALID_CHANNEL,sizeof(gdth_binfo_str))) {
1722 memcpy(&ha->binfo, (gdth_binfo_str *)ha->pscratch,
1723 sizeof(gdth_binfo_str));
1724 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, BOARD_FEATURES,
1725 INVALID_CHANNEL,sizeof(gdth_bfeat_str))) {
1726 TRACE2(("BOARD_INFO/BOARD_FEATURES supported\n"));
1727 ha->bfeat = *(gdth_bfeat_str *)ha->pscratch;
1728 ha->more_proc = TRUE;
1731 TRACE2(("BOARD_INFO requires firmware >= 1.10/2.08\n"));
1732 strcpy(ha->binfo.type_string, gdth_ctr_name(ha));
1734 TRACE2(("Controller name: %s\n",ha->binfo.type_string));
1736 /* read more informations */
1737 if (ha->more_proc) {
1738 /* physical drives, channel addresses */
1739 ioc = (gdth_iochan_str *)ha->pscratch;
1740 ioc->hdr.version = 0xffffffff;
1741 ioc->hdr.list_entries = MAXBUS;
1742 ioc->hdr.first_chan = 0;
1743 ioc->hdr.last_chan = MAXBUS-1;
1744 ioc->hdr.list_offset = GDTOFFSOF(gdth_iochan_str, list[0]);
1745 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, IOCHAN_DESC,
1746 INVALID_CHANNEL,sizeof(gdth_iochan_str))) {
1747 for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
1748 ha->raw[bus_no].address = ioc->list[bus_no].address;
1749 ha->raw[bus_no].local_no = ioc->list[bus_no].local_no;
1752 for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
1753 ha->raw[bus_no].address = IO_CHANNEL;
1754 ha->raw[bus_no].local_no = bus_no;
1757 for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
1758 chn = (gdth_getch_str *)ha->pscratch;
1759 chn->channel_no = ha->raw[bus_no].local_no;
1760 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
1761 SCSI_CHAN_CNT | L_CTRL_PATTERN,
1762 ha->raw[bus_no].address | INVALID_CHANNEL,
1763 sizeof(gdth_getch_str))) {
1764 ha->raw[bus_no].pdev_cnt = chn->drive_cnt;
1765 TRACE2(("Channel %d: %d phys. drives\n",
1766 bus_no,chn->drive_cnt));
1768 if (ha->raw[bus_no].pdev_cnt > 0) {
1769 drl = (gdth_drlist_str *)ha->pscratch;
1770 drl->sc_no = ha->raw[bus_no].local_no;
1771 drl->sc_cnt = ha->raw[bus_no].pdev_cnt;
1772 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
1773 SCSI_DR_LIST | L_CTRL_PATTERN,
1774 ha->raw[bus_no].address | INVALID_CHANNEL,
1775 sizeof(gdth_drlist_str))) {
1776 for (j = 0; j < ha->raw[bus_no].pdev_cnt; ++j)
1777 ha->raw[bus_no].id_list[j] = drl->sc_list[j];
1779 ha->raw[bus_no].pdev_cnt = 0;
1784 /* logical drives */
1785 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, CACHE_DRV_CNT,
1786 INVALID_CHANNEL,sizeof(u32))) {
1787 drv_cnt = *(u32 *)ha->pscratch;
1788 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, CACHE_DRV_LIST,
1789 INVALID_CHANNEL,drv_cnt * sizeof(u32))) {
1790 for (j = 0; j < drv_cnt; ++j) {
1791 drv_no = ((u32 *)ha->pscratch)[j];
1792 if (drv_no < MAX_LDRIVES) {
1793 ha->hdr[drv_no].is_logdrv = TRUE;
1794 TRACE2(("Drive %d is log. drive\n",drv_no));
1798 alst = (gdth_arcdl_str *)ha->pscratch;
1799 alst->entries_avail = MAX_LDRIVES;
1800 alst->first_entry = 0;
1801 alst->list_offset = GDTOFFSOF(gdth_arcdl_str, list[0]);
1802 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
1803 ARRAY_DRV_LIST2 | LA_CTRL_PATTERN,
1804 INVALID_CHANNEL, sizeof(gdth_arcdl_str) +
1805 (alst->entries_avail-1) * sizeof(gdth_alist_str))) {
1806 for (j = 0; j < alst->entries_init; ++j) {
1807 ha->hdr[j].is_arraydrv = alst->list[j].is_arrayd;
1808 ha->hdr[j].is_master = alst->list[j].is_master;
1809 ha->hdr[j].is_parity = alst->list[j].is_parity;
1810 ha->hdr[j].is_hotfix = alst->list[j].is_hotfix;
1811 ha->hdr[j].master_no = alst->list[j].cd_handle;
1813 } else if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
1814 ARRAY_DRV_LIST | LA_CTRL_PATTERN,
1815 0, 35 * sizeof(gdth_alist_str))) {
1816 for (j = 0; j < 35; ++j) {
1817 alst2 = &((gdth_alist_str *)ha->pscratch)[j];
1818 ha->hdr[j].is_arraydrv = alst2->is_arrayd;
1819 ha->hdr[j].is_master = alst2->is_master;
1820 ha->hdr[j].is_parity = alst2->is_parity;
1821 ha->hdr[j].is_hotfix = alst2->is_hotfix;
1822 ha->hdr[j].master_no = alst2->cd_handle;
1828 /* initialize raw service */
1831 ok = gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_X_INIT_RAW, 0, 0, 0);
1833 ha->raw_feat = GDT_64BIT;
1835 if (force_dma32 || (!ok && ha->status == (u16)S_NOFUNC))
1836 ok = gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_INIT, 0, 0, 0);
1838 printk("GDT-HA %d: Initialization error raw service (code %d)\n",
1839 ha->hanum, ha->status);
1842 TRACE2(("gdth_search_drives(): RAWSERVICE initialized\n"));
1844 /* set/get features raw service (scatter/gather) */
1845 if (gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_SET_FEAT, SCATTER_GATHER,
1847 TRACE2(("gdth_search_drives(): set features RAWSERVICE OK\n"));
1848 if (gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_GET_FEAT, 0, 0, 0)) {
1849 TRACE2(("gdth_search_dr(): get feat RAWSERVICE %d\n",
1851 ha->raw_feat |= (u16)ha->info;
1855 /* set/get features cache service (equal to raw service) */
1856 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_SET_FEAT, 0,
1857 SCATTER_GATHER,0)) {
1858 TRACE2(("gdth_search_drives(): set features CACHESERVICE OK\n"));
1859 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_GET_FEAT, 0, 0, 0)) {
1860 TRACE2(("gdth_search_dr(): get feat CACHESERV. %d\n",
1862 ha->cache_feat |= (u16)ha->info;
1866 /* reserve drives for raw service */
1867 if (reserve_mode != 0) {
1868 gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_RESERVE_ALL,
1869 reserve_mode == 1 ? 1 : 3, 0, 0);
1870 TRACE2(("gdth_search_drives(): RESERVE_ALL code %d\n",
1873 for (i = 0; i < MAX_RES_ARGS; i += 4) {
1874 if (reserve_list[i] == ha->hanum && reserve_list[i+1] < ha->bus_cnt &&
1875 reserve_list[i+2] < ha->tid_cnt && reserve_list[i+3] < MAXLUN) {
1876 TRACE2(("gdth_search_drives(): reserve ha %d bus %d id %d lun %d\n",
1877 reserve_list[i], reserve_list[i+1],
1878 reserve_list[i+2], reserve_list[i+3]));
1879 if (!gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_RESERVE, 0,
1880 reserve_list[i+1], reserve_list[i+2] |
1881 (reserve_list[i+3] << 8))) {
1882 printk("GDT-HA %d: Error raw service (RESERVE, code %d)\n",
1883 ha->hanum, ha->status);
1888 /* Determine OEM string using IOCTL */
1889 oemstr = (gdth_oem_str_ioctl *)ha->pscratch;
1890 oemstr->params.ctl_version = 0x01;
1891 oemstr->params.buffer_size = sizeof(oemstr->text);
1892 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
1893 CACHE_READ_OEM_STRING_RECORD,INVALID_CHANNEL,
1894 sizeof(gdth_oem_str_ioctl))) {
1895 TRACE2(("gdth_search_drives(): CACHE_READ_OEM_STRING_RECORD OK\n"));
1896 printk("GDT-HA %d: Vendor: %s Name: %s\n",
1897 ha->hanum, oemstr->text.oem_company_name, ha->binfo.type_string);
1898 /* Save the Host Drive inquiry data */
1899 strlcpy(ha->oem_name,oemstr->text.scsi_host_drive_inquiry_vendor_id,
1900 sizeof(ha->oem_name));
1902 /* Old method, based on PCI ID */
1903 TRACE2(("gdth_search_drives(): CACHE_READ_OEM_STRING_RECORD failed\n"));
1904 printk("GDT-HA %d: Name: %s\n",
1905 ha->hanum, ha->binfo.type_string);
1906 if (ha->oem_id == OEM_ID_INTEL)
1907 strlcpy(ha->oem_name,"Intel ", sizeof(ha->oem_name));
1909 strlcpy(ha->oem_name,"ICP ", sizeof(ha->oem_name));
1912 /* scanning for host drives */
1913 for (i = 0; i < cdev_cnt; ++i)
1914 gdth_analyse_hdrive(ha, i);
1916 TRACE(("gdth_search_drives() OK\n"));
1920 static int gdth_analyse_hdrive(gdth_ha_str *ha, u16 hdrive)
1923 int drv_hds, drv_secs;
1925 TRACE(("gdth_analyse_hdrive() hanum %d drive %d\n", ha->hanum, hdrive));
1926 if (hdrive >= MAX_HDRIVES)
1929 if (!gdth_internal_cmd(ha, CACHESERVICE, GDT_INFO, hdrive, 0, 0))
1931 ha->hdr[hdrive].present = TRUE;
1932 ha->hdr[hdrive].size = ha->info;
1934 /* evaluate mapping (sectors per head, heads per cylinder) */
1935 ha->hdr[hdrive].size &= ~SECS32;
1936 if (ha->info2 == 0) {
1937 gdth_eval_mapping(ha->hdr[hdrive].size,&drv_cyls,&drv_hds,&drv_secs);
1939 drv_hds = ha->info2 & 0xff;
1940 drv_secs = (ha->info2 >> 8) & 0xff;
1941 drv_cyls = (u32)ha->hdr[hdrive].size / drv_hds / drv_secs;
1943 ha->hdr[hdrive].heads = (u8)drv_hds;
1944 ha->hdr[hdrive].secs = (u8)drv_secs;
1946 ha->hdr[hdrive].size = drv_cyls * drv_hds * drv_secs;
1948 if (ha->cache_feat & GDT_64BIT) {
1949 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_X_INFO, hdrive, 0, 0)
1950 && ha->info2 != 0) {
1951 ha->hdr[hdrive].size = ((u64)ha->info2 << 32) | ha->info;
1954 TRACE2(("gdth_search_dr() cdr. %d size %d hds %d scs %d\n",
1955 hdrive,ha->hdr[hdrive].size,drv_hds,drv_secs));
1957 /* get informations about device */
1958 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_DEVTYPE, hdrive, 0, 0)) {
1959 TRACE2(("gdth_search_dr() cache drive %d devtype %d\n",
1961 ha->hdr[hdrive].devtype = (u16)ha->info;
1965 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_CLUST_INFO, hdrive, 0, 0)) {
1966 TRACE2(("gdth_search_dr() cache drive %d cluster info %d\n",
1969 ha->hdr[hdrive].cluster_type = (u8)ha->info;
1972 /* R/W attributes */
1973 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_RW_ATTRIBS, hdrive, 0, 0)) {
1974 TRACE2(("gdth_search_dr() cache drive %d r/w attrib. %d\n",
1976 ha->hdr[hdrive].rw_attribs = (u8)ha->info;
1983 /* command queueing/sending functions */
1985 static void gdth_putq(gdth_ha_str *ha, Scsi_Cmnd *scp, u8 priority)
1987 struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
1988 register Scsi_Cmnd *pscp;
1989 register Scsi_Cmnd *nscp;
1990 unsigned long flags;
1992 TRACE(("gdth_putq() priority %d\n",priority));
1993 spin_lock_irqsave(&ha->smp_lock, flags);
1995 if (!cmndinfo->internal_command)
1996 cmndinfo->priority = priority;
1998 if (ha->req_first==NULL) {
1999 ha->req_first = scp; /* queue was empty */
2000 scp->SCp.ptr = NULL;
2001 } else { /* queue not empty */
2002 pscp = ha->req_first;
2003 nscp = (Scsi_Cmnd *)pscp->SCp.ptr;
2004 /* priority: 0-highest,..,0xff-lowest */
2005 while (nscp && gdth_cmnd_priv(nscp)->priority <= priority) {
2007 nscp = (Scsi_Cmnd *)pscp->SCp.ptr;
2009 pscp->SCp.ptr = (char *)scp;
2010 scp->SCp.ptr = (char *)nscp;
2012 spin_unlock_irqrestore(&ha->smp_lock, flags);
2014 #ifdef GDTH_STATISTICS
2016 for (nscp=ha->req_first; nscp; nscp=(Scsi_Cmnd*)nscp->SCp.ptr)
2018 if (max_rq < flags) {
2020 TRACE3(("GDT: max_rq = %d\n",(u16)max_rq));
2025 static void gdth_next(gdth_ha_str *ha)
2027 register Scsi_Cmnd *pscp;
2028 register Scsi_Cmnd *nscp;
2029 u8 b, t, l, firsttime;
2030 u8 this_cmd, next_cmd;
2031 unsigned long flags = 0;
2034 TRACE(("gdth_next() hanum %d\n", ha->hanum));
2036 spin_lock_irqsave(&ha->smp_lock, flags);
2038 ha->cmd_cnt = ha->cmd_offs_dpmem = 0;
2039 this_cmd = firsttime = TRUE;
2040 next_cmd = gdth_polling ? FALSE:TRUE;
2043 for (nscp = pscp = ha->req_first; nscp; nscp = (Scsi_Cmnd *)nscp->SCp.ptr) {
2044 struct gdth_cmndinfo *nscp_cmndinfo = gdth_cmnd_priv(nscp);
2045 if (nscp != pscp && nscp != (Scsi_Cmnd *)pscp->SCp.ptr)
2046 pscp = (Scsi_Cmnd *)pscp->SCp.ptr;
2047 if (!nscp_cmndinfo->internal_command) {
2048 b = nscp->device->channel;
2049 t = nscp->device->id;
2050 l = nscp->device->lun;
2051 if (nscp_cmndinfo->priority >= DEFAULT_PRI) {
2052 if ((b != ha->virt_bus && ha->raw[BUS_L2P(ha,b)].lock) ||
2053 (b == ha->virt_bus && t < MAX_HDRIVES && ha->hdr[t].lock))
2060 if (gdth_test_busy(ha)) { /* controller busy ? */
2061 TRACE(("gdth_next() controller %d busy !\n", ha->hanum));
2062 if (!gdth_polling) {
2063 spin_unlock_irqrestore(&ha->smp_lock, flags);
2066 while (gdth_test_busy(ha))
2072 if (!nscp_cmndinfo->internal_command) {
2073 if (nscp_cmndinfo->phase == -1) {
2074 nscp_cmndinfo->phase = CACHESERVICE; /* default: cache svc. */
2075 if (nscp->cmnd[0] == TEST_UNIT_READY) {
2076 TRACE2(("TEST_UNIT_READY Bus %d Id %d LUN %d\n",
2078 /* TEST_UNIT_READY -> set scan mode */
2079 if ((ha->scan_mode & 0x0f) == 0) {
2080 if (b == 0 && t == 0 && l == 0) {
2082 TRACE2(("Scan mode: 0x%x\n", ha->scan_mode));
2084 } else if ((ha->scan_mode & 0x0f) == 1) {
2085 if (b == 0 && ((t == 0 && l == 1) ||
2086 (t == 1 && l == 0))) {
2087 nscp_cmndinfo->OpCode = GDT_SCAN_START;
2088 nscp_cmndinfo->phase = ((ha->scan_mode & 0x10 ? 1:0) << 8)
2090 ha->scan_mode = 0x12;
2091 TRACE2(("Scan mode: 0x%x (SCAN_START)\n",
2094 ha->scan_mode &= 0x10;
2095 TRACE2(("Scan mode: 0x%x\n", ha->scan_mode));
2097 } else if (ha->scan_mode == 0x12) {
2098 if (b == ha->bus_cnt && t == ha->tid_cnt-1) {
2099 nscp_cmndinfo->phase = SCSIRAWSERVICE;
2100 nscp_cmndinfo->OpCode = GDT_SCAN_END;
2101 ha->scan_mode &= 0x10;
2102 TRACE2(("Scan mode: 0x%x (SCAN_END)\n",
2107 if (b == ha->virt_bus && nscp->cmnd[0] != INQUIRY &&
2108 nscp->cmnd[0] != READ_CAPACITY && nscp->cmnd[0] != MODE_SENSE &&
2109 (ha->hdr[t].cluster_type & CLUSTER_DRIVE)) {
2110 /* always GDT_CLUST_INFO! */
2111 nscp_cmndinfo->OpCode = GDT_CLUST_INFO;
2116 if (nscp_cmndinfo->OpCode != -1) {
2117 if ((nscp_cmndinfo->phase & 0xff) == CACHESERVICE) {
2118 if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
2121 } else if ((nscp_cmndinfo->phase & 0xff) == SCSIRAWSERVICE) {
2122 if (!(cmd_index=gdth_fill_raw_cmd(ha, nscp, BUS_L2P(ha, b))))
2126 memset((char*)nscp->sense_buffer,0,16);
2127 nscp->sense_buffer[0] = 0x70;
2128 nscp->sense_buffer[2] = NOT_READY;
2129 nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
2130 if (!nscp_cmndinfo->wait_for_completion)
2131 nscp_cmndinfo->wait_for_completion++;
2133 gdth_scsi_done(nscp);
2135 } else if (gdth_cmnd_priv(nscp)->internal_command) {
2136 if (!(cmd_index=gdth_special_cmd(ha, nscp)))
2139 } else if (b != ha->virt_bus) {
2140 if (ha->raw[BUS_L2P(ha,b)].io_cnt[t] >= GDTH_MAX_RAW ||
2141 !(cmd_index=gdth_fill_raw_cmd(ha, nscp, BUS_L2P(ha, b))))
2144 ha->raw[BUS_L2P(ha,b)].io_cnt[t]++;
2145 } else if (t >= MAX_HDRIVES || !ha->hdr[t].present || l != 0) {
2146 TRACE2(("Command 0x%x to bus %d id %d lun %d -> IGNORE\n",
2147 nscp->cmnd[0], b, t, l));
2148 nscp->result = DID_BAD_TARGET << 16;
2149 if (!nscp_cmndinfo->wait_for_completion)
2150 nscp_cmndinfo->wait_for_completion++;
2152 gdth_scsi_done(nscp);
2154 switch (nscp->cmnd[0]) {
2155 case TEST_UNIT_READY:
2162 case SERVICE_ACTION_IN_16:
2163 TRACE(("cache cmd %x/%x/%x/%x/%x/%x\n",nscp->cmnd[0],
2164 nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
2165 nscp->cmnd[4],nscp->cmnd[5]));
2166 if (ha->hdr[t].media_changed && nscp->cmnd[0] != INQUIRY) {
2167 /* return UNIT_ATTENTION */
2168 TRACE2(("cmd 0x%x target %d: UNIT_ATTENTION\n",
2170 ha->hdr[t].media_changed = FALSE;
2171 memset((char*)nscp->sense_buffer,0,16);
2172 nscp->sense_buffer[0] = 0x70;
2173 nscp->sense_buffer[2] = UNIT_ATTENTION;
2174 nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
2175 if (!nscp_cmndinfo->wait_for_completion)
2176 nscp_cmndinfo->wait_for_completion++;
2178 gdth_scsi_done(nscp);
2179 } else if (gdth_internal_cache_cmd(ha, nscp))
2180 gdth_scsi_done(nscp);
2183 case ALLOW_MEDIUM_REMOVAL:
2184 TRACE(("cache cmd %x/%x/%x/%x/%x/%x\n",nscp->cmnd[0],
2185 nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
2186 nscp->cmnd[4],nscp->cmnd[5]));
2187 if ( (nscp->cmnd[4]&1) && !(ha->hdr[t].devtype&1) ) {
2188 TRACE(("Prevent r. nonremov. drive->do nothing\n"));
2189 nscp->result = DID_OK << 16;
2190 nscp->sense_buffer[0] = 0;
2191 if (!nscp_cmndinfo->wait_for_completion)
2192 nscp_cmndinfo->wait_for_completion++;
2194 gdth_scsi_done(nscp);
2196 nscp->cmnd[3] = (ha->hdr[t].devtype&1) ? 1:0;
2197 TRACE(("Prevent/allow r. %d rem. drive %d\n",
2198 nscp->cmnd[4],nscp->cmnd[3]));
2199 if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
2206 TRACE2(("cache cmd %s\n",nscp->cmnd[0] == RESERVE ?
2207 "RESERVE" : "RELEASE"));
2208 if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
2218 if (ha->hdr[t].media_changed) {
2219 /* return UNIT_ATTENTION */
2220 TRACE2(("cmd 0x%x target %d: UNIT_ATTENTION\n",
2222 ha->hdr[t].media_changed = FALSE;
2223 memset((char*)nscp->sense_buffer,0,16);
2224 nscp->sense_buffer[0] = 0x70;
2225 nscp->sense_buffer[2] = UNIT_ATTENTION;
2226 nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
2227 if (!nscp_cmndinfo->wait_for_completion)
2228 nscp_cmndinfo->wait_for_completion++;
2230 gdth_scsi_done(nscp);
2231 } else if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
2236 TRACE2(("cache cmd %x/%x/%x/%x/%x/%x unknown\n",nscp->cmnd[0],
2237 nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
2238 nscp->cmnd[4],nscp->cmnd[5]));
2239 printk("GDT-HA %d: Unknown SCSI command 0x%x to cache service !\n",
2240 ha->hanum, nscp->cmnd[0]);
2241 nscp->result = DID_ABORT << 16;
2242 if (!nscp_cmndinfo->wait_for_completion)
2243 nscp_cmndinfo->wait_for_completion++;
2245 gdth_scsi_done(nscp);
2252 if (nscp == ha->req_first)
2253 ha->req_first = pscp = (Scsi_Cmnd *)nscp->SCp.ptr;
2255 pscp->SCp.ptr = nscp->SCp.ptr;
2260 if (ha->cmd_cnt > 0) {
2261 gdth_release_event(ha);
2265 spin_unlock_irqrestore(&ha->smp_lock, flags);
2267 if (gdth_polling && ha->cmd_cnt > 0) {
2268 if (!gdth_wait(ha, cmd_index, POLL_TIMEOUT))
2269 printk("GDT-HA %d: Command %d timed out !\n",
2270 ha->hanum, cmd_index);
2275 * gdth_copy_internal_data() - copy to/from a buffer onto a scsi_cmnd's
2276 * buffers, kmap_atomic() as needed.
2278 static void gdth_copy_internal_data(gdth_ha_str *ha, Scsi_Cmnd *scp,
2279 char *buffer, u16 count)
2281 u16 cpcount,i, max_sg = scsi_sg_count(scp);
2283 struct scatterlist *sl;
2286 cpcount = min_t(u16, count, scsi_bufflen(scp));
2290 scsi_for_each_sg(scp, sl, max_sg, i) {
2291 unsigned long flags;
2292 cpnow = (u16)sl->length;
2293 TRACE(("copy_internal() now %d sum %d count %d %d\n",
2294 cpnow, cpsum, cpcount, scsi_bufflen(scp)));
2295 if (cpsum+cpnow > cpcount)
2296 cpnow = cpcount - cpsum;
2299 printk("GDT-HA %d: invalid sc/gt element in gdth_copy_internal_data()\n",
2303 local_irq_save(flags);
2304 address = kmap_atomic(sg_page(sl)) + sl->offset;
2305 memcpy(address, buffer, cpnow);
2306 flush_dcache_page(sg_page(sl));
2307 kunmap_atomic(address);
2308 local_irq_restore(flags);
2309 if (cpsum == cpcount)
2314 printk("GDT-HA %d: SCSI command with no buffers but data transfer expected!\n",
2320 static int gdth_internal_cache_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp)
2324 gdth_rdcap_data rdc;
2326 gdth_modep_data mpd;
2327 struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
2329 t = scp->device->id;
2330 TRACE(("gdth_internal_cache_cmd() cmd 0x%x hdrive %d\n",
2333 scp->result = DID_OK << 16;
2334 scp->sense_buffer[0] = 0;
2336 switch (scp->cmnd[0]) {
2337 case TEST_UNIT_READY:
2340 TRACE2(("Test/Verify/Start hdrive %d\n",t));
2344 TRACE2(("Inquiry hdrive %d devtype %d\n",
2345 t,ha->hdr[t].devtype));
2346 inq.type_qual = (ha->hdr[t].devtype&4) ? TYPE_ROM:TYPE_DISK;
2347 /* you can here set all disks to removable, if you want to do
2348 a flush using the ALLOW_MEDIUM_REMOVAL command */
2349 inq.modif_rmb = 0x00;
2350 if ((ha->hdr[t].devtype & 1) ||
2351 (ha->hdr[t].cluster_type & CLUSTER_DRIVE))
2352 inq.modif_rmb = 0x80;
2356 strcpy(inq.vendor,ha->oem_name);
2357 sprintf(inq.product,"Host Drive #%02d",t);
2358 strcpy(inq.revision," ");
2359 gdth_copy_internal_data(ha, scp, (char*)&inq, sizeof(gdth_inq_data));
2363 TRACE2(("Request sense hdrive %d\n",t));
2364 sd.errorcode = 0x70;
2369 gdth_copy_internal_data(ha, scp, (char*)&sd, sizeof(gdth_sense_data));
2373 TRACE2(("Mode sense hdrive %d\n",t));
2374 memset((char*)&mpd,0,sizeof(gdth_modep_data));
2375 mpd.hd.data_length = sizeof(gdth_modep_data);
2376 mpd.hd.dev_par = (ha->hdr[t].devtype&2) ? 0x80:0;
2377 mpd.hd.bd_length = sizeof(mpd.bd);
2378 mpd.bd.block_length[0] = (SECTOR_SIZE & 0x00ff0000) >> 16;
2379 mpd.bd.block_length[1] = (SECTOR_SIZE & 0x0000ff00) >> 8;
2380 mpd.bd.block_length[2] = (SECTOR_SIZE & 0x000000ff);
2381 gdth_copy_internal_data(ha, scp, (char*)&mpd, sizeof(gdth_modep_data));
2385 TRACE2(("Read capacity hdrive %d\n",t));
2386 if (ha->hdr[t].size > (u64)0xffffffff)
2387 rdc.last_block_no = 0xffffffff;
2389 rdc.last_block_no = cpu_to_be32(ha->hdr[t].size-1);
2390 rdc.block_length = cpu_to_be32(SECTOR_SIZE);
2391 gdth_copy_internal_data(ha, scp, (char*)&rdc, sizeof(gdth_rdcap_data));
2394 case SERVICE_ACTION_IN_16:
2395 if ((scp->cmnd[1] & 0x1f) == SAI_READ_CAPACITY_16 &&
2396 (ha->cache_feat & GDT_64BIT)) {
2397 gdth_rdcap16_data rdc16;
2399 TRACE2(("Read capacity (16) hdrive %d\n",t));
2400 rdc16.last_block_no = cpu_to_be64(ha->hdr[t].size-1);
2401 rdc16.block_length = cpu_to_be32(SECTOR_SIZE);
2402 gdth_copy_internal_data(ha, scp, (char*)&rdc16,
2403 sizeof(gdth_rdcap16_data));
2405 scp->result = DID_ABORT << 16;
2410 TRACE2(("Internal cache cmd 0x%x unknown\n",scp->cmnd[0]));
2414 if (!cmndinfo->wait_for_completion)
2415 cmndinfo->wait_for_completion++;
2422 static int gdth_fill_cache_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp, u16 hdrive)
2424 register gdth_cmd_str *cmdp;
2425 struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
2428 int i, cmd_index, read_write, sgcnt, mode64;
2431 TRACE(("gdth_fill_cache_cmd() cmd 0x%x cmdsize %d hdrive %d\n",
2432 scp->cmnd[0],scp->cmd_len,hdrive));
2434 if (ha->type==GDT_EISA && ha->cmd_cnt>0)
2437 mode64 = (ha->cache_feat & GDT_64BIT) ? TRUE : FALSE;
2438 /* test for READ_16, WRITE_16 if !mode64 ? ---
2439 not required, should not occur due to error return on
2442 cmdp->Service = CACHESERVICE;
2443 cmdp->RequestBuffer = scp;
2444 /* search free command index */
2445 if (!(cmd_index=gdth_get_cmd_index(ha))) {
2446 TRACE(("GDT: No free command index found\n"));
2449 /* if it's the first command, set command semaphore */
2450 if (ha->cmd_cnt == 0)
2455 if (cmndinfo->OpCode != -1)
2456 cmdp->OpCode = cmndinfo->OpCode; /* special cache cmd. */
2457 else if (scp->cmnd[0] == RESERVE)
2458 cmdp->OpCode = GDT_RESERVE_DRV;
2459 else if (scp->cmnd[0] == RELEASE)
2460 cmdp->OpCode = GDT_RELEASE_DRV;
2461 else if (scp->cmnd[0] == ALLOW_MEDIUM_REMOVAL) {
2462 if (scp->cmnd[4] & 1) /* prevent ? */
2463 cmdp->OpCode = GDT_MOUNT;
2464 else if (scp->cmnd[3] & 1) /* removable drive ? */
2465 cmdp->OpCode = GDT_UNMOUNT;
2467 cmdp->OpCode = GDT_FLUSH;
2468 } else if (scp->cmnd[0] == WRITE_6 || scp->cmnd[0] == WRITE_10 ||
2469 scp->cmnd[0] == WRITE_12 || scp->cmnd[0] == WRITE_16
2472 if (gdth_write_through || ((ha->hdr[hdrive].rw_attribs & 1) &&
2473 (ha->cache_feat & GDT_WR_THROUGH)))
2474 cmdp->OpCode = GDT_WRITE_THR;
2476 cmdp->OpCode = GDT_WRITE;
2479 cmdp->OpCode = GDT_READ;
2482 cmdp->BoardNode = LOCALBOARD;
2484 cmdp->u.cache64.DeviceNo = hdrive;
2485 cmdp->u.cache64.BlockNo = 1;
2486 cmdp->u.cache64.sg_canz = 0;
2488 cmdp->u.cache.DeviceNo = hdrive;
2489 cmdp->u.cache.BlockNo = 1;
2490 cmdp->u.cache.sg_canz = 0;
2494 if (scp->cmd_len == 16) {
2495 memcpy(&no, &scp->cmnd[2], sizeof(u64));
2496 blockno = be64_to_cpu(no);
2497 memcpy(&cnt, &scp->cmnd[10], sizeof(u32));
2498 blockcnt = be32_to_cpu(cnt);
2499 } else if (scp->cmd_len == 10) {
2500 memcpy(&no, &scp->cmnd[2], sizeof(u32));
2501 blockno = be32_to_cpu(no);
2502 memcpy(&cnt, &scp->cmnd[7], sizeof(u16));
2503 blockcnt = be16_to_cpu(cnt);
2505 memcpy(&no, &scp->cmnd[0], sizeof(u32));
2506 blockno = be32_to_cpu(no) & 0x001fffffUL;
2507 blockcnt= scp->cmnd[4]==0 ? 0x100 : scp->cmnd[4];
2510 cmdp->u.cache64.BlockNo = blockno;
2511 cmdp->u.cache64.BlockCnt = blockcnt;
2513 cmdp->u.cache.BlockNo = (u32)blockno;
2514 cmdp->u.cache.BlockCnt = blockcnt;
2517 if (scsi_bufflen(scp)) {
2518 cmndinfo->dma_dir = (read_write == 1 ?
2519 PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
2520 sgcnt = pci_map_sg(ha->pdev, scsi_sglist(scp), scsi_sg_count(scp),
2523 struct scatterlist *sl;
2525 cmdp->u.cache64.DestAddr= (u64)-1;
2526 cmdp->u.cache64.sg_canz = sgcnt;
2527 scsi_for_each_sg(scp, sl, sgcnt, i) {
2528 cmdp->u.cache64.sg_lst[i].sg_ptr = sg_dma_address(sl);
2529 #ifdef GDTH_DMA_STATISTICS
2530 if (cmdp->u.cache64.sg_lst[i].sg_ptr > (u64)0xffffffff)
2535 cmdp->u.cache64.sg_lst[i].sg_len = sg_dma_len(sl);
2538 struct scatterlist *sl;
2540 cmdp->u.cache.DestAddr= 0xffffffff;
2541 cmdp->u.cache.sg_canz = sgcnt;
2542 scsi_for_each_sg(scp, sl, sgcnt, i) {
2543 cmdp->u.cache.sg_lst[i].sg_ptr = sg_dma_address(sl);
2544 #ifdef GDTH_DMA_STATISTICS
2547 cmdp->u.cache.sg_lst[i].sg_len = sg_dma_len(sl);
2551 #ifdef GDTH_STATISTICS
2552 if (max_sg < (u32)sgcnt) {
2553 max_sg = (u32)sgcnt;
2554 TRACE3(("GDT: max_sg = %d\n",max_sg));
2560 /* evaluate command size, check space */
2562 TRACE(("cache cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
2563 cmdp->u.cache64.DestAddr,cmdp->u.cache64.sg_canz,
2564 cmdp->u.cache64.sg_lst[0].sg_ptr,
2565 cmdp->u.cache64.sg_lst[0].sg_len));
2566 TRACE(("cache cmd: cmd %d blockno. %d, blockcnt %d\n",
2567 cmdp->OpCode,cmdp->u.cache64.BlockNo,cmdp->u.cache64.BlockCnt));
2568 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.cache64.sg_lst) +
2569 (u16)cmdp->u.cache64.sg_canz * sizeof(gdth_sg64_str);
2571 TRACE(("cache cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
2572 cmdp->u.cache.DestAddr,cmdp->u.cache.sg_canz,
2573 cmdp->u.cache.sg_lst[0].sg_ptr,
2574 cmdp->u.cache.sg_lst[0].sg_len));
2575 TRACE(("cache cmd: cmd %d blockno. %d, blockcnt %d\n",
2576 cmdp->OpCode,cmdp->u.cache.BlockNo,cmdp->u.cache.BlockCnt));
2577 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.cache.sg_lst) +
2578 (u16)cmdp->u.cache.sg_canz * sizeof(gdth_sg_str);
2580 if (ha->cmd_len & 3)
2581 ha->cmd_len += (4 - (ha->cmd_len & 3));
2583 if (ha->cmd_cnt > 0) {
2584 if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
2586 TRACE2(("gdth_fill_cache() DPMEM overflow\n"));
2587 ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
2593 gdth_copy_command(ha);
2597 static int gdth_fill_raw_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp, u8 b)
2599 register gdth_cmd_str *cmdp;
2601 dma_addr_t sense_paddr;
2602 int cmd_index, sgcnt, mode64;
2605 unsigned long offset;
2606 struct gdth_cmndinfo *cmndinfo;
2608 t = scp->device->id;
2609 l = scp->device->lun;
2611 TRACE(("gdth_fill_raw_cmd() cmd 0x%x bus %d ID %d LUN %d\n",
2612 scp->cmnd[0],b,t,l));
2614 if (ha->type==GDT_EISA && ha->cmd_cnt>0)
2617 mode64 = (ha->raw_feat & GDT_64BIT) ? TRUE : FALSE;
2619 cmdp->Service = SCSIRAWSERVICE;
2620 cmdp->RequestBuffer = scp;
2621 /* search free command index */
2622 if (!(cmd_index=gdth_get_cmd_index(ha))) {
2623 TRACE(("GDT: No free command index found\n"));
2626 /* if it's the first command, set command semaphore */
2627 if (ha->cmd_cnt == 0)
2630 cmndinfo = gdth_cmnd_priv(scp);
2632 if (cmndinfo->OpCode != -1) {
2633 cmdp->OpCode = cmndinfo->OpCode; /* special raw cmd. */
2634 cmdp->BoardNode = LOCALBOARD;
2636 cmdp->u.raw64.direction = (cmndinfo->phase >> 8);
2637 TRACE2(("special raw cmd 0x%x param 0x%x\n",
2638 cmdp->OpCode, cmdp->u.raw64.direction));
2639 /* evaluate command size */
2640 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst);
2642 cmdp->u.raw.direction = (cmndinfo->phase >> 8);
2643 TRACE2(("special raw cmd 0x%x param 0x%x\n",
2644 cmdp->OpCode, cmdp->u.raw.direction));
2645 /* evaluate command size */
2646 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst);
2650 page = virt_to_page(scp->sense_buffer);
2651 offset = (unsigned long)scp->sense_buffer & ~PAGE_MASK;
2652 sense_paddr = pci_map_page(ha->pdev,page,offset,
2653 16,PCI_DMA_FROMDEVICE);
2655 cmndinfo->sense_paddr = sense_paddr;
2656 cmdp->OpCode = GDT_WRITE; /* always */
2657 cmdp->BoardNode = LOCALBOARD;
2659 cmdp->u.raw64.reserved = 0;
2660 cmdp->u.raw64.mdisc_time = 0;
2661 cmdp->u.raw64.mcon_time = 0;
2662 cmdp->u.raw64.clen = scp->cmd_len;
2663 cmdp->u.raw64.target = t;
2664 cmdp->u.raw64.lun = l;
2665 cmdp->u.raw64.bus = b;
2666 cmdp->u.raw64.priority = 0;
2667 cmdp->u.raw64.sdlen = scsi_bufflen(scp);
2668 cmdp->u.raw64.sense_len = 16;
2669 cmdp->u.raw64.sense_data = sense_paddr;
2670 cmdp->u.raw64.direction =
2671 gdth_direction_tab[scp->cmnd[0]]==DOU ? GDTH_DATA_OUT:GDTH_DATA_IN;
2672 memcpy(cmdp->u.raw64.cmd,scp->cmnd,16);
2673 cmdp->u.raw64.sg_ranz = 0;
2675 cmdp->u.raw.reserved = 0;
2676 cmdp->u.raw.mdisc_time = 0;
2677 cmdp->u.raw.mcon_time = 0;
2678 cmdp->u.raw.clen = scp->cmd_len;
2679 cmdp->u.raw.target = t;
2680 cmdp->u.raw.lun = l;
2681 cmdp->u.raw.bus = b;
2682 cmdp->u.raw.priority = 0;
2683 cmdp->u.raw.link_p = 0;
2684 cmdp->u.raw.sdlen = scsi_bufflen(scp);
2685 cmdp->u.raw.sense_len = 16;
2686 cmdp->u.raw.sense_data = sense_paddr;
2687 cmdp->u.raw.direction =
2688 gdth_direction_tab[scp->cmnd[0]]==DOU ? GDTH_DATA_OUT:GDTH_DATA_IN;
2689 memcpy(cmdp->u.raw.cmd,scp->cmnd,12);
2690 cmdp->u.raw.sg_ranz = 0;
2693 if (scsi_bufflen(scp)) {
2694 cmndinfo->dma_dir = PCI_DMA_BIDIRECTIONAL;
2695 sgcnt = pci_map_sg(ha->pdev, scsi_sglist(scp), scsi_sg_count(scp),
2698 struct scatterlist *sl;
2700 cmdp->u.raw64.sdata = (u64)-1;
2701 cmdp->u.raw64.sg_ranz = sgcnt;
2702 scsi_for_each_sg(scp, sl, sgcnt, i) {
2703 cmdp->u.raw64.sg_lst[i].sg_ptr = sg_dma_address(sl);
2704 #ifdef GDTH_DMA_STATISTICS
2705 if (cmdp->u.raw64.sg_lst[i].sg_ptr > (u64)0xffffffff)
2710 cmdp->u.raw64.sg_lst[i].sg_len = sg_dma_len(sl);
2713 struct scatterlist *sl;
2715 cmdp->u.raw.sdata = 0xffffffff;
2716 cmdp->u.raw.sg_ranz = sgcnt;
2717 scsi_for_each_sg(scp, sl, sgcnt, i) {
2718 cmdp->u.raw.sg_lst[i].sg_ptr = sg_dma_address(sl);
2719 #ifdef GDTH_DMA_STATISTICS
2722 cmdp->u.raw.sg_lst[i].sg_len = sg_dma_len(sl);
2726 #ifdef GDTH_STATISTICS
2727 if (max_sg < sgcnt) {
2729 TRACE3(("GDT: max_sg = %d\n",sgcnt));
2735 TRACE(("raw cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
2736 cmdp->u.raw64.sdata,cmdp->u.raw64.sg_ranz,
2737 cmdp->u.raw64.sg_lst[0].sg_ptr,
2738 cmdp->u.raw64.sg_lst[0].sg_len));
2739 /* evaluate command size */
2740 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst) +
2741 (u16)cmdp->u.raw64.sg_ranz * sizeof(gdth_sg64_str);
2743 TRACE(("raw cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
2744 cmdp->u.raw.sdata,cmdp->u.raw.sg_ranz,
2745 cmdp->u.raw.sg_lst[0].sg_ptr,
2746 cmdp->u.raw.sg_lst[0].sg_len));
2747 /* evaluate command size */
2748 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst) +
2749 (u16)cmdp->u.raw.sg_ranz * sizeof(gdth_sg_str);
2753 if (ha->cmd_len & 3)
2754 ha->cmd_len += (4 - (ha->cmd_len & 3));
2756 if (ha->cmd_cnt > 0) {
2757 if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
2759 TRACE2(("gdth_fill_raw() DPMEM overflow\n"));
2760 ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
2766 gdth_copy_command(ha);
2770 static int gdth_special_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp)
2772 register gdth_cmd_str *cmdp;
2773 struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
2777 TRACE2(("gdth_special_cmd(): "));
2779 if (ha->type==GDT_EISA && ha->cmd_cnt>0)
2782 *cmdp = *cmndinfo->internal_cmd_str;
2783 cmdp->RequestBuffer = scp;
2785 /* search free command index */
2786 if (!(cmd_index=gdth_get_cmd_index(ha))) {
2787 TRACE(("GDT: No free command index found\n"));
2791 /* if it's the first command, set command semaphore */
2792 if (ha->cmd_cnt == 0)
2795 /* evaluate command size, check space */
2796 if (cmdp->OpCode == GDT_IOCTL) {
2797 TRACE2(("IOCTL\n"));
2799 GDTOFFSOF(gdth_cmd_str,u.ioctl.p_param) + sizeof(u64);
2800 } else if (cmdp->Service == CACHESERVICE) {
2801 TRACE2(("cache command %d\n",cmdp->OpCode));
2802 if (ha->cache_feat & GDT_64BIT)
2804 GDTOFFSOF(gdth_cmd_str,u.cache64.sg_lst) + sizeof(gdth_sg64_str);
2807 GDTOFFSOF(gdth_cmd_str,u.cache.sg_lst) + sizeof(gdth_sg_str);
2808 } else if (cmdp->Service == SCSIRAWSERVICE) {
2809 TRACE2(("raw command %d\n",cmdp->OpCode));
2810 if (ha->raw_feat & GDT_64BIT)
2812 GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst) + sizeof(gdth_sg64_str);
2815 GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst) + sizeof(gdth_sg_str);
2818 if (ha->cmd_len & 3)
2819 ha->cmd_len += (4 - (ha->cmd_len & 3));
2821 if (ha->cmd_cnt > 0) {
2822 if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
2824 TRACE2(("gdth_special_cmd() DPMEM overflow\n"));
2825 ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
2831 gdth_copy_command(ha);
2836 /* Controller event handling functions */
2837 static gdth_evt_str *gdth_store_event(gdth_ha_str *ha, u16 source,
2838 u16 idx, gdth_evt_data *evt)
2842 /* no GDTH_LOCK_HA() ! */
2843 TRACE2(("gdth_store_event() source %d idx %d\n", source, idx));
2844 if (source == 0) /* no source -> no event */
2847 if (ebuffer[elastidx].event_source == source &&
2848 ebuffer[elastidx].event_idx == idx &&
2849 ((evt->size != 0 && ebuffer[elastidx].event_data.size != 0 &&
2850 !memcmp((char *)&ebuffer[elastidx].event_data.eu,
2851 (char *)&evt->eu, evt->size)) ||
2852 (evt->size == 0 && ebuffer[elastidx].event_data.size == 0 &&
2853 !strcmp((char *)&ebuffer[elastidx].event_data.event_string,
2854 (char *)&evt->event_string)))) {
2855 e = &ebuffer[elastidx];
2856 e->last_stamp = (u32)ktime_get_real_seconds();
2859 if (ebuffer[elastidx].event_source != 0) { /* entry not free ? */
2861 if (elastidx == MAX_EVENTS)
2863 if (elastidx == eoldidx) { /* reached mark ? */
2865 if (eoldidx == MAX_EVENTS)
2869 e = &ebuffer[elastidx];
2870 e->event_source = source;
2872 e->first_stamp = e->last_stamp = (u32)ktime_get_real_seconds();
2874 e->event_data = *evt;
2880 static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr)
2884 unsigned long flags;
2886 TRACE2(("gdth_read_event() handle %d\n", handle));
2887 spin_lock_irqsave(&ha->smp_lock, flags);
2892 estr->event_source = 0;
2894 if (eindex < 0 || eindex >= MAX_EVENTS) {
2895 spin_unlock_irqrestore(&ha->smp_lock, flags);
2898 e = &ebuffer[eindex];
2899 if (e->event_source != 0) {
2900 if (eindex != elastidx) {
2901 if (++eindex == MAX_EVENTS)
2906 memcpy(estr, e, sizeof(gdth_evt_str));
2908 spin_unlock_irqrestore(&ha->smp_lock, flags);
2912 static void gdth_readapp_event(gdth_ha_str *ha,
2913 u8 application, gdth_evt_str *estr)
2917 unsigned long flags;
2920 TRACE2(("gdth_readapp_event() app. %d\n", application));
2921 spin_lock_irqsave(&ha->smp_lock, flags);
2924 e = &ebuffer[eindex];
2925 if (e->event_source == 0)
2927 if ((e->application & application) == 0) {
2928 e->application |= application;
2932 if (eindex == elastidx)
2934 if (++eindex == MAX_EVENTS)
2938 memcpy(estr, e, sizeof(gdth_evt_str));
2940 estr->event_source = 0;
2941 spin_unlock_irqrestore(&ha->smp_lock, flags);
2944 static void gdth_clear_events(void)
2946 TRACE(("gdth_clear_events()"));
2948 eoldidx = elastidx = 0;
2949 ebuffer[0].event_source = 0;
2953 /* SCSI interface functions */
2955 static irqreturn_t __gdth_interrupt(gdth_ha_str *ha,
2956 int gdth_from_wait, int* pIndex)
2958 gdt6m_dpram_str __iomem *dp6m_ptr = NULL;
2959 gdt6_dpram_str __iomem *dp6_ptr;
2960 gdt2_dpram_str __iomem *dp2_ptr;
2965 unsigned long flags = 0;
2967 int coalesced = FALSE;
2969 gdth_coal_status *pcs = NULL;
2970 int act_int_coal = 0;
2973 TRACE(("gdth_interrupt() IRQ %d\n", ha->irq));
2975 /* if polling and not from gdth_wait() -> return */
2977 if (!gdth_from_wait) {
2983 spin_lock_irqsave(&ha->smp_lock, flags);
2985 /* search controller */
2986 IStatus = gdth_get_status(ha);
2988 /* spurious interrupt */
2990 spin_unlock_irqrestore(&ha->smp_lock, flags);
2994 #ifdef GDTH_STATISTICS
2999 /* See if the fw is returning coalesced status */
3000 if (IStatus == COALINDEX) {
3001 /* Coalesced status. Setup the initial status
3002 buffer pointer and flags */
3003 pcs = ha->coal_stat;
3010 /* For coalesced requests all status
3011 information is found in the status buffer */
3012 IStatus = (u8)(pcs->status & 0xff);
3016 if (ha->type == GDT_EISA) {
3017 if (IStatus & 0x80) { /* error flag */
3019 ha->status = inw(ha->bmic + MAILBOXREG+8);
3020 TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
3021 } else /* no error */
3023 ha->info = inl(ha->bmic + MAILBOXREG+12);
3024 ha->service = inw(ha->bmic + MAILBOXREG+10);
3025 ha->info2 = inl(ha->bmic + MAILBOXREG+4);
3027 outb(0xff, ha->bmic + EDOORREG); /* acknowledge interrupt */
3028 outb(0x00, ha->bmic + SEMA1REG); /* reset status semaphore */
3029 } else if (ha->type == GDT_ISA) {
3031 if (IStatus & 0x80) { /* error flag */
3033 ha->status = readw(&dp2_ptr->u.ic.Status);
3034 TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
3035 } else /* no error */
3037 ha->info = readl(&dp2_ptr->u.ic.Info[0]);
3038 ha->service = readw(&dp2_ptr->u.ic.Service);
3039 ha->info2 = readl(&dp2_ptr->u.ic.Info[1]);
3041 writeb(0xff, &dp2_ptr->io.irqdel); /* acknowledge interrupt */
3042 writeb(0, &dp2_ptr->u.ic.Cmd_Index);/* reset command index */
3043 writeb(0, &dp2_ptr->io.Sema1); /* reset status semaphore */
3044 } else if (ha->type == GDT_PCI) {
3046 if (IStatus & 0x80) { /* error flag */
3048 ha->status = readw(&dp6_ptr->u.ic.Status);
3049 TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
3050 } else /* no error */
3052 ha->info = readl(&dp6_ptr->u.ic.Info[0]);
3053 ha->service = readw(&dp6_ptr->u.ic.Service);
3054 ha->info2 = readl(&dp6_ptr->u.ic.Info[1]);
3056 writeb(0xff, &dp6_ptr->io.irqdel); /* acknowledge interrupt */
3057 writeb(0, &dp6_ptr->u.ic.Cmd_Index);/* reset command index */
3058 writeb(0, &dp6_ptr->io.Sema1); /* reset status semaphore */
3059 } else if (ha->type == GDT_PCINEW) {
3060 if (IStatus & 0x80) { /* error flag */
3062 ha->status = inw(PTR2USHORT(&ha->plx->status));
3063 TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
3066 ha->info = inl(PTR2USHORT(&ha->plx->info[0]));
3067 ha->service = inw(PTR2USHORT(&ha->plx->service));
3068 ha->info2 = inl(PTR2USHORT(&ha->plx->info[1]));
3070 outb(0xff, PTR2USHORT(&ha->plx->edoor_reg));
3071 outb(0x00, PTR2USHORT(&ha->plx->sema1_reg));
3072 } else if (ha->type == GDT_PCIMPR) {
3074 if (IStatus & 0x80) { /* error flag */
3078 ha->status = pcs->ext_status & 0xffff;
3081 ha->status = readw(&dp6m_ptr->i960r.status);
3082 TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
3083 } else /* no error */
3086 /* get information */
3088 ha->info = pcs->info0;
3089 ha->info2 = pcs->info1;
3090 ha->service = (pcs->ext_status >> 16) & 0xffff;
3094 ha->info = readl(&dp6m_ptr->i960r.info[0]);
3095 ha->service = readw(&dp6m_ptr->i960r.service);
3096 ha->info2 = readl(&dp6m_ptr->i960r.info[1]);
3099 if (IStatus == ASYNCINDEX) {
3100 if (ha->service != SCREENSERVICE &&
3101 (ha->fw_vers & 0xff) >= 0x1a) {
3102 ha->dvr.severity = readb
3103 (&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.severity);
3104 for (i = 0; i < 256; ++i) {
3105 ha->dvr.event_string[i] = readb
3106 (&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.evt_str[i]);
3107 if (ha->dvr.event_string[i] == 0)
3113 /* Make sure that non coalesced interrupts get cleared
3114 before being handled by gdth_async_event/gdth_sync_event */
3118 writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
3119 writeb(0, &dp6m_ptr->i960r.sema1_reg);
3122 TRACE2(("gdth_interrupt() unknown controller type\n"));
3124 spin_unlock_irqrestore(&ha->smp_lock, flags);
3128 TRACE(("gdth_interrupt() index %d stat %d info %d\n",
3129 IStatus,ha->status,ha->info));
3131 if (gdth_from_wait) {
3132 *pIndex = (int)IStatus;
3135 if (IStatus == ASYNCINDEX) {
3136 TRACE2(("gdth_interrupt() async. event\n"));
3137 gdth_async_event(ha);
3139 spin_unlock_irqrestore(&ha->smp_lock, flags);
3144 if (IStatus == SPEZINDEX) {
3145 TRACE2(("Service unknown or not initialized !\n"));
3146 ha->dvr.size = sizeof(ha->dvr.eu.driver);
3147 ha->dvr.eu.driver.ionode = ha->hanum;
3148 gdth_store_event(ha, ES_DRIVER, 4, &ha->dvr);
3150 spin_unlock_irqrestore(&ha->smp_lock, flags);
3153 scp = ha->cmd_tab[IStatus-2].cmnd;
3154 Service = ha->cmd_tab[IStatus-2].service;
3155 ha->cmd_tab[IStatus-2].cmnd = UNUSED_CMND;
3156 if (scp == UNUSED_CMND) {
3157 TRACE2(("gdth_interrupt() index to unused command (%d)\n",IStatus));
3158 ha->dvr.size = sizeof(ha->dvr.eu.driver);
3159 ha->dvr.eu.driver.ionode = ha->hanum;
3160 ha->dvr.eu.driver.index = IStatus;
3161 gdth_store_event(ha, ES_DRIVER, 1, &ha->dvr);
3163 spin_unlock_irqrestore(&ha->smp_lock, flags);
3166 if (scp == INTERNAL_CMND) {
3167 TRACE(("gdth_interrupt() answer to internal command\n"));
3169 spin_unlock_irqrestore(&ha->smp_lock, flags);
3173 TRACE(("gdth_interrupt() sync. status\n"));
3174 rval = gdth_sync_event(ha,Service,IStatus,scp);
3176 spin_unlock_irqrestore(&ha->smp_lock, flags);
3178 gdth_putq(ha, scp, gdth_cmnd_priv(scp)->priority);
3179 } else if (rval == 1) {
3180 gdth_scsi_done(scp);
3185 /* go to the next status in the status buffer */
3187 #ifdef GDTH_STATISTICS
3189 if (act_int_coal > max_int_coal) {
3190 max_int_coal = act_int_coal;
3191 printk("GDT: max_int_coal = %d\n",(u16)max_int_coal);
3194 /* see if there is another status */
3195 if (pcs->status == 0)
3196 /* Stop the coalesce loop */
3201 /* coalescing only for new GDT_PCIMPR controllers available */
3202 if (ha->type == GDT_PCIMPR && coalesced) {
3203 writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
3204 writeb(0, &dp6m_ptr->i960r.sema1_reg);
3212 static irqreturn_t gdth_interrupt(int irq, void *dev_id)
3214 gdth_ha_str *ha = dev_id;
3216 return __gdth_interrupt(ha, false, NULL);
3219 static int gdth_sync_event(gdth_ha_str *ha, int service, u8 index,
3225 struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
3228 TRACE(("gdth_sync_event() serv %d status %d\n",
3229 service,ha->status));
3231 if (service == SCREENSERVICE) {
3233 TRACE(("len: %d, answer: %d, ext: %d, alen: %d\n",
3234 msg->msg_len,msg->msg_answer,msg->msg_ext,msg->msg_alen));
3235 if (msg->msg_len > MSGLEN+1)
3236 msg->msg_len = MSGLEN+1;
3238 if (!(msg->msg_answer && msg->msg_ext)) {
3239 msg->msg_text[msg->msg_len] = '\0';
3240 printk("%s",msg->msg_text);
3243 if (msg->msg_ext && !msg->msg_answer) {
3244 while (gdth_test_busy(ha))
3246 cmdp->Service = SCREENSERVICE;
3247 cmdp->RequestBuffer = SCREEN_CMND;
3248 gdth_get_cmd_index(ha);
3250 cmdp->OpCode = GDT_READ;
3251 cmdp->BoardNode = LOCALBOARD;
3252 cmdp->u.screen.reserved = 0;
3253 cmdp->u.screen.su.msg.msg_handle= msg->msg_handle;
3254 cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
3255 ha->cmd_offs_dpmem = 0;
3256 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
3259 gdth_copy_command(ha);
3260 gdth_release_event(ha);
3264 if (msg->msg_answer && msg->msg_alen) {
3265 /* default answers (getchar() not possible) */
3266 if (msg->msg_alen == 1) {
3269 msg->msg_text[0] = 0;
3273 msg->msg_text[0] = 1;
3274 msg->msg_text[1] = 0;
3277 msg->msg_answer = 0;
3278 while (gdth_test_busy(ha))
3280 cmdp->Service = SCREENSERVICE;
3281 cmdp->RequestBuffer = SCREEN_CMND;
3282 gdth_get_cmd_index(ha);
3284 cmdp->OpCode = GDT_WRITE;
3285 cmdp->BoardNode = LOCALBOARD;
3286 cmdp->u.screen.reserved = 0;
3287 cmdp->u.screen.su.msg.msg_handle= msg->msg_handle;
3288 cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
3289 ha->cmd_offs_dpmem = 0;
3290 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
3293 gdth_copy_command(ha);
3294 gdth_release_event(ha);
3300 b = scp->device->channel;
3301 t = scp->device->id;
3302 if (cmndinfo->OpCode == -1 && b != ha->virt_bus) {
3303 ha->raw[BUS_L2P(ha,b)].io_cnt[t]--;
3305 /* cache or raw service */
3306 if (ha->status == S_BSY) {
3307 TRACE2(("Controller busy -> retry !\n"));
3308 if (cmndinfo->OpCode == GDT_MOUNT)
3309 cmndinfo->OpCode = GDT_CLUST_INFO;
3313 if (scsi_bufflen(scp))
3314 pci_unmap_sg(ha->pdev, scsi_sglist(scp), scsi_sg_count(scp),
3317 if (cmndinfo->sense_paddr)
3318 pci_unmap_page(ha->pdev, cmndinfo->sense_paddr, 16,
3319 PCI_DMA_FROMDEVICE);
3321 if (ha->status == S_OK) {
3322 cmndinfo->status = S_OK;
3323 cmndinfo->info = ha->info;
3324 if (cmndinfo->OpCode != -1) {
3325 TRACE2(("gdth_sync_event(): special cmd 0x%x OK\n",
3327 /* special commands GDT_CLUST_INFO/GDT_MOUNT ? */
3328 if (cmndinfo->OpCode == GDT_CLUST_INFO) {
3329 ha->hdr[t].cluster_type = (u8)ha->info;
3330 if (!(ha->hdr[t].cluster_type &
3332 /* NOT MOUNTED -> MOUNT */
3333 cmndinfo->OpCode = GDT_MOUNT;
3334 if (ha->hdr[t].cluster_type &
3336 /* cluster drive RESERVED (on the other node) */
3337 cmndinfo->phase = -2; /* reservation conflict */
3340 cmndinfo->OpCode = -1;
3343 if (cmndinfo->OpCode == GDT_MOUNT) {
3344 ha->hdr[t].cluster_type |= CLUSTER_MOUNTED;
3345 ha->hdr[t].media_changed = TRUE;
3346 } else if (cmndinfo->OpCode == GDT_UNMOUNT) {
3347 ha->hdr[t].cluster_type &= ~CLUSTER_MOUNTED;
3348 ha->hdr[t].media_changed = TRUE;
3350 cmndinfo->OpCode = -1;
3353 cmndinfo->priority = HIGH_PRI;
3356 /* RESERVE/RELEASE ? */
3357 if (scp->cmnd[0] == RESERVE) {
3358 ha->hdr[t].cluster_type |= CLUSTER_RESERVED;
3359 } else if (scp->cmnd[0] == RELEASE) {
3360 ha->hdr[t].cluster_type &= ~CLUSTER_RESERVED;
3362 scp->result = DID_OK << 16;
3363 scp->sense_buffer[0] = 0;
3366 cmndinfo->status = ha->status;
3367 cmndinfo->info = ha->info;
3369 if (cmndinfo->OpCode != -1) {
3370 TRACE2(("gdth_sync_event(): special cmd 0x%x error 0x%x\n",
3371 cmndinfo->OpCode, ha->status));
3372 if (cmndinfo->OpCode == GDT_SCAN_START ||
3373 cmndinfo->OpCode == GDT_SCAN_END) {
3374 cmndinfo->OpCode = -1;
3376 cmndinfo->priority = HIGH_PRI;
3379 memset((char*)scp->sense_buffer,0,16);
3380 scp->sense_buffer[0] = 0x70;
3381 scp->sense_buffer[2] = NOT_READY;
3382 scp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
3383 } else if (service == CACHESERVICE) {
3384 if (ha->status == S_CACHE_UNKNOWN &&
3385 (ha->hdr[t].cluster_type &
3386 CLUSTER_RESERVE_STATE) == CLUSTER_RESERVE_STATE) {
3387 /* bus reset -> force GDT_CLUST_INFO */
3388 ha->hdr[t].cluster_type &= ~CLUSTER_RESERVED;
3390 memset((char*)scp->sense_buffer,0,16);
3391 if (ha->status == (u16)S_CACHE_RESERV) {
3392 scp->result = (DID_OK << 16) | (RESERVATION_CONFLICT << 1);
3394 scp->sense_buffer[0] = 0x70;
3395 scp->sense_buffer[2] = NOT_READY;
3396 scp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
3398 if (!cmndinfo->internal_command) {
3399 ha->dvr.size = sizeof(ha->dvr.eu.sync);
3400 ha->dvr.eu.sync.ionode = ha->hanum;
3401 ha->dvr.eu.sync.service = service;
3402 ha->dvr.eu.sync.status = ha->status;
3403 ha->dvr.eu.sync.info = ha->info;
3404 ha->dvr.eu.sync.hostdrive = t;
3405 if (ha->status >= 0x8000)
3406 gdth_store_event(ha, ES_SYNC, 0, &ha->dvr);
3408 gdth_store_event(ha, ES_SYNC, service, &ha->dvr);
3411 /* sense buffer filled from controller firmware (DMA) */
3412 if (ha->status != S_RAW_SCSI || ha->info >= 0x100) {
3413 scp->result = DID_BAD_TARGET << 16;
3415 scp->result = (DID_OK << 16) | ha->info;
3419 if (!cmndinfo->wait_for_completion)
3420 cmndinfo->wait_for_completion++;
3428 static char *async_cache_tab[] = {
3429 /* 0*/ "\011\000\002\002\002\004\002\006\004"
3430 "GDT HA %u, service %u, async. status %u/%lu unknown",
3431 /* 1*/ "\011\000\002\002\002\004\002\006\004"
3432 "GDT HA %u, service %u, async. status %u/%lu unknown",
3433 /* 2*/ "\005\000\002\006\004"
3434 "GDT HA %u, Host Drive %lu not ready",
3435 /* 3*/ "\005\000\002\006\004"
3436 "GDT HA %u, Host Drive %lu: REASSIGN not successful and/or data error on reassigned blocks. Drive may crash in the future and should be replaced",
3437 /* 4*/ "\005\000\002\006\004"
3438 "GDT HA %u, mirror update on Host Drive %lu failed",
3439 /* 5*/ "\005\000\002\006\004"
3440 "GDT HA %u, Mirror Drive %lu failed",
3441 /* 6*/ "\005\000\002\006\004"
3442 "GDT HA %u, Mirror Drive %lu: REASSIGN not successful and/or data error on reassigned blocks. Drive may crash in the future and should be replaced",
3443 /* 7*/ "\005\000\002\006\004"
3444 "GDT HA %u, Host Drive %lu write protected",
3445 /* 8*/ "\005\000\002\006\004"
3446 "GDT HA %u, media changed in Host Drive %lu",
3447 /* 9*/ "\005\000\002\006\004"
3448 "GDT HA %u, Host Drive %lu is offline",
3449 /*10*/ "\005\000\002\006\004"
3450 "GDT HA %u, media change of Mirror Drive %lu",
3451 /*11*/ "\005\000\002\006\004"
3452 "GDT HA %u, Mirror Drive %lu is write protected",
3453 /*12*/ "\005\000\002\006\004"
3454 "GDT HA %u, general error on Host Drive %lu. Please check the devices of this drive!",
3455 /*13*/ "\007\000\002\006\002\010\002"
3456 "GDT HA %u, Array Drive %u: Cache Drive %u failed",
3457 /*14*/ "\005\000\002\006\002"
3458 "GDT HA %u, Array Drive %u: FAIL state entered",
3459 /*15*/ "\005\000\002\006\002"
3460 "GDT HA %u, Array Drive %u: error",
3461 /*16*/ "\007\000\002\006\002\010\002"
3462 "GDT HA %u, Array Drive %u: failed drive replaced by Cache Drive %u",
3463 /*17*/ "\005\000\002\006\002"
3464 "GDT HA %u, Array Drive %u: parity build failed",
3465 /*18*/ "\005\000\002\006\002"
3466 "GDT HA %u, Array Drive %u: drive rebuild failed",
3467 /*19*/ "\005\000\002\010\002"
3468 "GDT HA %u, Test of Hot Fix %u failed",
3469 /*20*/ "\005\000\002\006\002"
3470 "GDT HA %u, Array Drive %u: drive build finished successfully",
3471 /*21*/ "\005\000\002\006\002"
3472 "GDT HA %u, Array Drive %u: drive rebuild finished successfully",
3473 /*22*/ "\007\000\002\006\002\010\002"
3474 "GDT HA %u, Array Drive %u: Hot Fix %u activated",
3475 /*23*/ "\005\000\002\006\002"
3476 "GDT HA %u, Host Drive %u: processing of i/o aborted due to serious drive error",
3477 /*24*/ "\005\000\002\010\002"
3478 "GDT HA %u, mirror update on Cache Drive %u completed",
3479 /*25*/ "\005\000\002\010\002"
3480 "GDT HA %u, mirror update on Cache Drive %lu failed",
3481 /*26*/ "\005\000\002\006\002"
3482 "GDT HA %u, Array Drive %u: drive rebuild started",
3483 /*27*/ "\005\000\002\012\001"
3484 "GDT HA %u, Fault bus %u: SHELF OK detected",
3485 /*28*/ "\005\000\002\012\001"
3486 "GDT HA %u, Fault bus %u: SHELF not OK detected",
3487 /*29*/ "\007\000\002\012\001\013\001"
3488 "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug started",
3489 /*30*/ "\007\000\002\012\001\013\001"
3490 "GDT HA %u, Fault bus %u, ID %u: new disk detected",
3491 /*31*/ "\007\000\002\012\001\013\001"
3492 "GDT HA %u, Fault bus %u, ID %u: old disk detected",
3493 /*32*/ "\007\000\002\012\001\013\001"
3494 "GDT HA %u, Fault bus %u, ID %u: plugging an active disk is invalid",
3495 /*33*/ "\007\000\002\012\001\013\001"
3496 "GDT HA %u, Fault bus %u, ID %u: invalid device detected",
3497 /*34*/ "\011\000\002\012\001\013\001\006\004"
3498 "GDT HA %u, Fault bus %u, ID %u: insufficient disk capacity (%lu MB required)",
3499 /*35*/ "\007\000\002\012\001\013\001"
3500 "GDT HA %u, Fault bus %u, ID %u: disk write protected",
3501 /*36*/ "\007\000\002\012\001\013\001"
3502 "GDT HA %u, Fault bus %u, ID %u: disk not available",
3503 /*37*/ "\007\000\002\012\001\006\004"
3504 "GDT HA %u, Fault bus %u: swap detected (%lu)",
3505 /*38*/ "\007\000\002\012\001\013\001"
3506 "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug finished successfully",
3507 /*39*/ "\007\000\002\012\001\013\001"
3508 "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug aborted due to user Hot Plug",
3509 /*40*/ "\007\000\002\012\001\013\001"
3510 "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug aborted",
3511 /*41*/ "\007\000\002\012\001\013\001"
3512 "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug for Hot Fix started",
3513 /*42*/ "\005\000\002\006\002"
3514 "GDT HA %u, Array Drive %u: drive build started",
3515 /*43*/ "\003\000\002"
3516 "GDT HA %u, DRAM parity error detected",
3517 /*44*/ "\005\000\002\006\002"
3518 "GDT HA %u, Mirror Drive %u: update started",
3519 /*45*/ "\007\000\002\006\002\010\002"
3520 "GDT HA %u, Mirror Drive %u: Hot Fix %u activated",
3521 /*46*/ "\005\000\002\006\002"
3522 "GDT HA %u, Array Drive %u: no matching Pool Hot Fix Drive available",
3523 /*47*/ "\005\000\002\006\002"
3524 "GDT HA %u, Array Drive %u: Pool Hot Fix Drive available",
3525 /*48*/ "\005\000\002\006\002"
3526 "GDT HA %u, Mirror Drive %u: no matching Pool Hot Fix Drive available",
3527 /*49*/ "\005\000\002\006\002"
3528 "GDT HA %u, Mirror Drive %u: Pool Hot Fix Drive available",
3529 /*50*/ "\007\000\002\012\001\013\001"
3530 "GDT HA %u, SCSI bus %u, ID %u: IGNORE_WIDE_RESIDUE message received",
3531 /*51*/ "\005\000\002\006\002"
3532 "GDT HA %u, Array Drive %u: expand started",
3533 /*52*/ "\005\000\002\006\002"
3534 "GDT HA %u, Array Drive %u: expand finished successfully",
3535 /*53*/ "\005\000\002\006\002"
3536 "GDT HA %u, Array Drive %u: expand failed",
3537 /*54*/ "\003\000\002"
3538 "GDT HA %u, CPU temperature critical",
3539 /*55*/ "\003\000\002"
3540 "GDT HA %u, CPU temperature OK",
3541 /*56*/ "\005\000\002\006\004"
3542 "GDT HA %u, Host drive %lu created",
3543 /*57*/ "\005\000\002\006\002"
3544 "GDT HA %u, Array Drive %u: expand restarted",
3545 /*58*/ "\005\000\002\006\002"
3546 "GDT HA %u, Array Drive %u: expand stopped",
3547 /*59*/ "\005\000\002\010\002"
3548 "GDT HA %u, Mirror Drive %u: drive build quited",
3549 /*60*/ "\005\000\002\006\002"
3550 "GDT HA %u, Array Drive %u: parity build quited",
3551 /*61*/ "\005\000\002\006\002"
3552 "GDT HA %u, Array Drive %u: drive rebuild quited",
3553 /*62*/ "\005\000\002\006\002"
3554 "GDT HA %u, Array Drive %u: parity verify started",
3555 /*63*/ "\005\000\002\006\002"
3556 "GDT HA %u, Array Drive %u: parity verify done",
3557 /*64*/ "\005\000\002\006\002"
3558 "GDT HA %u, Array Drive %u: parity verify failed",
3559 /*65*/ "\005\000\002\006\002"
3560 "GDT HA %u, Array Drive %u: parity error detected",
3561 /*66*/ "\005\000\002\006\002"
3562 "GDT HA %u, Array Drive %u: parity verify quited",
3563 /*67*/ "\005\000\002\006\002"
3564 "GDT HA %u, Host Drive %u reserved",
3565 /*68*/ "\005\000\002\006\002"
3566 "GDT HA %u, Host Drive %u mounted and released",
3567 /*69*/ "\005\000\002\006\002"
3568 "GDT HA %u, Host Drive %u released",
3569 /*70*/ "\003\000\002"
3570 "GDT HA %u, DRAM error detected and corrected with ECC",
3571 /*71*/ "\003\000\002"
3572 "GDT HA %u, Uncorrectable DRAM error detected with ECC",
3573 /*72*/ "\011\000\002\012\001\013\001\014\001"
3574 "GDT HA %u, SCSI bus %u, ID %u, LUN %u: reassigning block",
3575 /*73*/ "\005\000\002\006\002"
3576 "GDT HA %u, Host drive %u resetted locally",
3577 /*74*/ "\005\000\002\006\002"
3578 "GDT HA %u, Host drive %u resetted remotely",
3579 /*75*/ "\003\000\002"
3580 "GDT HA %u, async. status 75 unknown",
3584 static int gdth_async_event(gdth_ha_str *ha)
3590 TRACE2(("gdth_async_event() ha %d serv %d\n",
3591 ha->hanum, ha->service));
3593 if (ha->service == SCREENSERVICE) {
3594 if (ha->status == MSG_REQUEST) {
3595 while (gdth_test_busy(ha))
3597 cmdp->Service = SCREENSERVICE;
3598 cmdp->RequestBuffer = SCREEN_CMND;
3599 cmd_index = gdth_get_cmd_index(ha);
3601 cmdp->OpCode = GDT_READ;
3602 cmdp->BoardNode = LOCALBOARD;
3603 cmdp->u.screen.reserved = 0;
3604 cmdp->u.screen.su.msg.msg_handle= MSG_INV_HANDLE;
3605 cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
3606 ha->cmd_offs_dpmem = 0;
3607 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
3610 gdth_copy_command(ha);
3611 if (ha->type == GDT_EISA)
3612 printk("[EISA slot %d] ",(u16)ha->brd_phys);
3613 else if (ha->type == GDT_ISA)
3614 printk("[DPMEM 0x%4X] ",(u16)ha->brd_phys);
3616 printk("[PCI %d/%d] ",(u16)(ha->brd_phys>>8),
3617 (u16)((ha->brd_phys>>3)&0x1f));
3618 gdth_release_event(ha);
3622 if (ha->type == GDT_PCIMPR &&
3623 (ha->fw_vers & 0xff) >= 0x1a) {
3625 ha->dvr.eu.async.ionode = ha->hanum;
3626 ha->dvr.eu.async.status = ha->status;
3627 /* severity and event_string already set! */
3629 ha->dvr.size = sizeof(ha->dvr.eu.async);
3630 ha->dvr.eu.async.ionode = ha->hanum;
3631 ha->dvr.eu.async.service = ha->service;
3632 ha->dvr.eu.async.status = ha->status;
3633 ha->dvr.eu.async.info = ha->info;
3634 *(u32 *)ha->dvr.eu.async.scsi_coord = ha->info2;
3636 gdth_store_event( ha, ES_ASYNC, ha->service, &ha->dvr );
3637 gdth_log_event( &ha->dvr, NULL );
3639 /* new host drive from expand? */
3640 if (ha->service == CACHESERVICE && ha->status == 56) {
3641 TRACE2(("gdth_async_event(): new host drive %d created\n",
3643 /* gdth_analyse_hdrive(hanum, (u16)ha->info); */
3649 static void gdth_log_event(gdth_evt_data *dvr, char *buffer)
3651 gdth_stackframe stack;
3655 TRACE2(("gdth_log_event()\n"));
3656 if (dvr->size == 0) {
3657 if (buffer == NULL) {
3658 printk("Adapter %d: %s\n",dvr->eu.async.ionode,dvr->event_string);
3660 sprintf(buffer,"Adapter %d: %s\n",
3661 dvr->eu.async.ionode,dvr->event_string);
3663 } else if (dvr->eu.async.service == CACHESERVICE &&
3664 INDEX_OK(dvr->eu.async.status, async_cache_tab)) {
3665 TRACE2(("GDT: Async. event cache service, event no.: %d\n",
3666 dvr->eu.async.status));
3668 f = async_cache_tab[dvr->eu.async.status];
3670 /* i: parameter to push, j: stack element to fill */
3671 for (j=0,i=1; i < f[0]; i+=2) {
3674 stack.b[j++] = *(u32*)&dvr->eu.stream[(int)f[i]];
3677 stack.b[j++] = *(u16*)&dvr->eu.stream[(int)f[i]];
3680 stack.b[j++] = *(u8*)&dvr->eu.stream[(int)f[i]];
3687 if (buffer == NULL) {
3688 printk(&f[(int)f[0]],stack);
3691 sprintf(buffer,&f[(int)f[0]],stack);
3695 if (buffer == NULL) {
3696 printk("GDT HA %u, Unknown async. event service %d event no. %d\n",
3697 dvr->eu.async.ionode,dvr->eu.async.service,dvr->eu.async.status);
3699 sprintf(buffer,"GDT HA %u, Unknown async. event service %d event no. %d",
3700 dvr->eu.async.ionode,dvr->eu.async.service,dvr->eu.async.status);
3705 #ifdef GDTH_STATISTICS
3706 static u8 gdth_timer_running;
3708 static void gdth_timeout(unsigned long data)
3713 unsigned long flags;
3715 if(unlikely(list_empty(&gdth_instances))) {
3716 gdth_timer_running = 0;
3720 ha = list_first_entry(&gdth_instances, gdth_ha_str, list);
3721 spin_lock_irqsave(&ha->smp_lock, flags);
3723 for (act_stats=0,i=0; i<GDTH_MAXCMDS; ++i)
3724 if (ha->cmd_tab[i].cmnd != UNUSED_CMND)
3727 for (act_rq=0,nscp=ha->req_first; nscp; nscp=(Scsi_Cmnd*)nscp->SCp.ptr)
3730 TRACE2(("gdth_to(): ints %d, ios %d, act_stats %d, act_rq %d\n",
3731 act_ints, act_ios, act_stats, act_rq));
3732 act_ints = act_ios = 0;
3734 gdth_timer.expires = jiffies + 30 * HZ;
3735 add_timer(&gdth_timer);
3736 spin_unlock_irqrestore(&ha->smp_lock, flags);
3739 static void gdth_timer_init(void)
3741 if (gdth_timer_running)
3743 gdth_timer_running = 1;
3744 TRACE2(("gdth_detect(): Initializing timer !\n"));
3745 gdth_timer.expires = jiffies + HZ;
3746 gdth_timer.data = 0L;
3747 gdth_timer.function = gdth_timeout;
3748 add_timer(&gdth_timer);
3751 static inline void gdth_timer_init(void)
3756 static void __init internal_setup(char *str,int *ints)
3759 char *cur_str, *argv;
3761 TRACE2(("internal_setup() str %s ints[0] %d\n",
3762 str ? str:"NULL", ints ? ints[0]:0));
3764 /* read irq[] from ints[] */
3770 for (i = 0; i < argc; ++i)
3775 /* analyse string */
3777 while (argv && (cur_str = strchr(argv, ':'))) {
3778 int val = 0, c = *++cur_str;
3780 if (c == 'n' || c == 'N')
3782 else if (c == 'y' || c == 'Y')
3785 val = (int)simple_strtoul(cur_str, NULL, 0);
3787 if (!strncmp(argv, "disable:", 8))
3789 else if (!strncmp(argv, "reserve_mode:", 13))
3791 else if (!strncmp(argv, "reverse_scan:", 13))
3793 else if (!strncmp(argv, "hdr_channel:", 12))
3795 else if (!strncmp(argv, "max_ids:", 8))
3797 else if (!strncmp(argv, "rescan:", 7))
3799 else if (!strncmp(argv, "shared_access:", 14))
3800 shared_access = val;
3801 else if (!strncmp(argv, "probe_eisa_isa:", 15))
3802 probe_eisa_isa = val;
3803 else if (!strncmp(argv, "reserve_list:", 13)) {
3804 reserve_list[0] = val;
3805 for (i = 1; i < MAX_RES_ARGS; i++) {
3806 cur_str = strchr(cur_str, ',');
3809 if (!isdigit((int)*++cur_str)) {
3814 (int)simple_strtoul(cur_str, NULL, 0);
3822 if ((argv = strchr(argv, ',')))
3827 int __init option_setup(char *str)
3833 TRACE2(("option_setup() str %s\n", str ? str:"NULL"));
3835 while (cur && isdigit(*cur) && i < MAXHA) {
3836 ints[i++] = simple_strtoul(cur, NULL, 0);
3837 if ((cur = strchr(cur, ',')) != NULL) cur++;
3841 internal_setup(cur, ints);
3845 static const char *gdth_ctr_name(gdth_ha_str *ha)
3847 TRACE2(("gdth_ctr_name()\n"));
3849 if (ha->type == GDT_EISA) {
3850 switch (ha->stype) {
3852 return("GDT3000/3020");
3854 return("GDT3000A/3020A/3050A");
3856 return("GDT3000B/3010A");
3858 } else if (ha->type == GDT_ISA) {
3859 return("GDT2000/2020");
3860 } else if (ha->type == GDT_PCI) {
3861 switch (ha->pdev->device) {
3862 case PCI_DEVICE_ID_VORTEX_GDT60x0:
3863 return("GDT6000/6020/6050");
3864 case PCI_DEVICE_ID_VORTEX_GDT6000B:
3865 return("GDT6000B/6010");
3868 /* new controllers (GDT_PCINEW, GDT_PCIMPR, ..) use board_info IOCTL! */
3873 static const char *gdth_info(struct Scsi_Host *shp)
3875 gdth_ha_str *ha = shost_priv(shp);
3877 TRACE2(("gdth_info()\n"));
3878 return ((const char *)ha->binfo.type_string);
3881 static enum blk_eh_timer_return gdth_timed_out(struct scsi_cmnd *scp)
3883 gdth_ha_str *ha = shost_priv(scp->device->host);
3884 struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
3886 unsigned long flags;
3887 enum blk_eh_timer_return retval = BLK_EH_NOT_HANDLED;
3889 TRACE(("%s() cmd 0x%x\n", scp->cmnd[0], __func__));
3890 b = scp->device->channel;
3891 t = scp->device->id;
3894 * We don't really honor the command timeout, but we try to
3895 * honor 6 times of the actual command timeout! So reset the
3896 * timer if this is less than 6th timeout on this command!
3898 if (++cmndinfo->timeout_count < 6)
3899 retval = BLK_EH_RESET_TIMER;
3901 /* Reset the timeout if it is locked IO */
3902 spin_lock_irqsave(&ha->smp_lock, flags);
3903 if ((b != ha->virt_bus && ha->raw[BUS_L2P(ha, b)].lock) ||
3904 (b == ha->virt_bus && t < MAX_HDRIVES && ha->hdr[t].lock)) {
3905 TRACE2(("%s(): locked IO, reset timeout\n", __func__));
3906 retval = BLK_EH_RESET_TIMER;
3908 spin_unlock_irqrestore(&ha->smp_lock, flags);
3914 static int gdth_eh_bus_reset(Scsi_Cmnd *scp)
3916 gdth_ha_str *ha = shost_priv(scp->device->host);
3918 unsigned long flags;
3922 TRACE2(("gdth_eh_bus_reset()\n"));
3924 b = scp->device->channel;
3926 /* clear command tab */
3927 spin_lock_irqsave(&ha->smp_lock, flags);
3928 for (i = 0; i < GDTH_MAXCMDS; ++i) {
3929 cmnd = ha->cmd_tab[i].cmnd;
3930 if (!SPECIAL_SCP(cmnd) && cmnd->device->channel == b)
3931 ha->cmd_tab[i].cmnd = UNUSED_CMND;
3933 spin_unlock_irqrestore(&ha->smp_lock, flags);
3935 if (b == ha->virt_bus) {
3937 for (i = 0; i < MAX_HDRIVES; ++i) {
3938 if (ha->hdr[i].present) {
3939 spin_lock_irqsave(&ha->smp_lock, flags);
3940 gdth_polling = TRUE;
3941 while (gdth_test_busy(ha))
3943 if (gdth_internal_cmd(ha, CACHESERVICE,
3944 GDT_CLUST_RESET, i, 0, 0))
3945 ha->hdr[i].cluster_type &= ~CLUSTER_RESERVED;
3946 gdth_polling = FALSE;
3947 spin_unlock_irqrestore(&ha->smp_lock, flags);
3952 spin_lock_irqsave(&ha->smp_lock, flags);
3953 for (i = 0; i < MAXID; ++i)
3954 ha->raw[BUS_L2P(ha,b)].io_cnt[i] = 0;
3955 gdth_polling = TRUE;
3956 while (gdth_test_busy(ha))
3958 gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_RESET_BUS,
3959 BUS_L2P(ha,b), 0, 0);
3960 gdth_polling = FALSE;
3961 spin_unlock_irqrestore(&ha->smp_lock, flags);
3966 static int gdth_bios_param(struct scsi_device *sdev,struct block_device *bdev,sector_t cap,int *ip)
3969 gdth_ha_str *ha = shost_priv(sdev->host);
3970 struct scsi_device *sd;
3977 TRACE2(("gdth_bios_param() ha %d bus %d target %d\n", ha->hanum, b, t));
3979 if (b != ha->virt_bus || ha->hdr[t].heads == 0) {
3980 /* raw device or host drive without mapping information */
3981 TRACE2(("Evaluate mapping\n"));
3982 gdth_eval_mapping(capacity,&ip[2],&ip[0],&ip[1]);
3984 ip[0] = ha->hdr[t].heads;
3985 ip[1] = ha->hdr[t].secs;
3986 ip[2] = capacity / ip[0] / ip[1];
3989 TRACE2(("gdth_bios_param(): %d heads, %d secs, %d cyls\n",
3990 ip[0],ip[1],ip[2]));
3995 static int gdth_queuecommand_lck(struct scsi_cmnd *scp,
3996 void (*done)(struct scsi_cmnd *))
3998 gdth_ha_str *ha = shost_priv(scp->device->host);
3999 struct gdth_cmndinfo *cmndinfo;
4001 TRACE(("gdth_queuecommand() cmd 0x%x\n", scp->cmnd[0]));
4003 cmndinfo = gdth_get_cmndinfo(ha);
4006 scp->scsi_done = done;
4007 cmndinfo->timeout_count = 0;
4008 cmndinfo->priority = DEFAULT_PRI;
4010 return __gdth_queuecommand(ha, scp, cmndinfo);
4013 static DEF_SCSI_QCMD(gdth_queuecommand)
4015 static int __gdth_queuecommand(gdth_ha_str *ha, struct scsi_cmnd *scp,
4016 struct gdth_cmndinfo *cmndinfo)
4018 scp->host_scribble = (unsigned char *)cmndinfo;
4019 cmndinfo->wait_for_completion = 1;
4020 cmndinfo->phase = -1;
4021 cmndinfo->OpCode = -1;
4023 #ifdef GDTH_STATISTICS
4027 gdth_putq(ha, scp, cmndinfo->priority);
4033 static int gdth_open(struct inode *inode, struct file *filep)
4037 mutex_lock(&gdth_mutex);
4038 list_for_each_entry(ha, &gdth_instances, list) {
4040 ha->sdev = scsi_get_host_dev(ha->shost);
4042 mutex_unlock(&gdth_mutex);
4044 TRACE(("gdth_open()\n"));
4048 static int gdth_close(struct inode *inode, struct file *filep)
4050 TRACE(("gdth_close()\n"));
4054 static int ioc_event(void __user *arg)
4056 gdth_ioctl_event evt;
4058 unsigned long flags;
4060 if (copy_from_user(&evt, arg, sizeof(gdth_ioctl_event)))
4062 ha = gdth_find_ha(evt.ionode);
4066 if (evt.erase == 0xff) {
4067 if (evt.event.event_source == ES_TEST)
4068 evt.event.event_data.size=sizeof(evt.event.event_data.eu.test);
4069 else if (evt.event.event_source == ES_DRIVER)
4070 evt.event.event_data.size=sizeof(evt.event.event_data.eu.driver);
4071 else if (evt.event.event_source == ES_SYNC)
4072 evt.event.event_data.size=sizeof(evt.event.event_data.eu.sync);
4074 evt.event.event_data.size=sizeof(evt.event.event_data.eu.async);
4075 spin_lock_irqsave(&ha->smp_lock, flags);
4076 gdth_store_event(ha, evt.event.event_source, evt.event.event_idx,
4077 &evt.event.event_data);
4078 spin_unlock_irqrestore(&ha->smp_lock, flags);
4079 } else if (evt.erase == 0xfe) {
4080 gdth_clear_events();
4081 } else if (evt.erase == 0) {
4082 evt.handle = gdth_read_event(ha, evt.handle, &evt.event);
4084 gdth_readapp_event(ha, evt.erase, &evt.event);
4086 if (copy_to_user(arg, &evt, sizeof(gdth_ioctl_event)))
4091 static int ioc_lockdrv(void __user *arg)
4093 gdth_ioctl_lockdrv ldrv;
4095 unsigned long flags;
4098 if (copy_from_user(&ldrv, arg, sizeof(gdth_ioctl_lockdrv)))
4100 ha = gdth_find_ha(ldrv.ionode);
4104 for (i = 0; i < ldrv.drive_cnt && i < MAX_HDRIVES; ++i) {
4106 if (j >= MAX_HDRIVES || !ha->hdr[j].present)
4109 spin_lock_irqsave(&ha->smp_lock, flags);
4110 ha->hdr[j].lock = 1;
4111 spin_unlock_irqrestore(&ha->smp_lock, flags);
4112 gdth_wait_completion(ha, ha->bus_cnt, j);
4114 spin_lock_irqsave(&ha->smp_lock, flags);
4115 ha->hdr[j].lock = 0;
4116 spin_unlock_irqrestore(&ha->smp_lock, flags);
4123 static int ioc_resetdrv(void __user *arg, char *cmnd)
4125 gdth_ioctl_reset res;
4130 if (copy_from_user(&res, arg, sizeof(gdth_ioctl_reset)) ||
4131 res.number >= MAX_HDRIVES)
4133 ha = gdth_find_ha(res.ionode);
4137 if (!ha->hdr[res.number].present)
4139 memset(&cmd, 0, sizeof(gdth_cmd_str));
4140 cmd.Service = CACHESERVICE;
4141 cmd.OpCode = GDT_CLUST_RESET;
4142 if (ha->cache_feat & GDT_64BIT)
4143 cmd.u.cache64.DeviceNo = res.number;
4145 cmd.u.cache.DeviceNo = res.number;
4147 rval = __gdth_execute(ha->sdev, &cmd, cmnd, 30, NULL);
4152 if (copy_to_user(arg, &res, sizeof(gdth_ioctl_reset)))
4157 static int ioc_general(void __user *arg, char *cmnd)
4159 gdth_ioctl_general gen;
4165 if (copy_from_user(&gen, arg, sizeof(gdth_ioctl_general)))
4167 ha = gdth_find_ha(gen.ionode);
4171 if (gen.data_len > INT_MAX)
4173 if (gen.sense_len > INT_MAX)
4175 if (gen.data_len + gen.sense_len > INT_MAX)
4178 if (gen.data_len + gen.sense_len != 0) {
4179 if (!(buf = gdth_ioctl_alloc(ha, gen.data_len + gen.sense_len,
4182 if (copy_from_user(buf, arg + sizeof(gdth_ioctl_general),
4183 gen.data_len + gen.sense_len)) {
4184 gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
4188 if (gen.command.OpCode == GDT_IOCTL) {
4189 gen.command.u.ioctl.p_param = paddr;
4190 } else if (gen.command.Service == CACHESERVICE) {
4191 if (ha->cache_feat & GDT_64BIT) {
4192 /* copy elements from 32-bit IOCTL structure */
4193 gen.command.u.cache64.BlockCnt = gen.command.u.cache.BlockCnt;
4194 gen.command.u.cache64.BlockNo = gen.command.u.cache.BlockNo;
4195 gen.command.u.cache64.DeviceNo = gen.command.u.cache.DeviceNo;
4197 if (ha->cache_feat & SCATTER_GATHER) {
4198 gen.command.u.cache64.DestAddr = (u64)-1;
4199 gen.command.u.cache64.sg_canz = 1;
4200 gen.command.u.cache64.sg_lst[0].sg_ptr = paddr;
4201 gen.command.u.cache64.sg_lst[0].sg_len = gen.data_len;
4202 gen.command.u.cache64.sg_lst[1].sg_len = 0;
4204 gen.command.u.cache64.DestAddr = paddr;
4205 gen.command.u.cache64.sg_canz = 0;
4208 if (ha->cache_feat & SCATTER_GATHER) {
4209 gen.command.u.cache.DestAddr = 0xffffffff;
4210 gen.command.u.cache.sg_canz = 1;
4211 gen.command.u.cache.sg_lst[0].sg_ptr = (u32)paddr;
4212 gen.command.u.cache.sg_lst[0].sg_len = gen.data_len;
4213 gen.command.u.cache.sg_lst[1].sg_len = 0;
4215 gen.command.u.cache.DestAddr = paddr;
4216 gen.command.u.cache.sg_canz = 0;
4219 } else if (gen.command.Service == SCSIRAWSERVICE) {
4220 if (ha->raw_feat & GDT_64BIT) {
4221 /* copy elements from 32-bit IOCTL structure */
4223 gen.command.u.raw64.sense_len = gen.command.u.raw.sense_len;
4224 gen.command.u.raw64.bus = gen.command.u.raw.bus;
4225 gen.command.u.raw64.lun = gen.command.u.raw.lun;
4226 gen.command.u.raw64.target = gen.command.u.raw.target;
4227 memcpy(cmd, gen.command.u.raw.cmd, 16);
4228 memcpy(gen.command.u.raw64.cmd, cmd, 16);
4229 gen.command.u.raw64.clen = gen.command.u.raw.clen;
4230 gen.command.u.raw64.sdlen = gen.command.u.raw.sdlen;
4231 gen.command.u.raw64.direction = gen.command.u.raw.direction;
4233 if (ha->raw_feat & SCATTER_GATHER) {
4234 gen.command.u.raw64.sdata = (u64)-1;
4235 gen.command.u.raw64.sg_ranz = 1;
4236 gen.command.u.raw64.sg_lst[0].sg_ptr = paddr;
4237 gen.command.u.raw64.sg_lst[0].sg_len = gen.data_len;
4238 gen.command.u.raw64.sg_lst[1].sg_len = 0;
4240 gen.command.u.raw64.sdata = paddr;
4241 gen.command.u.raw64.sg_ranz = 0;
4243 gen.command.u.raw64.sense_data = paddr + gen.data_len;
4245 if (ha->raw_feat & SCATTER_GATHER) {
4246 gen.command.u.raw.sdata = 0xffffffff;
4247 gen.command.u.raw.sg_ranz = 1;
4248 gen.command.u.raw.sg_lst[0].sg_ptr = (u32)paddr;
4249 gen.command.u.raw.sg_lst[0].sg_len = gen.data_len;
4250 gen.command.u.raw.sg_lst[1].sg_len = 0;
4252 gen.command.u.raw.sdata = paddr;
4253 gen.command.u.raw.sg_ranz = 0;
4255 gen.command.u.raw.sense_data = (u32)paddr + gen.data_len;
4258 gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
4263 rval = __gdth_execute(ha->sdev, &gen.command, cmnd, gen.timeout, &gen.info);
4265 gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
4270 if (copy_to_user(arg + sizeof(gdth_ioctl_general), buf,
4271 gen.data_len + gen.sense_len)) {
4272 gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
4275 if (copy_to_user(arg, &gen,
4276 sizeof(gdth_ioctl_general) - sizeof(gdth_cmd_str))) {
4277 gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
4280 gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
4284 static int ioc_hdrlist(void __user *arg, char *cmnd)
4286 gdth_ioctl_rescan *rsc;
4291 u32 cluster_type = 0;
4293 rsc = kmalloc(sizeof(*rsc), GFP_KERNEL);
4294 cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
4298 if (copy_from_user(rsc, arg, sizeof(gdth_ioctl_rescan)) ||
4299 (NULL == (ha = gdth_find_ha(rsc->ionode)))) {
4303 memset(cmd, 0, sizeof(gdth_cmd_str));
4305 for (i = 0; i < MAX_HDRIVES; ++i) {
4306 if (!ha->hdr[i].present) {
4307 rsc->hdr_list[i].bus = 0xff;
4310 rsc->hdr_list[i].bus = ha->virt_bus;
4311 rsc->hdr_list[i].target = i;
4312 rsc->hdr_list[i].lun = 0;
4313 rsc->hdr_list[i].cluster_type = ha->hdr[i].cluster_type;
4314 if (ha->hdr[i].cluster_type & CLUSTER_DRIVE) {
4315 cmd->Service = CACHESERVICE;
4316 cmd->OpCode = GDT_CLUST_INFO;
4317 if (ha->cache_feat & GDT_64BIT)
4318 cmd->u.cache64.DeviceNo = i;
4320 cmd->u.cache.DeviceNo = i;
4321 if (__gdth_execute(ha->sdev, cmd, cmnd, 30, &cluster_type) == S_OK)
4322 rsc->hdr_list[i].cluster_type = cluster_type;
4326 if (copy_to_user(arg, rsc, sizeof(gdth_ioctl_rescan)))
4337 static int ioc_rescan(void __user *arg, char *cmnd)
4339 gdth_ioctl_rescan *rsc;
4341 u16 i, status, hdr_cnt;
4343 int cyls, hds, secs;
4345 unsigned long flags;
4348 rsc = kmalloc(sizeof(*rsc), GFP_KERNEL);
4349 cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
4353 if (copy_from_user(rsc, arg, sizeof(gdth_ioctl_rescan)) ||
4354 (NULL == (ha = gdth_find_ha(rsc->ionode)))) {
4358 memset(cmd, 0, sizeof(gdth_cmd_str));
4360 if (rsc->flag == 0) {
4361 /* old method: re-init. cache service */
4362 cmd->Service = CACHESERVICE;
4363 if (ha->cache_feat & GDT_64BIT) {
4364 cmd->OpCode = GDT_X_INIT_HOST;
4365 cmd->u.cache64.DeviceNo = LINUX_OS;
4367 cmd->OpCode = GDT_INIT;
4368 cmd->u.cache.DeviceNo = LINUX_OS;
4371 status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
4373 hdr_cnt = (status == S_OK ? (u16)info : 0);
4379 for (; i < hdr_cnt && i < MAX_HDRIVES; ++i) {
4380 cmd->Service = CACHESERVICE;
4381 cmd->OpCode = GDT_INFO;
4382 if (ha->cache_feat & GDT_64BIT)
4383 cmd->u.cache64.DeviceNo = i;
4385 cmd->u.cache.DeviceNo = i;
4387 status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
4389 spin_lock_irqsave(&ha->smp_lock, flags);
4390 rsc->hdr_list[i].bus = ha->virt_bus;
4391 rsc->hdr_list[i].target = i;
4392 rsc->hdr_list[i].lun = 0;
4393 if (status != S_OK) {
4394 ha->hdr[i].present = FALSE;
4396 ha->hdr[i].present = TRUE;
4397 ha->hdr[i].size = info;
4398 /* evaluate mapping */
4399 ha->hdr[i].size &= ~SECS32;
4400 gdth_eval_mapping(ha->hdr[i].size,&cyls,&hds,&secs);
4401 ha->hdr[i].heads = hds;
4402 ha->hdr[i].secs = secs;
4404 ha->hdr[i].size = cyls * hds * secs;
4406 spin_unlock_irqrestore(&ha->smp_lock, flags);
4410 /* extended info, if GDT_64BIT, for drives > 2 TB */
4411 /* but we need ha->info2, not yet stored in scp->SCp */
4413 /* devtype, cluster info, R/W attribs */
4414 cmd->Service = CACHESERVICE;
4415 cmd->OpCode = GDT_DEVTYPE;
4416 if (ha->cache_feat & GDT_64BIT)
4417 cmd->u.cache64.DeviceNo = i;
4419 cmd->u.cache.DeviceNo = i;
4421 status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
4423 spin_lock_irqsave(&ha->smp_lock, flags);
4424 ha->hdr[i].devtype = (status == S_OK ? (u16)info : 0);
4425 spin_unlock_irqrestore(&ha->smp_lock, flags);
4427 cmd->Service = CACHESERVICE;
4428 cmd->OpCode = GDT_CLUST_INFO;
4429 if (ha->cache_feat & GDT_64BIT)
4430 cmd->u.cache64.DeviceNo = i;
4432 cmd->u.cache.DeviceNo = i;
4434 status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
4436 spin_lock_irqsave(&ha->smp_lock, flags);
4437 ha->hdr[i].cluster_type =
4438 ((status == S_OK && !shared_access) ? (u16)info : 0);
4439 spin_unlock_irqrestore(&ha->smp_lock, flags);
4440 rsc->hdr_list[i].cluster_type = ha->hdr[i].cluster_type;
4442 cmd->Service = CACHESERVICE;
4443 cmd->OpCode = GDT_RW_ATTRIBS;
4444 if (ha->cache_feat & GDT_64BIT)
4445 cmd->u.cache64.DeviceNo = i;
4447 cmd->u.cache.DeviceNo = i;
4449 status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
4451 spin_lock_irqsave(&ha->smp_lock, flags);
4452 ha->hdr[i].rw_attribs = (status == S_OK ? (u16)info : 0);
4453 spin_unlock_irqrestore(&ha->smp_lock, flags);
4456 if (copy_to_user(arg, rsc, sizeof(gdth_ioctl_rescan)))
4467 static int gdth_ioctl(struct file *filep, unsigned int cmd, unsigned long arg)
4471 unsigned long flags;
4472 char cmnd[MAX_COMMAND_SIZE];
4473 void __user *argp = (void __user *)arg;
4475 memset(cmnd, 0xff, 12);
4477 TRACE(("gdth_ioctl() cmd 0x%x\n", cmd));
4480 case GDTIOCTL_CTRCNT:
4482 int cnt = gdth_ctr_count;
4483 if (put_user(cnt, (int __user *)argp))
4488 case GDTIOCTL_DRVERS:
4490 int ver = (GDTH_VERSION<<8) | GDTH_SUBVERSION;
4491 if (put_user(ver, (int __user *)argp))
4496 case GDTIOCTL_OSVERS:
4498 gdth_ioctl_osvers osv;
4500 osv.version = (u8)(LINUX_VERSION_CODE >> 16);
4501 osv.subversion = (u8)(LINUX_VERSION_CODE >> 8);
4502 osv.revision = (u16)(LINUX_VERSION_CODE & 0xff);
4503 if (copy_to_user(argp, &osv, sizeof(gdth_ioctl_osvers)))
4508 case GDTIOCTL_CTRTYPE:
4510 gdth_ioctl_ctrtype ctrt;
4512 if (copy_from_user(&ctrt, argp, sizeof(gdth_ioctl_ctrtype)) ||
4513 (NULL == (ha = gdth_find_ha(ctrt.ionode))))
4516 if (ha->type == GDT_ISA || ha->type == GDT_EISA) {
4517 ctrt.type = (u8)((ha->stype>>20) - 0x10);
4519 if (ha->type != GDT_PCIMPR) {
4520 ctrt.type = (u8)((ha->stype<<4) + 6);
4523 (ha->oem_id == OEM_ID_INTEL ? 0xfd : 0xfe);
4524 if (ha->stype >= 0x300)
4525 ctrt.ext_type = 0x6000 | ha->pdev->subsystem_device;
4527 ctrt.ext_type = 0x6000 | ha->stype;
4529 ctrt.device_id = ha->pdev->device;
4530 ctrt.sub_device_id = ha->pdev->subsystem_device;
4532 ctrt.info = ha->brd_phys;
4533 ctrt.oem_id = ha->oem_id;
4534 if (copy_to_user(argp, &ctrt, sizeof(gdth_ioctl_ctrtype)))
4539 case GDTIOCTL_GENERAL:
4540 return ioc_general(argp, cmnd);
4542 case GDTIOCTL_EVENT:
4543 return ioc_event(argp);
4545 case GDTIOCTL_LOCKDRV:
4546 return ioc_lockdrv(argp);
4548 case GDTIOCTL_LOCKCHN:
4550 gdth_ioctl_lockchn lchn;
4553 if (copy_from_user(&lchn, argp, sizeof(gdth_ioctl_lockchn)) ||
4554 (NULL == (ha = gdth_find_ha(lchn.ionode))))
4558 if (i < ha->bus_cnt) {
4560 spin_lock_irqsave(&ha->smp_lock, flags);
4561 ha->raw[i].lock = 1;
4562 spin_unlock_irqrestore(&ha->smp_lock, flags);
4563 for (j = 0; j < ha->tid_cnt; ++j)
4564 gdth_wait_completion(ha, i, j);
4566 spin_lock_irqsave(&ha->smp_lock, flags);
4567 ha->raw[i].lock = 0;
4568 spin_unlock_irqrestore(&ha->smp_lock, flags);
4569 for (j = 0; j < ha->tid_cnt; ++j)
4576 case GDTIOCTL_RESCAN:
4577 return ioc_rescan(argp, cmnd);
4579 case GDTIOCTL_HDRLIST:
4580 return ioc_hdrlist(argp, cmnd);
4582 case GDTIOCTL_RESET_BUS:
4584 gdth_ioctl_reset res;
4587 if (copy_from_user(&res, argp, sizeof(gdth_ioctl_reset)) ||
4588 (NULL == (ha = gdth_find_ha(res.ionode))))
4591 scp = kzalloc(sizeof(*scp), GFP_KERNEL);
4594 scp->device = ha->sdev;
4596 scp->device->channel = res.number;
4597 rval = gdth_eh_bus_reset(scp);
4598 res.status = (rval == SUCCESS ? S_OK : S_GENERR);
4601 if (copy_to_user(argp, &res, sizeof(gdth_ioctl_reset)))
4606 case GDTIOCTL_RESET_DRV:
4607 return ioc_resetdrv(argp, cmnd);
4615 static long gdth_unlocked_ioctl(struct file *file, unsigned int cmd,
4620 mutex_lock(&gdth_mutex);
4621 ret = gdth_ioctl(file, cmd, arg);
4622 mutex_unlock(&gdth_mutex);
4628 static void gdth_flush(gdth_ha_str *ha)
4631 gdth_cmd_str gdtcmd;
4632 char cmnd[MAX_COMMAND_SIZE];
4633 memset(cmnd, 0xff, MAX_COMMAND_SIZE);
4635 TRACE2(("gdth_flush() hanum %d\n", ha->hanum));
4637 for (i = 0; i < MAX_HDRIVES; ++i) {
4638 if (ha->hdr[i].present) {
4639 gdtcmd.BoardNode = LOCALBOARD;
4640 gdtcmd.Service = CACHESERVICE;
4641 gdtcmd.OpCode = GDT_FLUSH;
4642 if (ha->cache_feat & GDT_64BIT) {
4643 gdtcmd.u.cache64.DeviceNo = i;
4644 gdtcmd.u.cache64.BlockNo = 1;
4645 gdtcmd.u.cache64.sg_canz = 0;
4647 gdtcmd.u.cache.DeviceNo = i;
4648 gdtcmd.u.cache.BlockNo = 1;
4649 gdtcmd.u.cache.sg_canz = 0;
4651 TRACE2(("gdth_flush(): flush ha %d drive %d\n", ha->hanum, i));
4653 gdth_execute(ha->shost, &gdtcmd, cmnd, 30, NULL);
4659 static int gdth_slave_configure(struct scsi_device *sdev)
4661 sdev->skip_ms_page_3f = 1;
4662 sdev->skip_ms_page_8 = 1;
4666 static struct scsi_host_template gdth_template = {
4667 .name = "GDT SCSI Disk Array Controller",
4669 .queuecommand = gdth_queuecommand,
4670 .eh_bus_reset_handler = gdth_eh_bus_reset,
4671 .slave_configure = gdth_slave_configure,
4672 .bios_param = gdth_bios_param,
4673 .show_info = gdth_show_info,
4674 .write_info = gdth_set_info,
4675 .eh_timed_out = gdth_timed_out,
4676 .proc_name = "gdth",
4677 .can_queue = GDTH_MAXCMDS,
4679 .sg_tablesize = GDTH_MAXSG,
4680 .cmd_per_lun = GDTH_MAXC_P_L,
4681 .unchecked_isa_dma = 1,
4682 .use_clustering = ENABLE_CLUSTERING,
4687 static int __init gdth_isa_probe_one(u32 isa_bios)
4689 struct Scsi_Host *shp;
4691 dma_addr_t scratch_dma_handle = 0;
4694 if (!gdth_search_isa(isa_bios))
4697 shp = scsi_host_alloc(&gdth_template, sizeof(gdth_ha_str));
4700 ha = shost_priv(shp);
4703 if (!gdth_init_isa(isa_bios,ha))
4706 /* controller found and initialized */
4707 printk("Configuring GDT-ISA HA at BIOS 0x%05X IRQ %u DRQ %u\n",
4708 isa_bios, ha->irq, ha->drq);
4710 error = request_irq(ha->irq, gdth_interrupt, 0, "gdth", ha);
4712 printk("GDT-ISA: Unable to allocate IRQ\n");
4716 error = request_dma(ha->drq, "gdth");
4718 printk("GDT-ISA: Unable to allocate DMA channel\n");
4722 set_dma_mode(ha->drq,DMA_MODE_CASCADE);
4723 enable_dma(ha->drq);
4724 shp->unchecked_isa_dma = 1;
4726 shp->dma_channel = ha->drq;
4728 ha->hanum = gdth_ctr_count++;
4731 ha->pccb = &ha->cmdext;
4737 ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
4738 &scratch_dma_handle);
4740 goto out_dec_counters;
4741 ha->scratch_phys = scratch_dma_handle;
4743 ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
4744 &scratch_dma_handle);
4746 goto out_free_pscratch;
4747 ha->msg_phys = scratch_dma_handle;
4750 ha->coal_stat = pci_alloc_consistent(ha->pdev,
4751 sizeof(gdth_coal_status) * MAXOFFSETS,
4752 &scratch_dma_handle);
4755 ha->coal_stat_phys = scratch_dma_handle;
4758 ha->scratch_busy = FALSE;
4759 ha->req_first = NULL;
4760 ha->tid_cnt = MAX_HDRIVES;
4761 if (max_ids > 0 && max_ids < ha->tid_cnt)
4762 ha->tid_cnt = max_ids;
4763 for (i = 0; i < GDTH_MAXCMDS; ++i)
4764 ha->cmd_tab[i].cmnd = UNUSED_CMND;
4765 ha->scan_mode = rescan ? 0x10 : 0;
4768 if (!gdth_search_drives(ha)) {
4769 printk("GDT-ISA: Error during device scan\n");
4770 goto out_free_coal_stat;
4773 if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
4774 hdr_channel = ha->bus_cnt;
4775 ha->virt_bus = hdr_channel;
4777 if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
4778 shp->max_cmd_len = 16;
4780 shp->max_id = ha->tid_cnt;
4781 shp->max_lun = MAXLUN;
4782 shp->max_channel = ha->bus_cnt;
4784 spin_lock_init(&ha->smp_lock);
4785 gdth_enable_int(ha);
4787 error = scsi_add_host(shp, NULL);
4789 goto out_free_coal_stat;
4790 list_add_tail(&ha->list, &gdth_instances);
4793 scsi_scan_host(shp);
4799 pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
4800 ha->coal_stat, ha->coal_stat_phys);
4803 pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
4804 ha->pmsg, ha->msg_phys);
4806 pci_free_consistent(ha->pdev, GDTH_SCRATCH,
4807 ha->pscratch, ha->scratch_phys);
4811 free_irq(ha->irq, ha);
4816 #endif /* CONFIG_ISA */
4819 static int __init gdth_eisa_probe_one(u16 eisa_slot)
4821 struct Scsi_Host *shp;
4823 dma_addr_t scratch_dma_handle = 0;
4826 if (!gdth_search_eisa(eisa_slot))
4829 shp = scsi_host_alloc(&gdth_template, sizeof(gdth_ha_str));
4832 ha = shost_priv(shp);
4835 if (!gdth_init_eisa(eisa_slot,ha))
4838 /* controller found and initialized */
4839 printk("Configuring GDT-EISA HA at Slot %d IRQ %u\n",
4840 eisa_slot >> 12, ha->irq);
4842 error = request_irq(ha->irq, gdth_interrupt, 0, "gdth", ha);
4844 printk("GDT-EISA: Unable to allocate IRQ\n");
4848 shp->unchecked_isa_dma = 0;
4850 shp->dma_channel = 0xff;
4852 ha->hanum = gdth_ctr_count++;
4855 TRACE2(("EISA detect Bus 0: hanum %d\n", ha->hanum));
4857 ha->pccb = &ha->cmdext;
4863 ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
4864 &scratch_dma_handle);
4867 ha->scratch_phys = scratch_dma_handle;
4869 ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
4870 &scratch_dma_handle);
4872 goto out_free_pscratch;
4873 ha->msg_phys = scratch_dma_handle;
4876 ha->coal_stat = pci_alloc_consistent(ha->pdev,
4877 sizeof(gdth_coal_status) * MAXOFFSETS,
4878 &scratch_dma_handle);
4881 ha->coal_stat_phys = scratch_dma_handle;
4884 ha->ccb_phys = pci_map_single(ha->pdev,ha->pccb,
4885 sizeof(gdth_cmd_str), PCI_DMA_BIDIRECTIONAL);
4887 goto out_free_coal_stat;
4889 ha->scratch_busy = FALSE;
4890 ha->req_first = NULL;
4891 ha->tid_cnt = MAX_HDRIVES;
4892 if (max_ids > 0 && max_ids < ha->tid_cnt)
4893 ha->tid_cnt = max_ids;
4894 for (i = 0; i < GDTH_MAXCMDS; ++i)
4895 ha->cmd_tab[i].cmnd = UNUSED_CMND;
4896 ha->scan_mode = rescan ? 0x10 : 0;
4898 if (!gdth_search_drives(ha)) {
4899 printk("GDT-EISA: Error during device scan\n");
4901 goto out_free_ccb_phys;
4904 if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
4905 hdr_channel = ha->bus_cnt;
4906 ha->virt_bus = hdr_channel;
4908 if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
4909 shp->max_cmd_len = 16;
4911 shp->max_id = ha->tid_cnt;
4912 shp->max_lun = MAXLUN;
4913 shp->max_channel = ha->bus_cnt;
4915 spin_lock_init(&ha->smp_lock);
4916 gdth_enable_int(ha);
4918 error = scsi_add_host(shp, NULL);
4920 goto out_free_ccb_phys;
4921 list_add_tail(&ha->list, &gdth_instances);
4924 scsi_scan_host(shp);
4929 pci_unmap_single(ha->pdev,ha->ccb_phys, sizeof(gdth_cmd_str),
4930 PCI_DMA_BIDIRECTIONAL);
4933 pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
4934 ha->coal_stat, ha->coal_stat_phys);
4937 pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
4938 ha->pmsg, ha->msg_phys);
4940 pci_free_consistent(ha->pdev, GDTH_SCRATCH,
4941 ha->pscratch, ha->scratch_phys);
4943 free_irq(ha->irq, ha);
4949 #endif /* CONFIG_EISA */
4952 static int gdth_pci_probe_one(gdth_pci_str *pcistr, gdth_ha_str **ha_out)
4954 struct Scsi_Host *shp;
4956 dma_addr_t scratch_dma_handle = 0;
4958 struct pci_dev *pdev = pcistr->pdev;
4962 shp = scsi_host_alloc(&gdth_template, sizeof(gdth_ha_str));
4965 ha = shost_priv(shp);
4968 if (!gdth_init_pci(pdev, pcistr, ha))
4971 /* controller found and initialized */
4972 printk("Configuring GDT-PCI HA at %d/%d IRQ %u\n",
4974 PCI_SLOT(pdev->devfn),
4977 error = request_irq(ha->irq, gdth_interrupt,
4978 IRQF_SHARED, "gdth", ha);
4980 printk("GDT-PCI: Unable to allocate IRQ\n");
4984 shp->unchecked_isa_dma = 0;
4986 shp->dma_channel = 0xff;
4988 ha->hanum = gdth_ctr_count++;
4991 ha->pccb = &ha->cmdext;
4996 ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
4997 &scratch_dma_handle);
5000 ha->scratch_phys = scratch_dma_handle;
5002 ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
5003 &scratch_dma_handle);
5005 goto out_free_pscratch;
5006 ha->msg_phys = scratch_dma_handle;
5009 ha->coal_stat = pci_alloc_consistent(ha->pdev,
5010 sizeof(gdth_coal_status) * MAXOFFSETS,
5011 &scratch_dma_handle);
5014 ha->coal_stat_phys = scratch_dma_handle;
5017 ha->scratch_busy = FALSE;
5018 ha->req_first = NULL;
5019 ha->tid_cnt = pdev->device >= 0x200 ? MAXID : MAX_HDRIVES;
5020 if (max_ids > 0 && max_ids < ha->tid_cnt)
5021 ha->tid_cnt = max_ids;
5022 for (i = 0; i < GDTH_MAXCMDS; ++i)
5023 ha->cmd_tab[i].cmnd = UNUSED_CMND;
5024 ha->scan_mode = rescan ? 0x10 : 0;
5027 if (!gdth_search_drives(ha)) {
5028 printk("GDT-PCI %d: Error during device scan\n", ha->hanum);
5029 goto out_free_coal_stat;
5032 if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
5033 hdr_channel = ha->bus_cnt;
5034 ha->virt_bus = hdr_channel;
5036 /* 64-bit DMA only supported from FW >= x.43 */
5037 if (!(ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT) ||
5038 !ha->dma64_support) {
5039 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
5040 printk(KERN_WARNING "GDT-PCI %d: "
5041 "Unable to set 32-bit DMA\n", ha->hanum);
5042 goto out_free_coal_stat;
5045 shp->max_cmd_len = 16;
5046 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
5047 printk("GDT-PCI %d: 64-bit DMA enabled\n", ha->hanum);
5048 } else if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
5049 printk(KERN_WARNING "GDT-PCI %d: "
5050 "Unable to set 64/32-bit DMA\n", ha->hanum);
5051 goto out_free_coal_stat;
5055 shp->max_id = ha->tid_cnt;
5056 shp->max_lun = MAXLUN;
5057 shp->max_channel = ha->bus_cnt;
5059 spin_lock_init(&ha->smp_lock);
5060 gdth_enable_int(ha);
5062 error = scsi_add_host(shp, &pdev->dev);
5064 goto out_free_coal_stat;
5065 list_add_tail(&ha->list, &gdth_instances);
5067 pci_set_drvdata(ha->pdev, ha);
5070 scsi_scan_host(shp);
5078 pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
5079 ha->coal_stat, ha->coal_stat_phys);
5082 pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
5083 ha->pmsg, ha->msg_phys);
5085 pci_free_consistent(ha->pdev, GDTH_SCRATCH,
5086 ha->pscratch, ha->scratch_phys);
5088 free_irq(ha->irq, ha);
5094 #endif /* CONFIG_PCI */
5096 static void gdth_remove_one(gdth_ha_str *ha)
5098 struct Scsi_Host *shp = ha->shost;
5100 TRACE2(("gdth_remove_one()\n"));
5102 scsi_remove_host(shp);
5107 scsi_free_host_dev(ha->sdev);
5112 free_irq(shp->irq,ha);
5115 if (shp->dma_channel != 0xff)
5116 free_dma(shp->dma_channel);
5120 pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) *
5121 MAXOFFSETS, ha->coal_stat, ha->coal_stat_phys);
5124 pci_free_consistent(ha->pdev, GDTH_SCRATCH,
5125 ha->pscratch, ha->scratch_phys);
5127 pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
5128 ha->pmsg, ha->msg_phys);
5130 pci_unmap_single(ha->pdev,ha->ccb_phys,
5131 sizeof(gdth_cmd_str),PCI_DMA_BIDIRECTIONAL);
5136 static int gdth_halt(struct notifier_block *nb, unsigned long event, void *buf)
5140 TRACE2(("gdth_halt() event %d\n", (int)event));
5141 if (event != SYS_RESTART && event != SYS_HALT && event != SYS_POWER_OFF)
5144 list_for_each_entry(ha, &gdth_instances, list)
5150 static struct notifier_block gdth_notifier = {
5154 static int __init gdth_init(void)
5157 printk("GDT-HA: Controller driver disabled from"
5158 " command line !\n");
5162 printk("GDT-HA: Storage RAID Controller Driver. Version: %s\n",
5165 /* initializations */
5166 gdth_polling = TRUE;
5167 gdth_clear_events();
5168 init_timer(&gdth_timer);
5170 /* As default we do not probe for EISA or ISA controllers */
5171 if (probe_eisa_isa) {
5172 /* scanning for controllers, at first: ISA controller */
5175 for (isa_bios = 0xc8000UL; isa_bios <= 0xd8000UL;
5176 isa_bios += 0x8000UL)
5177 gdth_isa_probe_one(isa_bios);
5182 for (eisa_slot = 0x1000; eisa_slot <= 0x8000;
5183 eisa_slot += 0x1000)
5184 gdth_eisa_probe_one(eisa_slot);
5190 /* scanning for PCI controllers */
5191 if (pci_register_driver(&gdth_pci_driver)) {
5194 list_for_each_entry(ha, &gdth_instances, list)
5195 gdth_remove_one(ha);
5198 #endif /* CONFIG_PCI */
5200 TRACE2(("gdth_detect() %d controller detected\n", gdth_ctr_count));
5202 major = register_chrdev(0,"gdth", &gdth_fops);
5203 register_reboot_notifier(&gdth_notifier);
5204 gdth_polling = FALSE;
5208 static void __exit gdth_exit(void)
5212 unregister_chrdev(major, "gdth");
5213 unregister_reboot_notifier(&gdth_notifier);
5215 #ifdef GDTH_STATISTICS
5216 del_timer_sync(&gdth_timer);
5220 pci_unregister_driver(&gdth_pci_driver);
5223 list_for_each_entry(ha, &gdth_instances, list)
5224 gdth_remove_one(ha);
5227 module_init(gdth_init);
5228 module_exit(gdth_exit);
5231 __setup("gdth=", option_setup);