2 * Disk Array driver for HP Smart Array SAS controllers
3 * Copyright 2000, 2009 Hewlett-Packard Development Company, L.P.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
12 * NON INFRINGEMENT. See the GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 * Questions/Comments/Bugfixes to iss_storagedev@hp.com
24 #include <scsi/scsicam.h>
31 struct access_method {
32 void (*submit_command)(struct ctlr_info *h,
33 struct CommandList *c);
34 void (*set_intr_mask)(struct ctlr_info *h, unsigned long val);
35 unsigned long (*fifo_full)(struct ctlr_info *h);
36 bool (*intr_pending)(struct ctlr_info *h);
37 unsigned long (*command_completed)(struct ctlr_info *h);
40 struct hpsa_scsi_dev_t {
42 int bus, target, lun; /* as presented to the OS */
43 unsigned char scsi3addr[8]; /* as presented to the HW */
44 #define RAID_CTLR_LUNID "\0\0\0\0\0\0\0\0"
45 unsigned char device_id[16]; /* from inquiry pg. 0x83 */
46 unsigned char vendor[8]; /* bytes 8-15 of inquiry data */
47 unsigned char model[16]; /* bytes 16-31 of inquiry data */
48 unsigned char raid_level; /* from inquiry page 0xC1 */
59 int nr_cmds; /* Number of commands allowed on this controller */
60 struct CfgTable __iomem *cfgtable;
62 int interrupts_enabled;
65 int commands_outstanding;
66 int max_outstanding; /* Debug */
67 int usage_count; /* number of opens all all minor devices */
68 # define PERF_MODE_INT 0
69 # define DOORBELL_INT 1
70 # define SIMPLE_MODE_INT 2
71 # define MEMQ_MODE_INT 3
73 unsigned int msix_vector;
74 unsigned int msi_vector;
75 struct access_method access;
77 /* queue and queue Info */
78 struct list_head reqQ;
79 struct list_head cmpQ;
81 unsigned int maxQsinceinit;
85 u8 max_cmd_sg_entries;
87 struct SGDescriptor **cmd_sg_list;
89 /* pointers to command and error info pool */
90 struct CommandList *cmd_pool;
91 dma_addr_t cmd_pool_dhandle;
92 struct ErrorInfo *errinfo_pool;
93 dma_addr_t errinfo_pool_dhandle;
94 unsigned long *cmd_pool_bits;
97 int busy_initializing;
100 spinlock_t scan_lock;
101 wait_queue_head_t scan_wait_queue;
103 struct Scsi_Host *scsi_host;
104 spinlock_t devlock; /* to protect hba[ctlr]->dev[]; */
105 int ndevices; /* number of used elements in .dev[] array. */
106 #define HPSA_MAX_SCSI_DEVS_PER_HBA 256
107 struct hpsa_scsi_dev_t *dev[HPSA_MAX_SCSI_DEVS_PER_HBA];
109 * Performant mode tables.
113 struct TransTable_struct *transtable;
114 unsigned long transMethod;
117 * Performant mode completion buffer
120 dma_addr_t reply_pool_dhandle;
121 u64 *reply_pool_head;
122 size_t reply_pool_size;
123 unsigned char reply_pool_wraparound;
124 u32 *blockFetchTable;
125 unsigned char *hba_inquiry_data;
127 #define HPSA_ABORT_MSG 0
128 #define HPSA_DEVICE_RESET_MSG 1
129 #define HPSA_BUS_RESET_MSG 2
130 #define HPSA_HOST_RESET_MSG 3
131 #define HPSA_MSG_SEND_RETRY_LIMIT 10
132 #define HPSA_MSG_SEND_RETRY_INTERVAL_MSECS 1000
134 /* Maximum time in seconds driver will wait for command completions
135 * when polling before giving up.
137 #define HPSA_MAX_POLL_TIME_SECS (20)
139 /* During SCSI error recovery, HPSA_TUR_RETRY_LIMIT defines
140 * how many times to retry TEST UNIT READY on a device
141 * while waiting for it to become ready before giving up.
142 * HPSA_MAX_WAIT_INTERVAL_SECS is the max wait interval
143 * between sending TURs while waiting for a device
146 #define HPSA_TUR_RETRY_LIMIT (20)
147 #define HPSA_MAX_WAIT_INTERVAL_SECS (30)
149 /* HPSA_BOARD_READY_WAIT_SECS is how long to wait for a board
150 * to become ready, in seconds, before giving up on it.
151 * HPSA_BOARD_READY_POLL_INTERVAL_MSECS * is how long to wait
152 * between polling the board to see if it is ready, in
153 * milliseconds. HPSA_BOARD_READY_POLL_INTERVAL and
154 * HPSA_BOARD_READY_ITERATIONS are derived from those.
156 #define HPSA_BOARD_READY_WAIT_SECS (120)
157 #define HPSA_BOARD_NOT_READY_WAIT_SECS (10)
158 #define HPSA_BOARD_READY_POLL_INTERVAL_MSECS (100)
159 #define HPSA_BOARD_READY_POLL_INTERVAL \
160 ((HPSA_BOARD_READY_POLL_INTERVAL_MSECS * HZ) / 1000)
161 #define HPSA_BOARD_READY_ITERATIONS \
162 ((HPSA_BOARD_READY_WAIT_SECS * 1000) / \
163 HPSA_BOARD_READY_POLL_INTERVAL_MSECS)
164 #define HPSA_BOARD_NOT_READY_ITERATIONS \
165 ((HPSA_BOARD_NOT_READY_WAIT_SECS * 1000) / \
166 HPSA_BOARD_READY_POLL_INTERVAL_MSECS)
167 #define HPSA_POST_RESET_PAUSE_MSECS (3000)
168 #define HPSA_POST_RESET_NOOP_RETRIES (12)
170 /* Defining the diffent access_menthods */
172 * Memory mapped FIFO interface (SMART 53xx cards)
174 #define SA5_DOORBELL 0x20
175 #define SA5_REQUEST_PORT_OFFSET 0x40
176 #define SA5_REPLY_INTR_MASK_OFFSET 0x34
177 #define SA5_REPLY_PORT_OFFSET 0x44
178 #define SA5_INTR_STATUS 0x30
179 #define SA5_SCRATCHPAD_OFFSET 0xB0
181 #define SA5_CTCFG_OFFSET 0xB4
182 #define SA5_CTMEM_OFFSET 0xB8
184 #define SA5_INTR_OFF 0x08
185 #define SA5B_INTR_OFF 0x04
186 #define SA5_INTR_PENDING 0x08
187 #define SA5B_INTR_PENDING 0x04
188 #define FIFO_EMPTY 0xffffffff
189 #define HPSA_FIRMWARE_READY 0xffff0000 /* value in scratchpad register */
191 #define HPSA_ERROR_BIT 0x02
193 /* Performant mode flags */
194 #define SA5_PERF_INTR_PENDING 0x04
195 #define SA5_PERF_INTR_OFF 0x05
196 #define SA5_OUTDB_STATUS_PERF_BIT 0x01
197 #define SA5_OUTDB_CLEAR_PERF_BIT 0x01
198 #define SA5_OUTDB_CLEAR 0xA0
199 #define SA5_OUTDB_CLEAR_PERF_BIT 0x01
200 #define SA5_OUTDB_STATUS 0x9C
203 #define HPSA_INTR_ON 1
204 #define HPSA_INTR_OFF 0
206 Send the command to the hardware
208 static void SA5_submit_command(struct ctlr_info *h,
209 struct CommandList *c)
211 dev_dbg(&h->pdev->dev, "Sending %x, tag = %x\n", c->busaddr,
212 c->Header.Tag.lower);
213 writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
214 h->commands_outstanding++;
215 if (h->commands_outstanding > h->max_outstanding)
216 h->max_outstanding = h->commands_outstanding;
220 * This card is the opposite of the other cards.
221 * 0 turns interrupts on...
222 * 0x08 turns them off...
224 static void SA5_intr_mask(struct ctlr_info *h, unsigned long val)
226 if (val) { /* Turn interrupts on */
227 h->interrupts_enabled = 1;
228 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
229 } else { /* Turn them off */
230 h->interrupts_enabled = 0;
232 h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
236 static void SA5_performant_intr_mask(struct ctlr_info *h, unsigned long val)
238 if (val) { /* turn on interrupts */
239 h->interrupts_enabled = 1;
240 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
242 h->interrupts_enabled = 0;
243 writel(SA5_PERF_INTR_OFF,
244 h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
248 static unsigned long SA5_performant_completed(struct ctlr_info *h)
250 unsigned long register_value = FIFO_EMPTY;
252 /* flush the controller write of the reply queue by reading
253 * outbound doorbell status register.
255 register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
256 /* msi auto clears the interrupt pending bit. */
257 if (!(h->msi_vector || h->msix_vector)) {
258 writel(SA5_OUTDB_CLEAR_PERF_BIT, h->vaddr + SA5_OUTDB_CLEAR);
259 /* Do a read in order to flush the write to the controller
262 register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
265 if ((*(h->reply_pool_head) & 1) == (h->reply_pool_wraparound)) {
266 register_value = *(h->reply_pool_head);
267 (h->reply_pool_head)++;
268 h->commands_outstanding--;
270 register_value = FIFO_EMPTY;
272 /* Check for wraparound */
273 if (h->reply_pool_head == (h->reply_pool + h->max_commands)) {
274 h->reply_pool_head = h->reply_pool;
275 h->reply_pool_wraparound ^= 1;
278 return register_value;
282 * Returns true if fifo is full.
285 static unsigned long SA5_fifo_full(struct ctlr_info *h)
287 if (h->commands_outstanding >= h->max_commands)
294 * returns value read from hardware.
295 * returns FIFO_EMPTY if there is nothing to read
297 static unsigned long SA5_completed(struct ctlr_info *h)
299 unsigned long register_value
300 = readl(h->vaddr + SA5_REPLY_PORT_OFFSET);
302 if (register_value != FIFO_EMPTY)
303 h->commands_outstanding--;
306 if (register_value != FIFO_EMPTY)
307 dev_dbg(&h->pdev->dev, "Read %lx back from board\n",
310 dev_dbg(&h->pdev->dev, "hpsa: FIFO Empty read\n");
313 return register_value;
316 * Returns true if an interrupt is pending..
318 static bool SA5_intr_pending(struct ctlr_info *h)
320 unsigned long register_value =
321 readl(h->vaddr + SA5_INTR_STATUS);
322 dev_dbg(&h->pdev->dev, "intr_pending %lx\n", register_value);
323 return register_value & SA5_INTR_PENDING;
326 static bool SA5_performant_intr_pending(struct ctlr_info *h)
328 unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS);
333 if (h->msi_vector || h->msix_vector)
336 /* Read outbound doorbell to flush */
337 register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
338 return register_value & SA5_OUTDB_STATUS_PERF_BIT;
341 static struct access_method SA5_access = {
349 static struct access_method SA5_performant_access = {
351 SA5_performant_intr_mask,
353 SA5_performant_intr_pending,
354 SA5_performant_completed,
360 struct access_method *access;