drivers/scsi/isci/core/scic_sds_controller.c

   1 /*
   2  * This file is provided under a dual BSD/GPLv2 license.  When using or
   3  * redistributing this file, you may do so under either license.
   4  *
   5  * GPL LICENSE SUMMARY
   6  *
   7  * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of version 2 of the GNU General Public License as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  21  * The full GNU General Public License is included in this distribution
  22  * in the file called LICENSE.GPL.
  23  *
  24  * BSD LICENSE
  25  *
  26  * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
  27  * All rights reserved.
  28  *
  29  * Redistribution and use in source and binary forms, with or without
  30  * modification, are permitted provided that the following conditions
  31  * are met:
  32  *
  33  *   * Redistributions of source code must retain the above copyright
  34  *     notice, this list of conditions and the following disclaimer.
  35  *   * Redistributions in binary form must reproduce the above copyright
  36  *     notice, this list of conditions and the following disclaimer in
  37  *     the documentation and/or other materials provided with the
  38  *     distribution.
  39  *   * Neither the name of Intel Corporation nor the names of its
  40  *     contributors may be used to endorse or promote products derived
  41  *     from this software without specific prior written permission.
  42  *
  43  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  44  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  45  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  46  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  47  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  48  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  49  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  50  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  51  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  52  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  53  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  54  */
  55
  56 #include <linux/device.h>
  57 #include "scic_controller.h"
  58 #include "scic_phy.h"
  59 #include "scic_port.h"
  60 #include "scic_remote_device.h"
  61 #include "scic_sds_controller.h"
  62 #include "scic_sds_controller_registers.h"
  63 #include "scic_sds_pci.h"
  64 #include "scic_sds_phy.h"
  65 #include "scic_sds_port_configuration_agent.h"
  66 #include "scic_sds_port.h"
  67 #include "scic_sds_remote_device.h"
  68 #include "scic_sds_request.h"
  69 #include "sci_environment.h"
  70 #include "sci_util.h"
  71 #include "scu_completion_codes.h"
  72 #include "scu_constants.h"
  73 #include "scu_event_codes.h"
  74 #include "scu_remote_node_context.h"
  75 #include "scu_task_context.h"
  76 #include "scu_unsolicited_frame.h"
  77
  78 #define SCU_CONTEXT_RAM_INIT_STALL_TIME      200
  79
  80 /**
  81  * smu_dcc_get_max_ports() -
  82  *
  83  * This macro returns the maximum number of logical ports supported by the
  84  * hardware. The caller passes in the value read from the device context
  85  * capacity register and this macro will mash and shift the value appropriately.
  86  */
  87 #define smu_dcc_get_max_ports(dcc_value) \
  88         (\
  89                 (((dcc_value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_MASK) \
  90                  >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_SHIFT) + 1 \
  91         )
  92
  93 /**
  94  * smu_dcc_get_max_task_context() -
  95  *
  96  * This macro returns the maximum number of task contexts supported by the
  97  * hardware. The caller passes in the value read from the device context
  98  * capacity register and this macro will mash and shift the value appropriately.
  99  */
 100 #define smu_dcc_get_max_task_context(dcc_value) \
 101         (\
 102                 (((dcc_value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_MASK) \
 103                  >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_SHIFT) + 1 \
 104         )
 105
 106 /**
 107  * smu_dcc_get_max_remote_node_context() -
 108  *
 109  * This macro returns the maximum number of remote node contexts supported by
 110  * the hardware. The caller passes in the value read from the device context
 111  * capacity register and this macro will mash and shift the value appropriately.
 112  */
 113 #define smu_dcc_get_max_remote_node_context(dcc_value) \
 114         (\
 115                 (((dcc_value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_MASK) \
 116                  >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_SHIFT) + 1 \
 117         )
 118
 119
 120 static void scic_sds_controller_power_control_timer_handler(
 121         void *controller);
 122 #define SCIC_SDS_CONTROLLER_MIN_TIMER_COUNT  3
 123 #define SCIC_SDS_CONTROLLER_MAX_TIMER_COUNT  3
 124
 125 /**
 126  *
 127  *
 128  * The number of milliseconds to wait for a phy to start.
 129  */
 130 #define SCIC_SDS_CONTROLLER_PHY_START_TIMEOUT      100
 131
 132 /**
 133  *
 134  *
 135  * The number of milliseconds to wait while a given phy is consuming power
 136  * before allowing another set of phys to consume power. Ultimately, this will
 137  * be specified by OEM parameter.
 138  */
 139 #define SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL 500
 140
 141 /**
 142  * COMPLETION_QUEUE_CYCLE_BIT() -
 143  *
 144  * This macro will return the cycle bit of the completion queue entry
 145  */
 146 #define COMPLETION_QUEUE_CYCLE_BIT(x) ((x) & 0x80000000)
 147
 148 /**
 149  * NORMALIZE_GET_POINTER() -
 150  *
 151  * This macro will normalize the completion queue get pointer so its value can
 152  * be used as an index into an array
 153  */
 154 #define NORMALIZE_GET_POINTER(x) \
 155         ((x) & SMU_COMPLETION_QUEUE_GET_POINTER_MASK)
 156
 157 /**
 158  * NORMALIZE_PUT_POINTER() -
 159  *
 160  * This macro will normalize the completion queue put pointer so its value can
 161  * be used as an array inde
 162  */
 163 #define NORMALIZE_PUT_POINTER(x) \
 164         ((x) & SMU_COMPLETION_QUEUE_PUT_POINTER_MASK)
 165
 166
 167 /**
 168  * NORMALIZE_GET_POINTER_CYCLE_BIT() -
 169  *
 170  * This macro will normalize the completion queue cycle pointer so it matches
 171  * the completion queue cycle bit
 172  */
 173 #define NORMALIZE_GET_POINTER_CYCLE_BIT(x) \
 174         ((SMU_CQGR_CYCLE_BIT & (x)) << (31 - SMU_COMPLETION_QUEUE_GET_CYCLE_BIT_SHIFT))
 175
 176 /**
 177  * NORMALIZE_EVENT_POINTER() -
 178  *
 179  * This macro will normalize the completion queue event entry so its value can
 180  * be used as an index.
 181  */
 182 #define NORMALIZE_EVENT_POINTER(x) \
 183         (\
 184                 ((x) & SMU_COMPLETION_QUEUE_GET_EVENT_POINTER_MASK) \
 185                 >> SMU_COMPLETION_QUEUE_GET_EVENT_POINTER_SHIFT \
 186         )
 187
 188 /**
 189  * INCREMENT_COMPLETION_QUEUE_GET() -
 190  *
 191  * This macro will increment the controllers completion queue index value and
 192  * possibly toggle the cycle bit if the completion queue index wraps back to 0.
 193  */
 194 #define INCREMENT_COMPLETION_QUEUE_GET(controller, index, cycle) \
 195         INCREMENT_QUEUE_GET(\
 196                 (index), \
 197                 (cycle), \
 198                 (controller)->completion_queue_entries, \
 199                 SMU_CQGR_CYCLE_BIT \
 200                 )
 201
 202 /**
 203  * INCREMENT_EVENT_QUEUE_GET() -
 204  *
 205  * This macro will increment the controllers event queue index value and
 206  * possibly toggle the event cycle bit if the event queue index wraps back to 0.
 207  */
 208 #define INCREMENT_EVENT_QUEUE_GET(controller, index, cycle) \
 209         INCREMENT_QUEUE_GET(\
 210                 (index), \
 211                 (cycle), \
 212                 (controller)->completion_event_entries, \
 213                 SMU_CQGR_EVENT_CYCLE_BIT \
 214                 )
 215
 216 struct sci_base_memory_descriptor_list *
 217 sci_controller_get_memory_descriptor_list_handle(struct scic_sds_controller *scic)
 218 {
 219        return &scic->parent.mdl;
 220 }
 221
 222 /*
 223  * ****************************************************************************-
 224  * * SCIC SDS Controller Initialization Methods
 225  * ****************************************************************************- */
 226
 227 /**
 228  * This timer is used to start another phy after we have given up on the
 229  *    previous phy to transition to the ready state.
 230  *
 231  *
 232  */
 233 static void scic_sds_controller_phy_startup_timeout_handler(
 234         void *controller)
 235 {
 236         enum sci_status status;
 237         struct scic_sds_controller *this_controller;
 238
 239         this_controller = (struct scic_sds_controller *)controller;
 240
 241         this_controller->phy_startup_timer_pending = false;
 242
 243         status = SCI_FAILURE;
 244
 245         while (status != SCI_SUCCESS) {
 246                 status = scic_sds_controller_start_next_phy(this_controller);
 247         }
 248 }
 249
 250 /**
 251  *
 252  *
 253  * This method initializes the phy startup operations for controller start.
 254  */
 255 enum sci_status scic_sds_controller_initialize_phy_startup(
 256         struct scic_sds_controller *this_controller)
 257 {
 258         this_controller->phy_startup_timer = isci_event_timer_create(
 259                 this_controller,
 260                 scic_sds_controller_phy_startup_timeout_handler,
 261                 this_controller
 262                 );
 263
 264         if (this_controller->phy_startup_timer == NULL) {
 265                 return SCI_FAILURE_INSUFFICIENT_RESOURCES;
 266         } else {
 267                 this_controller->next_phy_to_start = 0;
 268                 this_controller->phy_startup_timer_pending = false;
 269         }
 270
 271         return SCI_SUCCESS;
 272 }
 273
 274 /**
 275  *
 276  *
 277  * This method initializes the power control operations for the controller
 278  * object.
 279  */
 280 void scic_sds_controller_initialize_power_control(
 281         struct scic_sds_controller *this_controller)
 282 {
 283         this_controller->power_control.timer = isci_event_timer_create(
 284                 this_controller,
 285                 scic_sds_controller_power_control_timer_handler,
 286                 this_controller
 287                 );
 288
 289         memset(
 290                 this_controller->power_control.requesters,
 291                 0,
 292                 sizeof(this_controller->power_control.requesters)
 293                 );
 294
 295         this_controller->power_control.phys_waiting = 0;
 296         this_controller->power_control.phys_granted_power = 0;
 297 }
 298
 299 /* --------------------------------------------------------------------------- */
 300
 301 #define SCU_REMOTE_NODE_CONTEXT_ALIGNMENT       (32)
 302 #define SCU_TASK_CONTEXT_ALIGNMENT              (256)
 303 #define SCU_UNSOLICITED_FRAME_ADDRESS_ALIGNMENT (64)
 304 #define SCU_UNSOLICITED_FRAME_BUFFER_ALIGNMENT  (1024)
 305 #define SCU_UNSOLICITED_FRAME_HEADER_ALIGNMENT  (64)
 306
 307 /* --------------------------------------------------------------------------- */
 308
 309 /**
 310  * This method builds the memory descriptor table for this controller.
 311  * @this_controller: This parameter specifies the controller object for which
 312  *    to build the memory table.
 313  *
 314  */
 315 void scic_sds_controller_build_memory_descriptor_table(
 316         struct scic_sds_controller *this_controller)
 317 {
 318         sci_base_mde_construct(
 319                 &this_controller->memory_descriptors[SCU_MDE_COMPLETION_QUEUE],
 320                 SCU_COMPLETION_RAM_ALIGNMENT,
 321                 (sizeof(u32) * this_controller->completion_queue_entries),
 322                 (SCI_MDE_ATTRIBUTE_CACHEABLE | SCI_MDE_ATTRIBUTE_PHYSICALLY_CONTIGUOUS)
 323                 );
 324
 325         sci_base_mde_construct(
 326                 &this_controller->memory_descriptors[SCU_MDE_REMOTE_NODE_CONTEXT],
 327                 SCU_REMOTE_NODE_CONTEXT_ALIGNMENT,
 328                 this_controller->remote_node_entries * sizeof(union scu_remote_node_context),
 329                 SCI_MDE_ATTRIBUTE_PHYSICALLY_CONTIGUOUS
 330                 );
 331
 332         sci_base_mde_construct(
 333                 &this_controller->memory_descriptors[SCU_MDE_TASK_CONTEXT],
 334                 SCU_TASK_CONTEXT_ALIGNMENT,
 335                 this_controller->task_context_entries * sizeof(struct scu_task_context),
 336                 SCI_MDE_ATTRIBUTE_PHYSICALLY_CONTIGUOUS
 337                 );
 338
 339         /*
 340          * The UF buffer address table size must be programmed to a power
 341          * of 2.  Find the first power of 2 that is equal to or greater then
 342          * the number of unsolicited frame buffers to be utilized. */
 343         scic_sds_unsolicited_frame_control_set_address_table_count(
 344                 &this_controller->uf_control
 345                 );
 346
 347         sci_base_mde_construct(
 348                 &this_controller->memory_descriptors[SCU_MDE_UF_BUFFER],
 349                 SCU_UNSOLICITED_FRAME_BUFFER_ALIGNMENT,
 350                 scic_sds_unsolicited_frame_control_get_mde_size(this_controller->uf_control),
 351                 SCI_MDE_ATTRIBUTE_PHYSICALLY_CONTIGUOUS
 352                 );
 353 }
 354
 355 /**
 356  * This method validates the driver supplied memory descriptor table.
 357  * @this_controller:
 358  *
 359  * enum sci_status
 360  */
 361 enum sci_status scic_sds_controller_validate_memory_descriptor_table(
 362         struct scic_sds_controller *this_controller)
 363 {
 364         bool mde_list_valid;
 365
 366         mde_list_valid = sci_base_mde_is_valid(
 367                 &this_controller->memory_descriptors[SCU_MDE_COMPLETION_QUEUE],
 368                 SCU_COMPLETION_RAM_ALIGNMENT,
 369                 (sizeof(u32) * this_controller->completion_queue_entries),
 370                 (SCI_MDE_ATTRIBUTE_CACHEABLE | SCI_MDE_ATTRIBUTE_PHYSICALLY_CONTIGUOUS)
 371                 );
 372
 373         if (mde_list_valid == false)
 374                 return SCI_FAILURE_UNSUPPORTED_INFORMATION_FIELD;
 375
 376         mde_list_valid = sci_base_mde_is_valid(
 377                 &this_controller->memory_descriptors[SCU_MDE_REMOTE_NODE_CONTEXT],
 378                 SCU_REMOTE_NODE_CONTEXT_ALIGNMENT,
 379                 this_controller->remote_node_entries * sizeof(union scu_remote_node_context),
 380                 SCI_MDE_ATTRIBUTE_PHYSICALLY_CONTIGUOUS
 381                 );
 382
 383         if (mde_list_valid == false)
 384                 return SCI_FAILURE_UNSUPPORTED_INFORMATION_FIELD;
 385
 386         mde_list_valid = sci_base_mde_is_valid(
 387                 &this_controller->memory_descriptors[SCU_MDE_TASK_CONTEXT],
 388                 SCU_TASK_CONTEXT_ALIGNMENT,
 389                 this_controller->task_context_entries * sizeof(struct scu_task_context),
 390                 SCI_MDE_ATTRIBUTE_PHYSICALLY_CONTIGUOUS
 391                 );
 392
 393         if (mde_list_valid == false)
 394                 return SCI_FAILURE_UNSUPPORTED_INFORMATION_FIELD;
 395
 396         mde_list_valid = sci_base_mde_is_valid(
 397                 &this_controller->memory_descriptors[SCU_MDE_UF_BUFFER],
 398                 SCU_UNSOLICITED_FRAME_BUFFER_ALIGNMENT,
 399                 scic_sds_unsolicited_frame_control_get_mde_size(this_controller->uf_control),
 400                 SCI_MDE_ATTRIBUTE_PHYSICALLY_CONTIGUOUS
 401                 );
 402
 403         if (mde_list_valid == false)
 404                 return SCI_FAILURE_UNSUPPORTED_INFORMATION_FIELD;
 405
 406         return SCI_SUCCESS;
 407 }
 408
 409 /**
 410  * This method initializes the controller with the physical memory addresses
 411  *    that are used to communicate with the driver.
 412  * @this_controller:
 413  *
 414  */
 415 void scic_sds_controller_ram_initialization(
 416         struct scic_sds_controller *this_controller)
 417 {
 418         struct sci_physical_memory_descriptor *mde;
 419
 420         /*
 421          * The completion queue is actually placed in cacheable memory
 422          * Therefore it no longer comes out of memory in the MDL. */
 423         mde = &this_controller->memory_descriptors[SCU_MDE_COMPLETION_QUEUE];
 424         this_controller->completion_queue = (u32 *)mde->virtual_address;
 425         SMU_CQBAR_WRITE(this_controller, mde->physical_address);
 426
 427         /*
 428          * Program the location of the Remote Node Context table
 429          * into the SCU. */
 430         mde = &this_controller->memory_descriptors[SCU_MDE_REMOTE_NODE_CONTEXT];
 431         this_controller->remote_node_context_table = (union scu_remote_node_context *)
 432                                                      mde->virtual_address;
 433         SMU_RNCBAR_WRITE(this_controller, mde->physical_address);
 434
 435         /* Program the location of the Task Context table into the SCU. */
 436         mde = &this_controller->memory_descriptors[SCU_MDE_TASK_CONTEXT];
 437         this_controller->task_context_table = (struct scu_task_context *)
 438                                               mde->virtual_address;
 439         SMU_HTTBAR_WRITE(this_controller, mde->physical_address);
 440
 441         mde = &this_controller->memory_descriptors[SCU_MDE_UF_BUFFER];
 442         scic_sds_unsolicited_frame_control_construct(
 443                 &this_controller->uf_control, mde, this_controller
 444                 );
 445
 446         /*
 447          * Inform the silicon as to the location of the UF headers and
 448          * address table. */
 449         SCU_UFHBAR_WRITE(
 450                 this_controller,
 451                 this_controller->uf_control.headers.physical_address);
 452         SCU_PUFATHAR_WRITE(
 453                 this_controller,
 454                 this_controller->uf_control.address_table.physical_address);
 455 }
 456
 457 /**
 458  * This method initializes the task context data for the controller.
 459  * @this_controller:
 460  *
 461  */
 462 void scic_sds_controller_assign_task_entries(
 463         struct scic_sds_controller *this_controller)
 464 {
 465         u32 task_assignment;
 466
 467         /*
 468          * Assign all the TCs to function 0
 469          * TODO: Do we actually need to read this register to write it back? */
 470         task_assignment = SMU_TCA_READ(this_controller, 0);
 471
 472         task_assignment =
 473                 (
 474                         task_assignment
 475                         | (SMU_TCA_GEN_VAL(STARTING, 0))
 476                         | (SMU_TCA_GEN_VAL(ENDING,  this_controller->task_context_entries - 1))
 477                         | (SMU_TCA_GEN_BIT(RANGE_CHECK_ENABLE))
 478                 );
 479
 480         SMU_TCA_WRITE(this_controller, 0, task_assignment);
 481 }
 482
 483 /**
 484  * This method initializes the hardware completion queue.
 485  *
 486  *
 487  */
 488 void scic_sds_controller_initialize_completion_queue(
 489         struct scic_sds_controller *this_controller)
 490 {
 491         u32 index;
 492         u32 completion_queue_control_value;
 493         u32 completion_queue_get_value;
 494         u32 completion_queue_put_value;
 495
 496         this_controller->completion_queue_get = 0;
 497
 498         completion_queue_control_value = (
 499                 SMU_CQC_QUEUE_LIMIT_SET(this_controller->completion_queue_entries - 1)
 500                 | SMU_CQC_EVENT_LIMIT_SET(this_controller->completion_event_entries - 1)
 501                 );
 502
 503         SMU_CQC_WRITE(this_controller, completion_queue_control_value);
 504
 505         /* Set the completion queue get pointer and enable the queue */
 506         completion_queue_get_value = (
 507                 (SMU_CQGR_GEN_VAL(POINTER, 0))
 508                 | (SMU_CQGR_GEN_VAL(EVENT_POINTER, 0))
 509                 | (SMU_CQGR_GEN_BIT(ENABLE))
 510                 | (SMU_CQGR_GEN_BIT(EVENT_ENABLE))
 511                 );
 512
 513         SMU_CQGR_WRITE(this_controller, completion_queue_get_value);
 514
 515         /* Set the completion queue put pointer */
 516         completion_queue_put_value = (
 517                 (SMU_CQPR_GEN_VAL(POINTER, 0))
 518                 | (SMU_CQPR_GEN_VAL(EVENT_POINTER, 0))
 519                 );
 520
 521         SMU_CQPR_WRITE(this_controller, completion_queue_put_value);
 522
 523         /* Initialize the cycle bit of the completion queue entries */
 524         for (index = 0; index < this_controller->completion_queue_entries; index++) {
 525                 /*
 526                  * If get.cycle_bit != completion_queue.cycle_bit
 527                  * its not a valid completion queue entry
 528                  * so at system start all entries are invalid */
 529                 this_controller->completion_queue[index] = 0x80000000;
 530         }
 531 }
 532
 533 /**
 534  * This method initializes the hardware unsolicited frame queue.
 535  *
 536  *
 537  */
 538 void scic_sds_controller_initialize_unsolicited_frame_queue(
 539         struct scic_sds_controller *this_controller)
 540 {
 541         u32 frame_queue_control_value;
 542         u32 frame_queue_get_value;
 543         u32 frame_queue_put_value;
 544
 545         /* Write the queue size */
 546         frame_queue_control_value =
 547                 SCU_UFQC_GEN_VAL(QUEUE_SIZE, this_controller->uf_control.address_table.count);
 548
 549         SCU_UFQC_WRITE(this_controller, frame_queue_control_value);
 550
 551         /* Setup the get pointer for the unsolicited frame queue */
 552         frame_queue_get_value = (
 553                 SCU_UFQGP_GEN_VAL(POINTER, 0)
 554                 |  SCU_UFQGP_GEN_BIT(ENABLE_BIT)
 555                 );
 556
 557         SCU_UFQGP_WRITE(this_controller, frame_queue_get_value);
 558
 559         /* Setup the put pointer for the unsolicited frame queue */
 560         frame_queue_put_value = SCU_UFQPP_GEN_VAL(POINTER, 0);
 561
 562         SCU_UFQPP_WRITE(this_controller, frame_queue_put_value);
 563 }
 564
 565 /**
 566  * This method enables the hardware port task scheduler.
 567  *
 568  *
 569  */
 570 void scic_sds_controller_enable_port_task_scheduler(
 571         struct scic_sds_controller *this_controller)
 572 {
 573         u32 port_task_scheduler_value;
 574
 575         port_task_scheduler_value = SCU_PTSGCR_READ(this_controller);
 576
 577         port_task_scheduler_value |=
 578                 (SCU_PTSGCR_GEN_BIT(ETM_ENABLE) | SCU_PTSGCR_GEN_BIT(PTSG_ENABLE));
 579
 580         SCU_PTSGCR_WRITE(this_controller, port_task_scheduler_value);
 581 }
 582
 583 /* --------------------------------------------------------------------------- */
 584
 585 /**
 586  *
 587  *
 588  * This macro is used to delay between writes to the AFE registers during AFE
 589  * initialization.
 590  */
 591 #define AFE_REGISTER_WRITE_DELAY 10
 592
 593 /* Initialize the AFE for this phy index. We need to read the AFE setup from
 594  * the OEM parameters none
 595  */
 596 void scic_sds_controller_afe_initialization(struct scic_sds_controller *scic)
 597 {
 598         const struct scic_sds_oem_params *oem = &scic->oem_parameters.sds1;
 599         u32 afe_status;
 600         u32 phy_id;
 601
 602         /* Clear DFX Status registers */
 603         scu_afe_register_write(scic, afe_dfx_master_control0, 0x0081000f);
 604         udelay(AFE_REGISTER_WRITE_DELAY);
 605
 606         /* Configure bias currents to normal */
 607         if (is_a0())
 608                 scu_afe_register_write(scic, afe_bias_control, 0x00005500);
 609         else
 610                 scu_afe_register_write(scic, afe_bias_control, 0x00005A00);
 611
 612         udelay(AFE_REGISTER_WRITE_DELAY);
 613
 614         /* Enable PLL */
 615         if (is_b0())
 616                 scu_afe_register_write(scic, afe_pll_control0, 0x80040A08);
 617         else
 618                 scu_afe_register_write(scic, afe_pll_control0, 0x80040908);
 619
 620         udelay(AFE_REGISTER_WRITE_DELAY);
 621
 622         /* Wait for the PLL to lock */
 623         do {
 624                 afe_status = scu_afe_register_read(
 625                         scic, afe_common_block_status);
 626                 udelay(AFE_REGISTER_WRITE_DELAY);
 627         } while ((afe_status & 0x00001000) == 0);
 628
 629         if (is_b0()) {
 630                 /* Shorten SAS SNW lock time (RxLock timer value from 76 us to 50 us) */
 631                 scu_afe_register_write(scic, afe_pmsn_master_control0, 0x7bcc96ad);
 632                 udelay(AFE_REGISTER_WRITE_DELAY);
 633         }
 634
 635         for (phy_id = 0; phy_id < SCI_MAX_PHYS; phy_id++) {
 636                 const struct sci_phy_oem_params *oem_phy = &oem->phys[phy_id];
 637
 638                 if (is_b0()) {
 639                          /* Configure transmitter SSC parameters */
 640                         scu_afe_txreg_write(scic, phy_id, afe_tx_ssc_control, 0x00030000);
 641                         udelay(AFE_REGISTER_WRITE_DELAY);
 642                 } else {
 643                         /*
 644                          * All defaults, except the Receive Word Alignament/Comma Detect
 645                          * Enable....(0xe800) */
 646                         scu_afe_txreg_write(scic, phy_id, afe_xcvr_control0, 0x00004512);
 647                         udelay(AFE_REGISTER_WRITE_DELAY);
 648
 649                         scu_afe_txreg_write(scic, phy_id, afe_xcvr_control1, 0x0050100F);
 650                         udelay(AFE_REGISTER_WRITE_DELAY);
 651                 }
 652
 653                 /*
 654                  * Power up TX and RX out from power down (PWRDNTX and PWRDNRX)
 655                  * & increase TX int & ext bias 20%....(0xe85c) */
 656                 if (is_a0())
 657                         scu_afe_txreg_write(scic, phy_id, afe_channel_control, 0x000003D4);
 658                 else if (is_a2())
 659                         scu_afe_txreg_write(scic, phy_id, afe_channel_control, 0x000003F0);
 660                 else {
 661                          /* Power down TX and RX (PWRDNTX and PWRDNRX) */
 662                         scu_afe_txreg_write(scic, phy_id, afe_channel_control, 0x000003d7);
 663                         udelay(AFE_REGISTER_WRITE_DELAY);
 664
 665                         /*
 666                          * Power up TX and RX out from power down (PWRDNTX and PWRDNRX)
 667                          * & increase TX int & ext bias 20%....(0xe85c) */
 668                         scu_afe_txreg_write(scic, phy_id, afe_channel_control, 0x000003d4);
 669                 }
 670                 udelay(AFE_REGISTER_WRITE_DELAY);
 671
 672                 if (is_a0() || is_a2()) {
 673                         /* Enable TX equalization (0xe824) */
 674                         scu_afe_txreg_write(scic, phy_id, afe_tx_control, 0x00040000);
 675                         udelay(AFE_REGISTER_WRITE_DELAY);
 676                 }
 677
 678                 /*
 679                  * RDPI=0x0(RX Power On), RXOOBDETPDNC=0x0, TPD=0x0(TX Power On),
 680                  * RDD=0x0(RX Detect Enabled) ....(0xe800) */
 681                 scu_afe_txreg_write(scic, phy_id, afe_xcvr_control0, 0x00004100);
 682                 udelay(AFE_REGISTER_WRITE_DELAY);
 683
 684                 /* Leave DFE/FFE on */
 685                 if (is_a0())
 686                         scu_afe_txreg_write(scic, phy_id, afe_rx_ssc_control0, 0x3F09983F);
 687                 else if (is_a2())
 688                         scu_afe_txreg_write(scic, phy_id, afe_rx_ssc_control0, 0x3F11103F);
 689                 else {
 690                         scu_afe_txreg_write(scic, phy_id, afe_rx_ssc_control0, 0x3F11103F);
 691                         udelay(AFE_REGISTER_WRITE_DELAY);
 692                         /* Enable TX equalization (0xe824) */
 693                         scu_afe_txreg_write(scic, phy_id, afe_tx_control, 0x00040000);
 694                 }
 695                 udelay(AFE_REGISTER_WRITE_DELAY);
 696
 697                 scu_afe_txreg_write(scic, phy_id, afe_tx_amp_control0, oem_phy->afe_tx_amp_control0);
 698                 udelay(AFE_REGISTER_WRITE_DELAY);
 699
 700                 scu_afe_txreg_write(scic, phy_id, afe_tx_amp_control0, oem_phy->afe_tx_amp_control1);
 701                 udelay(AFE_REGISTER_WRITE_DELAY);
 702
 703                 scu_afe_txreg_write(scic, phy_id, afe_tx_amp_control0, oem_phy->afe_tx_amp_control2);
 704                 udelay(AFE_REGISTER_WRITE_DELAY);
 705
 706                 scu_afe_txreg_write(scic, phy_id, afe_tx_amp_control0, oem_phy->afe_tx_amp_control3);
 707                 udelay(AFE_REGISTER_WRITE_DELAY);
 708         }
 709
 710         /* Transfer control to the PEs */
 711         scu_afe_register_write(scic, afe_dfx_master_control0, 0x00010f00);
 712         udelay(AFE_REGISTER_WRITE_DELAY);
 713 }
 714
 715 /*
 716  * ****************************************************************************-
 717  * * SCIC SDS Controller Internal Start/Stop Routines
 718  * ****************************************************************************- */
 719
 720
 721 /**
 722  * This method will attempt to transition into the ready state for the
 723  *    controller and indicate that the controller start operation has completed
 724  *    if all criteria are met.
 725  * @this_controller: This parameter indicates the controller object for which
 726  *    to transition to ready.
 727  * @status: This parameter indicates the status value to be pass into the call
 728  *    to scic_cb_controller_start_complete().
 729  *
 730  * none.
 731  */
 732 static void scic_sds_controller_transition_to_ready(
 733         struct scic_sds_controller *this_controller,
 734         enum sci_status status)
 735 {
 736         if (this_controller->parent.state_machine.current_state_id
 737             == SCI_BASE_CONTROLLER_STATE_STARTING) {
 738                 /*
 739                  * We move into the ready state, because some of the phys/ports
 740                  * may be up and operational. */
 741                 sci_base_state_machine_change_state(
 742                         scic_sds_controller_get_base_state_machine(this_controller),
 743                         SCI_BASE_CONTROLLER_STATE_READY
 744                         );
 745
 746                 isci_event_controller_start_complete(this_controller, status);
 747         }
 748 }
 749
 750 /**
 751  * This method is the general timeout handler for the controller. It will take
 752  *    the correct timetout action based on the current controller state
 753  */
 754 void scic_sds_controller_timeout_handler(
 755         struct scic_sds_controller *scic)
 756 {
 757         enum sci_base_controller_states current_state;
 758
 759         current_state = sci_base_state_machine_get_state(
 760                 scic_sds_controller_get_base_state_machine(scic));
 761
 762         if (current_state == SCI_BASE_CONTROLLER_STATE_STARTING) {
 763                 scic_sds_controller_transition_to_ready(
 764                         scic, SCI_FAILURE_TIMEOUT);
 765         } else if (current_state == SCI_BASE_CONTROLLER_STATE_STOPPING) {
 766                 sci_base_state_machine_change_state(
 767                         scic_sds_controller_get_base_state_machine(scic),
 768                         SCI_BASE_CONTROLLER_STATE_FAILED);
 769                 isci_event_controller_stop_complete(scic, SCI_FAILURE_TIMEOUT);
 770         } else  /* / @todo Now what do we want to do in this case? */
 771                 dev_err(scic_to_dev(scic),
 772                         "%s: Controller timer fired when controller was not "
 773                         "in a state being timed.\n",
 774                         __func__);
 775 }
 776
 777 enum sci_status scic_sds_controller_stop_ports(struct scic_sds_controller *scic)
 778 {
 779         u32 index;
 780         enum sci_status port_status;
 781         enum sci_status status = SCI_SUCCESS;
 782
 783         for (index = 0; index < scic->logical_port_entries; index++) {
 784                 struct scic_sds_port *sci_port = &scic->port_table[index];
 785                 SCI_BASE_PORT_HANDLER_T stop;
 786
 787                 stop = sci_port->state_handlers->parent.stop_handler;
 788                 port_status = stop(&sci_port->parent);
 789
 790                 if ((port_status != SCI_SUCCESS) &&
 791                     (port_status != SCI_FAILURE_INVALID_STATE)) {
 792                         status = SCI_FAILURE;
 793
 794                         dev_warn(scic_to_dev(scic),
 795                                  "%s: Controller stop operation failed to "
 796                                  "stop port %d because of status %d.\n",
 797                                  __func__,
 798                                  sci_port->logical_port_index,
 799                                  port_status);
 800                 }
 801         }
 802
 803         return status;
 804 }
 805
 806 /**
 807  *
 808  *
 809  *
 810  */
 811 static void scic_sds_controller_phy_timer_start(
 812         struct scic_sds_controller *this_controller)
 813 {
 814         isci_event_timer_start(
 815                 this_controller,
 816                 this_controller->phy_startup_timer,
 817                 SCIC_SDS_CONTROLLER_PHY_START_TIMEOUT
 818                 );
 819
 820         this_controller->phy_startup_timer_pending = true;
 821 }
 822
 823 /**
 824  *
 825  *
 826  *
 827  */
 828 void scic_sds_controller_phy_timer_stop(
 829         struct scic_sds_controller *this_controller)
 830 {
 831         isci_event_timer_stop(
 832                 this_controller,
 833                 this_controller->phy_startup_timer
 834                 );
 835
 836         this_controller->phy_startup_timer_pending = false;
 837 }
 838
 839 /**
 840  * This method is called internally by the controller object to start the next
 841  *    phy on the controller.  If all the phys have been started, then this
 842  *    method will attempt to transition the controller to the READY state and
 843  *    inform the user (scic_cb_controller_start_complete()).
 844  * @this_controller: This parameter specifies the controller object for which
 845  *    to start the next phy.
 846  *
 847  * enum sci_status
 848  */
 849 enum sci_status scic_sds_controller_start_next_phy(struct scic_sds_controller *scic)
 850 {
 851         struct scic_sds_oem_params *oem = &scic->oem_parameters.sds1;
 852         struct scic_sds_phy *sci_phy;
 853         enum sci_status status;
 854
 855         status = SCI_SUCCESS;
 856
 857         if (scic->phy_startup_timer_pending)
 858                 return status;
 859
 860         if (scic->next_phy_to_start >= SCI_MAX_PHYS) {
 861                 bool is_controller_start_complete = true;
 862                 u32 state;
 863                 u8 index;
 864
 865                 for (index = 0; index < SCI_MAX_PHYS; index++) {
 866                         sci_phy = &scic->phy_table[index];
 867                         state = sci_phy->parent.state_machine.current_state_id;
 868
 869                         if (!scic_sds_phy_get_port(sci_phy))
 870                                 continue;
 871
 872                         /* The controller start operation is complete iff:
 873                          * - all links have been given an opportunity to start
 874                          * - have no indication of a connected device
 875                          * - have an indication of a connected device and it has
 876                          *   finished the link training process.
 877                          */
 878                         if ((sci_phy->is_in_link_training == false &&
 879                              state == SCI_BASE_PHY_STATE_INITIAL) ||
 880                             (sci_phy->is_in_link_training == false &&
 881                              state == SCI_BASE_PHY_STATE_STOPPED) ||
 882                             (sci_phy->is_in_link_training == true &&
 883                              state == SCI_BASE_PHY_STATE_STARTING)) {
 884                                 is_controller_start_complete = false;
 885                                 break;
 886                         }
 887                 }
 888
 889                 /*
 890                  * The controller has successfully finished the start process.
 891                  * Inform the SCI Core user and transition to the READY state. */
 892                 if (is_controller_start_complete == true) {
 893                         scic_sds_controller_transition_to_ready(scic, SCI_SUCCESS);
 894                         scic_sds_controller_phy_timer_stop(scic);
 895                 }
 896         } else {
 897                 sci_phy = &scic->phy_table[scic->next_phy_to_start];
 898
 899                 if (oem->controller.mode_type == SCIC_PORT_MANUAL_CONFIGURATION_MODE) {
 900                         if (scic_sds_phy_get_port(sci_phy) == NULL) {
 901                                 scic->next_phy_to_start++;
 902
 903                                 /* Caution recursion ahead be forwarned
 904                                  *
 905                                  * The PHY was never added to a PORT in MPC mode
 906                                  * so start the next phy in sequence This phy
 907                                  * will never go link up and will not draw power
 908                                  * the OEM parameters either configured the phy
 909                                  * incorrectly for the PORT or it was never
 910                                  * assigned to a PORT
 911                                  */
 912                                 return scic_sds_controller_start_next_phy(scic);
 913                         }
 914                 }
 915
 916                 status = scic_sds_phy_start(sci_phy);
 917
 918                 if (status == SCI_SUCCESS) {
 919                         scic_sds_controller_phy_timer_start(scic);
 920                 } else {
 921                         dev_warn(scic_to_dev(scic),
 922                                  "%s: Controller stop operation failed "
 923                                  "to stop phy %d because of status "
 924                                  "%d.\n",
 925                                  __func__,
 926                                  scic->phy_table[scic->next_phy_to_start].phy_index,
 927                                  status);
 928                 }
 929
 930                 scic->next_phy_to_start++;
 931         }
 932
 933         return status;
 934 }
 935
 936 /**
 937  *
 938  * @this_controller:
 939  *
 940  * enum sci_status
 941  */
 942 enum sci_status scic_sds_controller_stop_phys(
 943         struct scic_sds_controller *this_controller)
 944 {
 945         u32 index;
 946         enum sci_status status;
 947         enum sci_status phy_status;
 948
 949         status = SCI_SUCCESS;
 950
 951         for (index = 0; index < SCI_MAX_PHYS; index++) {
 952                 phy_status = scic_sds_phy_stop(&this_controller->phy_table[index]);
 953
 954                 if (
 955                         (phy_status != SCI_SUCCESS)
 956                         && (phy_status != SCI_FAILURE_INVALID_STATE)
 957                         ) {
 958                         status = SCI_FAILURE;
 959
 960                         dev_warn(scic_to_dev(this_controller),
 961                                  "%s: Controller stop operation failed to stop "
 962                                  "phy %d because of status %d.\n",
 963                                  __func__,
 964                                  this_controller->phy_table[index].phy_index, phy_status);
 965                 }
 966         }
 967
 968         return status;
 969 }
 970
 971 /**
 972  *
 973  * @this_controller:
 974  *
 975  * enum sci_status
 976  */
 977 enum sci_status scic_sds_controller_stop_devices(
 978         struct scic_sds_controller *this_controller)
 979 {
 980         u32 index;
 981         enum sci_status status;
 982         enum sci_status device_status;
 983
 984         status = SCI_SUCCESS;
 985
 986         for (index = 0; index < this_controller->remote_node_entries; index++) {
 987                 if (this_controller->device_table[index] != NULL) {
 988                         /* / @todo What timeout value do we want to provide to this request? */
 989                         device_status = scic_remote_device_stop(this_controller->device_table[index], 0);
 990
 991                         if ((device_status != SCI_SUCCESS) &&
 992                             (device_status != SCI_FAILURE_INVALID_STATE)) {
 993                                 dev_warn(scic_to_dev(this_controller),
 994                                          "%s: Controller stop operation failed "
 995                                          "to stop device 0x%p because of "
 996                                          "status %d.\n",
 997                                          __func__,
 998                                          this_controller->device_table[index], device_status);
 999                         }
1000                 }
1001         }
1002
1003         return status;
1004 }
1005
1006 /*
1007  * ****************************************************************************-
1008  * * SCIC SDS Controller Power Control (Staggered Spinup)
1009  * ****************************************************************************- */
1010
1011 /**
1012  *
1013  *
1014  * This method starts the power control timer for this controller object.
1015  */
1016 static void scic_sds_controller_power_control_timer_start(
1017         struct scic_sds_controller *this_controller)
1018 {
1019         isci_event_timer_start(
1020                 this_controller, this_controller->power_control.timer,
1021                 SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL
1022                 );
1023
1024         this_controller->power_control.timer_started = true;
1025 }
1026
1027 /**
1028  * This method stops the power control timer for this controller object.
1029  *
1030  * @param scic
1031  */
1032 void scic_sds_controller_power_control_timer_stop(struct scic_sds_controller *scic)
1033 {
1034         if (scic->power_control.timer_started) {
1035                 isci_event_timer_stop(scic, scic->power_control.timer);
1036                 scic->power_control.timer_started = false;
1037         }
1038 }
1039
1040 /**
1041  * This method stops and starts the power control timer for this controller object.
1042  *
1043  * @param scic
1044  */
1045 void scic_sds_controller_power_control_timer_restart(
1046         struct scic_sds_controller *scic)
1047 {
1048         scic_sds_controller_power_control_timer_stop(scic);
1049         scic_sds_controller_power_control_timer_start(scic);
1050 }
1051
1052 /**
1053  *
1054  *
1055  *
1056  */
1057 static void scic_sds_controller_power_control_timer_handler(
1058         void *controller)
1059 {
1060         struct scic_sds_controller *this_controller;
1061
1062         this_controller = (struct scic_sds_controller *)controller;
1063
1064         this_controller->power_control.phys_granted_power = 0;
1065
1066         if (this_controller->power_control.phys_waiting == 0) {
1067                 this_controller->power_control.timer_started = false;
1068         } else {
1069                 struct scic_sds_phy *the_phy = NULL;
1070                 u8 i;
1071
1072                 for (i = 0;
1073                      (i < SCI_MAX_PHYS)
1074                      && (this_controller->power_control.phys_waiting != 0);
1075                      i++) {
1076                         if (this_controller->power_control.requesters[i] != NULL) {
1077                                 if (this_controller->power_control.phys_granted_power <
1078                                     this_controller->oem_parameters.sds1.controller.max_concurrent_dev_spin_up) {
1079                                         the_phy = this_controller->power_control.requesters[i];
1080                                         this_controller->power_control.requesters[i] = NULL;
1081                                         this_controller->power_control.phys_waiting--;
1082                                         this_controller->power_control.phys_granted_power++;
1083                                         scic_sds_phy_consume_power_handler(the_phy);
1084                                 } else {
1085                                         break;
1086                                 }
1087                         }
1088                 }
1089
1090                 /*
1091                  * It doesn't matter if the power list is empty, we need to start the
1092                  * timer in case another phy becomes ready.
1093                  */
1094                 scic_sds_controller_power_control_timer_start(this_controller);
1095         }
1096 }
1097
1098 /**
1099  * This method inserts the phy in the stagger spinup control queue.
1100  * @this_controller:
1101  *
1102  *
1103  */
1104 void scic_sds_controller_power_control_queue_insert(
1105         struct scic_sds_controller *this_controller,
1106         struct scic_sds_phy *the_phy)
1107 {
1108         BUG_ON(the_phy == NULL);
1109
1110         if (this_controller->power_control.phys_granted_power <
1111             this_controller->oem_parameters.sds1.controller.max_concurrent_dev_spin_up) {
1112                 this_controller->power_control.phys_granted_power++;
1113                 scic_sds_phy_consume_power_handler(the_phy);
1114
1115                 /*
1116                  * stop and start the power_control timer. When the timer fires, the
1117                  * no_of_phys_granted_power will be set to 0
1118                  */
1119                 scic_sds_controller_power_control_timer_restart(this_controller);
1120         } else {
1121                 /* Add the phy in the waiting list */
1122                 this_controller->power_control.requesters[the_phy->phy_index] = the_phy;
1123                 this_controller->power_control.phys_waiting++;
1124         }
1125 }
1126
1127 /**
1128  * This method removes the phy from the stagger spinup control queue.
1129  * @this_controller:
1130  *
1131  *
1132  */
1133 void scic_sds_controller_power_control_queue_remove(
1134         struct scic_sds_controller *this_controller,
1135         struct scic_sds_phy *the_phy)
1136 {
1137         BUG_ON(the_phy == NULL);
1138
1139         if (this_controller->power_control.requesters[the_phy->phy_index] != NULL) {
1140                 this_controller->power_control.phys_waiting--;
1141         }
1142
1143         this_controller->power_control.requesters[the_phy->phy_index] = NULL;
1144 }
1145
1146 /*
1147  * ****************************************************************************-
1148  * * SCIC SDS Controller Completion Routines
1149  * ****************************************************************************- */
1150
1151 /**
1152  * This method returns a true value if the completion queue has entries that
1153  *    can be processed
1154  * @this_controller:
1155  *
1156  * bool true if the completion queue has entries to process false if the
1157  * completion queue has no entries to process
1158  */
1159 static bool scic_sds_controller_completion_queue_has_entries(
1160         struct scic_sds_controller *this_controller)
1161 {
1162         u32 get_value = this_controller->completion_queue_get;
1163         u32 get_index = get_value & SMU_COMPLETION_QUEUE_GET_POINTER_MASK;
1164
1165         if (
1166                 NORMALIZE_GET_POINTER_CYCLE_BIT(get_value)
1167                 == COMPLETION_QUEUE_CYCLE_BIT(this_controller->completion_queue[get_index])
1168                 ) {
1169                 return true;
1170         }
1171
1172         return false;
1173 }
1174
1175 /* --------------------------------------------------------------------------- */
1176
1177 /**
1178  * This method processes a task completion notification.  This is called from
1179  *    within the controller completion handler.
1180  * @this_controller:
1181  * @completion_entry:
1182  *
1183  */
1184 static void scic_sds_controller_task_completion(
1185         struct scic_sds_controller *this_controller,
1186         u32 completion_entry)
1187 {
1188         u32 index;
1189         struct scic_sds_request *io_request;
1190
1191         index = SCU_GET_COMPLETION_INDEX(completion_entry);
1192         io_request = this_controller->io_request_table[index];
1193
1194         /* Make sure that we really want to process this IO request */
1195         if (
1196                 (io_request != NULL)
1197                 && (io_request->io_tag != SCI_CONTROLLER_INVALID_IO_TAG)
1198                 && (
1199                         scic_sds_io_tag_get_sequence(io_request->io_tag)
1200                         == this_controller->io_request_sequence[index]
1201                         )
1202                 ) {
1203                 /* Yep this is a valid io request pass it along to the io request handler */
1204                 scic_sds_io_request_tc_completion(io_request, completion_entry);
1205         }
1206 }
1207
1208 /**
1209  * This method processes an SDMA completion event.  This is called from within
1210  *    the controller completion handler.
1211  * @this_controller:
1212  * @completion_entry:
1213  *
1214  */
1215 static void scic_sds_controller_sdma_completion(
1216         struct scic_sds_controller *this_controller,
1217         u32 completion_entry)
1218 {
1219         u32 index;
1220         struct scic_sds_request *io_request;
1221         struct scic_sds_remote_device *device;
1222
1223         index = SCU_GET_COMPLETION_INDEX(completion_entry);
1224
1225         switch (scu_get_command_request_type(completion_entry)) {
1226         case SCU_CONTEXT_COMMAND_REQUEST_TYPE_POST_TC:
1227         case SCU_CONTEXT_COMMAND_REQUEST_TYPE_DUMP_TC:
1228                 io_request = this_controller->io_request_table[index];
1229                 dev_warn(scic_to_dev(this_controller),
1230                          "%s: SCIC SDS Completion type SDMA %x for io request "
1231                          "%p\n",
1232                          __func__,
1233                          completion_entry,
1234                          io_request);
1235                 /* @todo For a post TC operation we need to fail the IO
1236                  * request
1237                  */
1238                 break;
1239
1240         case SCU_CONTEXT_COMMAND_REQUEST_TYPE_DUMP_RNC:
1241         case SCU_CONTEXT_COMMAND_REQUEST_TYPE_OTHER_RNC:
1242         case SCU_CONTEXT_COMMAND_REQUEST_TYPE_POST_RNC:
1243                 device = this_controller->device_table[index];
1244                 dev_warn(scic_to_dev(this_controller),
1245                          "%s: SCIC SDS Completion type SDMA %x for remote "
1246                          "device %p\n",
1247                          __func__,
1248                          completion_entry,
1249                          device);
1250                 /* @todo For a port RNC operation we need to fail the
1251                  * device
1252                  */
1253                 break;
1254
1255         default:
1256                 dev_warn(scic_to_dev(this_controller),
1257                          "%s: SCIC SDS Completion unknown SDMA completion "
1258                          "type %x\n",
1259                          __func__,
1260                          completion_entry);
1261                 break;
1262
1263         }
1264 }
1265
1266 /**
1267  *
1268  * @this_controller:
1269  * @completion_entry:
1270  *
1271  * This method processes an unsolicited frame message.  This is called from
1272  * within the controller completion handler. none
1273  */
1274 static void scic_sds_controller_unsolicited_frame(
1275         struct scic_sds_controller *this_controller,
1276         u32 completion_entry)
1277 {
1278         u32 index;
1279         u32 frame_index;
1280
1281         struct scu_unsolicited_frame_header *frame_header;
1282         struct scic_sds_phy *phy;
1283         struct scic_sds_remote_device *device;
1284
1285         enum sci_status result = SCI_FAILURE;
1286
1287         frame_index = SCU_GET_FRAME_INDEX(completion_entry);
1288
1289         frame_header
1290                 = this_controller->uf_control.buffers.array[frame_index].header;
1291         this_controller->uf_control.buffers.array[frame_index].state
1292                 = UNSOLICITED_FRAME_IN_USE;
1293
1294         if (SCU_GET_FRAME_ERROR(completion_entry)) {
1295                 /*
1296                  * / @todo If the IAF frame or SIGNATURE FIS frame has an error will
1297                  * /       this cause a problem? We expect the phy initialization will
1298                  * /       fail if there is an error in the frame. */
1299                 scic_sds_controller_release_frame(this_controller, frame_index);
1300                 return;
1301         }
1302
1303         if (frame_header->is_address_frame) {
1304                 index = SCU_GET_PROTOCOL_ENGINE_INDEX(completion_entry);
1305                 phy = &this_controller->phy_table[index];
1306                 if (phy != NULL) {
1307                         result = scic_sds_phy_frame_handler(phy, frame_index);
1308                 }
1309         } else {
1310
1311                 index = SCU_GET_COMPLETION_INDEX(completion_entry);
1312
1313                 if (index == SCIC_SDS_REMOTE_NODE_CONTEXT_INVALID_INDEX) {
1314                         /*
1315                          * This is a signature fis or a frame from a direct attached SATA
1316                          * device that has not yet been created.  In either case forwared
1317                          * the frame to the PE and let it take care of the frame data. */
1318                         index = SCU_GET_PROTOCOL_ENGINE_INDEX(completion_entry);
1319                         phy = &this_controller->phy_table[index];
1320                         result = scic_sds_phy_frame_handler(phy, frame_index);
1321                 } else {
1322                         if (index < this_controller->remote_node_entries)
1323                                 device = this_controller->device_table[index];
1324                         else
1325                                 device = NULL;
1326
1327                         if (device != NULL)
1328                                 result = scic_sds_remote_device_frame_handler(device, frame_index);
1329                         else
1330                                 scic_sds_controller_release_frame(this_controller, frame_index);
1331                 }
1332         }
1333
1334         if (result != SCI_SUCCESS) {
1335                 /*
1336                  * / @todo Is there any reason to report some additional error message
1337                  * /       when we get this failure notifiction? */
1338         }
1339 }
1340
1341 /**
1342  * This method processes an event completion entry.  This is called from within
1343  *    the controller completion handler.
1344  * @this_controller:
1345  * @completion_entry:
1346  *
1347  */
1348 static void scic_sds_controller_event_completion(
1349         struct scic_sds_controller *this_controller,
1350         u32 completion_entry)
1351 {
1352         u32 index;
1353         struct scic_sds_request *io_request;
1354         struct scic_sds_remote_device *device;
1355         struct scic_sds_phy *phy;
1356
1357         index = SCU_GET_COMPLETION_INDEX(completion_entry);
1358
1359         switch (scu_get_event_type(completion_entry)) {
1360         case SCU_EVENT_TYPE_SMU_COMMAND_ERROR:
1361                 /* / @todo The driver did something wrong and we need to fix the condtion. */
1362                 dev_err(scic_to_dev(this_controller),
1363                         "%s: SCIC Controller 0x%p received SMU command error "
1364                         "0x%x\n",
1365                         __func__,
1366                         this_controller,
1367                         completion_entry);
1368                 break;
1369
1370         case SCU_EVENT_TYPE_SMU_PCQ_ERROR:
1371         case SCU_EVENT_TYPE_SMU_ERROR:
1372         case SCU_EVENT_TYPE_FATAL_MEMORY_ERROR:
1373                 /*
1374                  * / @todo This is a hardware failure and its likely that we want to
1375                  * /       reset the controller. */
1376                 dev_err(scic_to_dev(this_controller),
1377                         "%s: SCIC Controller 0x%p received fatal controller "
1378                         "event  0x%x\n",
1379                         __func__,
1380                         this_controller,
1381                         completion_entry);
1382                 break;
1383
1384         case SCU_EVENT_TYPE_TRANSPORT_ERROR:
1385                 io_request = this_controller->io_request_table[index];
1386                 scic_sds_io_request_event_handler(io_request, completion_entry);
1387                 break;
1388
1389         case SCU_EVENT_TYPE_PTX_SCHEDULE_EVENT:
1390                 switch (scu_get_event_specifier(completion_entry)) {
1391                 case SCU_EVENT_SPECIFIC_SMP_RESPONSE_NO_PE:
1392                 case SCU_EVENT_SPECIFIC_TASK_TIMEOUT:
1393                         io_request = this_controller->io_request_table[index];
1394                         if (io_request != NULL)
1395                                 scic_sds_io_request_event_handler(io_request, completion_entry);
1396                         else
1397                                 dev_warn(scic_to_dev(this_controller),
1398                                          "%s: SCIC Controller 0x%p received "
1399                                          "event 0x%x for io request object "
1400                                          "that doesnt exist.\n",
1401                                          __func__,
1402                                          this_controller,
1403                                          completion_entry);
1404
1405                         break;
1406
1407                 case SCU_EVENT_SPECIFIC_IT_NEXUS_TIMEOUT:
1408                         device = this_controller->device_table[index];
1409                         if (device != NULL)
1410                                 scic_sds_remote_device_event_handler(device, completion_entry);
1411                         else
1412                                 dev_warn(scic_to_dev(this_controller),
1413                                          "%s: SCIC Controller 0x%p received "
1414                                          "event 0x%x for remote device object "
1415                                          "that doesnt exist.\n",
1416                                          __func__,
1417                                          this_controller,
1418                                          completion_entry);
1419
1420                         break;
1421                 }
1422                 break;
1423
1424         case SCU_EVENT_TYPE_BROADCAST_CHANGE:
1425         /*
1426          * direct the broadcast change event to the phy first and then let
1427          * the phy redirect the broadcast change to the port object */
1428         case SCU_EVENT_TYPE_ERR_CNT_EVENT:
1429         /*
1430          * direct error counter event to the phy object since that is where
1431          * we get the event notification.  This is a type 4 event. */
1432         case SCU_EVENT_TYPE_OSSP_EVENT:
1433                 index = SCU_GET_PROTOCOL_ENGINE_INDEX(completion_entry);
1434                 phy = &this_controller->phy_table[index];
1435                 scic_sds_phy_event_handler(phy, completion_entry);
1436                 break;
1437
1438         case SCU_EVENT_TYPE_RNC_SUSPEND_TX:
1439         case SCU_EVENT_TYPE_RNC_SUSPEND_TX_RX:
1440         case SCU_EVENT_TYPE_RNC_OPS_MISC:
1441                 if (index < this_controller->remote_node_entries) {
1442                         device = this_controller->device_table[index];
1443
1444                         if (device != NULL)
1445                                 scic_sds_remote_device_event_handler(device, completion_entry);
1446                 } else
1447                         dev_err(scic_to_dev(this_controller),
1448                                 "%s: SCIC Controller 0x%p received event 0x%x "
1449                                 "for remote device object 0x%0x that doesnt "
1450                                 "exist.\n",
1451                                 __func__,
1452                                 this_controller,
1453                                 completion_entry,
1454                                 index);
1455
1456                 break;
1457
1458         default:
1459                 dev_warn(scic_to_dev(this_controller),
1460                          "%s: SCIC Controller received unknown event code %x\n",
1461                          __func__,
1462                          completion_entry);
1463                 break;
1464         }
1465 }
1466
1467 /**
1468  * This method is a private routine for processing the completion queue entries.
1469  * @this_controller:
1470  *
1471  */
1472 static void scic_sds_controller_process_completions(
1473         struct scic_sds_controller *this_controller)
1474 {
1475         u32 completion_count = 0;
1476         u32 completion_entry;
1477         u32 get_index;
1478         u32 get_cycle;
1479         u32 event_index;
1480         u32 event_cycle;
1481
1482         dev_dbg(scic_to_dev(this_controller),
1483                 "%s: completion queue begining get:0x%08x\n",
1484                 __func__,
1485                 this_controller->completion_queue_get);
1486
1487         /* Get the component parts of the completion queue */
1488         get_index = NORMALIZE_GET_POINTER(this_controller->completion_queue_get);
1489         get_cycle = SMU_CQGR_CYCLE_BIT & this_controller->completion_queue_get;
1490
1491         event_index = NORMALIZE_EVENT_POINTER(this_controller->completion_queue_get);
1492         event_cycle = SMU_CQGR_EVENT_CYCLE_BIT & this_controller->completion_queue_get;
1493
1494         while (
1495                 NORMALIZE_GET_POINTER_CYCLE_BIT(get_cycle)
1496                 == COMPLETION_QUEUE_CYCLE_BIT(this_controller->completion_queue[get_index])
1497                 ) {
1498                 completion_count++;
1499
1500                 completion_entry = this_controller->completion_queue[get_index];
1501                 INCREMENT_COMPLETION_QUEUE_GET(this_controller, get_index, get_cycle);
1502
1503                 dev_dbg(scic_to_dev(this_controller),
1504                         "%s: completion queue entry:0x%08x\n",
1505                         __func__,
1506                         completion_entry);
1507
1508                 switch (SCU_GET_COMPLETION_TYPE(completion_entry)) {
1509                 case SCU_COMPLETION_TYPE_TASK:
1510                         scic_sds_controller_task_completion(this_controller, completion_entry);
1511                         break;
1512
1513                 case SCU_COMPLETION_TYPE_SDMA:
1514                         scic_sds_controller_sdma_completion(this_controller, completion_entry);
1515                         break;
1516
1517                 case SCU_COMPLETION_TYPE_UFI:
1518                         scic_sds_controller_unsolicited_frame(this_controller, completion_entry);
1519                         break;
1520
1521                 case SCU_COMPLETION_TYPE_EVENT:
1522                         INCREMENT_EVENT_QUEUE_GET(this_controller, event_index, event_cycle);
1523                         scic_sds_controller_event_completion(this_controller, completion_entry);
1524                         break;
1525
1526                 case SCU_COMPLETION_TYPE_NOTIFY:
1527                         /*
1528                          * Presently we do the same thing with a notify event that we do with the
1529                          * other event codes. */
1530                         INCREMENT_EVENT_QUEUE_GET(this_controller, event_index, event_cycle);
1531                         scic_sds_controller_event_completion(this_controller, completion_entry);
1532                         break;
1533
1534                 default:
1535                         dev_warn(scic_to_dev(this_controller),
1536                                  "%s: SCIC Controller received unknown "
1537                                  "completion type %x\n",
1538                                  __func__,
1539                                  completion_entry);
1540                         break;
1541                 }
1542         }
1543
1544         /* Update the get register if we completed one or more entries */
1545         if (completion_count > 0) {
1546                 this_controller->completion_queue_get =
1547                         SMU_CQGR_GEN_BIT(ENABLE)
1548                         | SMU_CQGR_GEN_BIT(EVENT_ENABLE)
1549                         | event_cycle | SMU_CQGR_GEN_VAL(EVENT_POINTER, event_index)
1550                         | get_cycle   | SMU_CQGR_GEN_VAL(POINTER, get_index);
1551
1552                 SMU_CQGR_WRITE(this_controller,
1553                                this_controller->completion_queue_get);
1554         }
1555
1556         dev_dbg(scic_to_dev(this_controller),
1557                 "%s: completion queue ending get:0x%08x\n",
1558                 __func__,
1559                 this_controller->completion_queue_get);
1560
1561 }
1562
1563 bool scic_sds_controller_isr(struct scic_sds_controller *scic)
1564 {
1565         if (scic_sds_controller_completion_queue_has_entries(scic)) {
1566                 return true;
1567         } else {
1568                 /*
1569                  * we have a spurious interrupt it could be that we have already
1570                  * emptied the completion queue from a previous interrupt */
1571                 SMU_ISR_WRITE(scic, SMU_ISR_COMPLETION);
1572
1573                 /*
1574                  * There is a race in the hardware that could cause us not to be notified
1575                  * of an interrupt completion if we do not take this step.  We will mask
1576                  * then unmask the interrupts so if there is another interrupt pending
1577                  * the clearing of the interrupt source we get the next interrupt message. */
1578                 SMU_IMR_WRITE(scic, 0xFF000000);
1579                 SMU_IMR_WRITE(scic, 0x00000000);
1580         }
1581
1582         return false;
1583 }
1584
1585 void scic_sds_controller_completion_handler(struct scic_sds_controller *scic)
1586 {
1587         /* Empty out the completion queue */
1588         if (scic_sds_controller_completion_queue_has_entries(scic))
1589                 scic_sds_controller_process_completions(scic);
1590
1591         /* Clear the interrupt and enable all interrupts again */
1592         SMU_ISR_WRITE(scic, SMU_ISR_COMPLETION);
1593         /* Could we write the value of SMU_ISR_COMPLETION? */
1594         SMU_IMR_WRITE(scic, 0xFF000000);
1595         SMU_IMR_WRITE(scic, 0x00000000);
1596 }
1597
1598 bool scic_sds_controller_error_isr(struct scic_sds_controller *scic)
1599 {
1600         u32 interrupt_status;
1601
1602         interrupt_status = SMU_ISR_READ(scic);
1603
1604         interrupt_status &= (SMU_ISR_QUEUE_ERROR | SMU_ISR_QUEUE_SUSPEND);
1605
1606         if (interrupt_status != 0) {
1607                 /*
1608                  * There is an error interrupt pending so let it through and handle
1609                  * in the callback */
1610                 return true;
1611         }
1612
1613         /*
1614          * There is a race in the hardware that could cause us not to be notified
1615          * of an interrupt completion if we do not take this step.  We will mask
1616          * then unmask the error interrupts so if there was another interrupt
1617          * pending we will be notified.
1618          * Could we write the value of (SMU_ISR_QUEUE_ERROR | SMU_ISR_QUEUE_SUSPEND)? */
1619         SMU_IMR_WRITE(scic, 0x000000FF);
1620         SMU_IMR_WRITE(scic, 0x00000000);
1621
1622         return false;
1623 }
1624
1625 void scic_sds_controller_error_handler(struct scic_sds_controller *scic)
1626 {
1627         u32 interrupt_status;
1628
1629         interrupt_status = SMU_ISR_READ(scic);
1630
1631         if ((interrupt_status & SMU_ISR_QUEUE_SUSPEND) &&
1632             scic_sds_controller_completion_queue_has_entries(scic)) {
1633
1634                 scic_sds_controller_process_completions(scic);
1635                 SMU_ISR_WRITE(scic, SMU_ISR_QUEUE_SUSPEND);
1636
1637         } else {
1638                 dev_err(scic_to_dev(scic), "%s: status: %#x\n", __func__,
1639                         interrupt_status);
1640
1641                 sci_base_state_machine_change_state(
1642                         scic_sds_controller_get_base_state_machine(scic),
1643                         SCI_BASE_CONTROLLER_STATE_FAILED);
1644
1645                 return;
1646         }
1647
1648         /*
1649          * If we dont process any completions I am not sure that we want to do this.
1650          * We are in the middle of a hardware fault and should probably be reset. */
1651         SMU_IMR_WRITE(scic, 0x00000000);
1652 }
1653
1654
1655 u32 scic_sds_controller_get_object_size(void)
1656 {
1657         return sizeof(struct scic_sds_controller);
1658 }
1659
1660
1661 void scic_sds_controller_link_up(
1662         struct scic_sds_controller *scic,
1663         struct scic_sds_port *sci_port,
1664         struct scic_sds_phy *sci_phy)
1665 {
1666         scic_sds_controller_phy_handler_t link_up;
1667         u32 state;
1668
1669         state = scic->parent.state_machine.current_state_id;
1670         link_up = scic_sds_controller_state_handler_table[state].link_up;
1671
1672         if (link_up)
1673                 link_up(scic, sci_port, sci_phy);
1674         else
1675                 dev_dbg(scic_to_dev(scic),
1676                         "%s: SCIC Controller linkup event from phy %d in "
1677                         "unexpected state %d\n",
1678                         __func__,
1679                         sci_phy->phy_index,
1680                         sci_base_state_machine_get_state(
1681                                 scic_sds_controller_get_base_state_machine(
1682                                         scic)));
1683 }
1684
1685
1686 void scic_sds_controller_link_down(
1687         struct scic_sds_controller *scic,
1688         struct scic_sds_port *sci_port,
1689         struct scic_sds_phy *sci_phy)
1690 {
1691         u32 state;
1692         scic_sds_controller_phy_handler_t link_down;
1693
1694         state = scic->parent.state_machine.current_state_id;
1695         link_down = scic_sds_controller_state_handler_table[state].link_down;
1696
1697         if (link_down)
1698                 link_down(scic, sci_port, sci_phy);
1699         else
1700                 dev_dbg(scic_to_dev(scic),
1701                         "%s: SCIC Controller linkdown event from phy %d in "
1702                         "unexpected state %d\n",
1703                         __func__,
1704                         sci_phy->phy_index, state);
1705 }
1706
1707 /**
1708  * This method is called by the remote device to inform the controller
1709  * that this remote device has started.
1710  *
1711  */
1712
1713 void scic_sds_controller_remote_device_started(struct scic_sds_controller *scic,
1714                                                struct scic_sds_remote_device *sci_dev)
1715 {
1716         u32 state;
1717         scic_sds_controller_device_handler_t started;
1718
1719         state = scic->parent.state_machine.current_state_id;
1720         started = scic_sds_controller_state_handler_table[state].remote_device_started_handler;
1721
1722         if (started)
1723                 started(scic, sci_dev);
1724         else {
1725                 dev_dbg(scic_to_dev(scic),
1726                          "%s: SCIC Controller 0x%p remote device started event "
1727                          "from device 0x%p in unexpected state  %d\n",
1728                          __func__, scic, sci_dev, state);
1729         }
1730 }
1731
1732 /**
1733  * This is a helper method to determine if any remote devices on this
1734  * controller are still in the stopping state.
1735  *
1736  */
1737 bool scic_sds_controller_has_remote_devices_stopping(
1738         struct scic_sds_controller *this_controller)
1739 {
1740         u32 index;
1741
1742         for (index = 0; index < this_controller->remote_node_entries; index++) {
1743                 if ((this_controller->device_table[index] != NULL) &&
1744                    (this_controller->device_table[index]->parent.state_machine.current_state_id
1745                     == SCI_BASE_REMOTE_DEVICE_STATE_STOPPING))
1746                         return true;
1747         }
1748
1749         return false;
1750 }
1751
1752 /**
1753  * This method is called by the remote device to inform the controller
1754  * object that the remote device has stopped.
1755  *
1756  */
1757
1758 void scic_sds_controller_remote_device_stopped(struct scic_sds_controller *scic,
1759                                                struct scic_sds_remote_device *sci_dev)
1760 {
1761
1762         u32 state;
1763         scic_sds_controller_device_handler_t stopped;
1764
1765         state = scic->parent.state_machine.current_state_id;
1766         stopped = scic_sds_controller_state_handler_table[state].remote_device_stopped_handler;
1767
1768         if (stopped)
1769                 stopped(scic, sci_dev);
1770         else {
1771                 dev_dbg(scic_to_dev(scic),
1772                         "%s: SCIC Controller 0x%p remote device stopped event "
1773                         "from device 0x%p in unexpected state  %d\n",
1774                         __func__, scic, sci_dev, state);
1775         }
1776 }
1777
1778
1779
1780 /**
1781  * This method will write to the SCU PCP register the request value. The method
1782  *    is used to suspend/resume ports, devices, and phys.
1783  * @this_controller:
1784  *
1785  *
1786  */
1787 void scic_sds_controller_post_request(
1788         struct scic_sds_controller *this_controller,
1789         u32 request)
1790 {
1791         dev_dbg(scic_to_dev(this_controller),
1792                 "%s: SCIC Controller 0x%p post request 0x%08x\n",
1793                 __func__,
1794                 this_controller,
1795                 request);
1796
1797         SMU_PCP_WRITE(this_controller, request);
1798 }
1799
1800 /**
1801  * This method will copy the soft copy of the task context into the physical
1802  *    memory accessible by the controller.
1803  * @this_controller: This parameter specifies the controller for which to copy
1804  *    the task context.
1805  * @this_request: This parameter specifies the request for which the task
1806  *    context is being copied.
1807  *
1808  * After this call is made the SCIC_SDS_IO_REQUEST object will always point to
1809  * the physical memory version of the task context. Thus, all subsequent
1810  * updates to the task context are performed in the TC table (i.e. DMAable
1811  * memory). none
1812  */
1813 void scic_sds_controller_copy_task_context(
1814         struct scic_sds_controller *this_controller,
1815         struct scic_sds_request *this_request)
1816 {
1817         struct scu_task_context *task_context_buffer;
1818
1819         task_context_buffer = scic_sds_controller_get_task_context_buffer(
1820                 this_controller, this_request->io_tag
1821                 );
1822
1823         memcpy(
1824                 task_context_buffer,
1825                 this_request->task_context_buffer,
1826                 SCI_FIELD_OFFSET(struct scu_task_context, sgl_snapshot_ac)
1827                 );
1828
1829         /*
1830          * Now that the soft copy of the TC has been copied into the TC
1831          * table accessible by the silicon.  Thus, any further changes to
1832          * the TC (e.g. TC termination) occur in the appropriate location. */
1833         this_request->task_context_buffer = task_context_buffer;
1834 }
1835
1836 /**
1837  * This method returns the task context buffer for the given io tag.
1838  * @this_controller:
1839  * @io_tag:
1840  *
1841  * struct scu_task_context*
1842  */
1843 struct scu_task_context *scic_sds_controller_get_task_context_buffer(
1844         struct scic_sds_controller *this_controller,
1845         u16 io_tag
1846         ) {
1847         u16 task_index = scic_sds_io_tag_get_index(io_tag);
1848
1849         if (task_index < this_controller->task_context_entries) {
1850                 return &this_controller->task_context_table[task_index];
1851         }
1852
1853         return NULL;
1854 }
1855
1856 /**
1857  * This method returnst the sequence value from the io tag value
1858  * @this_controller:
1859  * @io_tag:
1860  *
1861  * u16
1862  */
1863
1864 /**
1865  * This method returns the IO request associated with the tag value
1866  * @this_controller:
1867  * @io_tag:
1868  *
1869  * SCIC_SDS_IO_REQUEST_T* NULL if there is no valid IO request at the tag value
1870  */
1871 struct scic_sds_request *scic_sds_controller_get_io_request_from_tag(
1872         struct scic_sds_controller *this_controller,
1873         u16 io_tag
1874         ) {
1875         u16 task_index;
1876         u16 task_sequence;
1877
1878         task_index = scic_sds_io_tag_get_index(io_tag);
1879
1880         if (task_index  < this_controller->task_context_entries) {
1881                 if (this_controller->io_request_table[task_index] != NULL) {
1882                         task_sequence = scic_sds_io_tag_get_sequence(io_tag);
1883
1884                         if (task_sequence == this_controller->io_request_sequence[task_index]) {
1885                                 return this_controller->io_request_table[task_index];
1886                         }
1887                 }
1888         }
1889
1890         return NULL;
1891 }
1892
1893 /**
1894  * This method allocates remote node index and the reserves the remote node
1895  *    context space for use. This method can fail if there are no more remote
1896  *    node index available.
1897  * @this_controller: This is the controller object which contains the set of
1898  *    free remote node ids
1899  * @the_devce: This is the device object which is requesting the a remote node
1900  *    id
1901  * @node_id: This is the remote node id that is assinged to the device if one
1902  *    is available
1903  *
1904  * enum sci_status SCI_FAILURE_OUT_OF_RESOURCES if there are no available remote
1905  * node index available.
1906  */
1907 enum sci_status scic_sds_controller_allocate_remote_node_context(
1908         struct scic_sds_controller *this_controller,
1909         struct scic_sds_remote_device *the_device,
1910         u16 *node_id)
1911 {
1912         u16 node_index;
1913         u32 remote_node_count = scic_sds_remote_device_node_count(the_device);
1914
1915         node_index = scic_sds_remote_node_table_allocate_remote_node(
1916                 &this_controller->available_remote_nodes, remote_node_count
1917                 );
1918
1919         if (node_index != SCIC_SDS_REMOTE_NODE_CONTEXT_INVALID_INDEX) {
1920                 this_controller->device_table[node_index] = the_device;
1921
1922                 *node_id = node_index;
1923
1924                 return SCI_SUCCESS;
1925         }
1926
1927         return SCI_FAILURE_INSUFFICIENT_RESOURCES;
1928 }
1929
1930 /**
1931  * This method frees the remote node index back to the available pool.  Once
1932  *    this is done the remote node context buffer is no longer valid and can
1933  *    not be used.
1934  * @this_controller:
1935  * @the_device:
1936  * @node_id:
1937  *
1938  */
1939 void scic_sds_controller_free_remote_node_context(
1940         struct scic_sds_controller *this_controller,
1941         struct scic_sds_remote_device *the_device,
1942         u16 node_id)
1943 {
1944         u32 remote_node_count = scic_sds_remote_device_node_count(the_device);
1945
1946         if (this_controller->device_table[node_id] == the_device) {
1947                 this_controller->device_table[node_id] = NULL;
1948
1949                 scic_sds_remote_node_table_release_remote_node_index(
1950                         &this_controller->available_remote_nodes, remote_node_count, node_id
1951                         );
1952         }
1953 }
1954
1955 /**
1956  * This method returns the union scu_remote_node_context for the specified remote
1957  *    node id.
1958  * @this_controller:
1959  * @node_id:
1960  *
1961  * union scu_remote_node_context*
1962  */
1963 union scu_remote_node_context *scic_sds_controller_get_remote_node_context_buffer(
1964         struct scic_sds_controller *this_controller,
1965         u16 node_id
1966         ) {
1967         if (
1968                 (node_id < this_controller->remote_node_entries)
1969                 && (this_controller->device_table[node_id] != NULL)
1970                 ) {
1971                 return &this_controller->remote_node_context_table[node_id];
1972         }
1973
1974         return NULL;
1975 }
1976
1977 /**
1978  *
1979  * @resposne_buffer: This is the buffer into which the D2H register FIS will be
1980  *    constructed.
1981  * @frame_header: This is the frame header returned by the hardware.
1982  * @frame_buffer: This is the frame buffer returned by the hardware.
1983  *
1984  * This method will combind the frame header and frame buffer to create a SATA
1985  * D2H register FIS none
1986  */
1987 void scic_sds_controller_copy_sata_response(
1988         void *response_buffer,
1989         void *frame_header,
1990         void *frame_buffer)
1991 {
1992         memcpy(
1993                 response_buffer,
1994                 frame_header,
1995                 sizeof(u32)
1996                 );
1997
1998         memcpy(
1999                 (char *)((char *)response_buffer + sizeof(u32)),
2000                 frame_buffer,
2001                 sizeof(struct sata_fis_reg_d2h) - sizeof(u32)
2002                 );
2003 }
2004
2005 /**
2006  * This method releases the frame once this is done the frame is available for
2007  *    re-use by the hardware.  The data contained in the frame header and frame
2008  *    buffer is no longer valid. The UF queue get pointer is only updated if UF
2009  *    control indicates this is appropriate.
2010  * @this_controller:
2011  * @frame_index:
2012  *
2013  */
2014 void scic_sds_controller_release_frame(
2015         struct scic_sds_controller *this_controller,
2016         u32 frame_index)
2017 {
2018         if (scic_sds_unsolicited_frame_control_release_frame(
2019                     &this_controller->uf_control, frame_index) == true)
2020                 SCU_UFQGP_WRITE(this_controller, this_controller->uf_control.get);
2021 }
2022
2023 /**
2024  * This method sets user parameters and OEM parameters to default values.
2025  *    Users can override these values utilizing the scic_user_parameters_set()
2026  *    and scic_oem_parameters_set() methods.
2027  * @scic: This parameter specifies the controller for which to set the
2028  *    configuration parameters to their default values.
2029  *
2030  */
2031 static void scic_sds_controller_set_default_config_parameters(struct scic_sds_controller *scic)
2032 {
2033         struct isci_host *ihost = sci_object_get_association(scic);
2034         u16 index;
2035
2036         /* Default to APC mode. */
2037         scic->oem_parameters.sds1.controller.mode_type = SCIC_PORT_AUTOMATIC_CONFIGURATION_MODE;
2038
2039         /* Default to APC mode. */
2040         scic->oem_parameters.sds1.controller.max_concurrent_dev_spin_up = 1;
2041
2042         /* Default to no SSC operation. */
2043         scic->oem_parameters.sds1.controller.do_enable_ssc = false;
2044
2045         /* Initialize all of the port parameter information to narrow ports. */
2046         for (index = 0; index < SCI_MAX_PORTS; index++) {
2047                 scic->oem_parameters.sds1.ports[index].phy_mask = 0;
2048         }
2049
2050         /* Initialize all of the phy parameter information. */
2051         for (index = 0; index < SCI_MAX_PHYS; index++) {
2052                 /* Default to 6G (i.e. Gen 3) for now. */
2053                 scic->user_parameters.sds1.phys[index].max_speed_generation = 3;
2054
2055                 /* the frequencies cannot be 0 */
2056                 scic->user_parameters.sds1.phys[index].align_insertion_frequency = 0x7f;
2057                 scic->user_parameters.sds1.phys[index].in_connection_align_insertion_frequency = 0xff;
2058                 scic->user_parameters.sds1.phys[index].notify_enable_spin_up_insertion_frequency = 0x33;
2059
2060                 /*
2061                  * Previous Vitesse based expanders had a arbitration issue that
2062                  * is worked around by having the upper 32-bits of SAS address
2063                  * with a value greater then the Vitesse company identifier.
2064                  * Hence, usage of 0x5FCFFFFF. */
2065                 scic->oem_parameters.sds1.phys[index].sas_address.low = 0x1 + ihost->id;
2066                 scic->oem_parameters.sds1.phys[index].sas_address.high = 0x5FCFFFFF;
2067         }
2068
2069         scic->user_parameters.sds1.stp_inactivity_timeout = 5;
2070         scic->user_parameters.sds1.ssp_inactivity_timeout = 5;
2071         scic->user_parameters.sds1.stp_max_occupancy_timeout = 5;
2072         scic->user_parameters.sds1.ssp_max_occupancy_timeout = 20;
2073         scic->user_parameters.sds1.no_outbound_task_timeout = 20;
2074 }
2075
2076
2077 enum sci_status scic_controller_construct(struct scic_sds_controller *controller,
2078                                           void __iomem *scu_base,
2079                                           void __iomem *smu_base)
2080 {
2081         u8 index;
2082
2083         sci_base_controller_construct(
2084                 &controller->parent,
2085                 scic_sds_controller_state_table,
2086                 controller->memory_descriptors,
2087                 ARRAY_SIZE(controller->memory_descriptors),
2088                 NULL
2089                 );
2090
2091         controller->scu_registers = scu_base;
2092         controller->smu_registers = smu_base;
2093
2094         scic_sds_port_configuration_agent_construct(&controller->port_agent);
2095
2096         /* Construct the ports for this controller */
2097         for (index = 0; index < SCI_MAX_PORTS; index++)
2098                 scic_sds_port_construct(&controller->port_table[index],
2099                                         index, controller);
2100         scic_sds_port_construct(&controller->port_table[index],
2101                                 SCIC_SDS_DUMMY_PORT, controller);
2102
2103         /* Construct the phys for this controller */
2104         for (index = 0; index < SCI_MAX_PHYS; index++) {
2105                 /* Add all the PHYs to the dummy port */
2106                 scic_sds_phy_construct(
2107                         &controller->phy_table[index],
2108                         &controller->port_table[SCI_MAX_PORTS],
2109                         index
2110                         );
2111         }
2112
2113         controller->invalid_phy_mask = 0;
2114
2115         /* Set the default maximum values */
2116         controller->completion_event_entries      = SCU_EVENT_COUNT;
2117         controller->completion_queue_entries      = SCU_COMPLETION_QUEUE_COUNT;
2118         controller->remote_node_entries           = SCI_MAX_REMOTE_DEVICES;
2119         controller->logical_port_entries          = SCI_MAX_PORTS;
2120         controller->task_context_entries          = SCU_IO_REQUEST_COUNT;
2121         controller->uf_control.buffers.count      = SCU_UNSOLICITED_FRAME_COUNT;
2122         controller->uf_control.address_table.count = SCU_UNSOLICITED_FRAME_COUNT;
2123
2124         /* Initialize the User and OEM parameters to default values. */
2125         scic_sds_controller_set_default_config_parameters(controller);
2126
2127         return scic_controller_reset(controller);
2128 }
2129
2130 /* --------------------------------------------------------------------------- */
2131
2132 enum sci_status scic_controller_initialize(
2133         struct scic_sds_controller *scic)
2134 {
2135         enum sci_status status = SCI_FAILURE_INVALID_STATE;
2136         sci_base_controller_handler_t initialize;
2137         u32 state;
2138
2139         state = scic->parent.state_machine.current_state_id;
2140         initialize = scic_sds_controller_state_handler_table[state].base.initialize;
2141
2142         if (initialize)
2143                 status = initialize(&scic->parent);
2144         else
2145                 dev_warn(scic_to_dev(scic),
2146                          "%s: SCIC Controller initialize operation requested "
2147                          "in invalid state %d\n",
2148                          __func__,
2149                          sci_base_state_machine_get_state(
2150                                  scic_sds_controller_get_base_state_machine(
2151                                          scic)));
2152
2153         return status;
2154 }
2155
2156 /* --------------------------------------------------------------------------- */
2157
2158 u32 scic_controller_get_suggested_start_timeout(
2159         struct scic_sds_controller *sc)
2160 {
2161         /* Validate the user supplied parameters. */
2162         if (sc == NULL)
2163                 return 0;
2164
2165         /*
2166          * The suggested minimum timeout value for a controller start operation:
2167          *
2168          *     Signature FIS Timeout
2169          *   + Phy Start Timeout
2170          *   + Number of Phy Spin Up Intervals
2171          *   ---------------------------------
2172          *   Number of milliseconds for the controller start operation.
2173          *
2174          * NOTE: The number of phy spin up intervals will be equivalent
2175          *       to the number of phys divided by the number phys allowed
2176          *       per interval - 1 (once OEM parameters are supported).
2177          *       Currently we assume only 1 phy per interval. */
2178
2179         return SCIC_SDS_SIGNATURE_FIS_TIMEOUT
2180                 + SCIC_SDS_CONTROLLER_PHY_START_TIMEOUT
2181                 + ((SCI_MAX_PHYS - 1) * SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL);
2182 }
2183
2184 /* --------------------------------------------------------------------------- */
2185
2186 enum sci_status scic_controller_start(
2187         struct scic_sds_controller *scic,
2188         u32 timeout)
2189 {
2190         enum sci_status status = SCI_FAILURE_INVALID_STATE;
2191         sci_base_controller_timed_handler_t start;
2192         u32 state;
2193
2194         state = scic->parent.state_machine.current_state_id;
2195         start = scic_sds_controller_state_handler_table[state].base.start;
2196
2197         if (start)
2198                 status = start(&scic->parent, timeout);
2199         else
2200                 dev_warn(scic_to_dev(scic),
2201                          "%s: SCIC Controller start operation requested in "
2202                          "invalid state %d\n",
2203                          __func__,
2204                          sci_base_state_machine_get_state(
2205                                  scic_sds_controller_get_base_state_machine(
2206                                          scic)));
2207
2208         return status;
2209 }
2210
2211 /* --------------------------------------------------------------------------- */
2212
2213 enum sci_status scic_controller_stop(
2214         struct scic_sds_controller *scic,
2215         u32 timeout)
2216 {
2217         enum sci_status status = SCI_FAILURE_INVALID_STATE;
2218         sci_base_controller_timed_handler_t stop;
2219         u32 state;
2220
2221         state = scic->parent.state_machine.current_state_id;
2222         stop = scic_sds_controller_state_handler_table[state].base.stop;
2223
2224         if (stop)
2225                 status = stop(&scic->parent, timeout);
2226         else
2227                 dev_warn(scic_to_dev(scic),
2228                          "%s: SCIC Controller stop operation requested in "
2229                          "invalid state %d\n",
2230                          __func__,
2231                          sci_base_state_machine_get_state(
2232                                  scic_sds_controller_get_base_state_machine(
2233                                          scic)));
2234
2235         return status;
2236 }
2237
2238 /* --------------------------------------------------------------------------- */
2239
2240 enum sci_status scic_controller_reset(
2241         struct scic_sds_controller *scic)
2242 {
2243         enum sci_status status = SCI_FAILURE_INVALID_STATE;
2244         sci_base_controller_handler_t reset;
2245         u32 state;
2246
2247         state = scic->parent.state_machine.current_state_id;
2248         reset = scic_sds_controller_state_handler_table[state].base.reset;
2249
2250         if (reset)
2251                 status = reset(&scic->parent);
2252         else
2253                 dev_warn(scic_to_dev(scic),
2254                          "%s: SCIC Controller reset operation requested in "
2255                          "invalid state %d\n",
2256                          __func__,
2257                          sci_base_state_machine_get_state(
2258                                  scic_sds_controller_get_base_state_machine(
2259                                          scic)));
2260
2261         return status;
2262 }
2263
2264 enum sci_io_status scic_controller_start_io(
2265         struct scic_sds_controller *scic,
2266         struct scic_sds_remote_device *remote_device,
2267         struct scic_sds_request *io_request,
2268         u16 io_tag)
2269 {
2270         u32 state;
2271         sci_base_controller_start_request_handler_t start_io;
2272
2273         state = scic->parent.state_machine.current_state_id;
2274         start_io = scic_sds_controller_state_handler_table[state].base.start_io;
2275
2276         return start_io(&scic->parent,
2277                         (struct sci_base_remote_device *) remote_device,
2278                         (struct sci_base_request *)io_request, io_tag);
2279 }
2280
2281 /* --------------------------------------------------------------------------- */
2282
2283 enum sci_status scic_controller_terminate_request(
2284         struct scic_sds_controller *scic,
2285         struct scic_sds_remote_device *remote_device,
2286         struct scic_sds_request *request)
2287 {
2288         sci_base_controller_request_handler_t terminate_request;
2289         u32 state;
2290
2291         state = scic->parent.state_machine.current_state_id;
2292         terminate_request = scic_sds_controller_state_handler_table[state].terminate_request;
2293
2294         return terminate_request(&scic->parent,
2295                                  (struct sci_base_remote_device *)remote_device,
2296                                  (struct sci_base_request *)request);
2297 }
2298
2299 /* --------------------------------------------------------------------------- */
2300
2301 enum sci_status scic_controller_complete_io(
2302         struct scic_sds_controller *scic,
2303         struct scic_sds_remote_device *remote_device,
2304         struct scic_sds_request *io_request)
2305 {
2306         u32 state;
2307         sci_base_controller_request_handler_t complete_io;
2308
2309         state = scic->parent.state_machine.current_state_id;
2310         complete_io = scic_sds_controller_state_handler_table[state].base.complete_io;
2311
2312         return complete_io(&scic->parent,
2313                            (struct sci_base_remote_device *)remote_device,
2314                            (struct sci_base_request *)io_request);
2315 }
2316
2317 /* --------------------------------------------------------------------------- */
2318
2319
2320 enum sci_task_status scic_controller_start_task(
2321         struct scic_sds_controller *scic,
2322         struct scic_sds_remote_device *remote_device,
2323         struct scic_sds_request *task_request,
2324         u16 task_tag)
2325 {
2326         u32 state;
2327         sci_base_controller_start_request_handler_t start_task;
2328         enum sci_task_status status = SCI_TASK_FAILURE_INVALID_STATE;
2329
2330         state = scic->parent.state_machine.current_state_id;
2331         start_task = scic_sds_controller_state_handler_table[state].base.start_task;
2332
2333         if (start_task)
2334                 status = start_task(&scic->parent,
2335                                     (struct sci_base_remote_device *)remote_device,
2336                                     (struct sci_base_request *)task_request,
2337                                     task_tag);
2338         else
2339                 dev_warn(scic_to_dev(scic),
2340                          "%s: SCIC Controller starting task from invalid "
2341                          "state\n",
2342                          __func__);
2343
2344         return status;
2345 }
2346
2347 /* --------------------------------------------------------------------------- */
2348
2349 enum sci_status scic_controller_complete_task(
2350         struct scic_sds_controller *scic,
2351         struct scic_sds_remote_device *remote_device,
2352         struct scic_sds_request *task_request)
2353 {
2354         u32 state;
2355         sci_base_controller_request_handler_t complete_task;
2356         enum sci_status status = SCI_FAILURE_INVALID_STATE;
2357
2358         state = scic->parent.state_machine.current_state_id;
2359         complete_task = scic_sds_controller_state_handler_table[state].base.complete_task;
2360
2361         if (complete_task)
2362                 status = complete_task(&scic->parent,
2363                                        (struct sci_base_remote_device *)remote_device,
2364                                        (struct sci_base_request *)task_request);
2365         else
2366                 dev_warn(scic_to_dev(scic),
2367                          "%s: SCIC Controller completing task from invalid "
2368                          "state\n",
2369                          __func__);
2370
2371         return status;
2372 }
2373
2374
2375 /* --------------------------------------------------------------------------- */
2376
2377 enum sci_status scic_controller_get_port_handle(
2378         struct scic_sds_controller *scic,
2379         u8 port_index,
2380         struct scic_sds_port **port_handle)
2381 {
2382         if (port_index < scic->logical_port_entries) {
2383                 *port_handle = &scic->port_table[port_index];
2384
2385                 return SCI_SUCCESS;
2386         }
2387
2388         return SCI_FAILURE_INVALID_PORT;
2389 }
2390
2391 /* --------------------------------------------------------------------------- */
2392
2393 enum sci_status scic_controller_get_phy_handle(
2394         struct scic_sds_controller *scic,
2395         u8 phy_index,
2396         struct scic_sds_phy **phy_handle)
2397 {
2398         if (phy_index < ARRAY_SIZE(scic->phy_table)) {
2399                 *phy_handle = &scic->phy_table[phy_index];
2400
2401                 return SCI_SUCCESS;
2402         }
2403
2404         dev_err(scic_to_dev(scic),
2405                 "%s: Controller:0x%p PhyId:0x%x invalid phy index\n",
2406                 __func__, scic, phy_index);
2407
2408         return SCI_FAILURE_INVALID_PHY;
2409 }
2410
2411 /* --------------------------------------------------------------------------- */
2412
2413 u16 scic_controller_allocate_io_tag(
2414         struct scic_sds_controller *scic)
2415 {
2416         u16 task_context;
2417         u16 sequence_count;
2418
2419         if (!sci_pool_empty(scic->tci_pool)) {
2420                 sci_pool_get(scic->tci_pool, task_context);
2421
2422                 sequence_count = scic->io_request_sequence[task_context];
2423
2424                 return scic_sds_io_tag_construct(sequence_count, task_context);
2425         }
2426
2427         return SCI_CONTROLLER_INVALID_IO_TAG;
2428 }
2429
2430 /* --------------------------------------------------------------------------- */
2431
2432 enum sci_status scic_controller_free_io_tag(
2433         struct scic_sds_controller *scic,
2434         u16 io_tag)
2435 {
2436         u16 sequence;
2437         u16 index;
2438
2439         BUG_ON(io_tag == SCI_CONTROLLER_INVALID_IO_TAG);
2440
2441         sequence = scic_sds_io_tag_get_sequence(io_tag);
2442         index    = scic_sds_io_tag_get_index(io_tag);
2443
2444         if (!sci_pool_full(scic->tci_pool)) {
2445                 if (sequence == scic->io_request_sequence[index]) {
2446                         scic_sds_io_sequence_increment(
2447                                 scic->io_request_sequence[index]);
2448
2449                         sci_pool_put(scic->tci_pool, index);
2450
2451                         return SCI_SUCCESS;
2452                 }
2453         }
2454
2455         return SCI_FAILURE_INVALID_IO_TAG;
2456 }
2457
2458 /* --------------------------------------------------------------------------- */
2459
2460 void scic_controller_enable_interrupts(
2461         struct scic_sds_controller *scic)
2462 {
2463         BUG_ON(scic->smu_registers == NULL);
2464         SMU_IMR_WRITE(scic, 0x00000000);
2465 }
2466
2467 /* --------------------------------------------------------------------------- */
2468
2469 void scic_controller_disable_interrupts(
2470         struct scic_sds_controller *scic)
2471 {
2472         BUG_ON(scic->smu_registers == NULL);
2473         SMU_IMR_WRITE(scic, 0xffffffff);
2474 }
2475
2476 /* --------------------------------------------------------------------------- */
2477
2478 enum sci_status scic_controller_set_mode(
2479         struct scic_sds_controller *scic,
2480         enum sci_controller_mode operating_mode)
2481 {
2482         enum sci_status status          = SCI_SUCCESS;
2483
2484         if ((scic->parent.state_machine.current_state_id ==
2485                                 SCI_BASE_CONTROLLER_STATE_INITIALIZING) ||
2486             (scic->parent.state_machine.current_state_id ==
2487                                 SCI_BASE_CONTROLLER_STATE_INITIALIZED)) {
2488                 switch (operating_mode) {
2489                 case SCI_MODE_SPEED:
2490                         scic->remote_node_entries      = SCI_MAX_REMOTE_DEVICES;
2491                         scic->task_context_entries     = SCU_IO_REQUEST_COUNT;
2492                         scic->uf_control.buffers.count =
2493                                 SCU_UNSOLICITED_FRAME_COUNT;
2494                         scic->completion_event_entries = SCU_EVENT_COUNT;
2495                         scic->completion_queue_entries =
2496                                 SCU_COMPLETION_QUEUE_COUNT;
2497                         scic_sds_controller_build_memory_descriptor_table(scic);
2498                         break;
2499
2500                 case SCI_MODE_SIZE:
2501                         scic->remote_node_entries      = SCI_MIN_REMOTE_DEVICES;
2502                         scic->task_context_entries     = SCI_MIN_IO_REQUESTS;
2503                         scic->uf_control.buffers.count =
2504                                 SCU_MIN_UNSOLICITED_FRAMES;
2505                         scic->completion_event_entries = SCU_MIN_EVENTS;
2506                         scic->completion_queue_entries =
2507                                 SCU_MIN_COMPLETION_QUEUE_ENTRIES;
2508                         scic_sds_controller_build_memory_descriptor_table(scic);
2509                         break;
2510
2511                 default:
2512                         status = SCI_FAILURE_INVALID_PARAMETER_VALUE;
2513                         break;
2514                 }
2515         } else
2516                 status = SCI_FAILURE_INVALID_STATE;
2517
2518         return status;
2519 }
2520
2521 /**
2522  * scic_sds_controller_reset_hardware() -
2523  *
2524  * This method will reset the controller hardware.
2525  */
2526 void scic_sds_controller_reset_hardware(
2527         struct scic_sds_controller *scic)
2528 {
2529         /* Disable interrupts so we dont take any spurious interrupts */
2530         scic_controller_disable_interrupts(scic);
2531
2532         /* Reset the SCU */
2533         SMU_SMUSRCR_WRITE(scic, 0xFFFFFFFF);
2534
2535         /* Delay for 1ms to before clearing the CQP and UFQPR. */
2536         udelay(1000);
2537
2538         /* The write to the CQGR clears the CQP */
2539         SMU_CQGR_WRITE(scic, 0x00000000);
2540
2541         /* The write to the UFQGP clears the UFQPR */
2542         SCU_UFQGP_WRITE(scic, 0x00000000);
2543 }
2544
2545 /* --------------------------------------------------------------------------- */
2546
2547 enum sci_status scic_user_parameters_set(
2548         struct scic_sds_controller *scic,
2549         union scic_user_parameters *scic_parms)
2550 {
2551         if (
2552                 (scic->parent.state_machine.current_state_id
2553                  == SCI_BASE_CONTROLLER_STATE_RESET)
2554                 || (scic->parent.state_machine.current_state_id
2555                     == SCI_BASE_CONTROLLER_STATE_INITIALIZING)
2556                 || (scic->parent.state_machine.current_state_id
2557                     == SCI_BASE_CONTROLLER_STATE_INITIALIZED)
2558                 ) {
2559                 u16 index;
2560
2561                 /*
2562                  * Validate the user parameters.  If they are not legal, then
2563                  * return a failure. */
2564                 for (index = 0; index < SCI_MAX_PHYS; index++) {
2565                         if (!(scic_parms->sds1.phys[index].max_speed_generation
2566                              <= SCIC_SDS_PARM_MAX_SPEED
2567                              && scic_parms->sds1.phys[index].max_speed_generation
2568                              > SCIC_SDS_PARM_NO_SPEED))
2569                                 return SCI_FAILURE_INVALID_PARAMETER_VALUE;
2570
2571                         if (scic_parms->sds1.phys[index].in_connection_align_insertion_frequency < 3)
2572                                 return SCI_FAILURE_INVALID_PARAMETER_VALUE;
2573                         if (
2574                             (scic_parms->sds1.phys[index].in_connection_align_insertion_frequency < 3) ||
2575                             (scic_parms->sds1.phys[index].align_insertion_frequency == 0) ||
2576                             (scic_parms->sds1.phys[index].notify_enable_spin_up_insertion_frequency == 0)
2577                             )
2578                                 return SCI_FAILURE_INVALID_PARAMETER_VALUE;
2579                 }
2580
2581                 if ((scic_parms->sds1.stp_inactivity_timeout == 0) ||
2582                    (scic_parms->sds1.ssp_inactivity_timeout == 0) ||
2583                    (scic_parms->sds1.stp_max_occupancy_timeout == 0) ||
2584                    (scic_parms->sds1.ssp_max_occupancy_timeout == 0) ||
2585                    (scic_parms->sds1.no_outbound_task_timeout == 0))
2586                         return SCI_FAILURE_INVALID_PARAMETER_VALUE;
2587
2588                 memcpy(&scic->user_parameters, scic_parms, sizeof(*scic_parms));
2589
2590                 return SCI_SUCCESS;
2591         }
2592
2593         return SCI_FAILURE_INVALID_STATE;
2594 }
2595
2596 /* --------------------------------------------------------------------------- */
2597
2598 void scic_user_parameters_get(
2599         struct scic_sds_controller *scic,
2600         union scic_user_parameters *scic_parms)
2601 {
2602         memcpy(scic_parms, (&scic->user_parameters), sizeof(*scic_parms));
2603 }
2604
2605 /* --------------------------------------------------------------------------- */
2606
2607 enum sci_status scic_oem_parameters_set(
2608         struct scic_sds_controller *scic,
2609         union scic_oem_parameters *scic_parms)
2610 {
2611         u32 state = scic->parent.state_machine.current_state_id;
2612
2613         if (state == SCI_BASE_CONTROLLER_STATE_RESET ||
2614             state == SCI_BASE_CONTROLLER_STATE_INITIALIZING ||
2615             state == SCI_BASE_CONTROLLER_STATE_INITIALIZED) {
2616                 u16 index;
2617                 u8  combined_phy_mask = 0;
2618
2619                 /*
2620                  * Validate the oem parameters.  If they are not legal, then
2621                  * return a failure. */
2622                 for (index = 0; index < SCI_MAX_PORTS; index++) {
2623                         if (scic_parms->sds1.ports[index].phy_mask > SCIC_SDS_PARM_PHY_MASK_MAX) {
2624                                 return SCI_FAILURE_INVALID_PARAMETER_VALUE;
2625                         }
2626                 }
2627
2628                 for (index = 0; index < SCI_MAX_PHYS; index++) {
2629                         if (
2630                                 scic_parms->sds1.phys[index].sas_address.high == 0
2631                                 && scic_parms->sds1.phys[index].sas_address.low  == 0
2632                                 ) {
2633                                 return SCI_FAILURE_INVALID_PARAMETER_VALUE;
2634                         }
2635                 }
2636
2637                 if (scic_parms->sds1.controller.mode_type == SCIC_PORT_AUTOMATIC_CONFIGURATION_MODE) {
2638                         for (index = 0; index < SCI_MAX_PHYS; index++) {
2639                                 if (scic_parms->sds1.ports[index].phy_mask != 0)
2640                                         return SCI_FAILURE_INVALID_PARAMETER_VALUE;
2641                         }
2642                 } else if (scic_parms->sds1.controller.mode_type == SCIC_PORT_MANUAL_CONFIGURATION_MODE) {
2643                         for (index = 0; index < SCI_MAX_PHYS; index++)
2644                                 combined_phy_mask |= scic_parms->sds1.ports[index].phy_mask;
2645
2646                         if (combined_phy_mask == 0)
2647                                 return SCI_FAILURE_INVALID_PARAMETER_VALUE;
2648                 } else {
2649                         return SCI_FAILURE_INVALID_PARAMETER_VALUE;
2650                 }
2651
2652                 if (scic_parms->sds1.controller.max_concurrent_dev_spin_up > MAX_CONCURRENT_DEVICE_SPIN_UP_COUNT)
2653                         return SCI_FAILURE_INVALID_PARAMETER_VALUE;
2654
2655                 scic->oem_parameters.sds1 = scic_parms->sds1;
2656
2657                 return SCI_SUCCESS;
2658         }
2659
2660         return SCI_FAILURE_INVALID_STATE;
2661 }
2662
2663 /* --------------------------------------------------------------------------- */
2664
2665 void scic_oem_parameters_get(
2666         struct scic_sds_controller *scic,
2667         union scic_oem_parameters *scic_parms)
2668 {
2669         memcpy(scic_parms, (&scic->oem_parameters), sizeof(*scic_parms));
2670 }
2671
2672 /* --------------------------------------------------------------------------- */
2673
2674
2675 #define INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_LOWER_BOUND_NS 853
2676 #define INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_UPPER_BOUND_NS 1280
2677 #define INTERRUPT_COALESCE_TIMEOUT_MAX_US                    2700000
2678 #define INTERRUPT_COALESCE_NUMBER_MAX                        256
2679 #define INTERRUPT_COALESCE_TIMEOUT_ENCODE_MIN                7
2680 #define INTERRUPT_COALESCE_TIMEOUT_ENCODE_MAX                28
2681
2682 enum sci_status scic_controller_set_interrupt_coalescence(
2683         struct scic_sds_controller *scic_controller,
2684         u32 coalesce_number,
2685         u32 coalesce_timeout)
2686 {
2687         u8 timeout_encode = 0;
2688         u32 min = 0;
2689         u32 max = 0;
2690
2691         /* Check if the input parameters fall in the range. */
2692         if (coalesce_number > INTERRUPT_COALESCE_NUMBER_MAX)
2693                 return SCI_FAILURE_INVALID_PARAMETER_VALUE;
2694
2695         /*
2696          *  Defined encoding for interrupt coalescing timeout:
2697          *              Value   Min      Max     Units
2698          *              -----   ---      ---     -----
2699          *              0       -        -       Disabled
2700          *              1       13.3     20.0    ns
2701          *              2       26.7     40.0
2702          *              3       53.3     80.0
2703          *              4       106.7    160.0
2704          *              5       213.3    320.0
2705          *              6       426.7    640.0
2706          *              7       853.3    1280.0
2707          *              8       1.7      2.6     us
2708          *              9       3.4      5.1
2709          *              10      6.8      10.2
2710          *              11      13.7     20.5
2711          *              12      27.3     41.0
2712          *              13      54.6     81.9
2713          *              14      109.2    163.8
2714          *              15      218.5    327.7
2715          *              16      436.9    655.4
2716          *              17      873.8    1310.7
2717          *              18      1.7      2.6     ms
2718          *              19      3.5      5.2
2719          *              20      7.0      10.5
2720          *              21      14.0     21.0
2721          *              22      28.0     41.9
2722          *              23      55.9     83.9
2723          *              24      111.8    167.8
2724          *              25      223.7    335.5
2725          *              26      447.4    671.1
2726          *              27      894.8    1342.2
2727          *              28      1.8      2.7     s
2728          *              Others Undefined */
2729
2730         /*
2731          * Use the table above to decide the encode of interrupt coalescing timeout
2732          * value for register writing. */
2733         if (coalesce_timeout == 0)
2734                 timeout_encode = 0;
2735         else{
2736                 /* make the timeout value in unit of (10 ns). */
2737                 coalesce_timeout = coalesce_timeout * 100;
2738                 min = INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_LOWER_BOUND_NS / 10;
2739                 max = INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_UPPER_BOUND_NS / 10;
2740
2741                 /* get the encode of timeout for register writing. */
2742                 for (timeout_encode = INTERRUPT_COALESCE_TIMEOUT_ENCODE_MIN;
2743                       timeout_encode <= INTERRUPT_COALESCE_TIMEOUT_ENCODE_MAX;
2744                       timeout_encode++) {
2745                         if (min <= coalesce_timeout &&  max > coalesce_timeout)
2746                                 break;
2747                         else if (coalesce_timeout >= max && coalesce_timeout < min * 2
2748                                  && coalesce_timeout <= INTERRUPT_COALESCE_TIMEOUT_MAX_US * 100) {
2749                                 if ((coalesce_timeout - max) < (2 * min - coalesce_timeout))
2750                                         break;
2751                                 else{
2752                                         timeout_encode++;
2753                                         break;
2754                                 }
2755                         } else {
2756                                 max = max * 2;
2757                                 min = min * 2;
2758                         }
2759                 }
2760
2761                 if (timeout_encode == INTERRUPT_COALESCE_TIMEOUT_ENCODE_MAX + 1)
2762                         /* the value is out of range. */
2763                         return SCI_FAILURE_INVALID_PARAMETER_VALUE;
2764         }
2765
2766         SMU_ICC_WRITE(
2767                 scic_controller,
2768                 (SMU_ICC_GEN_VAL(NUMBER, coalesce_number) |
2769                  SMU_ICC_GEN_VAL(TIMER, timeout_encode))
2770                 );
2771
2772         scic_controller->interrupt_coalesce_number = (u16)coalesce_number;
2773         scic_controller->interrupt_coalesce_timeout = coalesce_timeout / 100;
2774
2775         return SCI_SUCCESS;
2776 }
2777
2778
2779 struct scic_sds_controller *scic_controller_alloc(struct device *dev)
2780 {
2781         return devm_kzalloc(dev, sizeof(struct scic_sds_controller), GFP_KERNEL);
2782 }
2783
2784 /*
2785  * *****************************************************************************
2786  * * DEFAULT STATE HANDLERS
2787  * ***************************************************************************** */
2788
2789 /**
2790  *
2791  * @controller: This is struct sci_base_controller object which is cast into a
2792  *    struct scic_sds_controller object.
2793  * @remote_device: This is struct sci_base_remote_device which, if it was used, would
2794  *    be cast to a struct scic_sds_remote_device.
2795  * @io_request: This is the struct sci_base_request which, if it was used, would be
2796  *    cast to a SCIC_SDS_IO_REQUEST.
2797  * @io_tag: This is the IO tag to be assigned to the IO request or
2798  *    SCI_CONTROLLER_INVALID_IO_TAG.
2799  *
2800  * This method is called when the struct scic_sds_controller default start io/task
2801  * handler is in place. - Issue a warning message enum sci_status
2802  * SCI_FAILURE_INVALID_STATE
2803  */
2804 static enum sci_status scic_sds_controller_default_start_operation_handler(
2805         struct sci_base_controller *controller,
2806         struct sci_base_remote_device *remote_device,
2807         struct sci_base_request *io_request,
2808         u16 io_tag)
2809 {
2810         struct scic_sds_controller *this_controller;
2811
2812         this_controller = (struct scic_sds_controller *)controller;
2813
2814         dev_warn(scic_to_dev(this_controller),
2815                  "%s: SCIC Controller requested to start an io/task from "
2816                  "invalid state %d\n",
2817                  __func__,
2818                  sci_base_state_machine_get_state(
2819                          scic_sds_controller_get_base_state_machine(
2820                                  this_controller)));
2821
2822         return SCI_FAILURE_INVALID_STATE;
2823 }
2824
2825 /**
2826  *
2827  * @controller: This is struct sci_base_controller object which is cast into a
2828  *    struct scic_sds_controller object.
2829  * @remote_device: This is struct sci_base_remote_device which, if it was used, would
2830  *    be cast to a struct scic_sds_remote_device.
2831  * @io_request: This is the struct sci_base_request which, if it was used, would be
2832  *    cast to a SCIC_SDS_IO_REQUEST.
2833  *
2834  * This method is called when the struct scic_sds_controller default request handler
2835  * is in place. - Issue a warning message enum sci_status SCI_FAILURE_INVALID_STATE
2836  */
2837 static enum sci_status scic_sds_controller_default_request_handler(
2838         struct sci_base_controller *controller,
2839         struct sci_base_remote_device *remote_device,
2840         struct sci_base_request *io_request)
2841 {
2842         struct scic_sds_controller *this_controller;
2843
2844         this_controller = (struct scic_sds_controller *)controller;
2845
2846         dev_warn(scic_to_dev(this_controller),
2847                 "%s: SCIC Controller request operation from invalid state %d\n",
2848                 __func__,
2849                 sci_base_state_machine_get_state(
2850                         scic_sds_controller_get_base_state_machine(
2851                                 this_controller)));
2852
2853         return SCI_FAILURE_INVALID_STATE;
2854 }
2855
2856 /*
2857  * *****************************************************************************
2858  * * GENERAL (COMMON) STATE HANDLERS
2859  * ***************************************************************************** */
2860
2861 /**
2862  *
2863  * @controller: The struct sci_base_controller object which is cast into a
2864  *    struct scic_sds_controller object.
2865  *
2866  * This method is called when the struct scic_sds_controller is in the ready state
2867  * reset handler is in place. - Transition to
2868  * SCI_BASE_CONTROLLER_STATE_RESETTING enum sci_status SCI_SUCCESS
2869  */
2870 static enum sci_status scic_sds_controller_general_reset_handler(
2871         struct sci_base_controller *controller)
2872 {
2873         struct scic_sds_controller *this_controller;
2874
2875         this_controller = (struct scic_sds_controller *)controller;
2876
2877         /*
2878          * The reset operation is not a graceful cleanup just perform the state
2879          * transition. */
2880         sci_base_state_machine_change_state(
2881                 scic_sds_controller_get_base_state_machine(this_controller),
2882                 SCI_BASE_CONTROLLER_STATE_RESETTING
2883                 );
2884
2885         return SCI_SUCCESS;
2886 }
2887
2888 /*
2889  * *****************************************************************************
2890  * * RESET STATE HANDLERS
2891  * ***************************************************************************** */
2892
2893 /**
2894  *
2895  * @controller: This is the struct sci_base_controller object which is cast into a
2896  *    struct scic_sds_controller object.
2897  *
2898  * This method is the struct scic_sds_controller initialize handler for the reset
2899  * state. - Currently this function does nothing enum sci_status SCI_FAILURE This
2900  * function is not yet implemented and is a valid request from the reset state.
2901  */
2902 static enum sci_status scic_sds_controller_reset_state_initialize_handler(
2903         struct sci_base_controller *controller)
2904 {
2905         u32 index;
2906         enum sci_status result = SCI_SUCCESS;
2907         struct scic_sds_controller *this_controller;
2908
2909         this_controller = (struct scic_sds_controller *)controller;
2910
2911         sci_base_state_machine_change_state(
2912                 scic_sds_controller_get_base_state_machine(this_controller),
2913                 SCI_BASE_CONTROLLER_STATE_INITIALIZING
2914                 );
2915
2916         this_controller->timeout_timer = isci_event_timer_create(
2917                 this_controller,
2918                 (void (*)(void *))scic_sds_controller_timeout_handler,
2919                 (void (*)(void *))controller);
2920
2921         scic_sds_controller_initialize_phy_startup(this_controller);
2922
2923         scic_sds_controller_initialize_power_control(this_controller);
2924
2925         /*
2926          * There is nothing to do here for B0 since we do not have to
2927          * program the AFE registers.
2928          * / @todo The AFE settings are supposed to be correct for the B0 but
2929          * /       presently they seem to be wrong. */
2930         scic_sds_controller_afe_initialization(this_controller);
2931
2932         if (SCI_SUCCESS == result) {
2933                 u32 status;
2934                 u32 terminate_loop;
2935
2936                 /* Take the hardware out of reset */
2937                 SMU_SMUSRCR_WRITE(this_controller, 0x00000000);
2938
2939                 /*
2940                  * / @todo Provide meaningfull error code for hardware failure
2941                  * result = SCI_FAILURE_CONTROLLER_HARDWARE; */
2942                 result = SCI_FAILURE;
2943                 terminate_loop = 100;
2944
2945                 while (terminate_loop-- && (result != SCI_SUCCESS)) {
2946                         /* Loop until the hardware reports success */
2947                         udelay(SCU_CONTEXT_RAM_INIT_STALL_TIME);
2948                         status = SMU_SMUCSR_READ(this_controller);
2949
2950                         if ((status & SCU_RAM_INIT_COMPLETED) == SCU_RAM_INIT_COMPLETED) {
2951                                 result = SCI_SUCCESS;
2952                         }
2953                 }
2954         }
2955
2956         if (result == SCI_SUCCESS) {
2957                 u32 max_supported_ports;
2958                 u32 max_supported_devices;
2959                 u32 max_supported_io_requests;
2960                 u32 device_context_capacity;
2961
2962                 /*
2963                  * Determine what are the actaul device capacities that the
2964                  * hardware will support */
2965                 device_context_capacity = SMU_DCC_READ(this_controller);
2966
2967                 max_supported_ports =
2968                         smu_dcc_get_max_ports(device_context_capacity);
2969                 max_supported_devices =
2970                         smu_dcc_get_max_remote_node_context(device_context_capacity);
2971                 max_supported_io_requests =
2972                         smu_dcc_get_max_task_context(device_context_capacity);
2973
2974                 /* Make all PEs that are unassigned match up with the logical ports */
2975                 for (index = 0; index < max_supported_ports; index++) {
2976                         scu_register_write(
2977                                 this_controller,
2978                                 this_controller->scu_registers->peg0.ptsg.protocol_engine[index],
2979                                 index
2980                                 );
2981                 }
2982
2983                 /* Record the smaller of the two capacity values */
2984                 this_controller->logical_port_entries =
2985                         min(max_supported_ports, this_controller->logical_port_entries);
2986
2987                 this_controller->task_context_entries =
2988                         min(max_supported_io_requests, this_controller->task_context_entries);
2989
2990                 this_controller->remote_node_entries =
2991                         min(max_supported_devices, this_controller->remote_node_entries);
2992
2993                 /*
2994                  * Now that we have the correct hardware reported minimum values
2995                  * build the MDL for the controller.  Default to a performance
2996                  * configuration. */
2997                 scic_controller_set_mode(this_controller, SCI_MODE_SPEED);
2998         }
2999
3000         /* Initialize hardware PCI Relaxed ordering in DMA engines */
3001         if (result == SCI_SUCCESS) {
3002                 u32 dma_configuration;
3003
3004                 /* Configure the payload DMA */
3005                 dma_configuration = SCU_PDMACR_READ(this_controller);
3006                 dma_configuration |= SCU_PDMACR_GEN_BIT(PCI_RELAXED_ORDERING_ENABLE);
3007                 SCU_PDMACR_WRITE(this_controller, dma_configuration);
3008
3009                 /* Configure the control DMA */
3010                 dma_configuration = SCU_CDMACR_READ(this_controller);
3011                 dma_configuration |= SCU_CDMACR_GEN_BIT(PCI_RELAXED_ORDERING_ENABLE);
3012                 SCU_CDMACR_WRITE(this_controller, dma_configuration);
3013         }
3014
3015         /*
3016          * Initialize the PHYs before the PORTs because the PHY registers
3017          * are accessed during the port initialization. */
3018         if (result == SCI_SUCCESS) {
3019                 /* Initialize the phys */
3020                 for (index = 0;
3021                      (result == SCI_SUCCESS) && (index < SCI_MAX_PHYS);
3022                      index++) {
3023                         result = scic_sds_phy_initialize(
3024                                 &this_controller->phy_table[index],
3025                                 &this_controller->scu_registers->peg0.pe[index].tl,
3026                                 &this_controller->scu_registers->peg0.pe[index].ll
3027                                 );
3028                 }
3029         }
3030
3031         if (result == SCI_SUCCESS) {
3032                 /* Initialize the logical ports */
3033                 for (index = 0;
3034                      (index < this_controller->logical_port_entries)
3035                      && (result == SCI_SUCCESS);
3036                      index++) {
3037                         result = scic_sds_port_initialize(
3038                                 &this_controller->port_table[index],
3039                                 &this_controller->scu_registers->peg0.ptsg.port[index],
3040                                 &this_controller->scu_registers->peg0.ptsg.protocol_engine,
3041                                 &this_controller->scu_registers->peg0.viit[index]
3042                                 );
3043                 }
3044         }
3045
3046         if (SCI_SUCCESS == result) {
3047                 result = scic_sds_port_configuration_agent_initialize(
3048                         this_controller,
3049                         &this_controller->port_agent
3050                         );
3051         }
3052
3053         /* Advance the controller state machine */
3054         if (result == SCI_SUCCESS) {
3055                 sci_base_state_machine_change_state(
3056                         scic_sds_controller_get_base_state_machine(this_controller),
3057                         SCI_BASE_CONTROLLER_STATE_INITIALIZED
3058                         );
3059         } else {
3060                 sci_base_state_machine_change_state(
3061                         scic_sds_controller_get_base_state_machine(this_controller),
3062                         SCI_BASE_CONTROLLER_STATE_FAILED
3063                         );
3064         }
3065
3066         return result;
3067 }
3068
3069 /*
3070  * *****************************************************************************
3071  * * INITIALIZED STATE HANDLERS
3072  * ***************************************************************************** */
3073
3074 /**
3075  *
3076  * @controller: This is the struct sci_base_controller object which is cast into a
3077  *    struct scic_sds_controller object.
3078  * @timeout: This is the allowed time for the controller object to reach the
3079  *    started state.
3080  *
3081  * This method is the struct scic_sds_controller start handler for the initialized
3082  * state. - Validate we have a good memory descriptor table - Initialze the
3083  * physical memory before programming the hardware - Program the SCU hardware
3084  * with the physical memory addresses passed in the memory descriptor table. -
3085  * Initialzie the TCi pool - Initialize the RNi pool - Initialize the
3086  * completion queue - Initialize the unsolicited frame data - Take the SCU port
3087  * task scheduler out of reset - Start the first phy object. - Transition to
3088  * SCI_BASE_CONTROLLER_STATE_STARTING. enum sci_status SCI_SUCCESS if all of the
3089  * controller start operations complete
3090  * SCI_FAILURE_UNSUPPORTED_INFORMATION_FIELD if one or more of the memory
3091  * descriptor fields is invalid.
3092  */
3093 static enum sci_status scic_sds_controller_initialized_state_start_handler(
3094         struct sci_base_controller *controller,
3095         u32 timeout)
3096 {
3097         u16 index;
3098         enum sci_status result;
3099         struct scic_sds_controller *this_controller;
3100
3101         this_controller = (struct scic_sds_controller *)controller;
3102
3103         /* Make sure that the SCI User filled in the memory descriptor table correctly */
3104         result = scic_sds_controller_validate_memory_descriptor_table(this_controller);
3105
3106         if (result == SCI_SUCCESS) {
3107                 /* The memory descriptor list looks good so program the hardware */
3108                 scic_sds_controller_ram_initialization(this_controller);
3109         }
3110
3111         if (result == SCI_SUCCESS) {
3112                 /* Build the TCi free pool */
3113                 sci_pool_initialize(this_controller->tci_pool);
3114                 for (index = 0; index < this_controller->task_context_entries; index++) {
3115                         sci_pool_put(this_controller->tci_pool, index);
3116                 }
3117
3118                 /* Build the RNi free pool */
3119                 scic_sds_remote_node_table_initialize(
3120                         &this_controller->available_remote_nodes,
3121                         this_controller->remote_node_entries
3122                         );
3123         }
3124
3125         if (result == SCI_SUCCESS) {
3126                 /*
3127                  * Before anything else lets make sure we will not be interrupted
3128                  * by the hardware. */
3129                 scic_controller_disable_interrupts(this_controller);
3130
3131                 /* Enable the port task scheduler */
3132                 scic_sds_controller_enable_port_task_scheduler(this_controller);
3133
3134                 /* Assign all the task entries to this controller physical function */
3135                 scic_sds_controller_assign_task_entries(this_controller);
3136
3137                 /* Now initialze the completion queue */
3138                 scic_sds_controller_initialize_completion_queue(this_controller);
3139
3140                 /* Initialize the unsolicited frame queue for use */
3141                 scic_sds_controller_initialize_unsolicited_frame_queue(this_controller);
3142         }
3143
3144         /* Start all of the ports on this controller */
3145         for (index = 0; index < this_controller->logical_port_entries &&
3146                         result == SCI_SUCCESS; index++) {
3147                 struct scic_sds_port *sci_port = &this_controller->port_table[index];
3148
3149                 result = sci_port->state_handlers->parent.start_handler(&sci_port->parent);
3150         }
3151
3152         if (result == SCI_SUCCESS) {
3153                 scic_sds_controller_start_next_phy(this_controller);
3154
3155                 isci_event_timer_start(this_controller,
3156                                     this_controller->timeout_timer,
3157                                     timeout);
3158
3159                 sci_base_state_machine_change_state(
3160                         scic_sds_controller_get_base_state_machine(this_controller),
3161                         SCI_BASE_CONTROLLER_STATE_STARTING
3162                         );
3163         }
3164
3165         return result;
3166 }
3167
3168 /*
3169  * *****************************************************************************
3170  * * INITIALIZED STATE HANDLERS
3171  * ***************************************************************************** */
3172
3173 /**
3174  *
3175  * @controller: This is struct scic_sds_controller which receives the link up
3176  *    notification.
3177  * @port: This is struct scic_sds_port with which the phy is associated.
3178  * @phy: This is the struct scic_sds_phy which has gone link up.
3179  *
3180  * This method is called when the struct scic_sds_controller is in the starting state
3181  * link up handler is called.  This method will perform the following: - Stop
3182  * the phy timer - Start the next phy - Report the link up condition to the
3183  * port object none
3184  */
3185 static void scic_sds_controller_starting_state_link_up_handler(
3186         struct scic_sds_controller *this_controller,
3187         struct scic_sds_port *port,
3188         struct scic_sds_phy *phy)
3189 {
3190         scic_sds_controller_phy_timer_stop(this_controller);
3191
3192         this_controller->port_agent.link_up_handler(
3193                 this_controller, &this_controller->port_agent, port, phy
3194                 );
3195         /* scic_sds_port_link_up(port, phy); */
3196
3197         scic_sds_controller_start_next_phy(this_controller);
3198 }
3199
3200 /**
3201  *
3202  * @controller: This is struct scic_sds_controller which receives the link down
3203  *    notification.
3204  * @port: This is struct scic_sds_port with which the phy is associated.
3205  * @phy: This is the struct scic_sds_phy which has gone link down.
3206  *
3207  * This method is called when the struct scic_sds_controller is in the starting state
3208  * link down handler is called. - Report the link down condition to the port
3209  * object none
3210  */
3211 static void scic_sds_controller_starting_state_link_down_handler(
3212         struct scic_sds_controller *this_controller,
3213         struct scic_sds_port *port,
3214         struct scic_sds_phy *phy)
3215 {
3216         this_controller->port_agent.link_down_handler(
3217                 this_controller, &this_controller->port_agent, port, phy
3218                 );
3219         /* scic_sds_port_link_down(port, phy); */
3220 }
3221
3222 /*
3223  * *****************************************************************************
3224  * * READY STATE HANDLERS
3225  * ***************************************************************************** */
3226
3227 /**
3228  *
3229  * @controller: The struct sci_base_controller object which is cast into a
3230  *    struct scic_sds_controller object.
3231  * @timeout: The timeout for when the stop operation should report a failure.
3232  *
3233  * This method is called when the struct scic_sds_controller is in the ready state
3234  * stop handler is called. - Start the timeout timer - Transition to
3235  * SCI_BASE_CONTROLLER_STATE_STOPPING. enum sci_status SCI_SUCCESS
3236  */
3237 static enum sci_status scic_sds_controller_ready_state_stop_handler(
3238         struct sci_base_controller *controller,
3239         u32 timeout)
3240 {
3241         struct scic_sds_controller *this_controller;
3242
3243         this_controller = (struct scic_sds_controller *)controller;
3244
3245         isci_event_timer_start(this_controller,
3246                             this_controller->timeout_timer,
3247                             timeout);
3248
3249         sci_base_state_machine_change_state(
3250                 scic_sds_controller_get_base_state_machine(this_controller),
3251                 SCI_BASE_CONTROLLER_STATE_STOPPING
3252                 );
3253
3254         return SCI_SUCCESS;
3255 }
3256
3257 /**
3258  *
3259  * @controller: This is struct sci_base_controller object which is cast into a
3260  *    struct scic_sds_controller object.
3261  * @remote_device: This is struct sci_base_remote_device which is cast to a
3262  *    struct scic_sds_remote_device object.
3263  * @io_request: This is the struct sci_base_request which is cast to a
3264  *    SCIC_SDS_IO_REQUEST object.
3265  * @io_tag: This is the IO tag to be assigned to the IO request or
3266  *    SCI_CONTROLLER_INVALID_IO_TAG.
3267  *
3268  * This method is called when the struct scic_sds_controller is in the ready state and
3269  * the start io handler is called. - Start the io request on the remote device
3270  * - if successful - assign the io_request to the io_request_table - post the
3271  * request to the hardware enum sci_status SCI_SUCCESS if the start io operation
3272  * succeeds SCI_FAILURE_INSUFFICIENT_RESOURCES if the IO tag could not be
3273  * allocated for the io request. SCI_FAILURE_INVALID_STATE if one or more
3274  * objects are not in a valid state to accept io requests. How does the io_tag
3275  * parameter get assigned to the io request?
3276  */
3277 static enum sci_status scic_sds_controller_ready_state_start_io_handler(
3278         struct sci_base_controller *controller,
3279         struct sci_base_remote_device *remote_device,
3280         struct sci_base_request *io_request,
3281         u16 io_tag)
3282 {
3283         enum sci_status status;
3284
3285         struct scic_sds_controller *this_controller;
3286         struct scic_sds_request *the_request;
3287         struct scic_sds_remote_device *the_device;
3288
3289         this_controller = (struct scic_sds_controller *)controller;
3290         the_request = (struct scic_sds_request *)io_request;
3291         the_device = (struct scic_sds_remote_device *)remote_device;
3292
3293         status = scic_sds_remote_device_start_io(this_controller, the_device, the_request);
3294
3295         if (status == SCI_SUCCESS) {
3296                 this_controller->io_request_table[
3297                         scic_sds_io_tag_get_index(the_request->io_tag)] = the_request;
3298
3299                 scic_sds_controller_post_request(
3300                         this_controller,
3301                         scic_sds_request_get_post_context(the_request)
3302                         );
3303         }
3304
3305         return status;
3306 }
3307
3308 /**
3309  *
3310  * @controller: This is struct sci_base_controller object which is cast into a
3311  *    struct scic_sds_controller object.
3312  * @remote_device: This is struct sci_base_remote_device which is cast to a
3313  *    struct scic_sds_remote_device object.
3314  * @io_request: This is the struct sci_base_request which is cast to a
3315  *    SCIC_SDS_IO_REQUEST object.
3316  *
3317  * This method is called when the struct scic_sds_controller is in the ready state and
3318  * the complete io handler is called. - Complete the io request on the remote
3319  * device - if successful - remove the io_request to the io_request_table
3320  * enum sci_status SCI_SUCCESS if the start io operation succeeds
3321  * SCI_FAILURE_INVALID_STATE if one or more objects are not in a valid state to
3322  * accept io requests.
3323  */
3324 static enum sci_status scic_sds_controller_ready_state_complete_io_handler(
3325         struct sci_base_controller *controller,
3326         struct sci_base_remote_device *remote_device,
3327         struct sci_base_request *io_request)
3328 {
3329         u16 index;
3330         enum sci_status status;
3331         struct scic_sds_controller *this_controller;
3332         struct scic_sds_request *the_request;
3333         struct scic_sds_remote_device *the_device;
3334
3335         this_controller = (struct scic_sds_controller *)controller;
3336         the_request = (struct scic_sds_request *)io_request;
3337         the_device = (struct scic_sds_remote_device *)remote_device;
3338
3339         status = scic_sds_remote_device_complete_io(
3340                 this_controller, the_device, the_request);
3341
3342         if (status == SCI_SUCCESS) {
3343                 index = scic_sds_io_tag_get_index(the_request->io_tag);
3344                 this_controller->io_request_table[index] = NULL;
3345         }
3346
3347         return status;
3348 }
3349
3350 /**
3351  *
3352  * @controller: This is struct sci_base_controller object which is cast into a
3353  *    struct scic_sds_controller object.
3354  * @remote_device: This is struct sci_base_remote_device which is cast to a
3355  *    struct scic_sds_remote_device object.
3356  * @io_request: This is the struct sci_base_request which is cast to a
3357  *    SCIC_SDS_IO_REQUEST object.
3358  *
3359  * This method is called when the struct scic_sds_controller is in the ready state and
3360  * the continue io handler is called. enum sci_status
3361  */
3362 static enum sci_status scic_sds_controller_ready_state_continue_io_handler(
3363         struct sci_base_controller *controller,
3364         struct sci_base_remote_device *remote_device,
3365         struct sci_base_request *io_request)
3366 {
3367         struct scic_sds_controller *this_controller;
3368         struct scic_sds_request *the_request;
3369
3370         the_request     = (struct scic_sds_request *)io_request;
3371         this_controller = (struct scic_sds_controller *)controller;
3372
3373         this_controller->io_request_table[
3374                 scic_sds_io_tag_get_index(the_request->io_tag)] = the_request;
3375
3376         scic_sds_controller_post_request(
3377                 this_controller,
3378                 scic_sds_request_get_post_context(the_request)
3379                 );
3380
3381         return SCI_SUCCESS;
3382 }
3383
3384 /**
3385  *
3386  * @controller: This is struct sci_base_controller object which is cast into a
3387  *    struct scic_sds_controller object.
3388  * @remote_device: This is struct sci_base_remote_device which is cast to a
3389  *    struct scic_sds_remote_device object.
3390  * @io_request: This is the struct sci_base_request which is cast to a
3391  *    SCIC_SDS_IO_REQUEST object.
3392  * @task_tag: This is the task tag to be assigned to the task request or
3393  *    SCI_CONTROLLER_INVALID_IO_TAG.
3394  *
3395  * This method is called when the struct scic_sds_controller is in the ready state and
3396  * the start task handler is called. - The remote device is requested to start
3397  * the task request - if successful - assign the task to the io_request_table -
3398  * post the request to the SCU hardware enum sci_status SCI_SUCCESS if the start io
3399  * operation succeeds SCI_FAILURE_INSUFFICIENT_RESOURCES if the IO tag could
3400  * not be allocated for the io request. SCI_FAILURE_INVALID_STATE if one or
3401  * more objects are not in a valid state to accept io requests. How does the io
3402  * tag get assigned in this code path?
3403  */
3404 static enum sci_status scic_sds_controller_ready_state_start_task_handler(
3405         struct sci_base_controller *controller,
3406         struct sci_base_remote_device *remote_device,
3407         struct sci_base_request *io_request,
3408         u16 task_tag)
3409 {
3410         struct scic_sds_controller *this_controller = (struct scic_sds_controller *)
3411                                                  controller;
3412         struct scic_sds_request *the_request     = (struct scic_sds_request *)
3413                                               io_request;
3414         struct scic_sds_remote_device *the_device      = (struct scic_sds_remote_device *)
3415                                                     remote_device;
3416         enum sci_status status;
3417
3418         status = scic_sds_remote_device_start_task(
3419                 this_controller, the_device, the_request
3420                 );
3421
3422         if (status == SCI_SUCCESS) {
3423                 this_controller->io_request_table[
3424                         scic_sds_io_tag_get_index(the_request->io_tag)] = the_request;
3425
3426                 scic_sds_controller_post_request(
3427                         this_controller,
3428                         scic_sds_request_get_post_context(the_request)
3429                         );
3430         } else if (status == SCI_FAILURE_RESET_DEVICE_PARTIAL_SUCCESS) {
3431                 this_controller->io_request_table[
3432                         scic_sds_io_tag_get_index(the_request->io_tag)] = the_request;
3433
3434                 /*
3435                  * We will let framework know this task request started successfully,
3436                  * although core is still woring on starting the request (to post tc when
3437                  * RNC is resumed.) */
3438                 status = SCI_SUCCESS;
3439         }
3440         return status;
3441 }
3442
3443 /**
3444  *
3445  * @controller: This is struct sci_base_controller object which is cast into a
3446  *    struct scic_sds_controller object.
3447  * @remote_device: This is struct sci_base_remote_device which is cast to a
3448  *    struct scic_sds_remote_device object.
3449  * @io_request: This is the struct sci_base_request which is cast to a
3450  *    SCIC_SDS_IO_REQUEST object.
3451  *
3452  * This method is called when the struct scic_sds_controller is in the ready state and
3453  * the terminate request handler is called. - call the io request terminate
3454  * function - if successful - post the terminate request to the SCU hardware
3455  * enum sci_status SCI_SUCCESS if the start io operation succeeds
3456  * SCI_FAILURE_INVALID_STATE if one or more objects are not in a valid state to
3457  * accept io requests.
3458  */
3459 static enum sci_status scic_sds_controller_ready_state_terminate_request_handler(
3460         struct sci_base_controller *controller,
3461         struct sci_base_remote_device *remote_device,
3462         struct sci_base_request *io_request)
3463 {
3464         struct scic_sds_controller *this_controller = (struct scic_sds_controller *)
3465                                                  controller;
3466         struct scic_sds_request *the_request     = (struct scic_sds_request *)
3467                                               io_request;
3468         enum sci_status status;
3469
3470         status = scic_sds_io_request_terminate(the_request);
3471         if (status == SCI_SUCCESS) {
3472                 /*
3473                  * Utilize the original post context command and or in the POST_TC_ABORT
3474                  * request sub-type. */
3475                 scic_sds_controller_post_request(
3476                         this_controller,
3477                         scic_sds_request_get_post_context(the_request)
3478                         | SCU_CONTEXT_COMMAND_REQUEST_POST_TC_ABORT
3479                         );
3480         }
3481
3482         return status;
3483 }
3484
3485 /**
3486  *
3487  * @controller: This is struct scic_sds_controller which receives the link up
3488  *    notification.
3489  * @port: This is struct scic_sds_port with which the phy is associated.
3490  * @phy: This is the struct scic_sds_phy which has gone link up.
3491  *
3492  * This method is called when the struct scic_sds_controller is in the starting state
3493  * link up handler is called.  This method will perform the following: - Stop
3494  * the phy timer - Start the next phy - Report the link up condition to the
3495  * port object none
3496  */
3497 static void scic_sds_controller_ready_state_link_up_handler(
3498         struct scic_sds_controller *this_controller,
3499         struct scic_sds_port *port,
3500         struct scic_sds_phy *phy)
3501 {
3502         this_controller->port_agent.link_up_handler(
3503                 this_controller, &this_controller->port_agent, port, phy
3504                 );
3505 }
3506
3507 /**
3508  *
3509  * @controller: This is struct scic_sds_controller which receives the link down
3510  *    notification.
3511  * @port: This is struct scic_sds_port with which the phy is associated.
3512  * @phy: This is the struct scic_sds_phy which has gone link down.
3513  *
3514  * This method is called when the struct scic_sds_controller is in the starting state
3515  * link down handler is called. - Report the link down condition to the port
3516  * object none
3517  */
3518 static void scic_sds_controller_ready_state_link_down_handler(
3519         struct scic_sds_controller *this_controller,
3520         struct scic_sds_port *port,
3521         struct scic_sds_phy *phy)
3522 {
3523         this_controller->port_agent.link_down_handler(
3524                 this_controller, &this_controller->port_agent, port, phy
3525                 );
3526 }
3527
3528 /*
3529  * *****************************************************************************
3530  * * STOPPING STATE HANDLERS
3531  * ***************************************************************************** */
3532
3533 /**
3534  *
3535  * @controller: This is struct sci_base_controller object which is cast into a
3536  *    struct scic_sds_controller object.
3537  * @remote_device: This is struct sci_base_remote_device which is cast to a
3538  *    struct scic_sds_remote_device object.
3539  * @io_request: This is the struct sci_base_request which is cast to a
3540  *    SCIC_SDS_IO_REQUEST object.
3541  *
3542  * This method is called when the struct scic_sds_controller is in a stopping state
3543  * and the complete io handler is called. - This function is not yet
3544  * implemented enum sci_status SCI_FAILURE
3545  */
3546 static enum sci_status scic_sds_controller_stopping_state_complete_io_handler(
3547         struct sci_base_controller *controller,
3548         struct sci_base_remote_device *remote_device,
3549         struct sci_base_request *io_request)
3550 {
3551         struct scic_sds_controller *this_controller;
3552
3553         this_controller = (struct scic_sds_controller *)controller;
3554
3555         /* / @todo Implement this function */
3556         return SCI_FAILURE;
3557 }
3558
3559 /**
3560  *
3561  * @controller: This is struct sci_base_controller object which is cast into a
3562  *    struct scic_sds_controller object.
3563  * @remote_device: This is struct sci_base_remote_device which is cast to a
3564  *    struct scic_sds_remote_device object.
3565  *
3566  * This method is called when the struct scic_sds_controller is in a stopping state
3567  * and the remote device has stopped.
3568  **/
3569 void scic_sds_controller_stopping_state_device_stopped_handler(
3570         struct scic_sds_controller *controller,
3571         struct scic_sds_remote_device *remote_device
3572 )
3573 {
3574         if (!scic_sds_controller_has_remote_devices_stopping(controller)) {
3575                 sci_base_state_machine_change_state(
3576                         &controller->parent.state_machine,
3577                         SCI_BASE_CONTROLLER_STATE_STOPPED
3578                 );
3579         }
3580 }
3581
3582 const struct scic_sds_controller_state_handler scic_sds_controller_state_handler_table[] = {
3583         [SCI_BASE_CONTROLLER_STATE_INITIAL] = {
3584                 .base.start_io     = scic_sds_controller_default_start_operation_handler,
3585                 .base.complete_io  = scic_sds_controller_default_request_handler,
3586                 .base.continue_io  = scic_sds_controller_default_request_handler,
3587                 .terminate_request = scic_sds_controller_default_request_handler,
3588         },
3589         [SCI_BASE_CONTROLLER_STATE_RESET] = {
3590                 .base.reset        = scic_sds_controller_general_reset_handler,
3591                 .base.initialize   = scic_sds_controller_reset_state_initialize_handler,
3592                 .base.start_io     = scic_sds_controller_default_start_operation_handler,
3593                 .base.complete_io  = scic_sds_controller_default_request_handler,
3594                 .base.continue_io  = scic_sds_controller_default_request_handler,
3595                 .terminate_request = scic_sds_controller_default_request_handler,
3596         },
3597         [SCI_BASE_CONTROLLER_STATE_INITIALIZING] = {
3598                 .base.start_io     = scic_sds_controller_default_start_operation_handler,
3599                 .base.complete_io  = scic_sds_controller_default_request_handler,
3600                 .base.continue_io  = scic_sds_controller_default_request_handler,
3601                 .terminate_request = scic_sds_controller_default_request_handler,
3602         },
3603         [SCI_BASE_CONTROLLER_STATE_INITIALIZED] = {
3604                 .base.start        = scic_sds_controller_initialized_state_start_handler,
3605                 .base.start_io     = scic_sds_controller_default_start_operation_handler,
3606                 .base.complete_io  = scic_sds_controller_default_request_handler,
3607                 .base.continue_io  = scic_sds_controller_default_request_handler,
3608                 .terminate_request = scic_sds_controller_default_request_handler,
3609         },
3610         [SCI_BASE_CONTROLLER_STATE_STARTING] = {
3611                 .base.start_io     = scic_sds_controller_default_start_operation_handler,
3612                 .base.complete_io  = scic_sds_controller_default_request_handler,
3613                 .base.continue_io  = scic_sds_controller_default_request_handler,
3614                 .terminate_request = scic_sds_controller_default_request_handler,
3615                 .link_up           = scic_sds_controller_starting_state_link_up_handler,
3616                 .link_down         = scic_sds_controller_starting_state_link_down_handler
3617         },
3618         [SCI_BASE_CONTROLLER_STATE_READY] = {
3619                 .base.stop         = scic_sds_controller_ready_state_stop_handler,
3620                 .base.reset        = scic_sds_controller_general_reset_handler,
3621                 .base.start_io     = scic_sds_controller_ready_state_start_io_handler,
3622                 .base.complete_io  = scic_sds_controller_ready_state_complete_io_handler,
3623                 .base.continue_io  = scic_sds_controller_ready_state_continue_io_handler,
3624                 .base.start_task   = scic_sds_controller_ready_state_start_task_handler,
3625                 .base.complete_task = scic_sds_controller_ready_state_complete_io_handler,
3626                 .terminate_request = scic_sds_controller_ready_state_terminate_request_handler,
3627                 .link_up           = scic_sds_controller_ready_state_link_up_handler,
3628                 .link_down         = scic_sds_controller_ready_state_link_down_handler
3629         },
3630         [SCI_BASE_CONTROLLER_STATE_RESETTING] = {
3631                 .base.start_io     = scic_sds_controller_default_start_operation_handler,
3632                 .base.complete_io  = scic_sds_controller_default_request_handler,
3633                 .base.continue_io  = scic_sds_controller_default_request_handler,
3634                 .terminate_request = scic_sds_controller_default_request_handler,
3635         },
3636         [SCI_BASE_CONTROLLER_STATE_STOPPING] = {
3637                 .base.start_io     = scic_sds_controller_default_start_operation_handler,
3638                 .base.complete_io  = scic_sds_controller_stopping_state_complete_io_handler,
3639                 .base.continue_io  = scic_sds_controller_default_request_handler,
3640                 .terminate_request = scic_sds_controller_default_request_handler,
3641                 .remote_device_stopped_handler = scic_sds_controller_stopping_state_device_stopped_handler,
3642         },
3643         [SCI_BASE_CONTROLLER_STATE_STOPPED] = {
3644                 .base.reset        = scic_sds_controller_general_reset_handler,
3645                 .base.start_io     = scic_sds_controller_default_start_operation_handler,
3646                 .base.complete_io  = scic_sds_controller_default_request_handler,
3647                 .base.continue_io  = scic_sds_controller_default_request_handler,
3648                 .terminate_request = scic_sds_controller_default_request_handler,
3649         },
3650         [SCI_BASE_CONTROLLER_STATE_FAILED] = {
3651                 .base.reset        = scic_sds_controller_general_reset_handler,
3652                 .base.start_io     = scic_sds_controller_default_start_operation_handler,
3653                 .base.complete_io  = scic_sds_controller_default_request_handler,
3654                 .base.continue_io  = scic_sds_controller_default_request_handler,
3655                 .terminate_request = scic_sds_controller_default_request_handler,
3656         },
3657 };
3658
3659 /**
3660  *
3661  * @object: This is the struct sci_base_object which is cast to a struct scic_sds_controller
3662  *    object.
3663  *
3664  * This method implements the actions taken by the struct scic_sds_controller on entry
3665  * to the SCI_BASE_CONTROLLER_STATE_INITIAL. - Set the state handlers to the
3666  * controllers initial state. none This function should initialze the
3667  * controller object.
3668  */
3669 static void scic_sds_controller_initial_state_enter(
3670         struct sci_base_object *object)
3671 {
3672         struct scic_sds_controller *this_controller;
3673
3674         this_controller = (struct scic_sds_controller *)object;
3675
3676         sci_base_state_machine_change_state(
3677                 &this_controller->parent.state_machine, SCI_BASE_CONTROLLER_STATE_RESET);
3678 }
3679
3680 /**
3681  *
3682  * @object: This is the struct sci_base_object which is cast to a struct scic_sds_controller
3683  *    object.
3684  *
3685  * This method implements the actions taken by the struct scic_sds_controller on exit
3686  * from the SCI_BASE_CONTROLLER_STATE_STARTING. - This function stops the
3687  * controller starting timeout timer. none
3688  */
3689 static void scic_sds_controller_starting_state_exit(
3690         struct sci_base_object *object)
3691 {
3692         struct scic_sds_controller *scic = (struct scic_sds_controller *)object;
3693
3694         isci_event_timer_stop(scic, scic->timeout_timer);
3695 }
3696
3697 /**
3698  *
3699  * @object: This is the struct sci_base_object which is cast to a struct scic_sds_controller
3700  *    object.
3701  *
3702  * This method implements the actions taken by the struct scic_sds_controller on entry
3703  * to the SCI_BASE_CONTROLLER_STATE_READY. - Set the state handlers to the
3704  * controllers ready state. none
3705  */
3706 static void scic_sds_controller_ready_state_enter(
3707         struct sci_base_object *object)
3708 {
3709         struct scic_sds_controller *this_controller;
3710
3711         this_controller = (struct scic_sds_controller *)object;
3712
3713         /* set the default interrupt coalescence number and timeout value. */
3714         scic_controller_set_interrupt_coalescence(
3715                 this_controller, 0x10, 250);
3716 }
3717
3718 /**
3719  *
3720  * @object: This is the struct sci_base_object which is cast to a struct scic_sds_controller
3721  *    object.
3722  *
3723  * This method implements the actions taken by the struct scic_sds_controller on exit
3724  * from the SCI_BASE_CONTROLLER_STATE_READY. - This function does nothing. none
3725  */
3726 static void scic_sds_controller_ready_state_exit(
3727         struct sci_base_object *object)
3728 {
3729         struct scic_sds_controller *this_controller;
3730
3731         this_controller = (struct scic_sds_controller *)object;
3732
3733         /* disable interrupt coalescence. */
3734         scic_controller_set_interrupt_coalescence(this_controller, 0, 0);
3735 }
3736
3737 /**
3738  *
3739  * @object: This is the struct sci_base_object which is cast to a struct scic_sds_controller
3740  *    object.
3741  *
3742  * This method implements the actions taken by the struct scic_sds_controller on entry
3743  * to the SCI_BASE_CONTROLLER_STATE_READY. - Set the state handlers to the
3744  * controllers ready state. - Stop the phys on this controller - Stop the ports
3745  * on this controller - Stop all of the remote devices on this controller none
3746  */
3747 static void scic_sds_controller_stopping_state_enter(
3748         struct sci_base_object *object)
3749 {
3750         struct scic_sds_controller *this_controller;
3751
3752         this_controller = (struct scic_sds_controller *)object;
3753
3754         /* Stop all of the components for this controller */
3755         scic_sds_controller_stop_phys(this_controller);
3756         scic_sds_controller_stop_ports(this_controller);
3757         scic_sds_controller_stop_devices(this_controller);
3758 }
3759
3760 /**
3761  *
3762  * @object: This is the struct sci_base_object which is cast to a struct scic_sds_controller
3763  *    object.
3764  *
3765  * This method implements the actions taken by the struct scic_sds_controller on exit
3766  * from the SCI_BASE_CONTROLLER_STATE_STOPPING. - This function stops the
3767  * controller stopping timeout timer. none
3768  */
3769 static void scic_sds_controller_stopping_state_exit(
3770         struct sci_base_object *object)
3771 {
3772         struct scic_sds_controller *this_controller;
3773
3774         this_controller = (struct scic_sds_controller *)object;
3775
3776         isci_event_timer_stop(this_controller, this_controller->timeout_timer);
3777 }
3778
3779 /**
3780  *
3781  * @object: This is the struct sci_base_object which is cast to a struct scic_sds_controller
3782  *    object.
3783  *
3784  * This method implements the actions taken by the struct scic_sds_controller on entry
3785  * to the SCI_BASE_CONTROLLER_STATE_RESETTING. - Set the state handlers to the
3786  * controllers resetting state. - Write to the SCU hardware reset register to
3787  * force a reset - Transition to the SCI_BASE_CONTROLLER_STATE_RESET none
3788  */
3789 static void scic_sds_controller_resetting_state_enter(
3790         struct sci_base_object *object)
3791 {
3792         struct scic_sds_controller *this_controller;
3793
3794         this_controller = (struct scic_sds_controller *)object;
3795
3796         scic_sds_controller_reset_hardware(this_controller);
3797
3798         sci_base_state_machine_change_state(
3799                 scic_sds_controller_get_base_state_machine(this_controller),
3800                 SCI_BASE_CONTROLLER_STATE_RESET
3801                 );
3802 }
3803
3804 /* --------------------------------------------------------------------------- */
3805
3806 const struct sci_base_state scic_sds_controller_state_table[] = {
3807         [SCI_BASE_CONTROLLER_STATE_INITIAL] = {
3808                 .enter_state = scic_sds_controller_initial_state_enter,
3809         },
3810         [SCI_BASE_CONTROLLER_STATE_RESET] = {},
3811         [SCI_BASE_CONTROLLER_STATE_INITIALIZING] = {},
3812         [SCI_BASE_CONTROLLER_STATE_INITIALIZED] = {},
3813         [SCI_BASE_CONTROLLER_STATE_STARTING] = {
3814                 .exit_state  = scic_sds_controller_starting_state_exit,
3815         },
3816         [SCI_BASE_CONTROLLER_STATE_READY] = {
3817                 .enter_state = scic_sds_controller_ready_state_enter,
3818                 .exit_state  = scic_sds_controller_ready_state_exit,
3819         },
3820         [SCI_BASE_CONTROLLER_STATE_RESETTING] = {
3821                 .enter_state = scic_sds_controller_resetting_state_enter,
3822         },
3823         [SCI_BASE_CONTROLLER_STATE_STOPPING] = {
3824                 .enter_state = scic_sds_controller_stopping_state_enter,
3825                 .exit_state = scic_sds_controller_stopping_state_exit,
3826         },
3827         [SCI_BASE_CONTROLLER_STATE_STOPPED] = {},
3828         [SCI_BASE_CONTROLLER_STATE_FAILED] = {}
3829 };
3830