2 * Linux MegaRAID driver for SAS based RAID controllers
4 * Copyright (c) 2009-2011 LSI Corporation.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 * FILE: megaraid_sas.h
22 * Authors: LSI Corporation
24 * Send feedback to: <megaraidlinux@lsi.com>
26 * Mail to: LSI Corporation, 1621 Barber Lane, Milpitas, CA 95035
30 #ifndef LSI_MEGARAID_SAS_H
31 #define LSI_MEGARAID_SAS_H
34 * MegaRAID SAS Driver meta data
36 #define MEGASAS_VERSION "00.00.05.34-rc1"
37 #define MEGASAS_RELDATE "Feb. 24, 2011"
38 #define MEGASAS_EXT_VERSION "Thu. Feb. 24 17:00:00 PDT 2011"
43 #define PCI_DEVICE_ID_LSI_SAS1078R 0x0060
44 #define PCI_DEVICE_ID_LSI_SAS1078DE 0x007C
45 #define PCI_DEVICE_ID_LSI_VERDE_ZCR 0x0413
46 #define PCI_DEVICE_ID_LSI_SAS1078GEN2 0x0078
47 #define PCI_DEVICE_ID_LSI_SAS0079GEN2 0x0079
48 #define PCI_DEVICE_ID_LSI_SAS0073SKINNY 0x0073
49 #define PCI_DEVICE_ID_LSI_SAS0071SKINNY 0x0071
50 #define PCI_DEVICE_ID_LSI_FUSION 0x005b
53 * =====================================
54 * MegaRAID SAS MFI firmware definitions
55 * =====================================
59 * MFI stands for MegaRAID SAS FW Interface. This is just a moniker for
60 * protocol between the software and firmware. Commands are issued using
65 * FW posts its state in upper 4 bits of outbound_msg_0 register
67 #define MFI_STATE_MASK 0xF0000000
68 #define MFI_STATE_UNDEFINED 0x00000000
69 #define MFI_STATE_BB_INIT 0x10000000
70 #define MFI_STATE_FW_INIT 0x40000000
71 #define MFI_STATE_WAIT_HANDSHAKE 0x60000000
72 #define MFI_STATE_FW_INIT_2 0x70000000
73 #define MFI_STATE_DEVICE_SCAN 0x80000000
74 #define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000
75 #define MFI_STATE_FLUSH_CACHE 0xA0000000
76 #define MFI_STATE_READY 0xB0000000
77 #define MFI_STATE_OPERATIONAL 0xC0000000
78 #define MFI_STATE_FAULT 0xF0000000
79 #define MFI_RESET_REQUIRED 0x00000001
81 #define MEGAMFI_FRAME_SIZE 64
84 * During FW init, clear pending cmds & reset state using inbound_msg_0
86 * ABORT : Abort all pending cmds
87 * READY : Move from OPERATIONAL to READY state; discard queue info
88 * MFIMODE : Discard (possible) low MFA posted in 64-bit mode (??)
89 * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver
90 * HOTPLUG : Resume from Hotplug
91 * MFI_STOP_ADP : Send signal to FW to stop processing
93 #define WRITE_SEQUENCE_OFFSET (0x0000000FC) /* I20 */
94 #define HOST_DIAGNOSTIC_OFFSET (0x000000F8) /* I20 */
95 #define DIAG_WRITE_ENABLE (0x00000080)
96 #define DIAG_RESET_ADAPTER (0x00000004)
98 #define MFI_ADP_RESET 0x00000040
99 #define MFI_INIT_ABORT 0x00000001
100 #define MFI_INIT_READY 0x00000002
101 #define MFI_INIT_MFIMODE 0x00000004
102 #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008
103 #define MFI_INIT_HOTPLUG 0x00000010
104 #define MFI_STOP_ADP 0x00000020
105 #define MFI_RESET_FLAGS MFI_INIT_READY| \
112 #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000
113 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001
114 #define MFI_FRAME_SGL32 0x0000
115 #define MFI_FRAME_SGL64 0x0002
116 #define MFI_FRAME_SENSE32 0x0000
117 #define MFI_FRAME_SENSE64 0x0004
118 #define MFI_FRAME_DIR_NONE 0x0000
119 #define MFI_FRAME_DIR_WRITE 0x0008
120 #define MFI_FRAME_DIR_READ 0x0010
121 #define MFI_FRAME_DIR_BOTH 0x0018
122 #define MFI_FRAME_IEEE 0x0020
125 * Definition for cmd_status
127 #define MFI_CMD_STATUS_POLL_MODE 0xFF
130 * MFI command opcodes
132 #define MFI_CMD_INIT 0x00
133 #define MFI_CMD_LD_READ 0x01
134 #define MFI_CMD_LD_WRITE 0x02
135 #define MFI_CMD_LD_SCSI_IO 0x03
136 #define MFI_CMD_PD_SCSI_IO 0x04
137 #define MFI_CMD_DCMD 0x05
138 #define MFI_CMD_ABORT 0x06
139 #define MFI_CMD_SMP 0x07
140 #define MFI_CMD_STP 0x08
142 #define MR_DCMD_CTRL_GET_INFO 0x01010000
143 #define MR_DCMD_LD_GET_LIST 0x03010000
145 #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000
146 #define MR_FLUSH_CTRL_CACHE 0x01
147 #define MR_FLUSH_DISK_CACHE 0x02
149 #define MR_DCMD_CTRL_SHUTDOWN 0x01050000
150 #define MR_DCMD_HIBERNATE_SHUTDOWN 0x01060000
151 #define MR_ENABLE_DRIVE_SPINDOWN 0x01
153 #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100
154 #define MR_DCMD_CTRL_EVENT_GET 0x01040300
155 #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500
156 #define MR_DCMD_LD_GET_PROPERTIES 0x03030000
158 #define MR_DCMD_CLUSTER 0x08000000
159 #define MR_DCMD_CLUSTER_RESET_ALL 0x08010100
160 #define MR_DCMD_CLUSTER_RESET_LD 0x08010200
161 #define MR_DCMD_PD_LIST_QUERY 0x02010100
164 * MFI command completion codes
168 MFI_STAT_INVALID_CMD = 0x01,
169 MFI_STAT_INVALID_DCMD = 0x02,
170 MFI_STAT_INVALID_PARAMETER = 0x03,
171 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04,
172 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05,
173 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06,
174 MFI_STAT_APP_IN_USE = 0x07,
175 MFI_STAT_APP_NOT_INITIALIZED = 0x08,
176 MFI_STAT_ARRAY_INDEX_INVALID = 0x09,
177 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a,
178 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b,
179 MFI_STAT_DEVICE_NOT_FOUND = 0x0c,
180 MFI_STAT_DRIVE_TOO_SMALL = 0x0d,
181 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e,
182 MFI_STAT_FLASH_BUSY = 0x0f,
183 MFI_STAT_FLASH_ERROR = 0x10,
184 MFI_STAT_FLASH_IMAGE_BAD = 0x11,
185 MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12,
186 MFI_STAT_FLASH_NOT_OPEN = 0x13,
187 MFI_STAT_FLASH_NOT_STARTED = 0x14,
188 MFI_STAT_FLUSH_FAILED = 0x15,
189 MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16,
190 MFI_STAT_LD_CC_IN_PROGRESS = 0x17,
191 MFI_STAT_LD_INIT_IN_PROGRESS = 0x18,
192 MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19,
193 MFI_STAT_LD_MAX_CONFIGURED = 0x1a,
194 MFI_STAT_LD_NOT_OPTIMAL = 0x1b,
195 MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c,
196 MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d,
197 MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e,
198 MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f,
199 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20,
200 MFI_STAT_MFC_HW_ERROR = 0x21,
201 MFI_STAT_NO_HW_PRESENT = 0x22,
202 MFI_STAT_NOT_FOUND = 0x23,
203 MFI_STAT_NOT_IN_ENCL = 0x24,
204 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25,
205 MFI_STAT_PD_TYPE_WRONG = 0x26,
206 MFI_STAT_PR_DISABLED = 0x27,
207 MFI_STAT_ROW_INDEX_INVALID = 0x28,
208 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29,
209 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a,
210 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b,
211 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c,
212 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d,
213 MFI_STAT_SCSI_IO_FAILED = 0x2e,
214 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f,
215 MFI_STAT_SHUTDOWN_FAILED = 0x30,
216 MFI_STAT_TIME_NOT_SET = 0x31,
217 MFI_STAT_WRONG_STATE = 0x32,
218 MFI_STAT_LD_OFFLINE = 0x33,
219 MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34,
220 MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35,
221 MFI_STAT_RESERVATION_IN_PROGRESS = 0x36,
222 MFI_STAT_I2C_ERRORS_DETECTED = 0x37,
223 MFI_STAT_PCI_ERRORS_DETECTED = 0x38,
225 MFI_STAT_INVALID_STATUS = 0xFF
229 * Number of mailbox bytes in DCMD message frame
231 #define MFI_MBOX_SIZE 12
235 MR_EVT_CLASS_DEBUG = -2,
236 MR_EVT_CLASS_PROGRESS = -1,
237 MR_EVT_CLASS_INFO = 0,
238 MR_EVT_CLASS_WARNING = 1,
239 MR_EVT_CLASS_CRITICAL = 2,
240 MR_EVT_CLASS_FATAL = 3,
241 MR_EVT_CLASS_DEAD = 4,
247 MR_EVT_LOCALE_LD = 0x0001,
248 MR_EVT_LOCALE_PD = 0x0002,
249 MR_EVT_LOCALE_ENCL = 0x0004,
250 MR_EVT_LOCALE_BBU = 0x0008,
251 MR_EVT_LOCALE_SAS = 0x0010,
252 MR_EVT_LOCALE_CTRL = 0x0020,
253 MR_EVT_LOCALE_CONFIG = 0x0040,
254 MR_EVT_LOCALE_CLUSTER = 0x0080,
255 MR_EVT_LOCALE_ALL = 0xffff,
262 MR_EVT_ARGS_CDB_SENSE,
264 MR_EVT_ARGS_LD_COUNT,
266 MR_EVT_ARGS_LD_OWNER,
267 MR_EVT_ARGS_LD_LBA_PD_LBA,
269 MR_EVT_ARGS_LD_STATE,
270 MR_EVT_ARGS_LD_STRIP,
274 MR_EVT_ARGS_PD_LBA_LD,
276 MR_EVT_ARGS_PD_STATE,
283 MR_EVT_ARGS_PD_SPARE,
284 MR_EVT_ARGS_PD_INDEX,
285 MR_EVT_ARGS_DIAG_PASS,
286 MR_EVT_ARGS_DIAG_FAIL,
287 MR_EVT_ARGS_PD_LBA_LBA,
288 MR_EVT_ARGS_PORT_PHY,
289 MR_EVT_ARGS_PD_MISSING,
290 MR_EVT_ARGS_PD_ADDRESS,
292 MR_EVT_ARGS_CONNECTOR,
295 MR_EVT_ARGS_PD_PATHINFO,
296 MR_EVT_ARGS_PD_POWER_STATE,
301 * define constants for device list query options
303 enum MR_PD_QUERY_TYPE {
304 MR_PD_QUERY_TYPE_ALL = 0,
305 MR_PD_QUERY_TYPE_STATE = 1,
306 MR_PD_QUERY_TYPE_POWER_STATE = 2,
307 MR_PD_QUERY_TYPE_MEDIA_TYPE = 3,
308 MR_PD_QUERY_TYPE_SPEED = 4,
309 MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5,
312 #define MR_EVT_CFG_CLEARED 0x0004
313 #define MR_EVT_LD_STATE_CHANGE 0x0051
314 #define MR_EVT_PD_INSERTED 0x005b
315 #define MR_EVT_PD_REMOVED 0x0070
316 #define MR_EVT_LD_CREATED 0x008a
317 #define MR_EVT_LD_DELETED 0x008b
318 #define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db
319 #define MR_EVT_LD_OFFLINE 0x00fc
320 #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152
321 #define MAX_LOGICAL_DRIVES 64
324 MR_PD_STATE_UNCONFIGURED_GOOD = 0x00,
325 MR_PD_STATE_UNCONFIGURED_BAD = 0x01,
326 MR_PD_STATE_HOT_SPARE = 0x02,
327 MR_PD_STATE_OFFLINE = 0x10,
328 MR_PD_STATE_FAILED = 0x11,
329 MR_PD_STATE_REBUILD = 0x14,
330 MR_PD_STATE_ONLINE = 0x18,
331 MR_PD_STATE_COPYBACK = 0x20,
332 MR_PD_STATE_SYSTEM = 0x40,
337 * defines the physical drive address structure
339 struct MR_PD_ADDRESS {
350 u8 enclConnectorIndex;
355 u8 connectedPortBitmap;
356 u8 connectedPortNumbers;
362 * defines the physical drive list structure
367 struct MR_PD_ADDRESS addr[1];
370 struct megasas_pd_list {
377 * defines the logical drive reference structure
389 * defines the logical drive list structure
399 } ldList[MAX_LOGICAL_DRIVES];
403 * SAS controller properties
405 struct megasas_ctrl_prop {
408 u16 pred_fail_poll_interval;
409 u16 intr_throttle_count;
410 u16 intr_throttle_timeouts;
416 u8 cache_flush_interval;
422 u8 disable_auto_rebuild;
423 u8 disable_battery_warn;
425 u16 ecc_bucket_leak_rate;
426 u8 restore_hotspare_on_insertion;
427 u8 expose_encl_devices;
428 u8 maintainPdFailHistory;
429 u8 disallowHostRequestReordering;
432 u8 disableAutoDetectBackplane;
437 * Add properties that can be controlled by
438 * a bit in the following structure.
441 u32 copyBackDisabled : 1;
442 u32 SMARTerEnabled : 1;
443 u32 prCorrectUnconfiguredAreas : 1;
446 u32 SSDSMARTerEnabled : 1;
447 u32 SSDPatrolReadEnabled : 1;
448 u32 enableSpinDownUnconfigured : 1;
449 u32 autoEnhancedImport : 1;
450 u32 enableSecretKeyControl : 1;
451 u32 disableOnlineCtrlReset : 1;
452 u32 allowBootWithPinnedCache : 1;
453 u32 disableSpinDownHS : 1;
464 * SAS controller information
466 struct megasas_ctrl_info {
469 * PCI device information
479 } __attribute__ ((packed)) pci;
482 * Host interface information
495 } __attribute__ ((packed)) host_interface;
498 * Device (backend) interface information
511 } __attribute__ ((packed)) device_interface;
514 * List of components residing in flash. All str are null terminated
516 u32 image_check_word;
517 u32 image_component_count;
526 } __attribute__ ((packed)) image_component[8];
529 * List of flash components that have been flashed on the card, but
530 * are not in use, pending reset of the adapter. This list will be
531 * empty if a flash operation has not occurred. All stings are null
534 u32 pending_image_component_count;
543 } __attribute__ ((packed)) pending_image_component[8];
550 char product_name[80];
554 * Other physical/controller/operation information. Indicates the
555 * presence of the hardware
565 } __attribute__ ((packed)) hw_present;
570 * Maximum data transfer sizes
572 u16 max_concurrent_cmds;
574 u32 max_request_size;
577 * Logical and physical device counts
579 u16 ld_present_count;
580 u16 ld_degraded_count;
581 u16 ld_offline_count;
583 u16 pd_present_count;
584 u16 pd_disk_present_count;
585 u16 pd_disk_pred_failure_count;
586 u16 pd_disk_failed_count;
589 * Memory size information
598 u16 mem_correctable_error_count;
599 u16 mem_uncorrectable_error_count;
602 * Cluster information
604 u8 cluster_permitted;
608 * Additional max data transfer sizes
610 u16 max_strips_per_io;
613 * Controller capabilities structures
624 } __attribute__ ((packed)) raid_levels;
634 u32 cluster_supported:1;
636 u32 spanning_allowed:1;
637 u32 dedicated_hotspares:1;
638 u32 revertible_hotspares:1;
639 u32 foreign_config_import:1;
640 u32 self_diagnostic:1;
641 u32 mixed_redundancy_arr:1;
642 u32 global_hot_spares:1;
645 } __attribute__ ((packed)) adapter_operations;
653 u32 disk_cache_policy:1;
656 } __attribute__ ((packed)) ld_operations;
664 } __attribute__ ((packed)) stripe_sz_ops;
673 } __attribute__ ((packed)) pd_operations;
677 u32 ctrl_supports_sas:1;
678 u32 ctrl_supports_sata:1;
679 u32 allow_mix_in_encl:1;
680 u32 allow_mix_in_ld:1;
681 u32 allow_sata_in_cluster:1;
684 } __attribute__ ((packed)) pd_mix_support;
687 * Define ECC single-bit-error bucket information
693 * Include the controller properties (changeable items)
695 struct megasas_ctrl_prop properties;
698 * Define FW pkg version (set in envt v'bles on OEM basis)
700 char package_version[0x60];
702 u8 pad[0x800 - 0x6a0];
707 * ===============================
708 * MegaRAID SAS driver definitions
709 * ===============================
711 #define MEGASAS_MAX_PD_CHANNELS 2
712 #define MEGASAS_MAX_LD_CHANNELS 2
713 #define MEGASAS_MAX_CHANNELS (MEGASAS_MAX_PD_CHANNELS + \
714 MEGASAS_MAX_LD_CHANNELS)
715 #define MEGASAS_MAX_DEV_PER_CHANNEL 128
716 #define MEGASAS_DEFAULT_INIT_ID -1
717 #define MEGASAS_MAX_LUN 8
718 #define MEGASAS_MAX_LD 64
719 #define MEGASAS_DEFAULT_CMD_PER_LUN 128
720 #define MEGASAS_MAX_PD (MEGASAS_MAX_PD_CHANNELS * \
721 MEGASAS_MAX_DEV_PER_CHANNEL)
722 #define MEGASAS_MAX_LD_IDS (MEGASAS_MAX_LD_CHANNELS * \
723 MEGASAS_MAX_DEV_PER_CHANNEL)
725 #define MEGASAS_MAX_SECTORS (2*1024)
726 #define MEGASAS_MAX_SECTORS_IEEE (2*128)
727 #define MEGASAS_DBG_LVL 1
729 #define MEGASAS_FW_BUSY 1
733 #define PTHRU_FRAME 1
736 * When SCSI mid-layer calls driver's reset routine, driver waits for
737 * MEGASAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note
738 * that the driver cannot _actually_ abort or reset pending commands. While
739 * it is waiting for the commands to complete, it prints a diagnostic message
740 * every MEGASAS_RESET_NOTICE_INTERVAL seconds
742 #define MEGASAS_RESET_WAIT_TIME 180
743 #define MEGASAS_INTERNAL_CMD_WAIT_TIME 180
744 #define MEGASAS_RESET_NOTICE_INTERVAL 5
745 #define MEGASAS_IOCTL_CMD 0
746 #define MEGASAS_DEFAULT_CMD_TIMEOUT 90
749 * FW reports the maximum of number of commands that it can accept (maximum
750 * commands that can be outstanding) at any time. The driver must report a
751 * lower number to the mid layer because it can issue a few internal commands
752 * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs
755 #define MEGASAS_INT_CMDS 32
756 #define MEGASAS_SKINNY_INT_CMDS 5
759 * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit
760 * SGLs based on the size of dma_addr_t
762 #define IS_DMA64 (sizeof(dma_addr_t) == 8)
764 #define MFI_XSCALE_OMR0_CHANGE_INTERRUPT 0x00000001
766 #define MFI_INTR_FLAG_REPLY_MESSAGE 0x00000001
767 #define MFI_INTR_FLAG_FIRMWARE_STATE_CHANGE 0x00000002
768 #define MFI_G2_OUTBOUND_DOORBELL_CHANGE_INTERRUPT 0x00000004
770 #define MFI_OB_INTR_STATUS_MASK 0x00000002
771 #define MFI_POLL_TIMEOUT_SECS 60
772 #define MEGASAS_COMPLETION_TIMER_INTERVAL (HZ/10)
774 #define MFI_REPLY_1078_MESSAGE_INTERRUPT 0x80000000
775 #define MFI_REPLY_GEN2_MESSAGE_INTERRUPT 0x00000001
776 #define MFI_GEN2_ENABLE_INTERRUPT_MASK (0x00000001 | 0x00000004)
777 #define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT 0x40000000
778 #define MFI_SKINNY_ENABLE_INTERRUPT_MASK (0x00000001)
780 #define MFI_1068_PCSR_OFFSET 0x84
781 #define MFI_1068_FW_HANDSHAKE_OFFSET 0x64
782 #define MFI_1068_FW_READY 0xDDDD0000
784 * register set for both 1068 and 1078 controllers
785 * structure extended for 1078 registers
788 struct megasas_register_set {
789 u32 doorbell; /*0000h*/
790 u32 fusion_seq_offset; /*0004h*/
791 u32 fusion_host_diag; /*0008h*/
792 u32 reserved_01; /*000Ch*/
794 u32 inbound_msg_0; /*0010h*/
795 u32 inbound_msg_1; /*0014h*/
796 u32 outbound_msg_0; /*0018h*/
797 u32 outbound_msg_1; /*001Ch*/
799 u32 inbound_doorbell; /*0020h*/
800 u32 inbound_intr_status; /*0024h*/
801 u32 inbound_intr_mask; /*0028h*/
803 u32 outbound_doorbell; /*002Ch*/
804 u32 outbound_intr_status; /*0030h*/
805 u32 outbound_intr_mask; /*0034h*/
807 u32 reserved_1[2]; /*0038h*/
809 u32 inbound_queue_port; /*0040h*/
810 u32 outbound_queue_port; /*0044h*/
812 u32 reserved_2[9]; /*0048h*/
813 u32 reply_post_host_index; /*006Ch*/
814 u32 reserved_2_2[12]; /*0070h*/
816 u32 outbound_doorbell_clear; /*00A0h*/
818 u32 reserved_3[3]; /*00A4h*/
820 u32 outbound_scratch_pad ; /*00B0h*/
821 u32 outbound_scratch_pad_2; /*00B4h*/
823 u32 reserved_4[2]; /*00B8h*/
825 u32 inbound_low_queue_port ; /*00C0h*/
827 u32 inbound_high_queue_port ; /*00C4h*/
829 u32 reserved_5; /*00C8h*/
830 u32 res_6[11]; /*CCh*/
833 u32 index_registers[807]; /*00CCh*/
834 } __attribute__ ((packed));
836 struct megasas_sge32 {
841 } __attribute__ ((packed));
843 struct megasas_sge64 {
848 } __attribute__ ((packed));
850 struct megasas_sge_skinny {
858 struct megasas_sge32 sge32[1];
859 struct megasas_sge64 sge64[1];
860 struct megasas_sge_skinny sge_skinny[1];
862 } __attribute__ ((packed));
864 struct megasas_header {
867 u8 sense_len; /*01h */
868 u8 cmd_status; /*02h */
869 u8 scsi_status; /*03h */
871 u8 target_id; /*04h */
874 u8 sge_count; /*07h */
876 u32 context; /*08h */
880 u16 timeout; /*12h */
881 u32 data_xferlen; /*14h */
883 } __attribute__ ((packed));
885 union megasas_sgl_frame {
887 struct megasas_sge32 sge32[8];
888 struct megasas_sge64 sge64[5];
890 } __attribute__ ((packed));
892 struct megasas_init_frame {
895 u8 reserved_0; /*01h */
896 u8 cmd_status; /*02h */
898 u8 reserved_1; /*03h */
899 u32 reserved_2; /*04h */
901 u32 context; /*08h */
905 u16 reserved_3; /*12h */
906 u32 data_xfer_len; /*14h */
908 u32 queue_info_new_phys_addr_lo; /*18h */
909 u32 queue_info_new_phys_addr_hi; /*1Ch */
910 u32 queue_info_old_phys_addr_lo; /*20h */
911 u32 queue_info_old_phys_addr_hi; /*24h */
913 u32 reserved_4[6]; /*28h */
915 } __attribute__ ((packed));
917 struct megasas_init_queue_info {
919 u32 init_flags; /*00h */
920 u32 reply_queue_entries; /*04h */
922 u32 reply_queue_start_phys_addr_lo; /*08h */
923 u32 reply_queue_start_phys_addr_hi; /*0Ch */
924 u32 producer_index_phys_addr_lo; /*10h */
925 u32 producer_index_phys_addr_hi; /*14h */
926 u32 consumer_index_phys_addr_lo; /*18h */
927 u32 consumer_index_phys_addr_hi; /*1Ch */
929 } __attribute__ ((packed));
931 struct megasas_io_frame {
934 u8 sense_len; /*01h */
935 u8 cmd_status; /*02h */
936 u8 scsi_status; /*03h */
938 u8 target_id; /*04h */
939 u8 access_byte; /*05h */
940 u8 reserved_0; /*06h */
941 u8 sge_count; /*07h */
943 u32 context; /*08h */
947 u16 timeout; /*12h */
948 u32 lba_count; /*14h */
950 u32 sense_buf_phys_addr_lo; /*18h */
951 u32 sense_buf_phys_addr_hi; /*1Ch */
953 u32 start_lba_lo; /*20h */
954 u32 start_lba_hi; /*24h */
956 union megasas_sgl sgl; /*28h */
958 } __attribute__ ((packed));
960 struct megasas_pthru_frame {
963 u8 sense_len; /*01h */
964 u8 cmd_status; /*02h */
965 u8 scsi_status; /*03h */
967 u8 target_id; /*04h */
970 u8 sge_count; /*07h */
972 u32 context; /*08h */
976 u16 timeout; /*12h */
977 u32 data_xfer_len; /*14h */
979 u32 sense_buf_phys_addr_lo; /*18h */
980 u32 sense_buf_phys_addr_hi; /*1Ch */
983 union megasas_sgl sgl; /*30h */
985 } __attribute__ ((packed));
987 struct megasas_dcmd_frame {
990 u8 reserved_0; /*01h */
991 u8 cmd_status; /*02h */
992 u8 reserved_1[4]; /*03h */
993 u8 sge_count; /*07h */
995 u32 context; /*08h */
999 u16 timeout; /*12h */
1001 u32 data_xfer_len; /*14h */
1002 u32 opcode; /*18h */
1010 union megasas_sgl sgl; /*28h */
1012 } __attribute__ ((packed));
1014 struct megasas_abort_frame {
1017 u8 reserved_0; /*01h */
1018 u8 cmd_status; /*02h */
1020 u8 reserved_1; /*03h */
1021 u32 reserved_2; /*04h */
1023 u32 context; /*08h */
1027 u16 reserved_3; /*12h */
1028 u32 reserved_4; /*14h */
1030 u32 abort_context; /*18h */
1033 u32 abort_mfi_phys_addr_lo; /*20h */
1034 u32 abort_mfi_phys_addr_hi; /*24h */
1036 u32 reserved_5[6]; /*28h */
1038 } __attribute__ ((packed));
1040 struct megasas_smp_frame {
1043 u8 reserved_1; /*01h */
1044 u8 cmd_status; /*02h */
1045 u8 connection_status; /*03h */
1047 u8 reserved_2[3]; /*04h */
1048 u8 sge_count; /*07h */
1050 u32 context; /*08h */
1054 u16 timeout; /*12h */
1056 u32 data_xfer_len; /*14h */
1057 u64 sas_addr; /*18h */
1060 struct megasas_sge32 sge32[2]; /* [0]: resp [1]: req */
1061 struct megasas_sge64 sge64[2]; /* [0]: resp [1]: req */
1064 } __attribute__ ((packed));
1066 struct megasas_stp_frame {
1069 u8 reserved_1; /*01h */
1070 u8 cmd_status; /*02h */
1071 u8 reserved_2; /*03h */
1073 u8 target_id; /*04h */
1074 u8 reserved_3[2]; /*05h */
1075 u8 sge_count; /*07h */
1077 u32 context; /*08h */
1081 u16 timeout; /*12h */
1083 u32 data_xfer_len; /*14h */
1085 u16 fis[10]; /*18h */
1089 struct megasas_sge32 sge32[2]; /* [0]: resp [1]: data */
1090 struct megasas_sge64 sge64[2]; /* [0]: resp [1]: data */
1093 } __attribute__ ((packed));
1095 union megasas_frame {
1097 struct megasas_header hdr;
1098 struct megasas_init_frame init;
1099 struct megasas_io_frame io;
1100 struct megasas_pthru_frame pthru;
1101 struct megasas_dcmd_frame dcmd;
1102 struct megasas_abort_frame abort;
1103 struct megasas_smp_frame smp;
1104 struct megasas_stp_frame stp;
1111 union megasas_evt_class_locale {
1117 } __attribute__ ((packed)) members;
1121 } __attribute__ ((packed));
1123 struct megasas_evt_log_info {
1127 u32 shutdown_seq_num;
1130 } __attribute__ ((packed));
1132 struct megasas_progress {
1135 u16 elapsed_seconds;
1137 } __attribute__ ((packed));
1139 struct megasas_evtarg_ld {
1145 } __attribute__ ((packed));
1147 struct megasas_evtarg_pd {
1152 } __attribute__ ((packed));
1154 struct megasas_evt_detail {
1159 union megasas_evt_class_locale cl;
1165 struct megasas_evtarg_pd pd;
1171 } __attribute__ ((packed)) cdbSense;
1173 struct megasas_evtarg_ld ld;
1176 struct megasas_evtarg_ld ld;
1178 } __attribute__ ((packed)) ld_count;
1182 struct megasas_evtarg_ld ld;
1183 } __attribute__ ((packed)) ld_lba;
1186 struct megasas_evtarg_ld ld;
1189 } __attribute__ ((packed)) ld_owner;
1194 struct megasas_evtarg_ld ld;
1195 struct megasas_evtarg_pd pd;
1196 } __attribute__ ((packed)) ld_lba_pd_lba;
1199 struct megasas_evtarg_ld ld;
1200 struct megasas_progress prog;
1201 } __attribute__ ((packed)) ld_prog;
1204 struct megasas_evtarg_ld ld;
1207 } __attribute__ ((packed)) ld_state;
1211 struct megasas_evtarg_ld ld;
1212 } __attribute__ ((packed)) ld_strip;
1214 struct megasas_evtarg_pd pd;
1217 struct megasas_evtarg_pd pd;
1219 } __attribute__ ((packed)) pd_err;
1223 struct megasas_evtarg_pd pd;
1224 } __attribute__ ((packed)) pd_lba;
1228 struct megasas_evtarg_pd pd;
1229 struct megasas_evtarg_ld ld;
1230 } __attribute__ ((packed)) pd_lba_ld;
1233 struct megasas_evtarg_pd pd;
1234 struct megasas_progress prog;
1235 } __attribute__ ((packed)) pd_prog;
1238 struct megasas_evtarg_pd pd;
1241 } __attribute__ ((packed)) pd_state;
1248 } __attribute__ ((packed)) pci;
1256 } __attribute__ ((packed)) time;
1262 } __attribute__ ((packed)) ecc;
1270 char description[128];
1272 } __attribute__ ((packed));
1274 struct megasas_aen_event {
1275 struct work_struct hotplug_work;
1276 struct megasas_instance *instance;
1279 struct megasas_instance {
1282 dma_addr_t producer_h;
1284 dma_addr_t consumer_h;
1287 dma_addr_t reply_queue_h;
1289 unsigned long base_addr;
1290 struct megasas_register_set __iomem *reg_set;
1292 struct megasas_pd_list pd_list[MEGASAS_MAX_PD];
1293 u8 ld_ids[MEGASAS_MAX_LD_IDS];
1298 /* For Fusion its num IOCTL cmds, for others MFI based its
1301 u32 max_sectors_per_req;
1302 struct megasas_aen_event *ev;
1304 struct megasas_cmd **cmd_list;
1305 struct list_head cmd_pool;
1306 /* used to sync fire the cmd to fw */
1307 spinlock_t cmd_pool_lock;
1308 /* used to sync fire the cmd to fw */
1309 spinlock_t hba_lock;
1310 /* used to synch producer, consumer ptrs in dpc */
1311 spinlock_t completion_lock;
1312 struct dma_pool *frame_dma_pool;
1313 struct dma_pool *sense_dma_pool;
1315 struct megasas_evt_detail *evt_detail;
1316 dma_addr_t evt_detail_h;
1317 struct megasas_cmd *aen_cmd;
1318 struct mutex aen_mutex;
1319 struct semaphore ioctl_sem;
1321 struct Scsi_Host *host;
1323 wait_queue_head_t int_cmd_wait_q;
1324 wait_queue_head_t abort_cmd_wait_q;
1326 struct pci_dev *pdev;
1328 u32 fw_support_ieee;
1330 atomic_t fw_outstanding;
1331 atomic_t fw_reset_no_pci_access;
1333 struct megasas_instance_template *instancet;
1334 struct tasklet_struct isr_tasklet;
1335 struct work_struct work_init;
1341 u8 disableOnlineCtrlReset;
1343 unsigned long last_time;
1347 struct timer_list io_completion_timer;
1348 struct list_head internal_reset_pending_q;
1350 /* Ptr to hba specific information */
1353 struct msix_entry msixentry;
1355 struct megasas_cmd *map_update_cmd;
1358 struct mutex reset_mutex;
1362 MEGASAS_HBA_OPERATIONAL = 0,
1363 MEGASAS_ADPRESET_SM_INFAULT = 1,
1364 MEGASAS_ADPRESET_SM_FW_RESET_SUCCESS = 2,
1365 MEGASAS_ADPRESET_SM_OPERATIONAL = 3,
1366 MEGASAS_HW_CRITICAL_ERROR = 4,
1367 MEGASAS_ADPRESET_INPROG_SIGN = 0xDEADDEAD,
1370 struct megasas_instance_template {
1371 void (*fire_cmd)(struct megasas_instance *, dma_addr_t, \
1372 u32, struct megasas_register_set __iomem *);
1374 void (*enable_intr)(struct megasas_register_set __iomem *) ;
1375 void (*disable_intr)(struct megasas_register_set __iomem *);
1377 int (*clear_intr)(struct megasas_register_set __iomem *);
1379 u32 (*read_fw_status_reg)(struct megasas_register_set __iomem *);
1380 int (*adp_reset)(struct megasas_instance *, \
1381 struct megasas_register_set __iomem *);
1382 int (*check_reset)(struct megasas_instance *, \
1383 struct megasas_register_set __iomem *);
1384 irqreturn_t (*service_isr)(int irq, void *devp);
1385 void (*tasklet)(unsigned long);
1386 u32 (*init_adapter)(struct megasas_instance *);
1387 u32 (*build_and_issue_cmd) (struct megasas_instance *,
1388 struct scsi_cmnd *);
1389 void (*issue_dcmd) (struct megasas_instance *instance,
1390 struct megasas_cmd *cmd);
1393 #define MEGASAS_IS_LOGICAL(scp) \
1394 (scp->device->channel < MEGASAS_MAX_PD_CHANNELS) ? 0 : 1
1396 #define MEGASAS_DEV_INDEX(inst, scp) \
1397 ((scp->device->channel % 2) * MEGASAS_MAX_DEV_PER_CHANNEL) + \
1400 struct megasas_cmd {
1402 union megasas_frame *frame;
1403 dma_addr_t frame_phys_addr;
1405 dma_addr_t sense_phys_addr;
1411 u8 retry_for_fw_reset;
1414 struct list_head list;
1415 struct scsi_cmnd *scmd;
1416 struct megasas_instance *instance;
1426 #define MAX_MGMT_ADAPTERS 1024
1427 #define MAX_IOCTL_SGE 16
1429 struct megasas_iocpacket {
1439 struct megasas_header hdr;
1442 struct iovec sgl[MAX_IOCTL_SGE];
1444 } __attribute__ ((packed));
1446 struct megasas_aen {
1450 u32 class_locale_word;
1451 } __attribute__ ((packed));
1453 #ifdef CONFIG_COMPAT
1454 struct compat_megasas_iocpacket {
1463 struct megasas_header hdr;
1465 struct compat_iovec sgl[MAX_IOCTL_SGE];
1466 } __attribute__ ((packed));
1468 #define MEGASAS_IOC_FIRMWARE32 _IOWR('M', 1, struct compat_megasas_iocpacket)
1471 #define MEGASAS_IOC_FIRMWARE _IOWR('M', 1, struct megasas_iocpacket)
1472 #define MEGASAS_IOC_GET_AEN _IOW('M', 3, struct megasas_aen)
1474 struct megasas_mgmt_info {
1477 struct megasas_instance *instance[MAX_MGMT_ADAPTERS];
1481 #define msi_control_reg(base) (base + PCI_MSI_FLAGS)
1482 #define PCI_MSIX_FLAGS_ENABLE (1 << 15)
1484 #endif /*LSI_MEGARAID_SAS_H */