2 * Copyright (c) 2000-2014 LSI Corporation.
6 * Title: MPI Message independent structures and definitions
7 * including System Interface Register Set and
8 * scatter/gather formats.
9 * Creation Date: June 21, 2006
11 * mpi2.h Version: 02.00.32
16 * Date Version Description
17 * -------- -------- ------------------------------------------------------
18 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
19 * 06-04-07 02.00.01 Bumped MPI2_HEADER_VERSION_UNIT.
20 * 06-26-07 02.00.02 Bumped MPI2_HEADER_VERSION_UNIT.
21 * 08-31-07 02.00.03 Bumped MPI2_HEADER_VERSION_UNIT.
22 * Moved ReplyPostHostIndex register to offset 0x6C of the
23 * MPI2_SYSTEM_INTERFACE_REGS and modified the define for
24 * MPI2_REPLY_POST_HOST_INDEX_OFFSET.
25 * Added union of request descriptors.
26 * Added union of reply descriptors.
27 * 10-31-07 02.00.04 Bumped MPI2_HEADER_VERSION_UNIT.
28 * Added define for MPI2_VERSION_02_00.
29 * Fixed the size of the FunctionDependent5 field in the
30 * MPI2_DEFAULT_REPLY structure.
31 * 12-18-07 02.00.05 Bumped MPI2_HEADER_VERSION_UNIT.
32 * Removed the MPI-defined Fault Codes and extended the
33 * product specific codes up to 0xEFFF.
34 * Added a sixth key value for the WriteSequence register
35 * and changed the flush value to 0x0.
36 * Added message function codes for Diagnostic Buffer Post
37 * and Diagnsotic Release.
38 * New IOCStatus define: MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED
39 * Moved MPI2_VERSION_UNION from mpi2_ioc.h.
40 * 02-29-08 02.00.06 Bumped MPI2_HEADER_VERSION_UNIT.
41 * 03-03-08 02.00.07 Bumped MPI2_HEADER_VERSION_UNIT.
42 * 05-21-08 02.00.08 Bumped MPI2_HEADER_VERSION_UNIT.
43 * Added #defines for marking a reply descriptor as unused.
44 * 06-27-08 02.00.09 Bumped MPI2_HEADER_VERSION_UNIT.
45 * 10-02-08 02.00.10 Bumped MPI2_HEADER_VERSION_UNIT.
46 * Moved LUN field defines from mpi2_init.h.
47 * 01-19-09 02.00.11 Bumped MPI2_HEADER_VERSION_UNIT.
48 * 05-06-09 02.00.12 Bumped MPI2_HEADER_VERSION_UNIT.
49 * In all request and reply descriptors, replaced VF_ID
50 * field with MSIxIndex field.
51 * Removed DevHandle field from
52 * MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR and made those
54 * Added RAID Accelerator functionality.
55 * 07-30-09 02.00.13 Bumped MPI2_HEADER_VERSION_UNIT.
56 * 10-28-09 02.00.14 Bumped MPI2_HEADER_VERSION_UNIT.
57 * Added MSI-x index mask and shift for Reply Post Host
59 * Added function code for Host Based Discovery Action.
60 * 02-10-10 02.00.15 Bumped MPI2_HEADER_VERSION_UNIT.
61 * Added define for MPI2_FUNCTION_PWR_MGMT_CONTROL.
62 * Added defines for product-specific range of message
63 * function codes, 0xF0 to 0xFF.
64 * 05-12-10 02.00.16 Bumped MPI2_HEADER_VERSION_UNIT.
65 * Added alternative defines for the SGE Direction bit.
66 * 08-11-10 02.00.17 Bumped MPI2_HEADER_VERSION_UNIT.
67 * 11-10-10 02.00.18 Bumped MPI2_HEADER_VERSION_UNIT.
68 * Added MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR define.
69 * 02-23-11 02.00.19 Bumped MPI2_HEADER_VERSION_UNIT.
70 * Added MPI2_FUNCTION_SEND_HOST_MESSAGE.
71 * 03-09-11 02.00.20 Bumped MPI2_HEADER_VERSION_UNIT.
72 * 05-25-11 02.00.21 Bumped MPI2_HEADER_VERSION_UNIT.
73 * 08-24-11 02.00.22 Bumped MPI2_HEADER_VERSION_UNIT.
74 * 11-18-11 02.00.23 Bumped MPI2_HEADER_VERSION_UNIT.
75 * 02-06-12 02.00.24 Bumped MPI2_HEADER_VERSION_UNIT.
76 * 03-29-12 02.00.25 Bumped MPI2_HEADER_VERSION_UNIT.
77 * Added Hard Reset delay timings.
78 * 07-10-12 02.00.26 Bumped MPI2_HEADER_VERSION_UNIT.
79 * 07-26-12 02.00.27 Bumped MPI2_HEADER_VERSION_UNIT.
80 * 11-27-12 02.00.28 Bumped MPI2_HEADER_VERSION_UNIT.
81 * 12-20-12 02.00.29 Bumped MPI2_HEADER_VERSION_UNIT.
82 * Added MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET.
83 * 04-09-13 02.00.30 Bumped MPI2_HEADER_VERSION_UNIT.
84 * 04-17-13 02.00.31 Bumped MPI2_HEADER_VERSION_UNIT.
85 * 08-19-13 02.00.32 Bumped MPI2_HEADER_VERSION_UNIT.
86 * --------------------------------------------------------------------------
93 /*****************************************************************************
95 * MPI Version Definitions
97 *****************************************************************************/
99 #define MPI2_VERSION_MAJOR (0x02)
100 #define MPI2_VERSION_MINOR (0x00)
101 #define MPI2_VERSION_MAJOR_MASK (0xFF00)
102 #define MPI2_VERSION_MAJOR_SHIFT (8)
103 #define MPI2_VERSION_MINOR_MASK (0x00FF)
104 #define MPI2_VERSION_MINOR_SHIFT (0)
105 #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
108 #define MPI2_VERSION_02_00 (0x0200)
110 /* versioning for this MPI header set */
111 #define MPI2_HEADER_VERSION_UNIT (0x20)
112 #define MPI2_HEADER_VERSION_DEV (0x00)
113 #define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00)
114 #define MPI2_HEADER_VERSION_UNIT_SHIFT (8)
115 #define MPI2_HEADER_VERSION_DEV_MASK (0x00FF)
116 #define MPI2_HEADER_VERSION_DEV_SHIFT (0)
117 #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | MPI2_HEADER_VERSION_DEV)
120 /*****************************************************************************
122 * IOC State Definitions
124 *****************************************************************************/
126 #define MPI2_IOC_STATE_RESET (0x00000000)
127 #define MPI2_IOC_STATE_READY (0x10000000)
128 #define MPI2_IOC_STATE_OPERATIONAL (0x20000000)
129 #define MPI2_IOC_STATE_FAULT (0x40000000)
131 #define MPI2_IOC_STATE_MASK (0xF0000000)
132 #define MPI2_IOC_STATE_SHIFT (28)
134 /* Fault state range for prodcut specific codes */
135 #define MPI2_FAULT_PRODUCT_SPECIFIC_MIN (0x0000)
136 #define MPI2_FAULT_PRODUCT_SPECIFIC_MAX (0xEFFF)
139 /*****************************************************************************
141 * System Interface Register Definitions
143 *****************************************************************************/
145 typedef volatile struct _MPI2_SYSTEM_INTERFACE_REGS
147 U32 Doorbell; /* 0x00 */
148 U32 WriteSequence; /* 0x04 */
149 U32 HostDiagnostic; /* 0x08 */
150 U32 Reserved1; /* 0x0C */
151 U32 DiagRWData; /* 0x10 */
152 U32 DiagRWAddressLow; /* 0x14 */
153 U32 DiagRWAddressHigh; /* 0x18 */
154 U32 Reserved2[5]; /* 0x1C */
155 U32 HostInterruptStatus; /* 0x30 */
156 U32 HostInterruptMask; /* 0x34 */
157 U32 DCRData; /* 0x38 */
158 U32 DCRAddress; /* 0x3C */
159 U32 Reserved3[2]; /* 0x40 */
160 U32 ReplyFreeHostIndex; /* 0x48 */
161 U32 Reserved4[8]; /* 0x4C */
162 U32 ReplyPostHostIndex; /* 0x6C */
163 U32 Reserved5; /* 0x70 */
164 U32 HCBSize; /* 0x74 */
165 U32 HCBAddressLow; /* 0x78 */
166 U32 HCBAddressHigh; /* 0x7C */
167 U32 Reserved6[16]; /* 0x80 */
168 U32 RequestDescriptorPostLow; /* 0xC0 */
169 U32 RequestDescriptorPostHigh; /* 0xC4 */
170 U32 Reserved7[14]; /* 0xC8 */
171 } MPI2_SYSTEM_INTERFACE_REGS, MPI2_POINTER PTR_MPI2_SYSTEM_INTERFACE_REGS,
172 Mpi2SystemInterfaceRegs_t, MPI2_POINTER pMpi2SystemInterfaceRegs_t;
175 * Defines for working with the Doorbell register.
177 #define MPI2_DOORBELL_OFFSET (0x00000000)
179 /* IOC --> System values */
180 #define MPI2_DOORBELL_USED (0x08000000)
181 #define MPI2_DOORBELL_WHO_INIT_MASK (0x07000000)
182 #define MPI2_DOORBELL_WHO_INIT_SHIFT (24)
183 #define MPI2_DOORBELL_FAULT_CODE_MASK (0x0000FFFF)
184 #define MPI2_DOORBELL_DATA_MASK (0x0000FFFF)
186 /* System --> IOC values */
187 #define MPI2_DOORBELL_FUNCTION_MASK (0xFF000000)
188 #define MPI2_DOORBELL_FUNCTION_SHIFT (24)
189 #define MPI2_DOORBELL_ADD_DWORDS_MASK (0x00FF0000)
190 #define MPI2_DOORBELL_ADD_DWORDS_SHIFT (16)
194 * Defines for the WriteSequence register
196 #define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004)
197 #define MPI2_WRSEQ_KEY_VALUE_MASK (0x0000000F)
198 #define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0)
199 #define MPI2_WRSEQ_1ST_KEY_VALUE (0xF)
200 #define MPI2_WRSEQ_2ND_KEY_VALUE (0x4)
201 #define MPI2_WRSEQ_3RD_KEY_VALUE (0xB)
202 #define MPI2_WRSEQ_4TH_KEY_VALUE (0x2)
203 #define MPI2_WRSEQ_5TH_KEY_VALUE (0x7)
204 #define MPI2_WRSEQ_6TH_KEY_VALUE (0xD)
207 * Defines for the HostDiagnostic register
209 #define MPI2_HOST_DIAGNOSTIC_OFFSET (0x00000008)
211 #define MPI2_DIAG_BOOT_DEVICE_SELECT_MASK (0x00001800)
212 #define MPI2_DIAG_BOOT_DEVICE_SELECT_DEFAULT (0x00000000)
213 #define MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW (0x00000800)
215 #define MPI2_DIAG_CLEAR_FLASH_BAD_SIG (0x00000400)
216 #define MPI2_DIAG_FORCE_HCB_ON_RESET (0x00000200)
217 #define MPI2_DIAG_HCB_MODE (0x00000100)
218 #define MPI2_DIAG_DIAG_WRITE_ENABLE (0x00000080)
219 #define MPI2_DIAG_FLASH_BAD_SIG (0x00000040)
220 #define MPI2_DIAG_RESET_HISTORY (0x00000020)
221 #define MPI2_DIAG_DIAG_RW_ENABLE (0x00000010)
222 #define MPI2_DIAG_RESET_ADAPTER (0x00000004)
223 #define MPI2_DIAG_HOLD_IOC_RESET (0x00000002)
226 * Offsets for DiagRWData and address
228 #define MPI2_DIAG_RW_DATA_OFFSET (0x00000010)
229 #define MPI2_DIAG_RW_ADDRESS_LOW_OFFSET (0x00000014)
230 #define MPI2_DIAG_RW_ADDRESS_HIGH_OFFSET (0x00000018)
233 * Defines for the HostInterruptStatus register
235 #define MPI2_HOST_INTERRUPT_STATUS_OFFSET (0x00000030)
236 #define MPI2_HIS_SYS2IOC_DB_STATUS (0x80000000)
237 #define MPI2_HIS_IOP_DOORBELL_STATUS MPI2_HIS_SYS2IOC_DB_STATUS
238 #define MPI2_HIS_RESET_IRQ_STATUS (0x40000000)
239 #define MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT (0x00000008)
240 #define MPI2_HIS_IOC2SYS_DB_STATUS (0x00000001)
241 #define MPI2_HIS_DOORBELL_INTERRUPT MPI2_HIS_IOC2SYS_DB_STATUS
244 * Defines for the HostInterruptMask register
246 #define MPI2_HOST_INTERRUPT_MASK_OFFSET (0x00000034)
247 #define MPI2_HIM_RESET_IRQ_MASK (0x40000000)
248 #define MPI2_HIM_REPLY_INT_MASK (0x00000008)
249 #define MPI2_HIM_RIM MPI2_HIM_REPLY_INT_MASK
250 #define MPI2_HIM_IOC2SYS_DB_MASK (0x00000001)
251 #define MPI2_HIM_DIM MPI2_HIM_IOC2SYS_DB_MASK
254 * Offsets for DCRData and address
256 #define MPI2_DCR_DATA_OFFSET (0x00000038)
257 #define MPI2_DCR_ADDRESS_OFFSET (0x0000003C)
260 * Offset for the Reply Free Queue
262 #define MPI2_REPLY_FREE_HOST_INDEX_OFFSET (0x00000048)
265 * Defines for the Reply Descriptor Post Queue
267 #define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C)
268 #define MPI2_REPLY_POST_HOST_INDEX_MASK (0x00FFFFFF)
269 #define MPI2_RPHI_MSIX_INDEX_MASK (0xFF000000)
270 #define MPI2_RPHI_MSIX_INDEX_SHIFT (24)
271 #define MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET (0x0000030C) /* MPI v2.5 only */
274 * Defines for the HCBSize and address
276 #define MPI2_HCB_SIZE_OFFSET (0x00000074)
277 #define MPI2_HCB_SIZE_SIZE_MASK (0xFFFFF000)
278 #define MPI2_HCB_SIZE_HCB_ENABLE (0x00000001)
280 #define MPI2_HCB_ADDRESS_LOW_OFFSET (0x00000078)
281 #define MPI2_HCB_ADDRESS_HIGH_OFFSET (0x0000007C)
284 * Offsets for the Request Queue
286 #define MPI2_REQUEST_DESCRIPTOR_POST_LOW_OFFSET (0x000000C0)
287 #define MPI2_REQUEST_DESCRIPTOR_POST_HIGH_OFFSET (0x000000C4)
290 /* Hard Reset delay timings */
291 #define MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC (50000)
292 #define MPI2_HARD_RESET_PCIE_RESET_READ_WINDOW_MICRO_SEC (255000)
293 #define MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC (256000)
295 /*****************************************************************************
297 * Message Descriptors
299 *****************************************************************************/
301 /* Request Descriptors */
303 /* Default Request Descriptor */
304 typedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR
306 U8 RequestFlags; /* 0x00 */
307 U8 MSIxIndex; /* 0x01 */
310 U16 DescriptorTypeDependent; /* 0x06 */
311 } MPI2_DEFAULT_REQUEST_DESCRIPTOR,
312 MPI2_POINTER PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR,
313 Mpi2DefaultRequestDescriptor_t, MPI2_POINTER pMpi2DefaultRequestDescriptor_t;
315 /* defines for the RequestFlags field */
316 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E)
317 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00)
318 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET (0x02)
319 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06)
320 #define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE (0x08)
321 #define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR (0x0A)
323 #define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01)
326 /* High Priority Request Descriptor */
327 typedef struct _MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR
329 U8 RequestFlags; /* 0x00 */
330 U8 MSIxIndex; /* 0x01 */
333 U16 Reserved1; /* 0x06 */
334 } MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
335 MPI2_POINTER PTR_MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
336 Mpi2HighPriorityRequestDescriptor_t,
337 MPI2_POINTER pMpi2HighPriorityRequestDescriptor_t;
340 /* SCSI IO Request Descriptor */
341 typedef struct _MPI2_SCSI_IO_REQUEST_DESCRIPTOR
343 U8 RequestFlags; /* 0x00 */
344 U8 MSIxIndex; /* 0x01 */
347 U16 DevHandle; /* 0x06 */
348 } MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
349 MPI2_POINTER PTR_MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
350 Mpi2SCSIIORequestDescriptor_t, MPI2_POINTER pMpi2SCSIIORequestDescriptor_t;
353 /* SCSI Target Request Descriptor */
354 typedef struct _MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR
356 U8 RequestFlags; /* 0x00 */
357 U8 MSIxIndex; /* 0x01 */
360 U16 IoIndex; /* 0x06 */
361 } MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
362 MPI2_POINTER PTR_MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
363 Mpi2SCSITargetRequestDescriptor_t,
364 MPI2_POINTER pMpi2SCSITargetRequestDescriptor_t;
367 /* RAID Accelerator Request Descriptor */
368 typedef struct _MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR {
369 U8 RequestFlags; /* 0x00 */
370 U8 MSIxIndex; /* 0x01 */
373 U16 Reserved; /* 0x06 */
374 } MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
375 MPI2_POINTER PTR_MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
376 Mpi2RAIDAcceleratorRequestDescriptor_t,
377 MPI2_POINTER pMpi2RAIDAcceleratorRequestDescriptor_t;
380 /* union of Request Descriptors */
381 typedef union _MPI2_REQUEST_DESCRIPTOR_UNION
383 MPI2_DEFAULT_REQUEST_DESCRIPTOR Default;
384 MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority;
385 MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO;
386 MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget;
387 MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator;
389 } MPI2_REQUEST_DESCRIPTOR_UNION, MPI2_POINTER PTR_MPI2_REQUEST_DESCRIPTOR_UNION,
390 Mpi2RequestDescriptorUnion_t, MPI2_POINTER pMpi2RequestDescriptorUnion_t;
393 /* Reply Descriptors */
395 /* Default Reply Descriptor */
396 typedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR
398 U8 ReplyFlags; /* 0x00 */
399 U8 MSIxIndex; /* 0x01 */
400 U16 DescriptorTypeDependent1; /* 0x02 */
401 U32 DescriptorTypeDependent2; /* 0x04 */
402 } MPI2_DEFAULT_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY_DESCRIPTOR,
403 Mpi2DefaultReplyDescriptor_t, MPI2_POINTER pMpi2DefaultReplyDescriptor_t;
405 /* defines for the ReplyFlags field */
406 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F)
407 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00)
408 #define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY (0x01)
409 #define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS (0x02)
410 #define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER (0x03)
411 #define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS (0x05)
412 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F)
414 /* values for marking a reply descriptor as unused */
415 #define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK (0xFFFFFFFF)
416 #define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK (0xFFFFFFFF)
418 /* Address Reply Descriptor */
419 typedef struct _MPI2_ADDRESS_REPLY_DESCRIPTOR
421 U8 ReplyFlags; /* 0x00 */
422 U8 MSIxIndex; /* 0x01 */
424 U32 ReplyFrameAddress; /* 0x04 */
425 } MPI2_ADDRESS_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_ADDRESS_REPLY_DESCRIPTOR,
426 Mpi2AddressReplyDescriptor_t, MPI2_POINTER pMpi2AddressReplyDescriptor_t;
428 #define MPI2_ADDRESS_REPLY_SMID_INVALID (0x00)
431 /* SCSI IO Success Reply Descriptor */
432 typedef struct _MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR
434 U8 ReplyFlags; /* 0x00 */
435 U8 MSIxIndex; /* 0x01 */
437 U16 TaskTag; /* 0x04 */
438 U16 Reserved1; /* 0x06 */
439 } MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
440 MPI2_POINTER PTR_MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
441 Mpi2SCSIIOSuccessReplyDescriptor_t,
442 MPI2_POINTER pMpi2SCSIIOSuccessReplyDescriptor_t;
445 /* TargetAssist Success Reply Descriptor */
446 typedef struct _MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR
448 U8 ReplyFlags; /* 0x00 */
449 U8 MSIxIndex; /* 0x01 */
451 U8 SequenceNumber; /* 0x04 */
452 U8 Reserved1; /* 0x05 */
453 U16 IoIndex; /* 0x06 */
454 } MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
455 MPI2_POINTER PTR_MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
456 Mpi2TargetAssistSuccessReplyDescriptor_t,
457 MPI2_POINTER pMpi2TargetAssistSuccessReplyDescriptor_t;
460 /* Target Command Buffer Reply Descriptor */
461 typedef struct _MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR
463 U8 ReplyFlags; /* 0x00 */
464 U8 MSIxIndex; /* 0x01 */
467 U16 InitiatorDevHandle; /* 0x04 */
468 U16 IoIndex; /* 0x06 */
469 } MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
470 MPI2_POINTER PTR_MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
471 Mpi2TargetCommandBufferReplyDescriptor_t,
472 MPI2_POINTER pMpi2TargetCommandBufferReplyDescriptor_t;
474 /* defines for Flags field */
475 #define MPI2_RPY_DESCRIPT_TCB_FLAGS_PHYNUM_MASK (0x3F)
478 /* RAID Accelerator Success Reply Descriptor */
479 typedef struct _MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR {
480 U8 ReplyFlags; /* 0x00 */
481 U8 MSIxIndex; /* 0x01 */
483 U32 Reserved; /* 0x04 */
484 } MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
485 MPI2_POINTER PTR_MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
486 Mpi2RAIDAcceleratorSuccessReplyDescriptor_t,
487 MPI2_POINTER pMpi2RAIDAcceleratorSuccessReplyDescriptor_t;
490 /* union of Reply Descriptors */
491 typedef union _MPI2_REPLY_DESCRIPTORS_UNION
493 MPI2_DEFAULT_REPLY_DESCRIPTOR Default;
494 MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply;
495 MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess;
496 MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess;
497 MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer;
498 MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR RAIDAcceleratorSuccess;
500 } MPI2_REPLY_DESCRIPTORS_UNION, MPI2_POINTER PTR_MPI2_REPLY_DESCRIPTORS_UNION,
501 Mpi2ReplyDescriptorsUnion_t, MPI2_POINTER pMpi2ReplyDescriptorsUnion_t;
505 /*****************************************************************************
509 *****************************************************************************/
511 #define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */
512 #define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01) /* SCSI Task Management */
513 #define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */
514 #define MPI2_FUNCTION_IOC_FACTS (0x03) /* IOC Facts */
515 #define MPI2_FUNCTION_CONFIG (0x04) /* Configuration */
516 #define MPI2_FUNCTION_PORT_FACTS (0x05) /* Port Facts */
517 #define MPI2_FUNCTION_PORT_ENABLE (0x06) /* Port Enable */
518 #define MPI2_FUNCTION_EVENT_NOTIFICATION (0x07) /* Event Notification */
519 #define MPI2_FUNCTION_EVENT_ACK (0x08) /* Event Acknowledge */
520 #define MPI2_FUNCTION_FW_DOWNLOAD (0x09) /* FW Download */
521 #define MPI2_FUNCTION_TARGET_ASSIST (0x0B) /* Target Assist */
522 #define MPI2_FUNCTION_TARGET_STATUS_SEND (0x0C) /* Target Status Send */
523 #define MPI2_FUNCTION_TARGET_MODE_ABORT (0x0D) /* Target Mode Abort */
524 #define MPI2_FUNCTION_FW_UPLOAD (0x12) /* FW Upload */
525 #define MPI2_FUNCTION_RAID_ACTION (0x15) /* RAID Action */
526 #define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16) /* SCSI IO RAID Passthrough */
527 #define MPI2_FUNCTION_TOOLBOX (0x17) /* Toolbox */
528 #define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18) /* SCSI Enclosure Processor */
529 #define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A) /* SMP Passthrough */
530 #define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B) /* SAS IO Unit Control */
531 #define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C) /* SATA Passthrough */
532 #define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D) /* Diagnostic Buffer Post */
533 #define MPI2_FUNCTION_DIAG_RELEASE (0x1E) /* Diagnostic Release */
534 #define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24) /* Target Command Buffer Post Base */
535 #define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25) /* Target Command Buffer Post List */
536 #define MPI2_FUNCTION_RAID_ACCELERATOR (0x2C) /* RAID Accelerator*/
537 /* Host Based Discovery Action */
538 #define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION (0x2F)
539 /* Power Management Control */
540 #define MPI2_FUNCTION_PWR_MGMT_CONTROL (0x30)
541 /* Send Host Message */
542 #define MPI2_FUNCTION_SEND_HOST_MESSAGE (0x31)
543 /* beginning of product-specific range */
544 #define MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC (0xF0)
545 /* end of product-specific range */
546 #define MPI2_FUNCTION_MAX_PRODUCT_SPECIFIC (0xFF)
551 /* Doorbell functions */
552 #define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40)
553 #define MPI2_FUNCTION_HANDSHAKE (0x42)
556 /*****************************************************************************
560 *****************************************************************************/
562 /* mask for IOCStatus status value */
563 #define MPI2_IOCSTATUS_MASK (0x7FFF)
565 /****************************************************************************
566 * Common IOCStatus values for all replies
567 ****************************************************************************/
569 #define MPI2_IOCSTATUS_SUCCESS (0x0000)
570 #define MPI2_IOCSTATUS_INVALID_FUNCTION (0x0001)
571 #define MPI2_IOCSTATUS_BUSY (0x0002)
572 #define MPI2_IOCSTATUS_INVALID_SGL (0x0003)
573 #define MPI2_IOCSTATUS_INTERNAL_ERROR (0x0004)
574 #define MPI2_IOCSTATUS_INVALID_VPID (0x0005)
575 #define MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES (0x0006)
576 #define MPI2_IOCSTATUS_INVALID_FIELD (0x0007)
577 #define MPI2_IOCSTATUS_INVALID_STATE (0x0008)
578 #define MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED (0x0009)
580 /****************************************************************************
581 * Config IOCStatus values
582 ****************************************************************************/
584 #define MPI2_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020)
585 #define MPI2_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021)
586 #define MPI2_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022)
587 #define MPI2_IOCSTATUS_CONFIG_INVALID_DATA (0x0023)
588 #define MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024)
589 #define MPI2_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025)
591 /****************************************************************************
593 ****************************************************************************/
595 #define MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR (0x0040)
596 #define MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE (0x0042)
597 #define MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE (0x0043)
598 #define MPI2_IOCSTATUS_SCSI_DATA_OVERRUN (0x0044)
599 #define MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN (0x0045)
600 #define MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR (0x0046)
601 #define MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR (0x0047)
602 #define MPI2_IOCSTATUS_SCSI_TASK_TERMINATED (0x0048)
603 #define MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH (0x0049)
604 #define MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED (0x004A)
605 #define MPI2_IOCSTATUS_SCSI_IOC_TERMINATED (0x004B)
606 #define MPI2_IOCSTATUS_SCSI_EXT_TERMINATED (0x004C)
608 /****************************************************************************
609 * For use by SCSI Initiator and SCSI Target end-to-end data protection
610 ****************************************************************************/
612 #define MPI2_IOCSTATUS_EEDP_GUARD_ERROR (0x004D)
613 #define MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR (0x004E)
614 #define MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR (0x004F)
616 /****************************************************************************
618 ****************************************************************************/
620 #define MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX (0x0062)
621 #define MPI2_IOCSTATUS_TARGET_ABORTED (0x0063)
622 #define MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE (0x0064)
623 #define MPI2_IOCSTATUS_TARGET_NO_CONNECTION (0x0065)
624 #define MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH (0x006A)
625 #define MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR (0x006D)
626 #define MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA (0x006E)
627 #define MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT (0x006F)
628 #define MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT (0x0070)
629 #define MPI2_IOCSTATUS_TARGET_NAK_RECEIVED (0x0071)
631 /****************************************************************************
632 * Serial Attached SCSI values
633 ****************************************************************************/
635 #define MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED (0x0090)
636 #define MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN (0x0091)
638 /****************************************************************************
639 * Diagnostic Buffer Post / Diagnostic Release values
640 ****************************************************************************/
642 #define MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED (0x00A0)
644 /****************************************************************************
645 * RAID Accelerator values
646 ****************************************************************************/
648 #define MPI2_IOCSTATUS_RAID_ACCEL_ERROR (0x00B0)
650 /****************************************************************************
651 * IOCStatus flag to indicate that log info is available
652 ****************************************************************************/
654 #define MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE (0x8000)
656 /****************************************************************************
658 ****************************************************************************/
660 #define MPI2_IOCLOGINFO_TYPE_MASK (0xF0000000)
661 #define MPI2_IOCLOGINFO_TYPE_SHIFT (28)
662 #define MPI2_IOCLOGINFO_TYPE_NONE (0x0)
663 #define MPI2_IOCLOGINFO_TYPE_SCSI (0x1)
664 #define MPI2_IOCLOGINFO_TYPE_FC (0x2)
665 #define MPI2_IOCLOGINFO_TYPE_SAS (0x3)
666 #define MPI2_IOCLOGINFO_TYPE_ISCSI (0x4)
667 #define MPI2_IOCLOGINFO_LOG_DATA_MASK (0x0FFFFFFF)
670 /*****************************************************************************
672 * Standard Message Structures
674 *****************************************************************************/
676 /****************************************************************************
677 * Request Message Header for all request messages
678 ****************************************************************************/
680 typedef struct _MPI2_REQUEST_HEADER
682 U16 FunctionDependent1; /* 0x00 */
683 U8 ChainOffset; /* 0x02 */
684 U8 Function; /* 0x03 */
685 U16 FunctionDependent2; /* 0x04 */
686 U8 FunctionDependent3; /* 0x06 */
687 U8 MsgFlags; /* 0x07 */
690 U16 Reserved1; /* 0x0A */
691 } MPI2_REQUEST_HEADER, MPI2_POINTER PTR_MPI2_REQUEST_HEADER,
692 MPI2RequestHeader_t, MPI2_POINTER pMPI2RequestHeader_t;
695 /****************************************************************************
697 ****************************************************************************/
699 typedef struct _MPI2_DEFAULT_REPLY
701 U16 FunctionDependent1; /* 0x00 */
702 U8 MsgLength; /* 0x02 */
703 U8 Function; /* 0x03 */
704 U16 FunctionDependent2; /* 0x04 */
705 U8 FunctionDependent3; /* 0x06 */
706 U8 MsgFlags; /* 0x07 */
709 U16 Reserved1; /* 0x0A */
710 U16 FunctionDependent5; /* 0x0C */
711 U16 IOCStatus; /* 0x0E */
712 U32 IOCLogInfo; /* 0x10 */
713 } MPI2_DEFAULT_REPLY, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY,
714 MPI2DefaultReply_t, MPI2_POINTER pMPI2DefaultReply_t;
717 /* common version structure/union used in messages and configuration pages */
719 typedef struct _MPI2_VERSION_STRUCT
725 } MPI2_VERSION_STRUCT;
727 typedef union _MPI2_VERSION_UNION
729 MPI2_VERSION_STRUCT Struct;
731 } MPI2_VERSION_UNION;
734 /* LUN field defines, common to many structures */
735 #define MPI2_LUN_FIRST_LEVEL_ADDRESSING (0x0000FFFF)
736 #define MPI2_LUN_SECOND_LEVEL_ADDRESSING (0xFFFF0000)
737 #define MPI2_LUN_THIRD_LEVEL_ADDRESSING (0x0000FFFF)
738 #define MPI2_LUN_FOURTH_LEVEL_ADDRESSING (0xFFFF0000)
739 #define MPI2_LUN_LEVEL_1_WORD (0xFF00)
740 #define MPI2_LUN_LEVEL_1_DWORD (0x0000FF00)
743 /*****************************************************************************
745 * Fusion-MPT MPI Scatter Gather Elements
747 *****************************************************************************/
749 /****************************************************************************
750 * MPI Simple Element structures
751 ****************************************************************************/
753 typedef struct _MPI2_SGE_SIMPLE32
757 } MPI2_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_SGE_SIMPLE32,
758 Mpi2SGESimple32_t, MPI2_POINTER pMpi2SGESimple32_t;
760 typedef struct _MPI2_SGE_SIMPLE64
764 } MPI2_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_SGE_SIMPLE64,
765 Mpi2SGESimple64_t, MPI2_POINTER pMpi2SGESimple64_t;
767 typedef struct _MPI2_SGE_SIMPLE_UNION
775 } MPI2_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_SIMPLE_UNION,
776 Mpi2SGESimpleUnion_t, MPI2_POINTER pMpi2SGESimpleUnion_t;
779 /****************************************************************************
780 * MPI Chain Element structures
781 ****************************************************************************/
783 typedef struct _MPI2_SGE_CHAIN32
789 } MPI2_SGE_CHAIN32, MPI2_POINTER PTR_MPI2_SGE_CHAIN32,
790 Mpi2SGEChain32_t, MPI2_POINTER pMpi2SGEChain32_t;
792 typedef struct _MPI2_SGE_CHAIN64
798 } MPI2_SGE_CHAIN64, MPI2_POINTER PTR_MPI2_SGE_CHAIN64,
799 Mpi2SGEChain64_t, MPI2_POINTER pMpi2SGEChain64_t;
801 typedef struct _MPI2_SGE_CHAIN_UNION
811 } MPI2_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_SGE_CHAIN_UNION,
812 Mpi2SGEChainUnion_t, MPI2_POINTER pMpi2SGEChainUnion_t;
815 /****************************************************************************
816 * MPI Transaction Context Element structures
817 ****************************************************************************/
819 typedef struct _MPI2_SGE_TRANSACTION32
825 U32 TransactionContext[1];
826 U32 TransactionDetails[1];
827 } MPI2_SGE_TRANSACTION32, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION32,
828 Mpi2SGETransaction32_t, MPI2_POINTER pMpi2SGETransaction32_t;
830 typedef struct _MPI2_SGE_TRANSACTION64
836 U32 TransactionContext[2];
837 U32 TransactionDetails[1];
838 } MPI2_SGE_TRANSACTION64, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION64,
839 Mpi2SGETransaction64_t, MPI2_POINTER pMpi2SGETransaction64_t;
841 typedef struct _MPI2_SGE_TRANSACTION96
847 U32 TransactionContext[3];
848 U32 TransactionDetails[1];
849 } MPI2_SGE_TRANSACTION96, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION96,
850 Mpi2SGETransaction96_t, MPI2_POINTER pMpi2SGETransaction96_t;
852 typedef struct _MPI2_SGE_TRANSACTION128
858 U32 TransactionContext[4];
859 U32 TransactionDetails[1];
860 } MPI2_SGE_TRANSACTION128, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION128,
861 Mpi2SGETransaction_t128, MPI2_POINTER pMpi2SGETransaction_t128;
863 typedef struct _MPI2_SGE_TRANSACTION_UNION
871 U32 TransactionContext32[1];
872 U32 TransactionContext64[2];
873 U32 TransactionContext96[3];
874 U32 TransactionContext128[4];
876 U32 TransactionDetails[1];
877 } MPI2_SGE_TRANSACTION_UNION, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION_UNION,
878 Mpi2SGETransactionUnion_t, MPI2_POINTER pMpi2SGETransactionUnion_t;
881 /****************************************************************************
882 * MPI SGE union for IO SGL's
883 ****************************************************************************/
885 typedef struct _MPI2_MPI_SGE_IO_UNION
889 MPI2_SGE_SIMPLE_UNION Simple;
890 MPI2_SGE_CHAIN_UNION Chain;
892 } MPI2_MPI_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_MPI_SGE_IO_UNION,
893 Mpi2MpiSGEIOUnion_t, MPI2_POINTER pMpi2MpiSGEIOUnion_t;
896 /****************************************************************************
897 * MPI SGE union for SGL's with Simple and Transaction elements
898 ****************************************************************************/
900 typedef struct _MPI2_SGE_TRANS_SIMPLE_UNION
904 MPI2_SGE_SIMPLE_UNION Simple;
905 MPI2_SGE_TRANSACTION_UNION Transaction;
907 } MPI2_SGE_TRANS_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_TRANS_SIMPLE_UNION,
908 Mpi2SGETransSimpleUnion_t, MPI2_POINTER pMpi2SGETransSimpleUnion_t;
911 /****************************************************************************
912 * All MPI SGE types union
913 ****************************************************************************/
915 typedef struct _MPI2_MPI_SGE_UNION
919 MPI2_SGE_SIMPLE_UNION Simple;
920 MPI2_SGE_CHAIN_UNION Chain;
921 MPI2_SGE_TRANSACTION_UNION Transaction;
923 } MPI2_MPI_SGE_UNION, MPI2_POINTER PTR_MPI2_MPI_SGE_UNION,
924 Mpi2MpiSgeUnion_t, MPI2_POINTER pMpi2MpiSgeUnion_t;
927 /****************************************************************************
928 * MPI SGE field definition and masks
929 ****************************************************************************/
931 /* Flags field bit definitions */
933 #define MPI2_SGE_FLAGS_LAST_ELEMENT (0x80)
934 #define MPI2_SGE_FLAGS_END_OF_BUFFER (0x40)
935 #define MPI2_SGE_FLAGS_ELEMENT_TYPE_MASK (0x30)
936 #define MPI2_SGE_FLAGS_LOCAL_ADDRESS (0x08)
937 #define MPI2_SGE_FLAGS_DIRECTION (0x04)
938 #define MPI2_SGE_FLAGS_ADDRESS_SIZE (0x02)
939 #define MPI2_SGE_FLAGS_END_OF_LIST (0x01)
941 #define MPI2_SGE_FLAGS_SHIFT (24)
943 #define MPI2_SGE_LENGTH_MASK (0x00FFFFFF)
944 #define MPI2_SGE_CHAIN_LENGTH_MASK (0x0000FFFF)
948 #define MPI2_SGE_FLAGS_TRANSACTION_ELEMENT (0x00)
949 #define MPI2_SGE_FLAGS_SIMPLE_ELEMENT (0x10)
950 #define MPI2_SGE_FLAGS_CHAIN_ELEMENT (0x30)
951 #define MPI2_SGE_FLAGS_ELEMENT_MASK (0x30)
953 /* Address location */
955 #define MPI2_SGE_FLAGS_SYSTEM_ADDRESS (0x00)
959 #define MPI2_SGE_FLAGS_IOC_TO_HOST (0x00)
960 #define MPI2_SGE_FLAGS_HOST_TO_IOC (0x04)
962 #define MPI2_SGE_FLAGS_DEST (MPI2_SGE_FLAGS_IOC_TO_HOST)
963 #define MPI2_SGE_FLAGS_SOURCE (MPI2_SGE_FLAGS_HOST_TO_IOC)
967 #define MPI2_SGE_FLAGS_32_BIT_ADDRESSING (0x00)
968 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02)
972 #define MPI2_SGE_FLAGS_32_BIT_CONTEXT (0x00)
973 #define MPI2_SGE_FLAGS_64_BIT_CONTEXT (0x02)
974 #define MPI2_SGE_FLAGS_96_BIT_CONTEXT (0x04)
975 #define MPI2_SGE_FLAGS_128_BIT_CONTEXT (0x06)
977 #define MPI2_SGE_CHAIN_OFFSET_MASK (0x00FF0000)
978 #define MPI2_SGE_CHAIN_OFFSET_SHIFT (16)
980 /****************************************************************************
981 * MPI SGE operation Macros
982 ****************************************************************************/
984 /* SIMPLE FlagsLength manipulations... */
985 #define MPI2_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_SGE_FLAGS_SHIFT)
986 #define MPI2_SGE_GET_FLAGS(f) (((f) & ~MPI2_SGE_LENGTH_MASK) >> MPI2_SGE_FLAGS_SHIFT)
987 #define MPI2_SGE_LENGTH(f) ((f) & MPI2_SGE_LENGTH_MASK)
988 #define MPI2_SGE_CHAIN_LENGTH(f) ((f) & MPI2_SGE_CHAIN_LENGTH_MASK)
990 #define MPI2_SGE_SET_FLAGS_LENGTH(f,l) (MPI2_SGE_SET_FLAGS(f) | MPI2_SGE_LENGTH(l))
992 #define MPI2_pSGE_GET_FLAGS(psg) MPI2_SGE_GET_FLAGS((psg)->FlagsLength)
993 #define MPI2_pSGE_GET_LENGTH(psg) MPI2_SGE_LENGTH((psg)->FlagsLength)
994 #define MPI2_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI2_SGE_SET_FLAGS_LENGTH(f,l)
996 /* CAUTION - The following are READ-MODIFY-WRITE! */
997 #define MPI2_pSGE_SET_FLAGS(psg,f) (psg)->FlagsLength |= MPI2_SGE_SET_FLAGS(f)
998 #define MPI2_pSGE_SET_LENGTH(psg,l) (psg)->FlagsLength |= MPI2_SGE_LENGTH(l)
1000 #define MPI2_GET_CHAIN_OFFSET(x) ((x & MPI2_SGE_CHAIN_OFFSET_MASK) >> MPI2_SGE_CHAIN_OFFSET_SHIFT)
1003 /*****************************************************************************
1005 * Fusion-MPT IEEE Scatter Gather Elements
1007 *****************************************************************************/
1009 /****************************************************************************
1010 * IEEE Simple Element structures
1011 ****************************************************************************/
1013 typedef struct _MPI2_IEEE_SGE_SIMPLE32
1017 } MPI2_IEEE_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE32,
1018 Mpi2IeeeSgeSimple32_t, MPI2_POINTER pMpi2IeeeSgeSimple32_t;
1020 typedef struct _MPI2_IEEE_SGE_SIMPLE64
1027 } MPI2_IEEE_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE64,
1028 Mpi2IeeeSgeSimple64_t, MPI2_POINTER pMpi2IeeeSgeSimple64_t;
1030 typedef union _MPI2_IEEE_SGE_SIMPLE_UNION
1032 MPI2_IEEE_SGE_SIMPLE32 Simple32;
1033 MPI2_IEEE_SGE_SIMPLE64 Simple64;
1034 } MPI2_IEEE_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE_UNION,
1035 Mpi2IeeeSgeSimpleUnion_t, MPI2_POINTER pMpi2IeeeSgeSimpleUnion_t;
1038 /****************************************************************************
1039 * IEEE Chain Element structures
1040 ****************************************************************************/
1042 typedef MPI2_IEEE_SGE_SIMPLE32 MPI2_IEEE_SGE_CHAIN32;
1044 typedef MPI2_IEEE_SGE_SIMPLE64 MPI2_IEEE_SGE_CHAIN64;
1046 typedef union _MPI2_IEEE_SGE_CHAIN_UNION
1048 MPI2_IEEE_SGE_CHAIN32 Chain32;
1049 MPI2_IEEE_SGE_CHAIN64 Chain64;
1050 } MPI2_IEEE_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_CHAIN_UNION,
1051 Mpi2IeeeSgeChainUnion_t, MPI2_POINTER pMpi2IeeeSgeChainUnion_t;
1054 /****************************************************************************
1055 * All IEEE SGE types union
1056 ****************************************************************************/
1058 typedef struct _MPI2_IEEE_SGE_UNION
1062 MPI2_IEEE_SGE_SIMPLE_UNION Simple;
1063 MPI2_IEEE_SGE_CHAIN_UNION Chain;
1065 } MPI2_IEEE_SGE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_UNION,
1066 Mpi2IeeeSgeUnion_t, MPI2_POINTER pMpi2IeeeSgeUnion_t;
1069 /****************************************************************************
1070 * IEEE SGE field definitions and masks
1071 ****************************************************************************/
1073 /* Flags field bit definitions */
1075 #define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK (0x80)
1077 #define MPI2_IEEE32_SGE_FLAGS_SHIFT (24)
1079 #define MPI2_IEEE32_SGE_LENGTH_MASK (0x00FFFFFF)
1083 #define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT (0x00)
1084 #define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80)
1086 /* Data Location Address Space */
1088 #define MPI2_IEEE_SGE_FLAGS_ADDR_MASK (0x03)
1089 #define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00)
1090 /* IEEE Simple Element only */
1091 #define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01)
1092 /* IEEE Simple Element only */
1093 #define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02)
1094 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03)
1095 /* IEEE Simple Element only */
1096 #define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR (0x03)
1097 /* IEEE Chain Element only */
1098 #define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR \
1099 (MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR) /* typo in name */
1101 /****************************************************************************
1102 * IEEE SGE operation Macros
1103 ****************************************************************************/
1105 /* SIMPLE FlagsLength manipulations... */
1106 #define MPI2_IEEE32_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_IEEE32_SGE_FLAGS_SHIFT)
1107 #define MPI2_IEEE32_SGE_GET_FLAGS(f) (((f) & ~MPI2_IEEE32_SGE_LENGTH_MASK) >> MPI2_IEEE32_SGE_FLAGS_SHIFT)
1108 #define MPI2_IEEE32_SGE_LENGTH(f) ((f) & MPI2_IEEE32_SGE_LENGTH_MASK)
1110 #define MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f, l) (MPI2_IEEE32_SGE_SET_FLAGS(f) | MPI2_IEEE32_SGE_LENGTH(l))
1112 #define MPI2_IEEE32_pSGE_GET_FLAGS(psg) MPI2_IEEE32_SGE_GET_FLAGS((psg)->FlagsLength)
1113 #define MPI2_IEEE32_pSGE_GET_LENGTH(psg) MPI2_IEEE32_SGE_LENGTH((psg)->FlagsLength)
1114 #define MPI2_IEEE32_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f,l)
1116 /* CAUTION - The following are READ-MODIFY-WRITE! */
1117 #define MPI2_IEEE32_pSGE_SET_FLAGS(psg,f) (psg)->FlagsLength |= MPI2_IEEE32_SGE_SET_FLAGS(f)
1118 #define MPI2_IEEE32_pSGE_SET_LENGTH(psg,l) (psg)->FlagsLength |= MPI2_IEEE32_SGE_LENGTH(l)
1123 /*****************************************************************************
1125 * Fusion-MPT MPI/IEEE Scatter Gather Unions
1127 *****************************************************************************/
1129 typedef union _MPI2_SIMPLE_SGE_UNION
1131 MPI2_SGE_SIMPLE_UNION MpiSimple;
1132 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
1133 } MPI2_SIMPLE_SGE_UNION, MPI2_POINTER PTR_MPI2_SIMPLE_SGE_UNION,
1134 Mpi2SimpleSgeUntion_t, MPI2_POINTER pMpi2SimpleSgeUntion_t;
1137 typedef union _MPI2_SGE_IO_UNION
1139 MPI2_SGE_SIMPLE_UNION MpiSimple;
1140 MPI2_SGE_CHAIN_UNION MpiChain;
1141 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
1142 MPI2_IEEE_SGE_CHAIN_UNION IeeeChain;
1143 } MPI2_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_SGE_IO_UNION,
1144 Mpi2SGEIOUnion_t, MPI2_POINTER pMpi2SGEIOUnion_t;
1147 /****************************************************************************
1149 * Values for SGLFlags field, used in many request messages with an SGL
1151 ****************************************************************************/
1153 /* values for MPI SGL Data Location Address Space subfield */
1154 #define MPI2_SGLFLAGS_ADDRESS_SPACE_MASK (0x0C)
1155 #define MPI2_SGLFLAGS_SYSTEM_ADDRESS_SPACE (0x00)
1156 #define MPI2_SGLFLAGS_IOCDDR_ADDRESS_SPACE (0x04)
1157 #define MPI2_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08)
1158 #define MPI2_SGLFLAGS_IOCPLBNTA_ADDRESS_SPACE (0x0C)
1159 /* values for SGL Type subfield */
1160 #define MPI2_SGLFLAGS_SGL_TYPE_MASK (0x03)
1161 #define MPI2_SGLFLAGS_SGL_TYPE_MPI (0x00)
1162 #define MPI2_SGLFLAGS_SGL_TYPE_IEEE32 (0x01)
1163 #define MPI2_SGLFLAGS_SGL_TYPE_IEEE64 (0x02)