drivers/scsi/mpt2sas/mpi/mpi2_ioc.h

   1 /*
   2  *  Copyright (c) 2000-2010 LSI Corporation.
   3  *
   4  *
   5  *           Name:  mpi2_ioc.h
   6  *          Title:  MPI IOC, Port, Event, FW Download, and FW Upload messages
   7  *  Creation Date:  October 11, 2006
   8  *
   9  *  mpi2_ioc.h Version:  02.00.16
  10  *
  11  *  Version History
  12  *  ---------------
  13  *
  14  *  Date      Version   Description
  15  *  --------  --------  ------------------------------------------------------
  16  *  04-30-07  02.00.00  Corresponds to Fusion-MPT MPI Specification Rev A.
  17  *  06-04-07  02.00.01  In IOCFacts Reply structure, renamed MaxDevices to
  18  *                      MaxTargets.
  19  *                      Added TotalImageSize field to FWDownload Request.
  20  *                      Added reserved words to FWUpload Request.
  21  *  06-26-07  02.00.02  Added IR Configuration Change List Event.
  22  *  08-31-07  02.00.03  Removed SystemReplyQueueDepth field from the IOCInit
  23  *                      request and replaced it with
  24  *                      ReplyDescriptorPostQueueDepth and ReplyFreeQueueDepth.
  25  *                      Replaced the MinReplyQueueDepth field of the IOCFacts
  26  *                      reply with MaxReplyDescriptorPostQueueDepth.
  27  *                      Added MPI2_RDPQ_DEPTH_MIN define to specify the minimum
  28  *                      depth for the Reply Descriptor Post Queue.
  29  *                      Added SASAddress field to Initiator Device Table
  30  *                      Overflow Event data.
  31  *  10-31-07  02.00.04  Added ReasonCode MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING
  32  *                      for SAS Initiator Device Status Change Event data.
  33  *                      Modified Reason Code defines for SAS Topology Change
  34  *                      List Event data, including adding a bit for PHY Vacant
  35  *                      status, and adding a mask for the Reason Code.
  36  *                      Added define for
  37  *                      MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING.
  38  *                      Added define for MPI2_EXT_IMAGE_TYPE_MEGARAID.
  39  *  12-18-07  02.00.05  Added Boot Status defines for the IOCExceptions field of
  40  *                      the IOCFacts Reply.
  41  *                      Removed MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define.
  42  *                      Moved MPI2_VERSION_UNION to mpi2.h.
  43  *                      Changed MPI2_EVENT_NOTIFICATION_REQUEST to use masks
  44  *                      instead of enables, and added SASBroadcastPrimitiveMasks
  45  *                      field.
  46  *                      Added Log Entry Added Event and related structure.
  47  *  02-29-08  02.00.06  Added define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID.
  48  *                      Removed define MPI2_IOCFACTS_PROTOCOL_SMP_TARGET.
  49  *                      Added MaxVolumes and MaxPersistentEntries fields to
  50  *                      IOCFacts reply.
  51  *                      Added ProtocalFlags and IOCCapabilities fields to
  52  *                      MPI2_FW_IMAGE_HEADER.
  53  *                      Removed MPI2_PORTENABLE_FLAGS_ENABLE_SINGLE_PORT.
  54  *  03-03-08  02.00.07  Fixed MPI2_FW_IMAGE_HEADER by changing Reserved26 to
  55  *                      a U16 (from a U32).
  56  *                      Removed extra 's' from EventMasks name.
  57  *  06-27-08  02.00.08  Fixed an offset in a comment.
  58  *  10-02-08  02.00.09  Removed SystemReplyFrameSize from MPI2_IOC_INIT_REQUEST.
  59  *                      Removed CurReplyFrameSize from MPI2_IOC_FACTS_REPLY and
  60  *                      renamed MinReplyFrameSize to ReplyFrameSize.
  61  *                      Added MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX.
  62  *                      Added two new RAIDOperation values for Integrated RAID
  63  *                      Operations Status Event data.
  64  *                      Added four new IR Configuration Change List Event data
  65  *                      ReasonCode values.
  66  *                      Added two new ReasonCode defines for SAS Device Status
  67  *                      Change Event data.
  68  *                      Added three new DiscoveryStatus bits for the SAS
  69  *                      Discovery event data.
  70  *                      Added Multiplexing Status Change bit to the PhyStatus
  71  *                      field of the SAS Topology Change List event data.
  72  *                      Removed define for MPI2_INIT_IMAGE_BOOTFLAGS_XMEMCOPY.
  73  *                      BootFlags are now product-specific.
  74  *                      Added defines for the indivdual signature bytes
  75  *                      for MPI2_INIT_IMAGE_FOOTER.
  76  *  01-19-09  02.00.10  Added MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY define.
  77  *                      Added MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR
  78  *                      define.
  79  *                      Added MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE
  80  *                      define.
  81  *                      Removed MPI2_EVENT_SAS_DISC_DS_SATA_INIT_FAILURE define.
  82  *  05-06-09  02.00.11  Added MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR define.
  83  *                      Added MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX define.
  84  *                      Added two new reason codes for SAS Device Status Change
  85  *                      Event.
  86  *                      Added new event: SAS PHY Counter.
  87  *  07-30-09  02.00.12  Added GPIO Interrupt event define and structure.
  88  *                      Added MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define.
  89  *                      Added new product id family for 2208.
  90  *  10-28-09  02.00.13  Added HostMSIxVectors field to MPI2_IOC_INIT_REQUEST.
  91  *                      Added MaxMSIxVectors field to MPI2_IOC_FACTS_REPLY.
  92  *                      Added MinDevHandle field to MPI2_IOC_FACTS_REPLY.
  93  *                      Added MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY.
  94  *                      Added MPI2_EVENT_HOST_BASED_DISCOVERY_PHY define.
  95  *                      Added MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER define.
  96  *                      Added Host Based Discovery Phy Event data.
  97  *                      Added defines for ProductID Product field
  98  *                      (MPI2_FW_HEADER_PID_).
  99  *                      Modified values for SAS ProductID Family
 100  *                      (MPI2_FW_HEADER_PID_FAMILY_).
 101  *  02-10-10  02.00.14  Added SAS Quiesce Event structure and defines.
 102  *                      Added PowerManagementControl Request structures and
 103  *                      defines.
 104  *  05-12-10  02.00.15  Marked Task Set Full Event as obsolete.
 105  *                      Added MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY define.
 106  *  11-10-10  02.00.16  Added MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC.
 107  *  --------------------------------------------------------------------------
 108  */
 109
 110 #ifndef MPI2_IOC_H
 111 #define MPI2_IOC_H
 112
 113 /*****************************************************************************
 114 *
 115 *               IOC Messages
 116 *
 117 *****************************************************************************/
 118
 119 /****************************************************************************
 120 *  IOCInit message
 121 ****************************************************************************/
 122
 123 /* IOCInit Request message */
 124 typedef struct _MPI2_IOC_INIT_REQUEST
 125 {
 126     U8                      WhoInit;                        /* 0x00 */
 127     U8                      Reserved1;                      /* 0x01 */
 128     U8                      ChainOffset;                    /* 0x02 */
 129     U8                      Function;                       /* 0x03 */
 130     U16                     Reserved2;                      /* 0x04 */
 131     U8                      Reserved3;                      /* 0x06 */
 132     U8                      MsgFlags;                       /* 0x07 */
 133     U8                      VP_ID;                          /* 0x08 */
 134     U8                      VF_ID;                          /* 0x09 */
 135     U16                     Reserved4;                      /* 0x0A */
 136     U16                     MsgVersion;                     /* 0x0C */
 137     U16                     HeaderVersion;                  /* 0x0E */
 138     U32                     Reserved5;                      /* 0x10 */
 139     U16                     Reserved6;                      /* 0x14 */
 140     U8                      Reserved7;                      /* 0x16 */
 141     U8                      HostMSIxVectors;                /* 0x17 */
 142     U16                     Reserved8;                      /* 0x18 */
 143     U16                     SystemRequestFrameSize;         /* 0x1A */
 144     U16                     ReplyDescriptorPostQueueDepth;  /* 0x1C */
 145     U16                     ReplyFreeQueueDepth;            /* 0x1E */
 146     U32                     SenseBufferAddressHigh;         /* 0x20 */
 147     U32                     SystemReplyAddressHigh;         /* 0x24 */
 148     U64                     SystemRequestFrameBaseAddress;  /* 0x28 */
 149     U64                     ReplyDescriptorPostQueueAddress;/* 0x30 */
 150     U64                     ReplyFreeQueueAddress;          /* 0x38 */
 151     U64                     TimeStamp;                      /* 0x40 */
 152 } MPI2_IOC_INIT_REQUEST, MPI2_POINTER PTR_MPI2_IOC_INIT_REQUEST,
 153   Mpi2IOCInitRequest_t, MPI2_POINTER pMpi2IOCInitRequest_t;
 154
 155 /* WhoInit values */
 156 #define MPI2_WHOINIT_NOT_INITIALIZED            (0x00)
 157 #define MPI2_WHOINIT_SYSTEM_BIOS                (0x01)
 158 #define MPI2_WHOINIT_ROM_BIOS                   (0x02)
 159 #define MPI2_WHOINIT_PCI_PEER                   (0x03)
 160 #define MPI2_WHOINIT_HOST_DRIVER                (0x04)
 161 #define MPI2_WHOINIT_MANUFACTURER               (0x05)
 162
 163 /* MsgVersion */
 164 #define MPI2_IOCINIT_MSGVERSION_MAJOR_MASK      (0xFF00)
 165 #define MPI2_IOCINIT_MSGVERSION_MAJOR_SHIFT     (8)
 166 #define MPI2_IOCINIT_MSGVERSION_MINOR_MASK      (0x00FF)
 167 #define MPI2_IOCINIT_MSGVERSION_MINOR_SHIFT     (0)
 168
 169 /* HeaderVersion */
 170 #define MPI2_IOCINIT_HDRVERSION_UNIT_MASK       (0xFF00)
 171 #define MPI2_IOCINIT_HDRVERSION_UNIT_SHIFT      (8)
 172 #define MPI2_IOCINIT_HDRVERSION_DEV_MASK        (0x00FF)
 173 #define MPI2_IOCINIT_HDRVERSION_DEV_SHIFT       (0)
 174
 175 /* minimum depth for the Reply Descriptor Post Queue */
 176 #define MPI2_RDPQ_DEPTH_MIN                     (16)
 177
 178
 179 /* IOCInit Reply message */
 180 typedef struct _MPI2_IOC_INIT_REPLY
 181 {
 182     U8                      WhoInit;                        /* 0x00 */
 183     U8                      Reserved1;                      /* 0x01 */
 184     U8                      MsgLength;                      /* 0x02 */
 185     U8                      Function;                       /* 0x03 */
 186     U16                     Reserved2;                      /* 0x04 */
 187     U8                      Reserved3;                      /* 0x06 */
 188     U8                      MsgFlags;                       /* 0x07 */
 189     U8                      VP_ID;                          /* 0x08 */
 190     U8                      VF_ID;                          /* 0x09 */
 191     U16                     Reserved4;                      /* 0x0A */
 192     U16                     Reserved5;                      /* 0x0C */
 193     U16                     IOCStatus;                      /* 0x0E */
 194     U32                     IOCLogInfo;                     /* 0x10 */
 195 } MPI2_IOC_INIT_REPLY, MPI2_POINTER PTR_MPI2_IOC_INIT_REPLY,
 196   Mpi2IOCInitReply_t, MPI2_POINTER pMpi2IOCInitReply_t;
 197
 198
 199 /****************************************************************************
 200 *  IOCFacts message
 201 ****************************************************************************/
 202
 203 /* IOCFacts Request message */
 204 typedef struct _MPI2_IOC_FACTS_REQUEST
 205 {
 206     U16                     Reserved1;                      /* 0x00 */
 207     U8                      ChainOffset;                    /* 0x02 */
 208     U8                      Function;                       /* 0x03 */
 209     U16                     Reserved2;                      /* 0x04 */
 210     U8                      Reserved3;                      /* 0x06 */
 211     U8                      MsgFlags;                       /* 0x07 */
 212     U8                      VP_ID;                          /* 0x08 */
 213     U8                      VF_ID;                          /* 0x09 */
 214     U16                     Reserved4;                      /* 0x0A */
 215 } MPI2_IOC_FACTS_REQUEST, MPI2_POINTER PTR_MPI2_IOC_FACTS_REQUEST,
 216   Mpi2IOCFactsRequest_t, MPI2_POINTER pMpi2IOCFactsRequest_t;
 217
 218
 219 /* IOCFacts Reply message */
 220 typedef struct _MPI2_IOC_FACTS_REPLY
 221 {
 222     U16                     MsgVersion;                     /* 0x00 */
 223     U8                      MsgLength;                      /* 0x02 */
 224     U8                      Function;                       /* 0x03 */
 225     U16                     HeaderVersion;                  /* 0x04 */
 226     U8                      IOCNumber;                      /* 0x06 */
 227     U8                      MsgFlags;                       /* 0x07 */
 228     U8                      VP_ID;                          /* 0x08 */
 229     U8                      VF_ID;                          /* 0x09 */
 230     U16                     Reserved1;                      /* 0x0A */
 231     U16                     IOCExceptions;                  /* 0x0C */
 232     U16                     IOCStatus;                      /* 0x0E */
 233     U32                     IOCLogInfo;                     /* 0x10 */
 234     U8                      MaxChainDepth;                  /* 0x14 */
 235     U8                      WhoInit;                        /* 0x15 */
 236     U8                      NumberOfPorts;                  /* 0x16 */
 237     U8                      MaxMSIxVectors;                 /* 0x17 */
 238     U16                     RequestCredit;                  /* 0x18 */
 239     U16                     ProductID;                      /* 0x1A */
 240     U32                     IOCCapabilities;                /* 0x1C */
 241     MPI2_VERSION_UNION      FWVersion;                      /* 0x20 */
 242     U16                     IOCRequestFrameSize;            /* 0x24 */
 243     U16                     Reserved3;                      /* 0x26 */
 244     U16                     MaxInitiators;                  /* 0x28 */
 245     U16                     MaxTargets;                     /* 0x2A */
 246     U16                     MaxSasExpanders;                /* 0x2C */
 247     U16                     MaxEnclosures;                  /* 0x2E */
 248     U16                     ProtocolFlags;                  /* 0x30 */
 249     U16                     HighPriorityCredit;             /* 0x32 */
 250     U16                     MaxReplyDescriptorPostQueueDepth; /* 0x34 */
 251     U8                      ReplyFrameSize;                 /* 0x36 */
 252     U8                      MaxVolumes;                     /* 0x37 */
 253     U16                     MaxDevHandle;                   /* 0x38 */
 254     U16                     MaxPersistentEntries;           /* 0x3A */
 255     U16                     MinDevHandle;                   /* 0x3C */
 256     U16                     Reserved4;                      /* 0x3E */
 257 } MPI2_IOC_FACTS_REPLY, MPI2_POINTER PTR_MPI2_IOC_FACTS_REPLY,
 258   Mpi2IOCFactsReply_t, MPI2_POINTER pMpi2IOCFactsReply_t;
 259
 260 /* MsgVersion */
 261 #define MPI2_IOCFACTS_MSGVERSION_MAJOR_MASK             (0xFF00)
 262 #define MPI2_IOCFACTS_MSGVERSION_MAJOR_SHIFT            (8)
 263 #define MPI2_IOCFACTS_MSGVERSION_MINOR_MASK             (0x00FF)
 264 #define MPI2_IOCFACTS_MSGVERSION_MINOR_SHIFT            (0)
 265
 266 /* HeaderVersion */
 267 #define MPI2_IOCFACTS_HDRVERSION_UNIT_MASK              (0xFF00)
 268 #define MPI2_IOCFACTS_HDRVERSION_UNIT_SHIFT             (8)
 269 #define MPI2_IOCFACTS_HDRVERSION_DEV_MASK               (0x00FF)
 270 #define MPI2_IOCFACTS_HDRVERSION_DEV_SHIFT              (0)
 271
 272 /* IOCExceptions */
 273 #define MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX      (0x0100)
 274
 275 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_MASK              (0x00E0)
 276 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_GOOD              (0x0000)
 277 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_BACKUP            (0x0020)
 278 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_RESTORED          (0x0040)
 279 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_CORRUPT_BACKUP    (0x0060)
 280
 281 #define MPI2_IOCFACTS_EXCEPT_METADATA_UNSUPPORTED       (0x0010)
 282 #define MPI2_IOCFACTS_EXCEPT_MANUFACT_CHECKSUM_FAIL     (0x0008)
 283 #define MPI2_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL           (0x0004)
 284 #define MPI2_IOCFACTS_EXCEPT_RAID_CONFIG_INVALID        (0x0002)
 285 #define MPI2_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL       (0x0001)
 286
 287 /* defines for WhoInit field are after the IOCInit Request */
 288
 289 /* ProductID field uses MPI2_FW_HEADER_PID_ */
 290
 291 /* IOCCapabilities */
 292 #define MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY   (0x00010000)
 293 #define MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX            (0x00008000)
 294 #define MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR       (0x00004000)
 295 #define MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY           (0x00002000)
 296 #define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID        (0x00001000)
 297 #define MPI2_IOCFACTS_CAPABILITY_TLR                    (0x00000800)
 298 #define MPI2_IOCFACTS_CAPABILITY_MULTICAST              (0x00000100)
 299 #define MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET   (0x00000080)
 300 #define MPI2_IOCFACTS_CAPABILITY_EEDP                   (0x00000040)
 301 #define MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER        (0x00000020)
 302 #define MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER        (0x00000010)
 303 #define MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER      (0x00000008)
 304 #define MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING (0x00000004)
 305
 306 /* ProtocolFlags */
 307 #define MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET              (0x0001)
 308 #define MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR           (0x0002)
 309
 310
 311 /****************************************************************************
 312 *  PortFacts message
 313 ****************************************************************************/
 314
 315 /* PortFacts Request message */
 316 typedef struct _MPI2_PORT_FACTS_REQUEST
 317 {
 318     U16                     Reserved1;                      /* 0x00 */
 319     U8                      ChainOffset;                    /* 0x02 */
 320     U8                      Function;                       /* 0x03 */
 321     U16                     Reserved2;                      /* 0x04 */
 322     U8                      PortNumber;                     /* 0x06 */
 323     U8                      MsgFlags;                       /* 0x07 */
 324     U8                      VP_ID;                          /* 0x08 */
 325     U8                      VF_ID;                          /* 0x09 */
 326     U16                     Reserved3;                      /* 0x0A */
 327 } MPI2_PORT_FACTS_REQUEST, MPI2_POINTER PTR_MPI2_PORT_FACTS_REQUEST,
 328   Mpi2PortFactsRequest_t, MPI2_POINTER pMpi2PortFactsRequest_t;
 329
 330 /* PortFacts Reply message */
 331 typedef struct _MPI2_PORT_FACTS_REPLY
 332 {
 333     U16                     Reserved1;                      /* 0x00 */
 334     U8                      MsgLength;                      /* 0x02 */
 335     U8                      Function;                       /* 0x03 */
 336     U16                     Reserved2;                      /* 0x04 */
 337     U8                      PortNumber;                     /* 0x06 */
 338     U8                      MsgFlags;                       /* 0x07 */
 339     U8                      VP_ID;                          /* 0x08 */
 340     U8                      VF_ID;                          /* 0x09 */
 341     U16                     Reserved3;                      /* 0x0A */
 342     U16                     Reserved4;                      /* 0x0C */
 343     U16                     IOCStatus;                      /* 0x0E */
 344     U32                     IOCLogInfo;                     /* 0x10 */
 345     U8                      Reserved5;                      /* 0x14 */
 346     U8                      PortType;                       /* 0x15 */
 347     U16                     Reserved6;                      /* 0x16 */
 348     U16                     MaxPostedCmdBuffers;            /* 0x18 */
 349     U16                     Reserved7;                      /* 0x1A */
 350 } MPI2_PORT_FACTS_REPLY, MPI2_POINTER PTR_MPI2_PORT_FACTS_REPLY,
 351   Mpi2PortFactsReply_t, MPI2_POINTER pMpi2PortFactsReply_t;
 352
 353 /* PortType values */
 354 #define MPI2_PORTFACTS_PORTTYPE_INACTIVE            (0x00)
 355 #define MPI2_PORTFACTS_PORTTYPE_FC                  (0x10)
 356 #define MPI2_PORTFACTS_PORTTYPE_ISCSI               (0x20)
 357 #define MPI2_PORTFACTS_PORTTYPE_SAS_PHYSICAL        (0x30)
 358 #define MPI2_PORTFACTS_PORTTYPE_SAS_VIRTUAL         (0x31)
 359
 360
 361 /****************************************************************************
 362 *  PortEnable message
 363 ****************************************************************************/
 364
 365 /* PortEnable Request message */
 366 typedef struct _MPI2_PORT_ENABLE_REQUEST
 367 {
 368     U16                     Reserved1;                      /* 0x00 */
 369     U8                      ChainOffset;                    /* 0x02 */
 370     U8                      Function;                       /* 0x03 */
 371     U8                      Reserved2;                      /* 0x04 */
 372     U8                      PortFlags;                      /* 0x05 */
 373     U8                      Reserved3;                      /* 0x06 */
 374     U8                      MsgFlags;                       /* 0x07 */
 375     U8                      VP_ID;                          /* 0x08 */
 376     U8                      VF_ID;                          /* 0x09 */
 377     U16                     Reserved4;                      /* 0x0A */
 378 } MPI2_PORT_ENABLE_REQUEST, MPI2_POINTER PTR_MPI2_PORT_ENABLE_REQUEST,
 379   Mpi2PortEnableRequest_t, MPI2_POINTER pMpi2PortEnableRequest_t;
 380
 381
 382 /* PortEnable Reply message */
 383 typedef struct _MPI2_PORT_ENABLE_REPLY
 384 {
 385     U16                     Reserved1;                      /* 0x00 */
 386     U8                      MsgLength;                      /* 0x02 */
 387     U8                      Function;                       /* 0x03 */
 388     U8                      Reserved2;                      /* 0x04 */
 389     U8                      PortFlags;                      /* 0x05 */
 390     U8                      Reserved3;                      /* 0x06 */
 391     U8                      MsgFlags;                       /* 0x07 */
 392     U8                      VP_ID;                          /* 0x08 */
 393     U8                      VF_ID;                          /* 0x09 */
 394     U16                     Reserved4;                      /* 0x0A */
 395     U16                     Reserved5;                      /* 0x0C */
 396     U16                     IOCStatus;                      /* 0x0E */
 397     U32                     IOCLogInfo;                     /* 0x10 */
 398 } MPI2_PORT_ENABLE_REPLY, MPI2_POINTER PTR_MPI2_PORT_ENABLE_REPLY,
 399   Mpi2PortEnableReply_t, MPI2_POINTER pMpi2PortEnableReply_t;
 400
 401
 402 /****************************************************************************
 403 *  EventNotification message
 404 ****************************************************************************/
 405
 406 /* EventNotification Request message */
 407 #define MPI2_EVENT_NOTIFY_EVENTMASK_WORDS           (4)
 408
 409 typedef struct _MPI2_EVENT_NOTIFICATION_REQUEST
 410 {
 411     U16                     Reserved1;                      /* 0x00 */
 412     U8                      ChainOffset;                    /* 0x02 */
 413     U8                      Function;                       /* 0x03 */
 414     U16                     Reserved2;                      /* 0x04 */
 415     U8                      Reserved3;                      /* 0x06 */
 416     U8                      MsgFlags;                       /* 0x07 */
 417     U8                      VP_ID;                          /* 0x08 */
 418     U8                      VF_ID;                          /* 0x09 */
 419     U16                     Reserved4;                      /* 0x0A */
 420     U32                     Reserved5;                      /* 0x0C */
 421     U32                     Reserved6;                      /* 0x10 */
 422     U32                     EventMasks[MPI2_EVENT_NOTIFY_EVENTMASK_WORDS];/* 0x14 */
 423     U16                     SASBroadcastPrimitiveMasks;     /* 0x24 */
 424     U16                     Reserved7;                      /* 0x26 */
 425     U32                     Reserved8;                      /* 0x28 */
 426 } MPI2_EVENT_NOTIFICATION_REQUEST,
 427   MPI2_POINTER PTR_MPI2_EVENT_NOTIFICATION_REQUEST,
 428   Mpi2EventNotificationRequest_t, MPI2_POINTER pMpi2EventNotificationRequest_t;
 429
 430
 431 /* EventNotification Reply message */
 432 typedef struct _MPI2_EVENT_NOTIFICATION_REPLY
 433 {
 434     U16                     EventDataLength;                /* 0x00 */
 435     U8                      MsgLength;                      /* 0x02 */
 436     U8                      Function;                       /* 0x03 */
 437     U16                     Reserved1;                      /* 0x04 */
 438     U8                      AckRequired;                    /* 0x06 */
 439     U8                      MsgFlags;                       /* 0x07 */
 440     U8                      VP_ID;                          /* 0x08 */
 441     U8                      VF_ID;                          /* 0x09 */
 442     U16                     Reserved2;                      /* 0x0A */
 443     U16                     Reserved3;                      /* 0x0C */
 444     U16                     IOCStatus;                      /* 0x0E */
 445     U32                     IOCLogInfo;                     /* 0x10 */
 446     U16                     Event;                          /* 0x14 */
 447     U16                     Reserved4;                      /* 0x16 */
 448     U32                     EventContext;                   /* 0x18 */
 449     U32                     EventData[1];                   /* 0x1C */
 450 } MPI2_EVENT_NOTIFICATION_REPLY, MPI2_POINTER PTR_MPI2_EVENT_NOTIFICATION_REPLY,
 451   Mpi2EventNotificationReply_t, MPI2_POINTER pMpi2EventNotificationReply_t;
 452
 453 /* AckRequired */
 454 #define MPI2_EVENT_NOTIFICATION_ACK_NOT_REQUIRED    (0x00)
 455 #define MPI2_EVENT_NOTIFICATION_ACK_REQUIRED        (0x01)
 456
 457 /* Event */
 458 #define MPI2_EVENT_LOG_DATA                         (0x0001)
 459 #define MPI2_EVENT_STATE_CHANGE                     (0x0002)
 460 #define MPI2_EVENT_HARD_RESET_RECEIVED              (0x0005)
 461 #define MPI2_EVENT_EVENT_CHANGE                     (0x000A)
 462 #define MPI2_EVENT_TASK_SET_FULL                    (0x000E) /* obsolete */
 463 #define MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE         (0x000F)
 464 #define MPI2_EVENT_IR_OPERATION_STATUS              (0x0014)
 465 #define MPI2_EVENT_SAS_DISCOVERY                    (0x0016)
 466 #define MPI2_EVENT_SAS_BROADCAST_PRIMITIVE          (0x0017)
 467 #define MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE    (0x0018)
 468 #define MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW          (0x0019)
 469 #define MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST         (0x001C)
 470 #define MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE    (0x001D)
 471 #define MPI2_EVENT_IR_VOLUME                        (0x001E)
 472 #define MPI2_EVENT_IR_PHYSICAL_DISK                 (0x001F)
 473 #define MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST     (0x0020)
 474 #define MPI2_EVENT_LOG_ENTRY_ADDED                  (0x0021)
 475 #define MPI2_EVENT_SAS_PHY_COUNTER                  (0x0022)
 476 #define MPI2_EVENT_GPIO_INTERRUPT                   (0x0023)
 477 #define MPI2_EVENT_HOST_BASED_DISCOVERY_PHY         (0x0024)
 478 #define MPI2_EVENT_SAS_QUIESCE                      (0x0025)
 479
 480
 481 /* Log Entry Added Event data */
 482
 483 /* the following structure matches MPI2_LOG_0_ENTRY in mpi2_cnfg.h */
 484 #define MPI2_EVENT_DATA_LOG_DATA_LENGTH             (0x1C)
 485
 486 typedef struct _MPI2_EVENT_DATA_LOG_ENTRY_ADDED
 487 {
 488     U64         TimeStamp;                          /* 0x00 */
 489     U32         Reserved1;                          /* 0x08 */
 490     U16         LogSequence;                        /* 0x0C */
 491     U16         LogEntryQualifier;                  /* 0x0E */
 492     U8          VP_ID;                              /* 0x10 */
 493     U8          VF_ID;                              /* 0x11 */
 494     U16         Reserved2;                          /* 0x12 */
 495     U8          LogData[MPI2_EVENT_DATA_LOG_DATA_LENGTH];/* 0x14 */
 496 } MPI2_EVENT_DATA_LOG_ENTRY_ADDED,
 497   MPI2_POINTER PTR_MPI2_EVENT_DATA_LOG_ENTRY_ADDED,
 498   Mpi2EventDataLogEntryAdded_t, MPI2_POINTER pMpi2EventDataLogEntryAdded_t;
 499
 500 /* GPIO Interrupt Event data */
 501
 502 typedef struct _MPI2_EVENT_DATA_GPIO_INTERRUPT {
 503     U8          GPIONum;                            /* 0x00 */
 504     U8          Reserved1;                          /* 0x01 */
 505     U16         Reserved2;                          /* 0x02 */
 506 } MPI2_EVENT_DATA_GPIO_INTERRUPT,
 507   MPI2_POINTER PTR_MPI2_EVENT_DATA_GPIO_INTERRUPT,
 508   Mpi2EventDataGpioInterrupt_t, MPI2_POINTER pMpi2EventDataGpioInterrupt_t;
 509
 510 /* Hard Reset Received Event data */
 511
 512 typedef struct _MPI2_EVENT_DATA_HARD_RESET_RECEIVED
 513 {
 514     U8                      Reserved1;                      /* 0x00 */
 515     U8                      Port;                           /* 0x01 */
 516     U16                     Reserved2;                      /* 0x02 */
 517 } MPI2_EVENT_DATA_HARD_RESET_RECEIVED,
 518   MPI2_POINTER PTR_MPI2_EVENT_DATA_HARD_RESET_RECEIVED,
 519   Mpi2EventDataHardResetReceived_t,
 520   MPI2_POINTER pMpi2EventDataHardResetReceived_t;
 521
 522 /* Task Set Full Event data */
 523 /*   this event is obsolete */
 524
 525 typedef struct _MPI2_EVENT_DATA_TASK_SET_FULL
 526 {
 527     U16                     DevHandle;                      /* 0x00 */
 528     U16                     CurrentDepth;                   /* 0x02 */
 529 } MPI2_EVENT_DATA_TASK_SET_FULL, MPI2_POINTER PTR_MPI2_EVENT_DATA_TASK_SET_FULL,
 530   Mpi2EventDataTaskSetFull_t, MPI2_POINTER pMpi2EventDataTaskSetFull_t;
 531
 532
 533 /* SAS Device Status Change Event data */
 534
 535 typedef struct _MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE
 536 {
 537     U16                     TaskTag;                        /* 0x00 */
 538     U8                      ReasonCode;                     /* 0x02 */
 539     U8                      Reserved1;                      /* 0x03 */
 540     U8                      ASC;                            /* 0x04 */
 541     U8                      ASCQ;                           /* 0x05 */
 542     U16                     DevHandle;                      /* 0x06 */
 543     U32                     Reserved2;                      /* 0x08 */
 544     U64                     SASAddress;                     /* 0x0C */
 545     U8                      LUN[8];                         /* 0x14 */
 546 } MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE,
 547   MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE,
 548   Mpi2EventDataSasDeviceStatusChange_t,
 549   MPI2_POINTER pMpi2EventDataSasDeviceStatusChange_t;
 550
 551 /* SAS Device Status Change Event data ReasonCode values */
 552 #define MPI2_EVENT_SAS_DEV_STAT_RC_SMART_DATA                           (0x05)
 553 #define MPI2_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED                          (0x07)
 554 #define MPI2_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET                (0x08)
 555 #define MPI2_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL                  (0x09)
 556 #define MPI2_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL              (0x0A)
 557 #define MPI2_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL              (0x0B)
 558 #define MPI2_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL                  (0x0C)
 559 #define MPI2_EVENT_SAS_DEV_STAT_RC_ASYNC_NOTIFICATION                   (0x0D)
 560 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_INTERNAL_DEV_RESET               (0x0E)
 561 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_TASK_ABORT_INTERNAL              (0x0F)
 562 #define MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE                    (0x10)
 563 #define MPI2_EVENT_SAS_DEV_STAT_RC_EXPANDER_REDUCED_FUNCTIONALITY       (0x11)
 564 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_EXPANDER_REDUCED_FUNCTIONALITY   (0x12)
 565
 566
 567 /* Integrated RAID Operation Status Event data */
 568
 569 typedef struct _MPI2_EVENT_DATA_IR_OPERATION_STATUS
 570 {
 571     U16                     VolDevHandle;               /* 0x00 */
 572     U16                     Reserved1;                  /* 0x02 */
 573     U8                      RAIDOperation;              /* 0x04 */
 574     U8                      PercentComplete;            /* 0x05 */
 575     U16                     Reserved2;                  /* 0x06 */
 576     U32                     Resereved3;                 /* 0x08 */
 577 } MPI2_EVENT_DATA_IR_OPERATION_STATUS,
 578   MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_OPERATION_STATUS,
 579   Mpi2EventDataIrOperationStatus_t,
 580   MPI2_POINTER pMpi2EventDataIrOperationStatus_t;
 581
 582 /* Integrated RAID Operation Status Event data RAIDOperation values */
 583 #define MPI2_EVENT_IR_RAIDOP_RESYNC                     (0x00)
 584 #define MPI2_EVENT_IR_RAIDOP_ONLINE_CAP_EXPANSION       (0x01)
 585 #define MPI2_EVENT_IR_RAIDOP_CONSISTENCY_CHECK          (0x02)
 586 #define MPI2_EVENT_IR_RAIDOP_BACKGROUND_INIT            (0x03)
 587 #define MPI2_EVENT_IR_RAIDOP_MAKE_DATA_CONSISTENT       (0x04)
 588
 589
 590 /* Integrated RAID Volume Event data */
 591
 592 typedef struct _MPI2_EVENT_DATA_IR_VOLUME
 593 {
 594     U16                     VolDevHandle;               /* 0x00 */
 595     U8                      ReasonCode;                 /* 0x02 */
 596     U8                      Reserved1;                  /* 0x03 */
 597     U32                     NewValue;                   /* 0x04 */
 598     U32                     PreviousValue;              /* 0x08 */
 599 } MPI2_EVENT_DATA_IR_VOLUME, MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_VOLUME,
 600   Mpi2EventDataIrVolume_t, MPI2_POINTER pMpi2EventDataIrVolume_t;
 601
 602 /* Integrated RAID Volume Event data ReasonCode values */
 603 #define MPI2_EVENT_IR_VOLUME_RC_SETTINGS_CHANGED        (0x01)
 604 #define MPI2_EVENT_IR_VOLUME_RC_STATUS_FLAGS_CHANGED    (0x02)
 605 #define MPI2_EVENT_IR_VOLUME_RC_STATE_CHANGED           (0x03)
 606
 607
 608 /* Integrated RAID Physical Disk Event data */
 609
 610 typedef struct _MPI2_EVENT_DATA_IR_PHYSICAL_DISK
 611 {
 612     U16                     Reserved1;                  /* 0x00 */
 613     U8                      ReasonCode;                 /* 0x02 */
 614     U8                      PhysDiskNum;                /* 0x03 */
 615     U16                     PhysDiskDevHandle;          /* 0x04 */
 616     U16                     Reserved2;                  /* 0x06 */
 617     U16                     Slot;                       /* 0x08 */
 618     U16                     EnclosureHandle;            /* 0x0A */
 619     U32                     NewValue;                   /* 0x0C */
 620     U32                     PreviousValue;              /* 0x10 */
 621 } MPI2_EVENT_DATA_IR_PHYSICAL_DISK,
 622   MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_PHYSICAL_DISK,
 623   Mpi2EventDataIrPhysicalDisk_t, MPI2_POINTER pMpi2EventDataIrPhysicalDisk_t;
 624
 625 /* Integrated RAID Physical Disk Event data ReasonCode values */
 626 #define MPI2_EVENT_IR_PHYSDISK_RC_SETTINGS_CHANGED      (0x01)
 627 #define MPI2_EVENT_IR_PHYSDISK_RC_STATUS_FLAGS_CHANGED  (0x02)
 628 #define MPI2_EVENT_IR_PHYSDISK_RC_STATE_CHANGED         (0x03)
 629
 630
 631 /* Integrated RAID Configuration Change List Event data */
 632
 633 /*
 634  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
 635  * one and check NumElements at runtime.
 636  */
 637 #ifndef MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT
 638 #define MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT          (1)
 639 #endif
 640
 641 typedef struct _MPI2_EVENT_IR_CONFIG_ELEMENT
 642 {
 643     U16                     ElementFlags;               /* 0x00 */
 644     U16                     VolDevHandle;               /* 0x02 */
 645     U8                      ReasonCode;                 /* 0x04 */
 646     U8                      PhysDiskNum;                /* 0x05 */
 647     U16                     PhysDiskDevHandle;          /* 0x06 */
 648 } MPI2_EVENT_IR_CONFIG_ELEMENT, MPI2_POINTER PTR_MPI2_EVENT_IR_CONFIG_ELEMENT,
 649   Mpi2EventIrConfigElement_t, MPI2_POINTER pMpi2EventIrConfigElement_t;
 650
 651 /* IR Configuration Change List Event data ElementFlags values */
 652 #define MPI2_EVENT_IR_CHANGE_EFLAGS_ELEMENT_TYPE_MASK   (0x000F)
 653 #define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLUME_ELEMENT      (0x0000)
 654 #define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLPHYSDISK_ELEMENT (0x0001)
 655 #define MPI2_EVENT_IR_CHANGE_EFLAGS_HOTSPARE_ELEMENT    (0x0002)
 656
 657 /* IR Configuration Change List Event data ReasonCode values */
 658 #define MPI2_EVENT_IR_CHANGE_RC_ADDED                   (0x01)
 659 #define MPI2_EVENT_IR_CHANGE_RC_REMOVED                 (0x02)
 660 #define MPI2_EVENT_IR_CHANGE_RC_NO_CHANGE               (0x03)
 661 #define MPI2_EVENT_IR_CHANGE_RC_HIDE                    (0x04)
 662 #define MPI2_EVENT_IR_CHANGE_RC_UNHIDE                  (0x05)
 663 #define MPI2_EVENT_IR_CHANGE_RC_VOLUME_CREATED          (0x06)
 664 #define MPI2_EVENT_IR_CHANGE_RC_VOLUME_DELETED          (0x07)
 665 #define MPI2_EVENT_IR_CHANGE_RC_PD_CREATED              (0x08)
 666 #define MPI2_EVENT_IR_CHANGE_RC_PD_DELETED              (0x09)
 667
 668 typedef struct _MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST
 669 {
 670     U8                              NumElements;        /* 0x00 */
 671     U8                              Reserved1;          /* 0x01 */
 672     U8                              Reserved2;          /* 0x02 */
 673     U8                              ConfigNum;          /* 0x03 */
 674     U32                             Flags;              /* 0x04 */
 675     MPI2_EVENT_IR_CONFIG_ELEMENT    ConfigElement[MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT];    /* 0x08 */
 676 } MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST,
 677   MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST,
 678   Mpi2EventDataIrConfigChangeList_t,
 679   MPI2_POINTER pMpi2EventDataIrConfigChangeList_t;
 680
 681 /* IR Configuration Change List Event data Flags values */
 682 #define MPI2_EVENT_IR_CHANGE_FLAGS_FOREIGN_CONFIG   (0x00000001)
 683
 684
 685 /* SAS Discovery Event data */
 686
 687 typedef struct _MPI2_EVENT_DATA_SAS_DISCOVERY
 688 {
 689     U8                      Flags;                      /* 0x00 */
 690     U8                      ReasonCode;                 /* 0x01 */
 691     U8                      PhysicalPort;               /* 0x02 */
 692     U8                      Reserved1;                  /* 0x03 */
 693     U32                     DiscoveryStatus;            /* 0x04 */
 694 } MPI2_EVENT_DATA_SAS_DISCOVERY,
 695   MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_DISCOVERY,
 696   Mpi2EventDataSasDiscovery_t, MPI2_POINTER pMpi2EventDataSasDiscovery_t;
 697
 698 /* SAS Discovery Event data Flags values */
 699 #define MPI2_EVENT_SAS_DISC_DEVICE_CHANGE                   (0x02)
 700 #define MPI2_EVENT_SAS_DISC_IN_PROGRESS                     (0x01)
 701
 702 /* SAS Discovery Event data ReasonCode values */
 703 #define MPI2_EVENT_SAS_DISC_RC_STARTED                      (0x01)
 704 #define MPI2_EVENT_SAS_DISC_RC_COMPLETED                    (0x02)
 705
 706 /* SAS Discovery Event data DiscoveryStatus values */
 707 #define MPI2_EVENT_SAS_DISC_DS_MAX_ENCLOSURES_EXCEED            (0x80000000)
 708 #define MPI2_EVENT_SAS_DISC_DS_MAX_EXPANDERS_EXCEED             (0x40000000)
 709 #define MPI2_EVENT_SAS_DISC_DS_MAX_DEVICES_EXCEED               (0x20000000)
 710 #define MPI2_EVENT_SAS_DISC_DS_MAX_TOPO_PHYS_EXCEED             (0x10000000)
 711 #define MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR             (0x08000000)
 712 #define MPI2_EVENT_SAS_DISC_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE    (0x00008000)
 713 #define MPI2_EVENT_SAS_DISC_DS_EXP_MULTI_SUBTRACTIVE            (0x00004000)
 714 #define MPI2_EVENT_SAS_DISC_DS_MULTI_PORT_DOMAIN                (0x00002000)
 715 #define MPI2_EVENT_SAS_DISC_DS_TABLE_TO_SUBTRACTIVE_LINK        (0x00001000)
 716 #define MPI2_EVENT_SAS_DISC_DS_UNSUPPORTED_DEVICE               (0x00000800)
 717 #define MPI2_EVENT_SAS_DISC_DS_TABLE_LINK                       (0x00000400)
 718 #define MPI2_EVENT_SAS_DISC_DS_SUBTRACTIVE_LINK                 (0x00000200)
 719 #define MPI2_EVENT_SAS_DISC_DS_SMP_CRC_ERROR                    (0x00000100)
 720 #define MPI2_EVENT_SAS_DISC_DS_SMP_FUNCTION_FAILED              (0x00000080)
 721 #define MPI2_EVENT_SAS_DISC_DS_INDEX_NOT_EXIST                  (0x00000040)
 722 #define MPI2_EVENT_SAS_DISC_DS_OUT_ROUTE_ENTRIES                (0x00000020)
 723 #define MPI2_EVENT_SAS_DISC_DS_SMP_TIMEOUT                      (0x00000010)
 724 #define MPI2_EVENT_SAS_DISC_DS_MULTIPLE_PORTS                   (0x00000004)
 725 #define MPI2_EVENT_SAS_DISC_DS_UNADDRESSABLE_DEVICE             (0x00000002)
 726 #define MPI2_EVENT_SAS_DISC_DS_LOOP_DETECTED                    (0x00000001)
 727
 728
 729 /* SAS Broadcast Primitive Event data */
 730
 731 typedef struct _MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE
 732 {
 733     U8                      PhyNum;                     /* 0x00 */
 734     U8                      Port;                       /* 0x01 */
 735     U8                      PortWidth;                  /* 0x02 */
 736     U8                      Primitive;                  /* 0x03 */
 737 } MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE,
 738   MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE,
 739   Mpi2EventDataSasBroadcastPrimitive_t,
 740   MPI2_POINTER pMpi2EventDataSasBroadcastPrimitive_t;
 741
 742 /* defines for the Primitive field */
 743 #define MPI2_EVENT_PRIMITIVE_CHANGE                         (0x01)
 744 #define MPI2_EVENT_PRIMITIVE_SES                            (0x02)
 745 #define MPI2_EVENT_PRIMITIVE_EXPANDER                       (0x03)
 746 #define MPI2_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT             (0x04)
 747 #define MPI2_EVENT_PRIMITIVE_RESERVED3                      (0x05)
 748 #define MPI2_EVENT_PRIMITIVE_RESERVED4                      (0x06)
 749 #define MPI2_EVENT_PRIMITIVE_CHANGE0_RESERVED               (0x07)
 750 #define MPI2_EVENT_PRIMITIVE_CHANGE1_RESERVED               (0x08)
 751
 752
 753 /* SAS Initiator Device Status Change Event data */
 754
 755 typedef struct _MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE
 756 {
 757     U8                      ReasonCode;                 /* 0x00 */
 758     U8                      PhysicalPort;               /* 0x01 */
 759     U16                     DevHandle;                  /* 0x02 */
 760     U64                     SASAddress;                 /* 0x04 */
 761 } MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE,
 762   MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE,
 763   Mpi2EventDataSasInitDevStatusChange_t,
 764   MPI2_POINTER pMpi2EventDataSasInitDevStatusChange_t;
 765
 766 /* SAS Initiator Device Status Change event ReasonCode values */
 767 #define MPI2_EVENT_SAS_INIT_RC_ADDED                (0x01)
 768 #define MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING       (0x02)
 769
 770
 771 /* SAS Initiator Device Table Overflow Event data */
 772
 773 typedef struct _MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW
 774 {
 775     U16                     MaxInit;                    /* 0x00 */
 776     U16                     CurrentInit;                /* 0x02 */
 777     U64                     SASAddress;                 /* 0x04 */
 778 } MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW,
 779   MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW,
 780   Mpi2EventDataSasInitTableOverflow_t,
 781   MPI2_POINTER pMpi2EventDataSasInitTableOverflow_t;
 782
 783
 784 /* SAS Topology Change List Event data */
 785
 786 /*
 787  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
 788  * one and check NumEntries at runtime.
 789  */
 790 #ifndef MPI2_EVENT_SAS_TOPO_PHY_COUNT
 791 #define MPI2_EVENT_SAS_TOPO_PHY_COUNT           (1)
 792 #endif
 793
 794 typedef struct _MPI2_EVENT_SAS_TOPO_PHY_ENTRY
 795 {
 796     U16                     AttachedDevHandle;          /* 0x00 */
 797     U8                      LinkRate;                   /* 0x02 */
 798     U8                      PhyStatus;                  /* 0x03 */
 799 } MPI2_EVENT_SAS_TOPO_PHY_ENTRY, MPI2_POINTER PTR_MPI2_EVENT_SAS_TOPO_PHY_ENTRY,
 800   Mpi2EventSasTopoPhyEntry_t, MPI2_POINTER pMpi2EventSasTopoPhyEntry_t;
 801
 802 typedef struct _MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST
 803 {
 804     U16                             EnclosureHandle;            /* 0x00 */
 805     U16                             ExpanderDevHandle;          /* 0x02 */
 806     U8                              NumPhys;                    /* 0x04 */
 807     U8                              Reserved1;                  /* 0x05 */
 808     U16                             Reserved2;                  /* 0x06 */
 809     U8                              NumEntries;                 /* 0x08 */
 810     U8                              StartPhyNum;                /* 0x09 */
 811     U8                              ExpStatus;                  /* 0x0A */
 812     U8                              PhysicalPort;               /* 0x0B */
 813     MPI2_EVENT_SAS_TOPO_PHY_ENTRY   PHY[MPI2_EVENT_SAS_TOPO_PHY_COUNT]; /* 0x0C*/
 814 } MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST,
 815   MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST,
 816   Mpi2EventDataSasTopologyChangeList_t,
 817   MPI2_POINTER pMpi2EventDataSasTopologyChangeList_t;
 818
 819 /* values for the ExpStatus field */
 820 #define MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER                  (0x00)
 821 #define MPI2_EVENT_SAS_TOPO_ES_ADDED                        (0x01)
 822 #define MPI2_EVENT_SAS_TOPO_ES_NOT_RESPONDING               (0x02)
 823 #define MPI2_EVENT_SAS_TOPO_ES_RESPONDING                   (0x03)
 824 #define MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING         (0x04)
 825
 826 /* defines for the LinkRate field */
 827 #define MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK                 (0xF0)
 828 #define MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT                (4)
 829 #define MPI2_EVENT_SAS_TOPO_LR_PREV_MASK                    (0x0F)
 830 #define MPI2_EVENT_SAS_TOPO_LR_PREV_SHIFT                   (0)
 831
 832 #define MPI2_EVENT_SAS_TOPO_LR_UNKNOWN_LINK_RATE            (0x00)
 833 #define MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED                 (0x01)
 834 #define MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED           (0x02)
 835 #define MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE            (0x03)
 836 #define MPI2_EVENT_SAS_TOPO_LR_PORT_SELECTOR                (0x04)
 837 #define MPI2_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS        (0x05)
 838 #define MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY              (0x06)
 839 #define MPI2_EVENT_SAS_TOPO_LR_RATE_1_5                     (0x08)
 840 #define MPI2_EVENT_SAS_TOPO_LR_RATE_3_0                     (0x09)
 841 #define MPI2_EVENT_SAS_TOPO_LR_RATE_6_0                     (0x0A)
 842
 843 /* values for the PhyStatus field */
 844 #define MPI2_EVENT_SAS_TOPO_PHYSTATUS_VACANT                (0x80)
 845 #define MPI2_EVENT_SAS_TOPO_PS_MULTIPLEX_CHANGE             (0x10)
 846 /* values for the PhyStatus ReasonCode sub-field */
 847 #define MPI2_EVENT_SAS_TOPO_RC_MASK                         (0x0F)
 848 #define MPI2_EVENT_SAS_TOPO_RC_TARG_ADDED                   (0x01)
 849 #define MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING          (0x02)
 850 #define MPI2_EVENT_SAS_TOPO_RC_PHY_CHANGED                  (0x03)
 851 #define MPI2_EVENT_SAS_TOPO_RC_NO_CHANGE                    (0x04)
 852 #define MPI2_EVENT_SAS_TOPO_RC_DELAY_NOT_RESPONDING         (0x05)
 853
 854
 855 /* SAS Enclosure Device Status Change Event data */
 856
 857 typedef struct _MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE
 858 {
 859     U16                     EnclosureHandle;            /* 0x00 */
 860     U8                      ReasonCode;                 /* 0x02 */
 861     U8                      PhysicalPort;               /* 0x03 */
 862     U64                     EnclosureLogicalID;         /* 0x04 */
 863     U16                     NumSlots;                   /* 0x0C */
 864     U16                     StartSlot;                  /* 0x0E */
 865     U32                     PhyBits;                    /* 0x10 */
 866 } MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE,
 867   MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE,
 868   Mpi2EventDataSasEnclDevStatusChange_t,
 869   MPI2_POINTER pMpi2EventDataSasEnclDevStatusChange_t;
 870
 871 /* SAS Enclosure Device Status Change event ReasonCode values */
 872 #define MPI2_EVENT_SAS_ENCL_RC_ADDED                (0x01)
 873 #define MPI2_EVENT_SAS_ENCL_RC_NOT_RESPONDING       (0x02)
 874
 875
 876 /* SAS PHY Counter Event data */
 877
 878 typedef struct _MPI2_EVENT_DATA_SAS_PHY_COUNTER {
 879     U64         TimeStamp;          /* 0x00 */
 880     U32         Reserved1;          /* 0x08 */
 881     U8          PhyEventCode;       /* 0x0C */
 882     U8          PhyNum;             /* 0x0D */
 883     U16         Reserved2;          /* 0x0E */
 884     U32         PhyEventInfo;       /* 0x10 */
 885     U8          CounterType;        /* 0x14 */
 886     U8          ThresholdWindow;    /* 0x15 */
 887     U8          TimeUnits;          /* 0x16 */
 888     U8          Reserved3;          /* 0x17 */
 889     U32         EventThreshold;     /* 0x18 */
 890     U16         ThresholdFlags;     /* 0x1C */
 891     U16         Reserved4;          /* 0x1E */
 892 } MPI2_EVENT_DATA_SAS_PHY_COUNTER,
 893   MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_PHY_COUNTER,
 894   Mpi2EventDataSasPhyCounter_t, MPI2_POINTER pMpi2EventDataSasPhyCounter_t;
 895
 896 /* use MPI2_SASPHY3_EVENT_CODE_ values from mpi2_cnfg.h for the
 897  * PhyEventCode field
 898  * use MPI2_SASPHY3_COUNTER_TYPE_ values from mpi2_cnfg.h for the
 899  * CounterType field
 900  * use MPI2_SASPHY3_TIME_UNITS_ values from mpi2_cnfg.h for the
 901  * TimeUnits field
 902  * use MPI2_SASPHY3_TFLAGS_ values from mpi2_cnfg.h for the
 903  * ThresholdFlags field
 904  * */
 905
 906
 907 /* SAS Quiesce Event data */
 908
 909 typedef struct _MPI2_EVENT_DATA_SAS_QUIESCE {
 910     U8                      ReasonCode;                 /* 0x00 */
 911     U8                      Reserved1;                  /* 0x01 */
 912     U16                     Reserved2;                  /* 0x02 */
 913     U32                     Reserved3;                  /* 0x04 */
 914 } MPI2_EVENT_DATA_SAS_QUIESCE,
 915   MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_QUIESCE,
 916   Mpi2EventDataSasQuiesce_t, MPI2_POINTER pMpi2EventDataSasQuiesce_t;
 917
 918 /* SAS Quiesce Event data ReasonCode values */
 919 #define MPI2_EVENT_SAS_QUIESCE_RC_STARTED                   (0x01)
 920 #define MPI2_EVENT_SAS_QUIESCE_RC_COMPLETED                 (0x02)
 921
 922
 923 /* Host Based Discovery Phy Event data */
 924
 925 typedef struct _MPI2_EVENT_HBD_PHY_SAS {
 926     U8          Flags;                      /* 0x00 */
 927     U8          NegotiatedLinkRate;         /* 0x01 */
 928     U8          PhyNum;                     /* 0x02 */
 929     U8          PhysicalPort;               /* 0x03 */
 930     U32         Reserved1;                  /* 0x04 */
 931     U8          InitialFrame[28];           /* 0x08 */
 932 } MPI2_EVENT_HBD_PHY_SAS, MPI2_POINTER PTR_MPI2_EVENT_HBD_PHY_SAS,
 933   Mpi2EventHbdPhySas_t, MPI2_POINTER pMpi2EventHbdPhySas_t;
 934
 935 /* values for the Flags field */
 936 #define MPI2_EVENT_HBD_SAS_FLAGS_FRAME_VALID        (0x02)
 937 #define MPI2_EVENT_HBD_SAS_FLAGS_SATA_FRAME         (0x01)
 938
 939 /* use MPI2_SAS_NEG_LINK_RATE_ defines from mpi2_cnfg.h for
 940  * the NegotiatedLinkRate field */
 941
 942 typedef union _MPI2_EVENT_HBD_DESCRIPTOR {
 943     MPI2_EVENT_HBD_PHY_SAS      Sas;
 944 } MPI2_EVENT_HBD_DESCRIPTOR, MPI2_POINTER PTR_MPI2_EVENT_HBD_DESCRIPTOR,
 945   Mpi2EventHbdDescriptor_t, MPI2_POINTER pMpi2EventHbdDescriptor_t;
 946
 947 typedef struct _MPI2_EVENT_DATA_HBD_PHY {
 948     U8                          DescriptorType;     /* 0x00 */
 949     U8                          Reserved1;          /* 0x01 */
 950     U16                         Reserved2;          /* 0x02 */
 951     U32                         Reserved3;          /* 0x04 */
 952     MPI2_EVENT_HBD_DESCRIPTOR   Descriptor;         /* 0x08 */
 953 } MPI2_EVENT_DATA_HBD_PHY, MPI2_POINTER PTR_MPI2_EVENT_DATA_HBD_PHY,
 954   Mpi2EventDataHbdPhy_t, MPI2_POINTER pMpi2EventDataMpi2EventDataHbdPhy_t;
 955
 956 /* values for the DescriptorType field */
 957 #define MPI2_EVENT_HBD_DT_SAS               (0x01)
 958
 959
 960
 961 /****************************************************************************
 962 *  EventAck message
 963 ****************************************************************************/
 964
 965 /* EventAck Request message */
 966 typedef struct _MPI2_EVENT_ACK_REQUEST
 967 {
 968     U16                     Reserved1;                      /* 0x00 */
 969     U8                      ChainOffset;                    /* 0x02 */
 970     U8                      Function;                       /* 0x03 */
 971     U16                     Reserved2;                      /* 0x04 */
 972     U8                      Reserved3;                      /* 0x06 */
 973     U8                      MsgFlags;                       /* 0x07 */
 974     U8                      VP_ID;                          /* 0x08 */
 975     U8                      VF_ID;                          /* 0x09 */
 976     U16                     Reserved4;                      /* 0x0A */
 977     U16                     Event;                          /* 0x0C */
 978     U16                     Reserved5;                      /* 0x0E */
 979     U32                     EventContext;                   /* 0x10 */
 980 } MPI2_EVENT_ACK_REQUEST, MPI2_POINTER PTR_MPI2_EVENT_ACK_REQUEST,
 981   Mpi2EventAckRequest_t, MPI2_POINTER pMpi2EventAckRequest_t;
 982
 983
 984 /* EventAck Reply message */
 985 typedef struct _MPI2_EVENT_ACK_REPLY
 986 {
 987     U16                     Reserved1;                      /* 0x00 */
 988     U8                      MsgLength;                      /* 0x02 */
 989     U8                      Function;                       /* 0x03 */
 990     U16                     Reserved2;                      /* 0x04 */
 991     U8                      Reserved3;                      /* 0x06 */
 992     U8                      MsgFlags;                       /* 0x07 */
 993     U8                      VP_ID;                          /* 0x08 */
 994     U8                      VF_ID;                          /* 0x09 */
 995     U16                     Reserved4;                      /* 0x0A */
 996     U16                     Reserved5;                      /* 0x0C */
 997     U16                     IOCStatus;                      /* 0x0E */
 998     U32                     IOCLogInfo;                     /* 0x10 */
 999 } MPI2_EVENT_ACK_REPLY, MPI2_POINTER PTR_MPI2_EVENT_ACK_REPLY,
1000   Mpi2EventAckReply_t, MPI2_POINTER pMpi2EventAckReply_t;
1001
1002
1003 /****************************************************************************
1004 *  FWDownload message
1005 ****************************************************************************/
1006
1007 /* FWDownload Request message */
1008 typedef struct _MPI2_FW_DOWNLOAD_REQUEST
1009 {
1010     U8                      ImageType;                  /* 0x00 */
1011     U8                      Reserved1;                  /* 0x01 */
1012     U8                      ChainOffset;                /* 0x02 */
1013     U8                      Function;                   /* 0x03 */
1014     U16                     Reserved2;                  /* 0x04 */
1015     U8                      Reserved3;                  /* 0x06 */
1016     U8                      MsgFlags;                   /* 0x07 */
1017     U8                      VP_ID;                      /* 0x08 */
1018     U8                      VF_ID;                      /* 0x09 */
1019     U16                     Reserved4;                  /* 0x0A */
1020     U32                     TotalImageSize;             /* 0x0C */
1021     U32                     Reserved5;                  /* 0x10 */
1022     MPI2_MPI_SGE_UNION      SGL;                        /* 0x14 */
1023 } MPI2_FW_DOWNLOAD_REQUEST, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_REQUEST,
1024   Mpi2FWDownloadRequest, MPI2_POINTER pMpi2FWDownloadRequest;
1025
1026 #define MPI2_FW_DOWNLOAD_MSGFLGS_LAST_SEGMENT   (0x01)
1027
1028 #define MPI2_FW_DOWNLOAD_ITYPE_FW                   (0x01)
1029 #define MPI2_FW_DOWNLOAD_ITYPE_BIOS                 (0x02)
1030 #define MPI2_FW_DOWNLOAD_ITYPE_MANUFACTURING        (0x06)
1031 #define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_1             (0x07)
1032 #define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_2             (0x08)
1033 #define MPI2_FW_DOWNLOAD_ITYPE_MEGARAID             (0x09)
1034 #define MPI2_FW_DOWNLOAD_ITYPE_COMPLETE             (0x0A)
1035 #define MPI2_FW_DOWNLOAD_ITYPE_COMMON_BOOT_BLOCK    (0x0B)
1036 #define MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC (0xF0)
1037
1038 /* FWDownload TransactionContext Element */
1039 typedef struct _MPI2_FW_DOWNLOAD_TCSGE
1040 {
1041     U8                      Reserved1;                  /* 0x00 */
1042     U8                      ContextSize;                /* 0x01 */
1043     U8                      DetailsLength;              /* 0x02 */
1044     U8                      Flags;                      /* 0x03 */
1045     U32                     Reserved2;                  /* 0x04 */
1046     U32                     ImageOffset;                /* 0x08 */
1047     U32                     ImageSize;                  /* 0x0C */
1048 } MPI2_FW_DOWNLOAD_TCSGE, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_TCSGE,
1049   Mpi2FWDownloadTCSGE_t, MPI2_POINTER pMpi2FWDownloadTCSGE_t;
1050
1051 /* FWDownload Reply message */
1052 typedef struct _MPI2_FW_DOWNLOAD_REPLY
1053 {
1054     U8                      ImageType;                  /* 0x00 */
1055     U8                      Reserved1;                  /* 0x01 */
1056     U8                      MsgLength;                  /* 0x02 */
1057     U8                      Function;                   /* 0x03 */
1058     U16                     Reserved2;                  /* 0x04 */
1059     U8                      Reserved3;                  /* 0x06 */
1060     U8                      MsgFlags;                   /* 0x07 */
1061     U8                      VP_ID;                      /* 0x08 */
1062     U8                      VF_ID;                      /* 0x09 */
1063     U16                     Reserved4;                  /* 0x0A */
1064     U16                     Reserved5;                  /* 0x0C */
1065     U16                     IOCStatus;                  /* 0x0E */
1066     U32                     IOCLogInfo;                 /* 0x10 */
1067 } MPI2_FW_DOWNLOAD_REPLY, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_REPLY,
1068   Mpi2FWDownloadReply_t, MPI2_POINTER pMpi2FWDownloadReply_t;
1069
1070
1071 /****************************************************************************
1072 *  FWUpload message
1073 ****************************************************************************/
1074
1075 /* FWUpload Request message */
1076 typedef struct _MPI2_FW_UPLOAD_REQUEST
1077 {
1078     U8                      ImageType;                  /* 0x00 */
1079     U8                      Reserved1;                  /* 0x01 */
1080     U8                      ChainOffset;                /* 0x02 */
1081     U8                      Function;                   /* 0x03 */
1082     U16                     Reserved2;                  /* 0x04 */
1083     U8                      Reserved3;                  /* 0x06 */
1084     U8                      MsgFlags;                   /* 0x07 */
1085     U8                      VP_ID;                      /* 0x08 */
1086     U8                      VF_ID;                      /* 0x09 */
1087     U16                     Reserved4;                  /* 0x0A */
1088     U32                     Reserved5;                  /* 0x0C */
1089     U32                     Reserved6;                  /* 0x10 */
1090     MPI2_MPI_SGE_UNION      SGL;                        /* 0x14 */
1091 } MPI2_FW_UPLOAD_REQUEST, MPI2_POINTER PTR_MPI2_FW_UPLOAD_REQUEST,
1092   Mpi2FWUploadRequest_t, MPI2_POINTER pMpi2FWUploadRequest_t;
1093
1094 #define MPI2_FW_UPLOAD_ITYPE_FW_CURRENT         (0x00)
1095 #define MPI2_FW_UPLOAD_ITYPE_FW_FLASH           (0x01)
1096 #define MPI2_FW_UPLOAD_ITYPE_BIOS_FLASH         (0x02)
1097 #define MPI2_FW_UPLOAD_ITYPE_FW_BACKUP          (0x05)
1098 #define MPI2_FW_UPLOAD_ITYPE_MANUFACTURING      (0x06)
1099 #define MPI2_FW_UPLOAD_ITYPE_CONFIG_1           (0x07)
1100 #define MPI2_FW_UPLOAD_ITYPE_CONFIG_2           (0x08)
1101 #define MPI2_FW_UPLOAD_ITYPE_MEGARAID           (0x09)
1102 #define MPI2_FW_UPLOAD_ITYPE_COMPLETE           (0x0A)
1103 #define MPI2_FW_UPLOAD_ITYPE_COMMON_BOOT_BLOCK  (0x0B)
1104
1105 typedef struct _MPI2_FW_UPLOAD_TCSGE
1106 {
1107     U8                      Reserved1;                  /* 0x00 */
1108     U8                      ContextSize;                /* 0x01 */
1109     U8                      DetailsLength;              /* 0x02 */
1110     U8                      Flags;                      /* 0x03 */
1111     U32                     Reserved2;                  /* 0x04 */
1112     U32                     ImageOffset;                /* 0x08 */
1113     U32                     ImageSize;                  /* 0x0C */
1114 } MPI2_FW_UPLOAD_TCSGE, MPI2_POINTER PTR_MPI2_FW_UPLOAD_TCSGE,
1115   Mpi2FWUploadTCSGE_t, MPI2_POINTER pMpi2FWUploadTCSGE_t;
1116
1117 /* FWUpload Reply message */
1118 typedef struct _MPI2_FW_UPLOAD_REPLY
1119 {
1120     U8                      ImageType;                  /* 0x00 */
1121     U8                      Reserved1;                  /* 0x01 */
1122     U8                      MsgLength;                  /* 0x02 */
1123     U8                      Function;                   /* 0x03 */
1124     U16                     Reserved2;                  /* 0x04 */
1125     U8                      Reserved3;                  /* 0x06 */
1126     U8                      MsgFlags;                   /* 0x07 */
1127     U8                      VP_ID;                      /* 0x08 */
1128     U8                      VF_ID;                      /* 0x09 */
1129     U16                     Reserved4;                  /* 0x0A */
1130     U16                     Reserved5;                  /* 0x0C */
1131     U16                     IOCStatus;                  /* 0x0E */
1132     U32                     IOCLogInfo;                 /* 0x10 */
1133     U32                     ActualImageSize;            /* 0x14 */
1134 } MPI2_FW_UPLOAD_REPLY, MPI2_POINTER PTR_MPI2_FW_UPLOAD_REPLY,
1135   Mpi2FWUploadReply_t, MPI2_POINTER pMPi2FWUploadReply_t;
1136
1137
1138 /* FW Image Header */
1139 typedef struct _MPI2_FW_IMAGE_HEADER
1140 {
1141     U32                     Signature;                  /* 0x00 */
1142     U32                     Signature0;                 /* 0x04 */
1143     U32                     Signature1;                 /* 0x08 */
1144     U32                     Signature2;                 /* 0x0C */
1145     MPI2_VERSION_UNION      MPIVersion;                 /* 0x10 */
1146     MPI2_VERSION_UNION      FWVersion;                  /* 0x14 */
1147     MPI2_VERSION_UNION      NVDATAVersion;              /* 0x18 */
1148     MPI2_VERSION_UNION      PackageVersion;             /* 0x1C */
1149     U16                     VendorID;                   /* 0x20 */
1150     U16                     ProductID;                  /* 0x22 */
1151     U16                     ProtocolFlags;              /* 0x24 */
1152     U16                     Reserved26;                 /* 0x26 */
1153     U32                     IOCCapabilities;            /* 0x28 */
1154     U32                     ImageSize;                  /* 0x2C */
1155     U32                     NextImageHeaderOffset;      /* 0x30 */
1156     U32                     Checksum;                   /* 0x34 */
1157     U32                     Reserved38;                 /* 0x38 */
1158     U32                     Reserved3C;                 /* 0x3C */
1159     U32                     Reserved40;                 /* 0x40 */
1160     U32                     Reserved44;                 /* 0x44 */
1161     U32                     Reserved48;                 /* 0x48 */
1162     U32                     Reserved4C;                 /* 0x4C */
1163     U32                     Reserved50;                 /* 0x50 */
1164     U32                     Reserved54;                 /* 0x54 */
1165     U32                     Reserved58;                 /* 0x58 */
1166     U32                     Reserved5C;                 /* 0x5C */
1167     U32                     Reserved60;                 /* 0x60 */
1168     U32                     FirmwareVersionNameWhat;    /* 0x64 */
1169     U8                      FirmwareVersionName[32];    /* 0x68 */
1170     U32                     VendorNameWhat;             /* 0x88 */
1171     U8                      VendorName[32];             /* 0x8C */
1172     U32                     PackageNameWhat;            /* 0x88 */
1173     U8                      PackageName[32];            /* 0x8C */
1174     U32                     ReservedD0;                 /* 0xD0 */
1175     U32                     ReservedD4;                 /* 0xD4 */
1176     U32                     ReservedD8;                 /* 0xD8 */
1177     U32                     ReservedDC;                 /* 0xDC */
1178     U32                     ReservedE0;                 /* 0xE0 */
1179     U32                     ReservedE4;                 /* 0xE4 */
1180     U32                     ReservedE8;                 /* 0xE8 */
1181     U32                     ReservedEC;                 /* 0xEC */
1182     U32                     ReservedF0;                 /* 0xF0 */
1183     U32                     ReservedF4;                 /* 0xF4 */
1184     U32                     ReservedF8;                 /* 0xF8 */
1185     U32                     ReservedFC;                 /* 0xFC */
1186 } MPI2_FW_IMAGE_HEADER, MPI2_POINTER PTR_MPI2_FW_IMAGE_HEADER,
1187   Mpi2FWImageHeader_t, MPI2_POINTER pMpi2FWImageHeader_t;
1188
1189 /* Signature field */
1190 #define MPI2_FW_HEADER_SIGNATURE_OFFSET         (0x00)
1191 #define MPI2_FW_HEADER_SIGNATURE_MASK           (0xFF000000)
1192 #define MPI2_FW_HEADER_SIGNATURE                (0xEA000000)
1193
1194 /* Signature0 field */
1195 #define MPI2_FW_HEADER_SIGNATURE0_OFFSET        (0x04)
1196 #define MPI2_FW_HEADER_SIGNATURE0               (0x5AFAA55A)
1197
1198 /* Signature1 field */
1199 #define MPI2_FW_HEADER_SIGNATURE1_OFFSET        (0x08)
1200 #define MPI2_FW_HEADER_SIGNATURE1               (0xA55AFAA5)
1201
1202 /* Signature2 field */
1203 #define MPI2_FW_HEADER_SIGNATURE2_OFFSET        (0x0C)
1204 #define MPI2_FW_HEADER_SIGNATURE2               (0x5AA55AFA)
1205
1206
1207 /* defines for using the ProductID field */
1208 #define MPI2_FW_HEADER_PID_TYPE_MASK            (0xF000)
1209 #define MPI2_FW_HEADER_PID_TYPE_SAS             (0x2000)
1210
1211 #define MPI2_FW_HEADER_PID_PROD_MASK                    (0x0F00)
1212 #define MPI2_FW_HEADER_PID_PROD_A                       (0x0000)
1213 #define MPI2_FW_HEADER_PID_PROD_TARGET_INITIATOR_SCSI   (0x0200)
1214 #define MPI2_FW_HEADER_PID_PROD_IR_SCSI                 (0x0700)
1215
1216
1217 #define MPI2_FW_HEADER_PID_FAMILY_MASK          (0x00FF)
1218 /* SAS */
1219 #define MPI2_FW_HEADER_PID_FAMILY_2108_SAS      (0x0013)
1220 #define MPI2_FW_HEADER_PID_FAMILY_2208_SAS      (0x0014)
1221
1222 /* use MPI2_IOCFACTS_PROTOCOL_ defines for ProtocolFlags field */
1223
1224 /* use MPI2_IOCFACTS_CAPABILITY_ defines for IOCCapabilities field */
1225
1226
1227 #define MPI2_FW_HEADER_IMAGESIZE_OFFSET         (0x2C)
1228 #define MPI2_FW_HEADER_NEXTIMAGE_OFFSET         (0x30)
1229 #define MPI2_FW_HEADER_VERNMHWAT_OFFSET         (0x64)
1230
1231 #define MPI2_FW_HEADER_WHAT_SIGNATURE           (0x29232840)
1232
1233 #define MPI2_FW_HEADER_SIZE                     (0x100)
1234
1235
1236 /* Extended Image Header */
1237 typedef struct _MPI2_EXT_IMAGE_HEADER
1238
1239 {
1240     U8                      ImageType;                  /* 0x00 */
1241     U8                      Reserved1;                  /* 0x01 */
1242     U16                     Reserved2;                  /* 0x02 */
1243     U32                     Checksum;                   /* 0x04 */
1244     U32                     ImageSize;                  /* 0x08 */
1245     U32                     NextImageHeaderOffset;      /* 0x0C */
1246     U32                     PackageVersion;             /* 0x10 */
1247     U32                     Reserved3;                  /* 0x14 */
1248     U32                     Reserved4;                  /* 0x18 */
1249     U32                     Reserved5;                  /* 0x1C */
1250     U8                      IdentifyString[32];         /* 0x20 */
1251 } MPI2_EXT_IMAGE_HEADER, MPI2_POINTER PTR_MPI2_EXT_IMAGE_HEADER,
1252   Mpi2ExtImageHeader_t, MPI2_POINTER pMpi2ExtImageHeader_t;
1253
1254 /* useful offsets */
1255 #define MPI2_EXT_IMAGE_IMAGETYPE_OFFSET         (0x00)
1256 #define MPI2_EXT_IMAGE_IMAGESIZE_OFFSET         (0x08)
1257 #define MPI2_EXT_IMAGE_NEXTIMAGE_OFFSET         (0x0C)
1258
1259 #define MPI2_EXT_IMAGE_HEADER_SIZE              (0x40)
1260
1261 /* defines for the ImageType field */
1262 #define MPI2_EXT_IMAGE_TYPE_UNSPECIFIED         (0x00)
1263 #define MPI2_EXT_IMAGE_TYPE_FW                  (0x01)
1264 #define MPI2_EXT_IMAGE_TYPE_NVDATA              (0x03)
1265 #define MPI2_EXT_IMAGE_TYPE_BOOTLOADER          (0x04)
1266 #define MPI2_EXT_IMAGE_TYPE_INITIALIZATION      (0x05)
1267 #define MPI2_EXT_IMAGE_TYPE_FLASH_LAYOUT        (0x06)
1268 #define MPI2_EXT_IMAGE_TYPE_SUPPORTED_DEVICES   (0x07)
1269 #define MPI2_EXT_IMAGE_TYPE_MEGARAID            (0x08)
1270
1271 #define MPI2_EXT_IMAGE_TYPE_MAX                 (MPI2_EXT_IMAGE_TYPE_MEGARAID)
1272
1273
1274
1275 /* FLASH Layout Extended Image Data */
1276
1277 /*
1278  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1279  * one and check RegionsPerLayout at runtime.
1280  */
1281 #ifndef MPI2_FLASH_NUMBER_OF_REGIONS
1282 #define MPI2_FLASH_NUMBER_OF_REGIONS        (1)
1283 #endif
1284
1285 /*
1286  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1287  * one and check NumberOfLayouts at runtime.
1288  */
1289 #ifndef MPI2_FLASH_NUMBER_OF_LAYOUTS
1290 #define MPI2_FLASH_NUMBER_OF_LAYOUTS        (1)
1291 #endif
1292
1293 typedef struct _MPI2_FLASH_REGION
1294 {
1295     U8                      RegionType;                 /* 0x00 */
1296     U8                      Reserved1;                  /* 0x01 */
1297     U16                     Reserved2;                  /* 0x02 */
1298     U32                     RegionOffset;               /* 0x04 */
1299     U32                     RegionSize;                 /* 0x08 */
1300     U32                     Reserved3;                  /* 0x0C */
1301 } MPI2_FLASH_REGION, MPI2_POINTER PTR_MPI2_FLASH_REGION,
1302   Mpi2FlashRegion_t, MPI2_POINTER pMpi2FlashRegion_t;
1303
1304 typedef struct _MPI2_FLASH_LAYOUT
1305 {
1306     U32                     FlashSize;                  /* 0x00 */
1307     U32                     Reserved1;                  /* 0x04 */
1308     U32                     Reserved2;                  /* 0x08 */
1309     U32                     Reserved3;                  /* 0x0C */
1310     MPI2_FLASH_REGION       Region[MPI2_FLASH_NUMBER_OF_REGIONS];/* 0x10 */
1311 } MPI2_FLASH_LAYOUT, MPI2_POINTER PTR_MPI2_FLASH_LAYOUT,
1312   Mpi2FlashLayout_t, MPI2_POINTER pMpi2FlashLayout_t;
1313
1314 typedef struct _MPI2_FLASH_LAYOUT_DATA
1315 {
1316     U8                      ImageRevision;              /* 0x00 */
1317     U8                      Reserved1;                  /* 0x01 */
1318     U8                      SizeOfRegion;               /* 0x02 */
1319     U8                      Reserved2;                  /* 0x03 */
1320     U16                     NumberOfLayouts;            /* 0x04 */
1321     U16                     RegionsPerLayout;           /* 0x06 */
1322     U16                     MinimumSectorAlignment;     /* 0x08 */
1323     U16                     Reserved3;                  /* 0x0A */
1324     U32                     Reserved4;                  /* 0x0C */
1325     MPI2_FLASH_LAYOUT       Layout[MPI2_FLASH_NUMBER_OF_LAYOUTS];/* 0x10 */
1326 } MPI2_FLASH_LAYOUT_DATA, MPI2_POINTER PTR_MPI2_FLASH_LAYOUT_DATA,
1327   Mpi2FlashLayoutData_t, MPI2_POINTER pMpi2FlashLayoutData_t;
1328
1329 /* defines for the RegionType field */
1330 #define MPI2_FLASH_REGION_UNUSED                (0x00)
1331 #define MPI2_FLASH_REGION_FIRMWARE              (0x01)
1332 #define MPI2_FLASH_REGION_BIOS                  (0x02)
1333 #define MPI2_FLASH_REGION_NVDATA                (0x03)
1334 #define MPI2_FLASH_REGION_FIRMWARE_BACKUP       (0x05)
1335 #define MPI2_FLASH_REGION_MFG_INFORMATION       (0x06)
1336 #define MPI2_FLASH_REGION_CONFIG_1              (0x07)
1337 #define MPI2_FLASH_REGION_CONFIG_2              (0x08)
1338 #define MPI2_FLASH_REGION_MEGARAID              (0x09)
1339 #define MPI2_FLASH_REGION_INIT                  (0x0A)
1340
1341 /* ImageRevision */
1342 #define MPI2_FLASH_LAYOUT_IMAGE_REVISION        (0x00)
1343
1344
1345
1346 /* Supported Devices Extended Image Data */
1347
1348 /*
1349  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1350  * one and check NumberOfDevices at runtime.
1351  */
1352 #ifndef MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES
1353 #define MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES    (1)
1354 #endif
1355
1356 typedef struct _MPI2_SUPPORTED_DEVICE
1357 {
1358     U16                     DeviceID;                   /* 0x00 */
1359     U16                     VendorID;                   /* 0x02 */
1360     U16                     DeviceIDMask;               /* 0x04 */
1361     U16                     Reserved1;                  /* 0x06 */
1362     U8                      LowPCIRev;                  /* 0x08 */
1363     U8                      HighPCIRev;                 /* 0x09 */
1364     U16                     Reserved2;                  /* 0x0A */
1365     U32                     Reserved3;                  /* 0x0C */
1366 } MPI2_SUPPORTED_DEVICE, MPI2_POINTER PTR_MPI2_SUPPORTED_DEVICE,
1367   Mpi2SupportedDevice_t, MPI2_POINTER pMpi2SupportedDevice_t;
1368
1369 typedef struct _MPI2_SUPPORTED_DEVICES_DATA
1370 {
1371     U8                      ImageRevision;              /* 0x00 */
1372     U8                      Reserved1;                  /* 0x01 */
1373     U8                      NumberOfDevices;            /* 0x02 */
1374     U8                      Reserved2;                  /* 0x03 */
1375     U32                     Reserved3;                  /* 0x04 */
1376     MPI2_SUPPORTED_DEVICE   SupportedDevice[MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES]; /* 0x08 */
1377 } MPI2_SUPPORTED_DEVICES_DATA, MPI2_POINTER PTR_MPI2_SUPPORTED_DEVICES_DATA,
1378   Mpi2SupportedDevicesData_t, MPI2_POINTER pMpi2SupportedDevicesData_t;
1379
1380 /* ImageRevision */
1381 #define MPI2_SUPPORTED_DEVICES_IMAGE_REVISION   (0x00)
1382
1383
1384 /* Init Extended Image Data */
1385
1386 typedef struct _MPI2_INIT_IMAGE_FOOTER
1387
1388 {
1389     U32                     BootFlags;                  /* 0x00 */
1390     U32                     ImageSize;                  /* 0x04 */
1391     U32                     Signature0;                 /* 0x08 */
1392     U32                     Signature1;                 /* 0x0C */
1393     U32                     Signature2;                 /* 0x10 */
1394     U32                     ResetVector;                /* 0x14 */
1395 } MPI2_INIT_IMAGE_FOOTER, MPI2_POINTER PTR_MPI2_INIT_IMAGE_FOOTER,
1396   Mpi2InitImageFooter_t, MPI2_POINTER pMpi2InitImageFooter_t;
1397
1398 /* defines for the BootFlags field */
1399 #define MPI2_INIT_IMAGE_BOOTFLAGS_OFFSET        (0x00)
1400
1401 /* defines for the ImageSize field */
1402 #define MPI2_INIT_IMAGE_IMAGESIZE_OFFSET        (0x04)
1403
1404 /* defines for the Signature0 field */
1405 #define MPI2_INIT_IMAGE_SIGNATURE0_OFFSET       (0x08)
1406 #define MPI2_INIT_IMAGE_SIGNATURE0              (0x5AA55AEA)
1407
1408 /* defines for the Signature1 field */
1409 #define MPI2_INIT_IMAGE_SIGNATURE1_OFFSET       (0x0C)
1410 #define MPI2_INIT_IMAGE_SIGNATURE1              (0xA55AEAA5)
1411
1412 /* defines for the Signature2 field */
1413 #define MPI2_INIT_IMAGE_SIGNATURE2_OFFSET       (0x10)
1414 #define MPI2_INIT_IMAGE_SIGNATURE2              (0x5AEAA55A)
1415
1416 /* Signature fields as individual bytes */
1417 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_0        (0xEA)
1418 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_1        (0x5A)
1419 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_2        (0xA5)
1420 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_3        (0x5A)
1421
1422 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_4        (0xA5)
1423 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_5        (0xEA)
1424 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_6        (0x5A)
1425 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_7        (0xA5)
1426
1427 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_8        (0x5A)
1428 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_9        (0xA5)
1429 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_A        (0xEA)
1430 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_B        (0x5A)
1431
1432 /* defines for the ResetVector field */
1433 #define MPI2_INIT_IMAGE_RESETVECTOR_OFFSET      (0x14)
1434
1435
1436 /****************************************************************************
1437 *  PowerManagementControl message
1438 ****************************************************************************/
1439
1440 /* PowerManagementControl Request message */
1441 typedef struct _MPI2_PWR_MGMT_CONTROL_REQUEST {
1442     U8                      Feature;                    /* 0x00 */
1443     U8                      Reserved1;                  /* 0x01 */
1444     U8                      ChainOffset;                /* 0x02 */
1445     U8                      Function;                   /* 0x03 */
1446     U16                     Reserved2;                  /* 0x04 */
1447     U8                      Reserved3;                  /* 0x06 */
1448     U8                      MsgFlags;                   /* 0x07 */
1449     U8                      VP_ID;                      /* 0x08 */
1450     U8                      VF_ID;                      /* 0x09 */
1451     U16                     Reserved4;                  /* 0x0A */
1452     U8                      Parameter1;                 /* 0x0C */
1453     U8                      Parameter2;                 /* 0x0D */
1454     U8                      Parameter3;                 /* 0x0E */
1455     U8                      Parameter4;                 /* 0x0F */
1456     U32                     Reserved5;                  /* 0x10 */
1457     U32                     Reserved6;                  /* 0x14 */
1458 } MPI2_PWR_MGMT_CONTROL_REQUEST, MPI2_POINTER PTR_MPI2_PWR_MGMT_CONTROL_REQUEST,
1459   Mpi2PwrMgmtControlRequest_t, MPI2_POINTER pMpi2PwrMgmtControlRequest_t;
1460
1461 /* defines for the Feature field */
1462 #define MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND       (0x01)
1463 #define MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION   (0x02)
1464 #define MPI2_PM_CONTROL_FEATURE_PCIE_LINK               (0x03)
1465 #define MPI2_PM_CONTROL_FEATURE_IOC_SPEED               (0x04)
1466 #define MPI2_PM_CONTROL_FEATURE_MIN_PRODUCT_SPECIFIC    (0x80)
1467 #define MPI2_PM_CONTROL_FEATURE_MAX_PRODUCT_SPECIFIC    (0xFF)
1468
1469 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND Feature */
1470 /* Parameter1 contains a PHY number */
1471 /* Parameter2 indicates power condition action using these defines */
1472 #define MPI2_PM_CONTROL_PARAM2_PARTIAL                  (0x01)
1473 #define MPI2_PM_CONTROL_PARAM2_SLUMBER                  (0x02)
1474 #define MPI2_PM_CONTROL_PARAM2_EXIT_PWR_MGMT            (0x03)
1475 /* Parameter3 and Parameter4 are reserved */
1476
1477 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION
1478  *  Feature */
1479 /* Parameter1 contains SAS port width modulation group number */
1480 /* Parameter2 indicates IOC action using these defines */
1481 #define MPI2_PM_CONTROL_PARAM2_REQUEST_OWNERSHIP        (0x01)
1482 #define MPI2_PM_CONTROL_PARAM2_CHANGE_MODULATION        (0x02)
1483 #define MPI2_PM_CONTROL_PARAM2_RELINQUISH_OWNERSHIP     (0x03)
1484 /* Parameter3 indicates desired modulation level using these defines */
1485 #define MPI2_PM_CONTROL_PARAM3_25_PERCENT               (0x00)
1486 #define MPI2_PM_CONTROL_PARAM3_50_PERCENT               (0x01)
1487 #define MPI2_PM_CONTROL_PARAM3_75_PERCENT               (0x02)
1488 #define MPI2_PM_CONTROL_PARAM3_100_PERCENT              (0x03)
1489 /* Parameter4 is reserved */
1490
1491 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_PCIE_LINK Feature */
1492 /* Parameter1 indicates desired PCIe link speed using these defines */
1493 #define MPI2_PM_CONTROL_PARAM1_PCIE_2_5_GBPS            (0x00)
1494 #define MPI2_PM_CONTROL_PARAM1_PCIE_5_0_GBPS            (0x01)
1495 #define MPI2_PM_CONTROL_PARAM1_PCIE_8_0_GBPS            (0x02)
1496 /* Parameter2 indicates desired PCIe link width using these defines */
1497 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X1                 (0x01)
1498 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X2                 (0x02)
1499 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X4                 (0x04)
1500 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X8                 (0x08)
1501 /* Parameter3 and Parameter4 are reserved */
1502
1503 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_IOC_SPEED Feature */
1504 /* Parameter1 indicates desired IOC hardware clock speed using these defines */
1505 #define MPI2_PM_CONTROL_PARAM1_FULL_IOC_SPEED           (0x01)
1506 #define MPI2_PM_CONTROL_PARAM1_HALF_IOC_SPEED           (0x02)
1507 #define MPI2_PM_CONTROL_PARAM1_QUARTER_IOC_SPEED        (0x04)
1508 #define MPI2_PM_CONTROL_PARAM1_EIGHTH_IOC_SPEED         (0x08)
1509 /* Parameter2, Parameter3, and Parameter4 are reserved */
1510
1511
1512 /* PowerManagementControl Reply message */
1513 typedef struct _MPI2_PWR_MGMT_CONTROL_REPLY {
1514     U8                      Feature;                    /* 0x00 */
1515     U8                      Reserved1;                  /* 0x01 */
1516     U8                      MsgLength;                  /* 0x02 */
1517     U8                      Function;                   /* 0x03 */
1518     U16                     Reserved2;                  /* 0x04 */
1519     U8                      Reserved3;                  /* 0x06 */
1520     U8                      MsgFlags;                   /* 0x07 */
1521     U8                      VP_ID;                      /* 0x08 */
1522     U8                      VF_ID;                      /* 0x09 */
1523     U16                     Reserved4;                  /* 0x0A */
1524     U16                     Reserved5;                  /* 0x0C */
1525     U16                     IOCStatus;                  /* 0x0E */
1526     U32                     IOCLogInfo;                 /* 0x10 */
1527 } MPI2_PWR_MGMT_CONTROL_REPLY, MPI2_POINTER PTR_MPI2_PWR_MGMT_CONTROL_REPLY,
1528   Mpi2PwrMgmtControlReply_t, MPI2_POINTER pMpi2PwrMgmtControlReply_t;
1529
1530
1531 #endif
1532