2 * Copyright 2000-2015 Avago Technologies. All rights reserved.
6 * Title: MPI Message independent structures and definitions
7 * including System Interface Register Set and
8 * scatter/gather formats.
9 * Creation Date: June 21, 2006
11 * mpi2.h Version: 02.00.37
13 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25
14 * prefix are for use only on MPI v2.5 products, and must not be used
15 * with MPI v2.0 products. Unless otherwise noted, names beginning with
16 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products.
21 * Date Version Description
22 * -------- -------- ------------------------------------------------------
23 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
24 * 06-04-07 02.00.01 Bumped MPI2_HEADER_VERSION_UNIT.
25 * 06-26-07 02.00.02 Bumped MPI2_HEADER_VERSION_UNIT.
26 * 08-31-07 02.00.03 Bumped MPI2_HEADER_VERSION_UNIT.
27 * Moved ReplyPostHostIndex register to offset 0x6C of the
28 * MPI2_SYSTEM_INTERFACE_REGS and modified the define for
29 * MPI2_REPLY_POST_HOST_INDEX_OFFSET.
30 * Added union of request descriptors.
31 * Added union of reply descriptors.
32 * 10-31-07 02.00.04 Bumped MPI2_HEADER_VERSION_UNIT.
33 * Added define for MPI2_VERSION_02_00.
34 * Fixed the size of the FunctionDependent5 field in the
35 * MPI2_DEFAULT_REPLY structure.
36 * 12-18-07 02.00.05 Bumped MPI2_HEADER_VERSION_UNIT.
37 * Removed the MPI-defined Fault Codes and extended the
38 * product specific codes up to 0xEFFF.
39 * Added a sixth key value for the WriteSequence register
40 * and changed the flush value to 0x0.
41 * Added message function codes for Diagnostic Buffer Post
42 * and Diagnsotic Release.
43 * New IOCStatus define: MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED
44 * Moved MPI2_VERSION_UNION from mpi2_ioc.h.
45 * 02-29-08 02.00.06 Bumped MPI2_HEADER_VERSION_UNIT.
46 * 03-03-08 02.00.07 Bumped MPI2_HEADER_VERSION_UNIT.
47 * 05-21-08 02.00.08 Bumped MPI2_HEADER_VERSION_UNIT.
48 * Added #defines for marking a reply descriptor as unused.
49 * 06-27-08 02.00.09 Bumped MPI2_HEADER_VERSION_UNIT.
50 * 10-02-08 02.00.10 Bumped MPI2_HEADER_VERSION_UNIT.
51 * Moved LUN field defines from mpi2_init.h.
52 * 01-19-09 02.00.11 Bumped MPI2_HEADER_VERSION_UNIT.
53 * 05-06-09 02.00.12 Bumped MPI2_HEADER_VERSION_UNIT.
54 * In all request and reply descriptors, replaced VF_ID
55 * field with MSIxIndex field.
56 * Removed DevHandle field from
57 * MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR and made those
59 * Added RAID Accelerator functionality.
60 * 07-30-09 02.00.13 Bumped MPI2_HEADER_VERSION_UNIT.
61 * 10-28-09 02.00.14 Bumped MPI2_HEADER_VERSION_UNIT.
62 * Added MSI-x index mask and shift for Reply Post Host
64 * Added function code for Host Based Discovery Action.
65 * 02-10-10 02.00.15 Bumped MPI2_HEADER_VERSION_UNIT.
66 * Added define for MPI2_FUNCTION_PWR_MGMT_CONTROL.
67 * Added defines for product-specific range of message
68 * function codes, 0xF0 to 0xFF.
69 * 05-12-10 02.00.16 Bumped MPI2_HEADER_VERSION_UNIT.
70 * Added alternative defines for the SGE Direction bit.
71 * 08-11-10 02.00.17 Bumped MPI2_HEADER_VERSION_UNIT.
72 * 11-10-10 02.00.18 Bumped MPI2_HEADER_VERSION_UNIT.
73 * Added MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR define.
74 * 02-23-11 02.00.19 Bumped MPI2_HEADER_VERSION_UNIT.
75 * Added MPI2_FUNCTION_SEND_HOST_MESSAGE.
76 * 03-09-11 02.00.20 Bumped MPI2_HEADER_VERSION_UNIT.
77 * 05-25-11 02.00.21 Bumped MPI2_HEADER_VERSION_UNIT.
78 * 08-24-11 02.00.22 Bumped MPI2_HEADER_VERSION_UNIT.
79 * 11-18-11 02.00.23 Bumped MPI2_HEADER_VERSION_UNIT.
80 * Incorporating additions for MPI v2.5.
81 * 02-06-12 02.00.24 Bumped MPI2_HEADER_VERSION_UNIT.
82 * 03-29-12 02.00.25 Bumped MPI2_HEADER_VERSION_UNIT.
83 * Added Hard Reset delay timings.
84 * 07-10-12 02.00.26 Bumped MPI2_HEADER_VERSION_UNIT.
85 * 07-26-12 02.00.27 Bumped MPI2_HEADER_VERSION_UNIT.
86 * 11-27-12 02.00.28 Bumped MPI2_HEADER_VERSION_UNIT.
87 * 12-20-12 02.00.29 Bumped MPI2_HEADER_VERSION_UNIT.
88 * Added MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET.
89 * 04-09-13 02.00.30 Bumped MPI2_HEADER_VERSION_UNIT.
90 * 04-17-13 02.00.31 Bumped MPI2_HEADER_VERSION_UNIT.
91 * 08-19-13 02.00.32 Bumped MPI2_HEADER_VERSION_UNIT.
92 * 12-05-13 02.00.33 Bumped MPI2_HEADER_VERSION_UNIT.
93 * 01-08-14 02.00.34 Bumped MPI2_HEADER_VERSION_UNIT
94 * 06-13-14 02.00.35 Bumped MPI2_HEADER_VERSION_UNIT.
95 * 11-18-14 02.00.36 Updated copyright information.
96 * Bumped MPI2_HEADER_VERSION_UNIT.
97 * 03-xx-15 02.00.37 Bumped MPI2_HEADER_VERSION_UNIT.
98 * Added Scratchpad registers to
99 * MPI2_SYSTEM_INTERFACE_REGS.
100 * Added MPI2_DIAG_SBR_RELOAD.
101 * --------------------------------------------------------------------------
107 /*****************************************************************************
109 * MPI Version Definitions
111 *****************************************************************************/
113 #define MPI2_VERSION_MAJOR_MASK (0xFF00)
114 #define MPI2_VERSION_MAJOR_SHIFT (8)
115 #define MPI2_VERSION_MINOR_MASK (0x00FF)
116 #define MPI2_VERSION_MINOR_SHIFT (0)
118 /*major version for all MPI v2.x */
119 #define MPI2_VERSION_MAJOR (0x02)
121 /*minor version for MPI v2.0 compatible products */
122 #define MPI2_VERSION_MINOR (0x00)
123 #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
125 #define MPI2_VERSION_02_00 (0x0200)
127 /*minor version for MPI v2.5 compatible products */
128 #define MPI25_VERSION_MINOR (0x05)
129 #define MPI25_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
131 #define MPI2_VERSION_02_05 (0x0205)
133 /*minor version for MPI v2.6 compatible products */
134 #define MPI26_VERSION_MINOR (0x06)
135 #define MPI26_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
137 #define MPI2_VERSION_02_06 (0x0206)
139 /*Unit and Dev versioning for this MPI header set */
140 #define MPI2_HEADER_VERSION_UNIT (0x23)
141 #define MPI2_HEADER_VERSION_DEV (0x00)
142 #define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00)
143 #define MPI2_HEADER_VERSION_UNIT_SHIFT (8)
144 #define MPI2_HEADER_VERSION_DEV_MASK (0x00FF)
145 #define MPI2_HEADER_VERSION_DEV_SHIFT (0)
146 #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | \
147 MPI2_HEADER_VERSION_DEV)
149 /*****************************************************************************
151 * IOC State Definitions
153 *****************************************************************************/
155 #define MPI2_IOC_STATE_RESET (0x00000000)
156 #define MPI2_IOC_STATE_READY (0x10000000)
157 #define MPI2_IOC_STATE_OPERATIONAL (0x20000000)
158 #define MPI2_IOC_STATE_FAULT (0x40000000)
160 #define MPI2_IOC_STATE_MASK (0xF0000000)
161 #define MPI2_IOC_STATE_SHIFT (28)
163 /*Fault state range for prodcut specific codes */
164 #define MPI2_FAULT_PRODUCT_SPECIFIC_MIN (0x0000)
165 #define MPI2_FAULT_PRODUCT_SPECIFIC_MAX (0xEFFF)
167 /*****************************************************************************
169 * System Interface Register Definitions
171 *****************************************************************************/
173 typedef volatile struct _MPI2_SYSTEM_INTERFACE_REGS {
174 U32 Doorbell; /*0x00 */
175 U32 WriteSequence; /*0x04 */
176 U32 HostDiagnostic; /*0x08 */
177 U32 Reserved1; /*0x0C */
178 U32 DiagRWData; /*0x10 */
179 U32 DiagRWAddressLow; /*0x14 */
180 U32 DiagRWAddressHigh; /*0x18 */
181 U32 Reserved2[5]; /*0x1C */
182 U32 HostInterruptStatus; /*0x30 */
183 U32 HostInterruptMask; /*0x34 */
184 U32 DCRData; /*0x38 */
185 U32 DCRAddress; /*0x3C */
186 U32 Reserved3[2]; /*0x40 */
187 U32 ReplyFreeHostIndex; /*0x48 */
188 U32 Reserved4[8]; /*0x4C */
189 U32 ReplyPostHostIndex; /*0x6C */
190 U32 Reserved5; /*0x70 */
191 U32 HCBSize; /*0x74 */
192 U32 HCBAddressLow; /*0x78 */
193 U32 HCBAddressHigh; /*0x7C */
194 U32 Reserved6[12]; /*0x80 */
195 U32 Scratchpad[4]; /*0xB0 */
196 U32 RequestDescriptorPostLow; /*0xC0 */
197 U32 RequestDescriptorPostHigh; /*0xC4 */
198 U32 AtomicRequestDescriptorPost;/*0xC8 */
199 U32 Reserved7[13]; /*0xCC */
200 } MPI2_SYSTEM_INTERFACE_REGS,
201 *PTR_MPI2_SYSTEM_INTERFACE_REGS,
202 Mpi2SystemInterfaceRegs_t,
203 *pMpi2SystemInterfaceRegs_t;
206 *Defines for working with the Doorbell register.
208 #define MPI2_DOORBELL_OFFSET (0x00000000)
210 /*IOC --> System values */
211 #define MPI2_DOORBELL_USED (0x08000000)
212 #define MPI2_DOORBELL_WHO_INIT_MASK (0x07000000)
213 #define MPI2_DOORBELL_WHO_INIT_SHIFT (24)
214 #define MPI2_DOORBELL_FAULT_CODE_MASK (0x0000FFFF)
215 #define MPI2_DOORBELL_DATA_MASK (0x0000FFFF)
217 /*System --> IOC values */
218 #define MPI2_DOORBELL_FUNCTION_MASK (0xFF000000)
219 #define MPI2_DOORBELL_FUNCTION_SHIFT (24)
220 #define MPI2_DOORBELL_ADD_DWORDS_MASK (0x00FF0000)
221 #define MPI2_DOORBELL_ADD_DWORDS_SHIFT (16)
224 *Defines for the WriteSequence register
226 #define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004)
227 #define MPI2_WRSEQ_KEY_VALUE_MASK (0x0000000F)
228 #define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0)
229 #define MPI2_WRSEQ_1ST_KEY_VALUE (0xF)
230 #define MPI2_WRSEQ_2ND_KEY_VALUE (0x4)
231 #define MPI2_WRSEQ_3RD_KEY_VALUE (0xB)
232 #define MPI2_WRSEQ_4TH_KEY_VALUE (0x2)
233 #define MPI2_WRSEQ_5TH_KEY_VALUE (0x7)
234 #define MPI2_WRSEQ_6TH_KEY_VALUE (0xD)
237 *Defines for the HostDiagnostic register
239 #define MPI2_HOST_DIAGNOSTIC_OFFSET (0x00000008)
241 #define MPI2_DIAG_SBR_RELOAD (0x00002000)
243 #define MPI2_DIAG_BOOT_DEVICE_SELECT_MASK (0x00001800)
244 #define MPI2_DIAG_BOOT_DEVICE_SELECT_DEFAULT (0x00000000)
245 #define MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW (0x00000800)
247 #define MPI2_DIAG_CLEAR_FLASH_BAD_SIG (0x00000400)
248 #define MPI2_DIAG_FORCE_HCB_ON_RESET (0x00000200)
249 #define MPI2_DIAG_HCB_MODE (0x00000100)
250 #define MPI2_DIAG_DIAG_WRITE_ENABLE (0x00000080)
251 #define MPI2_DIAG_FLASH_BAD_SIG (0x00000040)
252 #define MPI2_DIAG_RESET_HISTORY (0x00000020)
253 #define MPI2_DIAG_DIAG_RW_ENABLE (0x00000010)
254 #define MPI2_DIAG_RESET_ADAPTER (0x00000004)
255 #define MPI2_DIAG_HOLD_IOC_RESET (0x00000002)
258 *Offsets for DiagRWData and address
260 #define MPI2_DIAG_RW_DATA_OFFSET (0x00000010)
261 #define MPI2_DIAG_RW_ADDRESS_LOW_OFFSET (0x00000014)
262 #define MPI2_DIAG_RW_ADDRESS_HIGH_OFFSET (0x00000018)
265 *Defines for the HostInterruptStatus register
267 #define MPI2_HOST_INTERRUPT_STATUS_OFFSET (0x00000030)
268 #define MPI2_HIS_SYS2IOC_DB_STATUS (0x80000000)
269 #define MPI2_HIS_IOP_DOORBELL_STATUS MPI2_HIS_SYS2IOC_DB_STATUS
270 #define MPI2_HIS_RESET_IRQ_STATUS (0x40000000)
271 #define MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT (0x00000008)
272 #define MPI2_HIS_IOC2SYS_DB_STATUS (0x00000001)
273 #define MPI2_HIS_DOORBELL_INTERRUPT MPI2_HIS_IOC2SYS_DB_STATUS
276 *Defines for the HostInterruptMask register
278 #define MPI2_HOST_INTERRUPT_MASK_OFFSET (0x00000034)
279 #define MPI2_HIM_RESET_IRQ_MASK (0x40000000)
280 #define MPI2_HIM_REPLY_INT_MASK (0x00000008)
281 #define MPI2_HIM_RIM MPI2_HIM_REPLY_INT_MASK
282 #define MPI2_HIM_IOC2SYS_DB_MASK (0x00000001)
283 #define MPI2_HIM_DIM MPI2_HIM_IOC2SYS_DB_MASK
286 *Offsets for DCRData and address
288 #define MPI2_DCR_DATA_OFFSET (0x00000038)
289 #define MPI2_DCR_ADDRESS_OFFSET (0x0000003C)
292 *Offset for the Reply Free Queue
294 #define MPI2_REPLY_FREE_HOST_INDEX_OFFSET (0x00000048)
297 *Defines for the Reply Descriptor Post Queue
299 #define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C)
300 #define MPI2_REPLY_POST_HOST_INDEX_MASK (0x00FFFFFF)
301 #define MPI2_RPHI_MSIX_INDEX_MASK (0xFF000000)
302 #define MPI2_RPHI_MSIX_INDEX_SHIFT (24)
303 #define MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET (0x0000030C) /*MPI v2.5 only*/
307 *Defines for the HCBSize and address
309 #define MPI2_HCB_SIZE_OFFSET (0x00000074)
310 #define MPI2_HCB_SIZE_SIZE_MASK (0xFFFFF000)
311 #define MPI2_HCB_SIZE_HCB_ENABLE (0x00000001)
313 #define MPI2_HCB_ADDRESS_LOW_OFFSET (0x00000078)
314 #define MPI2_HCB_ADDRESS_HIGH_OFFSET (0x0000007C)
317 *Offsets for the Scratchpad registers
319 #define MPI26_SCRATCHPAD0_OFFSET (0x000000B0)
320 #define MPI26_SCRATCHPAD1_OFFSET (0x000000B4)
321 #define MPI26_SCRATCHPAD2_OFFSET (0x000000B8)
322 #define MPI26_SCRATCHPAD3_OFFSET (0x000000BC)
325 *Offsets for the Request Descriptor Post Queue
327 #define MPI2_REQUEST_DESCRIPTOR_POST_LOW_OFFSET (0x000000C0)
328 #define MPI2_REQUEST_DESCRIPTOR_POST_HIGH_OFFSET (0x000000C4)
329 #define MPI26_ATOMIC_REQUEST_DESCRIPTOR_POST_OFFSET (0x000000C8)
331 /*Hard Reset delay timings */
332 #define MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC (50000)
333 #define MPI2_HARD_RESET_PCIE_RESET_READ_WINDOW_MICRO_SEC (255000)
334 #define MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC (256000)
336 /*****************************************************************************
338 * Message Descriptors
340 *****************************************************************************/
342 /*Request Descriptors */
344 /*Default Request Descriptor */
345 typedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR {
346 U8 RequestFlags; /*0x00 */
347 U8 MSIxIndex; /*0x01 */
350 U16 DescriptorTypeDependent; /*0x06 */
351 } MPI2_DEFAULT_REQUEST_DESCRIPTOR,
352 *PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR,
353 Mpi2DefaultRequestDescriptor_t,
354 *pMpi2DefaultRequestDescriptor_t;
356 /*defines for the RequestFlags field */
357 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x1E)
358 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_RSHIFT (1)
359 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00)
360 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET (0x02)
361 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06)
362 #define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE (0x08)
363 #define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR (0x0A)
364 #define MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO (0x0C)
366 #define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01)
368 /*High Priority Request Descriptor */
369 typedef struct _MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR {
370 U8 RequestFlags; /*0x00 */
371 U8 MSIxIndex; /*0x01 */
374 U16 Reserved1; /*0x06 */
375 } MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
376 *PTR_MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
377 Mpi2HighPriorityRequestDescriptor_t,
378 *pMpi2HighPriorityRequestDescriptor_t;
380 /*SCSI IO Request Descriptor */
381 typedef struct _MPI2_SCSI_IO_REQUEST_DESCRIPTOR {
382 U8 RequestFlags; /*0x00 */
383 U8 MSIxIndex; /*0x01 */
386 U16 DevHandle; /*0x06 */
387 } MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
388 *PTR_MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
389 Mpi2SCSIIORequestDescriptor_t,
390 *pMpi2SCSIIORequestDescriptor_t;
392 /*SCSI Target Request Descriptor */
393 typedef struct _MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR {
394 U8 RequestFlags; /*0x00 */
395 U8 MSIxIndex; /*0x01 */
398 U16 IoIndex; /*0x06 */
399 } MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
400 *PTR_MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
401 Mpi2SCSITargetRequestDescriptor_t,
402 *pMpi2SCSITargetRequestDescriptor_t;
404 /*RAID Accelerator Request Descriptor */
405 typedef struct _MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR {
406 U8 RequestFlags; /*0x00 */
407 U8 MSIxIndex; /*0x01 */
410 U16 Reserved; /*0x06 */
411 } MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
412 *PTR_MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
413 Mpi2RAIDAcceleratorRequestDescriptor_t,
414 *pMpi2RAIDAcceleratorRequestDescriptor_t;
416 /*Fast Path SCSI IO Request Descriptor */
417 typedef MPI2_SCSI_IO_REQUEST_DESCRIPTOR
418 MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR,
419 *PTR_MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR,
420 Mpi25FastPathSCSIIORequestDescriptor_t,
421 *pMpi25FastPathSCSIIORequestDescriptor_t;
423 /*union of Request Descriptors */
424 typedef union _MPI2_REQUEST_DESCRIPTOR_UNION {
425 MPI2_DEFAULT_REQUEST_DESCRIPTOR Default;
426 MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority;
427 MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO;
428 MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget;
429 MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator;
430 MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR FastPathSCSIIO;
432 } MPI2_REQUEST_DESCRIPTOR_UNION,
433 *PTR_MPI2_REQUEST_DESCRIPTOR_UNION,
434 Mpi2RequestDescriptorUnion_t,
435 *pMpi2RequestDescriptorUnion_t;
437 /*Atomic Request Descriptors */
440 * All Atomic Request Descriptors have the same format, so the following
441 * structure is used for all Atomic Request Descriptors:
442 * Atomic Default Request Descriptor
443 * Atomic High Priority Request Descriptor
444 * Atomic SCSI IO Request Descriptor
445 * Atomic SCSI Target Request Descriptor
446 * Atomic RAID Accelerator Request Descriptor
447 * Atomic Fast Path SCSI IO Request Descriptor
450 /*Atomic Request Descriptor */
451 typedef struct _MPI26_ATOMIC_REQUEST_DESCRIPTOR {
452 U8 RequestFlags; /* 0x00 */
453 U8 MSIxIndex; /* 0x01 */
455 } MPI26_ATOMIC_REQUEST_DESCRIPTOR,
456 *PTR_MPI26_ATOMIC_REQUEST_DESCRIPTOR,
457 Mpi26AtomicRequestDescriptor_t,
458 *pMpi26AtomicRequestDescriptor_t;
460 /*for the RequestFlags field, use the same
461 *defines as MPI2_DEFAULT_REQUEST_DESCRIPTOR
464 /*Reply Descriptors */
466 /*Default Reply Descriptor */
467 typedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR {
468 U8 ReplyFlags; /*0x00 */
469 U8 MSIxIndex; /*0x01 */
470 U16 DescriptorTypeDependent1; /*0x02 */
471 U32 DescriptorTypeDependent2; /*0x04 */
472 } MPI2_DEFAULT_REPLY_DESCRIPTOR,
473 *PTR_MPI2_DEFAULT_REPLY_DESCRIPTOR,
474 Mpi2DefaultReplyDescriptor_t,
475 *pMpi2DefaultReplyDescriptor_t;
477 /*defines for the ReplyFlags field */
478 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F)
479 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00)
480 #define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY (0x01)
481 #define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS (0x02)
482 #define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER (0x03)
483 #define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS (0x05)
484 #define MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS (0x06)
485 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F)
487 /*values for marking a reply descriptor as unused */
488 #define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK (0xFFFFFFFF)
489 #define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK (0xFFFFFFFF)
491 /*Address Reply Descriptor */
492 typedef struct _MPI2_ADDRESS_REPLY_DESCRIPTOR {
493 U8 ReplyFlags; /*0x00 */
494 U8 MSIxIndex; /*0x01 */
496 U32 ReplyFrameAddress; /*0x04 */
497 } MPI2_ADDRESS_REPLY_DESCRIPTOR,
498 *PTR_MPI2_ADDRESS_REPLY_DESCRIPTOR,
499 Mpi2AddressReplyDescriptor_t,
500 *pMpi2AddressReplyDescriptor_t;
502 #define MPI2_ADDRESS_REPLY_SMID_INVALID (0x00)
504 /*SCSI IO Success Reply Descriptor */
505 typedef struct _MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR {
506 U8 ReplyFlags; /*0x00 */
507 U8 MSIxIndex; /*0x01 */
509 U16 TaskTag; /*0x04 */
510 U16 Reserved1; /*0x06 */
511 } MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
512 *PTR_MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
513 Mpi2SCSIIOSuccessReplyDescriptor_t,
514 *pMpi2SCSIIOSuccessReplyDescriptor_t;
516 /*TargetAssist Success Reply Descriptor */
517 typedef struct _MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR {
518 U8 ReplyFlags; /*0x00 */
519 U8 MSIxIndex; /*0x01 */
521 U8 SequenceNumber; /*0x04 */
522 U8 Reserved1; /*0x05 */
523 U16 IoIndex; /*0x06 */
524 } MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
525 *PTR_MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
526 Mpi2TargetAssistSuccessReplyDescriptor_t,
527 *pMpi2TargetAssistSuccessReplyDescriptor_t;
529 /*Target Command Buffer Reply Descriptor */
530 typedef struct _MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR {
531 U8 ReplyFlags; /*0x00 */
532 U8 MSIxIndex; /*0x01 */
535 U16 InitiatorDevHandle; /*0x04 */
536 U16 IoIndex; /*0x06 */
537 } MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
538 *PTR_MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
539 Mpi2TargetCommandBufferReplyDescriptor_t,
540 *pMpi2TargetCommandBufferReplyDescriptor_t;
542 /*defines for Flags field */
543 #define MPI2_RPY_DESCRIPT_TCB_FLAGS_PHYNUM_MASK (0x3F)
545 /*RAID Accelerator Success Reply Descriptor */
546 typedef struct _MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR {
547 U8 ReplyFlags; /*0x00 */
548 U8 MSIxIndex; /*0x01 */
550 U32 Reserved; /*0x04 */
551 } MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
552 *PTR_MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
553 Mpi2RAIDAcceleratorSuccessReplyDescriptor_t,
554 *pMpi2RAIDAcceleratorSuccessReplyDescriptor_t;
556 /*Fast Path SCSI IO Success Reply Descriptor */
557 typedef MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR
558 MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
559 *PTR_MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
560 Mpi25FastPathSCSIIOSuccessReplyDescriptor_t,
561 *pMpi25FastPathSCSIIOSuccessReplyDescriptor_t;
563 /*union of Reply Descriptors */
564 typedef union _MPI2_REPLY_DESCRIPTORS_UNION {
565 MPI2_DEFAULT_REPLY_DESCRIPTOR Default;
566 MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply;
567 MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess;
568 MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess;
569 MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer;
570 MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR RAIDAcceleratorSuccess;
571 MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR FastPathSCSIIOSuccess;
573 } MPI2_REPLY_DESCRIPTORS_UNION,
574 *PTR_MPI2_REPLY_DESCRIPTORS_UNION,
575 Mpi2ReplyDescriptorsUnion_t,
576 *pMpi2ReplyDescriptorsUnion_t;
578 /*****************************************************************************
582 *****************************************************************************/
584 #define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00)
585 #define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01)
586 #define MPI2_FUNCTION_IOC_INIT (0x02)
587 #define MPI2_FUNCTION_IOC_FACTS (0x03)
588 #define MPI2_FUNCTION_CONFIG (0x04)
589 #define MPI2_FUNCTION_PORT_FACTS (0x05)
590 #define MPI2_FUNCTION_PORT_ENABLE (0x06)
591 #define MPI2_FUNCTION_EVENT_NOTIFICATION (0x07)
592 #define MPI2_FUNCTION_EVENT_ACK (0x08)
593 #define MPI2_FUNCTION_FW_DOWNLOAD (0x09)
594 #define MPI2_FUNCTION_TARGET_ASSIST (0x0B)
595 #define MPI2_FUNCTION_TARGET_STATUS_SEND (0x0C)
596 #define MPI2_FUNCTION_TARGET_MODE_ABORT (0x0D)
597 #define MPI2_FUNCTION_FW_UPLOAD (0x12)
598 #define MPI2_FUNCTION_RAID_ACTION (0x15)
599 #define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16)
600 #define MPI2_FUNCTION_TOOLBOX (0x17)
601 #define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18)
602 #define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A)
603 #define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B)
604 #define MPI2_FUNCTION_IO_UNIT_CONTROL (0x1B)
605 #define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C)
606 #define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D)
607 #define MPI2_FUNCTION_DIAG_RELEASE (0x1E)
608 #define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24)
609 #define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25)
610 #define MPI2_FUNCTION_RAID_ACCELERATOR (0x2C)
611 #define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION (0x2F)
612 #define MPI2_FUNCTION_PWR_MGMT_CONTROL (0x30)
613 #define MPI2_FUNCTION_SEND_HOST_MESSAGE (0x31)
614 #define MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC (0xF0)
615 #define MPI2_FUNCTION_MAX_PRODUCT_SPECIFIC (0xFF)
617 /*Doorbell functions */
618 #define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40)
619 #define MPI2_FUNCTION_HANDSHAKE (0x42)
621 /*****************************************************************************
625 *****************************************************************************/
627 /*mask for IOCStatus status value */
628 #define MPI2_IOCSTATUS_MASK (0x7FFF)
630 /****************************************************************************
631 * Common IOCStatus values for all replies
632 ****************************************************************************/
634 #define MPI2_IOCSTATUS_SUCCESS (0x0000)
635 #define MPI2_IOCSTATUS_INVALID_FUNCTION (0x0001)
636 #define MPI2_IOCSTATUS_BUSY (0x0002)
637 #define MPI2_IOCSTATUS_INVALID_SGL (0x0003)
638 #define MPI2_IOCSTATUS_INTERNAL_ERROR (0x0004)
639 #define MPI2_IOCSTATUS_INVALID_VPID (0x0005)
640 #define MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES (0x0006)
641 #define MPI2_IOCSTATUS_INVALID_FIELD (0x0007)
642 #define MPI2_IOCSTATUS_INVALID_STATE (0x0008)
643 #define MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED (0x0009)
644 #define MPI2_IOCSTATUS_INSUFFICIENT_POWER (0x000A)
646 /****************************************************************************
647 * Config IOCStatus values
648 ****************************************************************************/
650 #define MPI2_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020)
651 #define MPI2_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021)
652 #define MPI2_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022)
653 #define MPI2_IOCSTATUS_CONFIG_INVALID_DATA (0x0023)
654 #define MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024)
655 #define MPI2_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025)
657 /****************************************************************************
659 ****************************************************************************/
661 #define MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR (0x0040)
662 #define MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE (0x0042)
663 #define MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE (0x0043)
664 #define MPI2_IOCSTATUS_SCSI_DATA_OVERRUN (0x0044)
665 #define MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN (0x0045)
666 #define MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR (0x0046)
667 #define MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR (0x0047)
668 #define MPI2_IOCSTATUS_SCSI_TASK_TERMINATED (0x0048)
669 #define MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH (0x0049)
670 #define MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED (0x004A)
671 #define MPI2_IOCSTATUS_SCSI_IOC_TERMINATED (0x004B)
672 #define MPI2_IOCSTATUS_SCSI_EXT_TERMINATED (0x004C)
674 /****************************************************************************
675 * For use by SCSI Initiator and SCSI Target end-to-end data protection
676 ****************************************************************************/
678 #define MPI2_IOCSTATUS_EEDP_GUARD_ERROR (0x004D)
679 #define MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR (0x004E)
680 #define MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR (0x004F)
682 /****************************************************************************
684 ****************************************************************************/
686 #define MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX (0x0062)
687 #define MPI2_IOCSTATUS_TARGET_ABORTED (0x0063)
688 #define MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE (0x0064)
689 #define MPI2_IOCSTATUS_TARGET_NO_CONNECTION (0x0065)
690 #define MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH (0x006A)
691 #define MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR (0x006D)
692 #define MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA (0x006E)
693 #define MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT (0x006F)
694 #define MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT (0x0070)
695 #define MPI2_IOCSTATUS_TARGET_NAK_RECEIVED (0x0071)
697 /****************************************************************************
698 * Serial Attached SCSI values
699 ****************************************************************************/
701 #define MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED (0x0090)
702 #define MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN (0x0091)
704 /****************************************************************************
705 * Diagnostic Buffer Post / Diagnostic Release values
706 ****************************************************************************/
708 #define MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED (0x00A0)
710 /****************************************************************************
711 * RAID Accelerator values
712 ****************************************************************************/
714 #define MPI2_IOCSTATUS_RAID_ACCEL_ERROR (0x00B0)
716 /****************************************************************************
717 * IOCStatus flag to indicate that log info is available
718 ****************************************************************************/
720 #define MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE (0x8000)
722 /****************************************************************************
724 ****************************************************************************/
726 #define MPI2_IOCLOGINFO_TYPE_MASK (0xF0000000)
727 #define MPI2_IOCLOGINFO_TYPE_SHIFT (28)
728 #define MPI2_IOCLOGINFO_TYPE_NONE (0x0)
729 #define MPI2_IOCLOGINFO_TYPE_SCSI (0x1)
730 #define MPI2_IOCLOGINFO_TYPE_FC (0x2)
731 #define MPI2_IOCLOGINFO_TYPE_SAS (0x3)
732 #define MPI2_IOCLOGINFO_TYPE_ISCSI (0x4)
733 #define MPI2_IOCLOGINFO_LOG_DATA_MASK (0x0FFFFFFF)
735 /*****************************************************************************
737 * Standard Message Structures
739 *****************************************************************************/
741 /****************************************************************************
742 *Request Message Header for all request messages
743 ****************************************************************************/
745 typedef struct _MPI2_REQUEST_HEADER {
746 U16 FunctionDependent1; /*0x00 */
747 U8 ChainOffset; /*0x02 */
748 U8 Function; /*0x03 */
749 U16 FunctionDependent2; /*0x04 */
750 U8 FunctionDependent3; /*0x06 */
751 U8 MsgFlags; /*0x07 */
754 U16 Reserved1; /*0x0A */
755 } MPI2_REQUEST_HEADER, *PTR_MPI2_REQUEST_HEADER,
756 MPI2RequestHeader_t, *pMPI2RequestHeader_t;
758 /****************************************************************************
760 ****************************************************************************/
762 typedef struct _MPI2_DEFAULT_REPLY {
763 U16 FunctionDependent1; /*0x00 */
764 U8 MsgLength; /*0x02 */
765 U8 Function; /*0x03 */
766 U16 FunctionDependent2; /*0x04 */
767 U8 FunctionDependent3; /*0x06 */
768 U8 MsgFlags; /*0x07 */
771 U16 Reserved1; /*0x0A */
772 U16 FunctionDependent5; /*0x0C */
773 U16 IOCStatus; /*0x0E */
774 U32 IOCLogInfo; /*0x10 */
775 } MPI2_DEFAULT_REPLY, *PTR_MPI2_DEFAULT_REPLY,
776 MPI2DefaultReply_t, *pMPI2DefaultReply_t;
778 /*common version structure/union used in messages and configuration pages */
780 typedef struct _MPI2_VERSION_STRUCT {
785 } MPI2_VERSION_STRUCT;
787 typedef union _MPI2_VERSION_UNION {
788 MPI2_VERSION_STRUCT Struct;
790 } MPI2_VERSION_UNION;
792 /*LUN field defines, common to many structures */
793 #define MPI2_LUN_FIRST_LEVEL_ADDRESSING (0x0000FFFF)
794 #define MPI2_LUN_SECOND_LEVEL_ADDRESSING (0xFFFF0000)
795 #define MPI2_LUN_THIRD_LEVEL_ADDRESSING (0x0000FFFF)
796 #define MPI2_LUN_FOURTH_LEVEL_ADDRESSING (0xFFFF0000)
797 #define MPI2_LUN_LEVEL_1_WORD (0xFF00)
798 #define MPI2_LUN_LEVEL_1_DWORD (0x0000FF00)
800 /*****************************************************************************
802 * Fusion-MPT MPI Scatter Gather Elements
804 *****************************************************************************/
806 /****************************************************************************
807 * MPI Simple Element structures
808 ****************************************************************************/
810 typedef struct _MPI2_SGE_SIMPLE32 {
813 } MPI2_SGE_SIMPLE32, *PTR_MPI2_SGE_SIMPLE32,
814 Mpi2SGESimple32_t, *pMpi2SGESimple32_t;
816 typedef struct _MPI2_SGE_SIMPLE64 {
819 } MPI2_SGE_SIMPLE64, *PTR_MPI2_SGE_SIMPLE64,
820 Mpi2SGESimple64_t, *pMpi2SGESimple64_t;
822 typedef struct _MPI2_SGE_SIMPLE_UNION {
828 } MPI2_SGE_SIMPLE_UNION,
829 *PTR_MPI2_SGE_SIMPLE_UNION,
830 Mpi2SGESimpleUnion_t,
831 *pMpi2SGESimpleUnion_t;
833 /****************************************************************************
834 * MPI Chain Element structures - for MPI v2.0 products only
835 ****************************************************************************/
837 typedef struct _MPI2_SGE_CHAIN32 {
842 } MPI2_SGE_CHAIN32, *PTR_MPI2_SGE_CHAIN32,
843 Mpi2SGEChain32_t, *pMpi2SGEChain32_t;
845 typedef struct _MPI2_SGE_CHAIN64 {
850 } MPI2_SGE_CHAIN64, *PTR_MPI2_SGE_CHAIN64,
851 Mpi2SGEChain64_t, *pMpi2SGEChain64_t;
853 typedef struct _MPI2_SGE_CHAIN_UNION {
861 } MPI2_SGE_CHAIN_UNION,
862 *PTR_MPI2_SGE_CHAIN_UNION,
864 *pMpi2SGEChainUnion_t;
866 /****************************************************************************
867 * MPI Transaction Context Element structures - for MPI v2.0 products only
868 ****************************************************************************/
870 typedef struct _MPI2_SGE_TRANSACTION32 {
875 U32 TransactionContext[1];
876 U32 TransactionDetails[1];
877 } MPI2_SGE_TRANSACTION32,
878 *PTR_MPI2_SGE_TRANSACTION32,
879 Mpi2SGETransaction32_t,
880 *pMpi2SGETransaction32_t;
882 typedef struct _MPI2_SGE_TRANSACTION64 {
887 U32 TransactionContext[2];
888 U32 TransactionDetails[1];
889 } MPI2_SGE_TRANSACTION64,
890 *PTR_MPI2_SGE_TRANSACTION64,
891 Mpi2SGETransaction64_t,
892 *pMpi2SGETransaction64_t;
894 typedef struct _MPI2_SGE_TRANSACTION96 {
899 U32 TransactionContext[3];
900 U32 TransactionDetails[1];
901 } MPI2_SGE_TRANSACTION96, *PTR_MPI2_SGE_TRANSACTION96,
902 Mpi2SGETransaction96_t, *pMpi2SGETransaction96_t;
904 typedef struct _MPI2_SGE_TRANSACTION128 {
909 U32 TransactionContext[4];
910 U32 TransactionDetails[1];
911 } MPI2_SGE_TRANSACTION128, *PTR_MPI2_SGE_TRANSACTION128,
912 Mpi2SGETransaction_t128, *pMpi2SGETransaction_t128;
914 typedef struct _MPI2_SGE_TRANSACTION_UNION {
920 U32 TransactionContext32[1];
921 U32 TransactionContext64[2];
922 U32 TransactionContext96[3];
923 U32 TransactionContext128[4];
925 U32 TransactionDetails[1];
926 } MPI2_SGE_TRANSACTION_UNION,
927 *PTR_MPI2_SGE_TRANSACTION_UNION,
928 Mpi2SGETransactionUnion_t,
929 *pMpi2SGETransactionUnion_t;
931 /****************************************************************************
932 * MPI SGE union for IO SGL's - for MPI v2.0 products only
933 ****************************************************************************/
935 typedef struct _MPI2_MPI_SGE_IO_UNION {
937 MPI2_SGE_SIMPLE_UNION Simple;
938 MPI2_SGE_CHAIN_UNION Chain;
940 } MPI2_MPI_SGE_IO_UNION, *PTR_MPI2_MPI_SGE_IO_UNION,
941 Mpi2MpiSGEIOUnion_t, *pMpi2MpiSGEIOUnion_t;
943 /****************************************************************************
944 * MPI SGE union for SGL's with Simple and Transaction elements - for MPI v2.0 products only
945 ****************************************************************************/
947 typedef struct _MPI2_SGE_TRANS_SIMPLE_UNION {
949 MPI2_SGE_SIMPLE_UNION Simple;
950 MPI2_SGE_TRANSACTION_UNION Transaction;
952 } MPI2_SGE_TRANS_SIMPLE_UNION,
953 *PTR_MPI2_SGE_TRANS_SIMPLE_UNION,
954 Mpi2SGETransSimpleUnion_t,
955 *pMpi2SGETransSimpleUnion_t;
957 /****************************************************************************
958 * All MPI SGE types union
959 ****************************************************************************/
961 typedef struct _MPI2_MPI_SGE_UNION {
963 MPI2_SGE_SIMPLE_UNION Simple;
964 MPI2_SGE_CHAIN_UNION Chain;
965 MPI2_SGE_TRANSACTION_UNION Transaction;
967 } MPI2_MPI_SGE_UNION, *PTR_MPI2_MPI_SGE_UNION,
968 Mpi2MpiSgeUnion_t, *pMpi2MpiSgeUnion_t;
970 /****************************************************************************
971 * MPI SGE field definition and masks
972 ****************************************************************************/
974 /*Flags field bit definitions */
976 #define MPI2_SGE_FLAGS_LAST_ELEMENT (0x80)
977 #define MPI2_SGE_FLAGS_END_OF_BUFFER (0x40)
978 #define MPI2_SGE_FLAGS_ELEMENT_TYPE_MASK (0x30)
979 #define MPI2_SGE_FLAGS_LOCAL_ADDRESS (0x08)
980 #define MPI2_SGE_FLAGS_DIRECTION (0x04)
981 #define MPI2_SGE_FLAGS_ADDRESS_SIZE (0x02)
982 #define MPI2_SGE_FLAGS_END_OF_LIST (0x01)
984 #define MPI2_SGE_FLAGS_SHIFT (24)
986 #define MPI2_SGE_LENGTH_MASK (0x00FFFFFF)
987 #define MPI2_SGE_CHAIN_LENGTH_MASK (0x0000FFFF)
991 #define MPI2_SGE_FLAGS_TRANSACTION_ELEMENT (0x00)
992 #define MPI2_SGE_FLAGS_SIMPLE_ELEMENT (0x10)
993 #define MPI2_SGE_FLAGS_CHAIN_ELEMENT (0x30)
994 #define MPI2_SGE_FLAGS_ELEMENT_MASK (0x30)
996 /*Address location */
998 #define MPI2_SGE_FLAGS_SYSTEM_ADDRESS (0x00)
1002 #define MPI2_SGE_FLAGS_IOC_TO_HOST (0x00)
1003 #define MPI2_SGE_FLAGS_HOST_TO_IOC (0x04)
1005 #define MPI2_SGE_FLAGS_DEST (MPI2_SGE_FLAGS_IOC_TO_HOST)
1006 #define MPI2_SGE_FLAGS_SOURCE (MPI2_SGE_FLAGS_HOST_TO_IOC)
1010 #define MPI2_SGE_FLAGS_32_BIT_ADDRESSING (0x00)
1011 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02)
1015 #define MPI2_SGE_FLAGS_32_BIT_CONTEXT (0x00)
1016 #define MPI2_SGE_FLAGS_64_BIT_CONTEXT (0x02)
1017 #define MPI2_SGE_FLAGS_96_BIT_CONTEXT (0x04)
1018 #define MPI2_SGE_FLAGS_128_BIT_CONTEXT (0x06)
1020 #define MPI2_SGE_CHAIN_OFFSET_MASK (0x00FF0000)
1021 #define MPI2_SGE_CHAIN_OFFSET_SHIFT (16)
1023 /****************************************************************************
1024 * MPI SGE operation Macros
1025 ****************************************************************************/
1027 /*SIMPLE FlagsLength manipulations... */
1028 #define MPI2_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_SGE_FLAGS_SHIFT)
1029 #define MPI2_SGE_GET_FLAGS(f) (((f) & ~MPI2_SGE_LENGTH_MASK) >> \
1030 MPI2_SGE_FLAGS_SHIFT)
1031 #define MPI2_SGE_LENGTH(f) ((f) & MPI2_SGE_LENGTH_MASK)
1032 #define MPI2_SGE_CHAIN_LENGTH(f) ((f) & MPI2_SGE_CHAIN_LENGTH_MASK)
1034 #define MPI2_SGE_SET_FLAGS_LENGTH(f, l) (MPI2_SGE_SET_FLAGS(f) | \
1037 #define MPI2_pSGE_GET_FLAGS(psg) MPI2_SGE_GET_FLAGS((psg)->FlagsLength)
1038 #define MPI2_pSGE_GET_LENGTH(psg) MPI2_SGE_LENGTH((psg)->FlagsLength)
1039 #define MPI2_pSGE_SET_FLAGS_LENGTH(psg, f, l) ((psg)->FlagsLength = \
1040 MPI2_SGE_SET_FLAGS_LENGTH(f, l))
1042 /*CAUTION - The following are READ-MODIFY-WRITE! */
1043 #define MPI2_pSGE_SET_FLAGS(psg, f) ((psg)->FlagsLength |= \
1044 MPI2_SGE_SET_FLAGS(f))
1045 #define MPI2_pSGE_SET_LENGTH(psg, l) ((psg)->FlagsLength |= \
1048 #define MPI2_GET_CHAIN_OFFSET(x) ((x & MPI2_SGE_CHAIN_OFFSET_MASK) >> \
1049 MPI2_SGE_CHAIN_OFFSET_SHIFT)
1051 /*****************************************************************************
1053 * Fusion-MPT IEEE Scatter Gather Elements
1055 *****************************************************************************/
1057 /****************************************************************************
1058 * IEEE Simple Element structures
1059 ****************************************************************************/
1061 /*MPI2_IEEE_SGE_SIMPLE32 is for MPI v2.0 products only */
1062 typedef struct _MPI2_IEEE_SGE_SIMPLE32 {
1065 } MPI2_IEEE_SGE_SIMPLE32, *PTR_MPI2_IEEE_SGE_SIMPLE32,
1066 Mpi2IeeeSgeSimple32_t, *pMpi2IeeeSgeSimple32_t;
1068 typedef struct _MPI2_IEEE_SGE_SIMPLE64 {
1074 } MPI2_IEEE_SGE_SIMPLE64, *PTR_MPI2_IEEE_SGE_SIMPLE64,
1075 Mpi2IeeeSgeSimple64_t, *pMpi2IeeeSgeSimple64_t;
1077 typedef union _MPI2_IEEE_SGE_SIMPLE_UNION {
1078 MPI2_IEEE_SGE_SIMPLE32 Simple32;
1079 MPI2_IEEE_SGE_SIMPLE64 Simple64;
1080 } MPI2_IEEE_SGE_SIMPLE_UNION,
1081 *PTR_MPI2_IEEE_SGE_SIMPLE_UNION,
1082 Mpi2IeeeSgeSimpleUnion_t,
1083 *pMpi2IeeeSgeSimpleUnion_t;
1085 /****************************************************************************
1086 * IEEE Chain Element structures
1087 ****************************************************************************/
1089 /*MPI2_IEEE_SGE_CHAIN32 is for MPI v2.0 products only */
1090 typedef MPI2_IEEE_SGE_SIMPLE32 MPI2_IEEE_SGE_CHAIN32;
1092 /*MPI2_IEEE_SGE_CHAIN64 is for MPI v2.0 products only */
1093 typedef MPI2_IEEE_SGE_SIMPLE64 MPI2_IEEE_SGE_CHAIN64;
1095 typedef union _MPI2_IEEE_SGE_CHAIN_UNION {
1096 MPI2_IEEE_SGE_CHAIN32 Chain32;
1097 MPI2_IEEE_SGE_CHAIN64 Chain64;
1098 } MPI2_IEEE_SGE_CHAIN_UNION,
1099 *PTR_MPI2_IEEE_SGE_CHAIN_UNION,
1100 Mpi2IeeeSgeChainUnion_t,
1101 *pMpi2IeeeSgeChainUnion_t;
1103 /*MPI25_IEEE_SGE_CHAIN64 is for MPI v2.5 and later */
1104 typedef struct _MPI25_IEEE_SGE_CHAIN64 {
1110 } MPI25_IEEE_SGE_CHAIN64,
1111 *PTR_MPI25_IEEE_SGE_CHAIN64,
1112 Mpi25IeeeSgeChain64_t,
1113 *pMpi25IeeeSgeChain64_t;
1115 /****************************************************************************
1116 * All IEEE SGE types union
1117 ****************************************************************************/
1119 /*MPI2_IEEE_SGE_UNION is for MPI v2.0 products only */
1120 typedef struct _MPI2_IEEE_SGE_UNION {
1122 MPI2_IEEE_SGE_SIMPLE_UNION Simple;
1123 MPI2_IEEE_SGE_CHAIN_UNION Chain;
1125 } MPI2_IEEE_SGE_UNION, *PTR_MPI2_IEEE_SGE_UNION,
1126 Mpi2IeeeSgeUnion_t, *pMpi2IeeeSgeUnion_t;
1128 /****************************************************************************
1129 * IEEE SGE union for IO SGL's
1130 ****************************************************************************/
1132 typedef union _MPI25_SGE_IO_UNION {
1133 MPI2_IEEE_SGE_SIMPLE64 IeeeSimple;
1134 MPI25_IEEE_SGE_CHAIN64 IeeeChain;
1135 } MPI25_SGE_IO_UNION, *PTR_MPI25_SGE_IO_UNION,
1136 Mpi25SGEIOUnion_t, *pMpi25SGEIOUnion_t;
1138 /****************************************************************************
1139 * IEEE SGE field definitions and masks
1140 ****************************************************************************/
1142 /*Flags field bit definitions */
1144 #define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK (0x80)
1145 #define MPI25_IEEE_SGE_FLAGS_END_OF_LIST (0x40)
1147 #define MPI2_IEEE32_SGE_FLAGS_SHIFT (24)
1149 #define MPI2_IEEE32_SGE_LENGTH_MASK (0x00FFFFFF)
1153 #define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT (0x00)
1154 #define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80)
1156 /*Next Segment Format */
1158 #define MPI26_IEEE_SGE_FLAGS_NSF_MASK (0x1C)
1159 #define MPI26_IEEE_SGE_FLAGS_NSF_MPI_IEEE (0x00)
1161 /*Data Location Address Space */
1163 #define MPI2_IEEE_SGE_FLAGS_ADDR_MASK (0x03)
1164 #define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00)
1165 #define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01)
1166 #define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02)
1167 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03)
1168 #define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR (0x03)
1169 #define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR \
1170 (MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR)
1171 #define MPI26_IEEE_SGE_FLAGS_IOCCTL_ADDR (0x02)
1173 /****************************************************************************
1174 * IEEE SGE operation Macros
1175 ****************************************************************************/
1177 /*SIMPLE FlagsLength manipulations... */
1178 #define MPI2_IEEE32_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_IEEE32_SGE_FLAGS_SHIFT)
1179 #define MPI2_IEEE32_SGE_GET_FLAGS(f) (((f) & ~MPI2_IEEE32_SGE_LENGTH_MASK) \
1180 >> MPI2_IEEE32_SGE_FLAGS_SHIFT)
1181 #define MPI2_IEEE32_SGE_LENGTH(f) ((f) & MPI2_IEEE32_SGE_LENGTH_MASK)
1183 #define MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f, l) (MPI2_IEEE32_SGE_SET_FLAGS(f) |\
1184 MPI2_IEEE32_SGE_LENGTH(l))
1186 #define MPI2_IEEE32_pSGE_GET_FLAGS(psg) \
1187 MPI2_IEEE32_SGE_GET_FLAGS((psg)->FlagsLength)
1188 #define MPI2_IEEE32_pSGE_GET_LENGTH(psg) \
1189 MPI2_IEEE32_SGE_LENGTH((psg)->FlagsLength)
1190 #define MPI2_IEEE32_pSGE_SET_FLAGS_LENGTH(psg, f, l) ((psg)->FlagsLength = \
1191 MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f, l))
1193 /*CAUTION - The following are READ-MODIFY-WRITE! */
1194 #define MPI2_IEEE32_pSGE_SET_FLAGS(psg, f) ((psg)->FlagsLength |= \
1195 MPI2_IEEE32_SGE_SET_FLAGS(f))
1196 #define MPI2_IEEE32_pSGE_SET_LENGTH(psg, l) ((psg)->FlagsLength |= \
1197 MPI2_IEEE32_SGE_LENGTH(l))
1199 /*****************************************************************************
1201 * Fusion-MPT MPI/IEEE Scatter Gather Unions
1203 *****************************************************************************/
1205 typedef union _MPI2_SIMPLE_SGE_UNION {
1206 MPI2_SGE_SIMPLE_UNION MpiSimple;
1207 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
1208 } MPI2_SIMPLE_SGE_UNION, *PTR_MPI2_SIMPLE_SGE_UNION,
1209 Mpi2SimpleSgeUntion_t, *pMpi2SimpleSgeUntion_t;
1211 typedef union _MPI2_SGE_IO_UNION {
1212 MPI2_SGE_SIMPLE_UNION MpiSimple;
1213 MPI2_SGE_CHAIN_UNION MpiChain;
1214 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
1215 MPI2_IEEE_SGE_CHAIN_UNION IeeeChain;
1216 } MPI2_SGE_IO_UNION, *PTR_MPI2_SGE_IO_UNION,
1217 Mpi2SGEIOUnion_t, *pMpi2SGEIOUnion_t;
1219 /****************************************************************************
1221 * Values for SGLFlags field, used in many request messages with an SGL
1223 ****************************************************************************/
1225 /*values for MPI SGL Data Location Address Space subfield */
1226 #define MPI2_SGLFLAGS_ADDRESS_SPACE_MASK (0x0C)
1227 #define MPI2_SGLFLAGS_SYSTEM_ADDRESS_SPACE (0x00)
1228 #define MPI2_SGLFLAGS_IOCDDR_ADDRESS_SPACE (0x04)
1229 #define MPI2_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08)
1230 #define MPI26_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08)
1231 #define MPI2_SGLFLAGS_IOCPLBNTA_ADDRESS_SPACE (0x0C)
1232 /*values for SGL Type subfield */
1233 #define MPI2_SGLFLAGS_SGL_TYPE_MASK (0x03)
1234 #define MPI2_SGLFLAGS_SGL_TYPE_MPI (0x00)
1235 #define MPI2_SGLFLAGS_SGL_TYPE_IEEE32 (0x01)
1236 #define MPI2_SGLFLAGS_SGL_TYPE_IEEE64 (0x02)