2 * Marvell 88SE64xx/88SE94xx pci init
4 * Copyright 2007 Red Hat, Inc.
5 * Copyright 2008 Marvell. <kewei@marvell.com>
6 * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
8 * This file is licensed under GPLv2.
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; version 2 of the
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
29 static int lldd_max_execute_num = 1;
30 module_param_named(collector, lldd_max_execute_num, int, S_IRUGO);
31 MODULE_PARM_DESC(collector, "\n"
32 "\tIf greater than one, tells the SAS Layer to run in Task Collector\n"
33 "\tMode. If 1 or 0, tells the SAS Layer to run in Direct Mode.\n"
34 "\tThe mvsas SAS LLDD supports both modes.\n"
35 "\tDefault: 1 (Direct Mode).\n");
37 int interrupt_coalescing = 0x80;
39 static struct scsi_transport_template *mvs_stt;
40 struct kmem_cache *mvs_task_list_cache;
41 static const struct mvs_chip_info mvs_chips[] = {
42 [chip_6320] = { 1, 2, 0x400, 17, 16, 6, 9, &mvs_64xx_dispatch, },
43 [chip_6440] = { 1, 4, 0x400, 17, 16, 6, 9, &mvs_64xx_dispatch, },
44 [chip_6485] = { 1, 8, 0x800, 33, 32, 6, 10, &mvs_64xx_dispatch, },
45 [chip_9180] = { 2, 4, 0x800, 17, 64, 8, 9, &mvs_94xx_dispatch, },
46 [chip_9480] = { 2, 4, 0x800, 17, 64, 8, 9, &mvs_94xx_dispatch, },
47 [chip_9445] = { 1, 4, 0x800, 17, 64, 8, 11, &mvs_94xx_dispatch, },
48 [chip_9485] = { 2, 4, 0x800, 17, 64, 8, 11, &mvs_94xx_dispatch, },
49 [chip_1300] = { 1, 4, 0x400, 17, 16, 6, 9, &mvs_64xx_dispatch, },
50 [chip_1320] = { 2, 4, 0x800, 17, 64, 8, 9, &mvs_94xx_dispatch, },
53 struct device_attribute *mvst_host_attrs[];
57 static struct scsi_host_template mvs_sht = {
58 .module = THIS_MODULE,
60 .queuecommand = sas_queuecommand,
61 .target_alloc = sas_target_alloc,
62 .slave_configure = sas_slave_configure,
63 .slave_destroy = sas_slave_destroy,
64 .scan_finished = mvs_scan_finished,
65 .scan_start = mvs_scan_start,
66 .change_queue_depth = sas_change_queue_depth,
67 .change_queue_type = sas_change_queue_type,
68 .bios_param = sas_bios_param,
72 .sg_tablesize = SG_ALL,
73 .max_sectors = SCSI_DEFAULT_MAX_SECTORS,
74 .use_clustering = ENABLE_CLUSTERING,
75 .eh_device_reset_handler = sas_eh_device_reset_handler,
76 .eh_bus_reset_handler = sas_eh_bus_reset_handler,
77 .slave_alloc = sas_slave_alloc,
78 .target_destroy = sas_target_destroy,
80 .shost_attrs = mvst_host_attrs,
83 static struct sas_domain_function_template mvs_transport_ops = {
84 .lldd_dev_found = mvs_dev_found,
85 .lldd_dev_gone = mvs_dev_gone,
86 .lldd_execute_task = mvs_queue_command,
87 .lldd_control_phy = mvs_phy_control,
89 .lldd_abort_task = mvs_abort_task,
90 .lldd_abort_task_set = mvs_abort_task_set,
91 .lldd_clear_aca = mvs_clear_aca,
92 .lldd_clear_task_set = mvs_clear_task_set,
93 .lldd_I_T_nexus_reset = mvs_I_T_nexus_reset,
94 .lldd_lu_reset = mvs_lu_reset,
95 .lldd_query_task = mvs_query_task,
96 .lldd_port_formed = mvs_port_formed,
97 .lldd_port_deformed = mvs_port_deformed,
101 static void __devinit mvs_phy_init(struct mvs_info *mvi, int phy_id)
103 struct mvs_phy *phy = &mvi->phy[phy_id];
104 struct asd_sas_phy *sas_phy = &phy->sas_phy;
108 init_timer(&phy->timer);
109 sas_phy->enabled = (phy_id < mvi->chip->n_phy) ? 1 : 0;
110 sas_phy->class = SAS;
111 sas_phy->iproto = SAS_PROTOCOL_ALL;
113 sas_phy->type = PHY_TYPE_PHYSICAL;
114 sas_phy->role = PHY_ROLE_INITIATOR;
115 sas_phy->oob_mode = OOB_NOT_CONNECTED;
116 sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN;
118 sas_phy->id = phy_id;
119 sas_phy->sas_addr = &mvi->sas_addr[0];
120 sas_phy->frame_rcvd = &phy->frame_rcvd[0];
121 sas_phy->ha = (struct sas_ha_struct *)mvi->shost->hostdata;
122 sas_phy->lldd_phy = phy;
125 static void mvs_free(struct mvs_info *mvi)
133 if (mvi->flags & MVF_FLAG_SOC)
134 slot_nr = MVS_SOC_SLOTS;
136 slot_nr = MVS_CHIP_SLOT_SZ;
139 pci_pool_destroy(mvi->dma_pool);
142 dma_free_coherent(mvi->dev,
143 sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ,
144 mvi->tx, mvi->tx_dma);
146 dma_free_coherent(mvi->dev, MVS_RX_FISL_SZ,
147 mvi->rx_fis, mvi->rx_fis_dma);
149 dma_free_coherent(mvi->dev,
150 sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1),
151 mvi->rx, mvi->rx_dma);
153 dma_free_coherent(mvi->dev,
154 sizeof(*mvi->slot) * slot_nr,
155 mvi->slot, mvi->slot_dma);
157 if (mvi->bulk_buffer)
158 dma_free_coherent(mvi->dev, TRASH_BUCKET_SIZE,
159 mvi->bulk_buffer, mvi->bulk_buffer_dma);
160 if (mvi->bulk_buffer1)
161 dma_free_coherent(mvi->dev, TRASH_BUCKET_SIZE,
162 mvi->bulk_buffer1, mvi->bulk_buffer_dma1);
164 MVS_CHIP_DISP->chip_iounmap(mvi);
166 scsi_host_put(mvi->shost);
167 list_for_each_entry(mwq, &mvi->wq_list, entry)
168 cancel_delayed_work(&mwq->work_q);
173 #ifdef CONFIG_SCSI_MVSAS_TASKLET
174 static void mvs_tasklet(unsigned long opaque)
179 struct mvs_info *mvi;
180 struct sas_ha_struct *sha = (struct sas_ha_struct *)opaque;
182 core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
183 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0];
188 stat = MVS_CHIP_DISP->isr_status(mvi, mvi->pdev->irq);
192 for (i = 0; i < core_nr; i++) {
193 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i];
194 MVS_CHIP_DISP->isr(mvi, mvi->pdev->irq, stat);
197 MVS_CHIP_DISP->interrupt_enable(mvi);
202 static irqreturn_t mvs_interrupt(int irq, void *opaque)
206 struct mvs_info *mvi;
207 struct sas_ha_struct *sha = opaque;
208 #ifndef CONFIG_SCSI_MVSAS_TASKLET
212 core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
213 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0];
217 #ifdef CONFIG_SCSI_MVSAS_TASKLET
218 MVS_CHIP_DISP->interrupt_disable(mvi);
221 stat = MVS_CHIP_DISP->isr_status(mvi, irq);
223 #ifdef CONFIG_SCSI_MVSAS_TASKLET
224 MVS_CHIP_DISP->interrupt_enable(mvi);
229 #ifdef CONFIG_SCSI_MVSAS_TASKLET
230 tasklet_schedule(&((struct mvs_prv_info *)sha->lldd_ha)->mv_tasklet);
232 for (i = 0; i < core_nr; i++) {
233 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i];
234 MVS_CHIP_DISP->isr(mvi, irq, stat);
240 static int __devinit mvs_alloc(struct mvs_info *mvi, struct Scsi_Host *shost)
245 if (mvi->flags & MVF_FLAG_SOC)
246 slot_nr = MVS_SOC_SLOTS;
248 slot_nr = MVS_CHIP_SLOT_SZ;
250 spin_lock_init(&mvi->lock);
251 for (i = 0; i < mvi->chip->n_phy; i++) {
252 mvs_phy_init(mvi, i);
253 mvi->port[i].wide_port_phymap = 0;
254 mvi->port[i].port_attached = 0;
255 INIT_LIST_HEAD(&mvi->port[i].list);
257 for (i = 0; i < MVS_MAX_DEVICES; i++) {
258 mvi->devices[i].taskfileset = MVS_ID_NOT_MAPPED;
259 mvi->devices[i].dev_type = NO_DEVICE;
260 mvi->devices[i].device_id = i;
261 mvi->devices[i].dev_status = MVS_DEV_NORMAL;
262 init_timer(&mvi->devices[i].timer);
266 * alloc and init our DMA areas
268 mvi->tx = dma_alloc_coherent(mvi->dev,
269 sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ,
270 &mvi->tx_dma, GFP_KERNEL);
273 memset(mvi->tx, 0, sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ);
274 mvi->rx_fis = dma_alloc_coherent(mvi->dev, MVS_RX_FISL_SZ,
275 &mvi->rx_fis_dma, GFP_KERNEL);
278 memset(mvi->rx_fis, 0, MVS_RX_FISL_SZ);
280 mvi->rx = dma_alloc_coherent(mvi->dev,
281 sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1),
282 &mvi->rx_dma, GFP_KERNEL);
285 memset(mvi->rx, 0, sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1));
286 mvi->rx[0] = cpu_to_le32(0xfff);
287 mvi->rx_cons = 0xfff;
289 mvi->slot = dma_alloc_coherent(mvi->dev,
290 sizeof(*mvi->slot) * slot_nr,
291 &mvi->slot_dma, GFP_KERNEL);
294 memset(mvi->slot, 0, sizeof(*mvi->slot) * slot_nr);
296 mvi->bulk_buffer = dma_alloc_coherent(mvi->dev,
298 &mvi->bulk_buffer_dma, GFP_KERNEL);
299 if (!mvi->bulk_buffer)
302 mvi->bulk_buffer1 = dma_alloc_coherent(mvi->dev,
304 &mvi->bulk_buffer_dma1, GFP_KERNEL);
305 if (!mvi->bulk_buffer1)
308 sprintf(pool_name, "%s%d", "mvs_dma_pool", mvi->id);
309 mvi->dma_pool = pci_pool_create(pool_name, mvi->pdev, MVS_SLOT_BUF_SZ, 16, 0);
310 if (!mvi->dma_pool) {
311 printk(KERN_DEBUG "failed to create dma pool %s.\n", pool_name);
314 mvi->tags_num = slot_nr;
316 /* Initialize tags */
324 int mvs_ioremap(struct mvs_info *mvi, int bar, int bar_ex)
326 unsigned long res_start, res_len, res_flag, res_flag_ex = 0;
327 struct pci_dev *pdev = mvi->pdev;
330 * ioremap main and peripheral registers
332 res_start = pci_resource_start(pdev, bar_ex);
333 res_len = pci_resource_len(pdev, bar_ex);
334 if (!res_start || !res_len)
337 res_flag_ex = pci_resource_flags(pdev, bar_ex);
338 if (res_flag_ex & IORESOURCE_MEM) {
339 if (res_flag_ex & IORESOURCE_CACHEABLE)
340 mvi->regs_ex = ioremap(res_start, res_len);
342 mvi->regs_ex = ioremap_nocache(res_start,
345 mvi->regs_ex = (void *)res_start;
350 res_start = pci_resource_start(pdev, bar);
351 res_len = pci_resource_len(pdev, bar);
352 if (!res_start || !res_len)
355 res_flag = pci_resource_flags(pdev, bar);
356 if (res_flag & IORESOURCE_CACHEABLE)
357 mvi->regs = ioremap(res_start, res_len);
359 mvi->regs = ioremap_nocache(res_start, res_len);
362 if (mvi->regs_ex && (res_flag_ex & IORESOURCE_MEM))
363 iounmap(mvi->regs_ex);
373 void mvs_iounmap(void __iomem *regs)
378 static struct mvs_info *__devinit mvs_pci_alloc(struct pci_dev *pdev,
379 const struct pci_device_id *ent,
380 struct Scsi_Host *shost, unsigned int id)
382 struct mvs_info *mvi = NULL;
383 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
385 mvi = kzalloc(sizeof(*mvi) +
386 (1L << mvs_chips[ent->driver_data].slot_width) *
387 sizeof(struct mvs_slot_info), GFP_KERNEL);
392 mvi->dev = &pdev->dev;
393 mvi->chip_id = ent->driver_data;
394 mvi->chip = &mvs_chips[mvi->chip_id];
395 INIT_LIST_HEAD(&mvi->wq_list);
397 ((struct mvs_prv_info *)sha->lldd_ha)->mvi[id] = mvi;
398 ((struct mvs_prv_info *)sha->lldd_ha)->n_phy = mvi->chip->n_phy;
404 mvi->tags = kzalloc(MVS_CHIP_SLOT_SZ>>3, GFP_KERNEL);
408 if (MVS_CHIP_DISP->chip_ioremap(mvi))
410 if (!mvs_alloc(mvi, shost))
417 static int pci_go_64(struct pci_dev *pdev)
421 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
422 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
424 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
426 dev_printk(KERN_ERR, &pdev->dev,
427 "64-bit DMA enable failed\n");
432 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
434 dev_printk(KERN_ERR, &pdev->dev,
435 "32-bit DMA enable failed\n");
438 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
440 dev_printk(KERN_ERR, &pdev->dev,
441 "32-bit consistent DMA enable failed\n");
449 static int __devinit mvs_prep_sas_ha_init(struct Scsi_Host *shost,
450 const struct mvs_chip_info *chip_info)
452 int phy_nr, port_nr; unsigned short core_nr;
453 struct asd_sas_phy **arr_phy;
454 struct asd_sas_port **arr_port;
455 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
457 core_nr = chip_info->n_host;
458 phy_nr = core_nr * chip_info->n_phy;
461 memset(sha, 0x00, sizeof(struct sas_ha_struct));
462 arr_phy = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL);
463 arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL);
464 if (!arr_phy || !arr_port)
467 sha->sas_phy = arr_phy;
468 sha->sas_port = arr_port;
469 sha->core.shost = shost;
471 sha->lldd_ha = kzalloc(sizeof(struct mvs_prv_info), GFP_KERNEL);
475 ((struct mvs_prv_info *)sha->lldd_ha)->n_host = core_nr;
477 shost->transportt = mvs_stt;
478 shost->max_id = MVS_MAX_DEVICES;
480 shost->max_channel = 1;
481 shost->max_cmd_len = 16;
491 static void __devinit mvs_post_sas_ha_init(struct Scsi_Host *shost,
492 const struct mvs_chip_info *chip_info)
494 int can_queue, i = 0, j = 0;
495 struct mvs_info *mvi = NULL;
496 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
497 unsigned short nr_core = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
499 for (j = 0; j < nr_core; j++) {
500 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[j];
501 for (i = 0; i < chip_info->n_phy; i++) {
502 sha->sas_phy[j * chip_info->n_phy + i] =
503 &mvi->phy[i].sas_phy;
504 sha->sas_port[j * chip_info->n_phy + i] =
505 &mvi->port[i].sas_port;
509 sha->sas_ha_name = DRV_NAME;
511 sha->lldd_module = THIS_MODULE;
512 sha->sas_addr = &mvi->sas_addr[0];
514 sha->num_phys = nr_core * chip_info->n_phy;
516 sha->lldd_max_execute_num = lldd_max_execute_num;
518 if (mvi->flags & MVF_FLAG_SOC)
519 can_queue = MVS_SOC_CAN_QUEUE;
521 can_queue = MVS_CHIP_SLOT_SZ;
523 sha->lldd_queue_size = can_queue;
524 shost->sg_tablesize = min_t(u16, SG_ALL, MVS_MAX_SG);
525 shost->can_queue = can_queue;
526 mvi->shost->cmd_per_lun = MVS_QUEUE_SIZE;
527 sha->core.shost = mvi->shost;
530 static void mvs_init_sas_add(struct mvs_info *mvi)
533 for (i = 0; i < mvi->chip->n_phy; i++) {
534 mvi->phy[i].dev_sas_addr = 0x5005043011ab0000ULL;
535 mvi->phy[i].dev_sas_addr =
536 cpu_to_be64((u64)(*(u64 *)&mvi->phy[i].dev_sas_addr));
539 memcpy(mvi->sas_addr, &mvi->phy[0].dev_sas_addr, SAS_ADDR_SIZE);
542 static int __devinit mvs_pci_init(struct pci_dev *pdev,
543 const struct pci_device_id *ent)
545 unsigned int rc, nhost = 0;
546 struct mvs_info *mvi;
547 struct mvs_prv_info *mpi;
548 irq_handler_t irq_handler = mvs_interrupt;
549 struct Scsi_Host *shost = NULL;
550 const struct mvs_chip_info *chip;
552 dev_printk(KERN_INFO, &pdev->dev,
553 "mvsas: driver version %s\n", DRV_VERSION);
554 rc = pci_enable_device(pdev);
558 pci_set_master(pdev);
560 rc = pci_request_regions(pdev, DRV_NAME);
562 goto err_out_disable;
564 rc = pci_go_64(pdev);
566 goto err_out_regions;
568 shost = scsi_host_alloc(&mvs_sht, sizeof(void *));
571 goto err_out_regions;
574 chip = &mvs_chips[ent->driver_data];
575 SHOST_TO_SAS_HA(shost) =
576 kcalloc(1, sizeof(struct sas_ha_struct), GFP_KERNEL);
577 if (!SHOST_TO_SAS_HA(shost)) {
580 goto err_out_regions;
583 rc = mvs_prep_sas_ha_init(shost, chip);
587 goto err_out_regions;
590 pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost));
593 mvi = mvs_pci_alloc(pdev, ent, shost, nhost);
596 goto err_out_regions;
599 memset(&mvi->hba_info_param, 0xFF,
600 sizeof(struct hba_info_page));
602 mvs_init_sas_add(mvi);
604 mvi->instance = nhost;
605 rc = MVS_CHIP_DISP->chip_init(mvi);
608 goto err_out_regions;
611 } while (nhost < chip->n_host);
612 mpi = (struct mvs_prv_info *)(SHOST_TO_SAS_HA(shost)->lldd_ha);
613 #ifdef CONFIG_SCSI_MVSAS_TASKLET
614 tasklet_init(&(mpi->mv_tasklet), mvs_tasklet,
615 (unsigned long)SHOST_TO_SAS_HA(shost));
618 mvs_post_sas_ha_init(shost, chip);
620 rc = scsi_add_host(shost, &pdev->dev);
624 rc = sas_register_ha(SHOST_TO_SAS_HA(shost));
627 rc = request_irq(pdev->irq, irq_handler, IRQF_SHARED,
628 DRV_NAME, SHOST_TO_SAS_HA(shost));
632 MVS_CHIP_DISP->interrupt_enable(mvi);
634 scsi_scan_host(mvi->shost);
639 sas_unregister_ha(SHOST_TO_SAS_HA(shost));
641 scsi_remove_host(mvi->shost);
643 pci_release_regions(pdev);
645 pci_disable_device(pdev);
650 static void __devexit mvs_pci_remove(struct pci_dev *pdev)
652 unsigned short core_nr, i = 0;
653 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
654 struct mvs_info *mvi = NULL;
656 core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
657 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0];
659 #ifdef CONFIG_SCSI_MVSAS_TASKLET
660 tasklet_kill(&((struct mvs_prv_info *)sha->lldd_ha)->mv_tasklet);
663 pci_set_drvdata(pdev, NULL);
664 sas_unregister_ha(sha);
665 sas_remove_host(mvi->shost);
666 scsi_remove_host(mvi->shost);
668 MVS_CHIP_DISP->interrupt_disable(mvi);
669 free_irq(mvi->pdev->irq, sha);
670 for (i = 0; i < core_nr; i++) {
671 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i];
675 kfree(sha->sas_port);
677 pci_release_regions(pdev);
678 pci_disable_device(pdev);
682 static struct pci_device_id __devinitdata mvs_pci_table[] = {
683 { PCI_VDEVICE(MARVELL, 0x6320), chip_6320 },
684 { PCI_VDEVICE(MARVELL, 0x6340), chip_6440 },
686 .vendor = PCI_VENDOR_ID_MARVELL,
688 .subvendor = PCI_ANY_ID,
692 .driver_data = chip_6485,
694 { PCI_VDEVICE(MARVELL, 0x6440), chip_6440 },
695 { PCI_VDEVICE(MARVELL, 0x6485), chip_6485 },
696 { PCI_VDEVICE(MARVELL, 0x9480), chip_9480 },
697 { PCI_VDEVICE(MARVELL, 0x9180), chip_9180 },
698 { PCI_VDEVICE(ARECA, PCI_DEVICE_ID_ARECA_1300), chip_1300 },
699 { PCI_VDEVICE(ARECA, PCI_DEVICE_ID_ARECA_1320), chip_1320 },
700 { PCI_VDEVICE(ADAPTEC2, 0x0450), chip_6440 },
701 { PCI_VDEVICE(TTI, 0x2710), chip_9480 },
702 { PCI_VDEVICE(TTI, 0x2720), chip_9480 },
703 { PCI_VDEVICE(TTI, 0x2721), chip_9480 },
704 { PCI_VDEVICE(TTI, 0x2722), chip_9480 },
705 { PCI_VDEVICE(TTI, 0x2740), chip_9480 },
706 { PCI_VDEVICE(TTI, 0x2744), chip_9480 },
707 { PCI_VDEVICE(TTI, 0x2760), chip_9480 },
711 .subvendor = PCI_ANY_ID,
715 .driver_data = chip_9480,
720 .subvendor = PCI_ANY_ID,
724 .driver_data = chip_9445,
729 .subvendor = PCI_ANY_ID,
733 .driver_data = chip_9485,
736 { } /* terminate list */
739 static struct pci_driver mvs_pci_driver = {
741 .id_table = mvs_pci_table,
742 .probe = mvs_pci_init,
743 .remove = __devexit_p(mvs_pci_remove),
747 mvs_show_driver_version(struct device *cdev,
748 struct device_attribute *attr, char *buffer)
750 return snprintf(buffer, PAGE_SIZE, "%s\n", DRV_VERSION);
753 static DEVICE_ATTR(driver_version,
755 mvs_show_driver_version,
759 mvs_store_interrupt_coalescing(struct device *cdev,
760 struct device_attribute *attr,
761 const char *buffer, size_t size)
764 struct mvs_info *mvi = NULL;
765 struct Scsi_Host *shost = class_to_shost(cdev);
766 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
771 if (sscanf(buffer, "%d", &val) != 1)
774 if (val >= 0x10000) {
775 mv_dprintk("interrupt coalescing timer %d us is"
777 return strlen(buffer);
780 interrupt_coalescing = val;
782 core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
783 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0];
788 for (i = 0; i < core_nr; i++) {
789 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i];
790 if (MVS_CHIP_DISP->tune_interrupt)
791 MVS_CHIP_DISP->tune_interrupt(mvi,
792 interrupt_coalescing);
794 mv_dprintk("set interrupt coalescing time to %d us\n",
795 interrupt_coalescing);
796 return strlen(buffer);
799 static ssize_t mvs_show_interrupt_coalescing(struct device *cdev,
800 struct device_attribute *attr, char *buffer)
802 return snprintf(buffer, PAGE_SIZE, "%d\n", interrupt_coalescing);
805 static DEVICE_ATTR(interrupt_coalescing,
807 mvs_show_interrupt_coalescing,
808 mvs_store_interrupt_coalescing);
811 struct task_struct *mvs_th;
812 static int __init mvs_init(void)
815 mvs_stt = sas_domain_attach_transport(&mvs_transport_ops);
819 mvs_task_list_cache = kmem_cache_create("mvs_task_list", sizeof(struct mvs_task_list),
820 0, SLAB_HWCACHE_ALIGN, NULL);
821 if (!mvs_task_list_cache) {
823 mv_printk("%s: mvs_task_list_cache alloc failed! \n", __func__);
827 rc = pci_register_driver(&mvs_pci_driver);
835 sas_release_transport(mvs_stt);
839 static void __exit mvs_exit(void)
841 pci_unregister_driver(&mvs_pci_driver);
842 sas_release_transport(mvs_stt);
843 kmem_cache_destroy(mvs_task_list_cache);
846 struct device_attribute *mvst_host_attrs[] = {
847 &dev_attr_driver_version,
848 &dev_attr_interrupt_coalescing,
852 module_init(mvs_init);
853 module_exit(mvs_exit);
855 MODULE_AUTHOR("Jeff Garzik <jgarzik@pobox.com>");
856 MODULE_DESCRIPTION("Marvell 88SE6440 SAS/SATA controller driver");
857 MODULE_VERSION(DRV_VERSION);
858 MODULE_LICENSE("GPL");
860 MODULE_DEVICE_TABLE(pci, mvs_pci_table);