drivers/scsi/pm8001/pm8001_hwi.c

   1 /*
   2  * PMC-Sierra SPC 8001 SAS/SATA based host adapters driver
   3  *
   4  * Copyright (c) 2008-2009 USI Co., Ltd.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions, and the following disclaimer,
  12  *    without modification.
  13  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  14  *    substantially similar to the "NO WARRANTY" disclaimer below
  15  *    ("Disclaimer") and any redistribution must be conditioned upon
  16  *    including a substantially similar Disclaimer requirement for further
  17  *    binary redistribution.
  18  * 3. Neither the names of the above-listed copyright holders nor the names
  19  *    of any contributors may be used to endorse or promote products derived
  20  *    from this software without specific prior written permission.
  21  *
  22  * Alternatively, this software may be distributed under the terms of the
  23  * GNU General Public License ("GPL") version 2 as published by the Free
  24  * Software Foundation.
  25  *
  26  * NO WARRANTY
  27  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
  30  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  31  * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  32  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  33  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  34  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  35  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  36  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  37  * POSSIBILITY OF SUCH DAMAGES.
  38  *
  39  */
  40  #include <linux/slab.h>
  41  #include "pm8001_sas.h"
  42  #include "pm8001_hwi.h"
  43  #include "pm8001_chips.h"
  44  #include "pm8001_ctl.h"
  45
  46 /**
  47  * read_main_config_table - read the configure table and save it.
  48  * @pm8001_ha: our hba card information
  49  */
  50 static void read_main_config_table(struct pm8001_hba_info *pm8001_ha)
  51 {
  52         void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
  53         pm8001_ha->main_cfg_tbl.pm8001_tbl.signature    =
  54                                 pm8001_mr32(address, 0x00);
  55         pm8001_ha->main_cfg_tbl.pm8001_tbl.interface_rev =
  56                                 pm8001_mr32(address, 0x04);
  57         pm8001_ha->main_cfg_tbl.pm8001_tbl.firmware_rev =
  58                                 pm8001_mr32(address, 0x08);
  59         pm8001_ha->main_cfg_tbl.pm8001_tbl.max_out_io   =
  60                                 pm8001_mr32(address, 0x0C);
  61         pm8001_ha->main_cfg_tbl.pm8001_tbl.max_sgl      =
  62                                 pm8001_mr32(address, 0x10);
  63         pm8001_ha->main_cfg_tbl.pm8001_tbl.ctrl_cap_flag =
  64                                 pm8001_mr32(address, 0x14);
  65         pm8001_ha->main_cfg_tbl.pm8001_tbl.gst_offset   =
  66                                 pm8001_mr32(address, 0x18);
  67         pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_queue_offset =
  68                 pm8001_mr32(address, MAIN_IBQ_OFFSET);
  69         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_queue_offset =
  70                 pm8001_mr32(address, MAIN_OBQ_OFFSET);
  71         pm8001_ha->main_cfg_tbl.pm8001_tbl.hda_mode_flag        =
  72                 pm8001_mr32(address, MAIN_HDA_FLAGS_OFFSET);
  73
  74         /* read analog Setting offset from the configuration table */
  75         pm8001_ha->main_cfg_tbl.pm8001_tbl.anolog_setup_table_offset =
  76                 pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET);
  77
  78         /* read Error Dump Offset and Length */
  79         pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_offset0 =
  80                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET);
  81         pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_length0 =
  82                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH);
  83         pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_offset1 =
  84                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET);
  85         pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_length1 =
  86                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH);
  87 }
  88
  89 /**
  90  * read_general_status_table - read the general status table and save it.
  91  * @pm8001_ha: our hba card information
  92  */
  93 static void read_general_status_table(struct pm8001_hba_info *pm8001_ha)
  94 {
  95         void __iomem *address = pm8001_ha->general_stat_tbl_addr;
  96         pm8001_ha->gs_tbl.pm8001_tbl.gst_len_mpistate   =
  97                                 pm8001_mr32(address, 0x00);
  98         pm8001_ha->gs_tbl.pm8001_tbl.iq_freeze_state0   =
  99                                 pm8001_mr32(address, 0x04);
 100         pm8001_ha->gs_tbl.pm8001_tbl.iq_freeze_state1   =
 101                                 pm8001_mr32(address, 0x08);
 102         pm8001_ha->gs_tbl.pm8001_tbl.msgu_tcnt          =
 103                                 pm8001_mr32(address, 0x0C);
 104         pm8001_ha->gs_tbl.pm8001_tbl.iop_tcnt           =
 105                                 pm8001_mr32(address, 0x10);
 106         pm8001_ha->gs_tbl.pm8001_tbl.rsvd               =
 107                                 pm8001_mr32(address, 0x14);
 108         pm8001_ha->gs_tbl.pm8001_tbl.phy_state[0]       =
 109                                 pm8001_mr32(address, 0x18);
 110         pm8001_ha->gs_tbl.pm8001_tbl.phy_state[1]       =
 111                                 pm8001_mr32(address, 0x1C);
 112         pm8001_ha->gs_tbl.pm8001_tbl.phy_state[2]       =
 113                                 pm8001_mr32(address, 0x20);
 114         pm8001_ha->gs_tbl.pm8001_tbl.phy_state[3]       =
 115                                 pm8001_mr32(address, 0x24);
 116         pm8001_ha->gs_tbl.pm8001_tbl.phy_state[4]       =
 117                                 pm8001_mr32(address, 0x28);
 118         pm8001_ha->gs_tbl.pm8001_tbl.phy_state[5]       =
 119                                 pm8001_mr32(address, 0x2C);
 120         pm8001_ha->gs_tbl.pm8001_tbl.phy_state[6]       =
 121                                 pm8001_mr32(address, 0x30);
 122         pm8001_ha->gs_tbl.pm8001_tbl.phy_state[7]       =
 123                                 pm8001_mr32(address, 0x34);
 124         pm8001_ha->gs_tbl.pm8001_tbl.gpio_input_val     =
 125                                 pm8001_mr32(address, 0x38);
 126         pm8001_ha->gs_tbl.pm8001_tbl.rsvd1[0]           =
 127                                 pm8001_mr32(address, 0x3C);
 128         pm8001_ha->gs_tbl.pm8001_tbl.rsvd1[1]           =
 129                                 pm8001_mr32(address, 0x40);
 130         pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[0]        =
 131                                 pm8001_mr32(address, 0x44);
 132         pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[1]        =
 133                                 pm8001_mr32(address, 0x48);
 134         pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[2]        =
 135                                 pm8001_mr32(address, 0x4C);
 136         pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[3]        =
 137                                 pm8001_mr32(address, 0x50);
 138         pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[4]        =
 139                                 pm8001_mr32(address, 0x54);
 140         pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[5]        =
 141                                 pm8001_mr32(address, 0x58);
 142         pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[6]        =
 143                                 pm8001_mr32(address, 0x5C);
 144         pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[7]        =
 145                                 pm8001_mr32(address, 0x60);
 146 }
 147
 148 /**
 149  * read_inbnd_queue_table - read the inbound queue table and save it.
 150  * @pm8001_ha: our hba card information
 151  */
 152 static void read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
 153 {
 154         int i;
 155         void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
 156         for (i = 0; i < PM8001_MAX_INB_NUM; i++) {
 157                 u32 offset = i * 0x20;
 158                 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
 159                       get_pci_bar_index(pm8001_mr32(address, (offset + 0x14)));
 160                 pm8001_ha->inbnd_q_tbl[i].pi_offset =
 161                         pm8001_mr32(address, (offset + 0x18));
 162         }
 163 }
 164
 165 /**
 166  * read_outbnd_queue_table - read the outbound queue table and save it.
 167  * @pm8001_ha: our hba card information
 168  */
 169 static void read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
 170 {
 171         int i;
 172         void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
 173         for (i = 0; i < PM8001_MAX_OUTB_NUM; i++) {
 174                 u32 offset = i * 0x24;
 175                 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
 176                       get_pci_bar_index(pm8001_mr32(address, (offset + 0x14)));
 177                 pm8001_ha->outbnd_q_tbl[i].ci_offset =
 178                         pm8001_mr32(address, (offset + 0x18));
 179         }
 180 }
 181
 182 /**
 183  * init_default_table_values - init the default table.
 184  * @pm8001_ha: our hba card information
 185  */
 186 static void init_default_table_values(struct pm8001_hba_info *pm8001_ha)
 187 {
 188         int i;
 189         u32 offsetib, offsetob;
 190         void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr;
 191         void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr;
 192
 193         pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_q_nppd_hppd          = 0;
 194         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid0_3     = 0;
 195         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid4_7     = 0;
 196         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid0_3    = 0;
 197         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid4_7    = 0;
 198         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ITNexus_event_pid0_3 =
 199                                                                          0;
 200         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ITNexus_event_pid4_7 =
 201                                                                          0;
 202         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ssp_event_pid0_3 = 0;
 203         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ssp_event_pid4_7 = 0;
 204         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_smp_event_pid0_3 = 0;
 205         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_smp_event_pid4_7 = 0;
 206
 207         pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_event_log_addr         =
 208                 pm8001_ha->memoryMap.region[AAP1].phys_addr_hi;
 209         pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_event_log_addr         =
 210                 pm8001_ha->memoryMap.region[AAP1].phys_addr_lo;
 211         pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_size               =
 212                 PM8001_EVENT_LOG_SIZE;
 213         pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_option             = 0x01;
 214         pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_iop_event_log_addr     =
 215                 pm8001_ha->memoryMap.region[IOP].phys_addr_hi;
 216         pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_iop_event_log_addr     =
 217                 pm8001_ha->memoryMap.region[IOP].phys_addr_lo;
 218         pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_size           =
 219                 PM8001_EVENT_LOG_SIZE;
 220         pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_option         = 0x01;
 221         pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_interrupt          = 0x01;
 222         for (i = 0; i < PM8001_MAX_INB_NUM; i++) {
 223                 pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt  =
 224                         PM8001_MPI_QUEUE | (64 << 16) | (0x00<<30);
 225                 pm8001_ha->inbnd_q_tbl[i].upper_base_addr       =
 226                         pm8001_ha->memoryMap.region[IB + i].phys_addr_hi;
 227                 pm8001_ha->inbnd_q_tbl[i].lower_base_addr       =
 228                 pm8001_ha->memoryMap.region[IB + i].phys_addr_lo;
 229                 pm8001_ha->inbnd_q_tbl[i].base_virt             =
 230                         (u8 *)pm8001_ha->memoryMap.region[IB + i].virt_ptr;
 231                 pm8001_ha->inbnd_q_tbl[i].total_length          =
 232                         pm8001_ha->memoryMap.region[IB + i].total_len;
 233                 pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr    =
 234                         pm8001_ha->memoryMap.region[CI + i].phys_addr_hi;
 235                 pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr    =
 236                         pm8001_ha->memoryMap.region[CI + i].phys_addr_lo;
 237                 pm8001_ha->inbnd_q_tbl[i].ci_virt               =
 238                         pm8001_ha->memoryMap.region[CI + i].virt_ptr;
 239                 offsetib = i * 0x20;
 240                 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar            =
 241                         get_pci_bar_index(pm8001_mr32(addressib,
 242                                 (offsetib + 0x14)));
 243                 pm8001_ha->inbnd_q_tbl[i].pi_offset             =
 244                         pm8001_mr32(addressib, (offsetib + 0x18));
 245                 pm8001_ha->inbnd_q_tbl[i].producer_idx          = 0;
 246                 pm8001_ha->inbnd_q_tbl[i].consumer_index        = 0;
 247         }
 248         for (i = 0; i < PM8001_MAX_OUTB_NUM; i++) {
 249                 pm8001_ha->outbnd_q_tbl[i].element_size_cnt     =
 250                         PM8001_MPI_QUEUE | (64 << 16) | (0x01<<30);
 251                 pm8001_ha->outbnd_q_tbl[i].upper_base_addr      =
 252                         pm8001_ha->memoryMap.region[OB + i].phys_addr_hi;
 253                 pm8001_ha->outbnd_q_tbl[i].lower_base_addr      =
 254                         pm8001_ha->memoryMap.region[OB + i].phys_addr_lo;
 255                 pm8001_ha->outbnd_q_tbl[i].base_virt            =
 256                         (u8 *)pm8001_ha->memoryMap.region[OB + i].virt_ptr;
 257                 pm8001_ha->outbnd_q_tbl[i].total_length         =
 258                         pm8001_ha->memoryMap.region[OB + i].total_len;
 259                 pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr   =
 260                         pm8001_ha->memoryMap.region[PI + i].phys_addr_hi;
 261                 pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr   =
 262                         pm8001_ha->memoryMap.region[PI + i].phys_addr_lo;
 263                 pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay       =
 264                         0 | (10 << 16) | (i << 24);
 265                 pm8001_ha->outbnd_q_tbl[i].pi_virt              =
 266                         pm8001_ha->memoryMap.region[PI + i].virt_ptr;
 267                 offsetob = i * 0x24;
 268                 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar           =
 269                         get_pci_bar_index(pm8001_mr32(addressob,
 270                         offsetob + 0x14));
 271                 pm8001_ha->outbnd_q_tbl[i].ci_offset            =
 272                         pm8001_mr32(addressob, (offsetob + 0x18));
 273                 pm8001_ha->outbnd_q_tbl[i].consumer_idx         = 0;
 274                 pm8001_ha->outbnd_q_tbl[i].producer_index       = 0;
 275         }
 276 }
 277
 278 /**
 279  * update_main_config_table - update the main default table to the HBA.
 280  * @pm8001_ha: our hba card information
 281  */
 282 static void update_main_config_table(struct pm8001_hba_info *pm8001_ha)
 283 {
 284         void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
 285         pm8001_mw32(address, 0x24,
 286                 pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_q_nppd_hppd);
 287         pm8001_mw32(address, 0x28,
 288                 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid0_3);
 289         pm8001_mw32(address, 0x2C,
 290                 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid4_7);
 291         pm8001_mw32(address, 0x30,
 292                 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid0_3);
 293         pm8001_mw32(address, 0x34,
 294                 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid4_7);
 295         pm8001_mw32(address, 0x38,
 296                 pm8001_ha->main_cfg_tbl.pm8001_tbl.
 297                                         outbound_tgt_ITNexus_event_pid0_3);
 298         pm8001_mw32(address, 0x3C,
 299                 pm8001_ha->main_cfg_tbl.pm8001_tbl.
 300                                         outbound_tgt_ITNexus_event_pid4_7);
 301         pm8001_mw32(address, 0x40,
 302                 pm8001_ha->main_cfg_tbl.pm8001_tbl.
 303                                         outbound_tgt_ssp_event_pid0_3);
 304         pm8001_mw32(address, 0x44,
 305                 pm8001_ha->main_cfg_tbl.pm8001_tbl.
 306                                         outbound_tgt_ssp_event_pid4_7);
 307         pm8001_mw32(address, 0x48,
 308                 pm8001_ha->main_cfg_tbl.pm8001_tbl.
 309                                         outbound_tgt_smp_event_pid0_3);
 310         pm8001_mw32(address, 0x4C,
 311                 pm8001_ha->main_cfg_tbl.pm8001_tbl.
 312                                         outbound_tgt_smp_event_pid4_7);
 313         pm8001_mw32(address, 0x50,
 314                 pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_event_log_addr);
 315         pm8001_mw32(address, 0x54,
 316                 pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_event_log_addr);
 317         pm8001_mw32(address, 0x58,
 318                 pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_size);
 319         pm8001_mw32(address, 0x5C,
 320                 pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_option);
 321         pm8001_mw32(address, 0x60,
 322                 pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_iop_event_log_addr);
 323         pm8001_mw32(address, 0x64,
 324                 pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_iop_event_log_addr);
 325         pm8001_mw32(address, 0x68,
 326                 pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_size);
 327         pm8001_mw32(address, 0x6C,
 328                 pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_option);
 329         pm8001_mw32(address, 0x70,
 330                 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_interrupt);
 331 }
 332
 333 /**
 334  * update_inbnd_queue_table - update the inbound queue table to the HBA.
 335  * @pm8001_ha: our hba card information
 336  */
 337 static void update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
 338                                      int number)
 339 {
 340         void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
 341         u16 offset = number * 0x20;
 342         pm8001_mw32(address, offset + 0x00,
 343                 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt);
 344         pm8001_mw32(address, offset + 0x04,
 345                 pm8001_ha->inbnd_q_tbl[number].upper_base_addr);
 346         pm8001_mw32(address, offset + 0x08,
 347                 pm8001_ha->inbnd_q_tbl[number].lower_base_addr);
 348         pm8001_mw32(address, offset + 0x0C,
 349                 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr);
 350         pm8001_mw32(address, offset + 0x10,
 351                 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr);
 352 }
 353
 354 /**
 355  * update_outbnd_queue_table - update the outbound queue table to the HBA.
 356  * @pm8001_ha: our hba card information
 357  */
 358 static void update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
 359                                       int number)
 360 {
 361         void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
 362         u16 offset = number * 0x24;
 363         pm8001_mw32(address, offset + 0x00,
 364                 pm8001_ha->outbnd_q_tbl[number].element_size_cnt);
 365         pm8001_mw32(address, offset + 0x04,
 366                 pm8001_ha->outbnd_q_tbl[number].upper_base_addr);
 367         pm8001_mw32(address, offset + 0x08,
 368                 pm8001_ha->outbnd_q_tbl[number].lower_base_addr);
 369         pm8001_mw32(address, offset + 0x0C,
 370                 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr);
 371         pm8001_mw32(address, offset + 0x10,
 372                 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr);
 373         pm8001_mw32(address, offset + 0x1C,
 374                 pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay);
 375 }
 376
 377 /**
 378  * pm8001_bar4_shift - function is called to shift BAR base address
 379  * @pm8001_ha : our hba card infomation
 380  * @shiftValue : shifting value in memory bar.
 381  */
 382 int pm8001_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue)
 383 {
 384         u32 regVal;
 385         unsigned long start;
 386
 387         /* program the inbound AXI translation Lower Address */
 388         pm8001_cw32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW, shiftValue);
 389
 390         /* confirm the setting is written */
 391         start = jiffies + HZ; /* 1 sec */
 392         do {
 393                 regVal = pm8001_cr32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW);
 394         } while ((regVal != shiftValue) && time_before(jiffies, start));
 395
 396         if (regVal != shiftValue) {
 397                 PM8001_INIT_DBG(pm8001_ha,
 398                         pm8001_printk("TIMEOUT:SPC_IBW_AXI_TRANSLATION_LOW"
 399                         " = 0x%x\n", regVal));
 400                 return -1;
 401         }
 402         return 0;
 403 }
 404
 405 /**
 406  * mpi_set_phys_g3_with_ssc
 407  * @pm8001_ha: our hba card information
 408  * @SSCbit: set SSCbit to 0 to disable all phys ssc; 1 to enable all phys ssc.
 409  */
 410 static void mpi_set_phys_g3_with_ssc(struct pm8001_hba_info *pm8001_ha,
 411                                      u32 SSCbit)
 412 {
 413         u32 value, offset, i;
 414         unsigned long flags;
 415
 416 #define SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR 0x00030000
 417 #define SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR 0x00040000
 418 #define SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET 0x1074
 419 #define SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET 0x1074
 420 #define PHY_G3_WITHOUT_SSC_BIT_SHIFT 12
 421 #define PHY_G3_WITH_SSC_BIT_SHIFT 13
 422 #define SNW3_PHY_CAPABILITIES_PARITY 31
 423
 424    /*
 425     * Using shifted destination address 0x3_0000:0x1074 + 0x4000*N (N=0:3)
 426     * Using shifted destination address 0x4_0000:0x1074 + 0x4000*(N-4) (N=4:7)
 427     */
 428         spin_lock_irqsave(&pm8001_ha->lock, flags);
 429         if (-1 == pm8001_bar4_shift(pm8001_ha,
 430                                 SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR)) {
 431                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 432                 return;
 433         }
 434
 435         for (i = 0; i < 4; i++) {
 436                 offset = SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET + 0x4000 * i;
 437                 pm8001_cw32(pm8001_ha, 2, offset, 0x80001501);
 438         }
 439         /* shift membase 3 for SAS2_SETTINGS_LOCAL_PHY 4 - 7 */
 440         if (-1 == pm8001_bar4_shift(pm8001_ha,
 441                                 SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR)) {
 442                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 443                 return;
 444         }
 445         for (i = 4; i < 8; i++) {
 446                 offset = SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET + 0x4000 * (i-4);
 447                 pm8001_cw32(pm8001_ha, 2, offset, 0x80001501);
 448         }
 449         /*************************************************************
 450         Change the SSC upspreading value to 0x0 so that upspreading is disabled.
 451         Device MABC SMOD0 Controls
 452         Address: (via MEMBASE-III):
 453         Using shifted destination address 0x0_0000: with Offset 0xD8
 454
 455         31:28 R/W Reserved Do not change
 456         27:24 R/W SAS_SMOD_SPRDUP 0000
 457         23:20 R/W SAS_SMOD_SPRDDN 0000
 458         19:0  R/W  Reserved Do not change
 459         Upon power-up this register will read as 0x8990c016,
 460         and I would like you to change the SAS_SMOD_SPRDUP bits to 0b0000
 461         so that the written value will be 0x8090c016.
 462         This will ensure only down-spreading SSC is enabled on the SPC.
 463         *************************************************************/
 464         value = pm8001_cr32(pm8001_ha, 2, 0xd8);
 465         pm8001_cw32(pm8001_ha, 2, 0xd8, 0x8000C016);
 466
 467         /*set the shifted destination address to 0x0 to avoid error operation */
 468         pm8001_bar4_shift(pm8001_ha, 0x0);
 469         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 470         return;
 471 }
 472
 473 /**
 474  * mpi_set_open_retry_interval_reg
 475  * @pm8001_ha: our hba card information
 476  * @interval - interval time for each OPEN_REJECT (RETRY). The units are in 1us.
 477  */
 478 static void mpi_set_open_retry_interval_reg(struct pm8001_hba_info *pm8001_ha,
 479                                             u32 interval)
 480 {
 481         u32 offset;
 482         u32 value;
 483         u32 i;
 484         unsigned long flags;
 485
 486 #define OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR 0x00030000
 487 #define OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR 0x00040000
 488 #define OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET 0x30B4
 489 #define OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET 0x30B4
 490 #define OPEN_RETRY_INTERVAL_REG_MASK 0x0000FFFF
 491
 492         value = interval & OPEN_RETRY_INTERVAL_REG_MASK;
 493         spin_lock_irqsave(&pm8001_ha->lock, flags);
 494         /* shift bar and set the OPEN_REJECT(RETRY) interval time of PHY 0 -3.*/
 495         if (-1 == pm8001_bar4_shift(pm8001_ha,
 496                              OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR)) {
 497                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 498                 return;
 499         }
 500         for (i = 0; i < 4; i++) {
 501                 offset = OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET + 0x4000 * i;
 502                 pm8001_cw32(pm8001_ha, 2, offset, value);
 503         }
 504
 505         if (-1 == pm8001_bar4_shift(pm8001_ha,
 506                              OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR)) {
 507                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 508                 return;
 509         }
 510         for (i = 4; i < 8; i++) {
 511                 offset = OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET + 0x4000 * (i-4);
 512                 pm8001_cw32(pm8001_ha, 2, offset, value);
 513         }
 514         /*set the shifted destination address to 0x0 to avoid error operation */
 515         pm8001_bar4_shift(pm8001_ha, 0x0);
 516         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 517         return;
 518 }
 519
 520 /**
 521  * mpi_init_check - check firmware initialization status.
 522  * @pm8001_ha: our hba card information
 523  */
 524 static int mpi_init_check(struct pm8001_hba_info *pm8001_ha)
 525 {
 526         u32 max_wait_count;
 527         u32 value;
 528         u32 gst_len_mpistate;
 529         /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the
 530         table is updated */
 531         pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_UPDATE);
 532         /* wait until Inbound DoorBell Clear Register toggled */
 533         max_wait_count = 1 * 1000 * 1000;/* 1 sec */
 534         do {
 535                 udelay(1);
 536                 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
 537                 value &= SPC_MSGU_CFG_TABLE_UPDATE;
 538         } while ((value != 0) && (--max_wait_count));
 539
 540         if (!max_wait_count)
 541                 return -1;
 542         /* check the MPI-State for initialization */
 543         gst_len_mpistate =
 544                 pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
 545                 GST_GSTLEN_MPIS_OFFSET);
 546         if (GST_MPI_STATE_INIT != (gst_len_mpistate & GST_MPI_STATE_MASK))
 547                 return -1;
 548         /* check MPI Initialization error */
 549         gst_len_mpistate = gst_len_mpistate >> 16;
 550         if (0x0000 != gst_len_mpistate)
 551                 return -1;
 552         return 0;
 553 }
 554
 555 /**
 556  * check_fw_ready - The LLDD check if the FW is ready, if not, return error.
 557  * @pm8001_ha: our hba card information
 558  */
 559 static int check_fw_ready(struct pm8001_hba_info *pm8001_ha)
 560 {
 561         u32 value, value1;
 562         u32 max_wait_count;
 563         /* check error state */
 564         value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
 565         value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
 566         /* check AAP error */
 567         if (SCRATCH_PAD1_ERR == (value & SCRATCH_PAD_STATE_MASK)) {
 568                 /* error state */
 569                 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
 570                 return -1;
 571         }
 572
 573         /* check IOP error */
 574         if (SCRATCH_PAD2_ERR == (value1 & SCRATCH_PAD_STATE_MASK)) {
 575                 /* error state */
 576                 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
 577                 return -1;
 578         }
 579
 580         /* bit 4-31 of scratch pad1 should be zeros if it is not
 581         in error state*/
 582         if (value & SCRATCH_PAD1_STATE_MASK) {
 583                 /* error case */
 584                 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
 585                 return -1;
 586         }
 587
 588         /* bit 2, 4-31 of scratch pad2 should be zeros if it is not
 589         in error state */
 590         if (value1 & SCRATCH_PAD2_STATE_MASK) {
 591                 /* error case */
 592                 return -1;
 593         }
 594
 595         max_wait_count = 1 * 1000 * 1000;/* 1 sec timeout */
 596
 597         /* wait until scratch pad 1 and 2 registers in ready state  */
 598         do {
 599                 udelay(1);
 600                 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)
 601                         & SCRATCH_PAD1_RDY;
 602                 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)
 603                         & SCRATCH_PAD2_RDY;
 604                 if ((--max_wait_count) == 0)
 605                         return -1;
 606         } while ((value != SCRATCH_PAD1_RDY) || (value1 != SCRATCH_PAD2_RDY));
 607         return 0;
 608 }
 609
 610 static void init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha)
 611 {
 612         void __iomem *base_addr;
 613         u32     value;
 614         u32     offset;
 615         u32     pcibar;
 616         u32     pcilogic;
 617
 618         value = pm8001_cr32(pm8001_ha, 0, 0x44);
 619         offset = value & 0x03FFFFFF;
 620         PM8001_INIT_DBG(pm8001_ha,
 621                 pm8001_printk("Scratchpad 0 Offset: %x\n", offset));
 622         pcilogic = (value & 0xFC000000) >> 26;
 623         pcibar = get_pci_bar_index(pcilogic);
 624         PM8001_INIT_DBG(pm8001_ha,
 625                 pm8001_printk("Scratchpad 0 PCI BAR: %d\n", pcibar));
 626         pm8001_ha->main_cfg_tbl_addr = base_addr =
 627                 pm8001_ha->io_mem[pcibar].memvirtaddr + offset;
 628         pm8001_ha->general_stat_tbl_addr =
 629                 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x18);
 630         pm8001_ha->inbnd_q_tbl_addr =
 631                 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C);
 632         pm8001_ha->outbnd_q_tbl_addr =
 633                 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x20);
 634 }
 635
 636 /**
 637  * pm8001_chip_init - the main init function that initialize whole PM8001 chip.
 638  * @pm8001_ha: our hba card information
 639  */
 640 static int pm8001_chip_init(struct pm8001_hba_info *pm8001_ha)
 641 {
 642         u8 i = 0;
 643         /* check the firmware status */
 644         if (-1 == check_fw_ready(pm8001_ha)) {
 645                 PM8001_FAIL_DBG(pm8001_ha,
 646                         pm8001_printk("Firmware is not ready!\n"));
 647                 return -EBUSY;
 648         }
 649
 650         /* Initialize pci space address eg: mpi offset */
 651         init_pci_device_addresses(pm8001_ha);
 652         init_default_table_values(pm8001_ha);
 653         read_main_config_table(pm8001_ha);
 654         read_general_status_table(pm8001_ha);
 655         read_inbnd_queue_table(pm8001_ha);
 656         read_outbnd_queue_table(pm8001_ha);
 657         /* update main config table ,inbound table and outbound table */
 658         update_main_config_table(pm8001_ha);
 659         for (i = 0; i < PM8001_MAX_INB_NUM; i++)
 660                 update_inbnd_queue_table(pm8001_ha, i);
 661         for (i = 0; i < PM8001_MAX_OUTB_NUM; i++)
 662                 update_outbnd_queue_table(pm8001_ha, i);
 663         mpi_set_phys_g3_with_ssc(pm8001_ha, 0);
 664         /* 7->130ms, 34->500ms, 119->1.5s */
 665         mpi_set_open_retry_interval_reg(pm8001_ha, 119);
 666         /* notify firmware update finished and check initialization status */
 667         if (0 == mpi_init_check(pm8001_ha)) {
 668                 PM8001_INIT_DBG(pm8001_ha,
 669                         pm8001_printk("MPI initialize successful!\n"));
 670         } else
 671                 return -EBUSY;
 672         /*This register is a 16-bit timer with a resolution of 1us. This is the
 673         timer used for interrupt delay/coalescing in the PCIe Application Layer.
 674         Zero is not a valid value. A value of 1 in the register will cause the
 675         interrupts to be normal. A value greater than 1 will cause coalescing
 676         delays.*/
 677         pm8001_cw32(pm8001_ha, 1, 0x0033c0, 0x1);
 678         pm8001_cw32(pm8001_ha, 1, 0x0033c4, 0x0);
 679         return 0;
 680 }
 681
 682 static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha)
 683 {
 684         u32 max_wait_count;
 685         u32 value;
 686         u32 gst_len_mpistate;
 687         init_pci_device_addresses(pm8001_ha);
 688         /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the
 689         table is stop */
 690         pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_RESET);
 691
 692         /* wait until Inbound DoorBell Clear Register toggled */
 693         max_wait_count = 1 * 1000 * 1000;/* 1 sec */
 694         do {
 695                 udelay(1);
 696                 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
 697                 value &= SPC_MSGU_CFG_TABLE_RESET;
 698         } while ((value != 0) && (--max_wait_count));
 699
 700         if (!max_wait_count) {
 701                 PM8001_FAIL_DBG(pm8001_ha,
 702                         pm8001_printk("TIMEOUT:IBDB value/=0x%x\n", value));
 703                 return -1;
 704         }
 705
 706         /* check the MPI-State for termination in progress */
 707         /* wait until Inbound DoorBell Clear Register toggled */
 708         max_wait_count = 1 * 1000 * 1000;  /* 1 sec */
 709         do {
 710                 udelay(1);
 711                 gst_len_mpistate =
 712                         pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
 713                         GST_GSTLEN_MPIS_OFFSET);
 714                 if (GST_MPI_STATE_UNINIT ==
 715                         (gst_len_mpistate & GST_MPI_STATE_MASK))
 716                         break;
 717         } while (--max_wait_count);
 718         if (!max_wait_count) {
 719                 PM8001_FAIL_DBG(pm8001_ha,
 720                         pm8001_printk(" TIME OUT MPI State = 0x%x\n",
 721                                 gst_len_mpistate & GST_MPI_STATE_MASK));
 722                 return -1;
 723         }
 724         return 0;
 725 }
 726
 727 /**
 728  * soft_reset_ready_check - Function to check FW is ready for soft reset.
 729  * @pm8001_ha: our hba card information
 730  */
 731 static u32 soft_reset_ready_check(struct pm8001_hba_info *pm8001_ha)
 732 {
 733         u32 regVal, regVal1, regVal2;
 734         if (mpi_uninit_check(pm8001_ha) != 0) {
 735                 PM8001_FAIL_DBG(pm8001_ha,
 736                         pm8001_printk("MPI state is not ready\n"));
 737                 return -1;
 738         }
 739         /* read the scratch pad 2 register bit 2 */
 740         regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)
 741                 & SCRATCH_PAD2_FWRDY_RST;
 742         if (regVal == SCRATCH_PAD2_FWRDY_RST) {
 743                 PM8001_INIT_DBG(pm8001_ha,
 744                         pm8001_printk("Firmware is ready for reset .\n"));
 745         } else {
 746                 unsigned long flags;
 747                 /* Trigger NMI twice via RB6 */
 748                 spin_lock_irqsave(&pm8001_ha->lock, flags);
 749                 if (-1 == pm8001_bar4_shift(pm8001_ha, RB6_ACCESS_REG)) {
 750                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 751                         PM8001_FAIL_DBG(pm8001_ha,
 752                                 pm8001_printk("Shift Bar4 to 0x%x failed\n",
 753                                         RB6_ACCESS_REG));
 754                         return -1;
 755                 }
 756                 pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET,
 757                         RB6_MAGIC_NUMBER_RST);
 758                 pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET, RB6_MAGIC_NUMBER_RST);
 759                 /* wait for 100 ms */
 760                 mdelay(100);
 761                 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2) &
 762                         SCRATCH_PAD2_FWRDY_RST;
 763                 if (regVal != SCRATCH_PAD2_FWRDY_RST) {
 764                         regVal1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
 765                         regVal2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
 766                         PM8001_FAIL_DBG(pm8001_ha,
 767                                 pm8001_printk("TIMEOUT:MSGU_SCRATCH_PAD1"
 768                                 "=0x%x, MSGU_SCRATCH_PAD2=0x%x\n",
 769                                 regVal1, regVal2));
 770                         PM8001_FAIL_DBG(pm8001_ha,
 771                                 pm8001_printk("SCRATCH_PAD0 value = 0x%x\n",
 772                                 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0)));
 773                         PM8001_FAIL_DBG(pm8001_ha,
 774                                 pm8001_printk("SCRATCH_PAD3 value = 0x%x\n",
 775                                 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3)));
 776                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 777                         return -1;
 778                 }
 779                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 780         }
 781         return 0;
 782 }
 783
 784 /**
 785  * pm8001_chip_soft_rst - soft reset the PM8001 chip, so that the clear all
 786  * the FW register status to the originated status.
 787  * @pm8001_ha: our hba card information
 788  */
 789 static int
 790 pm8001_chip_soft_rst(struct pm8001_hba_info *pm8001_ha)
 791 {
 792         u32     regVal, toggleVal;
 793         u32     max_wait_count;
 794         u32     regVal1, regVal2, regVal3;
 795         u32     signature = 0x252acbcd; /* for host scratch pad0 */
 796         unsigned long flags;
 797
 798         /* step1: Check FW is ready for soft reset */
 799         if (soft_reset_ready_check(pm8001_ha) != 0) {
 800                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("FW is not ready\n"));
 801                 return -1;
 802         }
 803
 804         /* step 2: clear NMI status register on AAP1 and IOP, write the same
 805         value to clear */
 806         /* map 0x60000 to BAR4(0x20), BAR2(win) */
 807         spin_lock_irqsave(&pm8001_ha->lock, flags);
 808         if (-1 == pm8001_bar4_shift(pm8001_ha, MBIC_AAP1_ADDR_BASE)) {
 809                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 810                 PM8001_FAIL_DBG(pm8001_ha,
 811                         pm8001_printk("Shift Bar4 to 0x%x failed\n",
 812                         MBIC_AAP1_ADDR_BASE));
 813                 return -1;
 814         }
 815         regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP);
 816         PM8001_INIT_DBG(pm8001_ha,
 817                 pm8001_printk("MBIC - NMI Enable VPE0 (IOP)= 0x%x\n", regVal));
 818         pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP, 0x0);
 819         /* map 0x70000 to BAR4(0x20), BAR2(win) */
 820         if (-1 == pm8001_bar4_shift(pm8001_ha, MBIC_IOP_ADDR_BASE)) {
 821                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 822                 PM8001_FAIL_DBG(pm8001_ha,
 823                         pm8001_printk("Shift Bar4 to 0x%x failed\n",
 824                         MBIC_IOP_ADDR_BASE));
 825                 return -1;
 826         }
 827         regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1);
 828         PM8001_INIT_DBG(pm8001_ha,
 829                 pm8001_printk("MBIC - NMI Enable VPE0 (AAP1)= 0x%x\n", regVal));
 830         pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1, 0x0);
 831
 832         regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE);
 833         PM8001_INIT_DBG(pm8001_ha,
 834                 pm8001_printk("PCIE -Event Interrupt Enable = 0x%x\n", regVal));
 835         pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE, 0x0);
 836
 837         regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT);
 838         PM8001_INIT_DBG(pm8001_ha,
 839                 pm8001_printk("PCIE - Event Interrupt  = 0x%x\n", regVal));
 840         pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT, regVal);
 841
 842         regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE);
 843         PM8001_INIT_DBG(pm8001_ha,
 844                 pm8001_printk("PCIE -Error Interrupt Enable = 0x%x\n", regVal));
 845         pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE, 0x0);
 846
 847         regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT);
 848         PM8001_INIT_DBG(pm8001_ha,
 849                 pm8001_printk("PCIE - Error Interrupt = 0x%x\n", regVal));
 850         pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT, regVal);
 851
 852         /* read the scratch pad 1 register bit 2 */
 853         regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)
 854                 & SCRATCH_PAD1_RST;
 855         toggleVal = regVal ^ SCRATCH_PAD1_RST;
 856
 857         /* set signature in host scratch pad0 register to tell SPC that the
 858         host performs the soft reset */
 859         pm8001_cw32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_0, signature);
 860
 861         /* read required registers for confirmming */
 862         /* map 0x0700000 to BAR4(0x20), BAR2(win) */
 863         if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_ADDR_BASE)) {
 864                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 865                 PM8001_FAIL_DBG(pm8001_ha,
 866                         pm8001_printk("Shift Bar4 to 0x%x failed\n",
 867                         GSM_ADDR_BASE));
 868                 return -1;
 869         }
 870         PM8001_INIT_DBG(pm8001_ha,
 871                 pm8001_printk("GSM 0x0(0x00007b88)-GSM Configuration and"
 872                 " Reset = 0x%x\n",
 873                 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
 874
 875         /* step 3: host read GSM Configuration and Reset register */
 876         regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET);
 877         /* Put those bits to low */
 878         /* GSM XCBI offset = 0x70 0000
 879         0x00 Bit 13 COM_SLV_SW_RSTB 1
 880         0x00 Bit 12 QSSP_SW_RSTB 1
 881         0x00 Bit 11 RAAE_SW_RSTB 1
 882         0x00 Bit 9 RB_1_SW_RSTB 1
 883         0x00 Bit 8 SM_SW_RSTB 1
 884         */
 885         regVal &= ~(0x00003b00);
 886         /* host write GSM Configuration and Reset register */
 887         pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal);
 888         PM8001_INIT_DBG(pm8001_ha,
 889                 pm8001_printk("GSM 0x0 (0x00007b88 ==> 0x00004088) - GSM "
 890                 "Configuration and Reset is set to = 0x%x\n",
 891                 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
 892
 893         /* step 4: */
 894         /* disable GSM - Read Address Parity Check */
 895         regVal1 = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK);
 896         PM8001_INIT_DBG(pm8001_ha,
 897                 pm8001_printk("GSM 0x700038 - Read Address Parity Check "
 898                 "Enable = 0x%x\n", regVal1));
 899         pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, 0x0);
 900         PM8001_INIT_DBG(pm8001_ha,
 901                 pm8001_printk("GSM 0x700038 - Read Address Parity Check Enable"
 902                 "is set to = 0x%x\n",
 903                 pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK)));
 904
 905         /* disable GSM - Write Address Parity Check */
 906         regVal2 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK);
 907         PM8001_INIT_DBG(pm8001_ha,
 908                 pm8001_printk("GSM 0x700040 - Write Address Parity Check"
 909                 " Enable = 0x%x\n", regVal2));
 910         pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, 0x0);
 911         PM8001_INIT_DBG(pm8001_ha,
 912                 pm8001_printk("GSM 0x700040 - Write Address Parity Check "
 913                 "Enable is set to = 0x%x\n",
 914                 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK)));
 915
 916         /* disable GSM - Write Data Parity Check */
 917         regVal3 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK);
 918         PM8001_INIT_DBG(pm8001_ha,
 919                 pm8001_printk("GSM 0x300048 - Write Data Parity Check"
 920                 " Enable = 0x%x\n", regVal3));
 921         pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, 0x0);
 922         PM8001_INIT_DBG(pm8001_ha,
 923                 pm8001_printk("GSM 0x300048 - Write Data Parity Check Enable"
 924                 "is set to = 0x%x\n",
 925         pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK)));
 926
 927         /* step 5: delay 10 usec */
 928         udelay(10);
 929         /* step 5-b: set GPIO-0 output control to tristate anyway */
 930         if (-1 == pm8001_bar4_shift(pm8001_ha, GPIO_ADDR_BASE)) {
 931                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 932                 PM8001_INIT_DBG(pm8001_ha,
 933                                 pm8001_printk("Shift Bar4 to 0x%x failed\n",
 934                                 GPIO_ADDR_BASE));
 935                 return -1;
 936         }
 937         regVal = pm8001_cr32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET);
 938                 PM8001_INIT_DBG(pm8001_ha,
 939                                 pm8001_printk("GPIO Output Control Register:"
 940                                 " = 0x%x\n", regVal));
 941         /* set GPIO-0 output control to tri-state */
 942         regVal &= 0xFFFFFFFC;
 943         pm8001_cw32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET, regVal);
 944
 945         /* Step 6: Reset the IOP and AAP1 */
 946         /* map 0x00000 to BAR4(0x20), BAR2(win) */
 947         if (-1 == pm8001_bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) {
 948                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 949                 PM8001_FAIL_DBG(pm8001_ha,
 950                         pm8001_printk("SPC Shift Bar4 to 0x%x failed\n",
 951                         SPC_TOP_LEVEL_ADDR_BASE));
 952                 return -1;
 953         }
 954         regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
 955         PM8001_INIT_DBG(pm8001_ha,
 956                 pm8001_printk("Top Register before resetting IOP/AAP1"
 957                 ":= 0x%x\n", regVal));
 958         regVal &= ~(SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS);
 959         pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
 960
 961         /* step 7: Reset the BDMA/OSSP */
 962         regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
 963         PM8001_INIT_DBG(pm8001_ha,
 964                 pm8001_printk("Top Register before resetting BDMA/OSSP"
 965                 ": = 0x%x\n", regVal));
 966         regVal &= ~(SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP);
 967         pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
 968
 969         /* step 8: delay 10 usec */
 970         udelay(10);
 971
 972         /* step 9: bring the BDMA and OSSP out of reset */
 973         regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
 974         PM8001_INIT_DBG(pm8001_ha,
 975                 pm8001_printk("Top Register before bringing up BDMA/OSSP"
 976                 ":= 0x%x\n", regVal));
 977         regVal |= (SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP);
 978         pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
 979
 980         /* step 10: delay 10 usec */
 981         udelay(10);
 982
 983         /* step 11: reads and sets the GSM Configuration and Reset Register */
 984         /* map 0x0700000 to BAR4(0x20), BAR2(win) */
 985         if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_ADDR_BASE)) {
 986                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 987                 PM8001_FAIL_DBG(pm8001_ha,
 988                         pm8001_printk("SPC Shift Bar4 to 0x%x failed\n",
 989                         GSM_ADDR_BASE));
 990                 return -1;
 991         }
 992         PM8001_INIT_DBG(pm8001_ha,
 993                 pm8001_printk("GSM 0x0 (0x00007b88)-GSM Configuration and "
 994                 "Reset = 0x%x\n", pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
 995         regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET);
 996         /* Put those bits to high */
 997         /* GSM XCBI offset = 0x70 0000
 998         0x00 Bit 13 COM_SLV_SW_RSTB 1
 999         0x00 Bit 12 QSSP_SW_RSTB 1
1000         0x00 Bit 11 RAAE_SW_RSTB 1
1001         0x00 Bit 9   RB_1_SW_RSTB 1
1002         0x00 Bit 8   SM_SW_RSTB 1
1003         */
1004         regVal |= (GSM_CONFIG_RESET_VALUE);
1005         pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal);
1006         PM8001_INIT_DBG(pm8001_ha,
1007                 pm8001_printk("GSM (0x00004088 ==> 0x00007b88) - GSM"
1008                 " Configuration and Reset is set to = 0x%x\n",
1009                 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
1010
1011         /* step 12: Restore GSM - Read Address Parity Check */
1012         regVal = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK);
1013         /* just for debugging */
1014         PM8001_INIT_DBG(pm8001_ha,
1015                 pm8001_printk("GSM 0x700038 - Read Address Parity Check Enable"
1016                 " = 0x%x\n", regVal));
1017         pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, regVal1);
1018         PM8001_INIT_DBG(pm8001_ha,
1019                 pm8001_printk("GSM 0x700038 - Read Address Parity"
1020                 " Check Enable is set to = 0x%x\n",
1021                 pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK)));
1022         /* Restore GSM - Write Address Parity Check */
1023         regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK);
1024         pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, regVal2);
1025         PM8001_INIT_DBG(pm8001_ha,
1026                 pm8001_printk("GSM 0x700040 - Write Address Parity Check"
1027                 " Enable is set to = 0x%x\n",
1028                 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK)));
1029         /* Restore GSM - Write Data Parity Check */
1030         regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK);
1031         pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, regVal3);
1032         PM8001_INIT_DBG(pm8001_ha,
1033                 pm8001_printk("GSM 0x700048 - Write Data Parity Check Enable"
1034                 "is set to = 0x%x\n",
1035                 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK)));
1036
1037         /* step 13: bring the IOP and AAP1 out of reset */
1038         /* map 0x00000 to BAR4(0x20), BAR2(win) */
1039         if (-1 == pm8001_bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) {
1040                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1041                 PM8001_FAIL_DBG(pm8001_ha,
1042                         pm8001_printk("Shift Bar4 to 0x%x failed\n",
1043                         SPC_TOP_LEVEL_ADDR_BASE));
1044                 return -1;
1045         }
1046         regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
1047         regVal |= (SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS);
1048         pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
1049
1050         /* step 14: delay 10 usec - Normal Mode */
1051         udelay(10);
1052         /* check Soft Reset Normal mode or Soft Reset HDA mode */
1053         if (signature == SPC_SOFT_RESET_SIGNATURE) {
1054                 /* step 15 (Normal Mode): wait until scratch pad1 register
1055                 bit 2 toggled */
1056                 max_wait_count = 2 * 1000 * 1000;/* 2 sec */
1057                 do {
1058                         udelay(1);
1059                         regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) &
1060                                 SCRATCH_PAD1_RST;
1061                 } while ((regVal != toggleVal) && (--max_wait_count));
1062
1063                 if (!max_wait_count) {
1064                         regVal = pm8001_cr32(pm8001_ha, 0,
1065                                 MSGU_SCRATCH_PAD_1);
1066                         PM8001_FAIL_DBG(pm8001_ha,
1067                                 pm8001_printk("TIMEOUT : ToggleVal 0x%x,"
1068                                 "MSGU_SCRATCH_PAD1 = 0x%x\n",
1069                                 toggleVal, regVal));
1070                         PM8001_FAIL_DBG(pm8001_ha,
1071                                 pm8001_printk("SCRATCH_PAD0 value = 0x%x\n",
1072                                 pm8001_cr32(pm8001_ha, 0,
1073                                 MSGU_SCRATCH_PAD_0)));
1074                         PM8001_FAIL_DBG(pm8001_ha,
1075                                 pm8001_printk("SCRATCH_PAD2 value = 0x%x\n",
1076                                 pm8001_cr32(pm8001_ha, 0,
1077                                 MSGU_SCRATCH_PAD_2)));
1078                         PM8001_FAIL_DBG(pm8001_ha,
1079                                 pm8001_printk("SCRATCH_PAD3 value = 0x%x\n",
1080                                 pm8001_cr32(pm8001_ha, 0,
1081                                 MSGU_SCRATCH_PAD_3)));
1082                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1083                         return -1;
1084                 }
1085
1086                 /* step 16 (Normal) - Clear ODMR and ODCR */
1087                 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1088                 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1089
1090                 /* step 17 (Normal Mode): wait for the FW and IOP to get
1091                 ready - 1 sec timeout */
1092                 /* Wait for the SPC Configuration Table to be ready */
1093                 if (check_fw_ready(pm8001_ha) == -1) {
1094                         regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1095                         /* return error if MPI Configuration Table not ready */
1096                         PM8001_INIT_DBG(pm8001_ha,
1097                                 pm8001_printk("FW not ready SCRATCH_PAD1"
1098                                 " = 0x%x\n", regVal));
1099                         regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
1100                         /* return error if MPI Configuration Table not ready */
1101                         PM8001_INIT_DBG(pm8001_ha,
1102                                 pm8001_printk("FW not ready SCRATCH_PAD2"
1103                                 " = 0x%x\n", regVal));
1104                         PM8001_INIT_DBG(pm8001_ha,
1105                                 pm8001_printk("SCRATCH_PAD0 value = 0x%x\n",
1106                                 pm8001_cr32(pm8001_ha, 0,
1107                                 MSGU_SCRATCH_PAD_0)));
1108                         PM8001_INIT_DBG(pm8001_ha,
1109                                 pm8001_printk("SCRATCH_PAD3 value = 0x%x\n",
1110                                 pm8001_cr32(pm8001_ha, 0,
1111                                 MSGU_SCRATCH_PAD_3)));
1112                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1113                         return -1;
1114                 }
1115         }
1116         pm8001_bar4_shift(pm8001_ha, 0);
1117         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1118
1119         PM8001_INIT_DBG(pm8001_ha,
1120                 pm8001_printk("SPC soft reset Complete\n"));
1121         return 0;
1122 }
1123
1124 static void pm8001_hw_chip_rst(struct pm8001_hba_info *pm8001_ha)
1125 {
1126         u32 i;
1127         u32 regVal;
1128         PM8001_INIT_DBG(pm8001_ha,
1129                 pm8001_printk("chip reset start\n"));
1130
1131         /* do SPC chip reset. */
1132         regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET);
1133         regVal &= ~(SPC_REG_RESET_DEVICE);
1134         pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal);
1135
1136         /* delay 10 usec */
1137         udelay(10);
1138
1139         /* bring chip reset out of reset */
1140         regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET);
1141         regVal |= SPC_REG_RESET_DEVICE;
1142         pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal);
1143
1144         /* delay 10 usec */
1145         udelay(10);
1146
1147         /* wait for 20 msec until the firmware gets reloaded */
1148         i = 20;
1149         do {
1150                 mdelay(1);
1151         } while ((--i) != 0);
1152
1153         PM8001_INIT_DBG(pm8001_ha,
1154                 pm8001_printk("chip reset finished\n"));
1155 }
1156
1157 /**
1158  * pm8001_chip_iounmap - which maped when initialized.
1159  * @pm8001_ha: our hba card information
1160  */
1161 void pm8001_chip_iounmap(struct pm8001_hba_info *pm8001_ha)
1162 {
1163         s8 bar, logical = 0;
1164         for (bar = 0; bar < 6; bar++) {
1165                 /*
1166                 ** logical BARs for SPC:
1167                 ** bar 0 and 1 - logical BAR0
1168                 ** bar 2 and 3 - logical BAR1
1169                 ** bar4 - logical BAR2
1170                 ** bar5 - logical BAR3
1171                 ** Skip the appropriate assignments:
1172                 */
1173                 if ((bar == 1) || (bar == 3))
1174                         continue;
1175                 if (pm8001_ha->io_mem[logical].memvirtaddr) {
1176                         iounmap(pm8001_ha->io_mem[logical].memvirtaddr);
1177                         logical++;
1178                 }
1179         }
1180 }
1181
1182 /**
1183  * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1184  * @pm8001_ha: our hba card information
1185  */
1186 static void
1187 pm8001_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha)
1188 {
1189         pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1190         pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1191 }
1192
1193  /**
1194   * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt
1195   * @pm8001_ha: our hba card information
1196   */
1197 static void
1198 pm8001_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha)
1199 {
1200         pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_MASK_ALL);
1201 }
1202
1203 /**
1204  * pm8001_chip_msix_interrupt_enable - enable PM8001 chip interrupt
1205  * @pm8001_ha: our hba card information
1206  */
1207 static void
1208 pm8001_chip_msix_interrupt_enable(struct pm8001_hba_info *pm8001_ha,
1209         u32 int_vec_idx)
1210 {
1211         u32 msi_index;
1212         u32 value;
1213         msi_index = int_vec_idx * MSIX_TABLE_ELEMENT_SIZE;
1214         msi_index += MSIX_TABLE_BASE;
1215         pm8001_cw32(pm8001_ha, 0, msi_index, MSIX_INTERRUPT_ENABLE);
1216         value = (1 << int_vec_idx);
1217         pm8001_cw32(pm8001_ha, 0,  MSGU_ODCR, value);
1218
1219 }
1220
1221 /**
1222  * pm8001_chip_msix_interrupt_disable - disable PM8001 chip interrupt
1223  * @pm8001_ha: our hba card information
1224  */
1225 static void
1226 pm8001_chip_msix_interrupt_disable(struct pm8001_hba_info *pm8001_ha,
1227         u32 int_vec_idx)
1228 {
1229         u32 msi_index;
1230         msi_index = int_vec_idx * MSIX_TABLE_ELEMENT_SIZE;
1231         msi_index += MSIX_TABLE_BASE;
1232         pm8001_cw32(pm8001_ha, 0,  msi_index, MSIX_INTERRUPT_DISABLE);
1233 }
1234
1235 /**
1236  * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1237  * @pm8001_ha: our hba card information
1238  */
1239 static void
1240 pm8001_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1241 {
1242 #ifdef PM8001_USE_MSIX
1243         pm8001_chip_msix_interrupt_enable(pm8001_ha, 0);
1244         return;
1245 #endif
1246         pm8001_chip_intx_interrupt_enable(pm8001_ha);
1247
1248 }
1249
1250 /**
1251  * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt
1252  * @pm8001_ha: our hba card information
1253  */
1254 static void
1255 pm8001_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1256 {
1257 #ifdef PM8001_USE_MSIX
1258         pm8001_chip_msix_interrupt_disable(pm8001_ha, 0);
1259         return;
1260 #endif
1261         pm8001_chip_intx_interrupt_disable(pm8001_ha);
1262
1263 }
1264
1265 /**
1266  * pm8001_mpi_msg_free_get - get the free message buffer for transfer
1267  * inbound queue.
1268  * @circularQ: the inbound queue  we want to transfer to HBA.
1269  * @messageSize: the message size of this transfer, normally it is 64 bytes
1270  * @messagePtr: the pointer to message.
1271  */
1272 int pm8001_mpi_msg_free_get(struct inbound_queue_table *circularQ,
1273                             u16 messageSize, void **messagePtr)
1274 {
1275         u32 offset, consumer_index;
1276         struct mpi_msg_hdr *msgHeader;
1277         u8 bcCount = 1; /* only support single buffer */
1278
1279         /* Checks is the requested message size can be allocated in this queue*/
1280         if (messageSize > IOMB_SIZE_SPCV) {
1281                 *messagePtr = NULL;
1282                 return -1;
1283         }
1284
1285         /* Stores the new consumer index */
1286         consumer_index = pm8001_read_32(circularQ->ci_virt);
1287         circularQ->consumer_index = cpu_to_le32(consumer_index);
1288         if (((circularQ->producer_idx + bcCount) % PM8001_MPI_QUEUE) ==
1289                 le32_to_cpu(circularQ->consumer_index)) {
1290                 *messagePtr = NULL;
1291                 return -1;
1292         }
1293         /* get memory IOMB buffer address */
1294         offset = circularQ->producer_idx * messageSize;
1295         /* increment to next bcCount element */
1296         circularQ->producer_idx = (circularQ->producer_idx + bcCount)
1297                                 % PM8001_MPI_QUEUE;
1298         /* Adds that distance to the base of the region virtual address plus
1299         the message header size*/
1300         msgHeader = (struct mpi_msg_hdr *)(circularQ->base_virt + offset);
1301         *messagePtr = ((void *)msgHeader) + sizeof(struct mpi_msg_hdr);
1302         return 0;
1303 }
1304
1305 /**
1306  * pm8001_mpi_build_cmd- build the message queue for transfer, update the PI to
1307  * FW to tell the fw to get this message from IOMB.
1308  * @pm8001_ha: our hba card information
1309  * @circularQ: the inbound queue we want to transfer to HBA.
1310  * @opCode: the operation code represents commands which LLDD and fw recognized.
1311  * @payload: the command payload of each operation command.
1312  */
1313 int pm8001_mpi_build_cmd(struct pm8001_hba_info *pm8001_ha,
1314                          struct inbound_queue_table *circularQ,
1315                          u32 opCode, void *payload, u32 responseQueue)
1316 {
1317         u32 Header = 0, hpriority = 0, bc = 1, category = 0x02;
1318         void *pMessage;
1319
1320         if (pm8001_mpi_msg_free_get(circularQ, pm8001_ha->iomb_size,
1321                 &pMessage) < 0) {
1322                 PM8001_IO_DBG(pm8001_ha,
1323                         pm8001_printk("No free mpi buffer\n"));
1324                 return -1;
1325         }
1326         BUG_ON(!payload);
1327         /*Copy to the payload*/
1328         memcpy(pMessage, payload, (pm8001_ha->iomb_size -
1329                                 sizeof(struct mpi_msg_hdr)));
1330
1331         /*Build the header*/
1332         Header = ((1 << 31) | (hpriority << 30) | ((bc & 0x1f) << 24)
1333                 | ((responseQueue & 0x3F) << 16)
1334                 | ((category & 0xF) << 12) | (opCode & 0xFFF));
1335
1336         pm8001_write_32((pMessage - 4), 0, cpu_to_le32(Header));
1337         /*Update the PI to the firmware*/
1338         pm8001_cw32(pm8001_ha, circularQ->pi_pci_bar,
1339                 circularQ->pi_offset, circularQ->producer_idx);
1340         PM8001_IO_DBG(pm8001_ha,
1341                 pm8001_printk("INB Q %x OPCODE:%x , UPDATED PI=%d CI=%d\n",
1342                         responseQueue, opCode, circularQ->producer_idx,
1343                         circularQ->consumer_index));
1344         return 0;
1345 }
1346
1347 u32 pm8001_mpi_msg_free_set(struct pm8001_hba_info *pm8001_ha, void *pMsg,
1348                             struct outbound_queue_table *circularQ, u8 bc)
1349 {
1350         u32 producer_index;
1351         struct mpi_msg_hdr *msgHeader;
1352         struct mpi_msg_hdr *pOutBoundMsgHeader;
1353
1354         msgHeader = (struct mpi_msg_hdr *)(pMsg - sizeof(struct mpi_msg_hdr));
1355         pOutBoundMsgHeader = (struct mpi_msg_hdr *)(circularQ->base_virt +
1356                                 circularQ->consumer_idx * pm8001_ha->iomb_size);
1357         if (pOutBoundMsgHeader != msgHeader) {
1358                 PM8001_FAIL_DBG(pm8001_ha,
1359                         pm8001_printk("consumer_idx = %d msgHeader = %p\n",
1360                         circularQ->consumer_idx, msgHeader));
1361
1362                 /* Update the producer index from SPC */
1363                 producer_index = pm8001_read_32(circularQ->pi_virt);
1364                 circularQ->producer_index = cpu_to_le32(producer_index);
1365                 PM8001_FAIL_DBG(pm8001_ha,
1366                         pm8001_printk("consumer_idx = %d producer_index = %d"
1367                         "msgHeader = %p\n", circularQ->consumer_idx,
1368                         circularQ->producer_index, msgHeader));
1369                 return 0;
1370         }
1371         /* free the circular queue buffer elements associated with the message*/
1372         circularQ->consumer_idx = (circularQ->consumer_idx + bc)
1373                                 % PM8001_MPI_QUEUE;
1374         /* update the CI of outbound queue */
1375         pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar, circularQ->ci_offset,
1376                 circularQ->consumer_idx);
1377         /* Update the producer index from SPC*/
1378         producer_index = pm8001_read_32(circularQ->pi_virt);
1379         circularQ->producer_index = cpu_to_le32(producer_index);
1380         PM8001_IO_DBG(pm8001_ha,
1381                 pm8001_printk(" CI=%d PI=%d\n", circularQ->consumer_idx,
1382                 circularQ->producer_index));
1383         return 0;
1384 }
1385
1386 /**
1387  * pm8001_mpi_msg_consume- get the MPI message from outbound queue
1388  * message table.
1389  * @pm8001_ha: our hba card information
1390  * @circularQ: the outbound queue  table.
1391  * @messagePtr1: the message contents of this outbound message.
1392  * @pBC: the message size.
1393  */
1394 u32 pm8001_mpi_msg_consume(struct pm8001_hba_info *pm8001_ha,
1395                            struct outbound_queue_table *circularQ,
1396                            void **messagePtr1, u8 *pBC)
1397 {
1398         struct mpi_msg_hdr      *msgHeader;
1399         __le32  msgHeader_tmp;
1400         u32 header_tmp;
1401         do {
1402                 /* If there are not-yet-delivered messages ... */
1403                 if (le32_to_cpu(circularQ->producer_index)
1404                         != circularQ->consumer_idx) {
1405                         /*Get the pointer to the circular queue buffer element*/
1406                         msgHeader = (struct mpi_msg_hdr *)
1407                                 (circularQ->base_virt +
1408                                 circularQ->consumer_idx * pm8001_ha->iomb_size);
1409                         /* read header */
1410                         header_tmp = pm8001_read_32(msgHeader);
1411                         msgHeader_tmp = cpu_to_le32(header_tmp);
1412                         if (0 != (le32_to_cpu(msgHeader_tmp) & 0x80000000)) {
1413                                 if (OPC_OUB_SKIP_ENTRY !=
1414                                         (le32_to_cpu(msgHeader_tmp) & 0xfff)) {
1415                                         *messagePtr1 =
1416                                                 ((u8 *)msgHeader) +
1417                                                 sizeof(struct mpi_msg_hdr);
1418                                         *pBC = (u8)((le32_to_cpu(msgHeader_tmp)
1419                                                 >> 24) & 0x1f);
1420                                         PM8001_IO_DBG(pm8001_ha,
1421                                                 pm8001_printk(": CI=%d PI=%d "
1422                                                 "msgHeader=%x\n",
1423                                                 circularQ->consumer_idx,
1424                                                 circularQ->producer_index,
1425                                                 msgHeader_tmp));
1426                                         return MPI_IO_STATUS_SUCCESS;
1427                                 } else {
1428                                         circularQ->consumer_idx =
1429                                                 (circularQ->consumer_idx +
1430                                                 ((le32_to_cpu(msgHeader_tmp)
1431                                                  >> 24) & 0x1f))
1432                                                         % PM8001_MPI_QUEUE;
1433                                         msgHeader_tmp = 0;
1434                                         pm8001_write_32(msgHeader, 0, 0);
1435                                         /* update the CI of outbound queue */
1436                                         pm8001_cw32(pm8001_ha,
1437                                                 circularQ->ci_pci_bar,
1438                                                 circularQ->ci_offset,
1439                                                 circularQ->consumer_idx);
1440                                 }
1441                         } else {
1442                                 circularQ->consumer_idx =
1443                                         (circularQ->consumer_idx +
1444                                         ((le32_to_cpu(msgHeader_tmp) >> 24) &
1445                                         0x1f)) % PM8001_MPI_QUEUE;
1446                                 msgHeader_tmp = 0;
1447                                 pm8001_write_32(msgHeader, 0, 0);
1448                                 /* update the CI of outbound queue */
1449                                 pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar,
1450                                         circularQ->ci_offset,
1451                                         circularQ->consumer_idx);
1452                                 return MPI_IO_STATUS_FAIL;
1453                         }
1454                 } else {
1455                         u32 producer_index;
1456                         void *pi_virt = circularQ->pi_virt;
1457                         /* Update the producer index from SPC */
1458                         producer_index = pm8001_read_32(pi_virt);
1459                         circularQ->producer_index = cpu_to_le32(producer_index);
1460                 }
1461         } while (le32_to_cpu(circularQ->producer_index) !=
1462                 circularQ->consumer_idx);
1463         /* while we don't have any more not-yet-delivered message */
1464         /* report empty */
1465         return MPI_IO_STATUS_BUSY;
1466 }
1467
1468 void pm8001_work_fn(struct work_struct *work)
1469 {
1470         struct pm8001_work *pw = container_of(work, struct pm8001_work, work);
1471         struct pm8001_device *pm8001_dev;
1472         struct domain_device *dev;
1473
1474         /*
1475          * So far, all users of this stash an associated structure here.
1476          * If we get here, and this pointer is null, then the action
1477          * was cancelled. This nullification happens when the device
1478          * goes away.
1479          */
1480         pm8001_dev = pw->data; /* Most stash device structure */
1481         if ((pm8001_dev == NULL)
1482          || ((pw->handler != IO_XFER_ERROR_BREAK)
1483           && (pm8001_dev->dev_type == NO_DEVICE))) {
1484                 kfree(pw);
1485                 return;
1486         }
1487
1488         switch (pw->handler) {
1489         case IO_XFER_ERROR_BREAK:
1490         {       /* This one stashes the sas_task instead */
1491                 struct sas_task *t = (struct sas_task *)pm8001_dev;
1492                 u32 tag;
1493                 struct pm8001_ccb_info *ccb;
1494                 struct pm8001_hba_info *pm8001_ha = pw->pm8001_ha;
1495                 unsigned long flags, flags1;
1496                 struct task_status_struct *ts;
1497                 int i;
1498
1499                 if (pm8001_query_task(t) == TMF_RESP_FUNC_SUCC)
1500                         break; /* Task still on lu */
1501                 spin_lock_irqsave(&pm8001_ha->lock, flags);
1502
1503                 spin_lock_irqsave(&t->task_state_lock, flags1);
1504                 if (unlikely((t->task_state_flags & SAS_TASK_STATE_DONE))) {
1505                         spin_unlock_irqrestore(&t->task_state_lock, flags1);
1506                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1507                         break; /* Task got completed by another */
1508                 }
1509                 spin_unlock_irqrestore(&t->task_state_lock, flags1);
1510
1511                 /* Search for a possible ccb that matches the task */
1512                 for (i = 0; ccb = NULL, i < PM8001_MAX_CCB; i++) {
1513                         ccb = &pm8001_ha->ccb_info[i];
1514                         tag = ccb->ccb_tag;
1515                         if ((tag != 0xFFFFFFFF) && (ccb->task == t))
1516                                 break;
1517                 }
1518                 if (!ccb) {
1519                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1520                         break; /* Task got freed by another */
1521                 }
1522                 ts = &t->task_status;
1523                 ts->resp = SAS_TASK_COMPLETE;
1524                 /* Force the midlayer to retry */
1525                 ts->stat = SAS_QUEUE_FULL;
1526                 pm8001_dev = ccb->device;
1527                 if (pm8001_dev)
1528                         pm8001_dev->running_req--;
1529                 spin_lock_irqsave(&t->task_state_lock, flags1);
1530                 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
1531                 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
1532                 t->task_state_flags |= SAS_TASK_STATE_DONE;
1533                 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
1534                         spin_unlock_irqrestore(&t->task_state_lock, flags1);
1535                         PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p"
1536                                 " done with event 0x%x resp 0x%x stat 0x%x but"
1537                                 " aborted by upper layer!\n",
1538                                 t, pw->handler, ts->resp, ts->stat));
1539                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1540                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1541                 } else {
1542                         spin_unlock_irqrestore(&t->task_state_lock, flags1);
1543                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1544                         mb();/* in order to force CPU ordering */
1545                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1546                         t->task_done(t);
1547                 }
1548         }       break;
1549         case IO_XFER_OPEN_RETRY_TIMEOUT:
1550         {       /* This one stashes the sas_task instead */
1551                 struct sas_task *t = (struct sas_task *)pm8001_dev;
1552                 u32 tag;
1553                 struct pm8001_ccb_info *ccb;
1554                 struct pm8001_hba_info *pm8001_ha = pw->pm8001_ha;
1555                 unsigned long flags, flags1;
1556                 int i, ret = 0;
1557
1558                 PM8001_IO_DBG(pm8001_ha,
1559                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
1560
1561                 ret = pm8001_query_task(t);
1562
1563                 PM8001_IO_DBG(pm8001_ha,
1564                         switch (ret) {
1565                         case TMF_RESP_FUNC_SUCC:
1566                                 pm8001_printk("...Task on lu\n");
1567                                 break;
1568
1569                         case TMF_RESP_FUNC_COMPLETE:
1570                                 pm8001_printk("...Task NOT on lu\n");
1571                                 break;
1572
1573                         default:
1574                                 pm8001_printk("...query task failed!!!\n");
1575                                 break;
1576                         });
1577
1578                 spin_lock_irqsave(&pm8001_ha->lock, flags);
1579
1580                 spin_lock_irqsave(&t->task_state_lock, flags1);
1581
1582                 if (unlikely((t->task_state_flags & SAS_TASK_STATE_DONE))) {
1583                         spin_unlock_irqrestore(&t->task_state_lock, flags1);
1584                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1585                         if (ret == TMF_RESP_FUNC_SUCC) /* task on lu */
1586                                 (void)pm8001_abort_task(t);
1587                         break; /* Task got completed by another */
1588                 }
1589
1590                 spin_unlock_irqrestore(&t->task_state_lock, flags1);
1591
1592                 /* Search for a possible ccb that matches the task */
1593                 for (i = 0; ccb = NULL, i < PM8001_MAX_CCB; i++) {
1594                         ccb = &pm8001_ha->ccb_info[i];
1595                         tag = ccb->ccb_tag;
1596                         if ((tag != 0xFFFFFFFF) && (ccb->task == t))
1597                                 break;
1598                 }
1599                 if (!ccb) {
1600                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1601                         if (ret == TMF_RESP_FUNC_SUCC) /* task on lu */
1602                                 (void)pm8001_abort_task(t);
1603                         break; /* Task got freed by another */
1604                 }
1605
1606                 pm8001_dev = ccb->device;
1607                 dev = pm8001_dev->sas_device;
1608
1609                 switch (ret) {
1610                 case TMF_RESP_FUNC_SUCC: /* task on lu */
1611                         ccb->open_retry = 1; /* Snub completion */
1612                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1613                         ret = pm8001_abort_task(t);
1614                         ccb->open_retry = 0;
1615                         switch (ret) {
1616                         case TMF_RESP_FUNC_SUCC:
1617                         case TMF_RESP_FUNC_COMPLETE:
1618                                 break;
1619                         default: /* device misbehavior */
1620                                 ret = TMF_RESP_FUNC_FAILED;
1621                                 PM8001_IO_DBG(pm8001_ha,
1622                                         pm8001_printk("...Reset phy\n"));
1623                                 pm8001_I_T_nexus_reset(dev);
1624                                 break;
1625                         }
1626                         break;
1627
1628                 case TMF_RESP_FUNC_COMPLETE: /* task not on lu */
1629                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1630                         /* Do we need to abort the task locally? */
1631                         break;
1632
1633                 default: /* device misbehavior */
1634                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1635                         ret = TMF_RESP_FUNC_FAILED;
1636                         PM8001_IO_DBG(pm8001_ha,
1637                                 pm8001_printk("...Reset phy\n"));
1638                         pm8001_I_T_nexus_reset(dev);
1639                 }
1640
1641                 if (ret == TMF_RESP_FUNC_FAILED)
1642                         t = NULL;
1643                 pm8001_open_reject_retry(pm8001_ha, t, pm8001_dev);
1644                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("...Complete\n"));
1645         }       break;
1646         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1647                 dev = pm8001_dev->sas_device;
1648                 pm8001_I_T_nexus_reset(dev);
1649                 break;
1650         case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
1651                 dev = pm8001_dev->sas_device;
1652                 pm8001_I_T_nexus_reset(dev);
1653                 break;
1654         case IO_DS_IN_ERROR:
1655                 dev = pm8001_dev->sas_device;
1656                 pm8001_I_T_nexus_reset(dev);
1657                 break;
1658         case IO_DS_NON_OPERATIONAL:
1659                 dev = pm8001_dev->sas_device;
1660                 pm8001_I_T_nexus_reset(dev);
1661                 break;
1662         }
1663         kfree(pw);
1664 }
1665
1666 int pm8001_handle_event(struct pm8001_hba_info *pm8001_ha, void *data,
1667                                int handler)
1668 {
1669         struct pm8001_work *pw;
1670         int ret = 0;
1671
1672         pw = kmalloc(sizeof(struct pm8001_work), GFP_ATOMIC);
1673         if (pw) {
1674                 pw->pm8001_ha = pm8001_ha;
1675                 pw->data = data;
1676                 pw->handler = handler;
1677                 INIT_WORK(&pw->work, pm8001_work_fn);
1678                 queue_work(pm8001_wq, &pw->work);
1679         } else
1680                 ret = -ENOMEM;
1681
1682         return ret;
1683 }
1684
1685 /**
1686  * mpi_ssp_completion- process the event that FW response to the SSP request.
1687  * @pm8001_ha: our hba card information
1688  * @piomb: the message contents of this outbound message.
1689  *
1690  * When FW has completed a ssp request for example a IO request, after it has
1691  * filled the SG data with the data, it will trigger this event represent
1692  * that he has finished the job,please check the coresponding buffer.
1693  * So we will tell the caller who maybe waiting the result to tell upper layer
1694  * that the task has been finished.
1695  */
1696 static void
1697 mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha , void *piomb)
1698 {
1699         struct sas_task *t;
1700         struct pm8001_ccb_info *ccb;
1701         unsigned long flags;
1702         u32 status;
1703         u32 param;
1704         u32 tag;
1705         struct ssp_completion_resp *psspPayload;
1706         struct task_status_struct *ts;
1707         struct ssp_response_iu *iu;
1708         struct pm8001_device *pm8001_dev;
1709         psspPayload = (struct ssp_completion_resp *)(piomb + 4);
1710         status = le32_to_cpu(psspPayload->status);
1711         tag = le32_to_cpu(psspPayload->tag);
1712         ccb = &pm8001_ha->ccb_info[tag];
1713         if ((status == IO_ABORTED) && ccb->open_retry) {
1714                 /* Being completed by another */
1715                 ccb->open_retry = 0;
1716                 return;
1717         }
1718         pm8001_dev = ccb->device;
1719         param = le32_to_cpu(psspPayload->param);
1720
1721         t = ccb->task;
1722
1723         if (status && status != IO_UNDERFLOW)
1724                 PM8001_FAIL_DBG(pm8001_ha,
1725                         pm8001_printk("sas IO status 0x%x\n", status));
1726         if (unlikely(!t || !t->lldd_task || !t->dev))
1727                 return;
1728         ts = &t->task_status;
1729         switch (status) {
1730         case IO_SUCCESS:
1731                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS"
1732                         ",param = %d\n", param));
1733                 if (param == 0) {
1734                         ts->resp = SAS_TASK_COMPLETE;
1735                         ts->stat = SAM_STAT_GOOD;
1736                 } else {
1737                         ts->resp = SAS_TASK_COMPLETE;
1738                         ts->stat = SAS_PROTO_RESPONSE;
1739                         ts->residual = param;
1740                         iu = &psspPayload->ssp_resp_iu;
1741                         sas_ssp_task_response(pm8001_ha->dev, t, iu);
1742                 }
1743                 if (pm8001_dev)
1744                         pm8001_dev->running_req--;
1745                 break;
1746         case IO_ABORTED:
1747                 PM8001_IO_DBG(pm8001_ha,
1748                         pm8001_printk("IO_ABORTED IOMB Tag\n"));
1749                 ts->resp = SAS_TASK_COMPLETE;
1750                 ts->stat = SAS_ABORTED_TASK;
1751                 break;
1752         case IO_UNDERFLOW:
1753                 /* SSP Completion with error */
1754                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW"
1755                         ",param = %d\n", param));
1756                 ts->resp = SAS_TASK_COMPLETE;
1757                 ts->stat = SAS_DATA_UNDERRUN;
1758                 ts->residual = param;
1759                 if (pm8001_dev)
1760                         pm8001_dev->running_req--;
1761                 break;
1762         case IO_NO_DEVICE:
1763                 PM8001_IO_DBG(pm8001_ha,
1764                         pm8001_printk("IO_NO_DEVICE\n"));
1765                 ts->resp = SAS_TASK_UNDELIVERED;
1766                 ts->stat = SAS_PHY_DOWN;
1767                 break;
1768         case IO_XFER_ERROR_BREAK:
1769                 PM8001_IO_DBG(pm8001_ha,
1770                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1771                 ts->resp = SAS_TASK_COMPLETE;
1772                 ts->stat = SAS_OPEN_REJECT;
1773                 /* Force the midlayer to retry */
1774                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1775                 break;
1776         case IO_XFER_ERROR_PHY_NOT_READY:
1777                 PM8001_IO_DBG(pm8001_ha,
1778                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1779                 ts->resp = SAS_TASK_COMPLETE;
1780                 ts->stat = SAS_OPEN_REJECT;
1781                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1782                 break;
1783         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1784                 PM8001_IO_DBG(pm8001_ha,
1785                 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
1786                 ts->resp = SAS_TASK_COMPLETE;
1787                 ts->stat = SAS_OPEN_REJECT;
1788                 ts->open_rej_reason = SAS_OREJ_EPROTO;
1789                 break;
1790         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1791                 PM8001_IO_DBG(pm8001_ha,
1792                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1793                 ts->resp = SAS_TASK_COMPLETE;
1794                 ts->stat = SAS_OPEN_REJECT;
1795                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1796                 break;
1797         case IO_OPEN_CNX_ERROR_BREAK:
1798                 PM8001_IO_DBG(pm8001_ha,
1799                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
1800                 ts->resp = SAS_TASK_COMPLETE;
1801                 ts->stat = SAS_OPEN_REJECT;
1802                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1803                 break;
1804         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1805                 PM8001_IO_DBG(pm8001_ha,
1806                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
1807                 ts->resp = SAS_TASK_COMPLETE;
1808                 ts->stat = SAS_OPEN_REJECT;
1809                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1810                 if (!t->uldd_task)
1811                         pm8001_handle_event(pm8001_ha,
1812                                 pm8001_dev,
1813                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1814                 break;
1815         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
1816                 PM8001_IO_DBG(pm8001_ha,
1817                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
1818                 ts->resp = SAS_TASK_COMPLETE;
1819                 ts->stat = SAS_OPEN_REJECT;
1820                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1821                 break;
1822         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
1823                 PM8001_IO_DBG(pm8001_ha,
1824                         pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
1825                         "NOT_SUPPORTED\n"));
1826                 ts->resp = SAS_TASK_COMPLETE;
1827                 ts->stat = SAS_OPEN_REJECT;
1828                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1829                 break;
1830         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
1831                 PM8001_IO_DBG(pm8001_ha,
1832                         pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
1833                 ts->resp = SAS_TASK_UNDELIVERED;
1834                 ts->stat = SAS_OPEN_REJECT;
1835                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
1836                 break;
1837         case IO_XFER_ERROR_NAK_RECEIVED:
1838                 PM8001_IO_DBG(pm8001_ha,
1839                         pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
1840                 ts->resp = SAS_TASK_COMPLETE;
1841                 ts->stat = SAS_OPEN_REJECT;
1842                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1843                 break;
1844         case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
1845                 PM8001_IO_DBG(pm8001_ha,
1846                         pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
1847                 ts->resp = SAS_TASK_COMPLETE;
1848                 ts->stat = SAS_NAK_R_ERR;
1849                 break;
1850         case IO_XFER_ERROR_DMA:
1851                 PM8001_IO_DBG(pm8001_ha,
1852                 pm8001_printk("IO_XFER_ERROR_DMA\n"));
1853                 ts->resp = SAS_TASK_COMPLETE;
1854                 ts->stat = SAS_OPEN_REJECT;
1855                 break;
1856         case IO_XFER_OPEN_RETRY_TIMEOUT:
1857                 PM8001_IO_DBG(pm8001_ha,
1858                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
1859                 ts->resp = SAS_TASK_COMPLETE;
1860                 ts->stat = SAS_OPEN_REJECT;
1861                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1862                 break;
1863         case IO_XFER_ERROR_OFFSET_MISMATCH:
1864                 PM8001_IO_DBG(pm8001_ha,
1865                         pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
1866                 ts->resp = SAS_TASK_COMPLETE;
1867                 ts->stat = SAS_OPEN_REJECT;
1868                 break;
1869         case IO_PORT_IN_RESET:
1870                 PM8001_IO_DBG(pm8001_ha,
1871                         pm8001_printk("IO_PORT_IN_RESET\n"));
1872                 ts->resp = SAS_TASK_COMPLETE;
1873                 ts->stat = SAS_OPEN_REJECT;
1874                 break;
1875         case IO_DS_NON_OPERATIONAL:
1876                 PM8001_IO_DBG(pm8001_ha,
1877                         pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
1878                 ts->resp = SAS_TASK_COMPLETE;
1879                 ts->stat = SAS_OPEN_REJECT;
1880                 if (!t->uldd_task)
1881                         pm8001_handle_event(pm8001_ha,
1882                                 pm8001_dev,
1883                                 IO_DS_NON_OPERATIONAL);
1884                 break;
1885         case IO_DS_IN_RECOVERY:
1886                 PM8001_IO_DBG(pm8001_ha,
1887                         pm8001_printk("IO_DS_IN_RECOVERY\n"));
1888                 ts->resp = SAS_TASK_COMPLETE;
1889                 ts->stat = SAS_OPEN_REJECT;
1890                 break;
1891         case IO_TM_TAG_NOT_FOUND:
1892                 PM8001_IO_DBG(pm8001_ha,
1893                         pm8001_printk("IO_TM_TAG_NOT_FOUND\n"));
1894                 ts->resp = SAS_TASK_COMPLETE;
1895                 ts->stat = SAS_OPEN_REJECT;
1896                 break;
1897         case IO_SSP_EXT_IU_ZERO_LEN_ERROR:
1898                 PM8001_IO_DBG(pm8001_ha,
1899                         pm8001_printk("IO_SSP_EXT_IU_ZERO_LEN_ERROR\n"));
1900                 ts->resp = SAS_TASK_COMPLETE;
1901                 ts->stat = SAS_OPEN_REJECT;
1902                 break;
1903         case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
1904                 PM8001_IO_DBG(pm8001_ha,
1905                         pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
1906                 ts->resp = SAS_TASK_COMPLETE;
1907                 ts->stat = SAS_OPEN_REJECT;
1908                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1909                 break;
1910         default:
1911                 PM8001_IO_DBG(pm8001_ha,
1912                         pm8001_printk("Unknown status 0x%x\n", status));
1913                 /* not allowed case. Therefore, return failed status */
1914                 ts->resp = SAS_TASK_COMPLETE;
1915                 ts->stat = SAS_OPEN_REJECT;
1916                 break;
1917         }
1918         PM8001_IO_DBG(pm8001_ha,
1919                 pm8001_printk("scsi_status = %x \n ",
1920                 psspPayload->ssp_resp_iu.status));
1921         spin_lock_irqsave(&t->task_state_lock, flags);
1922         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
1923         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
1924         t->task_state_flags |= SAS_TASK_STATE_DONE;
1925         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
1926                 spin_unlock_irqrestore(&t->task_state_lock, flags);
1927                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with"
1928                         " io_status 0x%x resp 0x%x "
1929                         "stat 0x%x but aborted by upper layer!\n",
1930                         t, status, ts->resp, ts->stat));
1931                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1932         } else {
1933                 spin_unlock_irqrestore(&t->task_state_lock, flags);
1934                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1935                 mb();/* in order to force CPU ordering */
1936                 t->task_done(t);
1937         }
1938 }
1939
1940 /*See the comments for mpi_ssp_completion */
1941 static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
1942 {
1943         struct sas_task *t;
1944         unsigned long flags;
1945         struct task_status_struct *ts;
1946         struct pm8001_ccb_info *ccb;
1947         struct pm8001_device *pm8001_dev;
1948         struct ssp_event_resp *psspPayload =
1949                 (struct ssp_event_resp *)(piomb + 4);
1950         u32 event = le32_to_cpu(psspPayload->event);
1951         u32 tag = le32_to_cpu(psspPayload->tag);
1952         u32 port_id = le32_to_cpu(psspPayload->port_id);
1953         u32 dev_id = le32_to_cpu(psspPayload->device_id);
1954
1955         ccb = &pm8001_ha->ccb_info[tag];
1956         t = ccb->task;
1957         pm8001_dev = ccb->device;
1958         if (event)
1959                 PM8001_FAIL_DBG(pm8001_ha,
1960                         pm8001_printk("sas IO status 0x%x\n", event));
1961         if (unlikely(!t || !t->lldd_task || !t->dev))
1962                 return;
1963         ts = &t->task_status;
1964         PM8001_IO_DBG(pm8001_ha,
1965                 pm8001_printk("port_id = %x,device_id = %x\n",
1966                 port_id, dev_id));
1967         switch (event) {
1968         case IO_OVERFLOW:
1969                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n");)
1970                 ts->resp = SAS_TASK_COMPLETE;
1971                 ts->stat = SAS_DATA_OVERRUN;
1972                 ts->residual = 0;
1973                 if (pm8001_dev)
1974                         pm8001_dev->running_req--;
1975                 break;
1976         case IO_XFER_ERROR_BREAK:
1977                 PM8001_IO_DBG(pm8001_ha,
1978                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1979                 pm8001_handle_event(pm8001_ha, t, IO_XFER_ERROR_BREAK);
1980                 return;
1981         case IO_XFER_ERROR_PHY_NOT_READY:
1982                 PM8001_IO_DBG(pm8001_ha,
1983                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1984                 ts->resp = SAS_TASK_COMPLETE;
1985                 ts->stat = SAS_OPEN_REJECT;
1986                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1987                 break;
1988         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1989                 PM8001_IO_DBG(pm8001_ha,
1990                         pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT"
1991                         "_SUPPORTED\n"));
1992                 ts->resp = SAS_TASK_COMPLETE;
1993                 ts->stat = SAS_OPEN_REJECT;
1994                 ts->open_rej_reason = SAS_OREJ_EPROTO;
1995                 break;
1996         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1997                 PM8001_IO_DBG(pm8001_ha,
1998                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1999                 ts->resp = SAS_TASK_COMPLETE;
2000                 ts->stat = SAS_OPEN_REJECT;
2001                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2002                 break;
2003         case IO_OPEN_CNX_ERROR_BREAK:
2004                 PM8001_IO_DBG(pm8001_ha,
2005                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2006                 ts->resp = SAS_TASK_COMPLETE;
2007                 ts->stat = SAS_OPEN_REJECT;
2008                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2009                 break;
2010         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2011                 PM8001_IO_DBG(pm8001_ha,
2012                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2013                 ts->resp = SAS_TASK_COMPLETE;
2014                 ts->stat = SAS_OPEN_REJECT;
2015                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2016                 if (!t->uldd_task)
2017                         pm8001_handle_event(pm8001_ha,
2018                                 pm8001_dev,
2019                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2020                 break;
2021         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2022                 PM8001_IO_DBG(pm8001_ha,
2023                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2024                 ts->resp = SAS_TASK_COMPLETE;
2025                 ts->stat = SAS_OPEN_REJECT;
2026                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2027                 break;
2028         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2029                 PM8001_IO_DBG(pm8001_ha,
2030                         pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
2031                         "NOT_SUPPORTED\n"));
2032                 ts->resp = SAS_TASK_COMPLETE;
2033                 ts->stat = SAS_OPEN_REJECT;
2034                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2035                 break;
2036         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2037                 PM8001_IO_DBG(pm8001_ha,
2038                        pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2039                 ts->resp = SAS_TASK_COMPLETE;
2040                 ts->stat = SAS_OPEN_REJECT;
2041                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2042                 break;
2043         case IO_XFER_ERROR_NAK_RECEIVED:
2044                 PM8001_IO_DBG(pm8001_ha,
2045                         pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2046                 ts->resp = SAS_TASK_COMPLETE;
2047                 ts->stat = SAS_OPEN_REJECT;
2048                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2049                 break;
2050         case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2051                 PM8001_IO_DBG(pm8001_ha,
2052                         pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
2053                 ts->resp = SAS_TASK_COMPLETE;
2054                 ts->stat = SAS_NAK_R_ERR;
2055                 break;
2056         case IO_XFER_OPEN_RETRY_TIMEOUT:
2057                 PM8001_IO_DBG(pm8001_ha,
2058                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2059                 pm8001_handle_event(pm8001_ha, t, IO_XFER_OPEN_RETRY_TIMEOUT);
2060                 return;
2061         case IO_XFER_ERROR_UNEXPECTED_PHASE:
2062                 PM8001_IO_DBG(pm8001_ha,
2063                         pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
2064                 ts->resp = SAS_TASK_COMPLETE;
2065                 ts->stat = SAS_DATA_OVERRUN;
2066                 break;
2067         case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2068                 PM8001_IO_DBG(pm8001_ha,
2069                         pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
2070                 ts->resp = SAS_TASK_COMPLETE;
2071                 ts->stat = SAS_DATA_OVERRUN;
2072                 break;
2073         case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2074                 PM8001_IO_DBG(pm8001_ha,
2075                        pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
2076                 ts->resp = SAS_TASK_COMPLETE;
2077                 ts->stat = SAS_DATA_OVERRUN;
2078                 break;
2079         case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT:
2080                 PM8001_IO_DBG(pm8001_ha,
2081                 pm8001_printk("IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n"));
2082                 ts->resp = SAS_TASK_COMPLETE;
2083                 ts->stat = SAS_DATA_OVERRUN;
2084                 break;
2085         case IO_XFER_ERROR_OFFSET_MISMATCH:
2086                 PM8001_IO_DBG(pm8001_ha,
2087                         pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
2088                 ts->resp = SAS_TASK_COMPLETE;
2089                 ts->stat = SAS_DATA_OVERRUN;
2090                 break;
2091         case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2092                 PM8001_IO_DBG(pm8001_ha,
2093                         pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
2094                 ts->resp = SAS_TASK_COMPLETE;
2095                 ts->stat = SAS_DATA_OVERRUN;
2096                 break;
2097         case IO_XFER_CMD_FRAME_ISSUED:
2098                 PM8001_IO_DBG(pm8001_ha,
2099                         pm8001_printk("  IO_XFER_CMD_FRAME_ISSUED\n"));
2100                 return;
2101         default:
2102                 PM8001_IO_DBG(pm8001_ha,
2103                         pm8001_printk("Unknown status 0x%x\n", event));
2104                 /* not allowed case. Therefore, return failed status */
2105                 ts->resp = SAS_TASK_COMPLETE;
2106                 ts->stat = SAS_DATA_OVERRUN;
2107                 break;
2108         }
2109         spin_lock_irqsave(&t->task_state_lock, flags);
2110         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2111         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2112         t->task_state_flags |= SAS_TASK_STATE_DONE;
2113         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2114                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2115                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with"
2116                         " event 0x%x resp 0x%x "
2117                         "stat 0x%x but aborted by upper layer!\n",
2118                         t, event, ts->resp, ts->stat));
2119                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2120         } else {
2121                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2122                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2123                 mb();/* in order to force CPU ordering */
2124                 t->task_done(t);
2125         }
2126 }
2127
2128 /*See the comments for mpi_ssp_completion */
2129 static void
2130 mpi_sata_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2131 {
2132         struct sas_task *t;
2133         struct pm8001_ccb_info *ccb;
2134         u32 param;
2135         u32 status;
2136         u32 tag;
2137         struct sata_completion_resp *psataPayload;
2138         struct task_status_struct *ts;
2139         struct ata_task_resp *resp ;
2140         u32 *sata_resp;
2141         struct pm8001_device *pm8001_dev;
2142         unsigned long flags;
2143
2144         psataPayload = (struct sata_completion_resp *)(piomb + 4);
2145         status = le32_to_cpu(psataPayload->status);
2146         tag = le32_to_cpu(psataPayload->tag);
2147
2148         ccb = &pm8001_ha->ccb_info[tag];
2149         param = le32_to_cpu(psataPayload->param);
2150         t = ccb->task;
2151         ts = &t->task_status;
2152         pm8001_dev = ccb->device;
2153         if (status)
2154                 PM8001_FAIL_DBG(pm8001_ha,
2155                         pm8001_printk("sata IO status 0x%x\n", status));
2156         if (unlikely(!t || !t->lldd_task || !t->dev))
2157                 return;
2158
2159         switch (status) {
2160         case IO_SUCCESS:
2161                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
2162                 if (param == 0) {
2163                         ts->resp = SAS_TASK_COMPLETE;
2164                         ts->stat = SAM_STAT_GOOD;
2165                 } else {
2166                         u8 len;
2167                         ts->resp = SAS_TASK_COMPLETE;
2168                         ts->stat = SAS_PROTO_RESPONSE;
2169                         ts->residual = param;
2170                         PM8001_IO_DBG(pm8001_ha,
2171                                 pm8001_printk("SAS_PROTO_RESPONSE len = %d\n",
2172                                 param));
2173                         sata_resp = &psataPayload->sata_resp[0];
2174                         resp = (struct ata_task_resp *)ts->buf;
2175                         if (t->ata_task.dma_xfer == 0 &&
2176                         t->data_dir == PCI_DMA_FROMDEVICE) {
2177                                 len = sizeof(struct pio_setup_fis);
2178                                 PM8001_IO_DBG(pm8001_ha,
2179                                 pm8001_printk("PIO read len = %d\n", len));
2180                         } else if (t->ata_task.use_ncq) {
2181                                 len = sizeof(struct set_dev_bits_fis);
2182                                 PM8001_IO_DBG(pm8001_ha,
2183                                         pm8001_printk("FPDMA len = %d\n", len));
2184                         } else {
2185                                 len = sizeof(struct dev_to_host_fis);
2186                                 PM8001_IO_DBG(pm8001_ha,
2187                                 pm8001_printk("other len = %d\n", len));
2188                         }
2189                         if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) {
2190                                 resp->frame_len = len;
2191                                 memcpy(&resp->ending_fis[0], sata_resp, len);
2192                                 ts->buf_valid_size = sizeof(*resp);
2193                         } else
2194                                 PM8001_IO_DBG(pm8001_ha,
2195                                         pm8001_printk("response to large\n"));
2196                 }
2197                 if (pm8001_dev)
2198                         pm8001_dev->running_req--;
2199                 break;
2200         case IO_ABORTED:
2201                 PM8001_IO_DBG(pm8001_ha,
2202                         pm8001_printk("IO_ABORTED IOMB Tag\n"));
2203                 ts->resp = SAS_TASK_COMPLETE;
2204                 ts->stat = SAS_ABORTED_TASK;
2205                 if (pm8001_dev)
2206                         pm8001_dev->running_req--;
2207                 break;
2208                 /* following cases are to do cases */
2209         case IO_UNDERFLOW:
2210                 /* SATA Completion with error */
2211                 PM8001_IO_DBG(pm8001_ha,
2212                         pm8001_printk("IO_UNDERFLOW param = %d\n", param));
2213                 ts->resp = SAS_TASK_COMPLETE;
2214                 ts->stat = SAS_DATA_UNDERRUN;
2215                 ts->residual =  param;
2216                 if (pm8001_dev)
2217                         pm8001_dev->running_req--;
2218                 break;
2219         case IO_NO_DEVICE:
2220                 PM8001_IO_DBG(pm8001_ha,
2221                         pm8001_printk("IO_NO_DEVICE\n"));
2222                 ts->resp = SAS_TASK_UNDELIVERED;
2223                 ts->stat = SAS_PHY_DOWN;
2224                 break;
2225         case IO_XFER_ERROR_BREAK:
2226                 PM8001_IO_DBG(pm8001_ha,
2227                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2228                 ts->resp = SAS_TASK_COMPLETE;
2229                 ts->stat = SAS_INTERRUPTED;
2230                 break;
2231         case IO_XFER_ERROR_PHY_NOT_READY:
2232                 PM8001_IO_DBG(pm8001_ha,
2233                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2234                 ts->resp = SAS_TASK_COMPLETE;
2235                 ts->stat = SAS_OPEN_REJECT;
2236                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2237                 break;
2238         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2239                 PM8001_IO_DBG(pm8001_ha,
2240                         pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT"
2241                         "_SUPPORTED\n"));
2242                 ts->resp = SAS_TASK_COMPLETE;
2243                 ts->stat = SAS_OPEN_REJECT;
2244                 ts->open_rej_reason = SAS_OREJ_EPROTO;
2245                 break;
2246         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2247                 PM8001_IO_DBG(pm8001_ha,
2248                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2249                 ts->resp = SAS_TASK_COMPLETE;
2250                 ts->stat = SAS_OPEN_REJECT;
2251                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2252                 break;
2253         case IO_OPEN_CNX_ERROR_BREAK:
2254                 PM8001_IO_DBG(pm8001_ha,
2255                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2256                 ts->resp = SAS_TASK_COMPLETE;
2257                 ts->stat = SAS_OPEN_REJECT;
2258                 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2259                 break;
2260         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2261                 PM8001_IO_DBG(pm8001_ha,
2262                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2263                 ts->resp = SAS_TASK_COMPLETE;
2264                 ts->stat = SAS_DEV_NO_RESPONSE;
2265                 if (!t->uldd_task) {
2266                         pm8001_handle_event(pm8001_ha,
2267                                 pm8001_dev,
2268                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2269                         ts->resp = SAS_TASK_UNDELIVERED;
2270                         ts->stat = SAS_QUEUE_FULL;
2271                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2272                         mb();/*in order to force CPU ordering*/
2273                         spin_unlock_irq(&pm8001_ha->lock);
2274                         t->task_done(t);
2275                         spin_lock_irq(&pm8001_ha->lock);
2276                         return;
2277                 }
2278                 break;
2279         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2280                 PM8001_IO_DBG(pm8001_ha,
2281                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2282                 ts->resp = SAS_TASK_UNDELIVERED;
2283                 ts->stat = SAS_OPEN_REJECT;
2284                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2285                 if (!t->uldd_task) {
2286                         pm8001_handle_event(pm8001_ha,
2287                                 pm8001_dev,
2288                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2289                         ts->resp = SAS_TASK_UNDELIVERED;
2290                         ts->stat = SAS_QUEUE_FULL;
2291                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2292                         mb();/*ditto*/
2293                         spin_unlock_irq(&pm8001_ha->lock);
2294                         t->task_done(t);
2295                         spin_lock_irq(&pm8001_ha->lock);
2296                         return;
2297                 }
2298                 break;
2299         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2300                 PM8001_IO_DBG(pm8001_ha,
2301                         pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
2302                         "NOT_SUPPORTED\n"));
2303                 ts->resp = SAS_TASK_COMPLETE;
2304                 ts->stat = SAS_OPEN_REJECT;
2305                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2306                 break;
2307         case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
2308                 PM8001_IO_DBG(pm8001_ha,
2309                         pm8001_printk("IO_OPEN_CNX_ERROR_STP_RESOURCES"
2310                         "_BUSY\n"));
2311                 ts->resp = SAS_TASK_COMPLETE;
2312                 ts->stat = SAS_DEV_NO_RESPONSE;
2313                 if (!t->uldd_task) {
2314                         pm8001_handle_event(pm8001_ha,
2315                                 pm8001_dev,
2316                                 IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY);
2317                         ts->resp = SAS_TASK_UNDELIVERED;
2318                         ts->stat = SAS_QUEUE_FULL;
2319                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2320                         mb();/* ditto*/
2321                         spin_unlock_irq(&pm8001_ha->lock);
2322                         t->task_done(t);
2323                         spin_lock_irq(&pm8001_ha->lock);
2324                         return;
2325                 }
2326                 break;
2327         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2328                 PM8001_IO_DBG(pm8001_ha,
2329                        pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2330                 ts->resp = SAS_TASK_COMPLETE;
2331                 ts->stat = SAS_OPEN_REJECT;
2332                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2333                 break;
2334         case IO_XFER_ERROR_NAK_RECEIVED:
2335                 PM8001_IO_DBG(pm8001_ha,
2336                         pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2337                 ts->resp = SAS_TASK_COMPLETE;
2338                 ts->stat = SAS_NAK_R_ERR;
2339                 break;
2340         case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2341                 PM8001_IO_DBG(pm8001_ha,
2342                         pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
2343                 ts->resp = SAS_TASK_COMPLETE;
2344                 ts->stat = SAS_NAK_R_ERR;
2345                 break;
2346         case IO_XFER_ERROR_DMA:
2347                 PM8001_IO_DBG(pm8001_ha,
2348                         pm8001_printk("IO_XFER_ERROR_DMA\n"));
2349                 ts->resp = SAS_TASK_COMPLETE;
2350                 ts->stat = SAS_ABORTED_TASK;
2351                 break;
2352         case IO_XFER_ERROR_SATA_LINK_TIMEOUT:
2353                 PM8001_IO_DBG(pm8001_ha,
2354                         pm8001_printk("IO_XFER_ERROR_SATA_LINK_TIMEOUT\n"));
2355                 ts->resp = SAS_TASK_UNDELIVERED;
2356                 ts->stat = SAS_DEV_NO_RESPONSE;
2357                 break;
2358         case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2359                 PM8001_IO_DBG(pm8001_ha,
2360                         pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
2361                 ts->resp = SAS_TASK_COMPLETE;
2362                 ts->stat = SAS_DATA_UNDERRUN;
2363                 break;
2364         case IO_XFER_OPEN_RETRY_TIMEOUT:
2365                 PM8001_IO_DBG(pm8001_ha,
2366                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2367                 ts->resp = SAS_TASK_COMPLETE;
2368                 ts->stat = SAS_OPEN_TO;
2369                 break;
2370         case IO_PORT_IN_RESET:
2371                 PM8001_IO_DBG(pm8001_ha,
2372                         pm8001_printk("IO_PORT_IN_RESET\n"));
2373                 ts->resp = SAS_TASK_COMPLETE;
2374                 ts->stat = SAS_DEV_NO_RESPONSE;
2375                 break;
2376         case IO_DS_NON_OPERATIONAL:
2377                 PM8001_IO_DBG(pm8001_ha,
2378                         pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
2379                 ts->resp = SAS_TASK_COMPLETE;
2380                 ts->stat = SAS_DEV_NO_RESPONSE;
2381                 if (!t->uldd_task) {
2382                         pm8001_handle_event(pm8001_ha, pm8001_dev,
2383                                     IO_DS_NON_OPERATIONAL);
2384                         ts->resp = SAS_TASK_UNDELIVERED;
2385                         ts->stat = SAS_QUEUE_FULL;
2386                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2387                         mb();/*ditto*/
2388                         spin_unlock_irq(&pm8001_ha->lock);
2389                         t->task_done(t);
2390                         spin_lock_irq(&pm8001_ha->lock);
2391                         return;
2392                 }
2393                 break;
2394         case IO_DS_IN_RECOVERY:
2395                 PM8001_IO_DBG(pm8001_ha,
2396                         pm8001_printk("  IO_DS_IN_RECOVERY\n"));
2397                 ts->resp = SAS_TASK_COMPLETE;
2398                 ts->stat = SAS_DEV_NO_RESPONSE;
2399                 break;
2400         case IO_DS_IN_ERROR:
2401                 PM8001_IO_DBG(pm8001_ha,
2402                         pm8001_printk("IO_DS_IN_ERROR\n"));
2403                 ts->resp = SAS_TASK_COMPLETE;
2404                 ts->stat = SAS_DEV_NO_RESPONSE;
2405                 if (!t->uldd_task) {
2406                         pm8001_handle_event(pm8001_ha, pm8001_dev,
2407                                     IO_DS_IN_ERROR);
2408                         ts->resp = SAS_TASK_UNDELIVERED;
2409                         ts->stat = SAS_QUEUE_FULL;
2410                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2411                         mb();/*ditto*/
2412                         spin_unlock_irq(&pm8001_ha->lock);
2413                         t->task_done(t);
2414                         spin_lock_irq(&pm8001_ha->lock);
2415                         return;
2416                 }
2417                 break;
2418         case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2419                 PM8001_IO_DBG(pm8001_ha,
2420                         pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
2421                 ts->resp = SAS_TASK_COMPLETE;
2422                 ts->stat = SAS_OPEN_REJECT;
2423                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2424         default:
2425                 PM8001_IO_DBG(pm8001_ha,
2426                         pm8001_printk("Unknown status 0x%x\n", status));
2427                 /* not allowed case. Therefore, return failed status */
2428                 ts->resp = SAS_TASK_COMPLETE;
2429                 ts->stat = SAS_DEV_NO_RESPONSE;
2430                 break;
2431         }
2432         spin_lock_irqsave(&t->task_state_lock, flags);
2433         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2434         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2435         t->task_state_flags |= SAS_TASK_STATE_DONE;
2436         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2437                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2438                 PM8001_FAIL_DBG(pm8001_ha,
2439                         pm8001_printk("task 0x%p done with io_status 0x%x"
2440                         " resp 0x%x stat 0x%x but aborted by upper layer!\n",
2441                         t, status, ts->resp, ts->stat));
2442                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2443         } else if (t->uldd_task) {
2444                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2445                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2446                 mb();/* ditto */
2447                 spin_unlock_irq(&pm8001_ha->lock);
2448                 t->task_done(t);
2449                 spin_lock_irq(&pm8001_ha->lock);
2450         } else if (!t->uldd_task) {
2451                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2452                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2453                 mb();/*ditto*/
2454                 spin_unlock_irq(&pm8001_ha->lock);
2455                 t->task_done(t);
2456                 spin_lock_irq(&pm8001_ha->lock);
2457         }
2458 }
2459
2460 /*See the comments for mpi_ssp_completion */
2461 static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
2462 {
2463         struct sas_task *t;
2464         struct task_status_struct *ts;
2465         struct pm8001_ccb_info *ccb;
2466         struct pm8001_device *pm8001_dev;
2467         struct sata_event_resp *psataPayload =
2468                 (struct sata_event_resp *)(piomb + 4);
2469         u32 event = le32_to_cpu(psataPayload->event);
2470         u32 tag = le32_to_cpu(psataPayload->tag);
2471         u32 port_id = le32_to_cpu(psataPayload->port_id);
2472         u32 dev_id = le32_to_cpu(psataPayload->device_id);
2473         unsigned long flags;
2474
2475         ccb = &pm8001_ha->ccb_info[tag];
2476         t = ccb->task;
2477         pm8001_dev = ccb->device;
2478         if (event)
2479                 PM8001_FAIL_DBG(pm8001_ha,
2480                         pm8001_printk("sata IO status 0x%x\n", event));
2481         if (unlikely(!t || !t->lldd_task || !t->dev))
2482                 return;
2483         ts = &t->task_status;
2484         PM8001_IO_DBG(pm8001_ha,
2485                 pm8001_printk("port_id = %x,device_id = %x\n",
2486                 port_id, dev_id));
2487         switch (event) {
2488         case IO_OVERFLOW:
2489                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
2490                 ts->resp = SAS_TASK_COMPLETE;
2491                 ts->stat = SAS_DATA_OVERRUN;
2492                 ts->residual = 0;
2493                 if (pm8001_dev)
2494                         pm8001_dev->running_req--;
2495                 break;
2496         case IO_XFER_ERROR_BREAK:
2497                 PM8001_IO_DBG(pm8001_ha,
2498                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2499                 ts->resp = SAS_TASK_COMPLETE;
2500                 ts->stat = SAS_INTERRUPTED;
2501                 break;
2502         case IO_XFER_ERROR_PHY_NOT_READY:
2503                 PM8001_IO_DBG(pm8001_ha,
2504                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2505                 ts->resp = SAS_TASK_COMPLETE;
2506                 ts->stat = SAS_OPEN_REJECT;
2507                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2508                 break;
2509         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2510                 PM8001_IO_DBG(pm8001_ha,
2511                         pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT"
2512                         "_SUPPORTED\n"));
2513                 ts->resp = SAS_TASK_COMPLETE;
2514                 ts->stat = SAS_OPEN_REJECT;
2515                 ts->open_rej_reason = SAS_OREJ_EPROTO;
2516                 break;
2517         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2518                 PM8001_IO_DBG(pm8001_ha,
2519                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2520                 ts->resp = SAS_TASK_COMPLETE;
2521                 ts->stat = SAS_OPEN_REJECT;
2522                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2523                 break;
2524         case IO_OPEN_CNX_ERROR_BREAK:
2525                 PM8001_IO_DBG(pm8001_ha,
2526                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2527                 ts->resp = SAS_TASK_COMPLETE;
2528                 ts->stat = SAS_OPEN_REJECT;
2529                 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2530                 break;
2531         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2532                 PM8001_IO_DBG(pm8001_ha,
2533                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2534                 ts->resp = SAS_TASK_UNDELIVERED;
2535                 ts->stat = SAS_DEV_NO_RESPONSE;
2536                 if (!t->uldd_task) {
2537                         pm8001_handle_event(pm8001_ha,
2538                                 pm8001_dev,
2539                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2540                         ts->resp = SAS_TASK_COMPLETE;
2541                         ts->stat = SAS_QUEUE_FULL;
2542                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2543                         mb();/*ditto*/
2544                         spin_unlock_irq(&pm8001_ha->lock);
2545                         t->task_done(t);
2546                         spin_lock_irq(&pm8001_ha->lock);
2547                         return;
2548                 }
2549                 break;
2550         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2551                 PM8001_IO_DBG(pm8001_ha,
2552                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2553                 ts->resp = SAS_TASK_UNDELIVERED;
2554                 ts->stat = SAS_OPEN_REJECT;
2555                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2556                 break;
2557         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2558                 PM8001_IO_DBG(pm8001_ha,
2559                         pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
2560                         "NOT_SUPPORTED\n"));
2561                 ts->resp = SAS_TASK_COMPLETE;
2562                 ts->stat = SAS_OPEN_REJECT;
2563                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2564                 break;
2565         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2566                 PM8001_IO_DBG(pm8001_ha,
2567                        pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2568                 ts->resp = SAS_TASK_COMPLETE;
2569                 ts->stat = SAS_OPEN_REJECT;
2570                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2571                 break;
2572         case IO_XFER_ERROR_NAK_RECEIVED:
2573                 PM8001_IO_DBG(pm8001_ha,
2574                         pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2575                 ts->resp = SAS_TASK_COMPLETE;
2576                 ts->stat = SAS_NAK_R_ERR;
2577                 break;
2578         case IO_XFER_ERROR_PEER_ABORTED:
2579                 PM8001_IO_DBG(pm8001_ha,
2580                         pm8001_printk("IO_XFER_ERROR_PEER_ABORTED\n"));
2581                 ts->resp = SAS_TASK_COMPLETE;
2582                 ts->stat = SAS_NAK_R_ERR;
2583                 break;
2584         case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2585                 PM8001_IO_DBG(pm8001_ha,
2586                         pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
2587                 ts->resp = SAS_TASK_COMPLETE;
2588                 ts->stat = SAS_DATA_UNDERRUN;
2589                 break;
2590         case IO_XFER_OPEN_RETRY_TIMEOUT:
2591                 PM8001_IO_DBG(pm8001_ha,
2592                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2593                 ts->resp = SAS_TASK_COMPLETE;
2594                 ts->stat = SAS_OPEN_TO;
2595                 break;
2596         case IO_XFER_ERROR_UNEXPECTED_PHASE:
2597                 PM8001_IO_DBG(pm8001_ha,
2598                         pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
2599                 ts->resp = SAS_TASK_COMPLETE;
2600                 ts->stat = SAS_OPEN_TO;
2601                 break;
2602         case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2603                 PM8001_IO_DBG(pm8001_ha,
2604                         pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
2605                 ts->resp = SAS_TASK_COMPLETE;
2606                 ts->stat = SAS_OPEN_TO;
2607                 break;
2608         case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2609                 PM8001_IO_DBG(pm8001_ha,
2610                        pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
2611                 ts->resp = SAS_TASK_COMPLETE;
2612                 ts->stat = SAS_OPEN_TO;
2613                 break;
2614         case IO_XFER_ERROR_OFFSET_MISMATCH:
2615                 PM8001_IO_DBG(pm8001_ha,
2616                         pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
2617                 ts->resp = SAS_TASK_COMPLETE;
2618                 ts->stat = SAS_OPEN_TO;
2619                 break;
2620         case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2621                 PM8001_IO_DBG(pm8001_ha,
2622                         pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
2623                 ts->resp = SAS_TASK_COMPLETE;
2624                 ts->stat = SAS_OPEN_TO;
2625                 break;
2626         case IO_XFER_CMD_FRAME_ISSUED:
2627                 PM8001_IO_DBG(pm8001_ha,
2628                         pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n"));
2629                 break;
2630         case IO_XFER_PIO_SETUP_ERROR:
2631                 PM8001_IO_DBG(pm8001_ha,
2632                         pm8001_printk("IO_XFER_PIO_SETUP_ERROR\n"));
2633                 ts->resp = SAS_TASK_COMPLETE;
2634                 ts->stat = SAS_OPEN_TO;
2635                 break;
2636         default:
2637                 PM8001_IO_DBG(pm8001_ha,
2638                         pm8001_printk("Unknown status 0x%x\n", event));
2639                 /* not allowed case. Therefore, return failed status */
2640                 ts->resp = SAS_TASK_COMPLETE;
2641                 ts->stat = SAS_OPEN_TO;
2642                 break;
2643         }
2644         spin_lock_irqsave(&t->task_state_lock, flags);
2645         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2646         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2647         t->task_state_flags |= SAS_TASK_STATE_DONE;
2648         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2649                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2650                 PM8001_FAIL_DBG(pm8001_ha,
2651                         pm8001_printk("task 0x%p done with io_status 0x%x"
2652                         " resp 0x%x stat 0x%x but aborted by upper layer!\n",
2653                         t, event, ts->resp, ts->stat));
2654                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2655         } else if (t->uldd_task) {
2656                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2657                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2658                 mb();/* ditto */
2659                 spin_unlock_irq(&pm8001_ha->lock);
2660                 t->task_done(t);
2661                 spin_lock_irq(&pm8001_ha->lock);
2662         } else if (!t->uldd_task) {
2663                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2664                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2665                 mb();/*ditto*/
2666                 spin_unlock_irq(&pm8001_ha->lock);
2667                 t->task_done(t);
2668                 spin_lock_irq(&pm8001_ha->lock);
2669         }
2670 }
2671
2672 /*See the comments for mpi_ssp_completion */
2673 static void
2674 mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2675 {
2676         u32 param;
2677         struct sas_task *t;
2678         struct pm8001_ccb_info *ccb;
2679         unsigned long flags;
2680         u32 status;
2681         u32 tag;
2682         struct smp_completion_resp *psmpPayload;
2683         struct task_status_struct *ts;
2684         struct pm8001_device *pm8001_dev;
2685
2686         psmpPayload = (struct smp_completion_resp *)(piomb + 4);
2687         status = le32_to_cpu(psmpPayload->status);
2688         tag = le32_to_cpu(psmpPayload->tag);
2689
2690         ccb = &pm8001_ha->ccb_info[tag];
2691         param = le32_to_cpu(psmpPayload->param);
2692         t = ccb->task;
2693         ts = &t->task_status;
2694         pm8001_dev = ccb->device;
2695         if (status)
2696                 PM8001_FAIL_DBG(pm8001_ha,
2697                         pm8001_printk("smp IO status 0x%x\n", status));
2698         if (unlikely(!t || !t->lldd_task || !t->dev))
2699                 return;
2700
2701         switch (status) {
2702         case IO_SUCCESS:
2703                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
2704                 ts->resp = SAS_TASK_COMPLETE;
2705                 ts->stat = SAM_STAT_GOOD;
2706         if (pm8001_dev)
2707                         pm8001_dev->running_req--;
2708                 break;
2709         case IO_ABORTED:
2710                 PM8001_IO_DBG(pm8001_ha,
2711                         pm8001_printk("IO_ABORTED IOMB\n"));
2712                 ts->resp = SAS_TASK_COMPLETE;
2713                 ts->stat = SAS_ABORTED_TASK;
2714                 if (pm8001_dev)
2715                         pm8001_dev->running_req--;
2716                 break;
2717         case IO_OVERFLOW:
2718                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
2719                 ts->resp = SAS_TASK_COMPLETE;
2720                 ts->stat = SAS_DATA_OVERRUN;
2721                 ts->residual = 0;
2722                 if (pm8001_dev)
2723                         pm8001_dev->running_req--;
2724                 break;
2725         case IO_NO_DEVICE:
2726                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_NO_DEVICE\n"));
2727                 ts->resp = SAS_TASK_COMPLETE;
2728                 ts->stat = SAS_PHY_DOWN;
2729                 break;
2730         case IO_ERROR_HW_TIMEOUT:
2731                 PM8001_IO_DBG(pm8001_ha,
2732                         pm8001_printk("IO_ERROR_HW_TIMEOUT\n"));
2733                 ts->resp = SAS_TASK_COMPLETE;
2734                 ts->stat = SAM_STAT_BUSY;
2735                 break;
2736         case IO_XFER_ERROR_BREAK:
2737                 PM8001_IO_DBG(pm8001_ha,
2738                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2739                 ts->resp = SAS_TASK_COMPLETE;
2740                 ts->stat = SAM_STAT_BUSY;
2741                 break;
2742         case IO_XFER_ERROR_PHY_NOT_READY:
2743                 PM8001_IO_DBG(pm8001_ha,
2744                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2745                 ts->resp = SAS_TASK_COMPLETE;
2746                 ts->stat = SAM_STAT_BUSY;
2747                 break;
2748         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2749                 PM8001_IO_DBG(pm8001_ha,
2750                 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
2751                 ts->resp = SAS_TASK_COMPLETE;
2752                 ts->stat = SAS_OPEN_REJECT;
2753                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2754                 break;
2755         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2756                 PM8001_IO_DBG(pm8001_ha,
2757                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2758                 ts->resp = SAS_TASK_COMPLETE;
2759                 ts->stat = SAS_OPEN_REJECT;
2760                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2761                 break;
2762         case IO_OPEN_CNX_ERROR_BREAK:
2763                 PM8001_IO_DBG(pm8001_ha,
2764                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2765                 ts->resp = SAS_TASK_COMPLETE;
2766                 ts->stat = SAS_OPEN_REJECT;
2767                 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2768                 break;
2769         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2770                 PM8001_IO_DBG(pm8001_ha,
2771                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2772                 ts->resp = SAS_TASK_COMPLETE;
2773                 ts->stat = SAS_OPEN_REJECT;
2774                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2775                 pm8001_handle_event(pm8001_ha,
2776                                 pm8001_dev,
2777                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2778                 break;
2779         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2780                 PM8001_IO_DBG(pm8001_ha,
2781                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2782                 ts->resp = SAS_TASK_COMPLETE;
2783                 ts->stat = SAS_OPEN_REJECT;
2784                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2785                 break;
2786         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2787                 PM8001_IO_DBG(pm8001_ha,
2788                         pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
2789                         "NOT_SUPPORTED\n"));
2790                 ts->resp = SAS_TASK_COMPLETE;
2791                 ts->stat = SAS_OPEN_REJECT;
2792                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2793                 break;
2794         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2795                 PM8001_IO_DBG(pm8001_ha,
2796                        pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2797                 ts->resp = SAS_TASK_COMPLETE;
2798                 ts->stat = SAS_OPEN_REJECT;
2799                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2800                 break;
2801         case IO_XFER_ERROR_RX_FRAME:
2802                 PM8001_IO_DBG(pm8001_ha,
2803                         pm8001_printk("IO_XFER_ERROR_RX_FRAME\n"));
2804                 ts->resp = SAS_TASK_COMPLETE;
2805                 ts->stat = SAS_DEV_NO_RESPONSE;
2806                 break;
2807         case IO_XFER_OPEN_RETRY_TIMEOUT:
2808                 PM8001_IO_DBG(pm8001_ha,
2809                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2810                 ts->resp = SAS_TASK_COMPLETE;
2811                 ts->stat = SAS_OPEN_REJECT;
2812                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2813                 break;
2814         case IO_ERROR_INTERNAL_SMP_RESOURCE:
2815                 PM8001_IO_DBG(pm8001_ha,
2816                         pm8001_printk("IO_ERROR_INTERNAL_SMP_RESOURCE\n"));
2817                 ts->resp = SAS_TASK_COMPLETE;
2818                 ts->stat = SAS_QUEUE_FULL;
2819                 break;
2820         case IO_PORT_IN_RESET:
2821                 PM8001_IO_DBG(pm8001_ha,
2822                         pm8001_printk("IO_PORT_IN_RESET\n"));
2823                 ts->resp = SAS_TASK_COMPLETE;
2824                 ts->stat = SAS_OPEN_REJECT;
2825                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2826                 break;
2827         case IO_DS_NON_OPERATIONAL:
2828                 PM8001_IO_DBG(pm8001_ha,
2829                         pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
2830                 ts->resp = SAS_TASK_COMPLETE;
2831                 ts->stat = SAS_DEV_NO_RESPONSE;
2832                 break;
2833         case IO_DS_IN_RECOVERY:
2834                 PM8001_IO_DBG(pm8001_ha,
2835                         pm8001_printk("IO_DS_IN_RECOVERY\n"));
2836                 ts->resp = SAS_TASK_COMPLETE;
2837                 ts->stat = SAS_OPEN_REJECT;
2838                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2839                 break;
2840         case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2841                 PM8001_IO_DBG(pm8001_ha,
2842                         pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
2843                 ts->resp = SAS_TASK_COMPLETE;
2844                 ts->stat = SAS_OPEN_REJECT;
2845                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2846                 break;
2847         default:
2848                 PM8001_IO_DBG(pm8001_ha,
2849                         pm8001_printk("Unknown status 0x%x\n", status));
2850                 ts->resp = SAS_TASK_COMPLETE;
2851                 ts->stat = SAS_DEV_NO_RESPONSE;
2852                 /* not allowed case. Therefore, return failed status */
2853                 break;
2854         }
2855         spin_lock_irqsave(&t->task_state_lock, flags);
2856         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2857         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2858         t->task_state_flags |= SAS_TASK_STATE_DONE;
2859         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2860                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2861                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with"
2862                         " io_status 0x%x resp 0x%x "
2863                         "stat 0x%x but aborted by upper layer!\n",
2864                         t, status, ts->resp, ts->stat));
2865                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2866         } else {
2867                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2868                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2869                 mb();/* in order to force CPU ordering */
2870                 t->task_done(t);
2871         }
2872 }
2873
2874 void pm8001_mpi_set_dev_state_resp(struct pm8001_hba_info *pm8001_ha,
2875                 void *piomb)
2876 {
2877         struct set_dev_state_resp *pPayload =
2878                 (struct set_dev_state_resp *)(piomb + 4);
2879         u32 tag = le32_to_cpu(pPayload->tag);
2880         struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
2881         struct pm8001_device *pm8001_dev = ccb->device;
2882         u32 status = le32_to_cpu(pPayload->status);
2883         u32 device_id = le32_to_cpu(pPayload->device_id);
2884         u8 pds = le32_to_cpu(pPayload->pds_nds) | PDS_BITS;
2885         u8 nds = le32_to_cpu(pPayload->pds_nds) | NDS_BITS;
2886         PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Set device id = 0x%x state "
2887                 "from 0x%x to 0x%x status = 0x%x!\n",
2888                 device_id, pds, nds, status));
2889         complete(pm8001_dev->setds_completion);
2890         ccb->task = NULL;
2891         ccb->ccb_tag = 0xFFFFFFFF;
2892         pm8001_ccb_free(pm8001_ha, tag);
2893 }
2894
2895 void pm8001_mpi_set_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
2896 {
2897         struct get_nvm_data_resp *pPayload =
2898                 (struct get_nvm_data_resp *)(piomb + 4);
2899         u32 tag = le32_to_cpu(pPayload->tag);
2900         struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
2901         u32 dlen_status = le32_to_cpu(pPayload->dlen_status);
2902         complete(pm8001_ha->nvmd_completion);
2903         PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Set nvm data complete!\n"));
2904         if ((dlen_status & NVMD_STAT) != 0) {
2905                 PM8001_FAIL_DBG(pm8001_ha,
2906                         pm8001_printk("Set nvm data error!\n"));
2907                 return;
2908         }
2909         ccb->task = NULL;
2910         ccb->ccb_tag = 0xFFFFFFFF;
2911         pm8001_ccb_free(pm8001_ha, tag);
2912 }
2913
2914 void
2915 pm8001_mpi_get_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
2916 {
2917         struct fw_control_ex    *fw_control_context;
2918         struct get_nvm_data_resp *pPayload =
2919                 (struct get_nvm_data_resp *)(piomb + 4);
2920         u32 tag = le32_to_cpu(pPayload->tag);
2921         struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
2922         u32 dlen_status = le32_to_cpu(pPayload->dlen_status);
2923         u32 ir_tds_bn_dps_das_nvm =
2924                 le32_to_cpu(pPayload->ir_tda_bn_dps_das_nvm);
2925         void *virt_addr = pm8001_ha->memoryMap.region[NVMD].virt_ptr;
2926         fw_control_context = ccb->fw_control_context;
2927
2928         PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Get nvm data complete!\n"));
2929         if ((dlen_status & NVMD_STAT) != 0) {
2930                 PM8001_FAIL_DBG(pm8001_ha,
2931                         pm8001_printk("Get nvm data error!\n"));
2932                 complete(pm8001_ha->nvmd_completion);
2933                 return;
2934         }
2935
2936         if (ir_tds_bn_dps_das_nvm & IPMode) {
2937                 /* indirect mode - IR bit set */
2938                 PM8001_MSG_DBG(pm8001_ha,
2939                         pm8001_printk("Get NVMD success, IR=1\n"));
2940                 if ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == TWI_DEVICE) {
2941                         if (ir_tds_bn_dps_das_nvm == 0x80a80200) {
2942                                 memcpy(pm8001_ha->sas_addr,
2943                                       ((u8 *)virt_addr + 4),
2944                                        SAS_ADDR_SIZE);
2945                                 PM8001_MSG_DBG(pm8001_ha,
2946                                         pm8001_printk("Get SAS address"
2947                                         " from VPD successfully!\n"));
2948                         }
2949                 } else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == C_SEEPROM)
2950                         || ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == VPD_FLASH) ||
2951                         ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == EXPAN_ROM)) {
2952                                 ;
2953                 } else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == AAP1_RDUMP)
2954                         || ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == IOP_RDUMP)) {
2955                         ;
2956                 } else {
2957                         /* Should not be happened*/
2958                         PM8001_MSG_DBG(pm8001_ha,
2959                                 pm8001_printk("(IR=1)Wrong Device type 0x%x\n",
2960                                 ir_tds_bn_dps_das_nvm));
2961                 }
2962         } else /* direct mode */{
2963                 PM8001_MSG_DBG(pm8001_ha,
2964                         pm8001_printk("Get NVMD success, IR=0, dataLen=%d\n",
2965                         (dlen_status & NVMD_LEN) >> 24));
2966         }
2967         memcpy(fw_control_context->usrAddr,
2968                 pm8001_ha->memoryMap.region[NVMD].virt_ptr,
2969                 fw_control_context->len);
2970         complete(pm8001_ha->nvmd_completion);
2971         ccb->task = NULL;
2972         ccb->ccb_tag = 0xFFFFFFFF;
2973         pm8001_ccb_free(pm8001_ha, tag);
2974 }
2975
2976 int pm8001_mpi_local_phy_ctl(struct pm8001_hba_info *pm8001_ha, void *piomb)
2977 {
2978         struct local_phy_ctl_resp *pPayload =
2979                 (struct local_phy_ctl_resp *)(piomb + 4);
2980         u32 status = le32_to_cpu(pPayload->status);
2981         u32 phy_id = le32_to_cpu(pPayload->phyop_phyid) & ID_BITS;
2982         u32 phy_op = le32_to_cpu(pPayload->phyop_phyid) & OP_BITS;
2983         if (status != 0) {
2984                 PM8001_MSG_DBG(pm8001_ha,
2985                         pm8001_printk("%x phy execute %x phy op failed!\n",
2986                         phy_id, phy_op));
2987         } else
2988                 PM8001_MSG_DBG(pm8001_ha,
2989                         pm8001_printk("%x phy execute %x phy op success!\n",
2990                         phy_id, phy_op));
2991         return 0;
2992 }
2993
2994 /**
2995  * pm8001_bytes_dmaed - one of the interface function communication with libsas
2996  * @pm8001_ha: our hba card information
2997  * @i: which phy that received the event.
2998  *
2999  * when HBA driver received the identify done event or initiate FIS received
3000  * event(for SATA), it will invoke this function to notify the sas layer that
3001  * the sas toplogy has formed, please discover the the whole sas domain,
3002  * while receive a broadcast(change) primitive just tell the sas
3003  * layer to discover the changed domain rather than the whole domain.
3004  */
3005 void pm8001_bytes_dmaed(struct pm8001_hba_info *pm8001_ha, int i)
3006 {
3007         struct pm8001_phy *phy = &pm8001_ha->phy[i];
3008         struct asd_sas_phy *sas_phy = &phy->sas_phy;
3009         struct sas_ha_struct *sas_ha;
3010         if (!phy->phy_attached)
3011                 return;
3012
3013         sas_ha = pm8001_ha->sas;
3014         if (sas_phy->phy) {
3015                 struct sas_phy *sphy = sas_phy->phy;
3016                 sphy->negotiated_linkrate = sas_phy->linkrate;
3017                 sphy->minimum_linkrate = phy->minimum_linkrate;
3018                 sphy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS;
3019                 sphy->maximum_linkrate = phy->maximum_linkrate;
3020                 sphy->maximum_linkrate_hw = phy->maximum_linkrate;
3021         }
3022
3023         if (phy->phy_type & PORT_TYPE_SAS) {
3024                 struct sas_identify_frame *id;
3025                 id = (struct sas_identify_frame *)phy->frame_rcvd;
3026                 id->dev_type = phy->identify.device_type;
3027                 id->initiator_bits = SAS_PROTOCOL_ALL;
3028                 id->target_bits = phy->identify.target_port_protocols;
3029         } else if (phy->phy_type & PORT_TYPE_SATA) {
3030                 /*Nothing*/
3031         }
3032         PM8001_MSG_DBG(pm8001_ha, pm8001_printk("phy %d byte dmaded.\n", i));
3033
3034         sas_phy->frame_rcvd_size = phy->frame_rcvd_size;
3035         pm8001_ha->sas->notify_port_event(sas_phy, PORTE_BYTES_DMAED);
3036 }
3037
3038 /* Get the link rate speed  */
3039 void pm8001_get_lrate_mode(struct pm8001_phy *phy, u8 link_rate)
3040 {
3041         struct sas_phy *sas_phy = phy->sas_phy.phy;
3042
3043         switch (link_rate) {
3044         case PHY_SPEED_60:
3045                 phy->sas_phy.linkrate = SAS_LINK_RATE_6_0_GBPS;
3046                 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_6_0_GBPS;
3047                 break;
3048         case PHY_SPEED_30:
3049                 phy->sas_phy.linkrate = SAS_LINK_RATE_3_0_GBPS;
3050                 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_3_0_GBPS;
3051                 break;
3052         case PHY_SPEED_15:
3053                 phy->sas_phy.linkrate = SAS_LINK_RATE_1_5_GBPS;
3054                 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_1_5_GBPS;
3055                 break;
3056         }
3057         sas_phy->negotiated_linkrate = phy->sas_phy.linkrate;
3058         sas_phy->maximum_linkrate_hw = SAS_LINK_RATE_6_0_GBPS;
3059         sas_phy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS;
3060         sas_phy->maximum_linkrate = SAS_LINK_RATE_6_0_GBPS;
3061         sas_phy->minimum_linkrate = SAS_LINK_RATE_1_5_GBPS;
3062 }
3063
3064 /**
3065  * asd_get_attached_sas_addr -- extract/generate attached SAS address
3066  * @phy: pointer to asd_phy
3067  * @sas_addr: pointer to buffer where the SAS address is to be written
3068  *
3069  * This function extracts the SAS address from an IDENTIFY frame
3070  * received.  If OOB is SATA, then a SAS address is generated from the
3071  * HA tables.
3072  *
3073  * LOCKING: the frame_rcvd_lock needs to be held since this parses the frame
3074  * buffer.
3075  */
3076 void pm8001_get_attached_sas_addr(struct pm8001_phy *phy,
3077         u8 *sas_addr)
3078 {
3079         if (phy->sas_phy.frame_rcvd[0] == 0x34
3080                 && phy->sas_phy.oob_mode == SATA_OOB_MODE) {
3081                 struct pm8001_hba_info *pm8001_ha = phy->sas_phy.ha->lldd_ha;
3082                 /* FIS device-to-host */
3083                 u64 addr = be64_to_cpu(*(__be64 *)pm8001_ha->sas_addr);
3084                 addr += phy->sas_phy.id;
3085                 *(__be64 *)sas_addr = cpu_to_be64(addr);
3086         } else {
3087                 struct sas_identify_frame *idframe =
3088                         (void *) phy->sas_phy.frame_rcvd;
3089                 memcpy(sas_addr, idframe->sas_addr, SAS_ADDR_SIZE);
3090         }
3091 }
3092
3093 /**
3094  * pm8001_hw_event_ack_req- For PM8001,some events need to acknowage to FW.
3095  * @pm8001_ha: our hba card information
3096  * @Qnum: the outbound queue message number.
3097  * @SEA: source of event to ack
3098  * @port_id: port id.
3099  * @phyId: phy id.
3100  * @param0: parameter 0.
3101  * @param1: parameter 1.
3102  */
3103 static void pm8001_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha,
3104         u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1)
3105 {
3106         struct hw_event_ack_req  payload;
3107         u32 opc = OPC_INB_SAS_HW_EVENT_ACK;
3108
3109         struct inbound_queue_table *circularQ;
3110
3111         memset((u8 *)&payload, 0, sizeof(payload));
3112         circularQ = &pm8001_ha->inbnd_q_tbl[Qnum];
3113         payload.tag = cpu_to_le32(1);
3114         payload.sea_phyid_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) |
3115                 ((phyId & 0x0F) << 4) | (port_id & 0x0F));
3116         payload.param0 = cpu_to_le32(param0);
3117         payload.param1 = cpu_to_le32(param1);
3118         pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
3119 }
3120
3121 static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
3122         u32 phyId, u32 phy_op);
3123
3124 /**
3125  * hw_event_sas_phy_up -FW tells me a SAS phy up event.
3126  * @pm8001_ha: our hba card information
3127  * @piomb: IO message buffer
3128  */
3129 static void
3130 hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
3131 {
3132         struct hw_event_resp *pPayload =
3133                 (struct hw_event_resp *)(piomb + 4);
3134         u32 lr_evt_status_phyid_portid =
3135                 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3136         u8 link_rate =
3137                 (u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28);
3138         u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3139         u8 phy_id =
3140                 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3141         u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
3142         u8 portstate = (u8)(npip_portstate & 0x0000000F);
3143         struct pm8001_port *port = &pm8001_ha->port[port_id];
3144         struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3145         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3146         unsigned long flags;
3147         u8 deviceType = pPayload->sas_identify.dev_type;
3148         port->port_state =  portstate;
3149         PM8001_MSG_DBG(pm8001_ha,
3150                 pm8001_printk("HW_EVENT_SAS_PHY_UP port id = %d, phy id = %d\n",
3151                 port_id, phy_id));
3152
3153         switch (deviceType) {
3154         case SAS_PHY_UNUSED:
3155                 PM8001_MSG_DBG(pm8001_ha,
3156                         pm8001_printk("device type no device.\n"));
3157                 break;
3158         case SAS_END_DEVICE:
3159                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("end device.\n"));
3160                 pm8001_chip_phy_ctl_req(pm8001_ha, phy_id,
3161                         PHY_NOTIFY_ENABLE_SPINUP);
3162                 port->port_attached = 1;
3163                 pm8001_get_lrate_mode(phy, link_rate);
3164                 break;
3165         case SAS_EDGE_EXPANDER_DEVICE:
3166                 PM8001_MSG_DBG(pm8001_ha,
3167                         pm8001_printk("expander device.\n"));
3168                 port->port_attached = 1;
3169                 pm8001_get_lrate_mode(phy, link_rate);
3170                 break;
3171         case SAS_FANOUT_EXPANDER_DEVICE:
3172                 PM8001_MSG_DBG(pm8001_ha,
3173                         pm8001_printk("fanout expander device.\n"));
3174                 port->port_attached = 1;
3175                 pm8001_get_lrate_mode(phy, link_rate);
3176                 break;
3177         default:
3178                 PM8001_MSG_DBG(pm8001_ha,
3179                         pm8001_printk("unknown device type(%x)\n", deviceType));
3180                 break;
3181         }
3182         phy->phy_type |= PORT_TYPE_SAS;
3183         phy->identify.device_type = deviceType;
3184         phy->phy_attached = 1;
3185         if (phy->identify.device_type == SAS_END_DEVICE)
3186                 phy->identify.target_port_protocols = SAS_PROTOCOL_SSP;
3187         else if (phy->identify.device_type != SAS_PHY_UNUSED)
3188                 phy->identify.target_port_protocols = SAS_PROTOCOL_SMP;
3189         phy->sas_phy.oob_mode = SAS_OOB_MODE;
3190         sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
3191         spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
3192         memcpy(phy->frame_rcvd, &pPayload->sas_identify,
3193                 sizeof(struct sas_identify_frame)-4);
3194         phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4;
3195         pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
3196         spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
3197         if (pm8001_ha->flags == PM8001F_RUN_TIME)
3198                 mdelay(200);/*delay a moment to wait disk to spinup*/
3199         pm8001_bytes_dmaed(pm8001_ha, phy_id);
3200 }
3201
3202 /**
3203  * hw_event_sata_phy_up -FW tells me a SATA phy up event.
3204  * @pm8001_ha: our hba card information
3205  * @piomb: IO message buffer
3206  */
3207 static void
3208 hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
3209 {
3210         struct hw_event_resp *pPayload =
3211                 (struct hw_event_resp *)(piomb + 4);
3212         u32 lr_evt_status_phyid_portid =
3213                 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3214         u8 link_rate =
3215                 (u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28);
3216         u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3217         u8 phy_id =
3218                 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3219         u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
3220         u8 portstate = (u8)(npip_portstate & 0x0000000F);
3221         struct pm8001_port *port = &pm8001_ha->port[port_id];
3222         struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3223         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3224         unsigned long flags;
3225         PM8001_MSG_DBG(pm8001_ha,
3226                 pm8001_printk("HW_EVENT_SATA_PHY_UP port id = %d,"
3227                 " phy id = %d\n", port_id, phy_id));
3228         port->port_state =  portstate;
3229         port->port_attached = 1;
3230         pm8001_get_lrate_mode(phy, link_rate);
3231         phy->phy_type |= PORT_TYPE_SATA;
3232         phy->phy_attached = 1;
3233         phy->sas_phy.oob_mode = SATA_OOB_MODE;
3234         sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
3235         spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
3236         memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4),
3237                 sizeof(struct dev_to_host_fis));
3238         phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
3239         phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
3240         phy->identify.device_type = SATA_DEV;
3241         pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
3242         spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
3243         pm8001_bytes_dmaed(pm8001_ha, phy_id);
3244 }
3245
3246 /**
3247  * hw_event_phy_down -we should notify the libsas the phy is down.
3248  * @pm8001_ha: our hba card information
3249  * @piomb: IO message buffer
3250  */
3251 static void
3252 hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb)
3253 {
3254         struct hw_event_resp *pPayload =
3255                 (struct hw_event_resp *)(piomb + 4);
3256         u32 lr_evt_status_phyid_portid =
3257                 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3258         u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3259         u8 phy_id =
3260                 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3261         u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
3262         u8 portstate = (u8)(npip_portstate & 0x0000000F);
3263         struct pm8001_port *port = &pm8001_ha->port[port_id];
3264         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3265         port->port_state =  portstate;
3266         phy->phy_type = 0;
3267         phy->identify.device_type = 0;
3268         phy->phy_attached = 0;
3269         memset(&phy->dev_sas_addr, 0, SAS_ADDR_SIZE);
3270         switch (portstate) {
3271         case PORT_VALID:
3272                 break;
3273         case PORT_INVALID:
3274                 PM8001_MSG_DBG(pm8001_ha,
3275                         pm8001_printk(" PortInvalid portID %d\n", port_id));
3276                 PM8001_MSG_DBG(pm8001_ha,
3277                         pm8001_printk(" Last phy Down and port invalid\n"));
3278                 port->port_attached = 0;
3279                 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3280                         port_id, phy_id, 0, 0);
3281                 break;
3282         case PORT_IN_RESET:
3283                 PM8001_MSG_DBG(pm8001_ha,
3284                         pm8001_printk(" Port In Reset portID %d\n", port_id));
3285                 break;
3286         case PORT_NOT_ESTABLISHED:
3287                 PM8001_MSG_DBG(pm8001_ha,
3288                         pm8001_printk(" phy Down and PORT_NOT_ESTABLISHED\n"));
3289                 port->port_attached = 0;
3290                 break;
3291         case PORT_LOSTCOMM:
3292                 PM8001_MSG_DBG(pm8001_ha,
3293                         pm8001_printk(" phy Down and PORT_LOSTCOMM\n"));
3294                 PM8001_MSG_DBG(pm8001_ha,
3295                         pm8001_printk(" Last phy Down and port invalid\n"));
3296                 port->port_attached = 0;
3297                 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3298                         port_id, phy_id, 0, 0);
3299                 break;
3300         default:
3301                 port->port_attached = 0;
3302                 PM8001_MSG_DBG(pm8001_ha,
3303                         pm8001_printk(" phy Down and(default) = %x\n",
3304                         portstate));
3305                 break;
3306
3307         }
3308 }
3309
3310 /**
3311  * pm8001_mpi_reg_resp -process register device ID response.
3312  * @pm8001_ha: our hba card information
3313  * @piomb: IO message buffer
3314  *
3315  * when sas layer find a device it will notify LLDD, then the driver register
3316  * the domain device to FW, this event is the return device ID which the FW
3317  * has assigned, from now,inter-communication with FW is no longer using the
3318  * SAS address, use device ID which FW assigned.
3319  */
3320 int pm8001_mpi_reg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3321 {
3322         u32 status;
3323         u32 device_id;
3324         u32 htag;
3325         struct pm8001_ccb_info *ccb;
3326         struct pm8001_device *pm8001_dev;
3327         struct dev_reg_resp *registerRespPayload =
3328                 (struct dev_reg_resp *)(piomb + 4);
3329
3330         htag = le32_to_cpu(registerRespPayload->tag);
3331         ccb = &pm8001_ha->ccb_info[htag];
3332         pm8001_dev = ccb->device;
3333         status = le32_to_cpu(registerRespPayload->status);
3334         device_id = le32_to_cpu(registerRespPayload->device_id);
3335         PM8001_MSG_DBG(pm8001_ha,
3336                 pm8001_printk(" register device is status = %d\n", status));
3337         switch (status) {
3338         case DEVREG_SUCCESS:
3339                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("DEVREG_SUCCESS\n"));
3340                 pm8001_dev->device_id = device_id;
3341                 break;
3342         case DEVREG_FAILURE_OUT_OF_RESOURCE:
3343                 PM8001_MSG_DBG(pm8001_ha,
3344                         pm8001_printk("DEVREG_FAILURE_OUT_OF_RESOURCE\n"));
3345                 break;
3346         case DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED:
3347                 PM8001_MSG_DBG(pm8001_ha,
3348                    pm8001_printk("DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED\n"));
3349                 break;
3350         case DEVREG_FAILURE_INVALID_PHY_ID:
3351                 PM8001_MSG_DBG(pm8001_ha,
3352                         pm8001_printk("DEVREG_FAILURE_INVALID_PHY_ID\n"));
3353                 break;
3354         case DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED:
3355                 PM8001_MSG_DBG(pm8001_ha,
3356                    pm8001_printk("DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED\n"));
3357                 break;
3358         case DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE:
3359                 PM8001_MSG_DBG(pm8001_ha,
3360                         pm8001_printk("DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE\n"));
3361                 break;
3362         case DEVREG_FAILURE_PORT_NOT_VALID_STATE:
3363                 PM8001_MSG_DBG(pm8001_ha,
3364                         pm8001_printk("DEVREG_FAILURE_PORT_NOT_VALID_STATE\n"));
3365                 break;
3366         case DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID:
3367                 PM8001_MSG_DBG(pm8001_ha,
3368                        pm8001_printk("DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID\n"));
3369                 break;
3370         default:
3371                 PM8001_MSG_DBG(pm8001_ha,
3372                  pm8001_printk("DEVREG_FAILURE_DEVICE_TYPE_NOT_UNSORPORTED\n"));
3373                 break;
3374         }
3375         complete(pm8001_dev->dcompletion);
3376         ccb->task = NULL;
3377         ccb->ccb_tag = 0xFFFFFFFF;
3378         pm8001_ccb_free(pm8001_ha, htag);
3379         return 0;
3380 }
3381
3382 int pm8001_mpi_dereg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3383 {
3384         u32 status;
3385         u32 device_id;
3386         struct dev_reg_resp *registerRespPayload =
3387                 (struct dev_reg_resp *)(piomb + 4);
3388
3389         status = le32_to_cpu(registerRespPayload->status);
3390         device_id = le32_to_cpu(registerRespPayload->device_id);
3391         if (status != 0)
3392                 PM8001_MSG_DBG(pm8001_ha,
3393                         pm8001_printk(" deregister device failed ,status = %x"
3394                         ", device_id = %x\n", status, device_id));
3395         return 0;
3396 }
3397
3398 /**
3399  * fw_flash_update_resp - Response from FW for flash update command.
3400  * @pm8001_ha: our hba card information
3401  * @piomb: IO message buffer
3402  */
3403 int pm8001_mpi_fw_flash_update_resp(struct pm8001_hba_info *pm8001_ha,
3404                 void *piomb)
3405 {
3406         u32 status;
3407         struct fw_control_ex    fw_control_context;
3408         struct fw_flash_Update_resp *ppayload =
3409                 (struct fw_flash_Update_resp *)(piomb + 4);
3410         u32 tag = le32_to_cpu(ppayload->tag);
3411         struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
3412         status = le32_to_cpu(ppayload->status);
3413         memcpy(&fw_control_context,
3414                 ccb->fw_control_context,
3415                 sizeof(fw_control_context));
3416         switch (status) {
3417         case FLASH_UPDATE_COMPLETE_PENDING_REBOOT:
3418                 PM8001_MSG_DBG(pm8001_ha,
3419                 pm8001_printk(": FLASH_UPDATE_COMPLETE_PENDING_REBOOT\n"));
3420                 break;
3421         case FLASH_UPDATE_IN_PROGRESS:
3422                 PM8001_MSG_DBG(pm8001_ha,
3423                         pm8001_printk(": FLASH_UPDATE_IN_PROGRESS\n"));
3424                 break;
3425         case FLASH_UPDATE_HDR_ERR:
3426                 PM8001_MSG_DBG(pm8001_ha,
3427                         pm8001_printk(": FLASH_UPDATE_HDR_ERR\n"));
3428                 break;
3429         case FLASH_UPDATE_OFFSET_ERR:
3430                 PM8001_MSG_DBG(pm8001_ha,
3431                         pm8001_printk(": FLASH_UPDATE_OFFSET_ERR\n"));
3432                 break;
3433         case FLASH_UPDATE_CRC_ERR:
3434                 PM8001_MSG_DBG(pm8001_ha,
3435                         pm8001_printk(": FLASH_UPDATE_CRC_ERR\n"));
3436                 break;
3437         case FLASH_UPDATE_LENGTH_ERR:
3438                 PM8001_MSG_DBG(pm8001_ha,
3439                         pm8001_printk(": FLASH_UPDATE_LENGTH_ERR\n"));
3440                 break;
3441         case FLASH_UPDATE_HW_ERR:
3442                 PM8001_MSG_DBG(pm8001_ha,
3443                         pm8001_printk(": FLASH_UPDATE_HW_ERR\n"));
3444                 break;
3445         case FLASH_UPDATE_DNLD_NOT_SUPPORTED:
3446                 PM8001_MSG_DBG(pm8001_ha,
3447                         pm8001_printk(": FLASH_UPDATE_DNLD_NOT_SUPPORTED\n"));
3448                 break;
3449         case FLASH_UPDATE_DISABLED:
3450                 PM8001_MSG_DBG(pm8001_ha,
3451                         pm8001_printk(": FLASH_UPDATE_DISABLED\n"));
3452                 break;
3453         default:
3454                 PM8001_MSG_DBG(pm8001_ha,
3455                         pm8001_printk("No matched status = %d\n", status));
3456                 break;
3457         }
3458         ccb->fw_control_context->fw_control->retcode = status;
3459         pci_free_consistent(pm8001_ha->pdev,
3460                         fw_control_context.len,
3461                         fw_control_context.virtAddr,
3462                         fw_control_context.phys_addr);
3463         complete(pm8001_ha->nvmd_completion);
3464         ccb->task = NULL;
3465         ccb->ccb_tag = 0xFFFFFFFF;
3466         pm8001_ccb_free(pm8001_ha, tag);
3467         return 0;
3468 }
3469
3470 int pm8001_mpi_general_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
3471 {
3472         u32 status;
3473         int i;
3474         struct general_event_resp *pPayload =
3475                 (struct general_event_resp *)(piomb + 4);
3476         status = le32_to_cpu(pPayload->status);
3477         PM8001_MSG_DBG(pm8001_ha,
3478                 pm8001_printk(" status = 0x%x\n", status));
3479         for (i = 0; i < GENERAL_EVENT_PAYLOAD; i++)
3480                 PM8001_MSG_DBG(pm8001_ha,
3481                         pm8001_printk("inb_IOMB_payload[0x%x] 0x%x,\n", i,
3482                         pPayload->inb_IOMB_payload[i]));
3483         return 0;
3484 }
3485
3486 int pm8001_mpi_task_abort_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3487 {
3488         struct sas_task *t;
3489         struct pm8001_ccb_info *ccb;
3490         unsigned long flags;
3491         u32 status ;
3492         u32 tag, scp;
3493         struct task_status_struct *ts;
3494
3495         struct task_abort_resp *pPayload =
3496                 (struct task_abort_resp *)(piomb + 4);
3497
3498         status = le32_to_cpu(pPayload->status);
3499         tag = le32_to_cpu(pPayload->tag);
3500         scp = le32_to_cpu(pPayload->scp);
3501         ccb = &pm8001_ha->ccb_info[tag];
3502         t = ccb->task;
3503         PM8001_IO_DBG(pm8001_ha,
3504                 pm8001_printk(" status = 0x%x\n", status));
3505         if (t == NULL)
3506                 return -1;
3507         ts = &t->task_status;
3508         if (status != 0)
3509                 PM8001_FAIL_DBG(pm8001_ha,
3510                         pm8001_printk("task abort failed status 0x%x ,"
3511                         "tag = 0x%x, scp= 0x%x\n", status, tag, scp));
3512         switch (status) {
3513         case IO_SUCCESS:
3514                 PM8001_EH_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
3515                 ts->resp = SAS_TASK_COMPLETE;
3516                 ts->stat = SAM_STAT_GOOD;
3517                 break;
3518         case IO_NOT_VALID:
3519                 PM8001_EH_DBG(pm8001_ha, pm8001_printk("IO_NOT_VALID\n"));
3520                 ts->resp = TMF_RESP_FUNC_FAILED;
3521                 break;
3522         }
3523         spin_lock_irqsave(&t->task_state_lock, flags);
3524         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
3525         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
3526         t->task_state_flags |= SAS_TASK_STATE_DONE;
3527         spin_unlock_irqrestore(&t->task_state_lock, flags);
3528         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
3529         mb();
3530         t->task_done(t);
3531         return 0;
3532 }
3533
3534 /**
3535  * mpi_hw_event -The hw event has come.
3536  * @pm8001_ha: our hba card information
3537  * @piomb: IO message buffer
3538  */
3539 static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void* piomb)
3540 {
3541         unsigned long flags;
3542         struct hw_event_resp *pPayload =
3543                 (struct hw_event_resp *)(piomb + 4);
3544         u32 lr_evt_status_phyid_portid =
3545                 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3546         u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3547         u8 phy_id =
3548                 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3549         u16 eventType =
3550                 (u16)((lr_evt_status_phyid_portid & 0x00FFFF00) >> 8);
3551         u8 status =
3552                 (u8)((lr_evt_status_phyid_portid & 0x0F000000) >> 24);
3553         struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3554         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3555         struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id];
3556         PM8001_MSG_DBG(pm8001_ha,
3557                 pm8001_printk("outbound queue HW event & event type : "));
3558         switch (eventType) {
3559         case HW_EVENT_PHY_START_STATUS:
3560                 PM8001_MSG_DBG(pm8001_ha,
3561                 pm8001_printk("HW_EVENT_PHY_START_STATUS"
3562                         " status = %x\n", status));
3563                 if (status == 0) {
3564                         phy->phy_state = 1;
3565                         if (pm8001_ha->flags == PM8001F_RUN_TIME)
3566                                 complete(phy->enable_completion);
3567                 }
3568                 break;
3569         case HW_EVENT_SAS_PHY_UP:
3570                 PM8001_MSG_DBG(pm8001_ha,
3571                         pm8001_printk("HW_EVENT_PHY_START_STATUS\n"));
3572                 hw_event_sas_phy_up(pm8001_ha, piomb);
3573                 break;
3574         case HW_EVENT_SATA_PHY_UP:
3575                 PM8001_MSG_DBG(pm8001_ha,
3576                         pm8001_printk("HW_EVENT_SATA_PHY_UP\n"));
3577                 hw_event_sata_phy_up(pm8001_ha, piomb);
3578                 break;
3579         case HW_EVENT_PHY_STOP_STATUS:
3580                 PM8001_MSG_DBG(pm8001_ha,
3581                         pm8001_printk("HW_EVENT_PHY_STOP_STATUS "
3582                         "status = %x\n", status));
3583                 if (status == 0)
3584                         phy->phy_state = 0;
3585                 break;
3586         case HW_EVENT_SATA_SPINUP_HOLD:
3587                 PM8001_MSG_DBG(pm8001_ha,
3588                         pm8001_printk("HW_EVENT_SATA_SPINUP_HOLD\n"));
3589                 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD);
3590                 break;
3591         case HW_EVENT_PHY_DOWN:
3592                 PM8001_MSG_DBG(pm8001_ha,
3593                         pm8001_printk("HW_EVENT_PHY_DOWN\n"));
3594                 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL);
3595                 phy->phy_attached = 0;
3596                 phy->phy_state = 0;
3597                 hw_event_phy_down(pm8001_ha, piomb);
3598                 break;
3599         case HW_EVENT_PORT_INVALID:
3600                 PM8001_MSG_DBG(pm8001_ha,
3601                         pm8001_printk("HW_EVENT_PORT_INVALID\n"));
3602                 sas_phy_disconnected(sas_phy);
3603                 phy->phy_attached = 0;
3604                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3605                 break;
3606         /* the broadcast change primitive received, tell the LIBSAS this event
3607         to revalidate the sas domain*/
3608         case HW_EVENT_BROADCAST_CHANGE:
3609                 PM8001_MSG_DBG(pm8001_ha,
3610                         pm8001_printk("HW_EVENT_BROADCAST_CHANGE\n"));
3611                 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE,
3612                         port_id, phy_id, 1, 0);
3613                 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3614                 sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE;
3615                 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3616                 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3617                 break;
3618         case HW_EVENT_PHY_ERROR:
3619                 PM8001_MSG_DBG(pm8001_ha,
3620                         pm8001_printk("HW_EVENT_PHY_ERROR\n"));
3621                 sas_phy_disconnected(&phy->sas_phy);
3622                 phy->phy_attached = 0;
3623                 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR);
3624                 break;
3625         case HW_EVENT_BROADCAST_EXP:
3626                 PM8001_MSG_DBG(pm8001_ha,
3627                         pm8001_printk("HW_EVENT_BROADCAST_EXP\n"));
3628                 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3629                 sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP;
3630                 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3631                 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3632                 break;
3633         case HW_EVENT_LINK_ERR_INVALID_DWORD:
3634                 PM8001_MSG_DBG(pm8001_ha,
3635                         pm8001_printk("HW_EVENT_LINK_ERR_INVALID_DWORD\n"));
3636                 pm8001_hw_event_ack_req(pm8001_ha, 0,
3637                         HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0);
3638                 sas_phy_disconnected(sas_phy);
3639                 phy->phy_attached = 0;
3640                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3641                 break;
3642         case HW_EVENT_LINK_ERR_DISPARITY_ERROR:
3643                 PM8001_MSG_DBG(pm8001_ha,
3644                         pm8001_printk("HW_EVENT_LINK_ERR_DISPARITY_ERROR\n"));
3645                 pm8001_hw_event_ack_req(pm8001_ha, 0,
3646                         HW_EVENT_LINK_ERR_DISPARITY_ERROR,
3647                         port_id, phy_id, 0, 0);
3648                 sas_phy_disconnected(sas_phy);
3649                 phy->phy_attached = 0;
3650                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3651                 break;
3652         case HW_EVENT_LINK_ERR_CODE_VIOLATION:
3653                 PM8001_MSG_DBG(pm8001_ha,
3654                         pm8001_printk("HW_EVENT_LINK_ERR_CODE_VIOLATION\n"));
3655                 pm8001_hw_event_ack_req(pm8001_ha, 0,
3656                         HW_EVENT_LINK_ERR_CODE_VIOLATION,
3657                         port_id, phy_id, 0, 0);
3658                 sas_phy_disconnected(sas_phy);
3659                 phy->phy_attached = 0;
3660                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3661                 break;
3662         case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH:
3663                 PM8001_MSG_DBG(pm8001_ha,
3664                       pm8001_printk("HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n"));
3665                 pm8001_hw_event_ack_req(pm8001_ha, 0,
3666                         HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH,
3667                         port_id, phy_id, 0, 0);
3668                 sas_phy_disconnected(sas_phy);
3669                 phy->phy_attached = 0;
3670                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3671                 break;
3672         case HW_EVENT_MALFUNCTION:
3673                 PM8001_MSG_DBG(pm8001_ha,
3674                         pm8001_printk("HW_EVENT_MALFUNCTION\n"));
3675                 break;
3676         case HW_EVENT_BROADCAST_SES:
3677                 PM8001_MSG_DBG(pm8001_ha,
3678                         pm8001_printk("HW_EVENT_BROADCAST_SES\n"));
3679                 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3680                 sas_phy->sas_prim = HW_EVENT_BROADCAST_SES;
3681                 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3682                 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3683                 break;
3684         case HW_EVENT_INBOUND_CRC_ERROR:
3685                 PM8001_MSG_DBG(pm8001_ha,
3686                         pm8001_printk("HW_EVENT_INBOUND_CRC_ERROR\n"));
3687                 pm8001_hw_event_ack_req(pm8001_ha, 0,
3688                         HW_EVENT_INBOUND_CRC_ERROR,
3689                         port_id, phy_id, 0, 0);
3690                 break;
3691         case HW_EVENT_HARD_RESET_RECEIVED:
3692                 PM8001_MSG_DBG(pm8001_ha,
3693                         pm8001_printk("HW_EVENT_HARD_RESET_RECEIVED\n"));
3694                 sas_ha->notify_port_event(sas_phy, PORTE_HARD_RESET);
3695                 break;
3696         case HW_EVENT_ID_FRAME_TIMEOUT:
3697                 PM8001_MSG_DBG(pm8001_ha,
3698                         pm8001_printk("HW_EVENT_ID_FRAME_TIMEOUT\n"));
3699                 sas_phy_disconnected(sas_phy);
3700                 phy->phy_attached = 0;
3701                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3702                 break;
3703         case HW_EVENT_LINK_ERR_PHY_RESET_FAILED:
3704                 PM8001_MSG_DBG(pm8001_ha,
3705                         pm8001_printk("HW_EVENT_LINK_ERR_PHY_RESET_FAILED\n"));
3706                 pm8001_hw_event_ack_req(pm8001_ha, 0,
3707                         HW_EVENT_LINK_ERR_PHY_RESET_FAILED,
3708                         port_id, phy_id, 0, 0);
3709                 sas_phy_disconnected(sas_phy);
3710                 phy->phy_attached = 0;
3711                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3712                 break;
3713         case HW_EVENT_PORT_RESET_TIMER_TMO:
3714                 PM8001_MSG_DBG(pm8001_ha,
3715                         pm8001_printk("HW_EVENT_PORT_RESET_TIMER_TMO\n"));
3716                 sas_phy_disconnected(sas_phy);
3717                 phy->phy_attached = 0;
3718                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3719                 break;
3720         case HW_EVENT_PORT_RECOVERY_TIMER_TMO:
3721                 PM8001_MSG_DBG(pm8001_ha,
3722                         pm8001_printk("HW_EVENT_PORT_RECOVERY_TIMER_TMO\n"));
3723                 sas_phy_disconnected(sas_phy);
3724                 phy->phy_attached = 0;
3725                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3726                 break;
3727         case HW_EVENT_PORT_RECOVER:
3728                 PM8001_MSG_DBG(pm8001_ha,
3729                         pm8001_printk("HW_EVENT_PORT_RECOVER\n"));
3730                 break;
3731         case HW_EVENT_PORT_RESET_COMPLETE:
3732                 PM8001_MSG_DBG(pm8001_ha,
3733                         pm8001_printk("HW_EVENT_PORT_RESET_COMPLETE\n"));
3734                 break;
3735         case EVENT_BROADCAST_ASYNCH_EVENT:
3736                 PM8001_MSG_DBG(pm8001_ha,
3737                         pm8001_printk("EVENT_BROADCAST_ASYNCH_EVENT\n"));
3738                 break;
3739         default:
3740                 PM8001_MSG_DBG(pm8001_ha,
3741                         pm8001_printk("Unknown event type = %x\n", eventType));
3742                 break;
3743         }
3744         return 0;
3745 }
3746
3747 /**
3748  * process_one_iomb - process one outbound Queue memory block
3749  * @pm8001_ha: our hba card information
3750  * @piomb: IO message buffer
3751  */
3752 static void process_one_iomb(struct pm8001_hba_info *pm8001_ha, void *piomb)
3753 {
3754         __le32 pHeader = *(__le32 *)piomb;
3755         u8 opc = (u8)((le32_to_cpu(pHeader)) & 0xFFF);
3756
3757         PM8001_MSG_DBG(pm8001_ha, pm8001_printk("process_one_iomb:"));
3758
3759         switch (opc) {
3760         case OPC_OUB_ECHO:
3761                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("OPC_OUB_ECHO\n"));
3762                 break;
3763         case OPC_OUB_HW_EVENT:
3764                 PM8001_MSG_DBG(pm8001_ha,
3765                         pm8001_printk("OPC_OUB_HW_EVENT\n"));
3766                 mpi_hw_event(pm8001_ha, piomb);
3767                 break;
3768         case OPC_OUB_SSP_COMP:
3769                 PM8001_MSG_DBG(pm8001_ha,
3770                         pm8001_printk("OPC_OUB_SSP_COMP\n"));
3771                 mpi_ssp_completion(pm8001_ha, piomb);
3772                 break;
3773         case OPC_OUB_SMP_COMP:
3774                 PM8001_MSG_DBG(pm8001_ha,
3775                         pm8001_printk("OPC_OUB_SMP_COMP\n"));
3776                 mpi_smp_completion(pm8001_ha, piomb);
3777                 break;
3778         case OPC_OUB_LOCAL_PHY_CNTRL:
3779                 PM8001_MSG_DBG(pm8001_ha,
3780                         pm8001_printk("OPC_OUB_LOCAL_PHY_CNTRL\n"));
3781                 pm8001_mpi_local_phy_ctl(pm8001_ha, piomb);
3782                 break;
3783         case OPC_OUB_DEV_REGIST:
3784                 PM8001_MSG_DBG(pm8001_ha,
3785                         pm8001_printk("OPC_OUB_DEV_REGIST\n"));
3786                 pm8001_mpi_reg_resp(pm8001_ha, piomb);
3787                 break;
3788         case OPC_OUB_DEREG_DEV:
3789                 PM8001_MSG_DBG(pm8001_ha,
3790                         pm8001_printk("unregister the device\n"));
3791                 pm8001_mpi_dereg_resp(pm8001_ha, piomb);
3792                 break;
3793         case OPC_OUB_GET_DEV_HANDLE:
3794                 PM8001_MSG_DBG(pm8001_ha,
3795                         pm8001_printk("OPC_OUB_GET_DEV_HANDLE\n"));
3796                 break;
3797         case OPC_OUB_SATA_COMP:
3798                 PM8001_MSG_DBG(pm8001_ha,
3799                         pm8001_printk("OPC_OUB_SATA_COMP\n"));
3800                 mpi_sata_completion(pm8001_ha, piomb);
3801                 break;
3802         case OPC_OUB_SATA_EVENT:
3803                 PM8001_MSG_DBG(pm8001_ha,
3804                         pm8001_printk("OPC_OUB_SATA_EVENT\n"));
3805                 mpi_sata_event(pm8001_ha, piomb);
3806                 break;
3807         case OPC_OUB_SSP_EVENT:
3808                 PM8001_MSG_DBG(pm8001_ha,
3809                         pm8001_printk("OPC_OUB_SSP_EVENT\n"));
3810                 mpi_ssp_event(pm8001_ha, piomb);
3811                 break;
3812         case OPC_OUB_DEV_HANDLE_ARRIV:
3813                 PM8001_MSG_DBG(pm8001_ha,
3814                         pm8001_printk("OPC_OUB_DEV_HANDLE_ARRIV\n"));
3815                 /*This is for target*/
3816                 break;
3817         case OPC_OUB_SSP_RECV_EVENT:
3818                 PM8001_MSG_DBG(pm8001_ha,
3819                         pm8001_printk("OPC_OUB_SSP_RECV_EVENT\n"));
3820                 /*This is for target*/
3821                 break;
3822         case OPC_OUB_DEV_INFO:
3823                 PM8001_MSG_DBG(pm8001_ha,
3824                         pm8001_printk("OPC_OUB_DEV_INFO\n"));
3825                 break;
3826         case OPC_OUB_FW_FLASH_UPDATE:
3827                 PM8001_MSG_DBG(pm8001_ha,
3828                         pm8001_printk("OPC_OUB_FW_FLASH_UPDATE\n"));
3829                 pm8001_mpi_fw_flash_update_resp(pm8001_ha, piomb);
3830                 break;
3831         case OPC_OUB_GPIO_RESPONSE:
3832                 PM8001_MSG_DBG(pm8001_ha,
3833                         pm8001_printk("OPC_OUB_GPIO_RESPONSE\n"));
3834                 break;
3835         case OPC_OUB_GPIO_EVENT:
3836                 PM8001_MSG_DBG(pm8001_ha,
3837                         pm8001_printk("OPC_OUB_GPIO_EVENT\n"));
3838                 break;
3839         case OPC_OUB_GENERAL_EVENT:
3840                 PM8001_MSG_DBG(pm8001_ha,
3841                         pm8001_printk("OPC_OUB_GENERAL_EVENT\n"));
3842                 pm8001_mpi_general_event(pm8001_ha, piomb);
3843                 break;
3844         case OPC_OUB_SSP_ABORT_RSP:
3845                 PM8001_MSG_DBG(pm8001_ha,
3846                         pm8001_printk("OPC_OUB_SSP_ABORT_RSP\n"));
3847                 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3848                 break;
3849         case OPC_OUB_SATA_ABORT_RSP:
3850                 PM8001_MSG_DBG(pm8001_ha,
3851                         pm8001_printk("OPC_OUB_SATA_ABORT_RSP\n"));
3852                 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3853                 break;
3854         case OPC_OUB_SAS_DIAG_MODE_START_END:
3855                 PM8001_MSG_DBG(pm8001_ha,
3856                         pm8001_printk("OPC_OUB_SAS_DIAG_MODE_START_END\n"));
3857                 break;
3858         case OPC_OUB_SAS_DIAG_EXECUTE:
3859                 PM8001_MSG_DBG(pm8001_ha,
3860                         pm8001_printk("OPC_OUB_SAS_DIAG_EXECUTE\n"));
3861                 break;
3862         case OPC_OUB_GET_TIME_STAMP:
3863                 PM8001_MSG_DBG(pm8001_ha,
3864                         pm8001_printk("OPC_OUB_GET_TIME_STAMP\n"));
3865                 break;
3866         case OPC_OUB_SAS_HW_EVENT_ACK:
3867                 PM8001_MSG_DBG(pm8001_ha,
3868                         pm8001_printk("OPC_OUB_SAS_HW_EVENT_ACK\n"));
3869                 break;
3870         case OPC_OUB_PORT_CONTROL:
3871                 PM8001_MSG_DBG(pm8001_ha,
3872                         pm8001_printk("OPC_OUB_PORT_CONTROL\n"));
3873                 break;
3874         case OPC_OUB_SMP_ABORT_RSP:
3875                 PM8001_MSG_DBG(pm8001_ha,
3876                         pm8001_printk("OPC_OUB_SMP_ABORT_RSP\n"));
3877                 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3878                 break;
3879         case OPC_OUB_GET_NVMD_DATA:
3880                 PM8001_MSG_DBG(pm8001_ha,
3881                         pm8001_printk("OPC_OUB_GET_NVMD_DATA\n"));
3882                 pm8001_mpi_get_nvmd_resp(pm8001_ha, piomb);
3883                 break;
3884         case OPC_OUB_SET_NVMD_DATA:
3885                 PM8001_MSG_DBG(pm8001_ha,
3886                         pm8001_printk("OPC_OUB_SET_NVMD_DATA\n"));
3887                 pm8001_mpi_set_nvmd_resp(pm8001_ha, piomb);
3888                 break;
3889         case OPC_OUB_DEVICE_HANDLE_REMOVAL:
3890                 PM8001_MSG_DBG(pm8001_ha,
3891                         pm8001_printk("OPC_OUB_DEVICE_HANDLE_REMOVAL\n"));
3892                 break;
3893         case OPC_OUB_SET_DEVICE_STATE:
3894                 PM8001_MSG_DBG(pm8001_ha,
3895                         pm8001_printk("OPC_OUB_SET_DEVICE_STATE\n"));
3896                 pm8001_mpi_set_dev_state_resp(pm8001_ha, piomb);
3897                 break;
3898         case OPC_OUB_GET_DEVICE_STATE:
3899                 PM8001_MSG_DBG(pm8001_ha,
3900                         pm8001_printk("OPC_OUB_GET_DEVICE_STATE\n"));
3901                 break;
3902         case OPC_OUB_SET_DEV_INFO:
3903                 PM8001_MSG_DBG(pm8001_ha,
3904                         pm8001_printk("OPC_OUB_SET_DEV_INFO\n"));
3905                 break;
3906         case OPC_OUB_SAS_RE_INITIALIZE:
3907                 PM8001_MSG_DBG(pm8001_ha,
3908                         pm8001_printk("OPC_OUB_SAS_RE_INITIALIZE\n"));
3909                 break;
3910         default:
3911                 PM8001_MSG_DBG(pm8001_ha,
3912                         pm8001_printk("Unknown outbound Queue IOMB OPC = %x\n",
3913                         opc));
3914                 break;
3915         }
3916 }
3917
3918 static int process_oq(struct pm8001_hba_info *pm8001_ha, u8 vec)
3919 {
3920         struct outbound_queue_table *circularQ;
3921         void *pMsg1 = NULL;
3922         u8 uninitialized_var(bc);
3923         u32 ret = MPI_IO_STATUS_FAIL;
3924         unsigned long flags;
3925
3926         spin_lock_irqsave(&pm8001_ha->lock, flags);
3927         circularQ = &pm8001_ha->outbnd_q_tbl[vec];
3928         do {
3929                 ret = pm8001_mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc);
3930                 if (MPI_IO_STATUS_SUCCESS == ret) {
3931                         /* process the outbound message */
3932                         process_one_iomb(pm8001_ha, (void *)(pMsg1 - 4));
3933                         /* free the message from the outbound circular buffer */
3934                         pm8001_mpi_msg_free_set(pm8001_ha, pMsg1,
3935                                                         circularQ, bc);
3936                 }
3937                 if (MPI_IO_STATUS_BUSY == ret) {
3938                         /* Update the producer index from SPC */
3939                         circularQ->producer_index =
3940                                 cpu_to_le32(pm8001_read_32(circularQ->pi_virt));
3941                         if (le32_to_cpu(circularQ->producer_index) ==
3942                                 circularQ->consumer_idx)
3943                                 /* OQ is empty */
3944                                 break;
3945                 }
3946         } while (1);
3947         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
3948         return ret;
3949 }
3950
3951 /* PCI_DMA_... to our direction translation. */
3952 static const u8 data_dir_flags[] = {
3953         [PCI_DMA_BIDIRECTIONAL] = DATA_DIR_BYRECIPIENT,/* UNSPECIFIED */
3954         [PCI_DMA_TODEVICE]      = DATA_DIR_OUT,/* OUTBOUND */
3955         [PCI_DMA_FROMDEVICE]    = DATA_DIR_IN,/* INBOUND */
3956         [PCI_DMA_NONE]          = DATA_DIR_NONE,/* NO TRANSFER */
3957 };
3958 void
3959 pm8001_chip_make_sg(struct scatterlist *scatter, int nr, void *prd)
3960 {
3961         int i;
3962         struct scatterlist *sg;
3963         struct pm8001_prd *buf_prd = prd;
3964
3965         for_each_sg(scatter, sg, nr, i) {
3966                 buf_prd->addr = cpu_to_le64(sg_dma_address(sg));
3967                 buf_prd->im_len.len = cpu_to_le32(sg_dma_len(sg));
3968                 buf_prd->im_len.e = 0;
3969                 buf_prd++;
3970         }
3971 }
3972
3973 static void build_smp_cmd(u32 deviceID, __le32 hTag, struct smp_req *psmp_cmd)
3974 {
3975         psmp_cmd->tag = hTag;
3976         psmp_cmd->device_id = cpu_to_le32(deviceID);
3977         psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1));
3978 }
3979
3980 /**
3981  * pm8001_chip_smp_req - send a SMP task to FW
3982  * @pm8001_ha: our hba card information.
3983  * @ccb: the ccb information this request used.
3984  */
3985 static int pm8001_chip_smp_req(struct pm8001_hba_info *pm8001_ha,
3986         struct pm8001_ccb_info *ccb)
3987 {
3988         int elem, rc;
3989         struct sas_task *task = ccb->task;
3990         struct domain_device *dev = task->dev;
3991         struct pm8001_device *pm8001_dev = dev->lldd_dev;
3992         struct scatterlist *sg_req, *sg_resp;
3993         u32 req_len, resp_len;
3994         struct smp_req smp_cmd;
3995         u32 opc;
3996         struct inbound_queue_table *circularQ;
3997
3998         memset(&smp_cmd, 0, sizeof(smp_cmd));
3999         /*
4000          * DMA-map SMP request, response buffers
4001          */
4002         sg_req = &task->smp_task.smp_req;
4003         elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, PCI_DMA_TODEVICE);
4004         if (!elem)
4005                 return -ENOMEM;
4006         req_len = sg_dma_len(sg_req);
4007
4008         sg_resp = &task->smp_task.smp_resp;
4009         elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, PCI_DMA_FROMDEVICE);
4010         if (!elem) {
4011                 rc = -ENOMEM;
4012                 goto err_out;
4013         }
4014         resp_len = sg_dma_len(sg_resp);
4015         /* must be in dwords */
4016         if ((req_len & 0x3) || (resp_len & 0x3)) {
4017                 rc = -EINVAL;
4018                 goto err_out_2;
4019         }
4020
4021         opc = OPC_INB_SMP_REQUEST;
4022         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4023         smp_cmd.tag = cpu_to_le32(ccb->ccb_tag);
4024         smp_cmd.long_smp_req.long_req_addr =
4025                 cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_req));
4026         smp_cmd.long_smp_req.long_req_size =
4027                 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4);
4028         smp_cmd.long_smp_req.long_resp_addr =
4029                 cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_resp));
4030         smp_cmd.long_smp_req.long_resp_size =
4031                 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_resp)-4);
4032         build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag, &smp_cmd);
4033         pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, (u32 *)&smp_cmd, 0);
4034         return 0;
4035
4036 err_out_2:
4037         dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1,
4038                         PCI_DMA_FROMDEVICE);
4039 err_out:
4040         dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1,
4041                         PCI_DMA_TODEVICE);
4042         return rc;
4043 }
4044
4045 /**
4046  * pm8001_chip_ssp_io_req - send a SSP task to FW
4047  * @pm8001_ha: our hba card information.
4048  * @ccb: the ccb information this request used.
4049  */
4050 static int pm8001_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha,
4051         struct pm8001_ccb_info *ccb)
4052 {
4053         struct sas_task *task = ccb->task;
4054         struct domain_device *dev = task->dev;
4055         struct pm8001_device *pm8001_dev = dev->lldd_dev;
4056         struct ssp_ini_io_start_req ssp_cmd;
4057         u32 tag = ccb->ccb_tag;
4058         int ret;
4059         u64 phys_addr;
4060         struct inbound_queue_table *circularQ;
4061         u32 opc = OPC_INB_SSPINIIOSTART;
4062         memset(&ssp_cmd, 0, sizeof(ssp_cmd));
4063         memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8);
4064         ssp_cmd.dir_m_tlr =
4065                 cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0);/*0 for
4066         SAS 1.1 compatible TLR*/
4067         ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4068         ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id);
4069         ssp_cmd.tag = cpu_to_le32(tag);
4070         if (task->ssp_task.enable_first_burst)
4071                 ssp_cmd.ssp_iu.efb_prio_attr |= 0x80;
4072         ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_prio << 3);
4073         ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7);
4074         memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cdb, 16);
4075         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4076
4077         /* fill in PRD (scatter/gather) table, if any */
4078         if (task->num_scatter > 1) {
4079                 pm8001_chip_make_sg(task->scatter, ccb->n_elem, ccb->buf_prd);
4080                 phys_addr = ccb->ccb_dma_handle +
4081                                 offsetof(struct pm8001_ccb_info, buf_prd[0]);
4082                 ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(phys_addr));
4083                 ssp_cmd.addr_high = cpu_to_le32(upper_32_bits(phys_addr));
4084                 ssp_cmd.esgl = cpu_to_le32(1<<31);
4085         } else if (task->num_scatter == 1) {
4086                 u64 dma_addr = sg_dma_address(task->scatter);
4087                 ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(dma_addr));
4088                 ssp_cmd.addr_high = cpu_to_le32(upper_32_bits(dma_addr));
4089                 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4090                 ssp_cmd.esgl = 0;
4091         } else if (task->num_scatter == 0) {
4092                 ssp_cmd.addr_low = 0;
4093                 ssp_cmd.addr_high = 0;
4094                 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4095                 ssp_cmd.esgl = 0;
4096         }
4097         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &ssp_cmd, 0);
4098         return ret;
4099 }
4100
4101 static int pm8001_chip_sata_req(struct pm8001_hba_info *pm8001_ha,
4102         struct pm8001_ccb_info *ccb)
4103 {
4104         struct sas_task *task = ccb->task;
4105         struct domain_device *dev = task->dev;
4106         struct pm8001_device *pm8001_ha_dev = dev->lldd_dev;
4107         u32 tag = ccb->ccb_tag;
4108         int ret;
4109         struct sata_start_req sata_cmd;
4110         u32 hdr_tag, ncg_tag = 0;
4111         u64 phys_addr;
4112         u32 ATAP = 0x0;
4113         u32 dir;
4114         struct inbound_queue_table *circularQ;
4115         u32  opc = OPC_INB_SATA_HOST_OPSTART;
4116         memset(&sata_cmd, 0, sizeof(sata_cmd));
4117         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4118         if (task->data_dir == PCI_DMA_NONE) {
4119                 ATAP = 0x04;  /* no data*/
4120                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("no data\n"));
4121         } else if (likely(!task->ata_task.device_control_reg_update)) {
4122                 if (task->ata_task.dma_xfer) {
4123                         ATAP = 0x06; /* DMA */
4124                         PM8001_IO_DBG(pm8001_ha, pm8001_printk("DMA\n"));
4125                 } else {
4126                         ATAP = 0x05; /* PIO*/
4127                         PM8001_IO_DBG(pm8001_ha, pm8001_printk("PIO\n"));
4128                 }
4129                 if (task->ata_task.use_ncq &&
4130                         dev->sata_dev.command_set != ATAPI_COMMAND_SET) {
4131                         ATAP = 0x07; /* FPDMA */
4132                         PM8001_IO_DBG(pm8001_ha, pm8001_printk("FPDMA\n"));
4133                 }
4134         }
4135         if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag))
4136                 ncg_tag = hdr_tag;
4137         dir = data_dir_flags[task->data_dir] << 8;
4138         sata_cmd.tag = cpu_to_le32(tag);
4139         sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
4140         sata_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4141         sata_cmd.ncqtag_atap_dir_m =
4142                 cpu_to_le32(((ncg_tag & 0xff)<<16)|((ATAP & 0x3f) << 10) | dir);
4143         sata_cmd.sata_fis = task->ata_task.fis;
4144         if (likely(!task->ata_task.device_control_reg_update))
4145                 sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */
4146         sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */
4147         /* fill in PRD (scatter/gather) table, if any */
4148         if (task->num_scatter > 1) {
4149                 pm8001_chip_make_sg(task->scatter, ccb->n_elem, ccb->buf_prd);
4150                 phys_addr = ccb->ccb_dma_handle +
4151                                 offsetof(struct pm8001_ccb_info, buf_prd[0]);
4152                 sata_cmd.addr_low = lower_32_bits(phys_addr);
4153                 sata_cmd.addr_high = upper_32_bits(phys_addr);
4154                 sata_cmd.esgl = cpu_to_le32(1 << 31);
4155         } else if (task->num_scatter == 1) {
4156                 u64 dma_addr = sg_dma_address(task->scatter);
4157                 sata_cmd.addr_low = lower_32_bits(dma_addr);
4158                 sata_cmd.addr_high = upper_32_bits(dma_addr);
4159                 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4160                 sata_cmd.esgl = 0;
4161         } else if (task->num_scatter == 0) {
4162                 sata_cmd.addr_low = 0;
4163                 sata_cmd.addr_high = 0;
4164                 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4165                 sata_cmd.esgl = 0;
4166         }
4167         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd, 0);
4168         return ret;
4169 }
4170
4171 /**
4172  * pm8001_chip_phy_start_req - start phy via PHY_START COMMAND
4173  * @pm8001_ha: our hba card information.
4174  * @num: the inbound queue number
4175  * @phy_id: the phy id which we wanted to start up.
4176  */
4177 static int
4178 pm8001_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id)
4179 {
4180         struct phy_start_req payload;
4181         struct inbound_queue_table *circularQ;
4182         int ret;
4183         u32 tag = 0x01;
4184         u32 opcode = OPC_INB_PHYSTART;
4185         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4186         memset(&payload, 0, sizeof(payload));
4187         payload.tag = cpu_to_le32(tag);
4188         /*
4189          ** [0:7]   PHY Identifier
4190          ** [8:11]  link rate 1.5G, 3G, 6G
4191          ** [12:13] link mode 01b SAS mode; 10b SATA mode; 11b both
4192          ** [14]    0b disable spin up hold; 1b enable spin up hold
4193          */
4194         payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE |
4195                 LINKMODE_AUTO | LINKRATE_15 |
4196                 LINKRATE_30 | LINKRATE_60 | phy_id);
4197         payload.sas_identify.dev_type = SAS_END_DEV;
4198         payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL;
4199         memcpy(payload.sas_identify.sas_addr,
4200                 pm8001_ha->sas_addr, SAS_ADDR_SIZE);
4201         payload.sas_identify.phy_id = phy_id;
4202         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload, 0);
4203         return ret;
4204 }
4205
4206 /**
4207  * pm8001_chip_phy_stop_req - start phy via PHY_STOP COMMAND
4208  * @pm8001_ha: our hba card information.
4209  * @num: the inbound queue number
4210  * @phy_id: the phy id which we wanted to start up.
4211  */
4212 int pm8001_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha,
4213         u8 phy_id)
4214 {
4215         struct phy_stop_req payload;
4216         struct inbound_queue_table *circularQ;
4217         int ret;
4218         u32 tag = 0x01;
4219         u32 opcode = OPC_INB_PHYSTOP;
4220         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4221         memset(&payload, 0, sizeof(payload));
4222         payload.tag = cpu_to_le32(tag);
4223         payload.phy_id = cpu_to_le32(phy_id);
4224         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload, 0);
4225         return ret;
4226 }
4227
4228 /**
4229  * see comments on pm8001_mpi_reg_resp.
4230  */
4231 static int pm8001_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha,
4232         struct pm8001_device *pm8001_dev, u32 flag)
4233 {
4234         struct reg_dev_req payload;
4235         u32     opc;
4236         u32 stp_sspsmp_sata = 0x4;
4237         struct inbound_queue_table *circularQ;
4238         u32 linkrate, phy_id;
4239         int rc, tag = 0xdeadbeef;
4240         struct pm8001_ccb_info *ccb;
4241         u8 retryFlag = 0x1;
4242         u16 firstBurstSize = 0;
4243         u16 ITNT = 2000;
4244         struct domain_device *dev = pm8001_dev->sas_device;
4245         struct domain_device *parent_dev = dev->parent;
4246         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4247
4248         memset(&payload, 0, sizeof(payload));
4249         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4250         if (rc)
4251                 return rc;
4252         ccb = &pm8001_ha->ccb_info[tag];
4253         ccb->device = pm8001_dev;
4254         ccb->ccb_tag = tag;
4255         payload.tag = cpu_to_le32(tag);
4256         if (flag == 1)
4257                 stp_sspsmp_sata = 0x02; /*direct attached sata */
4258         else {
4259                 if (pm8001_dev->dev_type == SATA_DEV)
4260                         stp_sspsmp_sata = 0x00; /* stp*/
4261                 else if (pm8001_dev->dev_type == SAS_END_DEV ||
4262                         pm8001_dev->dev_type == EDGE_DEV ||
4263                         pm8001_dev->dev_type == FANOUT_DEV)
4264                         stp_sspsmp_sata = 0x01; /*ssp or smp*/
4265         }
4266         if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
4267                 phy_id = parent_dev->ex_dev.ex_phy->phy_id;
4268         else
4269                 phy_id = pm8001_dev->attached_phy;
4270         opc = OPC_INB_REG_DEV;
4271         linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ?
4272                         pm8001_dev->sas_device->linkrate : dev->port->linkrate;
4273         payload.phyid_portid =
4274                 cpu_to_le32(((pm8001_dev->sas_device->port->id) & 0x0F) |
4275                 ((phy_id & 0x0F) << 4));
4276         payload.dtype_dlr_retry = cpu_to_le32((retryFlag & 0x01) |
4277                 ((linkrate & 0x0F) * 0x1000000) |
4278                 ((stp_sspsmp_sata & 0x03) * 0x10000000));
4279         payload.firstburstsize_ITNexustimeout =
4280                 cpu_to_le32(ITNT | (firstBurstSize * 0x10000));
4281         memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr,
4282                 SAS_ADDR_SIZE);
4283         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
4284         return rc;
4285 }
4286
4287 /**
4288  * see comments on pm8001_mpi_reg_resp.
4289  */
4290 int pm8001_chip_dereg_dev_req(struct pm8001_hba_info *pm8001_ha,
4291         u32 device_id)
4292 {
4293         struct dereg_dev_req payload;
4294         u32 opc = OPC_INB_DEREG_DEV_HANDLE;
4295         int ret;
4296         struct inbound_queue_table *circularQ;
4297
4298         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4299         memset(&payload, 0, sizeof(payload));
4300         payload.tag = cpu_to_le32(1);
4301         payload.device_id = cpu_to_le32(device_id);
4302         PM8001_MSG_DBG(pm8001_ha,
4303                 pm8001_printk("unregister device device_id = %d\n", device_id));
4304         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
4305         return ret;
4306 }
4307
4308 /**
4309  * pm8001_chip_phy_ctl_req - support the local phy operation
4310  * @pm8001_ha: our hba card information.
4311  * @num: the inbound queue number
4312  * @phy_id: the phy id which we wanted to operate
4313  * @phy_op:
4314  */
4315 static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
4316         u32 phyId, u32 phy_op)
4317 {
4318         struct local_phy_ctl_req payload;
4319         struct inbound_queue_table *circularQ;
4320         int ret;
4321         u32 opc = OPC_INB_LOCAL_PHY_CONTROL;
4322         memset(&payload, 0, sizeof(payload));
4323         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4324         payload.tag = cpu_to_le32(1);
4325         payload.phyop_phyid =
4326                 cpu_to_le32(((phy_op & 0xff) << 8) | (phyId & 0x0F));
4327         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
4328         return ret;
4329 }
4330
4331 static u32 pm8001_chip_is_our_interupt(struct pm8001_hba_info *pm8001_ha)
4332 {
4333         u32 value;
4334 #ifdef PM8001_USE_MSIX
4335         return 1;
4336 #endif
4337         value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR);
4338         if (value)
4339                 return 1;
4340         return 0;
4341
4342 }
4343
4344 /**
4345  * pm8001_chip_isr - PM8001 isr handler.
4346  * @pm8001_ha: our hba card information.
4347  * @irq: irq number.
4348  * @stat: stat.
4349  */
4350 static irqreturn_t
4351 pm8001_chip_isr(struct pm8001_hba_info *pm8001_ha, u8 vec)
4352 {
4353         pm8001_chip_interrupt_disable(pm8001_ha, vec);
4354         process_oq(pm8001_ha, vec);
4355         pm8001_chip_interrupt_enable(pm8001_ha, vec);
4356         return IRQ_HANDLED;
4357 }
4358
4359 static int send_task_abort(struct pm8001_hba_info *pm8001_ha, u32 opc,
4360         u32 dev_id, u8 flag, u32 task_tag, u32 cmd_tag)
4361 {
4362         struct task_abort_req task_abort;
4363         struct inbound_queue_table *circularQ;
4364         int ret;
4365         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4366         memset(&task_abort, 0, sizeof(task_abort));
4367         if (ABORT_SINGLE == (flag & ABORT_MASK)) {
4368                 task_abort.abort_all = 0;
4369                 task_abort.device_id = cpu_to_le32(dev_id);
4370                 task_abort.tag_to_abort = cpu_to_le32(task_tag);
4371                 task_abort.tag = cpu_to_le32(cmd_tag);
4372         } else if (ABORT_ALL == (flag & ABORT_MASK)) {
4373                 task_abort.abort_all = cpu_to_le32(1);
4374                 task_abort.device_id = cpu_to_le32(dev_id);
4375                 task_abort.tag = cpu_to_le32(cmd_tag);
4376         }
4377         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort, 0);
4378         return ret;
4379 }
4380
4381 /**
4382  * pm8001_chip_abort_task - SAS abort task when error or exception happened.
4383  * @task: the task we wanted to aborted.
4384  * @flag: the abort flag.
4385  */
4386 int pm8001_chip_abort_task(struct pm8001_hba_info *pm8001_ha,
4387         struct pm8001_device *pm8001_dev, u8 flag, u32 task_tag, u32 cmd_tag)
4388 {
4389         u32 opc, device_id;
4390         int rc = TMF_RESP_FUNC_FAILED;
4391         PM8001_EH_DBG(pm8001_ha, pm8001_printk("cmd_tag = %x, abort task tag"
4392                 " = %x", cmd_tag, task_tag));
4393         if (pm8001_dev->dev_type == SAS_END_DEV)
4394                 opc = OPC_INB_SSP_ABORT;
4395         else if (pm8001_dev->dev_type == SATA_DEV)
4396                 opc = OPC_INB_SATA_ABORT;
4397         else
4398                 opc = OPC_INB_SMP_ABORT;/* SMP */
4399         device_id = pm8001_dev->device_id;
4400         rc = send_task_abort(pm8001_ha, opc, device_id, flag,
4401                 task_tag, cmd_tag);
4402         if (rc != TMF_RESP_FUNC_COMPLETE)
4403                 PM8001_EH_DBG(pm8001_ha, pm8001_printk("rc= %d\n", rc));
4404         return rc;
4405 }
4406
4407 /**
4408  * pm8001_chip_ssp_tm_req - built the task management command.
4409  * @pm8001_ha: our hba card information.
4410  * @ccb: the ccb information.
4411  * @tmf: task management function.
4412  */
4413 int pm8001_chip_ssp_tm_req(struct pm8001_hba_info *pm8001_ha,
4414         struct pm8001_ccb_info *ccb, struct pm8001_tmf_task *tmf)
4415 {
4416         struct sas_task *task = ccb->task;
4417         struct domain_device *dev = task->dev;
4418         struct pm8001_device *pm8001_dev = dev->lldd_dev;
4419         u32 opc = OPC_INB_SSPINITMSTART;
4420         struct inbound_queue_table *circularQ;
4421         struct ssp_ini_tm_start_req sspTMCmd;
4422         int ret;
4423
4424         memset(&sspTMCmd, 0, sizeof(sspTMCmd));
4425         sspTMCmd.device_id = cpu_to_le32(pm8001_dev->device_id);
4426         sspTMCmd.relate_tag = cpu_to_le32(tmf->tag_of_task_to_be_managed);
4427         sspTMCmd.tmf = cpu_to_le32(tmf->tmf);
4428         memcpy(sspTMCmd.lun, task->ssp_task.LUN, 8);
4429         sspTMCmd.tag = cpu_to_le32(ccb->ccb_tag);
4430         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4431         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sspTMCmd, 0);
4432         return ret;
4433 }
4434
4435 int pm8001_chip_get_nvmd_req(struct pm8001_hba_info *pm8001_ha,
4436         void *payload)
4437 {
4438         u32 opc = OPC_INB_GET_NVMD_DATA;
4439         u32 nvmd_type;
4440         int rc;
4441         u32 tag;
4442         struct pm8001_ccb_info *ccb;
4443         struct inbound_queue_table *circularQ;
4444         struct get_nvm_data_req nvmd_req;
4445         struct fw_control_ex *fw_control_context;
4446         struct pm8001_ioctl_payload *ioctl_payload = payload;
4447
4448         nvmd_type = ioctl_payload->minor_function;
4449         fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
4450         if (!fw_control_context)
4451                 return -ENOMEM;
4452         fw_control_context->usrAddr = (u8 *)&ioctl_payload->func_specific[0];
4453         fw_control_context->len = ioctl_payload->length;
4454         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4455         memset(&nvmd_req, 0, sizeof(nvmd_req));
4456         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4457         if (rc) {
4458                 kfree(fw_control_context);
4459                 return rc;
4460         }
4461         ccb = &pm8001_ha->ccb_info[tag];
4462         ccb->ccb_tag = tag;
4463         ccb->fw_control_context = fw_control_context;
4464         nvmd_req.tag = cpu_to_le32(tag);
4465
4466         switch (nvmd_type) {
4467         case TWI_DEVICE: {
4468                 u32 twi_addr, twi_page_size;
4469                 twi_addr = 0xa8;
4470                 twi_page_size = 2;
4471
4472                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | twi_addr << 16 |
4473                         twi_page_size << 8 | TWI_DEVICE);
4474                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4475                 nvmd_req.resp_addr_hi =
4476                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4477                 nvmd_req.resp_addr_lo =
4478                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4479                 break;
4480         }
4481         case C_SEEPROM: {
4482                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | C_SEEPROM);
4483                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4484                 nvmd_req.resp_addr_hi =
4485                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4486                 nvmd_req.resp_addr_lo =
4487                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4488                 break;
4489         }
4490         case VPD_FLASH: {
4491                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | VPD_FLASH);
4492                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4493                 nvmd_req.resp_addr_hi =
4494                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4495                 nvmd_req.resp_addr_lo =
4496                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4497                 break;
4498         }
4499         case EXPAN_ROM: {
4500                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | EXPAN_ROM);
4501                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4502                 nvmd_req.resp_addr_hi =
4503                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4504                 nvmd_req.resp_addr_lo =
4505                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4506                 break;
4507         }
4508         default:
4509                 break;
4510         }
4511         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &nvmd_req, 0);
4512         return rc;
4513 }
4514
4515 int pm8001_chip_set_nvmd_req(struct pm8001_hba_info *pm8001_ha,
4516         void *payload)
4517 {
4518         u32 opc = OPC_INB_SET_NVMD_DATA;
4519         u32 nvmd_type;
4520         int rc;
4521         u32 tag;
4522         struct pm8001_ccb_info *ccb;
4523         struct inbound_queue_table *circularQ;
4524         struct set_nvm_data_req nvmd_req;
4525         struct fw_control_ex *fw_control_context;
4526         struct pm8001_ioctl_payload *ioctl_payload = payload;
4527
4528         nvmd_type = ioctl_payload->minor_function;
4529         fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
4530         if (!fw_control_context)
4531                 return -ENOMEM;
4532         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4533         memcpy(pm8001_ha->memoryMap.region[NVMD].virt_ptr,
4534                 ioctl_payload->func_specific,
4535                 ioctl_payload->length);
4536         memset(&nvmd_req, 0, sizeof(nvmd_req));
4537         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4538         if (rc) {
4539                 kfree(fw_control_context);
4540                 return rc;
4541         }
4542         ccb = &pm8001_ha->ccb_info[tag];
4543         ccb->fw_control_context = fw_control_context;
4544         ccb->ccb_tag = tag;
4545         nvmd_req.tag = cpu_to_le32(tag);
4546         switch (nvmd_type) {
4547         case TWI_DEVICE: {
4548                 u32 twi_addr, twi_page_size;
4549                 twi_addr = 0xa8;
4550                 twi_page_size = 2;
4551                 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4552                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | twi_addr << 16 |
4553                         twi_page_size << 8 | TWI_DEVICE);
4554                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4555                 nvmd_req.resp_addr_hi =
4556                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4557                 nvmd_req.resp_addr_lo =
4558                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4559                 break;
4560         }
4561         case C_SEEPROM:
4562                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | C_SEEPROM);
4563                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4564                 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4565                 nvmd_req.resp_addr_hi =
4566                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4567                 nvmd_req.resp_addr_lo =
4568                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4569                 break;
4570         case VPD_FLASH:
4571                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | VPD_FLASH);
4572                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4573                 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4574                 nvmd_req.resp_addr_hi =
4575                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4576                 nvmd_req.resp_addr_lo =
4577                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4578                 break;
4579         case EXPAN_ROM:
4580                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | EXPAN_ROM);
4581                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4582                 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4583                 nvmd_req.resp_addr_hi =
4584                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4585                 nvmd_req.resp_addr_lo =
4586                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4587                 break;
4588         default:
4589                 break;
4590         }
4591         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &nvmd_req, 0);
4592         return rc;
4593 }
4594
4595 /**
4596  * pm8001_chip_fw_flash_update_build - support the firmware update operation
4597  * @pm8001_ha: our hba card information.
4598  * @fw_flash_updata_info: firmware flash update param
4599  */
4600 int
4601 pm8001_chip_fw_flash_update_build(struct pm8001_hba_info *pm8001_ha,
4602         void *fw_flash_updata_info, u32 tag)
4603 {
4604         struct fw_flash_Update_req payload;
4605         struct fw_flash_updata_info *info;
4606         struct inbound_queue_table *circularQ;
4607         int ret;
4608         u32 opc = OPC_INB_FW_FLASH_UPDATE;
4609
4610         memset(&payload, 0, sizeof(struct fw_flash_Update_req));
4611         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4612         info = fw_flash_updata_info;
4613         payload.tag = cpu_to_le32(tag);
4614         payload.cur_image_len = cpu_to_le32(info->cur_image_len);
4615         payload.cur_image_offset = cpu_to_le32(info->cur_image_offset);
4616         payload.total_image_len = cpu_to_le32(info->total_image_len);
4617         payload.len = info->sgl.im_len.len ;
4618         payload.sgl_addr_lo =
4619                 cpu_to_le32(lower_32_bits(le64_to_cpu(info->sgl.addr)));
4620         payload.sgl_addr_hi =
4621                 cpu_to_le32(upper_32_bits(le64_to_cpu(info->sgl.addr)));
4622         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
4623         return ret;
4624 }
4625
4626 int
4627 pm8001_chip_fw_flash_update_req(struct pm8001_hba_info *pm8001_ha,
4628         void *payload)
4629 {
4630         struct fw_flash_updata_info flash_update_info;
4631         struct fw_control_info *fw_control;
4632         struct fw_control_ex *fw_control_context;
4633         int rc;
4634         u32 tag;
4635         struct pm8001_ccb_info *ccb;
4636         void *buffer = NULL;
4637         dma_addr_t phys_addr;
4638         u32 phys_addr_hi;
4639         u32 phys_addr_lo;
4640         struct pm8001_ioctl_payload *ioctl_payload = payload;
4641
4642         fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
4643         if (!fw_control_context)
4644                 return -ENOMEM;
4645         fw_control = (struct fw_control_info *)&ioctl_payload->func_specific[0];
4646         if (fw_control->len != 0) {
4647                 if (pm8001_mem_alloc(pm8001_ha->pdev,
4648                         (void **)&buffer,
4649                         &phys_addr,
4650                         &phys_addr_hi,
4651                         &phys_addr_lo,
4652                         fw_control->len, 0) != 0) {
4653                                 PM8001_FAIL_DBG(pm8001_ha,
4654                                         pm8001_printk("Mem alloc failure\n"));
4655                                 kfree(fw_control_context);
4656                                 return -ENOMEM;
4657                 }
4658         }
4659         memcpy(buffer, fw_control->buffer, fw_control->len);
4660         flash_update_info.sgl.addr = cpu_to_le64(phys_addr);
4661         flash_update_info.sgl.im_len.len = cpu_to_le32(fw_control->len);
4662         flash_update_info.sgl.im_len.e = 0;
4663         flash_update_info.cur_image_offset = fw_control->offset;
4664         flash_update_info.cur_image_len = fw_control->len;
4665         flash_update_info.total_image_len = fw_control->size;
4666         fw_control_context->fw_control = fw_control;
4667         fw_control_context->virtAddr = buffer;
4668         fw_control_context->len = fw_control->len;
4669         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4670         if (rc) {
4671                 kfree(fw_control_context);
4672                 return rc;
4673         }
4674         ccb = &pm8001_ha->ccb_info[tag];
4675         ccb->fw_control_context = fw_control_context;
4676         ccb->ccb_tag = tag;
4677         rc = pm8001_chip_fw_flash_update_build(pm8001_ha, &flash_update_info,
4678                 tag);
4679         return rc;
4680 }
4681
4682 int
4683 pm8001_chip_set_dev_state_req(struct pm8001_hba_info *pm8001_ha,
4684         struct pm8001_device *pm8001_dev, u32 state)
4685 {
4686         struct set_dev_state_req payload;
4687         struct inbound_queue_table *circularQ;
4688         struct pm8001_ccb_info *ccb;
4689         int rc;
4690         u32 tag;
4691         u32 opc = OPC_INB_SET_DEVICE_STATE;
4692         memset(&payload, 0, sizeof(payload));
4693         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4694         if (rc)
4695                 return -1;
4696         ccb = &pm8001_ha->ccb_info[tag];
4697         ccb->ccb_tag = tag;
4698         ccb->device = pm8001_dev;
4699         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4700         payload.tag = cpu_to_le32(tag);
4701         payload.device_id = cpu_to_le32(pm8001_dev->device_id);
4702         payload.nds = cpu_to_le32(state);
4703         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
4704         return rc;
4705
4706 }
4707
4708 static int
4709 pm8001_chip_sas_re_initialization(struct pm8001_hba_info *pm8001_ha)
4710 {
4711         struct sas_re_initialization_req payload;
4712         struct inbound_queue_table *circularQ;
4713         struct pm8001_ccb_info *ccb;
4714         int rc;
4715         u32 tag;
4716         u32 opc = OPC_INB_SAS_RE_INITIALIZE;
4717         memset(&payload, 0, sizeof(payload));
4718         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4719         if (rc)
4720                 return -1;
4721         ccb = &pm8001_ha->ccb_info[tag];
4722         ccb->ccb_tag = tag;
4723         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4724         payload.tag = cpu_to_le32(tag);
4725         payload.SSAHOLT = cpu_to_le32(0xd << 25);
4726         payload.sata_hol_tmo = cpu_to_le32(80);
4727         payload.open_reject_cmdretries_data_retries = cpu_to_le32(0xff00ff);
4728         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
4729         return rc;
4730
4731 }
4732
4733 const struct pm8001_dispatch pm8001_8001_dispatch = {
4734         .name                   = "pmc8001",
4735         .chip_init              = pm8001_chip_init,
4736         .chip_soft_rst          = pm8001_chip_soft_rst,
4737         .chip_rst               = pm8001_hw_chip_rst,
4738         .chip_iounmap           = pm8001_chip_iounmap,
4739         .isr                    = pm8001_chip_isr,
4740         .is_our_interupt        = pm8001_chip_is_our_interupt,
4741         .isr_process_oq         = process_oq,
4742         .interrupt_enable       = pm8001_chip_interrupt_enable,
4743         .interrupt_disable      = pm8001_chip_interrupt_disable,
4744         .make_prd               = pm8001_chip_make_sg,
4745         .smp_req                = pm8001_chip_smp_req,
4746         .ssp_io_req             = pm8001_chip_ssp_io_req,
4747         .sata_req               = pm8001_chip_sata_req,
4748         .phy_start_req          = pm8001_chip_phy_start_req,
4749         .phy_stop_req           = pm8001_chip_phy_stop_req,
4750         .reg_dev_req            = pm8001_chip_reg_dev_req,
4751         .dereg_dev_req          = pm8001_chip_dereg_dev_req,
4752         .phy_ctl_req            = pm8001_chip_phy_ctl_req,
4753         .task_abort             = pm8001_chip_abort_task,
4754         .ssp_tm_req             = pm8001_chip_ssp_tm_req,
4755         .get_nvmd_req           = pm8001_chip_get_nvmd_req,
4756         .set_nvmd_req           = pm8001_chip_set_nvmd_req,
4757         .fw_flash_update_req    = pm8001_chip_fw_flash_update_req,
4758         .set_dev_state_req      = pm8001_chip_set_dev_state_req,
4759         .sas_re_init_req        = pm8001_chip_sas_re_initialization,
4760 };