drivers/scsi/pm8001/pm8001_init.c

   1 /*
   2  * PMC-Sierra PM8001/8081/8088/8089 SAS/SATA based host adapters driver
   3  *
   4  * Copyright (c) 2008-2009 USI Co., Ltd.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions, and the following disclaimer,
  12  *    without modification.
  13  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  14  *    substantially similar to the "NO WARRANTY" disclaimer below
  15  *    ("Disclaimer") and any redistribution must be conditioned upon
  16  *    including a substantially similar Disclaimer requirement for further
  17  *    binary redistribution.
  18  * 3. Neither the names of the above-listed copyright holders nor the names
  19  *    of any contributors may be used to endorse or promote products derived
  20  *    from this software without specific prior written permission.
  21  *
  22  * Alternatively, this software may be distributed under the terms of the
  23  * GNU General Public License ("GPL") version 2 as published by the Free
  24  * Software Foundation.
  25  *
  26  * NO WARRANTY
  27  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
  30  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  31  * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  32  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  33  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  34  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  35  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  36  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  37  * POSSIBILITY OF SUCH DAMAGES.
  38  *
  39  */
  40
  41 #include <linux/slab.h>
  42 #include "pm8001_sas.h"
  43 #include "pm8001_chips.h"
  44
  45 static struct scsi_transport_template *pm8001_stt;
  46
  47 /**
  48  * chip info structure to identify chip key functionality as
  49  * encryption available/not, no of ports, hw specific function ref
  50  */
  51 static const struct pm8001_chip_info pm8001_chips[] = {
  52         [chip_8001] = {0,  8, &pm8001_8001_dispatch,},
  53         [chip_8008] = {0,  8, &pm8001_80xx_dispatch,},
  54         [chip_8009] = {1,  8, &pm8001_80xx_dispatch,},
  55         [chip_8018] = {0,  16, &pm8001_80xx_dispatch,},
  56         [chip_8019] = {1,  16, &pm8001_80xx_dispatch,},
  57         [chip_8074] = {0,  8, &pm8001_80xx_dispatch,},
  58         [chip_8076] = {0,  16, &pm8001_80xx_dispatch,},
  59         [chip_8077] = {0,  16, &pm8001_80xx_dispatch,},
  60 };
  61 static int pm8001_id;
  62
  63 LIST_HEAD(hba_list);
  64
  65 struct workqueue_struct *pm8001_wq;
  66
  67 /**
  68  * The main structure which LLDD must register for scsi core.
  69  */
  70 static struct scsi_host_template pm8001_sht = {
  71         .module                 = THIS_MODULE,
  72         .name                   = DRV_NAME,
  73         .queuecommand           = sas_queuecommand,
  74         .target_alloc           = sas_target_alloc,
  75         .slave_configure        = sas_slave_configure,
  76         .scan_finished          = pm8001_scan_finished,
  77         .scan_start             = pm8001_scan_start,
  78         .change_queue_depth     = sas_change_queue_depth,
  79         .change_queue_type      = sas_change_queue_type,
  80         .bios_param             = sas_bios_param,
  81         .can_queue              = 1,
  82         .cmd_per_lun            = 1,
  83         .this_id                = -1,
  84         .sg_tablesize           = SG_ALL,
  85         .max_sectors            = SCSI_DEFAULT_MAX_SECTORS,
  86         .use_clustering         = ENABLE_CLUSTERING,
  87         .eh_device_reset_handler = sas_eh_device_reset_handler,
  88         .eh_bus_reset_handler   = sas_eh_bus_reset_handler,
  89         .target_destroy         = sas_target_destroy,
  90         .ioctl                  = sas_ioctl,
  91         .shost_attrs            = pm8001_host_attrs,
  92         .use_blk_tags           = 1,
  93         .track_queue_depth      = 1,
  94 };
  95
  96 /**
  97  * Sas layer call this function to execute specific task.
  98  */
  99 static struct sas_domain_function_template pm8001_transport_ops = {
 100         .lldd_dev_found         = pm8001_dev_found,
 101         .lldd_dev_gone          = pm8001_dev_gone,
 102
 103         .lldd_execute_task      = pm8001_queue_command,
 104         .lldd_control_phy       = pm8001_phy_control,
 105
 106         .lldd_abort_task        = pm8001_abort_task,
 107         .lldd_abort_task_set    = pm8001_abort_task_set,
 108         .lldd_clear_aca         = pm8001_clear_aca,
 109         .lldd_clear_task_set    = pm8001_clear_task_set,
 110         .lldd_I_T_nexus_reset   = pm8001_I_T_nexus_reset,
 111         .lldd_lu_reset          = pm8001_lu_reset,
 112         .lldd_query_task        = pm8001_query_task,
 113 };
 114
 115 /**
 116  *pm8001_phy_init - initiate our adapter phys
 117  *@pm8001_ha: our hba structure.
 118  *@phy_id: phy id.
 119  */
 120 static void pm8001_phy_init(struct pm8001_hba_info *pm8001_ha, int phy_id)
 121 {
 122         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
 123         struct asd_sas_phy *sas_phy = &phy->sas_phy;
 124         phy->phy_state = 0;
 125         phy->pm8001_ha = pm8001_ha;
 126         sas_phy->enabled = (phy_id < pm8001_ha->chip->n_phy) ? 1 : 0;
 127         sas_phy->class = SAS;
 128         sas_phy->iproto = SAS_PROTOCOL_ALL;
 129         sas_phy->tproto = 0;
 130         sas_phy->type = PHY_TYPE_PHYSICAL;
 131         sas_phy->role = PHY_ROLE_INITIATOR;
 132         sas_phy->oob_mode = OOB_NOT_CONNECTED;
 133         sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN;
 134         sas_phy->id = phy_id;
 135         sas_phy->sas_addr = &pm8001_ha->sas_addr[0];
 136         sas_phy->frame_rcvd = &phy->frame_rcvd[0];
 137         sas_phy->ha = (struct sas_ha_struct *)pm8001_ha->shost->hostdata;
 138         sas_phy->lldd_phy = phy;
 139 }
 140
 141 /**
 142  *pm8001_free - free hba
 143  *@pm8001_ha:   our hba structure.
 144  *
 145  */
 146 static void pm8001_free(struct pm8001_hba_info *pm8001_ha)
 147 {
 148         int i;
 149
 150         if (!pm8001_ha)
 151                 return;
 152
 153         for (i = 0; i < USI_MAX_MEMCNT; i++) {
 154                 if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) {
 155                         pci_free_consistent(pm8001_ha->pdev,
 156                                 (pm8001_ha->memoryMap.region[i].total_len +
 157                                 pm8001_ha->memoryMap.region[i].alignment),
 158                                 pm8001_ha->memoryMap.region[i].virt_ptr,
 159                                 pm8001_ha->memoryMap.region[i].phys_addr);
 160                         }
 161         }
 162         PM8001_CHIP_DISP->chip_iounmap(pm8001_ha);
 163         if (pm8001_ha->shost)
 164                 scsi_host_put(pm8001_ha->shost);
 165         flush_workqueue(pm8001_wq);
 166         kfree(pm8001_ha->tags);
 167         kfree(pm8001_ha);
 168 }
 169
 170 #ifdef PM8001_USE_TASKLET
 171
 172 /**
 173  * tasklet for 64 msi-x interrupt handler
 174  * @opaque: the passed general host adapter struct
 175  * Note: pm8001_tasklet is common for pm8001 & pm80xx
 176  */
 177 static void pm8001_tasklet(unsigned long opaque)
 178 {
 179         struct pm8001_hba_info *pm8001_ha;
 180         struct isr_param *irq_vector;
 181
 182         irq_vector = (struct isr_param *)opaque;
 183         pm8001_ha = irq_vector->drv_inst;
 184         if (unlikely(!pm8001_ha))
 185                 BUG_ON(1);
 186         PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id);
 187 }
 188 #endif
 189
 190 /**
 191  * pm8001_interrupt_handler_msix - main MSIX interrupt handler.
 192  * It obtains the vector number and calls the equivalent bottom
 193  * half or services directly.
 194  * @opaque: the passed outbound queue/vector. Host structure is
 195  * retrieved from the same.
 196  */
 197 static irqreturn_t pm8001_interrupt_handler_msix(int irq, void *opaque)
 198 {
 199         struct isr_param *irq_vector;
 200         struct pm8001_hba_info *pm8001_ha;
 201         irqreturn_t ret = IRQ_HANDLED;
 202         irq_vector = (struct isr_param *)opaque;
 203         pm8001_ha = irq_vector->drv_inst;
 204
 205         if (unlikely(!pm8001_ha))
 206                 return IRQ_NONE;
 207         if (!PM8001_CHIP_DISP->is_our_interupt(pm8001_ha))
 208                 return IRQ_NONE;
 209 #ifdef PM8001_USE_TASKLET
 210         tasklet_schedule(&pm8001_ha->tasklet[irq_vector->irq_id]);
 211 #else
 212         ret = PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id);
 213 #endif
 214         return ret;
 215 }
 216
 217 /**
 218  * pm8001_interrupt_handler_intx - main INTx interrupt handler.
 219  * @dev_id: sas_ha structure. The HBA is retrieved from sas_has structure.
 220  */
 221
 222 static irqreturn_t pm8001_interrupt_handler_intx(int irq, void *dev_id)
 223 {
 224         struct pm8001_hba_info *pm8001_ha;
 225         irqreturn_t ret = IRQ_HANDLED;
 226         struct sas_ha_struct *sha = dev_id;
 227         pm8001_ha = sha->lldd_ha;
 228         if (unlikely(!pm8001_ha))
 229                 return IRQ_NONE;
 230         if (!PM8001_CHIP_DISP->is_our_interupt(pm8001_ha))
 231                 return IRQ_NONE;
 232
 233 #ifdef PM8001_USE_TASKLET
 234         tasklet_schedule(&pm8001_ha->tasklet[0]);
 235 #else
 236         ret = PM8001_CHIP_DISP->isr(pm8001_ha, 0);
 237 #endif
 238         return ret;
 239 }
 240
 241 /**
 242  * pm8001_alloc - initiate our hba structure and 6 DMAs area.
 243  * @pm8001_ha:our hba structure.
 244  *
 245  */
 246 static int pm8001_alloc(struct pm8001_hba_info *pm8001_ha,
 247                         const struct pci_device_id *ent)
 248 {
 249         int i;
 250         spin_lock_init(&pm8001_ha->lock);
 251         spin_lock_init(&pm8001_ha->bitmap_lock);
 252         PM8001_INIT_DBG(pm8001_ha,
 253                 pm8001_printk("pm8001_alloc: PHY:%x\n",
 254                                 pm8001_ha->chip->n_phy));
 255         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
 256                 pm8001_phy_init(pm8001_ha, i);
 257                 pm8001_ha->port[i].wide_port_phymap = 0;
 258                 pm8001_ha->port[i].port_attached = 0;
 259                 pm8001_ha->port[i].port_state = 0;
 260                 INIT_LIST_HEAD(&pm8001_ha->port[i].list);
 261         }
 262
 263         pm8001_ha->tags = kzalloc(PM8001_MAX_CCB, GFP_KERNEL);
 264         if (!pm8001_ha->tags)
 265                 goto err_out;
 266         /* MPI Memory region 1 for AAP Event Log for fw */
 267         pm8001_ha->memoryMap.region[AAP1].num_elements = 1;
 268         pm8001_ha->memoryMap.region[AAP1].element_size = PM8001_EVENT_LOG_SIZE;
 269         pm8001_ha->memoryMap.region[AAP1].total_len = PM8001_EVENT_LOG_SIZE;
 270         pm8001_ha->memoryMap.region[AAP1].alignment = 32;
 271
 272         /* MPI Memory region 2 for IOP Event Log for fw */
 273         pm8001_ha->memoryMap.region[IOP].num_elements = 1;
 274         pm8001_ha->memoryMap.region[IOP].element_size = PM8001_EVENT_LOG_SIZE;
 275         pm8001_ha->memoryMap.region[IOP].total_len = PM8001_EVENT_LOG_SIZE;
 276         pm8001_ha->memoryMap.region[IOP].alignment = 32;
 277
 278         for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) {
 279                 /* MPI Memory region 3 for consumer Index of inbound queues */
 280                 pm8001_ha->memoryMap.region[CI+i].num_elements = 1;
 281                 pm8001_ha->memoryMap.region[CI+i].element_size = 4;
 282                 pm8001_ha->memoryMap.region[CI+i].total_len = 4;
 283                 pm8001_ha->memoryMap.region[CI+i].alignment = 4;
 284
 285                 if ((ent->driver_data) != chip_8001) {
 286                         /* MPI Memory region 5 inbound queues */
 287                         pm8001_ha->memoryMap.region[IB+i].num_elements =
 288                                                 PM8001_MPI_QUEUE;
 289                         pm8001_ha->memoryMap.region[IB+i].element_size = 128;
 290                         pm8001_ha->memoryMap.region[IB+i].total_len =
 291                                                 PM8001_MPI_QUEUE * 128;
 292                         pm8001_ha->memoryMap.region[IB+i].alignment = 128;
 293                 } else {
 294                         pm8001_ha->memoryMap.region[IB+i].num_elements =
 295                                                 PM8001_MPI_QUEUE;
 296                         pm8001_ha->memoryMap.region[IB+i].element_size = 64;
 297                         pm8001_ha->memoryMap.region[IB+i].total_len =
 298                                                 PM8001_MPI_QUEUE * 64;
 299                         pm8001_ha->memoryMap.region[IB+i].alignment = 64;
 300                 }
 301         }
 302
 303         for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) {
 304                 /* MPI Memory region 4 for producer Index of outbound queues */
 305                 pm8001_ha->memoryMap.region[PI+i].num_elements = 1;
 306                 pm8001_ha->memoryMap.region[PI+i].element_size = 4;
 307                 pm8001_ha->memoryMap.region[PI+i].total_len = 4;
 308                 pm8001_ha->memoryMap.region[PI+i].alignment = 4;
 309
 310                 if (ent->driver_data != chip_8001) {
 311                         /* MPI Memory region 6 Outbound queues */
 312                         pm8001_ha->memoryMap.region[OB+i].num_elements =
 313                                                 PM8001_MPI_QUEUE;
 314                         pm8001_ha->memoryMap.region[OB+i].element_size = 128;
 315                         pm8001_ha->memoryMap.region[OB+i].total_len =
 316                                                 PM8001_MPI_QUEUE * 128;
 317                         pm8001_ha->memoryMap.region[OB+i].alignment = 128;
 318                 } else {
 319                         /* MPI Memory region 6 Outbound queues */
 320                         pm8001_ha->memoryMap.region[OB+i].num_elements =
 321                                                 PM8001_MPI_QUEUE;
 322                         pm8001_ha->memoryMap.region[OB+i].element_size = 64;
 323                         pm8001_ha->memoryMap.region[OB+i].total_len =
 324                                                 PM8001_MPI_QUEUE * 64;
 325                         pm8001_ha->memoryMap.region[OB+i].alignment = 64;
 326                 }
 327
 328         }
 329         /* Memory region write DMA*/
 330         pm8001_ha->memoryMap.region[NVMD].num_elements = 1;
 331         pm8001_ha->memoryMap.region[NVMD].element_size = 4096;
 332         pm8001_ha->memoryMap.region[NVMD].total_len = 4096;
 333         /* Memory region for devices*/
 334         pm8001_ha->memoryMap.region[DEV_MEM].num_elements = 1;
 335         pm8001_ha->memoryMap.region[DEV_MEM].element_size = PM8001_MAX_DEVICES *
 336                 sizeof(struct pm8001_device);
 337         pm8001_ha->memoryMap.region[DEV_MEM].total_len = PM8001_MAX_DEVICES *
 338                 sizeof(struct pm8001_device);
 339
 340         /* Memory region for ccb_info*/
 341         pm8001_ha->memoryMap.region[CCB_MEM].num_elements = 1;
 342         pm8001_ha->memoryMap.region[CCB_MEM].element_size = PM8001_MAX_CCB *
 343                 sizeof(struct pm8001_ccb_info);
 344         pm8001_ha->memoryMap.region[CCB_MEM].total_len = PM8001_MAX_CCB *
 345                 sizeof(struct pm8001_ccb_info);
 346
 347         /* Memory region for fw flash */
 348         pm8001_ha->memoryMap.region[FW_FLASH].total_len = 4096;
 349
 350         pm8001_ha->memoryMap.region[FORENSIC_MEM].num_elements = 1;
 351         pm8001_ha->memoryMap.region[FORENSIC_MEM].total_len = 0x10000;
 352         pm8001_ha->memoryMap.region[FORENSIC_MEM].element_size = 0x10000;
 353         pm8001_ha->memoryMap.region[FORENSIC_MEM].alignment = 0x10000;
 354         for (i = 0; i < USI_MAX_MEMCNT; i++) {
 355                 if (pm8001_mem_alloc(pm8001_ha->pdev,
 356                         &pm8001_ha->memoryMap.region[i].virt_ptr,
 357                         &pm8001_ha->memoryMap.region[i].phys_addr,
 358                         &pm8001_ha->memoryMap.region[i].phys_addr_hi,
 359                         &pm8001_ha->memoryMap.region[i].phys_addr_lo,
 360                         pm8001_ha->memoryMap.region[i].total_len,
 361                         pm8001_ha->memoryMap.region[i].alignment) != 0) {
 362                                 PM8001_FAIL_DBG(pm8001_ha,
 363                                         pm8001_printk("Mem%d alloc failed\n",
 364                                         i));
 365                                 goto err_out;
 366                 }
 367         }
 368
 369         pm8001_ha->devices = pm8001_ha->memoryMap.region[DEV_MEM].virt_ptr;
 370         for (i = 0; i < PM8001_MAX_DEVICES; i++) {
 371                 pm8001_ha->devices[i].dev_type = SAS_PHY_UNUSED;
 372                 pm8001_ha->devices[i].id = i;
 373                 pm8001_ha->devices[i].device_id = PM8001_MAX_DEVICES;
 374                 pm8001_ha->devices[i].running_req = 0;
 375         }
 376         pm8001_ha->ccb_info = pm8001_ha->memoryMap.region[CCB_MEM].virt_ptr;
 377         for (i = 0; i < PM8001_MAX_CCB; i++) {
 378                 pm8001_ha->ccb_info[i].ccb_dma_handle =
 379                         pm8001_ha->memoryMap.region[CCB_MEM].phys_addr +
 380                         i * sizeof(struct pm8001_ccb_info);
 381                 pm8001_ha->ccb_info[i].task = NULL;
 382                 pm8001_ha->ccb_info[i].ccb_tag = 0xffffffff;
 383                 pm8001_ha->ccb_info[i].device = NULL;
 384                 ++pm8001_ha->tags_num;
 385         }
 386         pm8001_ha->flags = PM8001F_INIT_TIME;
 387         /* Initialize tags */
 388         pm8001_tag_init(pm8001_ha);
 389         return 0;
 390 err_out:
 391         return 1;
 392 }
 393
 394 /**
 395  * pm8001_ioremap - remap the pci high physical address to kernal virtual
 396  * address so that we can access them.
 397  * @pm8001_ha:our hba structure.
 398  */
 399 static int pm8001_ioremap(struct pm8001_hba_info *pm8001_ha)
 400 {
 401         u32 bar;
 402         u32 logicalBar = 0;
 403         struct pci_dev *pdev;
 404
 405         pdev = pm8001_ha->pdev;
 406         /* map pci mem (PMC pci base 0-3)*/
 407         for (bar = 0; bar < 6; bar++) {
 408                 /*
 409                 ** logical BARs for SPC:
 410                 ** bar 0 and 1 - logical BAR0
 411                 ** bar 2 and 3 - logical BAR1
 412                 ** bar4 - logical BAR2
 413                 ** bar5 - logical BAR3
 414                 ** Skip the appropriate assignments:
 415                 */
 416                 if ((bar == 1) || (bar == 3))
 417                         continue;
 418                 if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
 419                         pm8001_ha->io_mem[logicalBar].membase =
 420                                 pci_resource_start(pdev, bar);
 421                         pm8001_ha->io_mem[logicalBar].membase &=
 422                                 (u32)PCI_BASE_ADDRESS_MEM_MASK;
 423                         pm8001_ha->io_mem[logicalBar].memsize =
 424                                 pci_resource_len(pdev, bar);
 425                         pm8001_ha->io_mem[logicalBar].memvirtaddr =
 426                                 ioremap(pm8001_ha->io_mem[logicalBar].membase,
 427                                 pm8001_ha->io_mem[logicalBar].memsize);
 428                         PM8001_INIT_DBG(pm8001_ha,
 429                                 pm8001_printk("PCI: bar %d, logicalBar %d ",
 430                                 bar, logicalBar));
 431                         PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
 432                                 "base addr %llx virt_addr=%llx len=%d\n",
 433                                 (u64)pm8001_ha->io_mem[logicalBar].membase,
 434                                 (u64)(unsigned long)
 435                                 pm8001_ha->io_mem[logicalBar].memvirtaddr,
 436                                 pm8001_ha->io_mem[logicalBar].memsize));
 437                 } else {
 438                         pm8001_ha->io_mem[logicalBar].membase   = 0;
 439                         pm8001_ha->io_mem[logicalBar].memsize   = 0;
 440                         pm8001_ha->io_mem[logicalBar].memvirtaddr = 0;
 441                 }
 442                 logicalBar++;
 443         }
 444         return 0;
 445 }
 446
 447 /**
 448  * pm8001_pci_alloc - initialize our ha card structure
 449  * @pdev: pci device.
 450  * @ent: ent
 451  * @shost: scsi host struct which has been initialized before.
 452  */
 453 static struct pm8001_hba_info *pm8001_pci_alloc(struct pci_dev *pdev,
 454                                  const struct pci_device_id *ent,
 455                                 struct Scsi_Host *shost)
 456
 457 {
 458         struct pm8001_hba_info *pm8001_ha;
 459         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
 460         int j;
 461
 462         pm8001_ha = sha->lldd_ha;
 463         if (!pm8001_ha)
 464                 return NULL;
 465
 466         pm8001_ha->pdev = pdev;
 467         pm8001_ha->dev = &pdev->dev;
 468         pm8001_ha->chip_id = ent->driver_data;
 469         pm8001_ha->chip = &pm8001_chips[pm8001_ha->chip_id];
 470         pm8001_ha->irq = pdev->irq;
 471         pm8001_ha->sas = sha;
 472         pm8001_ha->shost = shost;
 473         pm8001_ha->id = pm8001_id++;
 474         pm8001_ha->logging_level = 0x01;
 475         sprintf(pm8001_ha->name, "%s%d", DRV_NAME, pm8001_ha->id);
 476         /* IOMB size is 128 for 8088/89 controllers */
 477         if (pm8001_ha->chip_id != chip_8001)
 478                 pm8001_ha->iomb_size = IOMB_SIZE_SPCV;
 479         else
 480                 pm8001_ha->iomb_size = IOMB_SIZE_SPC;
 481
 482 #ifdef PM8001_USE_TASKLET
 483         /* Tasklet for non msi-x interrupt handler */
 484         if ((!pdev->msix_cap) || (pm8001_ha->chip_id == chip_8001))
 485                 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet,
 486                         (unsigned long)&(pm8001_ha->irq_vector[0]));
 487         else
 488                 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
 489                         tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet,
 490                                 (unsigned long)&(pm8001_ha->irq_vector[j]));
 491 #endif
 492         pm8001_ioremap(pm8001_ha);
 493         if (!pm8001_alloc(pm8001_ha, ent))
 494                 return pm8001_ha;
 495         pm8001_free(pm8001_ha);
 496         return NULL;
 497 }
 498
 499 /**
 500  * pci_go_44 - pm8001 specified, its DMA is 44 bit rather than 64 bit
 501  * @pdev: pci device.
 502  */
 503 static int pci_go_44(struct pci_dev *pdev)
 504 {
 505         int rc;
 506
 507         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(44))) {
 508                 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(44));
 509                 if (rc) {
 510                         rc = pci_set_consistent_dma_mask(pdev,
 511                                 DMA_BIT_MASK(32));
 512                         if (rc) {
 513                                 dev_printk(KERN_ERR, &pdev->dev,
 514                                         "44-bit DMA enable failed\n");
 515                                 return rc;
 516                         }
 517                 }
 518         } else {
 519                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
 520                 if (rc) {
 521                         dev_printk(KERN_ERR, &pdev->dev,
 522                                 "32-bit DMA enable failed\n");
 523                         return rc;
 524                 }
 525                 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
 526                 if (rc) {
 527                         dev_printk(KERN_ERR, &pdev->dev,
 528                                 "32-bit consistent DMA enable failed\n");
 529                         return rc;
 530                 }
 531         }
 532         return rc;
 533 }
 534
 535 /**
 536  * pm8001_prep_sas_ha_init - allocate memory in general hba struct && init them.
 537  * @shost: scsi host which has been allocated outside.
 538  * @chip_info: our ha struct.
 539  */
 540 static int pm8001_prep_sas_ha_init(struct Scsi_Host *shost,
 541                                    const struct pm8001_chip_info *chip_info)
 542 {
 543         int phy_nr, port_nr;
 544         struct asd_sas_phy **arr_phy;
 545         struct asd_sas_port **arr_port;
 546         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
 547
 548         phy_nr = chip_info->n_phy;
 549         port_nr = phy_nr;
 550         memset(sha, 0x00, sizeof(*sha));
 551         arr_phy = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL);
 552         if (!arr_phy)
 553                 goto exit;
 554         arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL);
 555         if (!arr_port)
 556                 goto exit_free2;
 557
 558         sha->sas_phy = arr_phy;
 559         sha->sas_port = arr_port;
 560         sha->lldd_ha = kzalloc(sizeof(struct pm8001_hba_info), GFP_KERNEL);
 561         if (!sha->lldd_ha)
 562                 goto exit_free1;
 563
 564         shost->transportt = pm8001_stt;
 565         shost->max_id = PM8001_MAX_DEVICES;
 566         shost->max_lun = 8;
 567         shost->max_channel = 0;
 568         shost->unique_id = pm8001_id;
 569         shost->max_cmd_len = 16;
 570         shost->can_queue = PM8001_CAN_QUEUE;
 571         shost->cmd_per_lun = 32;
 572         return 0;
 573 exit_free1:
 574         kfree(arr_port);
 575 exit_free2:
 576         kfree(arr_phy);
 577 exit:
 578         return -1;
 579 }
 580
 581 /**
 582  * pm8001_post_sas_ha_init - initialize general hba struct defined in libsas
 583  * @shost: scsi host which has been allocated outside
 584  * @chip_info: our ha struct.
 585  */
 586 static void  pm8001_post_sas_ha_init(struct Scsi_Host *shost,
 587                                      const struct pm8001_chip_info *chip_info)
 588 {
 589         int i = 0;
 590         struct pm8001_hba_info *pm8001_ha;
 591         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
 592
 593         pm8001_ha = sha->lldd_ha;
 594         for (i = 0; i < chip_info->n_phy; i++) {
 595                 sha->sas_phy[i] = &pm8001_ha->phy[i].sas_phy;
 596                 sha->sas_port[i] = &pm8001_ha->port[i].sas_port;
 597         }
 598         sha->sas_ha_name = DRV_NAME;
 599         sha->dev = pm8001_ha->dev;
 600
 601         sha->lldd_module = THIS_MODULE;
 602         sha->sas_addr = &pm8001_ha->sas_addr[0];
 603         sha->num_phys = chip_info->n_phy;
 604         sha->lldd_max_execute_num = 1;
 605         sha->lldd_queue_size = PM8001_CAN_QUEUE;
 606         sha->core.shost = shost;
 607 }
 608
 609 /**
 610  * pm8001_init_sas_add - initialize sas address
 611  * @chip_info: our ha struct.
 612  *
 613  * Currently we just set the fixed SAS address to our HBA,for manufacture,
 614  * it should read from the EEPROM
 615  */
 616 static void pm8001_init_sas_add(struct pm8001_hba_info *pm8001_ha)
 617 {
 618         u8 i, j;
 619 #ifdef PM8001_READ_VPD
 620         /* For new SPC controllers WWN is stored in flash vpd
 621         *  For SPC/SPCve controllers WWN is stored in EEPROM
 622         *  For Older SPC WWN is stored in NVMD
 623         */
 624         DECLARE_COMPLETION_ONSTACK(completion);
 625         struct pm8001_ioctl_payload payload;
 626         u16 deviceid;
 627         int rc;
 628
 629         pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid);
 630         pm8001_ha->nvmd_completion = &completion;
 631
 632         if (pm8001_ha->chip_id == chip_8001) {
 633                 if (deviceid == 0x8081 || deviceid == 0x0042) {
 634                         payload.minor_function = 4;
 635                         payload.length = 4096;
 636                 } else {
 637                         payload.minor_function = 0;
 638                         payload.length = 128;
 639                 }
 640         } else {
 641                 payload.minor_function = 1;
 642                 payload.length = 4096;
 643         }
 644         payload.offset = 0;
 645         payload.func_specific = kzalloc(payload.length, GFP_KERNEL);
 646         if (!payload.func_specific) {
 647                 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("mem alloc fail\n"));
 648                 return;
 649         }
 650         rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
 651         if (rc) {
 652                 kfree(payload.func_specific);
 653                 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("nvmd failed\n"));
 654                 return;
 655         }
 656         wait_for_completion(&completion);
 657
 658         for (i = 0, j = 0; i <= 7; i++, j++) {
 659                 if (pm8001_ha->chip_id == chip_8001) {
 660                         if (deviceid == 0x8081)
 661                                 pm8001_ha->sas_addr[j] =
 662                                         payload.func_specific[0x704 + i];
 663                         else if (deviceid == 0x0042)
 664                                 pm8001_ha->sas_addr[j] =
 665                                         payload.func_specific[0x010 + i];
 666                 } else
 667                         pm8001_ha->sas_addr[j] =
 668                                         payload.func_specific[0x804 + i];
 669         }
 670
 671         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
 672                 memcpy(&pm8001_ha->phy[i].dev_sas_addr,
 673                         pm8001_ha->sas_addr, SAS_ADDR_SIZE);
 674                 PM8001_INIT_DBG(pm8001_ha,
 675                         pm8001_printk("phy %d sas_addr = %016llx\n", i,
 676                         pm8001_ha->phy[i].dev_sas_addr));
 677         }
 678         kfree(payload.func_specific);
 679 #else
 680         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
 681                 pm8001_ha->phy[i].dev_sas_addr = 0x50010c600047f9d0ULL;
 682                 pm8001_ha->phy[i].dev_sas_addr =
 683                         cpu_to_be64((u64)
 684                                 (*(u64 *)&pm8001_ha->phy[i].dev_sas_addr));
 685         }
 686         memcpy(pm8001_ha->sas_addr, &pm8001_ha->phy[0].dev_sas_addr,
 687                 SAS_ADDR_SIZE);
 688 #endif
 689 }
 690
 691 /*
 692  * pm8001_get_phy_settings_info : Read phy setting values.
 693  * @pm8001_ha : our hba.
 694  */
 695 static int pm8001_get_phy_settings_info(struct pm8001_hba_info *pm8001_ha)
 696 {
 697
 698 #ifdef PM8001_READ_VPD
 699         /*OPTION ROM FLASH read for the SPC cards */
 700         DECLARE_COMPLETION_ONSTACK(completion);
 701         struct pm8001_ioctl_payload payload;
 702         int rc;
 703
 704         pm8001_ha->nvmd_completion = &completion;
 705         /* SAS ADDRESS read from flash / EEPROM */
 706         payload.minor_function = 6;
 707         payload.offset = 0;
 708         payload.length = 4096;
 709         payload.func_specific = kzalloc(4096, GFP_KERNEL);
 710         if (!payload.func_specific)
 711                 return -ENOMEM;
 712         /* Read phy setting values from flash */
 713         rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
 714         if (rc) {
 715                 kfree(payload.func_specific);
 716                 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("nvmd failed\n"));
 717                 return -ENOMEM;
 718         }
 719         wait_for_completion(&completion);
 720         pm8001_set_phy_profile(pm8001_ha, sizeof(u8), payload.func_specific);
 721         kfree(payload.func_specific);
 722 #endif
 723         return 0;
 724 }
 725
 726 #ifdef PM8001_USE_MSIX
 727 /**
 728  * pm8001_setup_msix - enable MSI-X interrupt
 729  * @chip_info: our ha struct.
 730  * @irq_handler: irq_handler
 731  */
 732 static u32 pm8001_setup_msix(struct pm8001_hba_info *pm8001_ha)
 733 {
 734         u32 i = 0, j = 0;
 735         u32 number_of_intr;
 736         int flag = 0;
 737         u32 max_entry;
 738         int rc;
 739         static char intr_drvname[PM8001_MAX_MSIX_VEC][sizeof(DRV_NAME)+3];
 740
 741         /* SPCv controllers supports 64 msi-x */
 742         if (pm8001_ha->chip_id == chip_8001) {
 743                 number_of_intr = 1;
 744         } else {
 745                 number_of_intr = PM8001_MAX_MSIX_VEC;
 746                 flag &= ~IRQF_SHARED;
 747         }
 748
 749         max_entry = sizeof(pm8001_ha->msix_entries) /
 750                 sizeof(pm8001_ha->msix_entries[0]);
 751         for (i = 0; i < max_entry ; i++)
 752                 pm8001_ha->msix_entries[i].entry = i;
 753         rc = pci_enable_msix_exact(pm8001_ha->pdev, pm8001_ha->msix_entries,
 754                 number_of_intr);
 755         pm8001_ha->number_of_intr = number_of_intr;
 756         if (rc)
 757                 return rc;
 758
 759         PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
 760                 "pci_enable_msix_exact request ret:%d no of intr %d\n",
 761                                 rc, pm8001_ha->number_of_intr));
 762
 763         for (i = 0; i < number_of_intr; i++) {
 764                 snprintf(intr_drvname[i], sizeof(intr_drvname[0]),
 765                                 DRV_NAME"%d", i);
 766                 pm8001_ha->irq_vector[i].irq_id = i;
 767                 pm8001_ha->irq_vector[i].drv_inst = pm8001_ha;
 768
 769                 rc = request_irq(pm8001_ha->msix_entries[i].vector,
 770                         pm8001_interrupt_handler_msix, flag,
 771                         intr_drvname[i], &(pm8001_ha->irq_vector[i]));
 772                 if (rc) {
 773                         for (j = 0; j < i; j++) {
 774                                 free_irq(pm8001_ha->msix_entries[j].vector,
 775                                         &(pm8001_ha->irq_vector[i]));
 776                         }
 777                         pci_disable_msix(pm8001_ha->pdev);
 778                         break;
 779                 }
 780         }
 781
 782         return rc;
 783 }
 784 #endif
 785
 786 /**
 787  * pm8001_request_irq - register interrupt
 788  * @chip_info: our ha struct.
 789  */
 790 static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha)
 791 {
 792         struct pci_dev *pdev;
 793         int rc;
 794
 795         pdev = pm8001_ha->pdev;
 796
 797 #ifdef PM8001_USE_MSIX
 798         if (pdev->msix_cap)
 799                 return pm8001_setup_msix(pm8001_ha);
 800         else {
 801                 PM8001_INIT_DBG(pm8001_ha,
 802                         pm8001_printk("MSIX not supported!!!\n"));
 803                 goto intx;
 804         }
 805 #endif
 806
 807 intx:
 808         /* initialize the INT-X interrupt */
 809         rc = request_irq(pdev->irq, pm8001_interrupt_handler_intx, IRQF_SHARED,
 810                 DRV_NAME, SHOST_TO_SAS_HA(pm8001_ha->shost));
 811         return rc;
 812 }
 813
 814 /**
 815  * pm8001_pci_probe - probe supported device
 816  * @pdev: pci device which kernel has been prepared for.
 817  * @ent: pci device id
 818  *
 819  * This function is the main initialization function, when register a new
 820  * pci driver it is invoked, all struct an hardware initilization should be done
 821  * here, also, register interrupt
 822  */
 823 static int pm8001_pci_probe(struct pci_dev *pdev,
 824                             const struct pci_device_id *ent)
 825 {
 826         unsigned int rc;
 827         u32     pci_reg;
 828         u8      i = 0;
 829         struct pm8001_hba_info *pm8001_ha;
 830         struct Scsi_Host *shost = NULL;
 831         const struct pm8001_chip_info *chip;
 832
 833         dev_printk(KERN_INFO, &pdev->dev,
 834                 "pm80xx: driver version %s\n", DRV_VERSION);
 835         rc = pci_enable_device(pdev);
 836         if (rc)
 837                 goto err_out_enable;
 838         pci_set_master(pdev);
 839         /*
 840          * Enable pci slot busmaster by setting pci command register.
 841          * This is required by FW for Cyclone card.
 842          */
 843
 844         pci_read_config_dword(pdev, PCI_COMMAND, &pci_reg);
 845         pci_reg |= 0x157;
 846         pci_write_config_dword(pdev, PCI_COMMAND, pci_reg);
 847         rc = pci_request_regions(pdev, DRV_NAME);
 848         if (rc)
 849                 goto err_out_disable;
 850         rc = pci_go_44(pdev);
 851         if (rc)
 852                 goto err_out_regions;
 853
 854         shost = scsi_host_alloc(&pm8001_sht, sizeof(void *));
 855         if (!shost) {
 856                 rc = -ENOMEM;
 857                 goto err_out_regions;
 858         }
 859         chip = &pm8001_chips[ent->driver_data];
 860         SHOST_TO_SAS_HA(shost) =
 861                 kzalloc(sizeof(struct sas_ha_struct), GFP_KERNEL);
 862         if (!SHOST_TO_SAS_HA(shost)) {
 863                 rc = -ENOMEM;
 864                 goto err_out_free_host;
 865         }
 866
 867         rc = pm8001_prep_sas_ha_init(shost, chip);
 868         if (rc) {
 869                 rc = -ENOMEM;
 870                 goto err_out_free;
 871         }
 872         pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost));
 873         /* ent->driver variable is used to differentiate between controllers */
 874         pm8001_ha = pm8001_pci_alloc(pdev, ent, shost);
 875         if (!pm8001_ha) {
 876                 rc = -ENOMEM;
 877                 goto err_out_free;
 878         }
 879         list_add_tail(&pm8001_ha->list, &hba_list);
 880         PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
 881         rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
 882         if (rc) {
 883                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
 884                         "chip_init failed [ret: %d]\n", rc));
 885                 goto err_out_ha_free;
 886         }
 887
 888         rc = scsi_add_host(shost, &pdev->dev);
 889         if (rc)
 890                 goto err_out_ha_free;
 891         rc = pm8001_request_irq(pm8001_ha);
 892         if (rc) {
 893                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
 894                         "pm8001_request_irq failed [ret: %d]\n", rc));
 895                 goto err_out_shost;
 896         }
 897
 898         PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
 899         if (pm8001_ha->chip_id != chip_8001) {
 900                 for (i = 1; i < pm8001_ha->number_of_intr; i++)
 901                         PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
 902                 /* setup thermal configuration. */
 903                 pm80xx_set_thermal_config(pm8001_ha);
 904         }
 905
 906         pm8001_init_sas_add(pm8001_ha);
 907         /* phy setting support for motherboard controller */
 908         if (pdev->subsystem_vendor != PCI_VENDOR_ID_ADAPTEC2 &&
 909                 pdev->subsystem_vendor != 0) {
 910                 rc = pm8001_get_phy_settings_info(pm8001_ha);
 911                 if (rc)
 912                         goto err_out_shost;
 913         }
 914         pm8001_post_sas_ha_init(shost, chip);
 915         rc = sas_register_ha(SHOST_TO_SAS_HA(shost));
 916         if (rc)
 917                 goto err_out_shost;
 918         scsi_scan_host(pm8001_ha->shost);
 919         return 0;
 920
 921 err_out_shost:
 922         scsi_remove_host(pm8001_ha->shost);
 923 err_out_ha_free:
 924         pm8001_free(pm8001_ha);
 925 err_out_free:
 926         kfree(SHOST_TO_SAS_HA(shost));
 927 err_out_free_host:
 928         kfree(shost);
 929 err_out_regions:
 930         pci_release_regions(pdev);
 931 err_out_disable:
 932         pci_disable_device(pdev);
 933 err_out_enable:
 934         return rc;
 935 }
 936
 937 static void pm8001_pci_remove(struct pci_dev *pdev)
 938 {
 939         struct sas_ha_struct *sha = pci_get_drvdata(pdev);
 940         struct pm8001_hba_info *pm8001_ha;
 941         int i, j;
 942         pm8001_ha = sha->lldd_ha;
 943         sas_unregister_ha(sha);
 944         sas_remove_host(pm8001_ha->shost);
 945         list_del(&pm8001_ha->list);
 946         scsi_remove_host(pm8001_ha->shost);
 947         PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
 948         PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
 949
 950 #ifdef PM8001_USE_MSIX
 951         for (i = 0; i < pm8001_ha->number_of_intr; i++)
 952                 synchronize_irq(pm8001_ha->msix_entries[i].vector);
 953         for (i = 0; i < pm8001_ha->number_of_intr; i++)
 954                 free_irq(pm8001_ha->msix_entries[i].vector,
 955                                 &(pm8001_ha->irq_vector[i]));
 956         pci_disable_msix(pdev);
 957 #else
 958         free_irq(pm8001_ha->irq, sha);
 959 #endif
 960 #ifdef PM8001_USE_TASKLET
 961         /* For non-msix and msix interrupts */
 962         if ((!pdev->msix_cap) || (pm8001_ha->chip_id == chip_8001))
 963                 tasklet_kill(&pm8001_ha->tasklet[0]);
 964         else
 965                 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
 966                         tasklet_kill(&pm8001_ha->tasklet[j]);
 967 #endif
 968         pm8001_free(pm8001_ha);
 969         kfree(sha->sas_phy);
 970         kfree(sha->sas_port);
 971         kfree(sha);
 972         pci_release_regions(pdev);
 973         pci_disable_device(pdev);
 974 }
 975
 976 /**
 977  * pm8001_pci_suspend - power management suspend main entry point
 978  * @pdev: PCI device struct
 979  * @state: PM state change to (usually PCI_D3)
 980  *
 981  * Returns 0 success, anything else error.
 982  */
 983 static int pm8001_pci_suspend(struct pci_dev *pdev, pm_message_t state)
 984 {
 985         struct sas_ha_struct *sha = pci_get_drvdata(pdev);
 986         struct pm8001_hba_info *pm8001_ha;
 987         int  i, j;
 988         u32 device_state;
 989         pm8001_ha = sha->lldd_ha;
 990         sas_suspend_ha(sha);
 991         flush_workqueue(pm8001_wq);
 992         scsi_block_requests(pm8001_ha->shost);
 993         if (!pdev->pm_cap) {
 994                 dev_err(&pdev->dev, " PCI PM not supported\n");
 995                 return -ENODEV;
 996         }
 997         PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
 998         PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
 999 #ifdef PM8001_USE_MSIX
1000         for (i = 0; i < pm8001_ha->number_of_intr; i++)
1001                 synchronize_irq(pm8001_ha->msix_entries[i].vector);
1002         for (i = 0; i < pm8001_ha->number_of_intr; i++)
1003                 free_irq(pm8001_ha->msix_entries[i].vector,
1004                                 &(pm8001_ha->irq_vector[i]));
1005         pci_disable_msix(pdev);
1006 #else
1007         free_irq(pm8001_ha->irq, sha);
1008 #endif
1009 #ifdef PM8001_USE_TASKLET
1010         /* For non-msix and msix interrupts */
1011         if ((!pdev->msix_cap) || (pm8001_ha->chip_id == chip_8001))
1012                 tasklet_kill(&pm8001_ha->tasklet[0]);
1013         else
1014                 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1015                         tasklet_kill(&pm8001_ha->tasklet[j]);
1016 #endif
1017         device_state = pci_choose_state(pdev, state);
1018         pm8001_printk("pdev=0x%p, slot=%s, entering "
1019                       "operating state [D%d]\n", pdev,
1020                       pm8001_ha->name, device_state);
1021         pci_save_state(pdev);
1022         pci_disable_device(pdev);
1023         pci_set_power_state(pdev, device_state);
1024         return 0;
1025 }
1026
1027 /**
1028  * pm8001_pci_resume - power management resume main entry point
1029  * @pdev: PCI device struct
1030  *
1031  * Returns 0 success, anything else error.
1032  */
1033 static int pm8001_pci_resume(struct pci_dev *pdev)
1034 {
1035         struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1036         struct pm8001_hba_info *pm8001_ha;
1037         int rc;
1038         u8 i = 0, j;
1039         u32 device_state;
1040         DECLARE_COMPLETION_ONSTACK(completion);
1041         pm8001_ha = sha->lldd_ha;
1042         device_state = pdev->current_state;
1043
1044         pm8001_printk("pdev=0x%p, slot=%s, resuming from previous "
1045                 "operating state [D%d]\n", pdev, pm8001_ha->name, device_state);
1046
1047         pci_set_power_state(pdev, PCI_D0);
1048         pci_enable_wake(pdev, PCI_D0, 0);
1049         pci_restore_state(pdev);
1050         rc = pci_enable_device(pdev);
1051         if (rc) {
1052                 pm8001_printk("slot=%s Enable device failed during resume\n",
1053                               pm8001_ha->name);
1054                 goto err_out_enable;
1055         }
1056
1057         pci_set_master(pdev);
1058         rc = pci_go_44(pdev);
1059         if (rc)
1060                 goto err_out_disable;
1061         sas_prep_resume_ha(sha);
1062         /* chip soft rst only for spc */
1063         if (pm8001_ha->chip_id == chip_8001) {
1064                 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1065                 PM8001_INIT_DBG(pm8001_ha,
1066                         pm8001_printk("chip soft reset successful\n"));
1067         }
1068         rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
1069         if (rc)
1070                 goto err_out_disable;
1071
1072         /* disable all the interrupt bits */
1073         PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1074
1075         rc = pm8001_request_irq(pm8001_ha);
1076         if (rc)
1077                 goto err_out_disable;
1078 #ifdef PM8001_USE_TASKLET
1079         /*  Tasklet for non msi-x interrupt handler */
1080         if ((!pdev->msix_cap) || (pm8001_ha->chip_id == chip_8001))
1081                 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet,
1082                         (unsigned long)&(pm8001_ha->irq_vector[0]));
1083         else
1084                 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1085                         tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet,
1086                                 (unsigned long)&(pm8001_ha->irq_vector[j]));
1087 #endif
1088         PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
1089         if (pm8001_ha->chip_id != chip_8001) {
1090                 for (i = 1; i < pm8001_ha->number_of_intr; i++)
1091                         PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
1092         }
1093         pm8001_ha->flags = PM8001F_RUN_TIME;
1094         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
1095                 pm8001_ha->phy[i].enable_completion = &completion;
1096                 PM8001_CHIP_DISP->phy_start_req(pm8001_ha, i);
1097                 wait_for_completion(&completion);
1098         }
1099         sas_resume_ha(sha);
1100         return 0;
1101
1102 err_out_disable:
1103         scsi_remove_host(pm8001_ha->shost);
1104         pci_disable_device(pdev);
1105 err_out_enable:
1106         return rc;
1107 }
1108
1109 /* update of pci device, vendor id and driver data with
1110  * unique value for each of the controller
1111  */
1112 static struct pci_device_id pm8001_pci_table[] = {
1113         { PCI_VDEVICE(PMC_Sierra, 0x8001), chip_8001 },
1114         { PCI_VDEVICE(ATTO, 0x0042), chip_8001 },
1115         /* Support for SPC/SPCv/SPCve controllers */
1116         { PCI_VDEVICE(ADAPTEC2, 0x8001), chip_8001 },
1117         { PCI_VDEVICE(PMC_Sierra, 0x8008), chip_8008 },
1118         { PCI_VDEVICE(ADAPTEC2, 0x8008), chip_8008 },
1119         { PCI_VDEVICE(PMC_Sierra, 0x8018), chip_8018 },
1120         { PCI_VDEVICE(ADAPTEC2, 0x8018), chip_8018 },
1121         { PCI_VDEVICE(PMC_Sierra, 0x8009), chip_8009 },
1122         { PCI_VDEVICE(ADAPTEC2, 0x8009), chip_8009 },
1123         { PCI_VDEVICE(PMC_Sierra, 0x8019), chip_8019 },
1124         { PCI_VDEVICE(ADAPTEC2, 0x8019), chip_8019 },
1125         { PCI_VDEVICE(PMC_Sierra, 0x8074), chip_8074 },
1126         { PCI_VDEVICE(ADAPTEC2, 0x8074), chip_8074 },
1127         { PCI_VDEVICE(PMC_Sierra, 0x8076), chip_8076 },
1128         { PCI_VDEVICE(ADAPTEC2, 0x8076), chip_8076 },
1129         { PCI_VDEVICE(PMC_Sierra, 0x8077), chip_8077 },
1130         { PCI_VDEVICE(ADAPTEC2, 0x8077), chip_8077 },
1131         { PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1132                 PCI_VENDOR_ID_ADAPTEC2, 0x0400, 0, 0, chip_8001 },
1133         { PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1134                 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8001 },
1135         { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1136                 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8008 },
1137         { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1138                 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8008 },
1139         { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1140                 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8009 },
1141         { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1142                 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8009 },
1143         { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1144                 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8018 },
1145         { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1146                 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8018 },
1147         { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1148                 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8019 },
1149         { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1150                 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8019 },
1151         { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1152                 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8074 },
1153         { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1154                 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8076 },
1155         { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1156                 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8077 },
1157         { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1158                 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8074 },
1159         { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1160                 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8076 },
1161         { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1162                 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8077 },
1163         { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1164                 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8076 },
1165         { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1166                 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8077 },
1167         { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1168                 PCI_VENDOR_ID_ADAPTEC2, 0x0404, 0, 0, chip_8074 },
1169         {} /* terminate list */
1170 };
1171
1172 static struct pci_driver pm8001_pci_driver = {
1173         .name           = DRV_NAME,
1174         .id_table       = pm8001_pci_table,
1175         .probe          = pm8001_pci_probe,
1176         .remove         = pm8001_pci_remove,
1177         .suspend        = pm8001_pci_suspend,
1178         .resume         = pm8001_pci_resume,
1179 };
1180
1181 /**
1182  *      pm8001_init - initialize scsi transport template
1183  */
1184 static int __init pm8001_init(void)
1185 {
1186         int rc = -ENOMEM;
1187
1188         pm8001_wq = alloc_workqueue("pm80xx", 0, 0);
1189         if (!pm8001_wq)
1190                 goto err;
1191
1192         pm8001_id = 0;
1193         pm8001_stt = sas_domain_attach_transport(&pm8001_transport_ops);
1194         if (!pm8001_stt)
1195                 goto err_wq;
1196         rc = pci_register_driver(&pm8001_pci_driver);
1197         if (rc)
1198                 goto err_tp;
1199         return 0;
1200
1201 err_tp:
1202         sas_release_transport(pm8001_stt);
1203 err_wq:
1204         destroy_workqueue(pm8001_wq);
1205 err:
1206         return rc;
1207 }
1208
1209 static void __exit pm8001_exit(void)
1210 {
1211         pci_unregister_driver(&pm8001_pci_driver);
1212         sas_release_transport(pm8001_stt);
1213         destroy_workqueue(pm8001_wq);
1214 }
1215
1216 module_init(pm8001_init);
1217 module_exit(pm8001_exit);
1218
1219 MODULE_AUTHOR("Jack Wang <jack_wang@usish.com>");
1220 MODULE_AUTHOR("Anand Kumar Santhanam <AnandKumar.Santhanam@pmcs.com>");
1221 MODULE_AUTHOR("Sangeetha Gnanasekaran <Sangeetha.Gnanasekaran@pmcs.com>");
1222 MODULE_AUTHOR("Nikith Ganigarakoppal <Nikith.Ganigarakoppal@pmcs.com>");
1223 MODULE_DESCRIPTION(
1224                 "PMC-Sierra PM8001/8081/8088/8089/8074/8076/8077 "
1225                 "SAS/SATA controller driver");
1226 MODULE_VERSION(DRV_VERSION);
1227 MODULE_LICENSE("GPL");
1228 MODULE_DEVICE_TABLE(pci, pm8001_pci_table);
1229