drivers/scsi/pm8001/pm80xx_hwi.c

   1 /*
   2  * PMC-Sierra SPCv/ve 8088/8089 SAS/SATA based host adapters driver
   3  *
   4  * Copyright (c) 2008-2009 PMC-Sierra, Inc.,
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  * notice, this list of conditions, and the following disclaimer,
  12  * without modification.
  13  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  14  * substantially similar to the "NO WARRANTY" disclaimer below
  15  * ("Disclaimer") and any redistribution must be conditioned upon
  16  * including a substantially similar Disclaimer requirement for further
  17  * binary redistribution.
  18  * 3. Neither the names of the above-listed copyright holders nor the names
  19  * of any contributors may be used to endorse or promote products derived
  20  * from this software without specific prior written permission.
  21  *
  22  * Alternatively, this software may be distributed under the terms of the
  23  * GNU General Public License ("GPL") version 2 as published by the Free
  24  * Software Foundation.
  25  *
  26  * NO WARRANTY
  27  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
  30  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  31  * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  32  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  33  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  34  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  35  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  36  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  37  * POSSIBILITY OF SUCH DAMAGES.
  38  *
  39  */
  40  #include <linux/slab.h>
  41  #include "pm8001_sas.h"
  42  #include "pm80xx_hwi.h"
  43  #include "pm8001_chips.h"
  44  #include "pm8001_ctl.h"
  45
  46 #define SMP_DIRECT 1
  47 #define SMP_INDIRECT 2
  48
  49
  50 int pm80xx_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shift_value)
  51 {
  52         u32 reg_val;
  53         unsigned long start;
  54         pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, shift_value);
  55         /* confirm the setting is written */
  56         start = jiffies + HZ; /* 1 sec */
  57         do {
  58                 reg_val = pm8001_cr32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER);
  59         } while ((reg_val != shift_value) && time_before(jiffies, start));
  60         if (reg_val != shift_value) {
  61                 PM8001_FAIL_DBG(pm8001_ha,
  62                         pm8001_printk("TIMEOUT:MEMBASE_II_SHIFT_REGISTER"
  63                         " = 0x%x\n", reg_val));
  64                 return -1;
  65         }
  66         return 0;
  67 }
  68
  69 void pm80xx_pci_mem_copy(struct pm8001_hba_info  *pm8001_ha, u32 soffset,
  70                                 const void *destination,
  71                                 u32 dw_count, u32 bus_base_number)
  72 {
  73         u32 index, value, offset;
  74         u32 *destination1;
  75         destination1 = (u32 *)destination;
  76
  77         for (index = 0; index < dw_count; index += 4, destination1++) {
  78                 offset = (soffset + index / 4);
  79                 if (offset < (64 * 1024)) {
  80                         value = pm8001_cr32(pm8001_ha, bus_base_number, offset);
  81                         *destination1 =  cpu_to_le32(value);
  82                 }
  83         }
  84         return;
  85 }
  86
  87 ssize_t pm80xx_get_fatal_dump(struct device *cdev,
  88         struct device_attribute *attr, char *buf)
  89 {
  90         struct Scsi_Host *shost = class_to_shost(cdev);
  91         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
  92         struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
  93         void __iomem *fatal_table_address = pm8001_ha->fatal_tbl_addr;
  94         u32 accum_len , reg_val, index, *temp;
  95         unsigned long start;
  96         u8 *direct_data;
  97         char *fatal_error_data = buf;
  98
  99         pm8001_ha->forensic_info.data_buf.direct_data = buf;
 100         if (pm8001_ha->chip_id == chip_8001) {
 101                 pm8001_ha->forensic_info.data_buf.direct_data +=
 102                         sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
 103                         "Not supported for SPC controller");
 104                 return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
 105                         (char *)buf;
 106         }
 107         if (pm8001_ha->forensic_info.data_buf.direct_offset == 0) {
 108                 PM8001_IO_DBG(pm8001_ha,
 109                 pm8001_printk("forensic_info TYPE_NON_FATAL..............\n"));
 110                 direct_data = (u8 *)fatal_error_data;
 111                 pm8001_ha->forensic_info.data_type = TYPE_NON_FATAL;
 112                 pm8001_ha->forensic_info.data_buf.direct_len = SYSFS_OFFSET;
 113                 pm8001_ha->forensic_info.data_buf.read_len = 0;
 114
 115                 pm8001_ha->forensic_info.data_buf.direct_data = direct_data;
 116
 117                 /* start to get data */
 118                 /* Program the MEMBASE II Shifting Register with 0x00.*/
 119                 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER,
 120                                 pm8001_ha->fatal_forensic_shift_offset);
 121                 pm8001_ha->forensic_last_offset = 0;
 122                 pm8001_ha->forensic_fatal_step = 0;
 123                 pm8001_ha->fatal_bar_loc = 0;
 124         }
 125
 126         /* Read until accum_len is retrived */
 127         accum_len = pm8001_mr32(fatal_table_address,
 128                                 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN);
 129         PM8001_IO_DBG(pm8001_ha, pm8001_printk("accum_len 0x%x\n",
 130                                                 accum_len));
 131         if (accum_len == 0xFFFFFFFF) {
 132                 PM8001_IO_DBG(pm8001_ha,
 133                         pm8001_printk("Possible PCI issue 0x%x not expected\n",
 134                                 accum_len));
 135                 return -EIO;
 136         }
 137         if (accum_len == 0 || accum_len >= 0x100000) {
 138                 pm8001_ha->forensic_info.data_buf.direct_data +=
 139                         sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
 140                                 "%08x ", 0xFFFFFFFF);
 141                 return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
 142                         (char *)buf;
 143         }
 144         temp = (u32 *)pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr;
 145         if (pm8001_ha->forensic_fatal_step == 0) {
 146 moreData:
 147                 if (pm8001_ha->forensic_info.data_buf.direct_data) {
 148                         /* Data is in bar, copy to host memory */
 149                         pm80xx_pci_mem_copy(pm8001_ha, pm8001_ha->fatal_bar_loc,
 150                          pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr,
 151                                 pm8001_ha->forensic_info.data_buf.direct_len ,
 152                                         1);
 153                 }
 154                 pm8001_ha->fatal_bar_loc +=
 155                         pm8001_ha->forensic_info.data_buf.direct_len;
 156                 pm8001_ha->forensic_info.data_buf.direct_offset +=
 157                         pm8001_ha->forensic_info.data_buf.direct_len;
 158                 pm8001_ha->forensic_last_offset +=
 159                         pm8001_ha->forensic_info.data_buf.direct_len;
 160                 pm8001_ha->forensic_info.data_buf.read_len =
 161                         pm8001_ha->forensic_info.data_buf.direct_len;
 162
 163                 if (pm8001_ha->forensic_last_offset  >= accum_len) {
 164                         pm8001_ha->forensic_info.data_buf.direct_data +=
 165                         sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
 166                                 "%08x ", 3);
 167                         for (index = 0; index < (SYSFS_OFFSET / 4); index++) {
 168                                 pm8001_ha->forensic_info.data_buf.direct_data +=
 169                                         sprintf(pm8001_ha->
 170                                          forensic_info.data_buf.direct_data,
 171                                                 "%08x ", *(temp + index));
 172                         }
 173
 174                         pm8001_ha->fatal_bar_loc = 0;
 175                         pm8001_ha->forensic_fatal_step = 1;
 176                         pm8001_ha->fatal_forensic_shift_offset = 0;
 177                         pm8001_ha->forensic_last_offset = 0;
 178                         return (char *)pm8001_ha->
 179                                 forensic_info.data_buf.direct_data -
 180                                 (char *)buf;
 181                 }
 182                 if (pm8001_ha->fatal_bar_loc < (64 * 1024)) {
 183                         pm8001_ha->forensic_info.data_buf.direct_data +=
 184                                 sprintf(pm8001_ha->
 185                                         forensic_info.data_buf.direct_data,
 186                                         "%08x ", 2);
 187                         for (index = 0; index < (SYSFS_OFFSET / 4); index++) {
 188                                 pm8001_ha->forensic_info.data_buf.direct_data +=
 189                                         sprintf(pm8001_ha->
 190                                         forensic_info.data_buf.direct_data,
 191                                         "%08x ", *(temp + index));
 192                         }
 193                         return (char *)pm8001_ha->
 194                                 forensic_info.data_buf.direct_data -
 195                                 (char *)buf;
 196                 }
 197
 198                 /* Increment the MEMBASE II Shifting Register value by 0x100.*/
 199                 pm8001_ha->forensic_info.data_buf.direct_data +=
 200                         sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
 201                                 "%08x ", 2);
 202                 for (index = 0; index < 256; index++) {
 203                         pm8001_ha->forensic_info.data_buf.direct_data +=
 204                                 sprintf(pm8001_ha->
 205                                         forensic_info.data_buf.direct_data,
 206                                                 "%08x ", *(temp + index));
 207                 }
 208                 pm8001_ha->fatal_forensic_shift_offset += 0x100;
 209                 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER,
 210                         pm8001_ha->fatal_forensic_shift_offset);
 211                 pm8001_ha->fatal_bar_loc = 0;
 212                 return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
 213                         (char *)buf;
 214         }
 215         if (pm8001_ha->forensic_fatal_step == 1) {
 216                 pm8001_ha->fatal_forensic_shift_offset = 0;
 217                 /* Read 64K of the debug data. */
 218                 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER,
 219                         pm8001_ha->fatal_forensic_shift_offset);
 220                 pm8001_mw32(fatal_table_address,
 221                         MPI_FATAL_EDUMP_TABLE_HANDSHAKE,
 222                                 MPI_FATAL_EDUMP_HANDSHAKE_RDY);
 223
 224                 /* Poll FDDHSHK  until clear  */
 225                 start = jiffies + (2 * HZ); /* 2 sec */
 226
 227                 do {
 228                         reg_val = pm8001_mr32(fatal_table_address,
 229                                         MPI_FATAL_EDUMP_TABLE_HANDSHAKE);
 230                 } while ((reg_val) && time_before(jiffies, start));
 231
 232                 if (reg_val != 0) {
 233                         PM8001_FAIL_DBG(pm8001_ha,
 234                         pm8001_printk("TIMEOUT:MEMBASE_II_SHIFT_REGISTER"
 235                         " = 0x%x\n", reg_val));
 236                         return -EIO;
 237                 }
 238
 239                 /* Read the next 64K of the debug data. */
 240                 pm8001_ha->forensic_fatal_step = 0;
 241                 if (pm8001_mr32(fatal_table_address,
 242                         MPI_FATAL_EDUMP_TABLE_STATUS) !=
 243                                 MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE) {
 244                         pm8001_mw32(fatal_table_address,
 245                                 MPI_FATAL_EDUMP_TABLE_HANDSHAKE, 0);
 246                         goto moreData;
 247                 } else {
 248                         pm8001_ha->forensic_info.data_buf.direct_data +=
 249                                 sprintf(pm8001_ha->
 250                                         forensic_info.data_buf.direct_data,
 251                                                 "%08x ", 4);
 252                         pm8001_ha->forensic_info.data_buf.read_len = 0xFFFFFFFF;
 253                         pm8001_ha->forensic_info.data_buf.direct_len =  0;
 254                         pm8001_ha->forensic_info.data_buf.direct_offset = 0;
 255                         pm8001_ha->forensic_info.data_buf.read_len = 0;
 256                 }
 257         }
 258
 259         return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
 260                 (char *)buf;
 261 }
 262
 263 /**
 264  * read_main_config_table - read the configure table and save it.
 265  * @pm8001_ha: our hba card information
 266  */
 267 static void read_main_config_table(struct pm8001_hba_info *pm8001_ha)
 268 {
 269         void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
 270
 271         pm8001_ha->main_cfg_tbl.pm80xx_tbl.signature    =
 272                 pm8001_mr32(address, MAIN_SIGNATURE_OFFSET);
 273         pm8001_ha->main_cfg_tbl.pm80xx_tbl.interface_rev =
 274                 pm8001_mr32(address, MAIN_INTERFACE_REVISION);
 275         pm8001_ha->main_cfg_tbl.pm80xx_tbl.firmware_rev =
 276                 pm8001_mr32(address, MAIN_FW_REVISION);
 277         pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_out_io   =
 278                 pm8001_mr32(address, MAIN_MAX_OUTSTANDING_IO_OFFSET);
 279         pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_sgl      =
 280                 pm8001_mr32(address, MAIN_MAX_SGL_OFFSET);
 281         pm8001_ha->main_cfg_tbl.pm80xx_tbl.ctrl_cap_flag =
 282                 pm8001_mr32(address, MAIN_CNTRL_CAP_OFFSET);
 283         pm8001_ha->main_cfg_tbl.pm80xx_tbl.gst_offset   =
 284                 pm8001_mr32(address, MAIN_GST_OFFSET);
 285         pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_queue_offset =
 286                 pm8001_mr32(address, MAIN_IBQ_OFFSET);
 287         pm8001_ha->main_cfg_tbl.pm80xx_tbl.outbound_queue_offset =
 288                 pm8001_mr32(address, MAIN_OBQ_OFFSET);
 289
 290         /* read Error Dump Offset and Length */
 291         pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset0 =
 292                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET);
 293         pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length0 =
 294                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH);
 295         pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset1 =
 296                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET);
 297         pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length1 =
 298                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH);
 299
 300         /* read GPIO LED settings from the configuration table */
 301         pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping =
 302                 pm8001_mr32(address, MAIN_GPIO_LED_FLAGS_OFFSET);
 303
 304         /* read analog Setting offset from the configuration table */
 305         pm8001_ha->main_cfg_tbl.pm80xx_tbl.analog_setup_table_offset =
 306                 pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET);
 307
 308         pm8001_ha->main_cfg_tbl.pm80xx_tbl.int_vec_table_offset =
 309                 pm8001_mr32(address, MAIN_INT_VECTOR_TABLE_OFFSET);
 310         pm8001_ha->main_cfg_tbl.pm80xx_tbl.phy_attr_table_offset =
 311                 pm8001_mr32(address, MAIN_SAS_PHY_ATTR_TABLE_OFFSET);
 312 }
 313
 314 /**
 315  * read_general_status_table - read the general status table and save it.
 316  * @pm8001_ha: our hba card information
 317  */
 318 static void read_general_status_table(struct pm8001_hba_info *pm8001_ha)
 319 {
 320         void __iomem *address = pm8001_ha->general_stat_tbl_addr;
 321         pm8001_ha->gs_tbl.pm80xx_tbl.gst_len_mpistate   =
 322                         pm8001_mr32(address, GST_GSTLEN_MPIS_OFFSET);
 323         pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state0   =
 324                         pm8001_mr32(address, GST_IQ_FREEZE_STATE0_OFFSET);
 325         pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state1   =
 326                         pm8001_mr32(address, GST_IQ_FREEZE_STATE1_OFFSET);
 327         pm8001_ha->gs_tbl.pm80xx_tbl.msgu_tcnt          =
 328                         pm8001_mr32(address, GST_MSGUTCNT_OFFSET);
 329         pm8001_ha->gs_tbl.pm80xx_tbl.iop_tcnt           =
 330                         pm8001_mr32(address, GST_IOPTCNT_OFFSET);
 331         pm8001_ha->gs_tbl.pm80xx_tbl.gpio_input_val     =
 332                         pm8001_mr32(address, GST_GPIO_INPUT_VAL);
 333         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[0] =
 334                         pm8001_mr32(address, GST_RERRINFO_OFFSET0);
 335         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[1] =
 336                         pm8001_mr32(address, GST_RERRINFO_OFFSET1);
 337         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[2] =
 338                         pm8001_mr32(address, GST_RERRINFO_OFFSET2);
 339         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[3] =
 340                         pm8001_mr32(address, GST_RERRINFO_OFFSET3);
 341         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[4] =
 342                         pm8001_mr32(address, GST_RERRINFO_OFFSET4);
 343         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[5] =
 344                         pm8001_mr32(address, GST_RERRINFO_OFFSET5);
 345         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[6] =
 346                         pm8001_mr32(address, GST_RERRINFO_OFFSET6);
 347         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[7] =
 348                          pm8001_mr32(address, GST_RERRINFO_OFFSET7);
 349 }
 350 /**
 351  * read_phy_attr_table - read the phy attribute table and save it.
 352  * @pm8001_ha: our hba card information
 353  */
 354 static void read_phy_attr_table(struct pm8001_hba_info *pm8001_ha)
 355 {
 356         void __iomem *address = pm8001_ha->pspa_q_tbl_addr;
 357         pm8001_ha->phy_attr_table.phystart1_16[0] =
 358                         pm8001_mr32(address, PSPA_PHYSTATE0_OFFSET);
 359         pm8001_ha->phy_attr_table.phystart1_16[1] =
 360                         pm8001_mr32(address, PSPA_PHYSTATE1_OFFSET);
 361         pm8001_ha->phy_attr_table.phystart1_16[2] =
 362                         pm8001_mr32(address, PSPA_PHYSTATE2_OFFSET);
 363         pm8001_ha->phy_attr_table.phystart1_16[3] =
 364                         pm8001_mr32(address, PSPA_PHYSTATE3_OFFSET);
 365         pm8001_ha->phy_attr_table.phystart1_16[4] =
 366                         pm8001_mr32(address, PSPA_PHYSTATE4_OFFSET);
 367         pm8001_ha->phy_attr_table.phystart1_16[5] =
 368                         pm8001_mr32(address, PSPA_PHYSTATE5_OFFSET);
 369         pm8001_ha->phy_attr_table.phystart1_16[6] =
 370                         pm8001_mr32(address, PSPA_PHYSTATE6_OFFSET);
 371         pm8001_ha->phy_attr_table.phystart1_16[7] =
 372                         pm8001_mr32(address, PSPA_PHYSTATE7_OFFSET);
 373         pm8001_ha->phy_attr_table.phystart1_16[8] =
 374                         pm8001_mr32(address, PSPA_PHYSTATE8_OFFSET);
 375         pm8001_ha->phy_attr_table.phystart1_16[9] =
 376                         pm8001_mr32(address, PSPA_PHYSTATE9_OFFSET);
 377         pm8001_ha->phy_attr_table.phystart1_16[10] =
 378                         pm8001_mr32(address, PSPA_PHYSTATE10_OFFSET);
 379         pm8001_ha->phy_attr_table.phystart1_16[11] =
 380                         pm8001_mr32(address, PSPA_PHYSTATE11_OFFSET);
 381         pm8001_ha->phy_attr_table.phystart1_16[12] =
 382                         pm8001_mr32(address, PSPA_PHYSTATE12_OFFSET);
 383         pm8001_ha->phy_attr_table.phystart1_16[13] =
 384                         pm8001_mr32(address, PSPA_PHYSTATE13_OFFSET);
 385         pm8001_ha->phy_attr_table.phystart1_16[14] =
 386                         pm8001_mr32(address, PSPA_PHYSTATE14_OFFSET);
 387         pm8001_ha->phy_attr_table.phystart1_16[15] =
 388                         pm8001_mr32(address, PSPA_PHYSTATE15_OFFSET);
 389
 390         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[0] =
 391                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID0_OFFSET);
 392         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[1] =
 393                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID1_OFFSET);
 394         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[2] =
 395                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID2_OFFSET);
 396         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[3] =
 397                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID3_OFFSET);
 398         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[4] =
 399                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID4_OFFSET);
 400         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[5] =
 401                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID5_OFFSET);
 402         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[6] =
 403                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID6_OFFSET);
 404         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[7] =
 405                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID7_OFFSET);
 406         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[8] =
 407                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID8_OFFSET);
 408         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[9] =
 409                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID9_OFFSET);
 410         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[10] =
 411                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID10_OFFSET);
 412         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[11] =
 413                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID11_OFFSET);
 414         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[12] =
 415                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID12_OFFSET);
 416         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[13] =
 417                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID13_OFFSET);
 418         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[14] =
 419                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID14_OFFSET);
 420         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[15] =
 421                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID15_OFFSET);
 422
 423 }
 424
 425 /**
 426  * read_inbnd_queue_table - read the inbound queue table and save it.
 427  * @pm8001_ha: our hba card information
 428  */
 429 static void read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
 430 {
 431         int i;
 432         void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
 433         for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) {
 434                 u32 offset = i * 0x20;
 435                 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
 436                         get_pci_bar_index(pm8001_mr32(address,
 437                                 (offset + IB_PIPCI_BAR)));
 438                 pm8001_ha->inbnd_q_tbl[i].pi_offset =
 439                         pm8001_mr32(address, (offset + IB_PIPCI_BAR_OFFSET));
 440         }
 441 }
 442
 443 /**
 444  * read_outbnd_queue_table - read the outbound queue table and save it.
 445  * @pm8001_ha: our hba card information
 446  */
 447 static void read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
 448 {
 449         int i;
 450         void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
 451         for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) {
 452                 u32 offset = i * 0x24;
 453                 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
 454                         get_pci_bar_index(pm8001_mr32(address,
 455                                 (offset + OB_CIPCI_BAR)));
 456                 pm8001_ha->outbnd_q_tbl[i].ci_offset =
 457                         pm8001_mr32(address, (offset + OB_CIPCI_BAR_OFFSET));
 458         }
 459 }
 460
 461 /**
 462  * init_default_table_values - init the default table.
 463  * @pm8001_ha: our hba card information
 464  */
 465 static void init_default_table_values(struct pm8001_hba_info *pm8001_ha)
 466 {
 467         int i;
 468         u32 offsetib, offsetob;
 469         void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr;
 470         void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr;
 471
 472         pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr         =
 473                 pm8001_ha->memoryMap.region[AAP1].phys_addr_hi;
 474         pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr         =
 475                 pm8001_ha->memoryMap.region[AAP1].phys_addr_lo;
 476         pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size               =
 477                                                         PM8001_EVENT_LOG_SIZE;
 478         pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity           = 0x01;
 479         pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr     =
 480                 pm8001_ha->memoryMap.region[IOP].phys_addr_hi;
 481         pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr     =
 482                 pm8001_ha->memoryMap.region[IOP].phys_addr_lo;
 483         pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size           =
 484                                                         PM8001_EVENT_LOG_SIZE;
 485         pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity       = 0x01;
 486         pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt          = 0x01;
 487
 488         /* Disable end to end CRC checking */
 489         pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump = (0x1 << 16);
 490
 491         for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) {
 492                 pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt  =
 493                         PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x00<<30);
 494                 pm8001_ha->inbnd_q_tbl[i].upper_base_addr       =
 495                         pm8001_ha->memoryMap.region[IB + i].phys_addr_hi;
 496                 pm8001_ha->inbnd_q_tbl[i].lower_base_addr       =
 497                 pm8001_ha->memoryMap.region[IB + i].phys_addr_lo;
 498                 pm8001_ha->inbnd_q_tbl[i].base_virt             =
 499                         (u8 *)pm8001_ha->memoryMap.region[IB + i].virt_ptr;
 500                 pm8001_ha->inbnd_q_tbl[i].total_length          =
 501                         pm8001_ha->memoryMap.region[IB + i].total_len;
 502                 pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr    =
 503                         pm8001_ha->memoryMap.region[CI + i].phys_addr_hi;
 504                 pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr    =
 505                         pm8001_ha->memoryMap.region[CI + i].phys_addr_lo;
 506                 pm8001_ha->inbnd_q_tbl[i].ci_virt               =
 507                         pm8001_ha->memoryMap.region[CI + i].virt_ptr;
 508                 offsetib = i * 0x20;
 509                 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar            =
 510                         get_pci_bar_index(pm8001_mr32(addressib,
 511                                 (offsetib + 0x14)));
 512                 pm8001_ha->inbnd_q_tbl[i].pi_offset             =
 513                         pm8001_mr32(addressib, (offsetib + 0x18));
 514                 pm8001_ha->inbnd_q_tbl[i].producer_idx          = 0;
 515                 pm8001_ha->inbnd_q_tbl[i].consumer_index        = 0;
 516         }
 517         for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) {
 518                 pm8001_ha->outbnd_q_tbl[i].element_size_cnt     =
 519                         PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x01<<30);
 520                 pm8001_ha->outbnd_q_tbl[i].upper_base_addr      =
 521                         pm8001_ha->memoryMap.region[OB + i].phys_addr_hi;
 522                 pm8001_ha->outbnd_q_tbl[i].lower_base_addr      =
 523                         pm8001_ha->memoryMap.region[OB + i].phys_addr_lo;
 524                 pm8001_ha->outbnd_q_tbl[i].base_virt            =
 525                         (u8 *)pm8001_ha->memoryMap.region[OB + i].virt_ptr;
 526                 pm8001_ha->outbnd_q_tbl[i].total_length         =
 527                         pm8001_ha->memoryMap.region[OB + i].total_len;
 528                 pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr   =
 529                         pm8001_ha->memoryMap.region[PI + i].phys_addr_hi;
 530                 pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr   =
 531                         pm8001_ha->memoryMap.region[PI + i].phys_addr_lo;
 532                 /* interrupt vector based on oq */
 533                 pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay = (i << 24);
 534                 pm8001_ha->outbnd_q_tbl[i].pi_virt              =
 535                         pm8001_ha->memoryMap.region[PI + i].virt_ptr;
 536                 offsetob = i * 0x24;
 537                 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar           =
 538                         get_pci_bar_index(pm8001_mr32(addressob,
 539                         offsetob + 0x14));
 540                 pm8001_ha->outbnd_q_tbl[i].ci_offset            =
 541                         pm8001_mr32(addressob, (offsetob + 0x18));
 542                 pm8001_ha->outbnd_q_tbl[i].consumer_idx         = 0;
 543                 pm8001_ha->outbnd_q_tbl[i].producer_index       = 0;
 544         }
 545 }
 546
 547 /**
 548  * update_main_config_table - update the main default table to the HBA.
 549  * @pm8001_ha: our hba card information
 550  */
 551 static void update_main_config_table(struct pm8001_hba_info *pm8001_ha)
 552 {
 553         void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
 554         pm8001_mw32(address, MAIN_IQNPPD_HPPD_OFFSET,
 555                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_q_nppd_hppd);
 556         pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_HI,
 557                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr);
 558         pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_LO,
 559                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr);
 560         pm8001_mw32(address, MAIN_EVENT_LOG_BUFF_SIZE,
 561                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size);
 562         pm8001_mw32(address, MAIN_EVENT_LOG_OPTION,
 563                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity);
 564         pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_HI,
 565                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr);
 566         pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_LO,
 567                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr);
 568         pm8001_mw32(address, MAIN_PCS_EVENT_LOG_BUFF_SIZE,
 569                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size);
 570         pm8001_mw32(address, MAIN_PCS_EVENT_LOG_OPTION,
 571                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity);
 572         pm8001_mw32(address, MAIN_FATAL_ERROR_INTERRUPT,
 573                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt);
 574         pm8001_mw32(address, MAIN_EVENT_CRC_CHECK,
 575                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump);
 576
 577         /* SPCv specific */
 578         pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping &= 0xCFFFFFFF;
 579         /* Set GPIOLED to 0x2 for LED indicator */
 580         pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping |= 0x20000000;
 581         pm8001_mw32(address, MAIN_GPIO_LED_FLAGS_OFFSET,
 582                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping);
 583
 584         pm8001_mw32(address, MAIN_PORT_RECOVERY_TIMER,
 585                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer);
 586         pm8001_mw32(address, MAIN_INT_REASSERTION_DELAY,
 587                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interrupt_reassertion_delay);
 588 }
 589
 590 /**
 591  * update_inbnd_queue_table - update the inbound queue table to the HBA.
 592  * @pm8001_ha: our hba card information
 593  */
 594 static void update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
 595                                          int number)
 596 {
 597         void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
 598         u16 offset = number * 0x20;
 599         pm8001_mw32(address, offset + IB_PROPERITY_OFFSET,
 600                 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt);
 601         pm8001_mw32(address, offset + IB_BASE_ADDR_HI_OFFSET,
 602                 pm8001_ha->inbnd_q_tbl[number].upper_base_addr);
 603         pm8001_mw32(address, offset + IB_BASE_ADDR_LO_OFFSET,
 604                 pm8001_ha->inbnd_q_tbl[number].lower_base_addr);
 605         pm8001_mw32(address, offset + IB_CI_BASE_ADDR_HI_OFFSET,
 606                 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr);
 607         pm8001_mw32(address, offset + IB_CI_BASE_ADDR_LO_OFFSET,
 608                 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr);
 609 }
 610
 611 /**
 612  * update_outbnd_queue_table - update the outbound queue table to the HBA.
 613  * @pm8001_ha: our hba card information
 614  */
 615 static void update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
 616                                                  int number)
 617 {
 618         void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
 619         u16 offset = number * 0x24;
 620         pm8001_mw32(address, offset + OB_PROPERITY_OFFSET,
 621                 pm8001_ha->outbnd_q_tbl[number].element_size_cnt);
 622         pm8001_mw32(address, offset + OB_BASE_ADDR_HI_OFFSET,
 623                 pm8001_ha->outbnd_q_tbl[number].upper_base_addr);
 624         pm8001_mw32(address, offset + OB_BASE_ADDR_LO_OFFSET,
 625                 pm8001_ha->outbnd_q_tbl[number].lower_base_addr);
 626         pm8001_mw32(address, offset + OB_PI_BASE_ADDR_HI_OFFSET,
 627                 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr);
 628         pm8001_mw32(address, offset + OB_PI_BASE_ADDR_LO_OFFSET,
 629                 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr);
 630         pm8001_mw32(address, offset + OB_INTERRUPT_COALES_OFFSET,
 631                 pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay);
 632 }
 633
 634 /**
 635  * mpi_init_check - check firmware initialization status.
 636  * @pm8001_ha: our hba card information
 637  */
 638 static int mpi_init_check(struct pm8001_hba_info *pm8001_ha)
 639 {
 640         u32 max_wait_count;
 641         u32 value;
 642         u32 gst_len_mpistate;
 643
 644         /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the
 645         table is updated */
 646         pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_UPDATE);
 647         /* wait until Inbound DoorBell Clear Register toggled */
 648         if (IS_SPCV_12G(pm8001_ha->pdev)) {
 649                 max_wait_count = 4 * 1000 * 1000;/* 4 sec */
 650         } else {
 651                 max_wait_count = 2 * 1000 * 1000;/* 2 sec */
 652         }
 653         do {
 654                 udelay(1);
 655                 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
 656                 value &= SPCv_MSGU_CFG_TABLE_UPDATE;
 657         } while ((value != 0) && (--max_wait_count));
 658
 659         if (!max_wait_count)
 660                 return -1;
 661         /* check the MPI-State for initialization upto 100ms*/
 662         max_wait_count = 100 * 1000;/* 100 msec */
 663         do {
 664                 udelay(1);
 665                 gst_len_mpistate =
 666                         pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
 667                                         GST_GSTLEN_MPIS_OFFSET);
 668         } while ((GST_MPI_STATE_INIT !=
 669                 (gst_len_mpistate & GST_MPI_STATE_MASK)) && (--max_wait_count));
 670         if (!max_wait_count)
 671                 return -1;
 672
 673         /* check MPI Initialization error */
 674         gst_len_mpistate = gst_len_mpistate >> 16;
 675         if (0x0000 != gst_len_mpistate)
 676                 return -1;
 677
 678         return 0;
 679 }
 680
 681 /**
 682  * check_fw_ready - The LLDD check if the FW is ready, if not, return error.
 683  * @pm8001_ha: our hba card information
 684  */
 685 static int check_fw_ready(struct pm8001_hba_info *pm8001_ha)
 686 {
 687         u32 value;
 688         u32 max_wait_count;
 689         u32 max_wait_time;
 690         int ret = 0;
 691
 692         /* reset / PCIe ready */
 693         max_wait_time = max_wait_count = 100 * 1000;    /* 100 milli sec */
 694         do {
 695                 udelay(1);
 696                 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
 697         } while ((value == 0xFFFFFFFF) && (--max_wait_count));
 698
 699         /* check ila status */
 700         max_wait_time = max_wait_count = 1000 * 1000;   /* 1000 milli sec */
 701         do {
 702                 udelay(1);
 703                 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
 704         } while (((value & SCRATCH_PAD_ILA_READY) !=
 705                         SCRATCH_PAD_ILA_READY) && (--max_wait_count));
 706         if (!max_wait_count)
 707                 ret = -1;
 708         else {
 709                 PM8001_MSG_DBG(pm8001_ha,
 710                         pm8001_printk(" ila ready status in %d millisec\n",
 711                                 (max_wait_time - max_wait_count)));
 712         }
 713
 714         /* check RAAE status */
 715         max_wait_time = max_wait_count = 1800 * 1000;   /* 1800 milli sec */
 716         do {
 717                 udelay(1);
 718                 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
 719         } while (((value & SCRATCH_PAD_RAAE_READY) !=
 720                                 SCRATCH_PAD_RAAE_READY) && (--max_wait_count));
 721         if (!max_wait_count)
 722                 ret = -1;
 723         else {
 724                 PM8001_MSG_DBG(pm8001_ha,
 725                         pm8001_printk(" raae ready status in %d millisec\n",
 726                                         (max_wait_time - max_wait_count)));
 727         }
 728
 729         /* check iop0 status */
 730         max_wait_time = max_wait_count = 600 * 1000;    /* 600 milli sec */
 731         do {
 732                 udelay(1);
 733                 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
 734         } while (((value & SCRATCH_PAD_IOP0_READY) != SCRATCH_PAD_IOP0_READY) &&
 735                         (--max_wait_count));
 736         if (!max_wait_count)
 737                 ret = -1;
 738         else {
 739                 PM8001_MSG_DBG(pm8001_ha,
 740                         pm8001_printk(" iop0 ready status in %d millisec\n",
 741                                 (max_wait_time - max_wait_count)));
 742         }
 743
 744         /* check iop1 status only for 16 port controllers */
 745         if ((pm8001_ha->chip_id != chip_8008) &&
 746                         (pm8001_ha->chip_id != chip_8009)) {
 747                 /* 200 milli sec */
 748                 max_wait_time = max_wait_count = 200 * 1000;
 749                 do {
 750                         udelay(1);
 751                         value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
 752                 } while (((value & SCRATCH_PAD_IOP1_READY) !=
 753                                 SCRATCH_PAD_IOP1_READY) && (--max_wait_count));
 754                 if (!max_wait_count)
 755                         ret = -1;
 756                 else {
 757                         PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
 758                                 "iop1 ready status in %d millisec\n",
 759                                 (max_wait_time - max_wait_count)));
 760                 }
 761         }
 762
 763         return ret;
 764 }
 765
 766 static void init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha)
 767 {
 768         void __iomem *base_addr;
 769         u32     value;
 770         u32     offset;
 771         u32     pcibar;
 772         u32     pcilogic;
 773
 774         value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
 775         offset = value & 0x03FFFFFF; /* scratch pad 0 TBL address */
 776
 777         PM8001_INIT_DBG(pm8001_ha,
 778                 pm8001_printk("Scratchpad 0 Offset: 0x%x value 0x%x\n",
 779                                 offset, value));
 780         pcilogic = (value & 0xFC000000) >> 26;
 781         pcibar = get_pci_bar_index(pcilogic);
 782         PM8001_INIT_DBG(pm8001_ha,
 783                 pm8001_printk("Scratchpad 0 PCI BAR: %d\n", pcibar));
 784         pm8001_ha->main_cfg_tbl_addr = base_addr =
 785                 pm8001_ha->io_mem[pcibar].memvirtaddr + offset;
 786         pm8001_ha->general_stat_tbl_addr =
 787                 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x18) &
 788                                         0xFFFFFF);
 789         pm8001_ha->inbnd_q_tbl_addr =
 790                 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C) &
 791                                         0xFFFFFF);
 792         pm8001_ha->outbnd_q_tbl_addr =
 793                 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x20) &
 794                                         0xFFFFFF);
 795         pm8001_ha->ivt_tbl_addr =
 796                 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C) &
 797                                         0xFFFFFF);
 798         pm8001_ha->pspa_q_tbl_addr =
 799                 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x90) &
 800                                         0xFFFFFF);
 801         pm8001_ha->fatal_tbl_addr =
 802                 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0xA0) &
 803                                         0xFFFFFF);
 804
 805         PM8001_INIT_DBG(pm8001_ha,
 806                         pm8001_printk("GST OFFSET 0x%x\n",
 807                         pm8001_cr32(pm8001_ha, pcibar, offset + 0x18)));
 808         PM8001_INIT_DBG(pm8001_ha,
 809                         pm8001_printk("INBND OFFSET 0x%x\n",
 810                         pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C)));
 811         PM8001_INIT_DBG(pm8001_ha,
 812                         pm8001_printk("OBND OFFSET 0x%x\n",
 813                         pm8001_cr32(pm8001_ha, pcibar, offset + 0x20)));
 814         PM8001_INIT_DBG(pm8001_ha,
 815                         pm8001_printk("IVT OFFSET 0x%x\n",
 816                         pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C)));
 817         PM8001_INIT_DBG(pm8001_ha,
 818                         pm8001_printk("PSPA OFFSET 0x%x\n",
 819                         pm8001_cr32(pm8001_ha, pcibar, offset + 0x90)));
 820         PM8001_INIT_DBG(pm8001_ha,
 821                         pm8001_printk("addr - main cfg %p general status %p\n",
 822                         pm8001_ha->main_cfg_tbl_addr,
 823                         pm8001_ha->general_stat_tbl_addr));
 824         PM8001_INIT_DBG(pm8001_ha,
 825                         pm8001_printk("addr - inbnd %p obnd %p\n",
 826                         pm8001_ha->inbnd_q_tbl_addr,
 827                         pm8001_ha->outbnd_q_tbl_addr));
 828         PM8001_INIT_DBG(pm8001_ha,
 829                         pm8001_printk("addr - pspa %p ivt %p\n",
 830                         pm8001_ha->pspa_q_tbl_addr,
 831                         pm8001_ha->ivt_tbl_addr));
 832 }
 833
 834 /**
 835  * pm80xx_set_thermal_config - support the thermal configuration
 836  * @pm8001_ha: our hba card information.
 837  */
 838 int
 839 pm80xx_set_thermal_config(struct pm8001_hba_info *pm8001_ha)
 840 {
 841         struct set_ctrl_cfg_req payload;
 842         struct inbound_queue_table *circularQ;
 843         int rc;
 844         u32 tag;
 845         u32 opc = OPC_INB_SET_CONTROLLER_CONFIG;
 846
 847         memset(&payload, 0, sizeof(struct set_ctrl_cfg_req));
 848         rc = pm8001_tag_alloc(pm8001_ha, &tag);
 849         if (rc)
 850                 return -1;
 851
 852         circularQ = &pm8001_ha->inbnd_q_tbl[0];
 853         payload.tag = cpu_to_le32(tag);
 854         payload.cfg_pg[0] = (THERMAL_LOG_ENABLE << 9) |
 855                         (THERMAL_ENABLE << 8) | THERMAL_OP_CODE;
 856         payload.cfg_pg[1] = (LTEMPHIL << 24) | (RTEMPHIL << 8);
 857
 858         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
 859         return rc;
 860
 861 }
 862
 863 /**
 864 * pm80xx_set_sas_protocol_timer_config - support the SAS Protocol
 865 * Timer configuration page
 866 * @pm8001_ha: our hba card information.
 867 */
 868 static int
 869 pm80xx_set_sas_protocol_timer_config(struct pm8001_hba_info *pm8001_ha)
 870 {
 871         struct set_ctrl_cfg_req payload;
 872         struct inbound_queue_table *circularQ;
 873         SASProtocolTimerConfig_t SASConfigPage;
 874         int rc;
 875         u32 tag;
 876         u32 opc = OPC_INB_SET_CONTROLLER_CONFIG;
 877
 878         memset(&payload, 0, sizeof(struct set_ctrl_cfg_req));
 879         memset(&SASConfigPage, 0, sizeof(SASProtocolTimerConfig_t));
 880
 881         rc = pm8001_tag_alloc(pm8001_ha, &tag);
 882
 883         if (rc)
 884                 return -1;
 885
 886         circularQ = &pm8001_ha->inbnd_q_tbl[0];
 887         payload.tag = cpu_to_le32(tag);
 888
 889         SASConfigPage.pageCode        =  SAS_PROTOCOL_TIMER_CONFIG_PAGE;
 890         SASConfigPage.MST_MSI         =  3 << 15;
 891         SASConfigPage.STP_SSP_MCT_TMO =  (STP_MCT_TMO << 16) | SSP_MCT_TMO;
 892         SASConfigPage.STP_FRM_TMO     = (SAS_MAX_OPEN_TIME << 24) |
 893                                 (SMP_MAX_CONN_TIMER << 16) | STP_FRM_TIMER;
 894         SASConfigPage.STP_IDLE_TMO    =  STP_IDLE_TIME;
 895
 896         if (SASConfigPage.STP_IDLE_TMO > 0x3FFFFFF)
 897                 SASConfigPage.STP_IDLE_TMO = 0x3FFFFFF;
 898
 899
 900         SASConfigPage.OPNRJT_RTRY_INTVL =         (SAS_MFD << 16) |
 901                                                 SAS_OPNRJT_RTRY_INTVL;
 902         SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO =  (SAS_DOPNRJT_RTRY_TMO << 16)
 903                                                 | SAS_COPNRJT_RTRY_TMO;
 904         SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR =  (SAS_DOPNRJT_RTRY_THR << 16)
 905                                                 | SAS_COPNRJT_RTRY_THR;
 906         SASConfigPage.MAX_AIP =  SAS_MAX_AIP;
 907
 908         PM8001_INIT_DBG(pm8001_ha,
 909                         pm8001_printk("SASConfigPage.pageCode "
 910                         "0x%08x\n", SASConfigPage.pageCode));
 911         PM8001_INIT_DBG(pm8001_ha,
 912                         pm8001_printk("SASConfigPage.MST_MSI "
 913                         " 0x%08x\n", SASConfigPage.MST_MSI));
 914         PM8001_INIT_DBG(pm8001_ha,
 915                         pm8001_printk("SASConfigPage.STP_SSP_MCT_TMO "
 916                         " 0x%08x\n", SASConfigPage.STP_SSP_MCT_TMO));
 917         PM8001_INIT_DBG(pm8001_ha,
 918                         pm8001_printk("SASConfigPage.STP_FRM_TMO "
 919                         " 0x%08x\n", SASConfigPage.STP_FRM_TMO));
 920         PM8001_INIT_DBG(pm8001_ha,
 921                         pm8001_printk("SASConfigPage.STP_IDLE_TMO "
 922                         " 0x%08x\n", SASConfigPage.STP_IDLE_TMO));
 923         PM8001_INIT_DBG(pm8001_ha,
 924                         pm8001_printk("SASConfigPage.OPNRJT_RTRY_INTVL "
 925                         " 0x%08x\n", SASConfigPage.OPNRJT_RTRY_INTVL));
 926         PM8001_INIT_DBG(pm8001_ha,
 927                         pm8001_printk("SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO "
 928                         " 0x%08x\n", SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO));
 929         PM8001_INIT_DBG(pm8001_ha,
 930                         pm8001_printk("SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR "
 931                         " 0x%08x\n", SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR));
 932         PM8001_INIT_DBG(pm8001_ha, pm8001_printk("SASConfigPage.MAX_AIP "
 933                         " 0x%08x\n", SASConfigPage.MAX_AIP));
 934
 935         memcpy(&payload.cfg_pg, &SASConfigPage,
 936                          sizeof(SASProtocolTimerConfig_t));
 937
 938         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
 939
 940         return rc;
 941 }
 942
 943 /**
 944  * pm80xx_get_encrypt_info - Check for encryption
 945  * @pm8001_ha: our hba card information.
 946  */
 947 static int
 948 pm80xx_get_encrypt_info(struct pm8001_hba_info *pm8001_ha)
 949 {
 950         u32 scratch3_value;
 951         int ret;
 952
 953         /* Read encryption status from SCRATCH PAD 3 */
 954         scratch3_value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
 955
 956         if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
 957                                         SCRATCH_PAD3_ENC_READY) {
 958                 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
 959                         pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
 960                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
 961                                                 SCRATCH_PAD3_SMF_ENABLED)
 962                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
 963                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
 964                                                 SCRATCH_PAD3_SMA_ENABLED)
 965                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
 966                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
 967                                                 SCRATCH_PAD3_SMB_ENABLED)
 968                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
 969                 pm8001_ha->encrypt_info.status = 0;
 970                 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
 971                         "Encryption: SCRATCH_PAD3_ENC_READY 0x%08X."
 972                         "Cipher mode 0x%x Sec mode 0x%x status 0x%x\n",
 973                         scratch3_value, pm8001_ha->encrypt_info.cipher_mode,
 974                         pm8001_ha->encrypt_info.sec_mode,
 975                         pm8001_ha->encrypt_info.status));
 976                 ret = 0;
 977         } else if ((scratch3_value & SCRATCH_PAD3_ENC_READY) ==
 978                                         SCRATCH_PAD3_ENC_DISABLED) {
 979                 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
 980                         "Encryption: SCRATCH_PAD3_ENC_DISABLED 0x%08X\n",
 981                         scratch3_value));
 982                 pm8001_ha->encrypt_info.status = 0xFFFFFFFF;
 983                 pm8001_ha->encrypt_info.cipher_mode = 0;
 984                 pm8001_ha->encrypt_info.sec_mode = 0;
 985                 return 0;
 986         } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
 987                                 SCRATCH_PAD3_ENC_DIS_ERR) {
 988                 pm8001_ha->encrypt_info.status =
 989                         (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16;
 990                 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
 991                         pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
 992                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
 993                                         SCRATCH_PAD3_SMF_ENABLED)
 994                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
 995                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
 996                                         SCRATCH_PAD3_SMA_ENABLED)
 997                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
 998                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
 999                                         SCRATCH_PAD3_SMB_ENABLED)
1000                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
1001                 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
1002                         "Encryption: SCRATCH_PAD3_DIS_ERR 0x%08X."
1003                         "Cipher mode 0x%x sec mode 0x%x status 0x%x\n",
1004                         scratch3_value, pm8001_ha->encrypt_info.cipher_mode,
1005                         pm8001_ha->encrypt_info.sec_mode,
1006                         pm8001_ha->encrypt_info.status));
1007                 ret = -1;
1008         } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
1009                                  SCRATCH_PAD3_ENC_ENA_ERR) {
1010
1011                 pm8001_ha->encrypt_info.status =
1012                         (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16;
1013                 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
1014                         pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
1015                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1016                                         SCRATCH_PAD3_SMF_ENABLED)
1017                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
1018                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1019                                         SCRATCH_PAD3_SMA_ENABLED)
1020                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
1021                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1022                                         SCRATCH_PAD3_SMB_ENABLED)
1023                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
1024
1025                 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
1026                         "Encryption: SCRATCH_PAD3_ENA_ERR 0x%08X."
1027                         "Cipher mode 0x%x sec mode 0x%x status 0x%x\n",
1028                         scratch3_value, pm8001_ha->encrypt_info.cipher_mode,
1029                         pm8001_ha->encrypt_info.sec_mode,
1030                         pm8001_ha->encrypt_info.status));
1031                 ret = -1;
1032         }
1033         return ret;
1034 }
1035
1036 /**
1037  * pm80xx_encrypt_update - update flash with encryption informtion
1038  * @pm8001_ha: our hba card information.
1039  */
1040 static int pm80xx_encrypt_update(struct pm8001_hba_info *pm8001_ha)
1041 {
1042         struct kek_mgmt_req payload;
1043         struct inbound_queue_table *circularQ;
1044         int rc;
1045         u32 tag;
1046         u32 opc = OPC_INB_KEK_MANAGEMENT;
1047
1048         memset(&payload, 0, sizeof(struct kek_mgmt_req));
1049         rc = pm8001_tag_alloc(pm8001_ha, &tag);
1050         if (rc)
1051                 return -1;
1052
1053         circularQ = &pm8001_ha->inbnd_q_tbl[0];
1054         payload.tag = cpu_to_le32(tag);
1055         /* Currently only one key is used. New KEK index is 1.
1056          * Current KEK index is 1. Store KEK to NVRAM is 1.
1057          */
1058         payload.new_curidx_ksop = ((1 << 24) | (1 << 16) | (1 << 8) |
1059                                         KEK_MGMT_SUBOP_KEYCARDUPDATE);
1060
1061         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
1062
1063         return rc;
1064 }
1065
1066 /**
1067  * pm8001_chip_init - the main init function that initialize whole PM8001 chip.
1068  * @pm8001_ha: our hba card information
1069  */
1070 static int pm80xx_chip_init(struct pm8001_hba_info *pm8001_ha)
1071 {
1072         int ret;
1073         u8 i = 0;
1074
1075         /* check the firmware status */
1076         if (-1 == check_fw_ready(pm8001_ha)) {
1077                 PM8001_FAIL_DBG(pm8001_ha,
1078                         pm8001_printk("Firmware is not ready!\n"));
1079                 return -EBUSY;
1080         }
1081
1082         /* Initialize pci space address eg: mpi offset */
1083         init_pci_device_addresses(pm8001_ha);
1084         init_default_table_values(pm8001_ha);
1085         read_main_config_table(pm8001_ha);
1086         read_general_status_table(pm8001_ha);
1087         read_inbnd_queue_table(pm8001_ha);
1088         read_outbnd_queue_table(pm8001_ha);
1089         read_phy_attr_table(pm8001_ha);
1090
1091         /* update main config table ,inbound table and outbound table */
1092         update_main_config_table(pm8001_ha);
1093         for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++)
1094                 update_inbnd_queue_table(pm8001_ha, i);
1095         for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++)
1096                 update_outbnd_queue_table(pm8001_ha, i);
1097
1098         /* notify firmware update finished and check initialization status */
1099         if (0 == mpi_init_check(pm8001_ha)) {
1100                 PM8001_INIT_DBG(pm8001_ha,
1101                         pm8001_printk("MPI initialize successful!\n"));
1102         } else
1103                 return -EBUSY;
1104
1105         /* send SAS protocol timer configuration page to FW */
1106         ret = pm80xx_set_sas_protocol_timer_config(pm8001_ha);
1107
1108         /* Check for encryption */
1109         if (pm8001_ha->chip->encrypt) {
1110                 PM8001_INIT_DBG(pm8001_ha,
1111                         pm8001_printk("Checking for encryption\n"));
1112                 ret = pm80xx_get_encrypt_info(pm8001_ha);
1113                 if (ret == -1) {
1114                         PM8001_INIT_DBG(pm8001_ha,
1115                                 pm8001_printk("Encryption error !!\n"));
1116                         if (pm8001_ha->encrypt_info.status == 0x81) {
1117                                 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
1118                                         "Encryption enabled with error."
1119                                         "Saving encryption key to flash\n"));
1120                                 pm80xx_encrypt_update(pm8001_ha);
1121                         }
1122                 }
1123         }
1124         return 0;
1125 }
1126
1127 static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha)
1128 {
1129         u32 max_wait_count;
1130         u32 value;
1131         u32 gst_len_mpistate;
1132         init_pci_device_addresses(pm8001_ha);
1133         /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the
1134         table is stop */
1135         pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_RESET);
1136
1137         /* wait until Inbound DoorBell Clear Register toggled */
1138         if (IS_SPCV_12G(pm8001_ha->pdev)) {
1139                 max_wait_count = 4 * 1000 * 1000;/* 4 sec */
1140         } else {
1141                 max_wait_count = 2 * 1000 * 1000;/* 2 sec */
1142         }
1143         do {
1144                 udelay(1);
1145                 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
1146                 value &= SPCv_MSGU_CFG_TABLE_RESET;
1147         } while ((value != 0) && (--max_wait_count));
1148
1149         if (!max_wait_count) {
1150                 PM8001_FAIL_DBG(pm8001_ha,
1151                         pm8001_printk("TIMEOUT:IBDB value/=%x\n", value));
1152                 return -1;
1153         }
1154
1155         /* check the MPI-State for termination in progress */
1156         /* wait until Inbound DoorBell Clear Register toggled */
1157         max_wait_count = 2 * 1000 * 1000;       /* 2 sec for spcv/ve */
1158         do {
1159                 udelay(1);
1160                 gst_len_mpistate =
1161                         pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
1162                         GST_GSTLEN_MPIS_OFFSET);
1163                 if (GST_MPI_STATE_UNINIT ==
1164                         (gst_len_mpistate & GST_MPI_STATE_MASK))
1165                         break;
1166         } while (--max_wait_count);
1167         if (!max_wait_count) {
1168                 PM8001_FAIL_DBG(pm8001_ha,
1169                         pm8001_printk(" TIME OUT MPI State = 0x%x\n",
1170                                 gst_len_mpistate & GST_MPI_STATE_MASK));
1171                 return -1;
1172         }
1173
1174         return 0;
1175 }
1176
1177 /**
1178  * pm8001_chip_soft_rst - soft reset the PM8001 chip, so that the clear all
1179  * the FW register status to the originated status.
1180  * @pm8001_ha: our hba card information
1181  */
1182
1183 static int
1184 pm80xx_chip_soft_rst(struct pm8001_hba_info *pm8001_ha)
1185 {
1186         u32 regval;
1187         u32 bootloader_state;
1188         u32 ibutton0, ibutton1;
1189
1190         /* Check if MPI is in ready state to reset */
1191         if (mpi_uninit_check(pm8001_ha) != 0) {
1192                 PM8001_FAIL_DBG(pm8001_ha,
1193                         pm8001_printk("MPI state is not ready\n"));
1194                 return -1;
1195         }
1196
1197         /* checked for reset register normal state; 0x0 */
1198         regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET);
1199         PM8001_INIT_DBG(pm8001_ha,
1200                 pm8001_printk("reset register before write : 0x%x\n", regval));
1201
1202         pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, SPCv_NORMAL_RESET_VALUE);
1203         mdelay(500);
1204
1205         regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET);
1206         PM8001_INIT_DBG(pm8001_ha,
1207         pm8001_printk("reset register after write 0x%x\n", regval));
1208
1209         if ((regval & SPCv_SOFT_RESET_READ_MASK) ==
1210                         SPCv_SOFT_RESET_NORMAL_RESET_OCCURED) {
1211                 PM8001_MSG_DBG(pm8001_ha,
1212                         pm8001_printk(" soft reset successful [regval: 0x%x]\n",
1213                                         regval));
1214         } else {
1215                 PM8001_MSG_DBG(pm8001_ha,
1216                         pm8001_printk(" soft reset failed [regval: 0x%x]\n",
1217                                         regval));
1218
1219                 /* check bootloader is successfully executed or in HDA mode */
1220                 bootloader_state =
1221                         pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) &
1222                         SCRATCH_PAD1_BOOTSTATE_MASK;
1223
1224                 if (bootloader_state == SCRATCH_PAD1_BOOTSTATE_HDA_SEEPROM) {
1225                         PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
1226                                 "Bootloader state - HDA mode SEEPROM\n"));
1227                 } else if (bootloader_state ==
1228                                 SCRATCH_PAD1_BOOTSTATE_HDA_BOOTSTRAP) {
1229                         PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
1230                                 "Bootloader state - HDA mode Bootstrap Pin\n"));
1231                 } else if (bootloader_state ==
1232                                 SCRATCH_PAD1_BOOTSTATE_HDA_SOFTRESET) {
1233                         PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
1234                                 "Bootloader state - HDA mode soft reset\n"));
1235                 } else if (bootloader_state ==
1236                                         SCRATCH_PAD1_BOOTSTATE_CRIT_ERROR) {
1237                         PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
1238                                 "Bootloader state-HDA mode critical error\n"));
1239                 }
1240                 return -EBUSY;
1241         }
1242
1243         /* check the firmware status after reset */
1244         if (-1 == check_fw_ready(pm8001_ha)) {
1245                 PM8001_FAIL_DBG(pm8001_ha,
1246                         pm8001_printk("Firmware is not ready!\n"));
1247                 /* check iButton feature support for motherboard controller */
1248                 if (pm8001_ha->pdev->subsystem_vendor !=
1249                         PCI_VENDOR_ID_ADAPTEC2 &&
1250                         pm8001_ha->pdev->subsystem_vendor != 0) {
1251                         ibutton0 = pm8001_cr32(pm8001_ha, 0,
1252                                         MSGU_HOST_SCRATCH_PAD_6);
1253                         ibutton1 = pm8001_cr32(pm8001_ha, 0,
1254                                         MSGU_HOST_SCRATCH_PAD_7);
1255                         if (!ibutton0 && !ibutton1) {
1256                                 PM8001_FAIL_DBG(pm8001_ha,
1257                                         pm8001_printk("iButton Feature is"
1258                                         " not Available!!!\n"));
1259                                 return -EBUSY;
1260                         }
1261                         if (ibutton0 == 0xdeadbeef && ibutton1 == 0xdeadbeef) {
1262                                 PM8001_FAIL_DBG(pm8001_ha,
1263                                         pm8001_printk("CRC Check for iButton"
1264                                         " Feature Failed!!!\n"));
1265                                 return -EBUSY;
1266                         }
1267                 }
1268         }
1269         PM8001_INIT_DBG(pm8001_ha,
1270                 pm8001_printk("SPCv soft reset Complete\n"));
1271         return 0;
1272 }
1273
1274 static void pm80xx_hw_chip_rst(struct pm8001_hba_info *pm8001_ha)
1275 {
1276          u32 i;
1277
1278         PM8001_INIT_DBG(pm8001_ha,
1279                 pm8001_printk("chip reset start\n"));
1280
1281         /* do SPCv chip reset. */
1282         pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, 0x11);
1283         PM8001_INIT_DBG(pm8001_ha,
1284                 pm8001_printk("SPC soft reset Complete\n"));
1285
1286         /* Check this ..whether delay is required or no */
1287         /* delay 10 usec */
1288         udelay(10);
1289
1290         /* wait for 20 msec until the firmware gets reloaded */
1291         i = 20;
1292         do {
1293                 mdelay(1);
1294         } while ((--i) != 0);
1295
1296         PM8001_INIT_DBG(pm8001_ha,
1297                 pm8001_printk("chip reset finished\n"));
1298 }
1299
1300 /**
1301  * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1302  * @pm8001_ha: our hba card information
1303  */
1304 static void
1305 pm80xx_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha)
1306 {
1307         pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1308         pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1309 }
1310
1311 /**
1312  * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt
1313  * @pm8001_ha: our hba card information
1314  */
1315 static void
1316 pm80xx_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha)
1317 {
1318         pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, ODMR_MASK_ALL);
1319 }
1320
1321 /**
1322  * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1323  * @pm8001_ha: our hba card information
1324  */
1325 static void
1326 pm80xx_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1327 {
1328 #ifdef PM8001_USE_MSIX
1329         u32 mask;
1330         mask = (u32)(1 << vec);
1331
1332         pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, (u32)(mask & 0xFFFFFFFF));
1333         return;
1334 #endif
1335         pm80xx_chip_intx_interrupt_enable(pm8001_ha);
1336
1337 }
1338
1339 /**
1340  * pm8001_chip_interrupt_disable- disable PM8001 chip interrupt
1341  * @pm8001_ha: our hba card information
1342  */
1343 static void
1344 pm80xx_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1345 {
1346 #ifdef PM8001_USE_MSIX
1347         u32 mask;
1348         if (vec == 0xFF)
1349                 mask = 0xFFFFFFFF;
1350         else
1351                 mask = (u32)(1 << vec);
1352         pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, (u32)(mask & 0xFFFFFFFF));
1353         return;
1354 #endif
1355         pm80xx_chip_intx_interrupt_disable(pm8001_ha);
1356 }
1357
1358 static void pm80xx_send_abort_all(struct pm8001_hba_info *pm8001_ha,
1359                 struct pm8001_device *pm8001_ha_dev)
1360 {
1361         int res;
1362         u32 ccb_tag;
1363         struct pm8001_ccb_info *ccb;
1364         struct sas_task *task = NULL;
1365         struct task_abort_req task_abort;
1366         struct inbound_queue_table *circularQ;
1367         u32 opc = OPC_INB_SATA_ABORT;
1368         int ret;
1369
1370         if (!pm8001_ha_dev) {
1371                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("dev is null\n"));
1372                 return;
1373         }
1374
1375         task = sas_alloc_slow_task(GFP_ATOMIC);
1376
1377         if (!task) {
1378                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("cannot "
1379                                                 "allocate task\n"));
1380                 return;
1381         }
1382
1383         task->task_done = pm8001_task_done;
1384
1385         res = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
1386         if (res)
1387                 return;
1388
1389         ccb = &pm8001_ha->ccb_info[ccb_tag];
1390         ccb->device = pm8001_ha_dev;
1391         ccb->ccb_tag = ccb_tag;
1392         ccb->task = task;
1393
1394         circularQ = &pm8001_ha->inbnd_q_tbl[0];
1395
1396         memset(&task_abort, 0, sizeof(task_abort));
1397         task_abort.abort_all = cpu_to_le32(1);
1398         task_abort.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1399         task_abort.tag = cpu_to_le32(ccb_tag);
1400
1401         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort, 0);
1402
1403 }
1404
1405 static void pm80xx_send_read_log(struct pm8001_hba_info *pm8001_ha,
1406                 struct pm8001_device *pm8001_ha_dev)
1407 {
1408         struct sata_start_req sata_cmd;
1409         int res;
1410         u32 ccb_tag;
1411         struct pm8001_ccb_info *ccb;
1412         struct sas_task *task = NULL;
1413         struct host_to_dev_fis fis;
1414         struct domain_device *dev;
1415         struct inbound_queue_table *circularQ;
1416         u32 opc = OPC_INB_SATA_HOST_OPSTART;
1417
1418         task = sas_alloc_slow_task(GFP_ATOMIC);
1419
1420         if (!task) {
1421                 PM8001_FAIL_DBG(pm8001_ha,
1422                         pm8001_printk("cannot allocate task !!!\n"));
1423                 return;
1424         }
1425         task->task_done = pm8001_task_done;
1426
1427         res = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
1428         if (res) {
1429                 PM8001_FAIL_DBG(pm8001_ha,
1430                         pm8001_printk("cannot allocate tag !!!\n"));
1431                 return;
1432         }
1433
1434         /* allocate domain device by ourselves as libsas
1435          * is not going to provide any
1436         */
1437         dev = kzalloc(sizeof(struct domain_device), GFP_ATOMIC);
1438         if (!dev) {
1439                 PM8001_FAIL_DBG(pm8001_ha,
1440                         pm8001_printk("Domain device cannot be allocated\n"));
1441                 sas_free_task(task);
1442                 return;
1443         } else {
1444                 task->dev = dev;
1445                 task->dev->lldd_dev = pm8001_ha_dev;
1446         }
1447
1448         ccb = &pm8001_ha->ccb_info[ccb_tag];
1449         ccb->device = pm8001_ha_dev;
1450         ccb->ccb_tag = ccb_tag;
1451         ccb->task = task;
1452         pm8001_ha_dev->id |= NCQ_READ_LOG_FLAG;
1453         pm8001_ha_dev->id |= NCQ_2ND_RLE_FLAG;
1454
1455         memset(&sata_cmd, 0, sizeof(sata_cmd));
1456         circularQ = &pm8001_ha->inbnd_q_tbl[0];
1457
1458         /* construct read log FIS */
1459         memset(&fis, 0, sizeof(struct host_to_dev_fis));
1460         fis.fis_type = 0x27;
1461         fis.flags = 0x80;
1462         fis.command = ATA_CMD_READ_LOG_EXT;
1463         fis.lbal = 0x10;
1464         fis.sector_count = 0x1;
1465
1466         sata_cmd.tag = cpu_to_le32(ccb_tag);
1467         sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1468         sata_cmd.ncqtag_atap_dir_m_dad |= ((0x1 << 7) | (0x5 << 9));
1469         memcpy(&sata_cmd.sata_fis, &fis, sizeof(struct host_to_dev_fis));
1470
1471         res = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd, 0);
1472
1473 }
1474
1475 /**
1476  * mpi_ssp_completion- process the event that FW response to the SSP request.
1477  * @pm8001_ha: our hba card information
1478  * @piomb: the message contents of this outbound message.
1479  *
1480  * When FW has completed a ssp request for example a IO request, after it has
1481  * filled the SG data with the data, it will trigger this event represent
1482  * that he has finished the job,please check the coresponding buffer.
1483  * So we will tell the caller who maybe waiting the result to tell upper layer
1484  * that the task has been finished.
1485  */
1486 static void
1487 mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha , void *piomb)
1488 {
1489         struct sas_task *t;
1490         struct pm8001_ccb_info *ccb;
1491         unsigned long flags;
1492         u32 status;
1493         u32 param;
1494         u32 tag;
1495         struct ssp_completion_resp *psspPayload;
1496         struct task_status_struct *ts;
1497         struct ssp_response_iu *iu;
1498         struct pm8001_device *pm8001_dev;
1499         psspPayload = (struct ssp_completion_resp *)(piomb + 4);
1500         status = le32_to_cpu(psspPayload->status);
1501         tag = le32_to_cpu(psspPayload->tag);
1502         ccb = &pm8001_ha->ccb_info[tag];
1503         if ((status == IO_ABORTED) && ccb->open_retry) {
1504                 /* Being completed by another */
1505                 ccb->open_retry = 0;
1506                 return;
1507         }
1508         pm8001_dev = ccb->device;
1509         param = le32_to_cpu(psspPayload->param);
1510         t = ccb->task;
1511
1512         if (status && status != IO_UNDERFLOW)
1513                 PM8001_FAIL_DBG(pm8001_ha,
1514                         pm8001_printk("sas IO status 0x%x\n", status));
1515         if (unlikely(!t || !t->lldd_task || !t->dev))
1516                 return;
1517         ts = &t->task_status;
1518         /* Print sas address of IO failed device */
1519         if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
1520                 (status != IO_UNDERFLOW))
1521                 PM8001_FAIL_DBG(pm8001_ha,
1522                         pm8001_printk("SAS Address of IO Failure Drive"
1523                         ":%016llx", SAS_ADDR(t->dev->sas_addr)));
1524
1525         switch (status) {
1526         case IO_SUCCESS:
1527                 PM8001_IO_DBG(pm8001_ha,
1528                         pm8001_printk("IO_SUCCESS ,param = 0x%x\n",
1529                                 param));
1530                 if (param == 0) {
1531                         ts->resp = SAS_TASK_COMPLETE;
1532                         ts->stat = SAM_STAT_GOOD;
1533                 } else {
1534                         ts->resp = SAS_TASK_COMPLETE;
1535                         ts->stat = SAS_PROTO_RESPONSE;
1536                         ts->residual = param;
1537                         iu = &psspPayload->ssp_resp_iu;
1538                         sas_ssp_task_response(pm8001_ha->dev, t, iu);
1539                 }
1540                 if (pm8001_dev)
1541                         pm8001_dev->running_req--;
1542                 break;
1543         case IO_ABORTED:
1544                 PM8001_IO_DBG(pm8001_ha,
1545                         pm8001_printk("IO_ABORTED IOMB Tag\n"));
1546                 ts->resp = SAS_TASK_COMPLETE;
1547                 ts->stat = SAS_ABORTED_TASK;
1548                 break;
1549         case IO_UNDERFLOW:
1550                 /* SSP Completion with error */
1551                 PM8001_IO_DBG(pm8001_ha,
1552                         pm8001_printk("IO_UNDERFLOW ,param = 0x%x\n",
1553                                 param));
1554                 ts->resp = SAS_TASK_COMPLETE;
1555                 ts->stat = SAS_DATA_UNDERRUN;
1556                 ts->residual = param;
1557                 if (pm8001_dev)
1558                         pm8001_dev->running_req--;
1559                 break;
1560         case IO_NO_DEVICE:
1561                 PM8001_IO_DBG(pm8001_ha,
1562                         pm8001_printk("IO_NO_DEVICE\n"));
1563                 ts->resp = SAS_TASK_UNDELIVERED;
1564                 ts->stat = SAS_PHY_DOWN;
1565                 break;
1566         case IO_XFER_ERROR_BREAK:
1567                 PM8001_IO_DBG(pm8001_ha,
1568                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1569                 ts->resp = SAS_TASK_COMPLETE;
1570                 ts->stat = SAS_OPEN_REJECT;
1571                 /* Force the midlayer to retry */
1572                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1573                 break;
1574         case IO_XFER_ERROR_PHY_NOT_READY:
1575                 PM8001_IO_DBG(pm8001_ha,
1576                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1577                 ts->resp = SAS_TASK_COMPLETE;
1578                 ts->stat = SAS_OPEN_REJECT;
1579                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1580                 break;
1581         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1582                 PM8001_IO_DBG(pm8001_ha,
1583                 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
1584                 ts->resp = SAS_TASK_COMPLETE;
1585                 ts->stat = SAS_OPEN_REJECT;
1586                 ts->open_rej_reason = SAS_OREJ_EPROTO;
1587                 break;
1588         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1589                 PM8001_IO_DBG(pm8001_ha,
1590                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1591                 ts->resp = SAS_TASK_COMPLETE;
1592                 ts->stat = SAS_OPEN_REJECT;
1593                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1594                 break;
1595         case IO_OPEN_CNX_ERROR_BREAK:
1596                 PM8001_IO_DBG(pm8001_ha,
1597                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
1598                 ts->resp = SAS_TASK_COMPLETE;
1599                 ts->stat = SAS_OPEN_REJECT;
1600                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1601                 break;
1602         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1603         case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
1604         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
1605         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
1606         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
1607         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
1608                 PM8001_IO_DBG(pm8001_ha,
1609                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
1610                 ts->resp = SAS_TASK_COMPLETE;
1611                 ts->stat = SAS_OPEN_REJECT;
1612                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1613                 if (!t->uldd_task)
1614                         pm8001_handle_event(pm8001_ha,
1615                                 pm8001_dev,
1616                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1617                 break;
1618         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
1619                 PM8001_IO_DBG(pm8001_ha,
1620                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
1621                 ts->resp = SAS_TASK_COMPLETE;
1622                 ts->stat = SAS_OPEN_REJECT;
1623                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1624                 break;
1625         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
1626                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
1627                         "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
1628                 ts->resp = SAS_TASK_COMPLETE;
1629                 ts->stat = SAS_OPEN_REJECT;
1630                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1631                 break;
1632         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
1633                 PM8001_IO_DBG(pm8001_ha,
1634                         pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
1635                 ts->resp = SAS_TASK_UNDELIVERED;
1636                 ts->stat = SAS_OPEN_REJECT;
1637                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
1638                 break;
1639         case IO_XFER_ERROR_NAK_RECEIVED:
1640                 PM8001_IO_DBG(pm8001_ha,
1641                         pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
1642                 ts->resp = SAS_TASK_COMPLETE;
1643                 ts->stat = SAS_OPEN_REJECT;
1644                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1645                 break;
1646         case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
1647                 PM8001_IO_DBG(pm8001_ha,
1648                         pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
1649                 ts->resp = SAS_TASK_COMPLETE;
1650                 ts->stat = SAS_NAK_R_ERR;
1651                 break;
1652         case IO_XFER_ERROR_DMA:
1653                 PM8001_IO_DBG(pm8001_ha,
1654                 pm8001_printk("IO_XFER_ERROR_DMA\n"));
1655                 ts->resp = SAS_TASK_COMPLETE;
1656                 ts->stat = SAS_OPEN_REJECT;
1657                 break;
1658         case IO_XFER_OPEN_RETRY_TIMEOUT:
1659                 PM8001_IO_DBG(pm8001_ha,
1660                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
1661                 ts->resp = SAS_TASK_COMPLETE;
1662                 ts->stat = SAS_OPEN_REJECT;
1663                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1664                 break;
1665         case IO_XFER_ERROR_OFFSET_MISMATCH:
1666                 PM8001_IO_DBG(pm8001_ha,
1667                         pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
1668                 ts->resp = SAS_TASK_COMPLETE;
1669                 ts->stat = SAS_OPEN_REJECT;
1670                 break;
1671         case IO_PORT_IN_RESET:
1672                 PM8001_IO_DBG(pm8001_ha,
1673                         pm8001_printk("IO_PORT_IN_RESET\n"));
1674                 ts->resp = SAS_TASK_COMPLETE;
1675                 ts->stat = SAS_OPEN_REJECT;
1676                 break;
1677         case IO_DS_NON_OPERATIONAL:
1678                 PM8001_IO_DBG(pm8001_ha,
1679                         pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
1680                 ts->resp = SAS_TASK_COMPLETE;
1681                 ts->stat = SAS_OPEN_REJECT;
1682                 if (!t->uldd_task)
1683                         pm8001_handle_event(pm8001_ha,
1684                                 pm8001_dev,
1685                                 IO_DS_NON_OPERATIONAL);
1686                 break;
1687         case IO_DS_IN_RECOVERY:
1688                 PM8001_IO_DBG(pm8001_ha,
1689                         pm8001_printk("IO_DS_IN_RECOVERY\n"));
1690                 ts->resp = SAS_TASK_COMPLETE;
1691                 ts->stat = SAS_OPEN_REJECT;
1692                 break;
1693         case IO_TM_TAG_NOT_FOUND:
1694                 PM8001_IO_DBG(pm8001_ha,
1695                         pm8001_printk("IO_TM_TAG_NOT_FOUND\n"));
1696                 ts->resp = SAS_TASK_COMPLETE;
1697                 ts->stat = SAS_OPEN_REJECT;
1698                 break;
1699         case IO_SSP_EXT_IU_ZERO_LEN_ERROR:
1700                 PM8001_IO_DBG(pm8001_ha,
1701                         pm8001_printk("IO_SSP_EXT_IU_ZERO_LEN_ERROR\n"));
1702                 ts->resp = SAS_TASK_COMPLETE;
1703                 ts->stat = SAS_OPEN_REJECT;
1704                 break;
1705         case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
1706                 PM8001_IO_DBG(pm8001_ha,
1707                         pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
1708                 ts->resp = SAS_TASK_COMPLETE;
1709                 ts->stat = SAS_OPEN_REJECT;
1710                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1711                 break;
1712         default:
1713                 PM8001_IO_DBG(pm8001_ha,
1714                         pm8001_printk("Unknown status 0x%x\n", status));
1715                 /* not allowed case. Therefore, return failed status */
1716                 ts->resp = SAS_TASK_COMPLETE;
1717                 ts->stat = SAS_OPEN_REJECT;
1718                 break;
1719         }
1720         PM8001_IO_DBG(pm8001_ha,
1721                 pm8001_printk("scsi_status = 0x%x\n ",
1722                 psspPayload->ssp_resp_iu.status));
1723         spin_lock_irqsave(&t->task_state_lock, flags);
1724         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
1725         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
1726         t->task_state_flags |= SAS_TASK_STATE_DONE;
1727         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
1728                 spin_unlock_irqrestore(&t->task_state_lock, flags);
1729                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
1730                         "task 0x%p done with io_status 0x%x resp 0x%x "
1731                         "stat 0x%x but aborted by upper layer!\n",
1732                         t, status, ts->resp, ts->stat));
1733                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1734         } else {
1735                 spin_unlock_irqrestore(&t->task_state_lock, flags);
1736                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1737                 mb();/* in order to force CPU ordering */
1738                 t->task_done(t);
1739         }
1740 }
1741
1742 /*See the comments for mpi_ssp_completion */
1743 static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
1744 {
1745         struct sas_task *t;
1746         unsigned long flags;
1747         struct task_status_struct *ts;
1748         struct pm8001_ccb_info *ccb;
1749         struct pm8001_device *pm8001_dev;
1750         struct ssp_event_resp *psspPayload =
1751                 (struct ssp_event_resp *)(piomb + 4);
1752         u32 event = le32_to_cpu(psspPayload->event);
1753         u32 tag = le32_to_cpu(psspPayload->tag);
1754         u32 port_id = le32_to_cpu(psspPayload->port_id);
1755
1756         ccb = &pm8001_ha->ccb_info[tag];
1757         t = ccb->task;
1758         pm8001_dev = ccb->device;
1759         if (event)
1760                 PM8001_FAIL_DBG(pm8001_ha,
1761                         pm8001_printk("sas IO status 0x%x\n", event));
1762         if (unlikely(!t || !t->lldd_task || !t->dev))
1763                 return;
1764         ts = &t->task_status;
1765         PM8001_IO_DBG(pm8001_ha,
1766                 pm8001_printk("port_id:0x%x, tag:0x%x, event:0x%x\n",
1767                                 port_id, tag, event));
1768         switch (event) {
1769         case IO_OVERFLOW:
1770                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n");)
1771                 ts->resp = SAS_TASK_COMPLETE;
1772                 ts->stat = SAS_DATA_OVERRUN;
1773                 ts->residual = 0;
1774                 if (pm8001_dev)
1775                         pm8001_dev->running_req--;
1776                 break;
1777         case IO_XFER_ERROR_BREAK:
1778                 PM8001_IO_DBG(pm8001_ha,
1779                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1780                 pm8001_handle_event(pm8001_ha, t, IO_XFER_ERROR_BREAK);
1781                 return;
1782         case IO_XFER_ERROR_PHY_NOT_READY:
1783                 PM8001_IO_DBG(pm8001_ha,
1784                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1785                 ts->resp = SAS_TASK_COMPLETE;
1786                 ts->stat = SAS_OPEN_REJECT;
1787                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1788                 break;
1789         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1790                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
1791                         "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
1792                 ts->resp = SAS_TASK_COMPLETE;
1793                 ts->stat = SAS_OPEN_REJECT;
1794                 ts->open_rej_reason = SAS_OREJ_EPROTO;
1795                 break;
1796         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1797                 PM8001_IO_DBG(pm8001_ha,
1798                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1799                 ts->resp = SAS_TASK_COMPLETE;
1800                 ts->stat = SAS_OPEN_REJECT;
1801                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1802                 break;
1803         case IO_OPEN_CNX_ERROR_BREAK:
1804                 PM8001_IO_DBG(pm8001_ha,
1805                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
1806                 ts->resp = SAS_TASK_COMPLETE;
1807                 ts->stat = SAS_OPEN_REJECT;
1808                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1809                 break;
1810         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1811         case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
1812         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
1813         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
1814         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
1815         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
1816                 PM8001_IO_DBG(pm8001_ha,
1817                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
1818                 ts->resp = SAS_TASK_COMPLETE;
1819                 ts->stat = SAS_OPEN_REJECT;
1820                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1821                 if (!t->uldd_task)
1822                         pm8001_handle_event(pm8001_ha,
1823                                 pm8001_dev,
1824                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1825                 break;
1826         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
1827                 PM8001_IO_DBG(pm8001_ha,
1828                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
1829                 ts->resp = SAS_TASK_COMPLETE;
1830                 ts->stat = SAS_OPEN_REJECT;
1831                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1832                 break;
1833         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
1834                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
1835                         "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
1836                 ts->resp = SAS_TASK_COMPLETE;
1837                 ts->stat = SAS_OPEN_REJECT;
1838                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1839                 break;
1840         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
1841                 PM8001_IO_DBG(pm8001_ha,
1842                         pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
1843                 ts->resp = SAS_TASK_COMPLETE;
1844                 ts->stat = SAS_OPEN_REJECT;
1845                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
1846                 break;
1847         case IO_XFER_ERROR_NAK_RECEIVED:
1848                 PM8001_IO_DBG(pm8001_ha,
1849                         pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
1850                 ts->resp = SAS_TASK_COMPLETE;
1851                 ts->stat = SAS_OPEN_REJECT;
1852                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1853                 break;
1854         case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
1855                 PM8001_IO_DBG(pm8001_ha,
1856                         pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
1857                 ts->resp = SAS_TASK_COMPLETE;
1858                 ts->stat = SAS_NAK_R_ERR;
1859                 break;
1860         case IO_XFER_OPEN_RETRY_TIMEOUT:
1861                 PM8001_IO_DBG(pm8001_ha,
1862                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
1863                 pm8001_handle_event(pm8001_ha, t, IO_XFER_OPEN_RETRY_TIMEOUT);
1864                 return;
1865         case IO_XFER_ERROR_UNEXPECTED_PHASE:
1866                 PM8001_IO_DBG(pm8001_ha,
1867                         pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
1868                 ts->resp = SAS_TASK_COMPLETE;
1869                 ts->stat = SAS_DATA_OVERRUN;
1870                 break;
1871         case IO_XFER_ERROR_XFER_RDY_OVERRUN:
1872                 PM8001_IO_DBG(pm8001_ha,
1873                         pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
1874                 ts->resp = SAS_TASK_COMPLETE;
1875                 ts->stat = SAS_DATA_OVERRUN;
1876                 break;
1877         case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
1878                 PM8001_IO_DBG(pm8001_ha,
1879                         pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
1880                 ts->resp = SAS_TASK_COMPLETE;
1881                 ts->stat = SAS_DATA_OVERRUN;
1882                 break;
1883         case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT:
1884                 PM8001_IO_DBG(pm8001_ha,
1885                 pm8001_printk("IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n"));
1886                 ts->resp = SAS_TASK_COMPLETE;
1887                 ts->stat = SAS_DATA_OVERRUN;
1888                 break;
1889         case IO_XFER_ERROR_OFFSET_MISMATCH:
1890                 PM8001_IO_DBG(pm8001_ha,
1891                         pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
1892                 ts->resp = SAS_TASK_COMPLETE;
1893                 ts->stat = SAS_DATA_OVERRUN;
1894                 break;
1895         case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
1896                 PM8001_IO_DBG(pm8001_ha,
1897                         pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
1898                 ts->resp = SAS_TASK_COMPLETE;
1899                 ts->stat = SAS_DATA_OVERRUN;
1900                 break;
1901         case IO_XFER_ERROR_INTERNAL_CRC_ERROR:
1902                 PM8001_IO_DBG(pm8001_ha,
1903                         pm8001_printk("IO_XFR_ERROR_INTERNAL_CRC_ERROR\n"));
1904                 /* TBC: used default set values */
1905                 ts->resp = SAS_TASK_COMPLETE;
1906                 ts->stat = SAS_DATA_OVERRUN;
1907                 break;
1908         case IO_XFER_CMD_FRAME_ISSUED:
1909                 PM8001_IO_DBG(pm8001_ha,
1910                         pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n"));
1911                 return;
1912         default:
1913                 PM8001_IO_DBG(pm8001_ha,
1914                         pm8001_printk("Unknown status 0x%x\n", event));
1915                 /* not allowed case. Therefore, return failed status */
1916                 ts->resp = SAS_TASK_COMPLETE;
1917                 ts->stat = SAS_DATA_OVERRUN;
1918                 break;
1919         }
1920         spin_lock_irqsave(&t->task_state_lock, flags);
1921         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
1922         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
1923         t->task_state_flags |= SAS_TASK_STATE_DONE;
1924         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
1925                 spin_unlock_irqrestore(&t->task_state_lock, flags);
1926                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
1927                         "task 0x%p done with event 0x%x resp 0x%x "
1928                         "stat 0x%x but aborted by upper layer!\n",
1929                         t, event, ts->resp, ts->stat));
1930                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1931         } else {
1932                 spin_unlock_irqrestore(&t->task_state_lock, flags);
1933                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1934                 mb();/* in order to force CPU ordering */
1935                 t->task_done(t);
1936         }
1937 }
1938
1939 /*See the comments for mpi_ssp_completion */
1940 static void
1941 mpi_sata_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
1942 {
1943         struct sas_task *t;
1944         struct pm8001_ccb_info *ccb;
1945         u32 param;
1946         u32 status;
1947         u32 tag;
1948         int i, j;
1949         u8 sata_addr_low[4];
1950         u32 temp_sata_addr_low, temp_sata_addr_hi;
1951         u8 sata_addr_hi[4];
1952         struct sata_completion_resp *psataPayload;
1953         struct task_status_struct *ts;
1954         struct ata_task_resp *resp ;
1955         u32 *sata_resp;
1956         struct pm8001_device *pm8001_dev;
1957         unsigned long flags;
1958
1959         psataPayload = (struct sata_completion_resp *)(piomb + 4);
1960         status = le32_to_cpu(psataPayload->status);
1961         tag = le32_to_cpu(psataPayload->tag);
1962
1963         if (!tag) {
1964                 PM8001_FAIL_DBG(pm8001_ha,
1965                         pm8001_printk("tag null\n"));
1966                 return;
1967         }
1968         ccb = &pm8001_ha->ccb_info[tag];
1969         param = le32_to_cpu(psataPayload->param);
1970         if (ccb) {
1971                 t = ccb->task;
1972                 pm8001_dev = ccb->device;
1973         } else {
1974                 PM8001_FAIL_DBG(pm8001_ha,
1975                         pm8001_printk("ccb null\n"));
1976                 return;
1977         }
1978
1979         if (t) {
1980                 if (t->dev && (t->dev->lldd_dev))
1981                         pm8001_dev = t->dev->lldd_dev;
1982         } else {
1983                 PM8001_FAIL_DBG(pm8001_ha,
1984                         pm8001_printk("task null\n"));
1985                 return;
1986         }
1987
1988         if ((pm8001_dev && !(pm8001_dev->id & NCQ_READ_LOG_FLAG))
1989                 && unlikely(!t || !t->lldd_task || !t->dev)) {
1990                 PM8001_FAIL_DBG(pm8001_ha,
1991                         pm8001_printk("task or dev null\n"));
1992                 return;
1993         }
1994
1995         ts = &t->task_status;
1996         if (!ts) {
1997                 PM8001_FAIL_DBG(pm8001_ha,
1998                         pm8001_printk("ts null\n"));
1999                 return;
2000         }
2001         /* Print sas address of IO failed device */
2002         if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
2003                 (status != IO_UNDERFLOW)) {
2004                 if (!((t->dev->parent) &&
2005                         (DEV_IS_EXPANDER(t->dev->parent->dev_type)))) {
2006                         for (i = 0 , j = 4; i <= 3 && j <= 7; i++ , j++)
2007                                 sata_addr_low[i] = pm8001_ha->sas_addr[j];
2008                         for (i = 0 , j = 0; i <= 3 && j <= 3; i++ , j++)
2009                                 sata_addr_hi[i] = pm8001_ha->sas_addr[j];
2010                         memcpy(&temp_sata_addr_low, sata_addr_low,
2011                                 sizeof(sata_addr_low));
2012                         memcpy(&temp_sata_addr_hi, sata_addr_hi,
2013                                 sizeof(sata_addr_hi));
2014                         temp_sata_addr_hi = (((temp_sata_addr_hi >> 24) & 0xff)
2015                                                 |((temp_sata_addr_hi << 8) &
2016                                                 0xff0000) |
2017                                                 ((temp_sata_addr_hi >> 8)
2018                                                 & 0xff00) |
2019                                                 ((temp_sata_addr_hi << 24) &
2020                                                 0xff000000));
2021                         temp_sata_addr_low = ((((temp_sata_addr_low >> 24)
2022                                                 & 0xff) |
2023                                                 ((temp_sata_addr_low << 8)
2024                                                 & 0xff0000) |
2025                                                 ((temp_sata_addr_low >> 8)
2026                                                 & 0xff00) |
2027                                                 ((temp_sata_addr_low << 24)
2028                                                 & 0xff000000)) +
2029                                                 pm8001_dev->attached_phy +
2030                                                 0x10);
2031                         PM8001_FAIL_DBG(pm8001_ha,
2032                                 pm8001_printk("SAS Address of IO Failure Drive:"
2033                                 "%08x%08x", temp_sata_addr_hi,
2034                                         temp_sata_addr_low));
2035
2036                 } else {
2037                         PM8001_FAIL_DBG(pm8001_ha,
2038                                 pm8001_printk("SAS Address of IO Failure Drive:"
2039                                 "%016llx", SAS_ADDR(t->dev->sas_addr)));
2040                 }
2041         }
2042         switch (status) {
2043         case IO_SUCCESS:
2044                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
2045                 if (param == 0) {
2046                         ts->resp = SAS_TASK_COMPLETE;
2047                         ts->stat = SAM_STAT_GOOD;
2048                         /* check if response is for SEND READ LOG */
2049                         if (pm8001_dev &&
2050                                 (pm8001_dev->id & NCQ_READ_LOG_FLAG)) {
2051                                 /* set new bit for abort_all */
2052                                 pm8001_dev->id |= NCQ_ABORT_ALL_FLAG;
2053                                 /* clear bit for read log */
2054                                 pm8001_dev->id = pm8001_dev->id & 0x7FFFFFFF;
2055                                 pm80xx_send_abort_all(pm8001_ha, pm8001_dev);
2056                                 /* Free the tag */
2057                                 pm8001_tag_free(pm8001_ha, tag);
2058                                 sas_free_task(t);
2059                                 return;
2060                         }
2061                 } else {
2062                         u8 len;
2063                         ts->resp = SAS_TASK_COMPLETE;
2064                         ts->stat = SAS_PROTO_RESPONSE;
2065                         ts->residual = param;
2066                         PM8001_IO_DBG(pm8001_ha,
2067                                 pm8001_printk("SAS_PROTO_RESPONSE len = %d\n",
2068                                 param));
2069                         sata_resp = &psataPayload->sata_resp[0];
2070                         resp = (struct ata_task_resp *)ts->buf;
2071                         if (t->ata_task.dma_xfer == 0 &&
2072                         t->data_dir == PCI_DMA_FROMDEVICE) {
2073                                 len = sizeof(struct pio_setup_fis);
2074                                 PM8001_IO_DBG(pm8001_ha,
2075                                 pm8001_printk("PIO read len = %d\n", len));
2076                         } else if (t->ata_task.use_ncq) {
2077                                 len = sizeof(struct set_dev_bits_fis);
2078                                 PM8001_IO_DBG(pm8001_ha,
2079                                         pm8001_printk("FPDMA len = %d\n", len));
2080                         } else {
2081                                 len = sizeof(struct dev_to_host_fis);
2082                                 PM8001_IO_DBG(pm8001_ha,
2083                                 pm8001_printk("other len = %d\n", len));
2084                         }
2085                         if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) {
2086                                 resp->frame_len = len;
2087                                 memcpy(&resp->ending_fis[0], sata_resp, len);
2088                                 ts->buf_valid_size = sizeof(*resp);
2089                         } else
2090                                 PM8001_IO_DBG(pm8001_ha,
2091                                         pm8001_printk("response to large\n"));
2092                 }
2093                 if (pm8001_dev)
2094                         pm8001_dev->running_req--;
2095                 break;
2096         case IO_ABORTED:
2097                 PM8001_IO_DBG(pm8001_ha,
2098                         pm8001_printk("IO_ABORTED IOMB Tag\n"));
2099                 ts->resp = SAS_TASK_COMPLETE;
2100                 ts->stat = SAS_ABORTED_TASK;
2101                 if (pm8001_dev)
2102                         pm8001_dev->running_req--;
2103                 break;
2104                 /* following cases are to do cases */
2105         case IO_UNDERFLOW:
2106                 /* SATA Completion with error */
2107                 PM8001_IO_DBG(pm8001_ha,
2108                         pm8001_printk("IO_UNDERFLOW param = %d\n", param));
2109                 ts->resp = SAS_TASK_COMPLETE;
2110                 ts->stat = SAS_DATA_UNDERRUN;
2111                 ts->residual = param;
2112                 if (pm8001_dev)
2113                         pm8001_dev->running_req--;
2114                 break;
2115         case IO_NO_DEVICE:
2116                 PM8001_IO_DBG(pm8001_ha,
2117                         pm8001_printk("IO_NO_DEVICE\n"));
2118                 ts->resp = SAS_TASK_UNDELIVERED;
2119                 ts->stat = SAS_PHY_DOWN;
2120                 break;
2121         case IO_XFER_ERROR_BREAK:
2122                 PM8001_IO_DBG(pm8001_ha,
2123                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2124                 ts->resp = SAS_TASK_COMPLETE;
2125                 ts->stat = SAS_INTERRUPTED;
2126                 break;
2127         case IO_XFER_ERROR_PHY_NOT_READY:
2128                 PM8001_IO_DBG(pm8001_ha,
2129                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2130                 ts->resp = SAS_TASK_COMPLETE;
2131                 ts->stat = SAS_OPEN_REJECT;
2132                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2133                 break;
2134         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2135                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2136                         "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
2137                 ts->resp = SAS_TASK_COMPLETE;
2138                 ts->stat = SAS_OPEN_REJECT;
2139                 ts->open_rej_reason = SAS_OREJ_EPROTO;
2140                 break;
2141         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2142                 PM8001_IO_DBG(pm8001_ha,
2143                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2144                 ts->resp = SAS_TASK_COMPLETE;
2145                 ts->stat = SAS_OPEN_REJECT;
2146                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2147                 break;
2148         case IO_OPEN_CNX_ERROR_BREAK:
2149                 PM8001_IO_DBG(pm8001_ha,
2150                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2151                 ts->resp = SAS_TASK_COMPLETE;
2152                 ts->stat = SAS_OPEN_REJECT;
2153                 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2154                 break;
2155         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2156         case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2157         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2158         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2159         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2160         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2161                 PM8001_IO_DBG(pm8001_ha,
2162                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2163                 ts->resp = SAS_TASK_COMPLETE;
2164                 ts->stat = SAS_DEV_NO_RESPONSE;
2165                 if (!t->uldd_task) {
2166                         pm8001_handle_event(pm8001_ha,
2167                                 pm8001_dev,
2168                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2169                         ts->resp = SAS_TASK_UNDELIVERED;
2170                         ts->stat = SAS_QUEUE_FULL;
2171                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2172                         mb();/*in order to force CPU ordering*/
2173                         spin_unlock_irq(&pm8001_ha->lock);
2174                         t->task_done(t);
2175                         spin_lock_irq(&pm8001_ha->lock);
2176                         return;
2177                 }
2178                 break;
2179         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2180                 PM8001_IO_DBG(pm8001_ha,
2181                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2182                 ts->resp = SAS_TASK_UNDELIVERED;
2183                 ts->stat = SAS_OPEN_REJECT;
2184                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2185                 if (!t->uldd_task) {
2186                         pm8001_handle_event(pm8001_ha,
2187                                 pm8001_dev,
2188                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2189                         ts->resp = SAS_TASK_UNDELIVERED;
2190                         ts->stat = SAS_QUEUE_FULL;
2191                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2192                         mb();/*ditto*/
2193                         spin_unlock_irq(&pm8001_ha->lock);
2194                         t->task_done(t);
2195                         spin_lock_irq(&pm8001_ha->lock);
2196                         return;
2197                 }
2198                 break;
2199         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2200                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2201                         "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
2202                 ts->resp = SAS_TASK_COMPLETE;
2203                 ts->stat = SAS_OPEN_REJECT;
2204                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2205                 break;
2206         case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
2207                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2208                         "IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY\n"));
2209                 ts->resp = SAS_TASK_COMPLETE;
2210                 ts->stat = SAS_DEV_NO_RESPONSE;
2211                 if (!t->uldd_task) {
2212                         pm8001_handle_event(pm8001_ha,
2213                                 pm8001_dev,
2214                                 IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY);
2215                         ts->resp = SAS_TASK_UNDELIVERED;
2216                         ts->stat = SAS_QUEUE_FULL;
2217                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2218                         mb();/* ditto*/
2219                         spin_unlock_irq(&pm8001_ha->lock);
2220                         t->task_done(t);
2221                         spin_lock_irq(&pm8001_ha->lock);
2222                         return;
2223                 }
2224                 break;
2225         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2226                 PM8001_IO_DBG(pm8001_ha,
2227                         pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2228                 ts->resp = SAS_TASK_COMPLETE;
2229                 ts->stat = SAS_OPEN_REJECT;
2230                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2231                 break;
2232         case IO_XFER_ERROR_NAK_RECEIVED:
2233                 PM8001_IO_DBG(pm8001_ha,
2234                         pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2235                 ts->resp = SAS_TASK_COMPLETE;
2236                 ts->stat = SAS_NAK_R_ERR;
2237                 break;
2238         case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2239                 PM8001_IO_DBG(pm8001_ha,
2240                         pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
2241                 ts->resp = SAS_TASK_COMPLETE;
2242                 ts->stat = SAS_NAK_R_ERR;
2243                 break;
2244         case IO_XFER_ERROR_DMA:
2245                 PM8001_IO_DBG(pm8001_ha,
2246                         pm8001_printk("IO_XFER_ERROR_DMA\n"));
2247                 ts->resp = SAS_TASK_COMPLETE;
2248                 ts->stat = SAS_ABORTED_TASK;
2249                 break;
2250         case IO_XFER_ERROR_SATA_LINK_TIMEOUT:
2251                 PM8001_IO_DBG(pm8001_ha,
2252                         pm8001_printk("IO_XFER_ERROR_SATA_LINK_TIMEOUT\n"));
2253                 ts->resp = SAS_TASK_UNDELIVERED;
2254                 ts->stat = SAS_DEV_NO_RESPONSE;
2255                 break;
2256         case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2257                 PM8001_IO_DBG(pm8001_ha,
2258                         pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
2259                 ts->resp = SAS_TASK_COMPLETE;
2260                 ts->stat = SAS_DATA_UNDERRUN;
2261                 break;
2262         case IO_XFER_OPEN_RETRY_TIMEOUT:
2263                 PM8001_IO_DBG(pm8001_ha,
2264                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2265                 ts->resp = SAS_TASK_COMPLETE;
2266                 ts->stat = SAS_OPEN_TO;
2267                 break;
2268         case IO_PORT_IN_RESET:
2269                 PM8001_IO_DBG(pm8001_ha,
2270                         pm8001_printk("IO_PORT_IN_RESET\n"));
2271                 ts->resp = SAS_TASK_COMPLETE;
2272                 ts->stat = SAS_DEV_NO_RESPONSE;
2273                 break;
2274         case IO_DS_NON_OPERATIONAL:
2275                 PM8001_IO_DBG(pm8001_ha,
2276                         pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
2277                 ts->resp = SAS_TASK_COMPLETE;
2278                 ts->stat = SAS_DEV_NO_RESPONSE;
2279                 if (!t->uldd_task) {
2280                         pm8001_handle_event(pm8001_ha, pm8001_dev,
2281                                         IO_DS_NON_OPERATIONAL);
2282                         ts->resp = SAS_TASK_UNDELIVERED;
2283                         ts->stat = SAS_QUEUE_FULL;
2284                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2285                         mb();/*ditto*/
2286                         spin_unlock_irq(&pm8001_ha->lock);
2287                         t->task_done(t);
2288                         spin_lock_irq(&pm8001_ha->lock);
2289                         return;
2290                 }
2291                 break;
2292         case IO_DS_IN_RECOVERY:
2293                 PM8001_IO_DBG(pm8001_ha,
2294                         pm8001_printk("IO_DS_IN_RECOVERY\n"));
2295                 ts->resp = SAS_TASK_COMPLETE;
2296                 ts->stat = SAS_DEV_NO_RESPONSE;
2297                 break;
2298         case IO_DS_IN_ERROR:
2299                 PM8001_IO_DBG(pm8001_ha,
2300                         pm8001_printk("IO_DS_IN_ERROR\n"));
2301                 ts->resp = SAS_TASK_COMPLETE;
2302                 ts->stat = SAS_DEV_NO_RESPONSE;
2303                 if (!t->uldd_task) {
2304                         pm8001_handle_event(pm8001_ha, pm8001_dev,
2305                                         IO_DS_IN_ERROR);
2306                         ts->resp = SAS_TASK_UNDELIVERED;
2307                         ts->stat = SAS_QUEUE_FULL;
2308                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2309                         mb();/*ditto*/
2310                         spin_unlock_irq(&pm8001_ha->lock);
2311                         t->task_done(t);
2312                         spin_lock_irq(&pm8001_ha->lock);
2313                         return;
2314                 }
2315                 break;
2316         case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2317                 PM8001_IO_DBG(pm8001_ha,
2318                         pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
2319                 ts->resp = SAS_TASK_COMPLETE;
2320                 ts->stat = SAS_OPEN_REJECT;
2321                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2322         default:
2323                 PM8001_IO_DBG(pm8001_ha,
2324                         pm8001_printk("Unknown status 0x%x\n", status));
2325                 /* not allowed case. Therefore, return failed status */
2326                 ts->resp = SAS_TASK_COMPLETE;
2327                 ts->stat = SAS_DEV_NO_RESPONSE;
2328                 break;
2329         }
2330         spin_lock_irqsave(&t->task_state_lock, flags);
2331         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2332         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2333         t->task_state_flags |= SAS_TASK_STATE_DONE;
2334         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2335                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2336                 PM8001_FAIL_DBG(pm8001_ha,
2337                         pm8001_printk("task 0x%p done with io_status 0x%x"
2338                         " resp 0x%x stat 0x%x but aborted by upper layer!\n",
2339                         t, status, ts->resp, ts->stat));
2340                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2341         } else if (t->uldd_task) {
2342                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2343                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2344                 mb();/* ditto */
2345                 spin_unlock_irq(&pm8001_ha->lock);
2346                 t->task_done(t);
2347                 spin_lock_irq(&pm8001_ha->lock);
2348         } else if (!t->uldd_task) {
2349                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2350                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2351                 mb();/*ditto*/
2352                 spin_unlock_irq(&pm8001_ha->lock);
2353                 t->task_done(t);
2354                 spin_lock_irq(&pm8001_ha->lock);
2355         }
2356 }
2357
2358 /*See the comments for mpi_ssp_completion */
2359 static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
2360 {
2361         struct sas_task *t;
2362         struct task_status_struct *ts;
2363         struct pm8001_ccb_info *ccb;
2364         struct pm8001_device *pm8001_dev;
2365         struct sata_event_resp *psataPayload =
2366                 (struct sata_event_resp *)(piomb + 4);
2367         u32 event = le32_to_cpu(psataPayload->event);
2368         u32 tag = le32_to_cpu(psataPayload->tag);
2369         u32 port_id = le32_to_cpu(psataPayload->port_id);
2370         u32 dev_id = le32_to_cpu(psataPayload->device_id);
2371         unsigned long flags;
2372
2373         ccb = &pm8001_ha->ccb_info[tag];
2374
2375         if (ccb) {
2376                 t = ccb->task;
2377                 pm8001_dev = ccb->device;
2378         } else {
2379                 PM8001_FAIL_DBG(pm8001_ha,
2380                         pm8001_printk("No CCB !!!. returning\n"));
2381                 return;
2382         }
2383         if (event)
2384                 PM8001_FAIL_DBG(pm8001_ha,
2385                         pm8001_printk("SATA EVENT 0x%x\n", event));
2386
2387         /* Check if this is NCQ error */
2388         if (event == IO_XFER_ERROR_ABORTED_NCQ_MODE) {
2389                 /* find device using device id */
2390                 pm8001_dev = pm8001_find_dev(pm8001_ha, dev_id);
2391                 /* send read log extension */
2392                 if (pm8001_dev)
2393                         pm80xx_send_read_log(pm8001_ha, pm8001_dev);
2394                 return;
2395         }
2396
2397         if (unlikely(!t || !t->lldd_task || !t->dev)) {
2398                 PM8001_FAIL_DBG(pm8001_ha,
2399                         pm8001_printk("task or dev null\n"));
2400                 return;
2401         }
2402
2403         ts = &t->task_status;
2404         PM8001_IO_DBG(pm8001_ha,
2405                 pm8001_printk("port_id:0x%x, tag:0x%x, event:0x%x\n",
2406                                 port_id, tag, event));
2407         switch (event) {
2408         case IO_OVERFLOW:
2409                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
2410                 ts->resp = SAS_TASK_COMPLETE;
2411                 ts->stat = SAS_DATA_OVERRUN;
2412                 ts->residual = 0;
2413                 if (pm8001_dev)
2414                         pm8001_dev->running_req--;
2415                 break;
2416         case IO_XFER_ERROR_BREAK:
2417                 PM8001_IO_DBG(pm8001_ha,
2418                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2419                 ts->resp = SAS_TASK_COMPLETE;
2420                 ts->stat = SAS_INTERRUPTED;
2421                 break;
2422         case IO_XFER_ERROR_PHY_NOT_READY:
2423                 PM8001_IO_DBG(pm8001_ha,
2424                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2425                 ts->resp = SAS_TASK_COMPLETE;
2426                 ts->stat = SAS_OPEN_REJECT;
2427                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2428                 break;
2429         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2430                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2431                         "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
2432                 ts->resp = SAS_TASK_COMPLETE;
2433                 ts->stat = SAS_OPEN_REJECT;
2434                 ts->open_rej_reason = SAS_OREJ_EPROTO;
2435                 break;
2436         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2437                 PM8001_IO_DBG(pm8001_ha,
2438                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2439                 ts->resp = SAS_TASK_COMPLETE;
2440                 ts->stat = SAS_OPEN_REJECT;
2441                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2442                 break;
2443         case IO_OPEN_CNX_ERROR_BREAK:
2444                 PM8001_IO_DBG(pm8001_ha,
2445                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2446                 ts->resp = SAS_TASK_COMPLETE;
2447                 ts->stat = SAS_OPEN_REJECT;
2448                 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2449                 break;
2450         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2451         case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2452         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2453         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2454         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2455         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2456                 PM8001_FAIL_DBG(pm8001_ha,
2457                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2458                 ts->resp = SAS_TASK_UNDELIVERED;
2459                 ts->stat = SAS_DEV_NO_RESPONSE;
2460                 if (!t->uldd_task) {
2461                         pm8001_handle_event(pm8001_ha,
2462                                 pm8001_dev,
2463                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2464                         ts->resp = SAS_TASK_COMPLETE;
2465                         ts->stat = SAS_QUEUE_FULL;
2466                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2467                         mb();/*ditto*/
2468                         spin_unlock_irq(&pm8001_ha->lock);
2469                         t->task_done(t);
2470                         spin_lock_irq(&pm8001_ha->lock);
2471                         return;
2472                 }
2473                 break;
2474         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2475                 PM8001_IO_DBG(pm8001_ha,
2476                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2477                 ts->resp = SAS_TASK_UNDELIVERED;
2478                 ts->stat = SAS_OPEN_REJECT;
2479                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2480                 break;
2481         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2482                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2483                         "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
2484                 ts->resp = SAS_TASK_COMPLETE;
2485                 ts->stat = SAS_OPEN_REJECT;
2486                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2487                 break;
2488         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2489                 PM8001_IO_DBG(pm8001_ha,
2490                         pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2491                 ts->resp = SAS_TASK_COMPLETE;
2492                 ts->stat = SAS_OPEN_REJECT;
2493                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2494                 break;
2495         case IO_XFER_ERROR_NAK_RECEIVED:
2496                 PM8001_IO_DBG(pm8001_ha,
2497                         pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2498                 ts->resp = SAS_TASK_COMPLETE;
2499                 ts->stat = SAS_NAK_R_ERR;
2500                 break;
2501         case IO_XFER_ERROR_PEER_ABORTED:
2502                 PM8001_IO_DBG(pm8001_ha,
2503                         pm8001_printk("IO_XFER_ERROR_PEER_ABORTED\n"));
2504                 ts->resp = SAS_TASK_COMPLETE;
2505                 ts->stat = SAS_NAK_R_ERR;
2506                 break;
2507         case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2508                 PM8001_IO_DBG(pm8001_ha,
2509                         pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
2510                 ts->resp = SAS_TASK_COMPLETE;
2511                 ts->stat = SAS_DATA_UNDERRUN;
2512                 break;
2513         case IO_XFER_OPEN_RETRY_TIMEOUT:
2514                 PM8001_IO_DBG(pm8001_ha,
2515                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2516                 ts->resp = SAS_TASK_COMPLETE;
2517                 ts->stat = SAS_OPEN_TO;
2518                 break;
2519         case IO_XFER_ERROR_UNEXPECTED_PHASE:
2520                 PM8001_IO_DBG(pm8001_ha,
2521                         pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
2522                 ts->resp = SAS_TASK_COMPLETE;
2523                 ts->stat = SAS_OPEN_TO;
2524                 break;
2525         case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2526                 PM8001_IO_DBG(pm8001_ha,
2527                         pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
2528                 ts->resp = SAS_TASK_COMPLETE;
2529                 ts->stat = SAS_OPEN_TO;
2530                 break;
2531         case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2532                 PM8001_IO_DBG(pm8001_ha,
2533                         pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
2534                 ts->resp = SAS_TASK_COMPLETE;
2535                 ts->stat = SAS_OPEN_TO;
2536                 break;
2537         case IO_XFER_ERROR_OFFSET_MISMATCH:
2538                 PM8001_IO_DBG(pm8001_ha,
2539                         pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
2540                 ts->resp = SAS_TASK_COMPLETE;
2541                 ts->stat = SAS_OPEN_TO;
2542                 break;
2543         case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2544                 PM8001_IO_DBG(pm8001_ha,
2545                         pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
2546                 ts->resp = SAS_TASK_COMPLETE;
2547                 ts->stat = SAS_OPEN_TO;
2548                 break;
2549         case IO_XFER_CMD_FRAME_ISSUED:
2550                 PM8001_IO_DBG(pm8001_ha,
2551                         pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n"));
2552                 break;
2553         case IO_XFER_PIO_SETUP_ERROR:
2554                 PM8001_IO_DBG(pm8001_ha,
2555                         pm8001_printk("IO_XFER_PIO_SETUP_ERROR\n"));
2556                 ts->resp = SAS_TASK_COMPLETE;
2557                 ts->stat = SAS_OPEN_TO;
2558                 break;
2559         case IO_XFER_ERROR_INTERNAL_CRC_ERROR:
2560                 PM8001_FAIL_DBG(pm8001_ha,
2561                         pm8001_printk("IO_XFR_ERROR_INTERNAL_CRC_ERROR\n"));
2562                 /* TBC: used default set values */
2563                 ts->resp = SAS_TASK_COMPLETE;
2564                 ts->stat = SAS_OPEN_TO;
2565                 break;
2566         case IO_XFER_DMA_ACTIVATE_TIMEOUT:
2567                 PM8001_FAIL_DBG(pm8001_ha,
2568                         pm8001_printk("IO_XFR_DMA_ACTIVATE_TIMEOUT\n"));
2569                 /* TBC: used default set values */
2570                 ts->resp = SAS_TASK_COMPLETE;
2571                 ts->stat = SAS_OPEN_TO;
2572                 break;
2573         default:
2574                 PM8001_IO_DBG(pm8001_ha,
2575                         pm8001_printk("Unknown status 0x%x\n", event));
2576                 /* not allowed case. Therefore, return failed status */
2577                 ts->resp = SAS_TASK_COMPLETE;
2578                 ts->stat = SAS_OPEN_TO;
2579                 break;
2580         }
2581         spin_lock_irqsave(&t->task_state_lock, flags);
2582         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2583         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2584         t->task_state_flags |= SAS_TASK_STATE_DONE;
2585         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2586                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2587                 PM8001_FAIL_DBG(pm8001_ha,
2588                         pm8001_printk("task 0x%p done with io_status 0x%x"
2589                         " resp 0x%x stat 0x%x but aborted by upper layer!\n",
2590                         t, event, ts->resp, ts->stat));
2591                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2592         } else if (t->uldd_task) {
2593                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2594                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2595                 mb();/* ditto */
2596                 spin_unlock_irq(&pm8001_ha->lock);
2597                 t->task_done(t);
2598                 spin_lock_irq(&pm8001_ha->lock);
2599         } else if (!t->uldd_task) {
2600                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2601                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2602                 mb();/*ditto*/
2603                 spin_unlock_irq(&pm8001_ha->lock);
2604                 t->task_done(t);
2605                 spin_lock_irq(&pm8001_ha->lock);
2606         }
2607 }
2608
2609 /*See the comments for mpi_ssp_completion */
2610 static void
2611 mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2612 {
2613         u32 param, i;
2614         struct sas_task *t;
2615         struct pm8001_ccb_info *ccb;
2616         unsigned long flags;
2617         u32 status;
2618         u32 tag;
2619         struct smp_completion_resp *psmpPayload;
2620         struct task_status_struct *ts;
2621         struct pm8001_device *pm8001_dev;
2622         char *pdma_respaddr = NULL;
2623
2624         psmpPayload = (struct smp_completion_resp *)(piomb + 4);
2625         status = le32_to_cpu(psmpPayload->status);
2626         tag = le32_to_cpu(psmpPayload->tag);
2627
2628         ccb = &pm8001_ha->ccb_info[tag];
2629         param = le32_to_cpu(psmpPayload->param);
2630         t = ccb->task;
2631         ts = &t->task_status;
2632         pm8001_dev = ccb->device;
2633         if (status)
2634                 PM8001_FAIL_DBG(pm8001_ha,
2635                         pm8001_printk("smp IO status 0x%x\n", status));
2636         if (unlikely(!t || !t->lldd_task || !t->dev))
2637                 return;
2638
2639         switch (status) {
2640
2641         case IO_SUCCESS:
2642                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
2643                 ts->resp = SAS_TASK_COMPLETE;
2644                 ts->stat = SAM_STAT_GOOD;
2645                 if (pm8001_dev)
2646                         pm8001_dev->running_req--;
2647                 if (pm8001_ha->smp_exp_mode == SMP_DIRECT) {
2648                         PM8001_IO_DBG(pm8001_ha,
2649                                 pm8001_printk("DIRECT RESPONSE Length:%d\n",
2650                                                 param));
2651                         pdma_respaddr = (char *)(phys_to_virt(cpu_to_le64
2652                                                 ((u64)sg_dma_address
2653                                                 (&t->smp_task.smp_resp))));
2654                         for (i = 0; i < param; i++) {
2655                                 *(pdma_respaddr+i) = psmpPayload->_r_a[i];
2656                                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2657                                         "SMP Byte%d DMA data 0x%x psmp 0x%x\n",
2658                                         i, *(pdma_respaddr+i),
2659                                         psmpPayload->_r_a[i]));
2660                         }
2661                 }
2662                 break;
2663         case IO_ABORTED:
2664                 PM8001_IO_DBG(pm8001_ha,
2665                         pm8001_printk("IO_ABORTED IOMB\n"));
2666                 ts->resp = SAS_TASK_COMPLETE;
2667                 ts->stat = SAS_ABORTED_TASK;
2668                 if (pm8001_dev)
2669                         pm8001_dev->running_req--;
2670                 break;
2671         case IO_OVERFLOW:
2672                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
2673                 ts->resp = SAS_TASK_COMPLETE;
2674                 ts->stat = SAS_DATA_OVERRUN;
2675                 ts->residual = 0;
2676                 if (pm8001_dev)
2677                         pm8001_dev->running_req--;
2678                 break;
2679         case IO_NO_DEVICE:
2680                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_NO_DEVICE\n"));
2681                 ts->resp = SAS_TASK_COMPLETE;
2682                 ts->stat = SAS_PHY_DOWN;
2683                 break;
2684         case IO_ERROR_HW_TIMEOUT:
2685                 PM8001_IO_DBG(pm8001_ha,
2686                         pm8001_printk("IO_ERROR_HW_TIMEOUT\n"));
2687                 ts->resp = SAS_TASK_COMPLETE;
2688                 ts->stat = SAM_STAT_BUSY;
2689                 break;
2690         case IO_XFER_ERROR_BREAK:
2691                 PM8001_IO_DBG(pm8001_ha,
2692                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2693                 ts->resp = SAS_TASK_COMPLETE;
2694                 ts->stat = SAM_STAT_BUSY;
2695                 break;
2696         case IO_XFER_ERROR_PHY_NOT_READY:
2697                 PM8001_IO_DBG(pm8001_ha,
2698                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2699                 ts->resp = SAS_TASK_COMPLETE;
2700                 ts->stat = SAM_STAT_BUSY;
2701                 break;
2702         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2703                 PM8001_IO_DBG(pm8001_ha,
2704                 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
2705                 ts->resp = SAS_TASK_COMPLETE;
2706                 ts->stat = SAS_OPEN_REJECT;
2707                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2708                 break;
2709         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2710                 PM8001_IO_DBG(pm8001_ha,
2711                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2712                 ts->resp = SAS_TASK_COMPLETE;
2713                 ts->stat = SAS_OPEN_REJECT;
2714                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2715                 break;
2716         case IO_OPEN_CNX_ERROR_BREAK:
2717                 PM8001_IO_DBG(pm8001_ha,
2718                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2719                 ts->resp = SAS_TASK_COMPLETE;
2720                 ts->stat = SAS_OPEN_REJECT;
2721                 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2722                 break;
2723         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2724         case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2725         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2726         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2727         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2728         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2729                 PM8001_IO_DBG(pm8001_ha,
2730                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2731                 ts->resp = SAS_TASK_COMPLETE;
2732                 ts->stat = SAS_OPEN_REJECT;
2733                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2734                 pm8001_handle_event(pm8001_ha,
2735                                 pm8001_dev,
2736                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2737                 break;
2738         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2739                 PM8001_IO_DBG(pm8001_ha,
2740                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2741                 ts->resp = SAS_TASK_COMPLETE;
2742                 ts->stat = SAS_OPEN_REJECT;
2743                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2744                 break;
2745         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2746                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(\
2747                         "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
2748                 ts->resp = SAS_TASK_COMPLETE;
2749                 ts->stat = SAS_OPEN_REJECT;
2750                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2751                 break;
2752         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2753                 PM8001_IO_DBG(pm8001_ha,
2754                         pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2755                 ts->resp = SAS_TASK_COMPLETE;
2756                 ts->stat = SAS_OPEN_REJECT;
2757                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2758                 break;
2759         case IO_XFER_ERROR_RX_FRAME:
2760                 PM8001_IO_DBG(pm8001_ha,
2761                         pm8001_printk("IO_XFER_ERROR_RX_FRAME\n"));
2762                 ts->resp = SAS_TASK_COMPLETE;
2763                 ts->stat = SAS_DEV_NO_RESPONSE;
2764                 break;
2765         case IO_XFER_OPEN_RETRY_TIMEOUT:
2766                 PM8001_IO_DBG(pm8001_ha,
2767                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2768                 ts->resp = SAS_TASK_COMPLETE;
2769                 ts->stat = SAS_OPEN_REJECT;
2770                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2771                 break;
2772         case IO_ERROR_INTERNAL_SMP_RESOURCE:
2773                 PM8001_IO_DBG(pm8001_ha,
2774                         pm8001_printk("IO_ERROR_INTERNAL_SMP_RESOURCE\n"));
2775                 ts->resp = SAS_TASK_COMPLETE;
2776                 ts->stat = SAS_QUEUE_FULL;
2777                 break;
2778         case IO_PORT_IN_RESET:
2779                 PM8001_IO_DBG(pm8001_ha,
2780                         pm8001_printk("IO_PORT_IN_RESET\n"));
2781                 ts->resp = SAS_TASK_COMPLETE;
2782                 ts->stat = SAS_OPEN_REJECT;
2783                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2784                 break;
2785         case IO_DS_NON_OPERATIONAL:
2786                 PM8001_IO_DBG(pm8001_ha,
2787                         pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
2788                 ts->resp = SAS_TASK_COMPLETE;
2789                 ts->stat = SAS_DEV_NO_RESPONSE;
2790                 break;
2791         case IO_DS_IN_RECOVERY:
2792                 PM8001_IO_DBG(pm8001_ha,
2793                         pm8001_printk("IO_DS_IN_RECOVERY\n"));
2794                 ts->resp = SAS_TASK_COMPLETE;
2795                 ts->stat = SAS_OPEN_REJECT;
2796                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2797                 break;
2798         case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2799                 PM8001_IO_DBG(pm8001_ha,
2800                         pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
2801                 ts->resp = SAS_TASK_COMPLETE;
2802                 ts->stat = SAS_OPEN_REJECT;
2803                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2804                 break;
2805         default:
2806                 PM8001_IO_DBG(pm8001_ha,
2807                         pm8001_printk("Unknown status 0x%x\n", status));
2808                 ts->resp = SAS_TASK_COMPLETE;
2809                 ts->stat = SAS_DEV_NO_RESPONSE;
2810                 /* not allowed case. Therefore, return failed status */
2811                 break;
2812         }
2813         spin_lock_irqsave(&t->task_state_lock, flags);
2814         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2815         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2816         t->task_state_flags |= SAS_TASK_STATE_DONE;
2817         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2818                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2819                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
2820                         "task 0x%p done with io_status 0x%x resp 0x%x"
2821                         "stat 0x%x but aborted by upper layer!\n",
2822                         t, status, ts->resp, ts->stat));
2823                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2824         } else {
2825                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2826                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2827                 mb();/* in order to force CPU ordering */
2828                 t->task_done(t);
2829         }
2830 }
2831
2832 /**
2833  * pm80xx_hw_event_ack_req- For PM8001,some events need to acknowage to FW.
2834  * @pm8001_ha: our hba card information
2835  * @Qnum: the outbound queue message number.
2836  * @SEA: source of event to ack
2837  * @port_id: port id.
2838  * @phyId: phy id.
2839  * @param0: parameter 0.
2840  * @param1: parameter 1.
2841  */
2842 static void pm80xx_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha,
2843         u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1)
2844 {
2845         struct hw_event_ack_req  payload;
2846         u32 opc = OPC_INB_SAS_HW_EVENT_ACK;
2847
2848         struct inbound_queue_table *circularQ;
2849
2850         memset((u8 *)&payload, 0, sizeof(payload));
2851         circularQ = &pm8001_ha->inbnd_q_tbl[Qnum];
2852         payload.tag = cpu_to_le32(1);
2853         payload.phyid_sea_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) |
2854                 ((phyId & 0xFF) << 24) | (port_id & 0xFF));
2855         payload.param0 = cpu_to_le32(param0);
2856         payload.param1 = cpu_to_le32(param1);
2857         pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
2858 }
2859
2860 static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
2861         u32 phyId, u32 phy_op);
2862
2863 /**
2864  * hw_event_sas_phy_up -FW tells me a SAS phy up event.
2865  * @pm8001_ha: our hba card information
2866  * @piomb: IO message buffer
2867  */
2868 static void
2869 hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
2870 {
2871         struct hw_event_resp *pPayload =
2872                 (struct hw_event_resp *)(piomb + 4);
2873         u32 lr_status_evt_portid =
2874                 le32_to_cpu(pPayload->lr_status_evt_portid);
2875         u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
2876
2877         u8 link_rate =
2878                 (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
2879         u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
2880         u8 phy_id =
2881                 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
2882         u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
2883
2884         struct pm8001_port *port = &pm8001_ha->port[port_id];
2885         struct sas_ha_struct *sas_ha = pm8001_ha->sas;
2886         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
2887         unsigned long flags;
2888         u8 deviceType = pPayload->sas_identify.dev_type;
2889         port->port_state = portstate;
2890         phy->phy_state = PHY_STATE_LINK_UP_SPCV;
2891         PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
2892                 "portid:%d; phyid:%d; linkrate:%d; "
2893                 "portstate:%x; devicetype:%x\n",
2894                 port_id, phy_id, link_rate, portstate, deviceType));
2895
2896         switch (deviceType) {
2897         case SAS_PHY_UNUSED:
2898                 PM8001_MSG_DBG(pm8001_ha,
2899                         pm8001_printk("device type no device.\n"));
2900                 break;
2901         case SAS_END_DEVICE:
2902                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("end device.\n"));
2903                 pm80xx_chip_phy_ctl_req(pm8001_ha, phy_id,
2904                         PHY_NOTIFY_ENABLE_SPINUP);
2905                 port->port_attached = 1;
2906                 pm8001_get_lrate_mode(phy, link_rate);
2907                 break;
2908         case SAS_EDGE_EXPANDER_DEVICE:
2909                 PM8001_MSG_DBG(pm8001_ha,
2910                         pm8001_printk("expander device.\n"));
2911                 port->port_attached = 1;
2912                 pm8001_get_lrate_mode(phy, link_rate);
2913                 break;
2914         case SAS_FANOUT_EXPANDER_DEVICE:
2915                 PM8001_MSG_DBG(pm8001_ha,
2916                         pm8001_printk("fanout expander device.\n"));
2917                 port->port_attached = 1;
2918                 pm8001_get_lrate_mode(phy, link_rate);
2919                 break;
2920         default:
2921                 PM8001_MSG_DBG(pm8001_ha,
2922                         pm8001_printk("unknown device type(%x)\n", deviceType));
2923                 break;
2924         }
2925         phy->phy_type |= PORT_TYPE_SAS;
2926         phy->identify.device_type = deviceType;
2927         phy->phy_attached = 1;
2928         if (phy->identify.device_type == SAS_END_DEVICE)
2929                 phy->identify.target_port_protocols = SAS_PROTOCOL_SSP;
2930         else if (phy->identify.device_type != SAS_PHY_UNUSED)
2931                 phy->identify.target_port_protocols = SAS_PROTOCOL_SMP;
2932         phy->sas_phy.oob_mode = SAS_OOB_MODE;
2933         sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
2934         spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
2935         memcpy(phy->frame_rcvd, &pPayload->sas_identify,
2936                 sizeof(struct sas_identify_frame)-4);
2937         phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4;
2938         pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
2939         spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
2940         if (pm8001_ha->flags == PM8001F_RUN_TIME)
2941                 mdelay(200);/*delay a moment to wait disk to spinup*/
2942         pm8001_bytes_dmaed(pm8001_ha, phy_id);
2943 }
2944
2945 /**
2946  * hw_event_sata_phy_up -FW tells me a SATA phy up event.
2947  * @pm8001_ha: our hba card information
2948  * @piomb: IO message buffer
2949  */
2950 static void
2951 hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
2952 {
2953         struct hw_event_resp *pPayload =
2954                 (struct hw_event_resp *)(piomb + 4);
2955         u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
2956         u32 lr_status_evt_portid =
2957                 le32_to_cpu(pPayload->lr_status_evt_portid);
2958         u8 link_rate =
2959                 (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
2960         u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
2961         u8 phy_id =
2962                 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
2963
2964         u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
2965
2966         struct pm8001_port *port = &pm8001_ha->port[port_id];
2967         struct sas_ha_struct *sas_ha = pm8001_ha->sas;
2968         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
2969         unsigned long flags;
2970         PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
2971                 "port id %d, phy id %d link_rate %d portstate 0x%x\n",
2972                                 port_id, phy_id, link_rate, portstate));
2973
2974         port->port_state = portstate;
2975         phy->phy_state = PHY_STATE_LINK_UP_SPCV;
2976         port->port_attached = 1;
2977         pm8001_get_lrate_mode(phy, link_rate);
2978         phy->phy_type |= PORT_TYPE_SATA;
2979         phy->phy_attached = 1;
2980         phy->sas_phy.oob_mode = SATA_OOB_MODE;
2981         sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
2982         spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
2983         memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4),
2984                 sizeof(struct dev_to_host_fis));
2985         phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
2986         phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
2987         phy->identify.device_type = SAS_SATA_DEV;
2988         pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
2989         spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
2990         pm8001_bytes_dmaed(pm8001_ha, phy_id);
2991 }
2992
2993 /**
2994  * hw_event_phy_down -we should notify the libsas the phy is down.
2995  * @pm8001_ha: our hba card information
2996  * @piomb: IO message buffer
2997  */
2998 static void
2999 hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb)
3000 {
3001         struct hw_event_resp *pPayload =
3002                 (struct hw_event_resp *)(piomb + 4);
3003
3004         u32 lr_status_evt_portid =
3005                 le32_to_cpu(pPayload->lr_status_evt_portid);
3006         u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3007         u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3008         u8 phy_id =
3009                 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3010         u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
3011
3012         struct pm8001_port *port = &pm8001_ha->port[port_id];
3013         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3014         port->port_state = portstate;
3015         phy->phy_type = 0;
3016         phy->identify.device_type = 0;
3017         phy->phy_attached = 0;
3018         memset(&phy->dev_sas_addr, 0, SAS_ADDR_SIZE);
3019         switch (portstate) {
3020         case PORT_VALID:
3021                 break;
3022         case PORT_INVALID:
3023                 PM8001_MSG_DBG(pm8001_ha,
3024                         pm8001_printk(" PortInvalid portID %d\n", port_id));
3025                 PM8001_MSG_DBG(pm8001_ha,
3026                         pm8001_printk(" Last phy Down and port invalid\n"));
3027                 port->port_attached = 0;
3028                 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3029                         port_id, phy_id, 0, 0);
3030                 break;
3031         case PORT_IN_RESET:
3032                 PM8001_MSG_DBG(pm8001_ha,
3033                         pm8001_printk(" Port In Reset portID %d\n", port_id));
3034                 break;
3035         case PORT_NOT_ESTABLISHED:
3036                 PM8001_MSG_DBG(pm8001_ha,
3037                         pm8001_printk(" phy Down and PORT_NOT_ESTABLISHED\n"));
3038                 port->port_attached = 0;
3039                 break;
3040         case PORT_LOSTCOMM:
3041                 PM8001_MSG_DBG(pm8001_ha,
3042                         pm8001_printk(" phy Down and PORT_LOSTCOMM\n"));
3043                 PM8001_MSG_DBG(pm8001_ha,
3044                         pm8001_printk(" Last phy Down and port invalid\n"));
3045                 port->port_attached = 0;
3046                 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3047                         port_id, phy_id, 0, 0);
3048                 break;
3049         default:
3050                 port->port_attached = 0;
3051                 PM8001_MSG_DBG(pm8001_ha,
3052                         pm8001_printk(" phy Down and(default) = 0x%x\n",
3053                         portstate));
3054                 break;
3055
3056         }
3057 }
3058
3059 static int mpi_phy_start_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3060 {
3061         struct phy_start_resp *pPayload =
3062                 (struct phy_start_resp *)(piomb + 4);
3063         u32 status =
3064                 le32_to_cpu(pPayload->status);
3065         u32 phy_id =
3066                 le32_to_cpu(pPayload->phyid);
3067         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3068
3069         PM8001_INIT_DBG(pm8001_ha,
3070                 pm8001_printk("phy start resp status:0x%x, phyid:0x%x\n",
3071                                 status, phy_id));
3072         if (status == 0) {
3073                 phy->phy_state = 1;
3074                 if (pm8001_ha->flags == PM8001F_RUN_TIME)
3075                         complete(phy->enable_completion);
3076         }
3077         return 0;
3078
3079 }
3080
3081 /**
3082  * mpi_thermal_hw_event -The hw event has come.
3083  * @pm8001_ha: our hba card information
3084  * @piomb: IO message buffer
3085  */
3086 static int mpi_thermal_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
3087 {
3088         struct thermal_hw_event *pPayload =
3089                 (struct thermal_hw_event *)(piomb + 4);
3090
3091         u32 thermal_event = le32_to_cpu(pPayload->thermal_event);
3092         u32 rht_lht = le32_to_cpu(pPayload->rht_lht);
3093
3094         if (thermal_event & 0x40) {
3095                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3096                         "Thermal Event: Local high temperature violated!\n"));
3097                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3098                         "Thermal Event: Measured local high temperature %d\n",
3099                                 ((rht_lht & 0xFF00) >> 8)));
3100         }
3101         if (thermal_event & 0x10) {
3102                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3103                         "Thermal Event: Remote high temperature violated!\n"));
3104                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3105                         "Thermal Event: Measured remote high temperature %d\n",
3106                                 ((rht_lht & 0xFF000000) >> 24)));
3107         }
3108         return 0;
3109 }
3110
3111 /**
3112  * mpi_hw_event -The hw event has come.
3113  * @pm8001_ha: our hba card information
3114  * @piomb: IO message buffer
3115  */
3116 static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
3117 {
3118         unsigned long flags;
3119         struct hw_event_resp *pPayload =
3120                 (struct hw_event_resp *)(piomb + 4);
3121         u32 lr_status_evt_portid =
3122                 le32_to_cpu(pPayload->lr_status_evt_portid);
3123         u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3124         u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3125         u8 phy_id =
3126                 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3127         u16 eventType =
3128                 (u16)((lr_status_evt_portid & 0x00FFFF00) >> 8);
3129         u8 status =
3130                 (u8)((lr_status_evt_portid & 0x0F000000) >> 24);
3131
3132         struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3133         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3134         struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id];
3135         PM8001_MSG_DBG(pm8001_ha,
3136                 pm8001_printk("portid:%d phyid:%d event:0x%x status:0x%x\n",
3137                                 port_id, phy_id, eventType, status));
3138
3139         switch (eventType) {
3140
3141         case HW_EVENT_SAS_PHY_UP:
3142                 PM8001_MSG_DBG(pm8001_ha,
3143                         pm8001_printk("HW_EVENT_PHY_START_STATUS\n"));
3144                 hw_event_sas_phy_up(pm8001_ha, piomb);
3145                 break;
3146         case HW_EVENT_SATA_PHY_UP:
3147                 PM8001_MSG_DBG(pm8001_ha,
3148                         pm8001_printk("HW_EVENT_SATA_PHY_UP\n"));
3149                 hw_event_sata_phy_up(pm8001_ha, piomb);
3150                 break;
3151         case HW_EVENT_SATA_SPINUP_HOLD:
3152                 PM8001_MSG_DBG(pm8001_ha,
3153                         pm8001_printk("HW_EVENT_SATA_SPINUP_HOLD\n"));
3154                 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD);
3155                 break;
3156         case HW_EVENT_PHY_DOWN:
3157                 PM8001_MSG_DBG(pm8001_ha,
3158                         pm8001_printk("HW_EVENT_PHY_DOWN\n"));
3159                 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL);
3160                 phy->phy_attached = 0;
3161                 phy->phy_state = 0;
3162                 hw_event_phy_down(pm8001_ha, piomb);
3163                 break;
3164         case HW_EVENT_PORT_INVALID:
3165                 PM8001_MSG_DBG(pm8001_ha,
3166                         pm8001_printk("HW_EVENT_PORT_INVALID\n"));
3167                 sas_phy_disconnected(sas_phy);
3168                 phy->phy_attached = 0;
3169                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3170                 break;
3171         /* the broadcast change primitive received, tell the LIBSAS this event
3172         to revalidate the sas domain*/
3173         case HW_EVENT_BROADCAST_CHANGE:
3174                 PM8001_MSG_DBG(pm8001_ha,
3175                         pm8001_printk("HW_EVENT_BROADCAST_CHANGE\n"));
3176                 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE,
3177                         port_id, phy_id, 1, 0);
3178                 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3179                 sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE;
3180                 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3181                 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3182                 break;
3183         case HW_EVENT_PHY_ERROR:
3184                 PM8001_MSG_DBG(pm8001_ha,
3185                         pm8001_printk("HW_EVENT_PHY_ERROR\n"));
3186                 sas_phy_disconnected(&phy->sas_phy);
3187                 phy->phy_attached = 0;
3188                 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR);
3189                 break;
3190         case HW_EVENT_BROADCAST_EXP:
3191                 PM8001_MSG_DBG(pm8001_ha,
3192                         pm8001_printk("HW_EVENT_BROADCAST_EXP\n"));
3193                 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3194                 sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP;
3195                 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3196                 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3197                 break;
3198         case HW_EVENT_LINK_ERR_INVALID_DWORD:
3199                 PM8001_MSG_DBG(pm8001_ha,
3200                         pm8001_printk("HW_EVENT_LINK_ERR_INVALID_DWORD\n"));
3201                 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3202                         HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0);
3203                 sas_phy_disconnected(sas_phy);
3204                 phy->phy_attached = 0;
3205                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3206                 break;
3207         case HW_EVENT_LINK_ERR_DISPARITY_ERROR:
3208                 PM8001_MSG_DBG(pm8001_ha,
3209                         pm8001_printk("HW_EVENT_LINK_ERR_DISPARITY_ERROR\n"));
3210                 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3211                         HW_EVENT_LINK_ERR_DISPARITY_ERROR,
3212                         port_id, phy_id, 0, 0);
3213                 sas_phy_disconnected(sas_phy);
3214                 phy->phy_attached = 0;
3215                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3216                 break;
3217         case HW_EVENT_LINK_ERR_CODE_VIOLATION:
3218                 PM8001_MSG_DBG(pm8001_ha,
3219                         pm8001_printk("HW_EVENT_LINK_ERR_CODE_VIOLATION\n"));
3220                 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3221                         HW_EVENT_LINK_ERR_CODE_VIOLATION,
3222                         port_id, phy_id, 0, 0);
3223                 sas_phy_disconnected(sas_phy);
3224                 phy->phy_attached = 0;
3225                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3226                 break;
3227         case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH:
3228                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3229                                 "HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n"));
3230                 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3231                         HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH,
3232                         port_id, phy_id, 0, 0);
3233                 sas_phy_disconnected(sas_phy);
3234                 phy->phy_attached = 0;
3235                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3236                 break;
3237         case HW_EVENT_MALFUNCTION:
3238                 PM8001_MSG_DBG(pm8001_ha,
3239                         pm8001_printk("HW_EVENT_MALFUNCTION\n"));
3240                 break;
3241         case HW_EVENT_BROADCAST_SES:
3242                 PM8001_MSG_DBG(pm8001_ha,
3243                         pm8001_printk("HW_EVENT_BROADCAST_SES\n"));
3244                 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3245                 sas_phy->sas_prim = HW_EVENT_BROADCAST_SES;
3246                 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3247                 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3248                 break;
3249         case HW_EVENT_INBOUND_CRC_ERROR:
3250                 PM8001_MSG_DBG(pm8001_ha,
3251                         pm8001_printk("HW_EVENT_INBOUND_CRC_ERROR\n"));
3252                 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3253                         HW_EVENT_INBOUND_CRC_ERROR,
3254                         port_id, phy_id, 0, 0);
3255                 break;
3256         case HW_EVENT_HARD_RESET_RECEIVED:
3257                 PM8001_MSG_DBG(pm8001_ha,
3258                         pm8001_printk("HW_EVENT_HARD_RESET_RECEIVED\n"));
3259                 sas_ha->notify_port_event(sas_phy, PORTE_HARD_RESET);
3260                 break;
3261         case HW_EVENT_ID_FRAME_TIMEOUT:
3262                 PM8001_MSG_DBG(pm8001_ha,
3263                         pm8001_printk("HW_EVENT_ID_FRAME_TIMEOUT\n"));
3264                 sas_phy_disconnected(sas_phy);
3265                 phy->phy_attached = 0;
3266                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3267                 break;
3268         case HW_EVENT_LINK_ERR_PHY_RESET_FAILED:
3269                 PM8001_MSG_DBG(pm8001_ha,
3270                         pm8001_printk("HW_EVENT_LINK_ERR_PHY_RESET_FAILED\n"));
3271                 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3272                         HW_EVENT_LINK_ERR_PHY_RESET_FAILED,
3273                         port_id, phy_id, 0, 0);
3274                 sas_phy_disconnected(sas_phy);
3275                 phy->phy_attached = 0;
3276                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3277                 break;
3278         case HW_EVENT_PORT_RESET_TIMER_TMO:
3279                 PM8001_MSG_DBG(pm8001_ha,
3280                         pm8001_printk("HW_EVENT_PORT_RESET_TIMER_TMO\n"));
3281                 sas_phy_disconnected(sas_phy);
3282                 phy->phy_attached = 0;
3283                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3284                 break;
3285         case HW_EVENT_PORT_RECOVERY_TIMER_TMO:
3286                 PM8001_MSG_DBG(pm8001_ha,
3287                         pm8001_printk("HW_EVENT_PORT_RECOVERY_TIMER_TMO\n"));
3288                 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3289                         HW_EVENT_PORT_RECOVERY_TIMER_TMO,
3290                         port_id, phy_id, 0, 0);
3291                 sas_phy_disconnected(sas_phy);
3292                 phy->phy_attached = 0;
3293                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3294                 break;
3295         case HW_EVENT_PORT_RECOVER:
3296                 PM8001_MSG_DBG(pm8001_ha,
3297                         pm8001_printk("HW_EVENT_PORT_RECOVER\n"));
3298                 break;
3299         case HW_EVENT_PORT_RESET_COMPLETE:
3300                 PM8001_MSG_DBG(pm8001_ha,
3301                         pm8001_printk("HW_EVENT_PORT_RESET_COMPLETE\n"));
3302                 break;
3303         case EVENT_BROADCAST_ASYNCH_EVENT:
3304                 PM8001_MSG_DBG(pm8001_ha,
3305                         pm8001_printk("EVENT_BROADCAST_ASYNCH_EVENT\n"));
3306                 break;
3307         default:
3308                 PM8001_MSG_DBG(pm8001_ha,
3309                         pm8001_printk("Unknown event type 0x%x\n", eventType));
3310                 break;
3311         }
3312         return 0;
3313 }
3314
3315 /**
3316  * mpi_phy_stop_resp - SPCv specific
3317  * @pm8001_ha: our hba card information
3318  * @piomb: IO message buffer
3319  */
3320 static int mpi_phy_stop_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3321 {
3322         struct phy_stop_resp *pPayload =
3323                 (struct phy_stop_resp *)(piomb + 4);
3324         u32 status =
3325                 le32_to_cpu(pPayload->status);
3326         u32 phyid =
3327                 le32_to_cpu(pPayload->phyid);
3328         struct pm8001_phy *phy = &pm8001_ha->phy[phyid];
3329         PM8001_MSG_DBG(pm8001_ha,
3330                         pm8001_printk("phy:0x%x status:0x%x\n",
3331                                         phyid, status));
3332         if (status == 0)
3333                 phy->phy_state = 0;
3334         return 0;
3335 }
3336
3337 /**
3338  * mpi_set_controller_config_resp - SPCv specific
3339  * @pm8001_ha: our hba card information
3340  * @piomb: IO message buffer
3341  */
3342 static int mpi_set_controller_config_resp(struct pm8001_hba_info *pm8001_ha,
3343                         void *piomb)
3344 {
3345         struct set_ctrl_cfg_resp *pPayload =
3346                         (struct set_ctrl_cfg_resp *)(piomb + 4);
3347         u32 status = le32_to_cpu(pPayload->status);
3348         u32 err_qlfr_pgcd = le32_to_cpu(pPayload->err_qlfr_pgcd);
3349
3350         PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3351                         "SET CONTROLLER RESP: status 0x%x qlfr_pgcd 0x%x\n",
3352                         status, err_qlfr_pgcd));
3353
3354         return 0;
3355 }
3356
3357 /**
3358  * mpi_get_controller_config_resp - SPCv specific
3359  * @pm8001_ha: our hba card information
3360  * @piomb: IO message buffer
3361  */
3362 static int mpi_get_controller_config_resp(struct pm8001_hba_info *pm8001_ha,
3363                         void *piomb)
3364 {
3365         PM8001_MSG_DBG(pm8001_ha,
3366                         pm8001_printk(" pm80xx_addition_functionality\n"));
3367
3368         return 0;
3369 }
3370
3371 /**
3372  * mpi_get_phy_profile_resp - SPCv specific
3373  * @pm8001_ha: our hba card information
3374  * @piomb: IO message buffer
3375  */
3376 static int mpi_get_phy_profile_resp(struct pm8001_hba_info *pm8001_ha,
3377                         void *piomb)
3378 {
3379         PM8001_MSG_DBG(pm8001_ha,
3380                         pm8001_printk(" pm80xx_addition_functionality\n"));
3381
3382         return 0;
3383 }
3384
3385 /**
3386  * mpi_flash_op_ext_resp - SPCv specific
3387  * @pm8001_ha: our hba card information
3388  * @piomb: IO message buffer
3389  */
3390 static int mpi_flash_op_ext_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3391 {
3392         PM8001_MSG_DBG(pm8001_ha,
3393                         pm8001_printk(" pm80xx_addition_functionality\n"));
3394
3395         return 0;
3396 }
3397
3398 /**
3399  * mpi_set_phy_profile_resp - SPCv specific
3400  * @pm8001_ha: our hba card information
3401  * @piomb: IO message buffer
3402  */
3403 static int mpi_set_phy_profile_resp(struct pm8001_hba_info *pm8001_ha,
3404                         void *piomb)
3405 {
3406         u8 page_code;
3407         struct set_phy_profile_resp *pPayload =
3408                 (struct set_phy_profile_resp *)(piomb + 4);
3409         u32 ppc_phyid = le32_to_cpu(pPayload->ppc_phyid);
3410         u32 status = le32_to_cpu(pPayload->status);
3411
3412         page_code = (u8)((ppc_phyid & 0xFF00) >> 8);
3413         if (status) {
3414                 /* status is FAILED */
3415                 PM8001_FAIL_DBG(pm8001_ha,
3416                         pm8001_printk("PhyProfile command failed  with status "
3417                         "0x%08X \n", status));
3418                 return -1;
3419         } else {
3420                 if (page_code != SAS_PHY_ANALOG_SETTINGS_PAGE) {
3421                         PM8001_FAIL_DBG(pm8001_ha,
3422                                 pm8001_printk("Invalid page code 0x%X\n",
3423                                         page_code));
3424                         return -1;
3425                 }
3426         }
3427         return 0;
3428 }
3429
3430 /**
3431  * mpi_kek_management_resp - SPCv specific
3432  * @pm8001_ha: our hba card information
3433  * @piomb: IO message buffer
3434  */
3435 static int mpi_kek_management_resp(struct pm8001_hba_info *pm8001_ha,
3436                         void *piomb)
3437 {
3438         struct kek_mgmt_resp *pPayload = (struct kek_mgmt_resp *)(piomb + 4);
3439
3440         u32 status = le32_to_cpu(pPayload->status);
3441         u32 kidx_new_curr_ksop = le32_to_cpu(pPayload->kidx_new_curr_ksop);
3442         u32 err_qlfr = le32_to_cpu(pPayload->err_qlfr);
3443
3444         PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3445                 "KEK MGMT RESP. Status 0x%x idx_ksop 0x%x err_qlfr 0x%x\n",
3446                 status, kidx_new_curr_ksop, err_qlfr));
3447
3448         return 0;
3449 }
3450
3451 /**
3452  * mpi_dek_management_resp - SPCv specific
3453  * @pm8001_ha: our hba card information
3454  * @piomb: IO message buffer
3455  */
3456 static int mpi_dek_management_resp(struct pm8001_hba_info *pm8001_ha,
3457                         void *piomb)
3458 {
3459         PM8001_MSG_DBG(pm8001_ha,
3460                         pm8001_printk(" pm80xx_addition_functionality\n"));
3461
3462         return 0;
3463 }
3464
3465 /**
3466  * ssp_coalesced_comp_resp - SPCv specific
3467  * @pm8001_ha: our hba card information
3468  * @piomb: IO message buffer
3469  */
3470 static int ssp_coalesced_comp_resp(struct pm8001_hba_info *pm8001_ha,
3471                         void *piomb)
3472 {
3473         PM8001_MSG_DBG(pm8001_ha,
3474                         pm8001_printk(" pm80xx_addition_functionality\n"));
3475
3476         return 0;
3477 }
3478
3479 /**
3480  * process_one_iomb - process one outbound Queue memory block
3481  * @pm8001_ha: our hba card information
3482  * @piomb: IO message buffer
3483  */
3484 static void process_one_iomb(struct pm8001_hba_info *pm8001_ha, void *piomb)
3485 {
3486         __le32 pHeader = *(__le32 *)piomb;
3487         u32 opc = (u32)((le32_to_cpu(pHeader)) & 0xFFF);
3488
3489         switch (opc) {
3490         case OPC_OUB_ECHO:
3491                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("OPC_OUB_ECHO\n"));
3492                 break;
3493         case OPC_OUB_HW_EVENT:
3494                 PM8001_MSG_DBG(pm8001_ha,
3495                         pm8001_printk("OPC_OUB_HW_EVENT\n"));
3496                 mpi_hw_event(pm8001_ha, piomb);
3497                 break;
3498         case OPC_OUB_THERM_HW_EVENT:
3499                 PM8001_MSG_DBG(pm8001_ha,
3500                         pm8001_printk("OPC_OUB_THERMAL_EVENT\n"));
3501                 mpi_thermal_hw_event(pm8001_ha, piomb);
3502                 break;
3503         case OPC_OUB_SSP_COMP:
3504                 PM8001_MSG_DBG(pm8001_ha,
3505                         pm8001_printk("OPC_OUB_SSP_COMP\n"));
3506                 mpi_ssp_completion(pm8001_ha, piomb);
3507                 break;
3508         case OPC_OUB_SMP_COMP:
3509                 PM8001_MSG_DBG(pm8001_ha,
3510                         pm8001_printk("OPC_OUB_SMP_COMP\n"));
3511                 mpi_smp_completion(pm8001_ha, piomb);
3512                 break;
3513         case OPC_OUB_LOCAL_PHY_CNTRL:
3514                 PM8001_MSG_DBG(pm8001_ha,
3515                         pm8001_printk("OPC_OUB_LOCAL_PHY_CNTRL\n"));
3516                 pm8001_mpi_local_phy_ctl(pm8001_ha, piomb);
3517                 break;
3518         case OPC_OUB_DEV_REGIST:
3519                 PM8001_MSG_DBG(pm8001_ha,
3520                 pm8001_printk("OPC_OUB_DEV_REGIST\n"));
3521                 pm8001_mpi_reg_resp(pm8001_ha, piomb);
3522                 break;
3523         case OPC_OUB_DEREG_DEV:
3524                 PM8001_MSG_DBG(pm8001_ha,
3525                         pm8001_printk("unregister the device\n"));
3526                 pm8001_mpi_dereg_resp(pm8001_ha, piomb);
3527                 break;
3528         case OPC_OUB_GET_DEV_HANDLE:
3529                 PM8001_MSG_DBG(pm8001_ha,
3530                         pm8001_printk("OPC_OUB_GET_DEV_HANDLE\n"));
3531                 break;
3532         case OPC_OUB_SATA_COMP:
3533                 PM8001_MSG_DBG(pm8001_ha,
3534                         pm8001_printk("OPC_OUB_SATA_COMP\n"));
3535                 mpi_sata_completion(pm8001_ha, piomb);
3536                 break;
3537         case OPC_OUB_SATA_EVENT:
3538                 PM8001_MSG_DBG(pm8001_ha,
3539                         pm8001_printk("OPC_OUB_SATA_EVENT\n"));
3540                 mpi_sata_event(pm8001_ha, piomb);
3541                 break;
3542         case OPC_OUB_SSP_EVENT:
3543                 PM8001_MSG_DBG(pm8001_ha,
3544                         pm8001_printk("OPC_OUB_SSP_EVENT\n"));
3545                 mpi_ssp_event(pm8001_ha, piomb);
3546                 break;
3547         case OPC_OUB_DEV_HANDLE_ARRIV:
3548                 PM8001_MSG_DBG(pm8001_ha,
3549                         pm8001_printk("OPC_OUB_DEV_HANDLE_ARRIV\n"));
3550                 /*This is for target*/
3551                 break;
3552         case OPC_OUB_SSP_RECV_EVENT:
3553                 PM8001_MSG_DBG(pm8001_ha,
3554                         pm8001_printk("OPC_OUB_SSP_RECV_EVENT\n"));
3555                 /*This is for target*/
3556                 break;
3557         case OPC_OUB_FW_FLASH_UPDATE:
3558                 PM8001_MSG_DBG(pm8001_ha,
3559                         pm8001_printk("OPC_OUB_FW_FLASH_UPDATE\n"));
3560                 pm8001_mpi_fw_flash_update_resp(pm8001_ha, piomb);
3561                 break;
3562         case OPC_OUB_GPIO_RESPONSE:
3563                 PM8001_MSG_DBG(pm8001_ha,
3564                         pm8001_printk("OPC_OUB_GPIO_RESPONSE\n"));
3565                 break;
3566         case OPC_OUB_GPIO_EVENT:
3567                 PM8001_MSG_DBG(pm8001_ha,
3568                         pm8001_printk("OPC_OUB_GPIO_EVENT\n"));
3569                 break;
3570         case OPC_OUB_GENERAL_EVENT:
3571                 PM8001_MSG_DBG(pm8001_ha,
3572                         pm8001_printk("OPC_OUB_GENERAL_EVENT\n"));
3573                 pm8001_mpi_general_event(pm8001_ha, piomb);
3574                 break;
3575         case OPC_OUB_SSP_ABORT_RSP:
3576                 PM8001_MSG_DBG(pm8001_ha,
3577                         pm8001_printk("OPC_OUB_SSP_ABORT_RSP\n"));
3578                 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3579                 break;
3580         case OPC_OUB_SATA_ABORT_RSP:
3581                 PM8001_MSG_DBG(pm8001_ha,
3582                         pm8001_printk("OPC_OUB_SATA_ABORT_RSP\n"));
3583                 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3584                 break;
3585         case OPC_OUB_SAS_DIAG_MODE_START_END:
3586                 PM8001_MSG_DBG(pm8001_ha,
3587                         pm8001_printk("OPC_OUB_SAS_DIAG_MODE_START_END\n"));
3588                 break;
3589         case OPC_OUB_SAS_DIAG_EXECUTE:
3590                 PM8001_MSG_DBG(pm8001_ha,
3591                         pm8001_printk("OPC_OUB_SAS_DIAG_EXECUTE\n"));
3592                 break;
3593         case OPC_OUB_GET_TIME_STAMP:
3594                 PM8001_MSG_DBG(pm8001_ha,
3595                         pm8001_printk("OPC_OUB_GET_TIME_STAMP\n"));
3596                 break;
3597         case OPC_OUB_SAS_HW_EVENT_ACK:
3598                 PM8001_MSG_DBG(pm8001_ha,
3599                         pm8001_printk("OPC_OUB_SAS_HW_EVENT_ACK\n"));
3600                 break;
3601         case OPC_OUB_PORT_CONTROL:
3602                 PM8001_MSG_DBG(pm8001_ha,
3603                         pm8001_printk("OPC_OUB_PORT_CONTROL\n"));
3604                 break;
3605         case OPC_OUB_SMP_ABORT_RSP:
3606                 PM8001_MSG_DBG(pm8001_ha,
3607                         pm8001_printk("OPC_OUB_SMP_ABORT_RSP\n"));
3608                 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3609                 break;
3610         case OPC_OUB_GET_NVMD_DATA:
3611                 PM8001_MSG_DBG(pm8001_ha,
3612                         pm8001_printk("OPC_OUB_GET_NVMD_DATA\n"));
3613                 pm8001_mpi_get_nvmd_resp(pm8001_ha, piomb);
3614                 break;
3615         case OPC_OUB_SET_NVMD_DATA:
3616                 PM8001_MSG_DBG(pm8001_ha,
3617                         pm8001_printk("OPC_OUB_SET_NVMD_DATA\n"));
3618                 pm8001_mpi_set_nvmd_resp(pm8001_ha, piomb);
3619                 break;
3620         case OPC_OUB_DEVICE_HANDLE_REMOVAL:
3621                 PM8001_MSG_DBG(pm8001_ha,
3622                         pm8001_printk("OPC_OUB_DEVICE_HANDLE_REMOVAL\n"));
3623                 break;
3624         case OPC_OUB_SET_DEVICE_STATE:
3625                 PM8001_MSG_DBG(pm8001_ha,
3626                         pm8001_printk("OPC_OUB_SET_DEVICE_STATE\n"));
3627                 pm8001_mpi_set_dev_state_resp(pm8001_ha, piomb);
3628                 break;
3629         case OPC_OUB_GET_DEVICE_STATE:
3630                 PM8001_MSG_DBG(pm8001_ha,
3631                         pm8001_printk("OPC_OUB_GET_DEVICE_STATE\n"));
3632                 break;
3633         case OPC_OUB_SET_DEV_INFO:
3634                 PM8001_MSG_DBG(pm8001_ha,
3635                         pm8001_printk("OPC_OUB_SET_DEV_INFO\n"));
3636                 break;
3637         /* spcv specifc commands */
3638         case OPC_OUB_PHY_START_RESP:
3639                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3640                         "OPC_OUB_PHY_START_RESP opcode:%x\n", opc));
3641                 mpi_phy_start_resp(pm8001_ha, piomb);
3642                 break;
3643         case OPC_OUB_PHY_STOP_RESP:
3644                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3645                         "OPC_OUB_PHY_STOP_RESP opcode:%x\n", opc));
3646                 mpi_phy_stop_resp(pm8001_ha, piomb);
3647                 break;
3648         case OPC_OUB_SET_CONTROLLER_CONFIG:
3649                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3650                         "OPC_OUB_SET_CONTROLLER_CONFIG opcode:%x\n", opc));
3651                 mpi_set_controller_config_resp(pm8001_ha, piomb);
3652                 break;
3653         case OPC_OUB_GET_CONTROLLER_CONFIG:
3654                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3655                         "OPC_OUB_GET_CONTROLLER_CONFIG opcode:%x\n", opc));
3656                 mpi_get_controller_config_resp(pm8001_ha, piomb);
3657                 break;
3658         case OPC_OUB_GET_PHY_PROFILE:
3659                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3660                         "OPC_OUB_GET_PHY_PROFILE opcode:%x\n", opc));
3661                 mpi_get_phy_profile_resp(pm8001_ha, piomb);
3662                 break;
3663         case OPC_OUB_FLASH_OP_EXT:
3664                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3665                         "OPC_OUB_FLASH_OP_EXT opcode:%x\n", opc));
3666                 mpi_flash_op_ext_resp(pm8001_ha, piomb);
3667                 break;
3668         case OPC_OUB_SET_PHY_PROFILE:
3669                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3670                         "OPC_OUB_SET_PHY_PROFILE opcode:%x\n", opc));
3671                 mpi_set_phy_profile_resp(pm8001_ha, piomb);
3672                 break;
3673         case OPC_OUB_KEK_MANAGEMENT_RESP:
3674                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3675                         "OPC_OUB_KEK_MANAGEMENT_RESP opcode:%x\n", opc));
3676                 mpi_kek_management_resp(pm8001_ha, piomb);
3677                 break;
3678         case OPC_OUB_DEK_MANAGEMENT_RESP:
3679                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3680                         "OPC_OUB_DEK_MANAGEMENT_RESP opcode:%x\n", opc));
3681                 mpi_dek_management_resp(pm8001_ha, piomb);
3682                 break;
3683         case OPC_OUB_SSP_COALESCED_COMP_RESP:
3684                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3685                         "OPC_OUB_SSP_COALESCED_COMP_RESP opcode:%x\n", opc));
3686                 ssp_coalesced_comp_resp(pm8001_ha, piomb);
3687                 break;
3688         default:
3689                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3690                         "Unknown outbound Queue IOMB OPC = 0x%x\n", opc));
3691                 break;
3692         }
3693 }
3694
3695 static int process_oq(struct pm8001_hba_info *pm8001_ha, u8 vec)
3696 {
3697         struct outbound_queue_table *circularQ;
3698         void *pMsg1 = NULL;
3699         u8 uninitialized_var(bc);
3700         u32 ret = MPI_IO_STATUS_FAIL;
3701         unsigned long flags;
3702
3703         spin_lock_irqsave(&pm8001_ha->lock, flags);
3704         circularQ = &pm8001_ha->outbnd_q_tbl[vec];
3705         do {
3706                 ret = pm8001_mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc);
3707                 if (MPI_IO_STATUS_SUCCESS == ret) {
3708                         /* process the outbound message */
3709                         process_one_iomb(pm8001_ha, (void *)(pMsg1 - 4));
3710                         /* free the message from the outbound circular buffer */
3711                         pm8001_mpi_msg_free_set(pm8001_ha, pMsg1,
3712                                                         circularQ, bc);
3713                 }
3714                 if (MPI_IO_STATUS_BUSY == ret) {
3715                         /* Update the producer index from SPC */
3716                         circularQ->producer_index =
3717                                 cpu_to_le32(pm8001_read_32(circularQ->pi_virt));
3718                         if (le32_to_cpu(circularQ->producer_index) ==
3719                                 circularQ->consumer_idx)
3720                                 /* OQ is empty */
3721                                 break;
3722                 }
3723         } while (1);
3724         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
3725         return ret;
3726 }
3727
3728 /* PCI_DMA_... to our direction translation. */
3729 static const u8 data_dir_flags[] = {
3730         [PCI_DMA_BIDIRECTIONAL] = DATA_DIR_BYRECIPIENT,/* UNSPECIFIED */
3731         [PCI_DMA_TODEVICE]      = DATA_DIR_OUT,/* OUTBOUND */
3732         [PCI_DMA_FROMDEVICE]    = DATA_DIR_IN,/* INBOUND */
3733         [PCI_DMA_NONE]          = DATA_DIR_NONE,/* NO TRANSFER */
3734 };
3735
3736 static void build_smp_cmd(u32 deviceID, __le32 hTag,
3737                         struct smp_req *psmp_cmd, int mode, int length)
3738 {
3739         psmp_cmd->tag = hTag;
3740         psmp_cmd->device_id = cpu_to_le32(deviceID);
3741         if (mode == SMP_DIRECT) {
3742                 length = length - 4; /* subtract crc */
3743                 psmp_cmd->len_ip_ir = cpu_to_le32(length << 16);
3744         } else {
3745                 psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1));
3746         }
3747 }
3748
3749 /**
3750  * pm8001_chip_smp_req - send a SMP task to FW
3751  * @pm8001_ha: our hba card information.
3752  * @ccb: the ccb information this request used.
3753  */
3754 static int pm80xx_chip_smp_req(struct pm8001_hba_info *pm8001_ha,
3755         struct pm8001_ccb_info *ccb)
3756 {
3757         int elem, rc;
3758         struct sas_task *task = ccb->task;
3759         struct domain_device *dev = task->dev;
3760         struct pm8001_device *pm8001_dev = dev->lldd_dev;
3761         struct scatterlist *sg_req, *sg_resp;
3762         u32 req_len, resp_len;
3763         struct smp_req smp_cmd;
3764         u32 opc;
3765         struct inbound_queue_table *circularQ;
3766         char *preq_dma_addr = NULL;
3767         __le64 tmp_addr;
3768         u32 i, length;
3769
3770         memset(&smp_cmd, 0, sizeof(smp_cmd));
3771         /*
3772          * DMA-map SMP request, response buffers
3773          */
3774         sg_req = &task->smp_task.smp_req;
3775         elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, PCI_DMA_TODEVICE);
3776         if (!elem)
3777                 return -ENOMEM;
3778         req_len = sg_dma_len(sg_req);
3779
3780         sg_resp = &task->smp_task.smp_resp;
3781         elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, PCI_DMA_FROMDEVICE);
3782         if (!elem) {
3783                 rc = -ENOMEM;
3784                 goto err_out;
3785         }
3786         resp_len = sg_dma_len(sg_resp);
3787         /* must be in dwords */
3788         if ((req_len & 0x3) || (resp_len & 0x3)) {
3789                 rc = -EINVAL;
3790                 goto err_out_2;
3791         }
3792
3793         opc = OPC_INB_SMP_REQUEST;
3794         circularQ = &pm8001_ha->inbnd_q_tbl[0];
3795         smp_cmd.tag = cpu_to_le32(ccb->ccb_tag);
3796
3797         length = sg_req->length;
3798         PM8001_IO_DBG(pm8001_ha,
3799                 pm8001_printk("SMP Frame Length %d\n", sg_req->length));
3800         if (!(length - 8))
3801                 pm8001_ha->smp_exp_mode = SMP_DIRECT;
3802         else
3803                 pm8001_ha->smp_exp_mode = SMP_INDIRECT;
3804
3805
3806         tmp_addr = cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_req));
3807         preq_dma_addr = (char *)phys_to_virt(tmp_addr);
3808
3809         /* INDIRECT MODE command settings. Use DMA */
3810         if (pm8001_ha->smp_exp_mode == SMP_INDIRECT) {
3811                 PM8001_IO_DBG(pm8001_ha,
3812                         pm8001_printk("SMP REQUEST INDIRECT MODE\n"));
3813                 /* for SPCv indirect mode. Place the top 4 bytes of
3814                  * SMP Request header here. */
3815                 for (i = 0; i < 4; i++)
3816                         smp_cmd.smp_req16[i] = *(preq_dma_addr + i);
3817                 /* exclude top 4 bytes for SMP req header */
3818                 smp_cmd.long_smp_req.long_req_addr =
3819                         cpu_to_le64((u64)sg_dma_address
3820                                 (&task->smp_task.smp_req) + 4);
3821                 /* exclude 4 bytes for SMP req header and CRC */
3822                 smp_cmd.long_smp_req.long_req_size =
3823                         cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-8);
3824                 smp_cmd.long_smp_req.long_resp_addr =
3825                                 cpu_to_le64((u64)sg_dma_address
3826                                         (&task->smp_task.smp_resp));
3827                 smp_cmd.long_smp_req.long_resp_size =
3828                                 cpu_to_le32((u32)sg_dma_len
3829                                         (&task->smp_task.smp_resp)-4);
3830         } else { /* DIRECT MODE */
3831                 smp_cmd.long_smp_req.long_req_addr =
3832                         cpu_to_le64((u64)sg_dma_address
3833                                         (&task->smp_task.smp_req));
3834                 smp_cmd.long_smp_req.long_req_size =
3835                         cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4);
3836                 smp_cmd.long_smp_req.long_resp_addr =
3837                         cpu_to_le64((u64)sg_dma_address
3838                                 (&task->smp_task.smp_resp));
3839                 smp_cmd.long_smp_req.long_resp_size =
3840                         cpu_to_le32
3841                         ((u32)sg_dma_len(&task->smp_task.smp_resp)-4);
3842         }
3843         if (pm8001_ha->smp_exp_mode == SMP_DIRECT) {
3844                 PM8001_IO_DBG(pm8001_ha,
3845                         pm8001_printk("SMP REQUEST DIRECT MODE\n"));
3846                 for (i = 0; i < length; i++)
3847                         if (i < 16) {
3848                                 smp_cmd.smp_req16[i] = *(preq_dma_addr+i);
3849                                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3850                                         "Byte[%d]:%x (DMA data:%x)\n",
3851                                         i, smp_cmd.smp_req16[i],
3852                                         *(preq_dma_addr)));
3853                         } else {
3854                                 smp_cmd.smp_req[i] = *(preq_dma_addr+i);
3855                                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3856                                         "Byte[%d]:%x (DMA data:%x)\n",
3857                                         i, smp_cmd.smp_req[i],
3858                                         *(preq_dma_addr)));
3859                         }
3860         }
3861
3862         build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag,
3863                                 &smp_cmd, pm8001_ha->smp_exp_mode, length);
3864         pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, (u32 *)&smp_cmd, 0);
3865         return 0;
3866
3867 err_out_2:
3868         dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1,
3869                         PCI_DMA_FROMDEVICE);
3870 err_out:
3871         dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1,
3872                         PCI_DMA_TODEVICE);
3873         return rc;
3874 }
3875
3876 static int check_enc_sas_cmd(struct sas_task *task)
3877 {
3878         u8 cmd = task->ssp_task.cmd->cmnd[0];
3879
3880         if (cmd == READ_10 || cmd == WRITE_10 || cmd == WRITE_VERIFY)
3881                 return 1;
3882         else
3883                 return 0;
3884 }
3885
3886 static int check_enc_sat_cmd(struct sas_task *task)
3887 {
3888         int ret = 0;
3889         switch (task->ata_task.fis.command) {
3890         case ATA_CMD_FPDMA_READ:
3891         case ATA_CMD_READ_EXT:
3892         case ATA_CMD_READ:
3893         case ATA_CMD_FPDMA_WRITE:
3894         case ATA_CMD_WRITE_EXT:
3895         case ATA_CMD_WRITE:
3896         case ATA_CMD_PIO_READ:
3897         case ATA_CMD_PIO_READ_EXT:
3898         case ATA_CMD_PIO_WRITE:
3899         case ATA_CMD_PIO_WRITE_EXT:
3900                 ret = 1;
3901                 break;
3902         default:
3903                 ret = 0;
3904                 break;
3905         }
3906         return ret;
3907 }
3908
3909 /**
3910  * pm80xx_chip_ssp_io_req - send a SSP task to FW
3911  * @pm8001_ha: our hba card information.
3912  * @ccb: the ccb information this request used.
3913  */
3914 static int pm80xx_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha,
3915         struct pm8001_ccb_info *ccb)
3916 {
3917         struct sas_task *task = ccb->task;
3918         struct domain_device *dev = task->dev;
3919         struct pm8001_device *pm8001_dev = dev->lldd_dev;
3920         struct ssp_ini_io_start_req ssp_cmd;
3921         u32 tag = ccb->ccb_tag;
3922         int ret;
3923         u64 phys_addr, start_addr, end_addr;
3924         u32 end_addr_high, end_addr_low;
3925         struct inbound_queue_table *circularQ;
3926         u32 q_index;
3927         u32 opc = OPC_INB_SSPINIIOSTART;
3928         memset(&ssp_cmd, 0, sizeof(ssp_cmd));
3929         memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8);
3930         /* data address domain added for spcv; set to 0 by host,
3931          * used internally by controller
3932          * 0 for SAS 1.1 and SAS 2.0 compatible TLR
3933          */
3934         ssp_cmd.dad_dir_m_tlr =
3935                 cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0);
3936         ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len);
3937         ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id);
3938         ssp_cmd.tag = cpu_to_le32(tag);
3939         if (task->ssp_task.enable_first_burst)
3940                 ssp_cmd.ssp_iu.efb_prio_attr |= 0x80;
3941         ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_prio << 3);
3942         ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7);
3943         memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cmd->cmnd,
3944                        task->ssp_task.cmd->cmd_len);
3945         q_index = (u32) (pm8001_dev->id & 0x00ffffff) % PM8001_MAX_INB_NUM;
3946         circularQ = &pm8001_ha->inbnd_q_tbl[q_index];
3947
3948         /* Check if encryption is set */
3949         if (pm8001_ha->chip->encrypt &&
3950                 !(pm8001_ha->encrypt_info.status) && check_enc_sas_cmd(task)) {
3951                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3952                         "Encryption enabled.Sending Encrypt SAS command 0x%x\n",
3953                         task->ssp_task.cmd->cmnd[0]));
3954                 opc = OPC_INB_SSP_INI_DIF_ENC_IO;
3955                 /* enable encryption. 0 for SAS 1.1 and SAS 2.0 compatible TLR*/
3956                 ssp_cmd.dad_dir_m_tlr = cpu_to_le32
3957                         ((data_dir_flags[task->data_dir] << 8) | 0x20 | 0x0);
3958
3959                 /* fill in PRD (scatter/gather) table, if any */
3960                 if (task->num_scatter > 1) {
3961                         pm8001_chip_make_sg(task->scatter,
3962                                                 ccb->n_elem, ccb->buf_prd);
3963                         phys_addr = ccb->ccb_dma_handle +
3964                                 offsetof(struct pm8001_ccb_info, buf_prd[0]);
3965                         ssp_cmd.enc_addr_low =
3966                                 cpu_to_le32(lower_32_bits(phys_addr));
3967                         ssp_cmd.enc_addr_high =
3968                                 cpu_to_le32(upper_32_bits(phys_addr));
3969                         ssp_cmd.enc_esgl = cpu_to_le32(1<<31);
3970                 } else if (task->num_scatter == 1) {
3971                         u64 dma_addr = sg_dma_address(task->scatter);
3972                         ssp_cmd.enc_addr_low =
3973                                 cpu_to_le32(lower_32_bits(dma_addr));
3974                         ssp_cmd.enc_addr_high =
3975                                 cpu_to_le32(upper_32_bits(dma_addr));
3976                         ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
3977                         ssp_cmd.enc_esgl = 0;
3978                         /* Check 4G Boundary */
3979                         start_addr = cpu_to_le64(dma_addr);
3980                         end_addr = (start_addr + ssp_cmd.enc_len) - 1;
3981                         end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
3982                         end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
3983                         if (end_addr_high != ssp_cmd.enc_addr_high) {
3984                                 PM8001_FAIL_DBG(pm8001_ha,
3985                                         pm8001_printk("The sg list address "
3986                                         "start_addr=0x%016llx data_len=0x%x "
3987                                         "end_addr_high=0x%08x end_addr_low="
3988                                         "0x%08x has crossed 4G boundary\n",
3989                                                 start_addr, ssp_cmd.enc_len,
3990                                                 end_addr_high, end_addr_low));
3991                                 pm8001_chip_make_sg(task->scatter, 1,
3992                                         ccb->buf_prd);
3993                                 phys_addr = ccb->ccb_dma_handle +
3994                                         offsetof(struct pm8001_ccb_info,
3995                                                 buf_prd[0]);
3996                                 ssp_cmd.enc_addr_low =
3997                                         cpu_to_le32(lower_32_bits(phys_addr));
3998                                 ssp_cmd.enc_addr_high =
3999                                         cpu_to_le32(upper_32_bits(phys_addr));
4000                                 ssp_cmd.enc_esgl = cpu_to_le32(1<<31);
4001                         }
4002                 } else if (task->num_scatter == 0) {
4003                         ssp_cmd.enc_addr_low = 0;
4004                         ssp_cmd.enc_addr_high = 0;
4005                         ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4006                         ssp_cmd.enc_esgl = 0;
4007                 }
4008                 /* XTS mode. All other fields are 0 */
4009                 ssp_cmd.key_cmode = 0x6 << 4;
4010                 /* set tweak values. Should be the start lba */
4011                 ssp_cmd.twk_val0 = cpu_to_le32((task->ssp_task.cmd->cmnd[2] << 24) |
4012                                                 (task->ssp_task.cmd->cmnd[3] << 16) |
4013                                                 (task->ssp_task.cmd->cmnd[4] << 8) |
4014                                                 (task->ssp_task.cmd->cmnd[5]));
4015         } else {
4016                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
4017                         "Sending Normal SAS command 0x%x inb q %x\n",
4018                         task->ssp_task.cmd->cmnd[0], q_index));
4019                 /* fill in PRD (scatter/gather) table, if any */
4020                 if (task->num_scatter > 1) {
4021                         pm8001_chip_make_sg(task->scatter, ccb->n_elem,
4022                                         ccb->buf_prd);
4023                         phys_addr = ccb->ccb_dma_handle +
4024                                 offsetof(struct pm8001_ccb_info, buf_prd[0]);
4025                         ssp_cmd.addr_low =
4026                                 cpu_to_le32(lower_32_bits(phys_addr));
4027                         ssp_cmd.addr_high =
4028                                 cpu_to_le32(upper_32_bits(phys_addr));
4029                         ssp_cmd.esgl = cpu_to_le32(1<<31);
4030                 } else if (task->num_scatter == 1) {
4031                         u64 dma_addr = sg_dma_address(task->scatter);
4032                         ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(dma_addr));
4033                         ssp_cmd.addr_high =
4034                                 cpu_to_le32(upper_32_bits(dma_addr));
4035                         ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4036                         ssp_cmd.esgl = 0;
4037                         /* Check 4G Boundary */
4038                         start_addr = cpu_to_le64(dma_addr);
4039                         end_addr = (start_addr + ssp_cmd.len) - 1;
4040                         end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
4041                         end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
4042                         if (end_addr_high != ssp_cmd.addr_high) {
4043                                 PM8001_FAIL_DBG(pm8001_ha,
4044                                         pm8001_printk("The sg list address "
4045                                         "start_addr=0x%016llx data_len=0x%x "
4046                                         "end_addr_high=0x%08x end_addr_low="
4047                                         "0x%08x has crossed 4G boundary\n",
4048                                                  start_addr, ssp_cmd.len,
4049                                                  end_addr_high, end_addr_low));
4050                                 pm8001_chip_make_sg(task->scatter, 1,
4051                                         ccb->buf_prd);
4052                                 phys_addr = ccb->ccb_dma_handle +
4053                                         offsetof(struct pm8001_ccb_info,
4054                                                  buf_prd[0]);
4055                                 ssp_cmd.addr_low =
4056                                         cpu_to_le32(lower_32_bits(phys_addr));
4057                                 ssp_cmd.addr_high =
4058                                         cpu_to_le32(upper_32_bits(phys_addr));
4059                                 ssp_cmd.esgl = cpu_to_le32(1<<31);
4060                         }
4061                 } else if (task->num_scatter == 0) {
4062                         ssp_cmd.addr_low = 0;
4063                         ssp_cmd.addr_high = 0;
4064                         ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4065                         ssp_cmd.esgl = 0;
4066                 }
4067         }
4068         q_index = (u32) (pm8001_dev->id & 0x00ffffff) % PM8001_MAX_OUTB_NUM;
4069         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc,
4070                                                 &ssp_cmd, q_index);
4071         return ret;
4072 }
4073
4074 static int pm80xx_chip_sata_req(struct pm8001_hba_info *pm8001_ha,
4075         struct pm8001_ccb_info *ccb)
4076 {
4077         struct sas_task *task = ccb->task;
4078         struct domain_device *dev = task->dev;
4079         struct pm8001_device *pm8001_ha_dev = dev->lldd_dev;
4080         u32 tag = ccb->ccb_tag;
4081         int ret;
4082         u32 q_index;
4083         struct sata_start_req sata_cmd;
4084         u32 hdr_tag, ncg_tag = 0;
4085         u64 phys_addr, start_addr, end_addr;
4086         u32 end_addr_high, end_addr_low;
4087         u32 ATAP = 0x0;
4088         u32 dir;
4089         struct inbound_queue_table *circularQ;
4090         unsigned long flags;
4091         u32 opc = OPC_INB_SATA_HOST_OPSTART;
4092         memset(&sata_cmd, 0, sizeof(sata_cmd));
4093         q_index = (u32) (pm8001_ha_dev->id & 0x00ffffff) % PM8001_MAX_INB_NUM;
4094         circularQ = &pm8001_ha->inbnd_q_tbl[q_index];
4095
4096         if (task->data_dir == PCI_DMA_NONE) {
4097                 ATAP = 0x04; /* no data*/
4098                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("no data\n"));
4099         } else if (likely(!task->ata_task.device_control_reg_update)) {
4100                 if (task->ata_task.dma_xfer) {
4101                         ATAP = 0x06; /* DMA */
4102                         PM8001_IO_DBG(pm8001_ha, pm8001_printk("DMA\n"));
4103                 } else {
4104                         ATAP = 0x05; /* PIO*/
4105                         PM8001_IO_DBG(pm8001_ha, pm8001_printk("PIO\n"));
4106                 }
4107                 if (task->ata_task.use_ncq &&
4108                         dev->sata_dev.command_set != ATAPI_COMMAND_SET) {
4109                         ATAP = 0x07; /* FPDMA */
4110                         PM8001_IO_DBG(pm8001_ha, pm8001_printk("FPDMA\n"));
4111                 }
4112         }
4113         if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag)) {
4114                 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
4115                 ncg_tag = hdr_tag;
4116         }
4117         dir = data_dir_flags[task->data_dir] << 8;
4118         sata_cmd.tag = cpu_to_le32(tag);
4119         sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
4120         sata_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4121
4122         sata_cmd.sata_fis = task->ata_task.fis;
4123         if (likely(!task->ata_task.device_control_reg_update))
4124                 sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */
4125         sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */
4126
4127         /* Check if encryption is set */
4128         if (pm8001_ha->chip->encrypt &&
4129                 !(pm8001_ha->encrypt_info.status) && check_enc_sat_cmd(task)) {
4130                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
4131                         "Encryption enabled.Sending Encrypt SATA cmd 0x%x\n",
4132                         sata_cmd.sata_fis.command));
4133                 opc = OPC_INB_SATA_DIF_ENC_IO;
4134
4135                 /* set encryption bit */
4136                 sata_cmd.ncqtag_atap_dir_m_dad =
4137                         cpu_to_le32(((ncg_tag & 0xff)<<16)|
4138                                 ((ATAP & 0x3f) << 10) | 0x20 | dir);
4139                                                         /* dad (bit 0-1) is 0 */
4140                 /* fill in PRD (scatter/gather) table, if any */
4141                 if (task->num_scatter > 1) {
4142                         pm8001_chip_make_sg(task->scatter,
4143                                                 ccb->n_elem, ccb->buf_prd);
4144                         phys_addr = ccb->ccb_dma_handle +
4145                                 offsetof(struct pm8001_ccb_info, buf_prd[0]);
4146                         sata_cmd.enc_addr_low = lower_32_bits(phys_addr);
4147                         sata_cmd.enc_addr_high = upper_32_bits(phys_addr);
4148                         sata_cmd.enc_esgl = cpu_to_le32(1 << 31);
4149                 } else if (task->num_scatter == 1) {
4150                         u64 dma_addr = sg_dma_address(task->scatter);
4151                         sata_cmd.enc_addr_low = lower_32_bits(dma_addr);
4152                         sata_cmd.enc_addr_high = upper_32_bits(dma_addr);
4153                         sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4154                         sata_cmd.enc_esgl = 0;
4155                         /* Check 4G Boundary */
4156                         start_addr = cpu_to_le64(dma_addr);
4157                         end_addr = (start_addr + sata_cmd.enc_len) - 1;
4158                         end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
4159                         end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
4160                         if (end_addr_high != sata_cmd.enc_addr_high) {
4161                                 PM8001_FAIL_DBG(pm8001_ha,
4162                                         pm8001_printk("The sg list address "
4163                                         "start_addr=0x%016llx data_len=0x%x "
4164                                         "end_addr_high=0x%08x end_addr_low"
4165                                         "=0x%08x has crossed 4G boundary\n",
4166                                                 start_addr, sata_cmd.enc_len,
4167                                                 end_addr_high, end_addr_low));
4168                                 pm8001_chip_make_sg(task->scatter, 1,
4169                                         ccb->buf_prd);
4170                                 phys_addr = ccb->ccb_dma_handle +
4171                                                 offsetof(struct pm8001_ccb_info,
4172                                                 buf_prd[0]);
4173                                 sata_cmd.enc_addr_low =
4174                                         lower_32_bits(phys_addr);
4175                                 sata_cmd.enc_addr_high =
4176                                         upper_32_bits(phys_addr);
4177                                 sata_cmd.enc_esgl =
4178                                         cpu_to_le32(1 << 31);
4179                         }
4180                 } else if (task->num_scatter == 0) {
4181                         sata_cmd.enc_addr_low = 0;
4182                         sata_cmd.enc_addr_high = 0;
4183                         sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4184                         sata_cmd.enc_esgl = 0;
4185                 }
4186                 /* XTS mode. All other fields are 0 */
4187                 sata_cmd.key_index_mode = 0x6 << 4;
4188                 /* set tweak values. Should be the start lba */
4189                 sata_cmd.twk_val0 =
4190                         cpu_to_le32((sata_cmd.sata_fis.lbal_exp << 24) |
4191                                         (sata_cmd.sata_fis.lbah << 16) |
4192                                         (sata_cmd.sata_fis.lbam << 8) |
4193                                         (sata_cmd.sata_fis.lbal));
4194                 sata_cmd.twk_val1 =
4195                         cpu_to_le32((sata_cmd.sata_fis.lbah_exp << 8) |
4196                                          (sata_cmd.sata_fis.lbam_exp));
4197         } else {
4198                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
4199                         "Sending Normal SATA command 0x%x inb %x\n",
4200                         sata_cmd.sata_fis.command, q_index));
4201                 /* dad (bit 0-1) is 0 */
4202                 sata_cmd.ncqtag_atap_dir_m_dad =
4203                         cpu_to_le32(((ncg_tag & 0xff)<<16) |
4204                                         ((ATAP & 0x3f) << 10) | dir);
4205
4206                 /* fill in PRD (scatter/gather) table, if any */
4207                 if (task->num_scatter > 1) {
4208                         pm8001_chip_make_sg(task->scatter,
4209                                         ccb->n_elem, ccb->buf_prd);
4210                         phys_addr = ccb->ccb_dma_handle +
4211                                 offsetof(struct pm8001_ccb_info, buf_prd[0]);
4212                         sata_cmd.addr_low = lower_32_bits(phys_addr);
4213                         sata_cmd.addr_high = upper_32_bits(phys_addr);
4214                         sata_cmd.esgl = cpu_to_le32(1 << 31);
4215                 } else if (task->num_scatter == 1) {
4216                         u64 dma_addr = sg_dma_address(task->scatter);
4217                         sata_cmd.addr_low = lower_32_bits(dma_addr);
4218                         sata_cmd.addr_high = upper_32_bits(dma_addr);
4219                         sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4220                         sata_cmd.esgl = 0;
4221                         /* Check 4G Boundary */
4222                         start_addr = cpu_to_le64(dma_addr);
4223                         end_addr = (start_addr + sata_cmd.len) - 1;
4224                         end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
4225                         end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
4226                         if (end_addr_high != sata_cmd.addr_high) {
4227                                 PM8001_FAIL_DBG(pm8001_ha,
4228                                         pm8001_printk("The sg list address "
4229                                         "start_addr=0x%016llx data_len=0x%x"
4230                                         "end_addr_high=0x%08x end_addr_low="
4231                                         "0x%08x has crossed 4G boundary\n",
4232                                                 start_addr, sata_cmd.len,
4233                                                 end_addr_high, end_addr_low));
4234                                 pm8001_chip_make_sg(task->scatter, 1,
4235                                         ccb->buf_prd);
4236                                 phys_addr = ccb->ccb_dma_handle +
4237                                         offsetof(struct pm8001_ccb_info,
4238                                         buf_prd[0]);
4239                                 sata_cmd.addr_low =
4240                                         lower_32_bits(phys_addr);
4241                                 sata_cmd.addr_high =
4242                                         upper_32_bits(phys_addr);
4243                                 sata_cmd.esgl = cpu_to_le32(1 << 31);
4244                         }
4245                 } else if (task->num_scatter == 0) {
4246                         sata_cmd.addr_low = 0;
4247                         sata_cmd.addr_high = 0;
4248                         sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4249                         sata_cmd.esgl = 0;
4250                 }
4251                         /* scsi cdb */
4252                         sata_cmd.atapi_scsi_cdb[0] =
4253                                 cpu_to_le32(((task->ata_task.atapi_packet[0]) |
4254                                 (task->ata_task.atapi_packet[1] << 8) |
4255                                 (task->ata_task.atapi_packet[2] << 16) |
4256                                 (task->ata_task.atapi_packet[3] << 24)));
4257                         sata_cmd.atapi_scsi_cdb[1] =
4258                                 cpu_to_le32(((task->ata_task.atapi_packet[4]) |
4259                                 (task->ata_task.atapi_packet[5] << 8) |
4260                                 (task->ata_task.atapi_packet[6] << 16) |
4261                                 (task->ata_task.atapi_packet[7] << 24)));
4262                         sata_cmd.atapi_scsi_cdb[2] =
4263                                 cpu_to_le32(((task->ata_task.atapi_packet[8]) |
4264                                 (task->ata_task.atapi_packet[9] << 8) |
4265                                 (task->ata_task.atapi_packet[10] << 16) |
4266                                 (task->ata_task.atapi_packet[11] << 24)));
4267                         sata_cmd.atapi_scsi_cdb[3] =
4268                                 cpu_to_le32(((task->ata_task.atapi_packet[12]) |
4269                                 (task->ata_task.atapi_packet[13] << 8) |
4270                                 (task->ata_task.atapi_packet[14] << 16) |
4271                                 (task->ata_task.atapi_packet[15] << 24)));
4272         }
4273
4274         /* Check for read log for failed drive and return */
4275         if (sata_cmd.sata_fis.command == 0x2f) {
4276                 if (pm8001_ha_dev && ((pm8001_ha_dev->id & NCQ_READ_LOG_FLAG) ||
4277                         (pm8001_ha_dev->id & NCQ_ABORT_ALL_FLAG) ||
4278                         (pm8001_ha_dev->id & NCQ_2ND_RLE_FLAG))) {
4279                         struct task_status_struct *ts;
4280
4281                         pm8001_ha_dev->id &= 0xDFFFFFFF;
4282                         ts = &task->task_status;
4283
4284                         spin_lock_irqsave(&task->task_state_lock, flags);
4285                         ts->resp = SAS_TASK_COMPLETE;
4286                         ts->stat = SAM_STAT_GOOD;
4287                         task->task_state_flags &= ~SAS_TASK_STATE_PENDING;
4288                         task->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
4289                         task->task_state_flags |= SAS_TASK_STATE_DONE;
4290                         if (unlikely((task->task_state_flags &
4291                                         SAS_TASK_STATE_ABORTED))) {
4292                                 spin_unlock_irqrestore(&task->task_state_lock,
4293                                                         flags);
4294                                 PM8001_FAIL_DBG(pm8001_ha,
4295                                         pm8001_printk("task 0x%p resp 0x%x "
4296                                         " stat 0x%x but aborted by upper layer "
4297                                         "\n", task, ts->resp, ts->stat));
4298                                 pm8001_ccb_task_free(pm8001_ha, task, ccb, tag);
4299                                 return 0;
4300                         } else if (task->uldd_task) {
4301                                 spin_unlock_irqrestore(&task->task_state_lock,
4302                                                         flags);
4303                                 pm8001_ccb_task_free(pm8001_ha, task, ccb, tag);
4304                                 mb();/* ditto */
4305                                 spin_unlock_irq(&pm8001_ha->lock);
4306                                 task->task_done(task);
4307                                 spin_lock_irq(&pm8001_ha->lock);
4308                                 return 0;
4309                         } else if (!task->uldd_task) {
4310                                 spin_unlock_irqrestore(&task->task_state_lock,
4311                                                         flags);
4312                                 pm8001_ccb_task_free(pm8001_ha, task, ccb, tag);
4313                                 mb();/*ditto*/
4314                                 spin_unlock_irq(&pm8001_ha->lock);
4315                                 task->task_done(task);
4316                                 spin_lock_irq(&pm8001_ha->lock);
4317                                 return 0;
4318                         }
4319                 }
4320         }
4321         q_index = (u32) (pm8001_ha_dev->id & 0x00ffffff) % PM8001_MAX_OUTB_NUM;
4322         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc,
4323                                                 &sata_cmd, q_index);
4324         return ret;
4325 }
4326
4327 /**
4328  * pm80xx_chip_phy_start_req - start phy via PHY_START COMMAND
4329  * @pm8001_ha: our hba card information.
4330  * @num: the inbound queue number
4331  * @phy_id: the phy id which we wanted to start up.
4332  */
4333 static int
4334 pm80xx_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id)
4335 {
4336         struct phy_start_req payload;
4337         struct inbound_queue_table *circularQ;
4338         int ret;
4339         u32 tag = 0x01;
4340         u32 opcode = OPC_INB_PHYSTART;
4341         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4342         memset(&payload, 0, sizeof(payload));
4343         payload.tag = cpu_to_le32(tag);
4344
4345         PM8001_INIT_DBG(pm8001_ha,
4346                 pm8001_printk("PHY START REQ for phy_id %d\n", phy_id));
4347         /*
4348          ** [0:7]       PHY Identifier
4349          ** [8:11]      link rate 1.5G, 3G, 6G
4350          ** [12:13] link mode 01b SAS mode; 10b SATA mode; 11b Auto mode
4351          ** [14]        0b disable spin up hold; 1b enable spin up hold
4352          ** [15] ob no change in current PHY analig setup 1b enable using SPAST
4353          */
4354         if (!IS_SPCV_12G(pm8001_ha->pdev))
4355                 payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE |
4356                                 LINKMODE_AUTO | LINKRATE_15 |
4357                                 LINKRATE_30 | LINKRATE_60 | phy_id);
4358         else
4359                 payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE |
4360                                 LINKMODE_AUTO | LINKRATE_15 |
4361                                 LINKRATE_30 | LINKRATE_60 | LINKRATE_120 |
4362                                 phy_id);
4363
4364         /* SSC Disable and SAS Analog ST configuration */
4365         /**
4366         payload.ase_sh_lm_slr_phyid =
4367                 cpu_to_le32(SSC_DISABLE_30 | SAS_ASE | SPINHOLD_DISABLE |
4368                 LINKMODE_AUTO | LINKRATE_15 | LINKRATE_30 | LINKRATE_60 |
4369                 phy_id);
4370         Have to add "SAS PHY Analog Setup SPASTI 1 Byte" Based on need
4371         **/
4372
4373         payload.sas_identify.dev_type = SAS_END_DEVICE;
4374         payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL;
4375         memcpy(payload.sas_identify.sas_addr,
4376                 pm8001_ha->sas_addr, SAS_ADDR_SIZE);
4377         payload.sas_identify.phy_id = phy_id;
4378         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload, 0);
4379         return ret;
4380 }
4381
4382 /**
4383  * pm8001_chip_phy_stop_req - start phy via PHY_STOP COMMAND
4384  * @pm8001_ha: our hba card information.
4385  * @num: the inbound queue number
4386  * @phy_id: the phy id which we wanted to start up.
4387  */
4388 static int pm80xx_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha,
4389         u8 phy_id)
4390 {
4391         struct phy_stop_req payload;
4392         struct inbound_queue_table *circularQ;
4393         int ret;
4394         u32 tag = 0x01;
4395         u32 opcode = OPC_INB_PHYSTOP;
4396         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4397         memset(&payload, 0, sizeof(payload));
4398         payload.tag = cpu_to_le32(tag);
4399         payload.phy_id = cpu_to_le32(phy_id);
4400         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload, 0);
4401         return ret;
4402 }
4403
4404 /**
4405  * see comments on pm8001_mpi_reg_resp.
4406  */
4407 static int pm80xx_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha,
4408         struct pm8001_device *pm8001_dev, u32 flag)
4409 {
4410         struct reg_dev_req payload;
4411         u32     opc;
4412         u32 stp_sspsmp_sata = 0x4;
4413         struct inbound_queue_table *circularQ;
4414         u32 linkrate, phy_id;
4415         int rc, tag = 0xdeadbeef;
4416         struct pm8001_ccb_info *ccb;
4417         u8 retryFlag = 0x1;
4418         u16 firstBurstSize = 0;
4419         u16 ITNT = 2000;
4420         struct domain_device *dev = pm8001_dev->sas_device;
4421         struct domain_device *parent_dev = dev->parent;
4422         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4423
4424         memset(&payload, 0, sizeof(payload));
4425         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4426         if (rc)
4427                 return rc;
4428         ccb = &pm8001_ha->ccb_info[tag];
4429         ccb->device = pm8001_dev;
4430         ccb->ccb_tag = tag;
4431         payload.tag = cpu_to_le32(tag);
4432
4433         if (flag == 1) {
4434                 stp_sspsmp_sata = 0x02; /*direct attached sata */
4435         } else {
4436                 if (pm8001_dev->dev_type == SAS_SATA_DEV)
4437                         stp_sspsmp_sata = 0x00; /* stp*/
4438                 else if (pm8001_dev->dev_type == SAS_END_DEVICE ||
4439                         pm8001_dev->dev_type == SAS_EDGE_EXPANDER_DEVICE ||
4440                         pm8001_dev->dev_type == SAS_FANOUT_EXPANDER_DEVICE)
4441                         stp_sspsmp_sata = 0x01; /*ssp or smp*/
4442         }
4443         if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
4444                 phy_id = parent_dev->ex_dev.ex_phy->phy_id;
4445         else
4446                 phy_id = pm8001_dev->attached_phy;
4447
4448         opc = OPC_INB_REG_DEV;
4449
4450         linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ?
4451                         pm8001_dev->sas_device->linkrate : dev->port->linkrate;
4452
4453         payload.phyid_portid =
4454                 cpu_to_le32(((pm8001_dev->sas_device->port->id) & 0xFF) |
4455                 ((phy_id & 0xFF) << 8));
4456
4457         payload.dtype_dlr_mcn_ir_retry = cpu_to_le32((retryFlag & 0x01) |
4458                 ((linkrate & 0x0F) << 24) |
4459                 ((stp_sspsmp_sata & 0x03) << 28));
4460         payload.firstburstsize_ITNexustimeout =
4461                 cpu_to_le32(ITNT | (firstBurstSize * 0x10000));
4462
4463         memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr,
4464                 SAS_ADDR_SIZE);
4465
4466         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
4467
4468         return rc;
4469 }
4470
4471 /**
4472  * pm80xx_chip_phy_ctl_req - support the local phy operation
4473  * @pm8001_ha: our hba card information.
4474  * @num: the inbound queue number
4475  * @phy_id: the phy id which we wanted to operate
4476  * @phy_op:
4477  */
4478 static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
4479         u32 phyId, u32 phy_op)
4480 {
4481         struct local_phy_ctl_req payload;
4482         struct inbound_queue_table *circularQ;
4483         int ret;
4484         u32 opc = OPC_INB_LOCAL_PHY_CONTROL;
4485         memset(&payload, 0, sizeof(payload));
4486         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4487         payload.tag = cpu_to_le32(1);
4488         payload.phyop_phyid =
4489                 cpu_to_le32(((phy_op & 0xFF) << 8) | (phyId & 0xFF));
4490         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
4491         return ret;
4492 }
4493
4494 static u32 pm80xx_chip_is_our_interupt(struct pm8001_hba_info *pm8001_ha)
4495 {
4496         u32 value;
4497 #ifdef PM8001_USE_MSIX
4498         return 1;
4499 #endif
4500         value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR);
4501         if (value)
4502                 return 1;
4503         return 0;
4504
4505 }
4506
4507 /**
4508  * pm8001_chip_isr - PM8001 isr handler.
4509  * @pm8001_ha: our hba card information.
4510  * @irq: irq number.
4511  * @stat: stat.
4512  */
4513 static irqreturn_t
4514 pm80xx_chip_isr(struct pm8001_hba_info *pm8001_ha, u8 vec)
4515 {
4516         pm80xx_chip_interrupt_disable(pm8001_ha, vec);
4517         process_oq(pm8001_ha, vec);
4518         pm80xx_chip_interrupt_enable(pm8001_ha, vec);
4519         return IRQ_HANDLED;
4520 }
4521
4522 void mpi_set_phy_profile_req(struct pm8001_hba_info *pm8001_ha,
4523         u32 operation, u32 phyid, u32 length, u32 *buf)
4524 {
4525         u32 tag , i, j = 0;
4526         int rc;
4527         struct set_phy_profile_req payload;
4528         struct inbound_queue_table *circularQ;
4529         u32 opc = OPC_INB_SET_PHY_PROFILE;
4530
4531         memset(&payload, 0, sizeof(payload));
4532         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4533         if (rc)
4534                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("Invalid tag\n"));
4535         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4536         payload.tag = cpu_to_le32(tag);
4537         payload.ppc_phyid = (((operation & 0xF) << 8) | (phyid  & 0xFF));
4538         PM8001_INIT_DBG(pm8001_ha,
4539                 pm8001_printk(" phy profile command for phy %x ,length is %d\n",
4540                         payload.ppc_phyid, length));
4541         for (i = length; i < (length + PHY_DWORD_LENGTH - 1); i++) {
4542                 payload.reserved[j] =  cpu_to_le32(*((u32 *)buf + i));
4543                 j++;
4544         }
4545         pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
4546 }
4547
4548 void pm8001_set_phy_profile(struct pm8001_hba_info *pm8001_ha,
4549         u32 length, u8 *buf)
4550 {
4551         u32 page_code, i;
4552
4553         page_code = SAS_PHY_ANALOG_SETTINGS_PAGE;
4554         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
4555                 mpi_set_phy_profile_req(pm8001_ha,
4556                         SAS_PHY_ANALOG_SETTINGS_PAGE, i, length, (u32 *)buf);
4557                 length = length + PHY_DWORD_LENGTH;
4558         }
4559         PM8001_INIT_DBG(pm8001_ha, pm8001_printk("phy settings completed\n"));
4560 }
4561 const struct pm8001_dispatch pm8001_80xx_dispatch = {
4562         .name                   = "pmc80xx",
4563         .chip_init              = pm80xx_chip_init,
4564         .chip_soft_rst          = pm80xx_chip_soft_rst,
4565         .chip_rst               = pm80xx_hw_chip_rst,
4566         .chip_iounmap           = pm8001_chip_iounmap,
4567         .isr                    = pm80xx_chip_isr,
4568         .is_our_interupt        = pm80xx_chip_is_our_interupt,
4569         .isr_process_oq         = process_oq,
4570         .interrupt_enable       = pm80xx_chip_interrupt_enable,
4571         .interrupt_disable      = pm80xx_chip_interrupt_disable,
4572         .make_prd               = pm8001_chip_make_sg,
4573         .smp_req                = pm80xx_chip_smp_req,
4574         .ssp_io_req             = pm80xx_chip_ssp_io_req,
4575         .sata_req               = pm80xx_chip_sata_req,
4576         .phy_start_req          = pm80xx_chip_phy_start_req,
4577         .phy_stop_req           = pm80xx_chip_phy_stop_req,
4578         .reg_dev_req            = pm80xx_chip_reg_dev_req,
4579         .dereg_dev_req          = pm8001_chip_dereg_dev_req,
4580         .phy_ctl_req            = pm80xx_chip_phy_ctl_req,
4581         .task_abort             = pm8001_chip_abort_task,
4582         .ssp_tm_req             = pm8001_chip_ssp_tm_req,
4583         .get_nvmd_req           = pm8001_chip_get_nvmd_req,
4584         .set_nvmd_req           = pm8001_chip_set_nvmd_req,
4585         .fw_flash_update_req    = pm8001_chip_fw_flash_update_req,
4586         .set_dev_state_req      = pm8001_chip_set_dev_state_req,
4587 };