2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2014 QLogic Corporation
5 * See LICENSE.qla2xxx for copyright and licensing details.
10 #include <linux/kernel.h>
11 #include <linux/init.h>
12 #include <linux/types.h>
13 #include <linux/module.h>
14 #include <linux/list.h>
15 #include <linux/pci.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/sched.h>
18 #include <linux/slab.h>
19 #include <linux/dmapool.h>
20 #include <linux/mempool.h>
21 #include <linux/spinlock.h>
22 #include <linux/completion.h>
23 #include <linux/interrupt.h>
24 #include <linux/workqueue.h>
25 #include <linux/firmware.h>
26 #include <linux/aer.h>
27 #include <linux/mutex.h>
29 #include <scsi/scsi.h>
30 #include <scsi/scsi_host.h>
31 #include <scsi/scsi_device.h>
32 #include <scsi/scsi_cmnd.h>
33 #include <scsi/scsi_transport_fc.h>
34 #include <scsi/scsi_bsg_fc.h>
39 #define QLA2XXX_DRIVER_NAME "qla2xxx"
40 #define QLA2XXX_APIDEV "ql2xapidev"
41 #define QLA2XXX_MANUFACTURER "QLogic Corporation"
44 * We have MAILBOX_REGISTER_COUNT sized arrays in a few places,
45 * but that's fine as we don't look at the last 24 ones for
48 #define MAILBOX_REGISTER_COUNT_2100 8
49 #define MAILBOX_REGISTER_COUNT_2200 24
50 #define MAILBOX_REGISTER_COUNT 32
52 #define QLA2200A_RISC_ROM_VER 4
56 #include "qla_settings.h"
59 * Data bit definitions
77 #define BIT_16 0x10000
78 #define BIT_17 0x20000
79 #define BIT_18 0x40000
80 #define BIT_19 0x80000
81 #define BIT_20 0x100000
82 #define BIT_21 0x200000
83 #define BIT_22 0x400000
84 #define BIT_23 0x800000
85 #define BIT_24 0x1000000
86 #define BIT_25 0x2000000
87 #define BIT_26 0x4000000
88 #define BIT_27 0x8000000
89 #define BIT_28 0x10000000
90 #define BIT_29 0x20000000
91 #define BIT_30 0x40000000
92 #define BIT_31 0x80000000
94 #define LSB(x) ((uint8_t)(x))
95 #define MSB(x) ((uint8_t)((uint16_t)(x) >> 8))
97 #define LSW(x) ((uint16_t)(x))
98 #define MSW(x) ((uint16_t)((uint32_t)(x) >> 16))
100 #define LSD(x) ((uint32_t)((uint64_t)(x)))
101 #define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16))
103 #define MAKE_HANDLE(x, y) ((uint32_t)((((uint32_t)(x)) << 16) | (uint32_t)(y)))
109 #define RD_REG_BYTE(addr) readb(addr)
110 #define RD_REG_WORD(addr) readw(addr)
111 #define RD_REG_DWORD(addr) readl(addr)
112 #define RD_REG_BYTE_RELAXED(addr) readb_relaxed(addr)
113 #define RD_REG_WORD_RELAXED(addr) readw_relaxed(addr)
114 #define RD_REG_DWORD_RELAXED(addr) readl_relaxed(addr)
115 #define WRT_REG_BYTE(addr, data) writeb(data,addr)
116 #define WRT_REG_WORD(addr, data) writew(data,addr)
117 #define WRT_REG_DWORD(addr, data) writel(data,addr)
120 * ISP83XX specific remote register addresses
122 #define QLA83XX_LED_PORT0 0x00201320
123 #define QLA83XX_LED_PORT1 0x00201328
124 #define QLA83XX_IDC_DEV_STATE 0x22102384
125 #define QLA83XX_IDC_MAJOR_VERSION 0x22102380
126 #define QLA83XX_IDC_MINOR_VERSION 0x22102398
127 #define QLA83XX_IDC_DRV_PRESENCE 0x22102388
128 #define QLA83XX_IDC_DRIVER_ACK 0x2210238c
129 #define QLA83XX_IDC_CONTROL 0x22102390
130 #define QLA83XX_IDC_AUDIT 0x22102394
131 #define QLA83XX_IDC_LOCK_RECOVERY 0x2210239c
132 #define QLA83XX_DRIVER_LOCKID 0x22102104
133 #define QLA83XX_DRIVER_LOCK 0x8111c028
134 #define QLA83XX_DRIVER_UNLOCK 0x8111c02c
135 #define QLA83XX_FLASH_LOCKID 0x22102100
136 #define QLA83XX_FLASH_LOCK 0x8111c010
137 #define QLA83XX_FLASH_UNLOCK 0x8111c014
138 #define QLA83XX_DEV_PARTINFO1 0x221023e0
139 #define QLA83XX_DEV_PARTINFO2 0x221023e4
140 #define QLA83XX_FW_HEARTBEAT 0x221020b0
141 #define QLA83XX_PEG_HALT_STATUS1 0x221020a8
142 #define QLA83XX_PEG_HALT_STATUS2 0x221020ac
144 /* 83XX: Macros defining 8200 AEN Reason codes */
145 #define IDC_DEVICE_STATE_CHANGE BIT_0
146 #define IDC_PEG_HALT_STATUS_CHANGE BIT_1
147 #define IDC_NIC_FW_REPORTED_FAILURE BIT_2
148 #define IDC_HEARTBEAT_FAILURE BIT_3
150 /* 83XX: Macros defining 8200 AEN Error-levels */
151 #define ERR_LEVEL_NON_FATAL 0x1
152 #define ERR_LEVEL_RECOVERABLE_FATAL 0x2
153 #define ERR_LEVEL_UNRECOVERABLE_FATAL 0x4
155 /* 83XX: Macros for IDC Version */
156 #define QLA83XX_SUPP_IDC_MAJOR_VERSION 0x01
157 #define QLA83XX_SUPP_IDC_MINOR_VERSION 0x0
159 /* 83XX: Macros for scheduling dpc tasks */
160 #define QLA83XX_NIC_CORE_RESET 0x1
161 #define QLA83XX_IDC_STATE_HANDLER 0x2
162 #define QLA83XX_NIC_CORE_UNRECOVERABLE 0x3
164 /* 83XX: Macros for defining IDC-Control bits */
165 #define QLA83XX_IDC_RESET_DISABLED BIT_0
166 #define QLA83XX_IDC_GRACEFUL_RESET BIT_1
168 /* 83XX: Macros for different timeouts */
169 #define QLA83XX_IDC_INITIALIZATION_TIMEOUT 30
170 #define QLA83XX_IDC_RESET_ACK_TIMEOUT 10
171 #define QLA83XX_MAX_LOCK_RECOVERY_WAIT (2 * HZ)
173 /* 83XX: Macros for defining class in DEV-Partition Info register */
174 #define QLA83XX_CLASS_TYPE_NONE 0x0
175 #define QLA83XX_CLASS_TYPE_NIC 0x1
176 #define QLA83XX_CLASS_TYPE_FCOE 0x2
177 #define QLA83XX_CLASS_TYPE_ISCSI 0x3
179 /* 83XX: Macros for IDC Lock-Recovery stages */
180 #define IDC_LOCK_RECOVERY_STAGE1 0x1 /* Stage1: Intent for
183 #define IDC_LOCK_RECOVERY_STAGE2 0x2 /* Stage2: Perform lock-recovery */
185 /* 83XX: Macros for IDC Audit type */
186 #define IDC_AUDIT_TIMESTAMP 0x0 /* IDC-AUDIT: Record timestamp of
187 * dev-state change to NEED-RESET
190 #define IDC_AUDIT_COMPLETION 0x1 /* IDC-AUDIT: Record duration of
191 * reset-recovery completion is
194 /* ISP2031: Values for laser on/off */
195 #define PORT_0_2031 0x00201340
196 #define PORT_1_2031 0x00201350
197 #define LASER_ON_2031 0x01800100
198 #define LASER_OFF_2031 0x01800180
201 * The ISP2312 v2 chip cannot access the FLASH/GPIO registers via MMIO in an
204 #define RD_REG_WORD_PIO(addr) (inw((unsigned long)addr))
205 #define WRT_REG_WORD_PIO(addr, data) (outw(data,(unsigned long)addr))
208 * Fibre Channel device definitions.
210 #define WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */
211 #define MAX_FIBRE_DEVICES_2100 512
212 #define MAX_FIBRE_DEVICES_2400 2048
213 #define MAX_FIBRE_DEVICES_LOOP 128
214 #define MAX_FIBRE_DEVICES_MAX MAX_FIBRE_DEVICES_2400
215 #define LOOPID_MAP_SIZE (ha->max_fibre_devices)
216 #define MAX_FIBRE_LUNS 0xFFFF
217 #define MAX_HOST_COUNT 16
220 * Host adapter default definitions.
222 #define MAX_BUSES 1 /* We only have one bus today */
224 #define MAX_LUNS MAX_FIBRE_LUNS
225 #define MAX_CMDS_PER_LUN 255
228 * Fibre Channel device definitions.
230 #define SNS_LAST_LOOP_ID_2100 0xfe
231 #define SNS_LAST_LOOP_ID_2300 0x7ff
233 #define LAST_LOCAL_LOOP_ID 0x7d
234 #define SNS_FL_PORT 0x7e
235 #define FABRIC_CONTROLLER 0x7f
236 #define SIMPLE_NAME_SERVER 0x80
237 #define SNS_FIRST_LOOP_ID 0x81
238 #define MANAGEMENT_SERVER 0xfe
239 #define BROADCAST 0xff
242 * There is no correspondence between an N-PORT id and an AL_PA. Therefore the
243 * valid range of an N-PORT id is 0 through 0x7ef.
245 #define NPH_LAST_HANDLE 0x7ef
246 #define NPH_MGMT_SERVER 0x7fa /* FFFFFA */
247 #define NPH_SNS 0x7fc /* FFFFFC */
248 #define NPH_FABRIC_CONTROLLER 0x7fd /* FFFFFD */
249 #define NPH_F_PORT 0x7fe /* FFFFFE */
250 #define NPH_IP_BROADCAST 0x7ff /* FFFFFF */
252 #define MAX_CMDSZ 16 /* SCSI maximum CDB size. */
255 * Timeout timer counts in seconds
257 #define PORT_RETRY_TIME 1
258 #define LOOP_DOWN_TIMEOUT 60
259 #define LOOP_DOWN_TIME 255 /* 240 */
260 #define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30)
262 #define DEFAULT_OUTSTANDING_COMMANDS 4096
263 #define MIN_OUTSTANDING_COMMANDS 128
265 /* ISP request and response entry counts (37-65535) */
266 #define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */
267 #define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */
268 #define REQUEST_ENTRY_CNT_24XX 2048 /* Number of request entries. */
269 #define REQUEST_ENTRY_CNT_83XX 8192 /* Number of request entries. */
270 #define RESPONSE_ENTRY_CNT_83XX 4096 /* Number of response entries.*/
271 #define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/
272 #define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/
273 #define RESPONSE_ENTRY_CNT_MQ 128 /* Number of response entries.*/
274 #define ATIO_ENTRY_CNT_24XX 4096 /* Number of ATIO entries. */
275 #define RESPONSE_ENTRY_CNT_FX00 256 /* Number of response entries.*/
276 #define EXTENDED_EXCH_ENTRY_CNT 32768 /* Entries for offload case */
282 * (sd.h is not exported, hence local inclusion)
283 * Data Integrity Field tuple.
285 struct sd_dif_tuple {
286 __be16 guard_tag; /* Checksum */
287 __be16 app_tag; /* Opaque storage */
288 __be32 ref_tag; /* Target LBA or indirect LBA */
295 struct scsi_cmnd *cmd; /* Linux SCSI command pkt */
296 uint32_t request_sense_length;
297 uint32_t fw_sense_length;
298 uint8_t *request_sense_ptr;
303 * SRB flag definitions
305 #define SRB_DMA_VALID BIT_0 /* Command sent to ISP */
306 #define SRB_FCP_CMND_DMA_VALID BIT_12 /* DIF: DSD List valid */
307 #define SRB_CRC_CTX_DMA_VALID BIT_2 /* DIF: context DMA valid */
308 #define SRB_CRC_PROT_DMA_VALID BIT_4 /* DIF: prot DMA valid */
309 #define SRB_CRC_CTX_DSD_VALID BIT_5 /* DIF: dsd_list valid */
311 /* To identify if a srb is of T10-CRC type. @sp => srb_t pointer */
312 #define IS_PROT_IO(sp) (sp->flags & SRB_CRC_CTX_DSD_VALID)
314 struct els_logo_payload {
319 uint8_t wwpn[WWN_SIZE];
329 #define SRB_LOGIN_RETRIED BIT_0
330 #define SRB_LOGIN_COND_PLOGI BIT_1
331 #define SRB_LOGIN_SKIP_PRLI BIT_2
335 #define ELS_DCMD_TIMEOUT 20
336 #define ELS_DCMD_LOGO 0x5
339 struct completion comp;
340 struct els_logo_payload *els_logo_pyld;
341 dma_addr_t els_logo_pyld_dma;
345 * Values for flags field below are as
346 * defined in tsk_mgmt_entry struct
347 * for control_flags field in qla_fw.h.
352 struct completion comp;
356 #define SRB_FXDISC_REQ_DMA_VALID BIT_0
357 #define SRB_FXDISC_RESP_DMA_VALID BIT_1
358 #define SRB_FXDISC_REQ_DWRD_VALID BIT_2
359 #define SRB_FXDISC_RSP_DWRD_VALID BIT_3
360 #define FXDISC_TIMEOUT 20
366 dma_addr_t req_dma_handle;
367 dma_addr_t rsp_dma_handle;
369 __le32 adapter_id_hi;
370 __le16 req_func_type;
372 __le32 req_data_extra;
376 struct completion fxiocb_comp;
383 struct completion comp;
387 struct timer_list timer;
388 void (*timeout)(void *);
391 /* Values for srb_ctx type */
392 #define SRB_LOGIN_CMD 1
393 #define SRB_LOGOUT_CMD 2
394 #define SRB_ELS_CMD_RPT 3
395 #define SRB_ELS_CMD_HST 4
397 #define SRB_ADISC_CMD 6
399 #define SRB_SCSI_CMD 8
400 #define SRB_BIDI_CMD 9
401 #define SRB_FXIOCB_DCMD 10
402 #define SRB_FXIOCB_BCMD 11
403 #define SRB_ABT_CMD 12
404 #define SRB_ELS_DCMD 13
408 struct fc_port *fcport;
415 struct srb_iocb iocb_cmd;
416 struct fc_bsg_job *bsg_job;
419 void (*done)(void *, void *, int);
420 void (*free)(void *, void *);
423 #define GET_CMD_SP(sp) (sp->u.scmd.cmd)
424 #define SET_CMD_SP(sp, cmd) (sp->u.scmd.cmd = cmd)
425 #define GET_CMD_CTX_SP(sp) (sp->u.scmd.ctx)
427 #define GET_CMD_SENSE_LEN(sp) \
428 (sp->u.scmd.request_sense_length)
429 #define SET_CMD_SENSE_LEN(sp, len) \
430 (sp->u.scmd.request_sense_length = len)
431 #define GET_CMD_SENSE_PTR(sp) \
432 (sp->u.scmd.request_sense_ptr)
433 #define SET_CMD_SENSE_PTR(sp, ptr) \
434 (sp->u.scmd.request_sense_ptr = ptr)
435 #define GET_FW_SENSE_LEN(sp) \
436 (sp->u.scmd.fw_sense_length)
437 #define SET_FW_SENSE_LEN(sp, len) \
438 (sp->u.scmd.fw_sense_length = len)
446 uint32_t transfer_size;
447 uint32_t iteration_count;
451 * ISP I/O Register Set structure definitions.
453 struct device_reg_2xxx {
454 uint16_t flash_address; /* Flash BIOS address */
455 uint16_t flash_data; /* Flash BIOS data */
456 uint16_t unused_1[1]; /* Gap */
457 uint16_t ctrl_status; /* Control/Status */
458 #define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */
459 #define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */
460 #define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */
462 uint16_t ictrl; /* Interrupt control */
463 #define ICR_EN_INT BIT_15 /* ISP enable interrupts. */
464 #define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */
466 uint16_t istatus; /* Interrupt status */
467 #define ISR_RISC_INT BIT_3 /* RISC interrupt */
469 uint16_t semaphore; /* Semaphore */
470 uint16_t nvram; /* NVRAM register. */
471 #define NVR_DESELECT 0
472 #define NVR_BUSY BIT_15
473 #define NVR_WRT_ENABLE BIT_14 /* Write enable */
474 #define NVR_PR_ENABLE BIT_13 /* Protection register enable */
475 #define NVR_DATA_IN BIT_3
476 #define NVR_DATA_OUT BIT_2
477 #define NVR_SELECT BIT_1
478 #define NVR_CLOCK BIT_0
480 #define NVR_WAIT_CNT 20000
492 uint16_t unused_2[59]; /* Gap */
493 } __attribute__((packed)) isp2100;
496 uint16_t req_q_in; /* In-Pointer */
497 uint16_t req_q_out; /* Out-Pointer */
499 uint16_t rsp_q_in; /* In-Pointer */
500 uint16_t rsp_q_out; /* Out-Pointer */
502 /* RISC to Host Status */
503 uint32_t host_status;
504 #define HSR_RISC_INT BIT_15 /* RISC interrupt */
505 #define HSR_RISC_PAUSED BIT_8 /* RISC Paused */
507 /* Host to Host Semaphore */
508 uint16_t host_semaphore;
509 uint16_t unused_3[17]; /* Gap */
543 uint16_t unused_4[10]; /* Gap */
544 } __attribute__((packed)) isp2300;
547 uint16_t fpm_diag_config;
548 uint16_t unused_5[0x4]; /* Gap */
550 uint16_t unused_5_1; /* Gap */
551 uint16_t pcr; /* Processor Control Register. */
552 uint16_t unused_6[0x5]; /* Gap */
553 uint16_t mctr; /* Memory Configuration and Timing. */
554 uint16_t unused_7[0x3]; /* Gap */
555 uint16_t fb_cmd_2100; /* Unused on 23XX */
556 uint16_t unused_8[0x3]; /* Gap */
557 uint16_t hccr; /* Host command & control register. */
558 #define HCCR_HOST_INT BIT_7 /* Host interrupt bit */
559 #define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */
561 #define HCCR_RESET_RISC 0x1000 /* Reset RISC */
562 #define HCCR_PAUSE_RISC 0x2000 /* Pause RISC */
563 #define HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */
564 #define HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */
565 #define HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */
566 #define HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */
567 #define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */
568 #define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */
570 uint16_t unused_9[5]; /* Gap */
571 uint16_t gpiod; /* GPIO Data register. */
572 uint16_t gpioe; /* GPIO Enable register. */
573 #define GPIO_LED_MASK 0x00C0
574 #define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000
575 #define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040
576 #define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080
577 #define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0
578 #define GPIO_LED_ALL_OFF 0x0000
579 #define GPIO_LED_RED_ON_OTHER_OFF 0x0001 /* isp2322 */
580 #define GPIO_LED_RGA_ON 0x00C1 /* isp2322: red green amber */
584 uint16_t unused_10[8]; /* Gap */
600 uint16_t mailbox23; /* Also probe reg. */
601 } __attribute__((packed)) isp2200;
605 struct device_reg_25xxmq {
615 struct device_reg_fx00 {
616 uint32_t mailbox0; /* 00 */
617 uint32_t mailbox1; /* 04 */
618 uint32_t mailbox2; /* 08 */
619 uint32_t mailbox3; /* 0C */
620 uint32_t mailbox4; /* 10 */
621 uint32_t mailbox5; /* 14 */
622 uint32_t mailbox6; /* 18 */
623 uint32_t mailbox7; /* 1C */
624 uint32_t mailbox8; /* 20 */
625 uint32_t mailbox9; /* 24 */
626 uint32_t mailbox10; /* 28 */
648 uint32_t aenmailbox0;
649 uint32_t aenmailbox1;
650 uint32_t aenmailbox2;
651 uint32_t aenmailbox3;
652 uint32_t aenmailbox4;
653 uint32_t aenmailbox5;
654 uint32_t aenmailbox6;
655 uint32_t aenmailbox7;
657 uint32_t req_q_in; /* A0 - Request Queue In-Pointer */
658 uint32_t req_q_out; /* A4 - Request Queue Out-Pointer */
659 /* Response Queue. */
660 uint32_t rsp_q_in; /* A8 - Response Queue In-Pointer */
661 uint32_t rsp_q_out; /* AC - Response Queue Out-Pointer */
662 /* Init values shadowed on FW Up Event */
663 uint32_t initval0; /* B0 */
664 uint32_t initval1; /* B4 */
665 uint32_t initval2; /* B8 */
666 uint32_t initval3; /* BC */
667 uint32_t initval4; /* C0 */
668 uint32_t initval5; /* C4 */
669 uint32_t initval6; /* C8 */
670 uint32_t initval7; /* CC */
671 uint32_t fwheartbeat; /* D0 */
672 uint32_t pseudoaen; /* D4 */
678 struct device_reg_2xxx isp;
679 struct device_reg_24xx isp24;
680 struct device_reg_25xxmq isp25mq;
681 struct device_reg_82xx isp82;
682 struct device_reg_fx00 ispfx00;
683 } __iomem device_reg_t;
685 #define ISP_REQ_Q_IN(ha, reg) \
686 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
687 &(reg)->u.isp2100.mailbox4 : \
688 &(reg)->u.isp2300.req_q_in)
689 #define ISP_REQ_Q_OUT(ha, reg) \
690 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
691 &(reg)->u.isp2100.mailbox4 : \
692 &(reg)->u.isp2300.req_q_out)
693 #define ISP_RSP_Q_IN(ha, reg) \
694 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
695 &(reg)->u.isp2100.mailbox5 : \
696 &(reg)->u.isp2300.rsp_q_in)
697 #define ISP_RSP_Q_OUT(ha, reg) \
698 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
699 &(reg)->u.isp2100.mailbox5 : \
700 &(reg)->u.isp2300.rsp_q_out)
702 #define ISP_ATIO_Q_IN(vha) (vha->hw->tgt.atio_q_in)
703 #define ISP_ATIO_Q_OUT(vha) (vha->hw->tgt.atio_q_out)
705 #define MAILBOX_REG(ha, reg, num) \
706 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
708 &(reg)->u.isp2100.mailbox0 + (num) : \
709 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \
710 &(reg)->u.isp2300.mailbox0 + (num))
711 #define RD_MAILBOX_REG(ha, reg, num) \
712 RD_REG_WORD(MAILBOX_REG(ha, reg, num))
713 #define WRT_MAILBOX_REG(ha, reg, num, data) \
714 WRT_REG_WORD(MAILBOX_REG(ha, reg, num), data)
716 #define FB_CMD_REG(ha, reg) \
717 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
718 &(reg)->fb_cmd_2100 : \
719 &(reg)->u.isp2300.fb_cmd)
720 #define RD_FB_CMD_REG(ha, reg) \
721 RD_REG_WORD(FB_CMD_REG(ha, reg))
722 #define WRT_FB_CMD_REG(ha, reg, data) \
723 WRT_REG_WORD(FB_CMD_REG(ha, reg), data)
726 uint32_t out_mb; /* outbound from driver */
727 uint32_t in_mb; /* Incoming from RISC */
728 uint16_t mb[MAILBOX_REGISTER_COUNT];
733 #define MBX_DMA_IN BIT_0
734 #define MBX_DMA_OUT BIT_1
735 #define IOCTL_CMD BIT_2
739 uint32_t out_mb; /* outbound from driver */
740 uint32_t in_mb; /* Incoming from RISC */
741 uint32_t mb[MAILBOX_REGISTER_COUNT];
746 #define MBX_DMA_IN BIT_0
747 #define MBX_DMA_OUT BIT_1
748 #define IOCTL_CMD BIT_2
752 #define MBX_TOV_SECONDS 30
755 * ISP product identification definitions in mailboxes after reset.
757 #define PROD_ID_1 0x4953
758 #define PROD_ID_2 0x0000
759 #define PROD_ID_2a 0x5020
760 #define PROD_ID_3 0x2020
763 * ISP mailbox Self-Test status codes
765 #define MBS_FRM_ALIVE 0 /* Firmware Alive. */
766 #define MBS_CHKSUM_ERR 1 /* Checksum Error. */
767 #define MBS_BUSY 4 /* Busy. */
770 * ISP mailbox command complete status codes
772 #define MBS_COMMAND_COMPLETE 0x4000
773 #define MBS_INVALID_COMMAND 0x4001
774 #define MBS_HOST_INTERFACE_ERROR 0x4002
775 #define MBS_TEST_FAILED 0x4003
776 #define MBS_COMMAND_ERROR 0x4005
777 #define MBS_COMMAND_PARAMETER_ERROR 0x4006
778 #define MBS_PORT_ID_USED 0x4007
779 #define MBS_LOOP_ID_USED 0x4008
780 #define MBS_ALL_IDS_IN_USE 0x4009
781 #define MBS_NOT_LOGGED_IN 0x400A
782 #define MBS_LINK_DOWN_ERROR 0x400B
783 #define MBS_DIAG_ECHO_TEST_ERROR 0x400C
786 * ISP mailbox asynchronous event status codes
788 #define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */
789 #define MBA_RESET 0x8001 /* Reset Detected. */
790 #define MBA_SYSTEM_ERR 0x8002 /* System Error. */
791 #define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */
792 #define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */
793 #define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */
794 #define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */
796 #define MBA_LOOP_UP 0x8011 /* FC Loop UP. */
797 #define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */
798 #define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */
799 #define MBA_PORT_UPDATE 0x8014 /* Port Database update. */
800 #define MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */
801 #define MBA_LIP_F8 0x8016 /* Received a LIP F8. */
802 #define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */
803 #define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */
804 #define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */
805 #define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */
806 #define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */
807 #define MBA_IP_RECEIVE 0x8023 /* IP Received. */
808 #define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */
809 #define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */
810 #define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */
811 #define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */
813 #define MBA_TRACE_NOTIFICATION 0x8028 /* Trace/Diagnostic notification. */
814 #define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */
815 #define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */
816 #define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */
817 #define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */
818 #define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */
819 #define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */
820 #define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */
821 #define MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */
822 #define MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */
823 #define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */
824 #define MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */
825 #define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */
826 #define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */
827 #define MBA_FW_NOT_STARTED 0x8050 /* Firmware not started */
828 #define MBA_FW_STARTING 0x8051 /* Firmware starting */
829 #define MBA_FW_RESTART_CMPLT 0x8060 /* Firmware restart complete */
830 #define MBA_INIT_REQUIRED 0x8061 /* Initialization required */
831 #define MBA_SHUTDOWN_REQUESTED 0x8062 /* Shutdown Requested */
832 #define MBA_DPORT_DIAGNOSTICS 0x8080 /* D-port Diagnostics */
833 #define MBA_FW_INIT_FAILURE 0x8401 /* Firmware initialization failure */
834 #define MBA_MIRROR_LUN_CHANGE 0x8402 /* Mirror LUN State Change
836 #define MBA_FW_POLL_STATE 0x8600 /* Firmware in poll diagnostic state */
837 #define MBA_FW_RESET_FCT 0x8502 /* Firmware reset factory defaults */
838 #define MBA_FW_INIT_INPROGRESS 0x8500 /* Firmware boot in progress */
839 /* 83XX FCoE specific */
840 #define MBA_IDC_AEN 0x8200 /* FCoE: NIC Core state change AEN */
842 /* Interrupt type codes */
843 #define INTR_ROM_MB_SUCCESS 0x1
844 #define INTR_ROM_MB_FAILED 0x2
845 #define INTR_MB_SUCCESS 0x10
846 #define INTR_MB_FAILED 0x11
847 #define INTR_ASYNC_EVENT 0x12
848 #define INTR_RSP_QUE_UPDATE 0x13
849 #define INTR_RSP_QUE_UPDATE_83XX 0x14
850 #define INTR_ATIO_QUE_UPDATE 0x1C
851 #define INTR_ATIO_RSP_QUE_UPDATE 0x1D
853 /* ISP mailbox loopback echo diagnostic error code */
854 #define MBS_LB_RESET 0x17
856 * Firmware options 1, 2, 3.
858 #define FO1_AE_ON_LIPF8 BIT_0
859 #define FO1_AE_ALL_LIP_RESET BIT_1
860 #define FO1_CTIO_RETRY BIT_3
861 #define FO1_DISABLE_LIP_F7_SW BIT_4
862 #define FO1_DISABLE_100MS_LOS_WAIT BIT_5
863 #define FO1_DISABLE_GPIO6_7 BIT_6 /* LED bits */
864 #define FO1_AE_ON_LOOP_INIT_ERR BIT_7
865 #define FO1_SET_EMPHASIS_SWING BIT_8
866 #define FO1_AE_AUTO_BYPASS BIT_9
867 #define FO1_ENABLE_PURE_IOCB BIT_10
868 #define FO1_AE_PLOGI_RJT BIT_11
869 #define FO1_ENABLE_ABORT_SEQUENCE BIT_12
870 #define FO1_AE_QUEUE_FULL BIT_13
872 #define FO2_ENABLE_ATIO_TYPE_3 BIT_0
873 #define FO2_REV_LOOPBACK BIT_1
875 #define FO3_ENABLE_EMERG_IOCB BIT_0
876 #define FO3_AE_RND_ERROR BIT_1
878 /* 24XX additional firmware options */
879 #define ADD_FO_COUNT 3
880 #define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6 /* LED bits */
881 #define ADD_FO1_ENABLE_PUREX_IOCB BIT_10
883 #define ADD_FO2_ENABLE_SEL_CLS2 BIT_5
885 #define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14
888 * ISP mailbox commands
890 #define MBC_LOAD_RAM 1 /* Load RAM. */
891 #define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */
892 #define MBC_READ_RAM_WORD 5 /* Read RAM word. */
893 #define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */
894 #define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */
895 #define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */
896 #define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */
897 #define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */
898 #define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */
899 #define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */
900 #define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */
901 #define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */
902 #define MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */
903 #define MBC_STOP_FIRMWARE 0x14 /* Stop firmware. */
904 #define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */
905 #define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */
906 #define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */
907 #define MBC_RESET 0x18 /* Reset. */
908 #define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */
909 #define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */
910 #define MBC_DISABLE_VI 0x24 /* Disable VI operation. */
911 #define MBC_ENABLE_VI 0x25 /* Enable VI operation. */
912 #define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */
913 #define MBC_GET_MEM_OFFLOAD_CNTRL_STAT 0x34 /* Memory Offload ctrl/Stat*/
914 #define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */
915 #define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */
916 #define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */
917 #define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */
918 #define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */
919 #define MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */
920 #define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */
921 #define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */
922 #define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */
923 #define MBC_CONFIGURE_VF 0x4b /* Configure VFs */
924 #define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */
925 #define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */
926 #define MBC_PORT_LOGOUT 0x56 /* Port Logout request */
927 #define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */
928 #define MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */
929 #define MBC_GET_RNID_PARAMS 0x5a /* Get RNID parameters */
930 #define MBC_DATA_RATE 0x5d /* Data Rate */
931 #define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */
932 #define MBC_INITIATE_LIP 0x62 /* Initiate Loop */
933 /* Initialization Procedure */
934 #define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */
935 #define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */
936 #define MBC_CLEAR_ACA 0x65 /* Clear ACA. */
937 #define MBC_TARGET_RESET 0x66 /* Target Reset. */
938 #define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */
939 #define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */
940 #define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */
941 #define MBC_GET_PORT_NAME 0x6a /* Get port name. */
942 #define MBC_GET_LINK_STATUS 0x6b /* Get port link status. */
943 #define MBC_LIP_RESET 0x6c /* LIP reset. */
944 #define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */
946 #define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */
947 #define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */
948 #define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */
949 #define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */
950 #define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */
951 #define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */
952 #define MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */
953 #define MBC_UNLOAD_IP 0x79 /* Shutdown IP */
954 #define MBC_GET_ID_LIST 0x7C /* Get Port ID list. */
955 #define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */
956 #define MBC_LUN_RESET 0x7E /* Send LUN reset */
959 * all the Mt. Rainier mailbox command codes that clash with FC/FCoE ones
960 * should be defined with MBC_MR_*
962 #define MBC_MR_DRV_SHUTDOWN 0x6A
965 * ISP24xx mailbox commands
967 #define MBC_WRITE_SERDES 0x3 /* Write serdes word. */
968 #define MBC_READ_SERDES 0x4 /* Read serdes word. */
969 #define MBC_LOAD_DUMP_MPI_RAM 0x5 /* Load/Dump MPI RAM. */
970 #define MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */
971 #define MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */
972 #define MBC_PORT_PARAMS 0x1A /* Port iDMA Parameters. */
973 #define MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */
974 #define MBC_TRACE_CONTROL 0x27 /* Trace control command. */
975 #define MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */
976 #define MBC_WRITE_SFP 0x30 /* Write SFP Data. */
977 #define MBC_READ_SFP 0x31 /* Read SFP Data. */
978 #define MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */
979 #define MBC_DPORT_DIAGNOSTICS 0x47 /* D-Port Diagnostics */
980 #define MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */
981 #define MBC_MID_GET_VP_DATABASE 0x49 /* MID Get VP Database. */
982 #define MBC_MID_GET_VP_ENTRY 0x4a /* MID Get VP Entry. */
983 #define MBC_HOST_MEMORY_COPY 0x53 /* Host Memory Copy. */
984 #define MBC_SEND_RNFT_ELS 0x5e /* Send RNFT ELS request */
985 #define MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */
986 #define MBC_LINK_INITIALIZATION 0x72 /* Do link initialization. */
987 #define MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */
988 #define MBC_PORT_RESET 0x120 /* Port Reset */
989 #define MBC_SET_PORT_CONFIG 0x122 /* Set port configuration */
990 #define MBC_GET_PORT_CONFIG 0x123 /* Get port configuration */
993 * ISP81xx mailbox commands
995 #define MBC_WRITE_MPI_REGISTER 0x01 /* Write MPI Register. */
998 * ISP8044 mailbox commands
1000 #define MBC_SET_GET_ETH_SERDES_REG 0x150
1001 #define HCS_WRITE_SERDES 0x3
1002 #define HCS_READ_SERDES 0x4
1004 /* Firmware return data sizes */
1005 #define FCAL_MAP_SIZE 128
1007 /* Mailbox bit definitions for out_mb and in_mb */
1008 #define MBX_31 BIT_31
1009 #define MBX_30 BIT_30
1010 #define MBX_29 BIT_29
1011 #define MBX_28 BIT_28
1012 #define MBX_27 BIT_27
1013 #define MBX_26 BIT_26
1014 #define MBX_25 BIT_25
1015 #define MBX_24 BIT_24
1016 #define MBX_23 BIT_23
1017 #define MBX_22 BIT_22
1018 #define MBX_21 BIT_21
1019 #define MBX_20 BIT_20
1020 #define MBX_19 BIT_19
1021 #define MBX_18 BIT_18
1022 #define MBX_17 BIT_17
1023 #define MBX_16 BIT_16
1024 #define MBX_15 BIT_15
1025 #define MBX_14 BIT_14
1026 #define MBX_13 BIT_13
1027 #define MBX_12 BIT_12
1028 #define MBX_11 BIT_11
1029 #define MBX_10 BIT_10
1041 #define RNID_TYPE_SET_VERSION 0x9
1042 #define RNID_TYPE_ASIC_TEMP 0xC
1045 * Firmware state codes from get firmware state mailbox command
1047 #define FSTATE_CONFIG_WAIT 0
1048 #define FSTATE_WAIT_AL_PA 1
1049 #define FSTATE_WAIT_LOGIN 2
1050 #define FSTATE_READY 3
1051 #define FSTATE_LOSS_OF_SYNC 4
1052 #define FSTATE_ERROR 5
1053 #define FSTATE_REINIT 6
1054 #define FSTATE_NON_PART 7
1056 #define FSTATE_CONFIG_CORRECT 0
1057 #define FSTATE_P2P_RCV_LIP 1
1058 #define FSTATE_P2P_CHOOSE_LOOP 2
1059 #define FSTATE_P2P_RCV_UNIDEN_LIP 3
1060 #define FSTATE_FATAL_ERROR 4
1061 #define FSTATE_LOOP_BACK_CONN 5
1064 * Port Database structure definition
1065 * Little endian except where noted.
1067 #define PORT_DATABASE_SIZE 128 /* bytes */
1071 uint8_t master_state;
1072 uint8_t slave_state;
1073 uint8_t reserved[2];
1074 uint8_t hard_address;
1077 uint8_t node_name[WWN_SIZE];
1078 uint8_t port_name[WWN_SIZE];
1079 uint16_t execution_throttle;
1080 uint16_t execution_count;
1081 uint8_t reset_count;
1083 uint16_t resource_allocation;
1084 uint16_t current_allocation;
1085 uint16_t queue_head;
1086 uint16_t queue_tail;
1087 uint16_t transmit_execution_list_next;
1088 uint16_t transmit_execution_list_previous;
1089 uint16_t common_features;
1090 uint16_t total_concurrent_sequences;
1091 uint16_t RO_by_information_category;
1094 uint16_t receive_data_size;
1095 uint16_t concurrent_sequences;
1096 uint16_t open_sequences_per_exchange;
1097 uint16_t lun_abort_flags;
1098 uint16_t lun_stop_flags;
1099 uint16_t stop_queue_head;
1100 uint16_t stop_queue_tail;
1101 uint16_t port_retry_timer;
1102 uint16_t next_sequence_id;
1103 uint16_t frame_count;
1104 uint16_t PRLI_payload_length;
1105 uint8_t prli_svc_param_word_0[2]; /* Big endian */
1106 /* Bits 15-0 of word 0 */
1107 uint8_t prli_svc_param_word_3[2]; /* Big endian */
1108 /* Bits 15-0 of word 3 */
1110 uint16_t extended_lun_info_list_pointer;
1111 uint16_t extended_lun_stop_list_pointer;
1115 * Port database slave/master states
1117 #define PD_STATE_DISCOVERY 0
1118 #define PD_STATE_WAIT_DISCOVERY_ACK 1
1119 #define PD_STATE_PORT_LOGIN 2
1120 #define PD_STATE_WAIT_PORT_LOGIN_ACK 3
1121 #define PD_STATE_PROCESS_LOGIN 4
1122 #define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5
1123 #define PD_STATE_PORT_LOGGED_IN 6
1124 #define PD_STATE_PORT_UNAVAILABLE 7
1125 #define PD_STATE_PROCESS_LOGOUT 8
1126 #define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9
1127 #define PD_STATE_PORT_LOGOUT 10
1128 #define PD_STATE_WAIT_PORT_LOGOUT_ACK 11
1131 #define QLA_ZIO_MODE_6 (BIT_2 | BIT_1)
1132 #define QLA_ZIO_DISABLED 0
1133 #define QLA_ZIO_DEFAULT_TIMER 2
1136 * ISP Initialization Control Block.
1137 * Little endian except where noted.
1139 #define ICB_VERSION 1
1145 * LSB BIT 0 = Enable Hard Loop Id
1146 * LSB BIT 1 = Enable Fairness
1147 * LSB BIT 2 = Enable Full-Duplex
1148 * LSB BIT 3 = Enable Fast Posting
1149 * LSB BIT 4 = Enable Target Mode
1150 * LSB BIT 5 = Disable Initiator Mode
1151 * LSB BIT 6 = Enable ADISC
1152 * LSB BIT 7 = Enable Target Inquiry Data
1154 * MSB BIT 0 = Enable PDBC Notify
1155 * MSB BIT 1 = Non Participating LIP
1156 * MSB BIT 2 = Descending Loop ID Search
1157 * MSB BIT 3 = Acquire Loop ID in LIPA
1158 * MSB BIT 4 = Stop PortQ on Full Status
1159 * MSB BIT 5 = Full Login after LIP
1160 * MSB BIT 6 = Node Name Option
1161 * MSB BIT 7 = Ext IFWCB enable bit
1163 uint8_t firmware_options[2];
1165 uint16_t frame_payload_size;
1166 uint16_t max_iocb_allocation;
1167 uint16_t execution_throttle;
1168 uint8_t retry_count;
1169 uint8_t retry_delay; /* unused */
1170 uint8_t port_name[WWN_SIZE]; /* Big endian. */
1171 uint16_t hard_address;
1172 uint8_t inquiry_data;
1173 uint8_t login_timeout;
1174 uint8_t node_name[WWN_SIZE]; /* Big endian. */
1176 uint16_t request_q_outpointer;
1177 uint16_t response_q_inpointer;
1178 uint16_t request_q_length;
1179 uint16_t response_q_length;
1180 uint32_t request_q_address[2];
1181 uint32_t response_q_address[2];
1183 uint16_t lun_enables;
1184 uint8_t command_resource_count;
1185 uint8_t immediate_notify_resource_count;
1187 uint8_t reserved_2[2];
1190 * LSB BIT 0 = Timer Operation mode bit 0
1191 * LSB BIT 1 = Timer Operation mode bit 1
1192 * LSB BIT 2 = Timer Operation mode bit 2
1193 * LSB BIT 3 = Timer Operation mode bit 3
1194 * LSB BIT 4 = Init Config Mode bit 0
1195 * LSB BIT 5 = Init Config Mode bit 1
1196 * LSB BIT 6 = Init Config Mode bit 2
1197 * LSB BIT 7 = Enable Non part on LIHA failure
1199 * MSB BIT 0 = Enable class 2
1200 * MSB BIT 1 = Enable ACK0
1203 * MSB BIT 4 = FC Tape Enable
1204 * MSB BIT 5 = Enable FC Confirm
1205 * MSB BIT 6 = Enable command queuing in target mode
1206 * MSB BIT 7 = No Logo On Link Down
1208 uint8_t add_firmware_options[2];
1210 uint8_t response_accumulation_timer;
1211 uint8_t interrupt_delay_timer;
1214 * LSB BIT 0 = Enable Read xfr_rdy
1215 * LSB BIT 1 = Soft ID only
1218 * LSB BIT 4 = FCP RSP Payload [0]
1219 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
1220 * LSB BIT 6 = Enable Out-of-Order frame handling
1221 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
1223 * MSB BIT 0 = Sbus enable - 2300
1227 * MSB BIT 4 = LED mode
1228 * MSB BIT 5 = enable 50 ohm termination
1229 * MSB BIT 6 = Data Rate (2300 only)
1230 * MSB BIT 7 = Data Rate (2300 only)
1232 uint8_t special_options[2];
1234 uint8_t reserved_3[26];
1238 * Get Link Status mailbox command return buffer.
1240 #define GLSO_SEND_RPS BIT_0
1241 #define GLSO_USE_DID BIT_3
1243 struct link_statistics {
1244 uint32_t link_fail_cnt;
1245 uint32_t loss_sync_cnt;
1246 uint32_t loss_sig_cnt;
1247 uint32_t prim_seq_err_cnt;
1248 uint32_t inval_xmit_word_cnt;
1249 uint32_t inval_crc_cnt;
1251 uint32_t unused1[0x1a];
1254 uint32_t discarded_frames;
1255 uint32_t dropped_frames;
1256 uint32_t unused2[1];
1261 * NVRAM Command values.
1263 #define NV_START_BIT BIT_2
1264 #define NV_WRITE_OP (BIT_26+BIT_24)
1265 #define NV_READ_OP (BIT_26+BIT_25)
1266 #define NV_ERASE_OP (BIT_26+BIT_25+BIT_24)
1267 #define NV_MASK_OP (BIT_26+BIT_25+BIT_24)
1268 #define NV_DELAY_COUNT 10
1271 * QLogic ISP2100, ISP2200 and ISP2300 NVRAM structure definition.
1278 uint8_t nvram_version;
1282 * NVRAM RISC parameter block
1284 uint8_t parameter_block_version;
1288 * LSB BIT 0 = Enable Hard Loop Id
1289 * LSB BIT 1 = Enable Fairness
1290 * LSB BIT 2 = Enable Full-Duplex
1291 * LSB BIT 3 = Enable Fast Posting
1292 * LSB BIT 4 = Enable Target Mode
1293 * LSB BIT 5 = Disable Initiator Mode
1294 * LSB BIT 6 = Enable ADISC
1295 * LSB BIT 7 = Enable Target Inquiry Data
1297 * MSB BIT 0 = Enable PDBC Notify
1298 * MSB BIT 1 = Non Participating LIP
1299 * MSB BIT 2 = Descending Loop ID Search
1300 * MSB BIT 3 = Acquire Loop ID in LIPA
1301 * MSB BIT 4 = Stop PortQ on Full Status
1302 * MSB BIT 5 = Full Login after LIP
1303 * MSB BIT 6 = Node Name Option
1304 * MSB BIT 7 = Ext IFWCB enable bit
1306 uint8_t firmware_options[2];
1308 uint16_t frame_payload_size;
1309 uint16_t max_iocb_allocation;
1310 uint16_t execution_throttle;
1311 uint8_t retry_count;
1312 uint8_t retry_delay; /* unused */
1313 uint8_t port_name[WWN_SIZE]; /* Big endian. */
1314 uint16_t hard_address;
1315 uint8_t inquiry_data;
1316 uint8_t login_timeout;
1317 uint8_t node_name[WWN_SIZE]; /* Big endian. */
1320 * LSB BIT 0 = Timer Operation mode bit 0
1321 * LSB BIT 1 = Timer Operation mode bit 1
1322 * LSB BIT 2 = Timer Operation mode bit 2
1323 * LSB BIT 3 = Timer Operation mode bit 3
1324 * LSB BIT 4 = Init Config Mode bit 0
1325 * LSB BIT 5 = Init Config Mode bit 1
1326 * LSB BIT 6 = Init Config Mode bit 2
1327 * LSB BIT 7 = Enable Non part on LIHA failure
1329 * MSB BIT 0 = Enable class 2
1330 * MSB BIT 1 = Enable ACK0
1333 * MSB BIT 4 = FC Tape Enable
1334 * MSB BIT 5 = Enable FC Confirm
1335 * MSB BIT 6 = Enable command queuing in target mode
1336 * MSB BIT 7 = No Logo On Link Down
1338 uint8_t add_firmware_options[2];
1340 uint8_t response_accumulation_timer;
1341 uint8_t interrupt_delay_timer;
1344 * LSB BIT 0 = Enable Read xfr_rdy
1345 * LSB BIT 1 = Soft ID only
1348 * LSB BIT 4 = FCP RSP Payload [0]
1349 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
1350 * LSB BIT 6 = Enable Out-of-Order frame handling
1351 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
1353 * MSB BIT 0 = Sbus enable - 2300
1357 * MSB BIT 4 = LED mode
1358 * MSB BIT 5 = enable 50 ohm termination
1359 * MSB BIT 6 = Data Rate (2300 only)
1360 * MSB BIT 7 = Data Rate (2300 only)
1362 uint8_t special_options[2];
1364 /* Reserved for expanded RISC parameter block */
1365 uint8_t reserved_2[22];
1368 * LSB BIT 0 = Tx Sensitivity 1G bit 0
1369 * LSB BIT 1 = Tx Sensitivity 1G bit 1
1370 * LSB BIT 2 = Tx Sensitivity 1G bit 2
1371 * LSB BIT 3 = Tx Sensitivity 1G bit 3
1372 * LSB BIT 4 = Rx Sensitivity 1G bit 0
1373 * LSB BIT 5 = Rx Sensitivity 1G bit 1
1374 * LSB BIT 6 = Rx Sensitivity 1G bit 2
1375 * LSB BIT 7 = Rx Sensitivity 1G bit 3
1377 * MSB BIT 0 = Tx Sensitivity 2G bit 0
1378 * MSB BIT 1 = Tx Sensitivity 2G bit 1
1379 * MSB BIT 2 = Tx Sensitivity 2G bit 2
1380 * MSB BIT 3 = Tx Sensitivity 2G bit 3
1381 * MSB BIT 4 = Rx Sensitivity 2G bit 0
1382 * MSB BIT 5 = Rx Sensitivity 2G bit 1
1383 * MSB BIT 6 = Rx Sensitivity 2G bit 2
1384 * MSB BIT 7 = Rx Sensitivity 2G bit 3
1386 * LSB BIT 0 = Output Swing 1G bit 0
1387 * LSB BIT 1 = Output Swing 1G bit 1
1388 * LSB BIT 2 = Output Swing 1G bit 2
1389 * LSB BIT 3 = Output Emphasis 1G bit 0
1390 * LSB BIT 4 = Output Emphasis 1G bit 1
1391 * LSB BIT 5 = Output Swing 2G bit 0
1392 * LSB BIT 6 = Output Swing 2G bit 1
1393 * LSB BIT 7 = Output Swing 2G bit 2
1395 * MSB BIT 0 = Output Emphasis 2G bit 0
1396 * MSB BIT 1 = Output Emphasis 2G bit 1
1397 * MSB BIT 2 = Output Enable
1404 uint8_t seriallink_options[4];
1407 * NVRAM host parameter block
1409 * LSB BIT 0 = Enable spinup delay
1410 * LSB BIT 1 = Disable BIOS
1411 * LSB BIT 2 = Enable Memory Map BIOS
1412 * LSB BIT 3 = Enable Selectable Boot
1413 * LSB BIT 4 = Disable RISC code load
1414 * LSB BIT 5 = Set cache line size 1
1415 * LSB BIT 6 = PCI Parity Disable
1416 * LSB BIT 7 = Enable extended logging
1418 * MSB BIT 0 = Enable 64bit addressing
1419 * MSB BIT 1 = Enable lip reset
1420 * MSB BIT 2 = Enable lip full login
1421 * MSB BIT 3 = Enable target reset
1422 * MSB BIT 4 = Enable database storage
1423 * MSB BIT 5 = Enable cache flush read
1424 * MSB BIT 6 = Enable database load
1425 * MSB BIT 7 = Enable alternate WWN
1429 uint8_t boot_node_name[WWN_SIZE];
1430 uint8_t boot_lun_number;
1431 uint8_t reset_delay;
1432 uint8_t port_down_retry_count;
1433 uint8_t boot_id_number;
1434 uint16_t max_luns_per_target;
1435 uint8_t fcode_boot_port_name[WWN_SIZE];
1436 uint8_t alternate_port_name[WWN_SIZE];
1437 uint8_t alternate_node_name[WWN_SIZE];
1440 * BIT 0 = Selective Login
1441 * BIT 1 = Alt-Boot Enable
1443 * BIT 3 = Boot Order List
1445 * BIT 5 = Selective LUN
1449 uint8_t efi_parameters;
1451 uint8_t link_down_timeout;
1453 uint8_t adapter_id[16];
1455 uint8_t alt1_boot_node_name[WWN_SIZE];
1456 uint16_t alt1_boot_lun_number;
1457 uint8_t alt2_boot_node_name[WWN_SIZE];
1458 uint16_t alt2_boot_lun_number;
1459 uint8_t alt3_boot_node_name[WWN_SIZE];
1460 uint16_t alt3_boot_lun_number;
1461 uint8_t alt4_boot_node_name[WWN_SIZE];
1462 uint16_t alt4_boot_lun_number;
1463 uint8_t alt5_boot_node_name[WWN_SIZE];
1464 uint16_t alt5_boot_lun_number;
1465 uint8_t alt6_boot_node_name[WWN_SIZE];
1466 uint16_t alt6_boot_lun_number;
1467 uint8_t alt7_boot_node_name[WWN_SIZE];
1468 uint16_t alt7_boot_lun_number;
1470 uint8_t reserved_3[2];
1472 /* Offset 200-215 : Model Number */
1473 uint8_t model_number[16];
1475 /* OEM related items */
1476 uint8_t oem_specific[16];
1479 * NVRAM Adapter Features offset 232-239
1481 * LSB BIT 0 = External GBIC
1482 * LSB BIT 1 = Risc RAM parity
1483 * LSB BIT 2 = Buffer Plus Module
1484 * LSB BIT 3 = Multi Chip Adapter
1485 * LSB BIT 4 = Internal connector
1499 uint8_t adapter_features[2];
1501 uint8_t reserved_4[16];
1503 /* Subsystem vendor ID for ISP2200 */
1504 uint16_t subsystem_vendor_id_2200;
1506 /* Subsystem device ID for ISP2200 */
1507 uint16_t subsystem_device_id_2200;
1514 * ISP queue - response queue entry definition.
1517 uint8_t entry_type; /* Entry type. */
1518 uint8_t entry_count; /* Entry count. */
1519 uint8_t sys_define; /* System defined. */
1520 uint8_t entry_status; /* Entry Status. */
1521 uint32_t handle; /* System defined handle */
1524 #define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */
1528 * ISP queue - ATIO queue entry definition.
1531 uint8_t entry_type; /* Entry type. */
1532 uint8_t entry_count; /* Entry count. */
1535 #define ATIO_PROCESSED 0xDEADDEAD /* Signature */
1546 #define SET_TARGET_ID(ha, to, from) \
1548 if (HAS_EXTENDED_IDS(ha)) \
1549 to.extended = cpu_to_le16(from); \
1551 to.id.standard = (uint8_t)from; \
1555 * ISP queue - command entry structure definition.
1557 #define COMMAND_TYPE 0x11 /* Command entry */
1559 uint8_t entry_type; /* Entry type. */
1560 uint8_t entry_count; /* Entry count. */
1561 uint8_t sys_define; /* System defined. */
1562 uint8_t entry_status; /* Entry Status. */
1563 uint32_t handle; /* System handle. */
1564 target_id_t target; /* SCSI ID */
1565 uint16_t lun; /* SCSI LUN */
1566 uint16_t control_flags; /* Control flags. */
1567 #define CF_WRITE BIT_6
1568 #define CF_READ BIT_5
1569 #define CF_SIMPLE_TAG BIT_3
1570 #define CF_ORDERED_TAG BIT_2
1571 #define CF_HEAD_TAG BIT_1
1572 uint16_t reserved_1;
1573 uint16_t timeout; /* Command timeout. */
1574 uint16_t dseg_count; /* Data segment count. */
1575 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1576 uint32_t byte_count; /* Total byte count. */
1577 uint32_t dseg_0_address; /* Data segment 0 address. */
1578 uint32_t dseg_0_length; /* Data segment 0 length. */
1579 uint32_t dseg_1_address; /* Data segment 1 address. */
1580 uint32_t dseg_1_length; /* Data segment 1 length. */
1581 uint32_t dseg_2_address; /* Data segment 2 address. */
1582 uint32_t dseg_2_length; /* Data segment 2 length. */
1586 * ISP queue - 64-Bit addressing, command entry structure definition.
1588 #define COMMAND_A64_TYPE 0x19 /* Command A64 entry */
1590 uint8_t entry_type; /* Entry type. */
1591 uint8_t entry_count; /* Entry count. */
1592 uint8_t sys_define; /* System defined. */
1593 uint8_t entry_status; /* Entry Status. */
1594 uint32_t handle; /* System handle. */
1595 target_id_t target; /* SCSI ID */
1596 uint16_t lun; /* SCSI LUN */
1597 uint16_t control_flags; /* Control flags. */
1598 uint16_t reserved_1;
1599 uint16_t timeout; /* Command timeout. */
1600 uint16_t dseg_count; /* Data segment count. */
1601 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1602 uint32_t byte_count; /* Total byte count. */
1603 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1604 uint32_t dseg_0_length; /* Data segment 0 length. */
1605 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1606 uint32_t dseg_1_length; /* Data segment 1 length. */
1607 } cmd_a64_entry_t, request_t;
1610 * ISP queue - continuation entry structure definition.
1612 #define CONTINUE_TYPE 0x02 /* Continuation entry. */
1614 uint8_t entry_type; /* Entry type. */
1615 uint8_t entry_count; /* Entry count. */
1616 uint8_t sys_define; /* System defined. */
1617 uint8_t entry_status; /* Entry Status. */
1619 uint32_t dseg_0_address; /* Data segment 0 address. */
1620 uint32_t dseg_0_length; /* Data segment 0 length. */
1621 uint32_t dseg_1_address; /* Data segment 1 address. */
1622 uint32_t dseg_1_length; /* Data segment 1 length. */
1623 uint32_t dseg_2_address; /* Data segment 2 address. */
1624 uint32_t dseg_2_length; /* Data segment 2 length. */
1625 uint32_t dseg_3_address; /* Data segment 3 address. */
1626 uint32_t dseg_3_length; /* Data segment 3 length. */
1627 uint32_t dseg_4_address; /* Data segment 4 address. */
1628 uint32_t dseg_4_length; /* Data segment 4 length. */
1629 uint32_t dseg_5_address; /* Data segment 5 address. */
1630 uint32_t dseg_5_length; /* Data segment 5 length. */
1631 uint32_t dseg_6_address; /* Data segment 6 address. */
1632 uint32_t dseg_6_length; /* Data segment 6 length. */
1636 * ISP queue - 64-Bit addressing, continuation entry structure definition.
1638 #define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */
1640 uint8_t entry_type; /* Entry type. */
1641 uint8_t entry_count; /* Entry count. */
1642 uint8_t sys_define; /* System defined. */
1643 uint8_t entry_status; /* Entry Status. */
1644 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1645 uint32_t dseg_0_length; /* Data segment 0 length. */
1646 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1647 uint32_t dseg_1_length; /* Data segment 1 length. */
1648 uint32_t dseg_2_address [2]; /* Data segment 2 address. */
1649 uint32_t dseg_2_length; /* Data segment 2 length. */
1650 uint32_t dseg_3_address[2]; /* Data segment 3 address. */
1651 uint32_t dseg_3_length; /* Data segment 3 length. */
1652 uint32_t dseg_4_address[2]; /* Data segment 4 address. */
1653 uint32_t dseg_4_length; /* Data segment 4 length. */
1656 #define PO_MODE_DIF_INSERT 0
1657 #define PO_MODE_DIF_REMOVE 1
1658 #define PO_MODE_DIF_PASS 2
1659 #define PO_MODE_DIF_REPLACE 3
1660 #define PO_MODE_DIF_TCP_CKSUM 6
1661 #define PO_ENABLE_INCR_GUARD_SEED BIT_3
1662 #define PO_DISABLE_GUARD_CHECK BIT_4
1663 #define PO_DISABLE_INCR_REF_TAG BIT_5
1664 #define PO_DIS_HEADER_MODE BIT_7
1665 #define PO_ENABLE_DIF_BUNDLING BIT_8
1666 #define PO_DIS_FRAME_MODE BIT_9
1667 #define PO_DIS_VALD_APP_ESC BIT_10 /* Dis validation for escape tag/ffffh */
1668 #define PO_DIS_VALD_APP_REF_ESC BIT_11
1670 #define PO_DIS_APP_TAG_REPL BIT_12 /* disable REG Tag replacement */
1671 #define PO_DIS_REF_TAG_REPL BIT_13
1672 #define PO_DIS_APP_TAG_VALD BIT_14 /* disable REF Tag validation */
1673 #define PO_DIS_REF_TAG_VALD BIT_15
1676 * ISP queue - 64-Bit addressing, continuation crc entry structure definition.
1678 struct crc_context {
1679 uint32_t handle; /* System handle. */
1682 uint8_t ref_tag_mask[4]; /* Validation/Replacement Mask*/
1683 uint8_t app_tag_mask[2]; /* Validation/Replacement Mask*/
1684 __le16 guard_seed; /* Initial Guard Seed */
1685 __le16 prot_opts; /* Requested Data Protection Mode */
1686 __le16 blk_size; /* Data size in bytes */
1687 uint16_t runt_blk_guard; /* Guard value for runt block (tape
1689 __le32 byte_count; /* Total byte count/ total data
1693 uint32_t reserved_1;
1694 uint16_t reserved_2;
1695 uint16_t reserved_3;
1696 uint32_t reserved_4;
1697 uint32_t data_address[2];
1698 uint32_t data_length;
1699 uint32_t reserved_5[2];
1700 uint32_t reserved_6;
1703 __le32 dif_byte_count; /* Total DIF byte
1705 uint16_t reserved_1;
1706 __le16 dseg_count; /* Data segment count */
1707 uint32_t reserved_2;
1708 uint32_t data_address[2];
1709 uint32_t data_length;
1710 uint32_t dif_address[2];
1711 uint32_t dif_length; /* Data segment 0
1716 struct fcp_cmnd fcp_cmnd;
1717 dma_addr_t crc_ctx_dma;
1718 /* List of DMA context transfers */
1719 struct list_head dsd_list;
1721 /* This structure should not exceed 512 bytes */
1724 #define CRC_CONTEXT_LEN_FW (offsetof(struct crc_context, fcp_cmnd.lun))
1725 #define CRC_CONTEXT_FCPCMND_OFF (offsetof(struct crc_context, fcp_cmnd.lun))
1728 * ISP queue - status entry structure definition.
1730 #define STATUS_TYPE 0x03 /* Status entry. */
1732 uint8_t entry_type; /* Entry type. */
1733 uint8_t entry_count; /* Entry count. */
1734 uint8_t sys_define; /* System defined. */
1735 uint8_t entry_status; /* Entry Status. */
1736 uint32_t handle; /* System handle. */
1737 uint16_t scsi_status; /* SCSI status. */
1738 uint16_t comp_status; /* Completion status. */
1739 uint16_t state_flags; /* State flags. */
1740 uint16_t status_flags; /* Status flags. */
1741 uint16_t rsp_info_len; /* Response Info Length. */
1742 uint16_t req_sense_length; /* Request sense data length. */
1743 uint32_t residual_length; /* Residual transfer length. */
1744 uint8_t rsp_info[8]; /* FCP response information. */
1745 uint8_t req_sense_data[32]; /* Request sense data. */
1749 * Status entry entry status
1751 #define RF_RQ_DMA_ERROR BIT_6 /* Request Queue DMA error. */
1752 #define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */
1753 #define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */
1754 #define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */
1755 #define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */
1756 #define RF_BUSY BIT_1 /* Busy */
1757 #define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \
1758 RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY)
1759 #define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \
1763 * Status entry SCSI status bit definitions.
1765 #define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/
1766 #define SS_RESIDUAL_UNDER BIT_11
1767 #define SS_RESIDUAL_OVER BIT_10
1768 #define SS_SENSE_LEN_VALID BIT_9
1769 #define SS_RESPONSE_INFO_LEN_VALID BIT_8
1771 #define SS_RESERVE_CONFLICT (BIT_4 | BIT_3)
1772 #define SS_BUSY_CONDITION BIT_3
1773 #define SS_CONDITION_MET BIT_2
1774 #define SS_CHECK_CONDITION BIT_1
1777 * Status entry completion status
1779 #define CS_COMPLETE 0x0 /* No errors */
1780 #define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */
1781 #define CS_DMA 0x2 /* A DMA direction error. */
1782 #define CS_TRANSPORT 0x3 /* Transport error. */
1783 #define CS_RESET 0x4 /* SCSI bus reset occurred */
1784 #define CS_ABORTED 0x5 /* System aborted command. */
1785 #define CS_TIMEOUT 0x6 /* Timeout error. */
1786 #define CS_DATA_OVERRUN 0x7 /* Data overrun. */
1787 #define CS_DIF_ERROR 0xC /* DIF error detected */
1789 #define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */
1790 #define CS_QUEUE_FULL 0x1C /* Queue Full. */
1791 #define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */
1792 /* (selection timeout) */
1793 #define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */
1794 #define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */
1795 #define CS_PORT_BUSY 0x2B /* Port Busy */
1796 #define CS_COMPLETE_CHKCOND 0x30 /* Error? */
1797 #define CS_IOCB_ERROR 0x31 /* Generic error for IOCB request
1799 #define CS_BAD_PAYLOAD 0x80 /* Driver defined */
1800 #define CS_UNKNOWN 0x81 /* Driver defined */
1801 #define CS_RETRY 0x82 /* Driver defined */
1802 #define CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */
1804 #define CS_BIDIR_RD_OVERRUN 0x700
1805 #define CS_BIDIR_RD_WR_OVERRUN 0x707
1806 #define CS_BIDIR_RD_OVERRUN_WR_UNDERRUN 0x715
1807 #define CS_BIDIR_RD_UNDERRUN 0x1500
1808 #define CS_BIDIR_RD_UNDERRUN_WR_OVERRUN 0x1507
1809 #define CS_BIDIR_RD_WR_UNDERRUN 0x1515
1810 #define CS_BIDIR_DMA 0x200
1812 * Status entry status flags
1814 #define SF_ABTS_TERMINATED BIT_10
1815 #define SF_LOGOUT_SENT BIT_13
1818 * ISP queue - status continuation entry structure definition.
1820 #define STATUS_CONT_TYPE 0x10 /* Status continuation entry. */
1822 uint8_t entry_type; /* Entry type. */
1823 uint8_t entry_count; /* Entry count. */
1824 uint8_t sys_define; /* System defined. */
1825 uint8_t entry_status; /* Entry Status. */
1826 uint8_t data[60]; /* data */
1830 * ISP queue - RIO Type 1 status entry (32 bit I/O entry handles)
1831 * structure definition.
1833 #define STATUS_TYPE_21 0x21 /* Status entry. */
1835 uint8_t entry_type; /* Entry type. */
1836 uint8_t entry_count; /* Entry count. */
1837 uint8_t handle_count; /* Handle count. */
1838 uint8_t entry_status; /* Entry Status. */
1839 uint32_t handle[15]; /* System handles. */
1843 * ISP queue - RIO Type 2 status entry (16 bit I/O entry handles)
1844 * structure definition.
1846 #define STATUS_TYPE_22 0x22 /* Status entry. */
1848 uint8_t entry_type; /* Entry type. */
1849 uint8_t entry_count; /* Entry count. */
1850 uint8_t handle_count; /* Handle count. */
1851 uint8_t entry_status; /* Entry Status. */
1852 uint16_t handle[30]; /* System handles. */
1856 * ISP queue - marker entry structure definition.
1858 #define MARKER_TYPE 0x04 /* Marker entry. */
1860 uint8_t entry_type; /* Entry type. */
1861 uint8_t entry_count; /* Entry count. */
1862 uint8_t handle_count; /* Handle count. */
1863 uint8_t entry_status; /* Entry Status. */
1864 uint32_t sys_define_2; /* System defined. */
1865 target_id_t target; /* SCSI ID */
1866 uint8_t modifier; /* Modifier (7-0). */
1867 #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */
1868 #define MK_SYNC_ID 1 /* Synchronize ID */
1869 #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */
1870 #define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */
1871 /* clear port changed, */
1872 /* use sequence number. */
1874 uint16_t sequence_number; /* Sequence number of event */
1875 uint16_t lun; /* SCSI LUN */
1876 uint8_t reserved_2[48];
1880 * ISP queue - Management Server entry structure definition.
1882 #define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */
1884 uint8_t entry_type; /* Entry type. */
1885 uint8_t entry_count; /* Entry count. */
1886 uint8_t handle_count; /* Handle count. */
1887 uint8_t entry_status; /* Entry Status. */
1888 uint32_t handle1; /* System handle. */
1889 target_id_t loop_id;
1891 uint16_t control_flags; /* Control flags. */
1894 uint16_t cmd_dsd_count;
1895 uint16_t total_dsd_count;
1901 uint32_t rsp_bytecount;
1902 uint32_t req_bytecount;
1903 uint32_t dseg_req_address[2]; /* Data segment 0 address. */
1904 uint32_t dseg_req_length; /* Data segment 0 length. */
1905 uint32_t dseg_rsp_address[2]; /* Data segment 1 address. */
1906 uint32_t dseg_rsp_length; /* Data segment 1 length. */
1911 * ISP queue - Mailbox Command entry structure definition.
1913 #define MBX_IOCB_TYPE 0x39
1916 uint8_t entry_count;
1917 uint8_t sys_define1;
1918 /* Use sys_define1 for source type */
1919 #define SOURCE_SCSI 0x00
1920 #define SOURCE_IP 0x01
1921 #define SOURCE_VI 0x02
1922 #define SOURCE_SCTP 0x03
1923 #define SOURCE_MP 0x04
1924 #define SOURCE_MPIOCTL 0x05
1925 #define SOURCE_ASYNC_IOCB 0x07
1927 uint8_t entry_status;
1930 target_id_t loop_id;
1933 uint16_t state_flags;
1934 uint16_t status_flags;
1936 uint32_t sys_define2[2];
1946 uint32_t reserved_2[2];
1947 uint8_t node_name[WWN_SIZE];
1948 uint8_t port_name[WWN_SIZE];
1952 * ISP request and response queue entry sizes
1954 #define RESPONSE_ENTRY_SIZE (sizeof(response_t))
1955 #define REQUEST_ENTRY_SIZE (sizeof(request_t))
1959 * 24 bit port ID type definition.
1969 #elif defined(__LITTLE_ENDIAN)
1974 #error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined!"
1979 #define INVALID_PORT_ID 0xFFFFFF
1982 * Switch info gathering structure.
1986 uint8_t node_name[WWN_SIZE];
1987 uint8_t port_name[WWN_SIZE];
1988 uint8_t fabric_port_name[WWN_SIZE];
1994 #define FC4_TYPE_FCP_SCSI 0x08
1995 #define FC4_TYPE_OTHER 0x0
1996 #define FC4_TYPE_UNKNOWN 0xff
1999 * Fibre channel port type.
2011 * Fibre channel port structure.
2013 typedef struct fc_port {
2014 struct list_head list;
2015 struct scsi_qla_host *vha;
2017 uint8_t node_name[WWN_SIZE];
2018 uint8_t port_name[WWN_SIZE];
2021 uint16_t old_loop_id;
2024 uint16_t old_tgt_id;
2028 uint8_t fabric_port_name[WWN_SIZE];
2031 fc_port_type_t port_type;
2038 struct fc_rport *rport, *drport;
2039 u32 supported_classes;
2044 unsigned long last_queue_full;
2045 unsigned long last_ramp_up;
2049 unsigned long retry_delay_timestamp;
2050 struct qla_tgt_sess *tgt_session;
2056 * Fibre channel port/lun states.
2058 #define FCS_UNCONFIGURED 1
2059 #define FCS_DEVICE_DEAD 2
2060 #define FCS_DEVICE_LOST 3
2061 #define FCS_ONLINE 4
2063 static const char * const port_state_str[] = {
2074 #define FCF_FABRIC_DEVICE BIT_0
2075 #define FCF_LOGIN_NEEDED BIT_1
2076 #define FCF_FCP2_DEVICE BIT_2
2077 #define FCF_ASYNC_SENT BIT_3
2078 #define FCF_CONF_COMP_SUPPORTED BIT_4
2080 /* No loop ID flag. */
2081 #define FC_NO_LOOP_ID 0x1000
2086 * NOTE: All structures are big-endian in form.
2089 #define CT_REJECT_RESPONSE 0x8001
2090 #define CT_ACCEPT_RESPONSE 0x8002
2091 #define CT_REASON_INVALID_COMMAND_CODE 0x01
2092 #define CT_REASON_CANNOT_PERFORM 0x09
2093 #define CT_REASON_COMMAND_UNSUPPORTED 0x0b
2094 #define CT_EXPL_ALREADY_REGISTERED 0x10
2095 #define CT_EXPL_HBA_ATTR_NOT_REGISTERED 0x11
2096 #define CT_EXPL_MULTIPLE_HBA_ATTR 0x12
2097 #define CT_EXPL_INVALID_HBA_BLOCK_LENGTH 0x13
2098 #define CT_EXPL_MISSING_REQ_HBA_ATTR 0x14
2099 #define CT_EXPL_PORT_NOT_REGISTERED_ 0x15
2100 #define CT_EXPL_MISSING_HBA_ID_PORT_LIST 0x16
2101 #define CT_EXPL_HBA_NOT_REGISTERED 0x17
2102 #define CT_EXPL_PORT_ATTR_NOT_REGISTERED 0x20
2103 #define CT_EXPL_PORT_NOT_REGISTERED 0x21
2104 #define CT_EXPL_MULTIPLE_PORT_ATTR 0x22
2105 #define CT_EXPL_INVALID_PORT_BLOCK_LENGTH 0x23
2107 #define NS_N_PORT_TYPE 0x01
2108 #define NS_NL_PORT_TYPE 0x02
2109 #define NS_NX_PORT_TYPE 0x7F
2111 #define GA_NXT_CMD 0x100
2112 #define GA_NXT_REQ_SIZE (16 + 4)
2113 #define GA_NXT_RSP_SIZE (16 + 620)
2115 #define GID_PT_CMD 0x1A1
2116 #define GID_PT_REQ_SIZE (16 + 4)
2118 #define GPN_ID_CMD 0x112
2119 #define GPN_ID_REQ_SIZE (16 + 4)
2120 #define GPN_ID_RSP_SIZE (16 + 8)
2122 #define GNN_ID_CMD 0x113
2123 #define GNN_ID_REQ_SIZE (16 + 4)
2124 #define GNN_ID_RSP_SIZE (16 + 8)
2126 #define GFT_ID_CMD 0x117
2127 #define GFT_ID_REQ_SIZE (16 + 4)
2128 #define GFT_ID_RSP_SIZE (16 + 32)
2130 #define RFT_ID_CMD 0x217
2131 #define RFT_ID_REQ_SIZE (16 + 4 + 32)
2132 #define RFT_ID_RSP_SIZE 16
2134 #define RFF_ID_CMD 0x21F
2135 #define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1)
2136 #define RFF_ID_RSP_SIZE 16
2138 #define RNN_ID_CMD 0x213
2139 #define RNN_ID_REQ_SIZE (16 + 4 + 8)
2140 #define RNN_ID_RSP_SIZE 16
2142 #define RSNN_NN_CMD 0x239
2143 #define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255)
2144 #define RSNN_NN_RSP_SIZE 16
2146 #define GFPN_ID_CMD 0x11C
2147 #define GFPN_ID_REQ_SIZE (16 + 4)
2148 #define GFPN_ID_RSP_SIZE (16 + 8)
2150 #define GPSC_CMD 0x127
2151 #define GPSC_REQ_SIZE (16 + 8)
2152 #define GPSC_RSP_SIZE (16 + 2 + 2)
2154 #define GFF_ID_CMD 0x011F
2155 #define GFF_ID_REQ_SIZE (16 + 4)
2156 #define GFF_ID_RSP_SIZE (16 + 128)
2159 * HBA attribute types.
2161 #define FDMI_HBA_ATTR_COUNT 9
2162 #define FDMIV2_HBA_ATTR_COUNT 17
2163 #define FDMI_HBA_NODE_NAME 0x1
2164 #define FDMI_HBA_MANUFACTURER 0x2
2165 #define FDMI_HBA_SERIAL_NUMBER 0x3
2166 #define FDMI_HBA_MODEL 0x4
2167 #define FDMI_HBA_MODEL_DESCRIPTION 0x5
2168 #define FDMI_HBA_HARDWARE_VERSION 0x6
2169 #define FDMI_HBA_DRIVER_VERSION 0x7
2170 #define FDMI_HBA_OPTION_ROM_VERSION 0x8
2171 #define FDMI_HBA_FIRMWARE_VERSION 0x9
2172 #define FDMI_HBA_OS_NAME_AND_VERSION 0xa
2173 #define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb
2174 #define FDMI_HBA_NODE_SYMBOLIC_NAME 0xc
2175 #define FDMI_HBA_VENDOR_ID 0xd
2176 #define FDMI_HBA_NUM_PORTS 0xe
2177 #define FDMI_HBA_FABRIC_NAME 0xf
2178 #define FDMI_HBA_BOOT_BIOS_NAME 0x10
2179 #define FDMI_HBA_TYPE_VENDOR_IDENTIFIER 0xe0
2181 struct ct_fdmi_hba_attr {
2185 uint8_t node_name[WWN_SIZE];
2186 uint8_t manufacturer[64];
2187 uint8_t serial_num[32];
2188 uint8_t model[16+1];
2189 uint8_t model_desc[80];
2190 uint8_t hw_version[32];
2191 uint8_t driver_version[32];
2192 uint8_t orom_version[16];
2193 uint8_t fw_version[32];
2194 uint8_t os_version[128];
2195 uint32_t max_ct_len;
2199 struct ct_fdmi_hba_attributes {
2201 struct ct_fdmi_hba_attr entry[FDMI_HBA_ATTR_COUNT];
2204 struct ct_fdmiv2_hba_attr {
2208 uint8_t node_name[WWN_SIZE];
2209 uint8_t manufacturer[64];
2210 uint8_t serial_num[32];
2211 uint8_t model[16+1];
2212 uint8_t model_desc[80];
2213 uint8_t hw_version[16];
2214 uint8_t driver_version[32];
2215 uint8_t orom_version[16];
2216 uint8_t fw_version[32];
2217 uint8_t os_version[128];
2218 uint32_t max_ct_len;
2219 uint8_t sym_name[256];
2222 uint8_t fabric_name[WWN_SIZE];
2223 uint8_t bios_name[32];
2224 uint8_t vendor_indentifer[8];
2228 struct ct_fdmiv2_hba_attributes {
2230 struct ct_fdmiv2_hba_attr entry[FDMIV2_HBA_ATTR_COUNT];
2234 * Port attribute types.
2236 #define FDMI_PORT_ATTR_COUNT 6
2237 #define FDMIV2_PORT_ATTR_COUNT 16
2238 #define FDMI_PORT_FC4_TYPES 0x1
2239 #define FDMI_PORT_SUPPORT_SPEED 0x2
2240 #define FDMI_PORT_CURRENT_SPEED 0x3
2241 #define FDMI_PORT_MAX_FRAME_SIZE 0x4
2242 #define FDMI_PORT_OS_DEVICE_NAME 0x5
2243 #define FDMI_PORT_HOST_NAME 0x6
2244 #define FDMI_PORT_NODE_NAME 0x7
2245 #define FDMI_PORT_NAME 0x8
2246 #define FDMI_PORT_SYM_NAME 0x9
2247 #define FDMI_PORT_TYPE 0xa
2248 #define FDMI_PORT_SUPP_COS 0xb
2249 #define FDMI_PORT_FABRIC_NAME 0xc
2250 #define FDMI_PORT_FC4_TYPE 0xd
2251 #define FDMI_PORT_STATE 0x101
2252 #define FDMI_PORT_COUNT 0x102
2253 #define FDMI_PORT_ID 0x103
2255 #define FDMI_PORT_SPEED_1GB 0x1
2256 #define FDMI_PORT_SPEED_2GB 0x2
2257 #define FDMI_PORT_SPEED_10GB 0x4
2258 #define FDMI_PORT_SPEED_4GB 0x8
2259 #define FDMI_PORT_SPEED_8GB 0x10
2260 #define FDMI_PORT_SPEED_16GB 0x20
2261 #define FDMI_PORT_SPEED_32GB 0x40
2262 #define FDMI_PORT_SPEED_UNKNOWN 0x8000
2264 #define FC_CLASS_2 0x04
2265 #define FC_CLASS_3 0x08
2266 #define FC_CLASS_2_3 0x0C
2268 struct ct_fdmiv2_port_attr {
2272 uint8_t fc4_types[32];
2275 uint32_t max_frame_size;
2276 uint8_t os_dev_name[32];
2277 uint8_t host_name[256];
2278 uint8_t node_name[WWN_SIZE];
2279 uint8_t port_name[WWN_SIZE];
2280 uint8_t port_sym_name[128];
2282 uint32_t port_supported_cos;
2283 uint8_t fabric_name[WWN_SIZE];
2284 uint8_t port_fc4_type[32];
2285 uint32_t port_state;
2292 * Port Attribute Block.
2294 struct ct_fdmiv2_port_attributes {
2296 struct ct_fdmiv2_port_attr entry[FDMIV2_PORT_ATTR_COUNT];
2299 struct ct_fdmi_port_attr {
2303 uint8_t fc4_types[32];
2306 uint32_t max_frame_size;
2307 uint8_t os_dev_name[32];
2308 uint8_t host_name[256];
2312 struct ct_fdmi_port_attributes {
2314 struct ct_fdmi_port_attr entry[FDMI_PORT_ATTR_COUNT];
2317 /* FDMI definitions. */
2318 #define GRHL_CMD 0x100
2319 #define GHAT_CMD 0x101
2320 #define GRPL_CMD 0x102
2321 #define GPAT_CMD 0x110
2323 #define RHBA_CMD 0x200
2324 #define RHBA_RSP_SIZE 16
2326 #define RHAT_CMD 0x201
2327 #define RPRT_CMD 0x210
2329 #define RPA_CMD 0x211
2330 #define RPA_RSP_SIZE 16
2332 #define DHBA_CMD 0x300
2333 #define DHBA_REQ_SIZE (16 + 8)
2334 #define DHBA_RSP_SIZE 16
2336 #define DHAT_CMD 0x301
2337 #define DPRT_CMD 0x310
2338 #define DPA_CMD 0x311
2340 /* CT command header -- request/response common fields */
2350 /* CT command request */
2352 struct ct_cmd_hdr header;
2354 uint16_t max_rsp_size;
2355 uint8_t fragment_id;
2356 uint8_t reserved[3];
2359 /* GA_NXT, GPN_ID, GNN_ID, GFT_ID, GFPN_ID */
2375 uint8_t fc4_types[32];
2382 uint8_t fc4_feature;
2389 uint8_t node_name[8];
2393 uint8_t node_name[8];
2395 uint8_t sym_node_name[255];
2399 uint8_t hba_indentifier[8];
2403 uint8_t hba_identifier[8];
2404 uint32_t entry_count;
2405 uint8_t port_name[8];
2406 struct ct_fdmi_hba_attributes attrs;
2410 uint8_t hba_identifier[8];
2411 uint32_t entry_count;
2412 uint8_t port_name[8];
2413 struct ct_fdmiv2_hba_attributes attrs;
2417 uint8_t hba_identifier[8];
2418 struct ct_fdmi_hba_attributes attrs;
2422 uint8_t port_name[8];
2423 struct ct_fdmi_port_attributes attrs;
2427 uint8_t port_name[8];
2428 struct ct_fdmiv2_port_attributes attrs;
2432 uint8_t port_name[8];
2436 uint8_t port_name[8];
2440 uint8_t port_name[8];
2444 uint8_t port_name[8];
2448 uint8_t port_name[8];
2453 uint8_t port_name[3];
2458 /* CT command response header */
2460 struct ct_cmd_hdr header;
2463 uint8_t fragment_id;
2464 uint8_t reason_code;
2465 uint8_t explanation_code;
2466 uint8_t vendor_unique;
2469 struct ct_sns_gid_pt_data {
2470 uint8_t control_byte;
2475 struct ct_rsp_hdr header;
2481 uint8_t port_name[8];
2482 uint8_t sym_port_name_len;
2483 uint8_t sym_port_name[255];
2484 uint8_t node_name[8];
2485 uint8_t sym_node_name_len;
2486 uint8_t sym_node_name[255];
2487 uint8_t init_proc_assoc[8];
2488 uint8_t node_ip_addr[16];
2489 uint8_t class_of_service[4];
2490 uint8_t fc4_types[32];
2491 uint8_t ip_address[16];
2492 uint8_t fabric_port_name[8];
2494 uint8_t hard_address[3];
2498 /* Assume the largest number of targets for the union */
2499 struct ct_sns_gid_pt_data
2500 entries[MAX_FIBRE_DEVICES_MAX];
2504 uint8_t port_name[8];
2508 uint8_t node_name[8];
2512 uint8_t fc4_types[32];
2516 uint32_t entry_count;
2517 uint8_t port_name[8];
2518 struct ct_fdmi_hba_attributes attrs;
2522 uint8_t port_name[8];
2530 #define GFF_FCP_SCSI_OFFSET 7
2532 uint8_t fc4_features[128];
2539 struct ct_sns_req req;
2540 struct ct_sns_rsp rsp;
2545 * SNS command structures -- for 2200 compatibility.
2547 #define RFT_ID_SNS_SCMD_LEN 22
2548 #define RFT_ID_SNS_CMD_SIZE 60
2549 #define RFT_ID_SNS_DATA_SIZE 16
2551 #define RNN_ID_SNS_SCMD_LEN 10
2552 #define RNN_ID_SNS_CMD_SIZE 36
2553 #define RNN_ID_SNS_DATA_SIZE 16
2555 #define GA_NXT_SNS_SCMD_LEN 6
2556 #define GA_NXT_SNS_CMD_SIZE 28
2557 #define GA_NXT_SNS_DATA_SIZE (620 + 16)
2559 #define GID_PT_SNS_SCMD_LEN 6
2560 #define GID_PT_SNS_CMD_SIZE 28
2562 * Assume MAX_FIBRE_DEVICES_2100 as these defines are only used with older
2565 #define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES_2100 * 4 + 16)
2567 #define GPN_ID_SNS_SCMD_LEN 6
2568 #define GPN_ID_SNS_CMD_SIZE 28
2569 #define GPN_ID_SNS_DATA_SIZE (8 + 16)
2571 #define GNN_ID_SNS_SCMD_LEN 6
2572 #define GNN_ID_SNS_CMD_SIZE 28
2573 #define GNN_ID_SNS_DATA_SIZE (8 + 16)
2575 struct sns_cmd_pkt {
2578 uint16_t buffer_length;
2579 uint16_t reserved_1;
2580 uint32_t buffer_address[2];
2581 uint16_t subcommand_length;
2582 uint16_t reserved_2;
2583 uint16_t subcommand;
2585 uint32_t reserved_3;
2589 uint8_t rft_data[RFT_ID_SNS_DATA_SIZE];
2590 uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE];
2591 uint8_t gan_data[GA_NXT_SNS_DATA_SIZE];
2592 uint8_t gid_data[GID_PT_SNS_DATA_SIZE];
2593 uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE];
2594 uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE];
2601 const struct firmware *fw;
2604 /* Return data from MBC_GET_ID_LIST call. */
2605 struct gid_list_info {
2609 uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */
2610 uint16_t loop_id; /* ISP23XX -- 6 bytes. */
2611 uint16_t reserved_1; /* ISP24XX -- 8 bytes. */
2615 typedef struct vport_info {
2616 uint8_t port_name[WWN_SIZE];
2617 uint8_t node_name[WWN_SIZE];
2620 unsigned long host_no;
2625 typedef struct vport_params {
2626 uint8_t port_name[WWN_SIZE];
2627 uint8_t node_name[WWN_SIZE];
2629 #define VP_OPTS_RETRY_ENABLE BIT_0
2630 #define VP_OPTS_VP_DISABLE BIT_1
2633 /* NPIV - return codes of VP create and modify */
2634 #define VP_RET_CODE_OK 0
2635 #define VP_RET_CODE_FATAL 1
2636 #define VP_RET_CODE_WRONG_ID 2
2637 #define VP_RET_CODE_WWPN 3
2638 #define VP_RET_CODE_RESOURCES 4
2639 #define VP_RET_CODE_NO_MEM 5
2640 #define VP_RET_CODE_NOT_FOUND 6
2647 struct isp_operations {
2649 int (*pci_config) (struct scsi_qla_host *);
2650 void (*reset_chip) (struct scsi_qla_host *);
2651 int (*chip_diag) (struct scsi_qla_host *);
2652 void (*config_rings) (struct scsi_qla_host *);
2653 void (*reset_adapter) (struct scsi_qla_host *);
2654 int (*nvram_config) (struct scsi_qla_host *);
2655 void (*update_fw_options) (struct scsi_qla_host *);
2656 int (*load_risc) (struct scsi_qla_host *, uint32_t *);
2658 char * (*pci_info_str) (struct scsi_qla_host *, char *);
2659 char * (*fw_version_str)(struct scsi_qla_host *, char *, size_t);
2661 irq_handler_t intr_handler;
2662 void (*enable_intrs) (struct qla_hw_data *);
2663 void (*disable_intrs) (struct qla_hw_data *);
2665 int (*abort_command) (srb_t *);
2666 int (*target_reset) (struct fc_port *, uint64_t, int);
2667 int (*lun_reset) (struct fc_port *, uint64_t, int);
2668 int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t,
2669 uint8_t, uint8_t, uint16_t *, uint8_t);
2670 int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t,
2673 uint16_t (*calc_req_entries) (uint16_t);
2674 void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t);
2675 void * (*prep_ms_iocb) (struct scsi_qla_host *, uint32_t, uint32_t);
2676 void * (*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t,
2679 uint8_t * (*read_nvram) (struct scsi_qla_host *, uint8_t *,
2680 uint32_t, uint32_t);
2681 int (*write_nvram) (struct scsi_qla_host *, uint8_t *, uint32_t,
2684 void (*fw_dump) (struct scsi_qla_host *, int);
2686 int (*beacon_on) (struct scsi_qla_host *);
2687 int (*beacon_off) (struct scsi_qla_host *);
2688 void (*beacon_blink) (struct scsi_qla_host *);
2690 uint8_t * (*read_optrom) (struct scsi_qla_host *, uint8_t *,
2691 uint32_t, uint32_t);
2692 int (*write_optrom) (struct scsi_qla_host *, uint8_t *, uint32_t,
2695 int (*get_flash_version) (struct scsi_qla_host *, void *);
2696 int (*start_scsi) (srb_t *);
2697 int (*abort_isp) (struct scsi_qla_host *);
2698 int (*iospace_config)(struct qla_hw_data*);
2699 int (*initialize_adapter)(struct scsi_qla_host *);
2702 /* MSI-X Support *************************************************************/
2704 #define QLA_MSIX_CHIP_REV_24XX 3
2705 #define QLA_MSIX_FW_MODE(m) (((m) & (BIT_7|BIT_8|BIT_9)) >> 7)
2706 #define QLA_MSIX_FW_MODE_1(m) (QLA_MSIX_FW_MODE(m) == 1)
2708 #define QLA_MSIX_DEFAULT 0x00
2709 #define QLA_MSIX_RSP_Q 0x01
2711 #define QLA_MIDX_DEFAULT 0
2712 #define QLA_MIDX_RSP_Q 1
2713 #define QLA_PCI_MSIX_CONTROL 0xa2
2714 #define QLA_83XX_PCI_MSIX_CONTROL 0x92
2716 struct scsi_qla_host;
2719 #define QLA83XX_RSPQ_MSIX_ENTRY_NUMBER 1 /* refer to qla83xx_msix_entries */
2721 struct qla_msix_entry {
2725 struct rsp_que *rsp;
2726 struct irq_affinity_notify irq_notify;
2730 #define WATCH_INTERVAL 1 /* number of seconds */
2733 enum qla_work_type {
2736 QLA_EVT_ASYNC_LOGIN,
2737 QLA_EVT_ASYNC_LOGIN_DONE,
2738 QLA_EVT_ASYNC_LOGOUT,
2739 QLA_EVT_ASYNC_LOGOUT_DONE,
2740 QLA_EVT_ASYNC_ADISC,
2741 QLA_EVT_ASYNC_ADISC_DONE,
2747 struct qla_work_evt {
2748 struct list_head list;
2749 enum qla_work_type type;
2751 #define QLA_EVT_FLAG_FREE 0x1
2755 enum fc_host_event_code code;
2759 #define QLA_IDC_ACK_REGS 7
2760 uint16_t mb[QLA_IDC_ACK_REGS];
2763 struct fc_port *fcport;
2764 #define QLA_LOGIO_LOGIN_RETRIED BIT_0
2769 #define QLA_UEVENT_CODE_FW_DUMP 0
2782 struct qla_chip_state_84xx {
2783 struct list_head list;
2787 spinlock_t access_lock;
2788 struct mutex fw_update_mutex;
2790 uint32_t op_fw_version;
2791 uint32_t op_fw_size;
2792 uint32_t op_fw_seq_size;
2793 uint32_t diag_fw_version;
2794 uint32_t gold_fw_version;
2797 struct qla_statistics {
2798 uint32_t total_isp_aborts;
2799 uint64_t input_bytes;
2800 uint64_t output_bytes;
2801 uint64_t input_requests;
2802 uint64_t output_requests;
2803 uint32_t control_requests;
2805 uint64_t jiffies_at_last_reset;
2806 uint32_t stat_max_pend_cmds;
2807 uint32_t stat_max_qfull_cmds_alloc;
2808 uint32_t stat_max_qfull_cmds_dropped;
2811 struct bidi_statistics {
2812 unsigned long long io_count;
2813 unsigned long long transfer_bytes;
2816 /* Multi queue support */
2817 #define MBC_INITIALIZE_MULTIQ 0x1f
2818 #define QLA_QUE_PAGE 0X1000
2819 #define QLA_MQ_SIZE 32
2820 #define QLA_MAX_QUEUES 256
2821 #define ISP_QUE_REG(ha, id) \
2822 ((ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) ? \
2823 ((void __iomem *)ha->mqiobase + (QLA_QUE_PAGE * id)) :\
2824 ((void __iomem *)ha->iobase))
2825 #define QLA_REQ_QUE_ID(tag) \
2826 ((tag < QLA_MAX_QUEUES && tag > 0) ? tag : 0)
2827 #define QLA_DEFAULT_QUE_QOS 5
2828 #define QLA_PRECONFIG_VPORTS 32
2829 #define QLA_MAX_VPORTS_QLA24XX 128
2830 #define QLA_MAX_VPORTS_QLA25XX 256
2831 /* Response queue data structure */
2835 response_t *ring_ptr;
2836 uint32_t __iomem *rsp_q_in; /* FWI2-capable only. */
2837 uint32_t __iomem *rsp_q_out;
2838 uint16_t ring_index;
2840 uint16_t *in_ptr; /* queue shadow in index */
2846 struct qla_hw_data *hw;
2847 struct qla_msix_entry *msix;
2848 struct req_que *req;
2849 srb_t *status_srb; /* status continuation entry */
2850 struct work_struct q_work;
2852 dma_addr_t dma_fx00;
2853 response_t *ring_fx00;
2854 uint16_t length_fx00;
2855 uint8_t rsp_pkt[REQUEST_ENTRY_SIZE];
2858 /* Request queue data structure */
2862 request_t *ring_ptr;
2863 uint32_t __iomem *req_q_in; /* FWI2-capable only. */
2864 uint32_t __iomem *req_q_out;
2865 uint16_t ring_index;
2867 uint16_t *out_ptr; /* queue shadow out index */
2875 struct rsp_que *rsp;
2876 srb_t **outstanding_cmds;
2877 uint32_t current_outstanding_cmd;
2878 uint16_t num_outstanding_cmds;
2881 dma_addr_t dma_fx00;
2882 request_t *ring_fx00;
2883 uint16_t length_fx00;
2884 uint8_t req_pkt[REQUEST_ENTRY_SIZE];
2887 /* Place holder for FW buffer parameters */
2894 struct scsi_qlt_host {
2895 void *target_lport_ptr;
2896 struct mutex tgt_mutex;
2897 struct mutex tgt_host_action_mutex;
2898 struct qla_tgt *qla_tgt;
2901 struct qlt_hw_data {
2902 /* Protected by hw lock */
2903 uint32_t enable_class_2:1;
2904 uint32_t enable_explicit_conf:1;
2905 uint32_t ini_mode_force_reverse:1;
2906 uint32_t node_name_set:1;
2908 dma_addr_t atio_dma; /* Physical address. */
2909 struct atio *atio_ring; /* Base virtual address */
2910 struct atio *atio_ring_ptr; /* Current address. */
2911 uint16_t atio_ring_index; /* Current index. */
2912 uint16_t atio_q_length;
2913 uint32_t __iomem *atio_q_in;
2914 uint32_t __iomem *atio_q_out;
2916 struct qla_tgt_func_tmpl *tgt_ops;
2917 struct qla_tgt_cmd *cmds[DEFAULT_OUTSTANDING_COMMANDS];
2918 uint16_t current_handle;
2920 struct qla_tgt_vp_map *tgt_vp_map;
2923 uint16_t saved_exchange_count;
2924 uint32_t saved_firmware_options_1;
2925 uint32_t saved_firmware_options_2;
2926 uint32_t saved_firmware_options_3;
2927 uint8_t saved_firmware_options[2];
2928 uint8_t saved_add_firmware_options[2];
2930 uint8_t tgt_node_name[WWN_SIZE];
2932 struct list_head q_full_list;
2933 uint32_t num_pend_cmds;
2934 uint32_t num_qfull_cmds_alloc;
2935 uint32_t num_qfull_cmds_dropped;
2936 spinlock_t q_full_lock;
2937 uint32_t leak_exchg_thresh_hold;
2938 spinlock_t sess_lock;
2939 int rspq_vector_cpuid;
2940 spinlock_t atio_lock ____cacheline_aligned;
2943 #define MAX_QFULL_CMDS_ALLOC 8192
2944 #define Q_FULL_THRESH_HOLD_PERCENT 90
2945 #define Q_FULL_THRESH_HOLD(ha) \
2946 ((ha->cur_fw_xcb_count/100) * Q_FULL_THRESH_HOLD_PERCENT)
2948 #define LEAK_EXCHG_THRESH_HOLD_PERCENT 75 /* 75 percent */
2951 * Qlogic host adapter specific data structure.
2953 struct qla_hw_data {
2954 struct pci_dev *pdev;
2956 #define SRB_MIN_REQ 128
2957 mempool_t *srb_mempool;
2960 uint32_t mbox_int :1;
2961 uint32_t mbox_busy :1;
2962 uint32_t disable_risc_code_load :1;
2963 uint32_t enable_64bit_addressing :1;
2964 uint32_t enable_lip_reset :1;
2965 uint32_t enable_target_reset :1;
2966 uint32_t enable_lip_full_login :1;
2967 uint32_t enable_led_scheme :1;
2969 uint32_t msi_enabled :1;
2970 uint32_t msix_enabled :1;
2971 uint32_t disable_serdes :1;
2972 uint32_t gpsc_supported :1;
2973 uint32_t npiv_supported :1;
2974 uint32_t pci_channel_io_perm_failure :1;
2975 uint32_t fce_enabled :1;
2976 uint32_t fac_supported :1;
2978 uint32_t chip_reset_done :1;
2979 uint32_t running_gold_fw :1;
2980 uint32_t eeh_busy :1;
2981 uint32_t cpu_affinity_enabled :1;
2982 uint32_t disable_msix_handshake :1;
2983 uint32_t fcp_prio_enabled :1;
2984 uint32_t isp82xx_fw_hung:1;
2985 uint32_t nic_core_hung:1;
2987 uint32_t quiesce_owner:1;
2988 uint32_t nic_core_reset_hdlr_active:1;
2989 uint32_t nic_core_reset_owner:1;
2990 uint32_t isp82xx_no_md_cap:1;
2991 uint32_t host_shutting_down:1;
2992 uint32_t idc_compl_status:1;
2993 uint32_t mr_reset_hdlr_active:1;
2994 uint32_t mr_intr_valid:1;
2996 uint32_t fawwpn_enabled:1;
2997 uint32_t exlogins_enabled:1;
2998 uint32_t exchoffld_enabled:1;
3002 /* This spinlock is used to protect "io transactions", you must
3003 * acquire it before doing any IO to the card, eg with RD_REG*() and
3004 * WRT_REG*() for the duration of your entire commandtransaction.
3006 * This spinlock is of lower priority than the io request lock.
3009 spinlock_t hardware_lock ____cacheline_aligned;
3012 device_reg_t *iobase; /* Base I/O address */
3013 resource_size_t pio_address;
3015 #define MIN_IOBASE_LEN 0x100
3016 dma_addr_t bar0_hdl;
3018 void __iomem *cregbase;
3019 dma_addr_t bar2_hdl;
3020 #define BAR0_LEN_FX00 (1024 * 1024)
3021 #define BAR2_LEN_FX00 (128 * 1024)
3023 uint32_t rqstq_intr_code;
3024 uint32_t mbx_intr_code;
3025 uint32_t req_que_len;
3026 uint32_t rsp_que_len;
3027 uint32_t req_que_off;
3028 uint32_t rsp_que_off;
3030 /* Multi queue data structs */
3031 device_reg_t *mqiobase;
3032 device_reg_t *msixbase;
3033 uint16_t msix_count;
3035 struct req_que **req_q_map;
3036 struct rsp_que **rsp_q_map;
3037 unsigned long req_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
3038 unsigned long rsp_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
3039 uint8_t max_req_queues;
3040 uint8_t max_rsp_queues;
3041 struct qla_npiv_entry *npiv_info;
3042 uint16_t nvram_npiv_size;
3044 uint16_t switch_cap;
3045 #define FLOGI_SEQ_DEL BIT_8
3046 #define FLOGI_MID_SUPPORT BIT_10
3047 #define FLOGI_VSAN_SUPPORT BIT_12
3048 #define FLOGI_SP_SUPPORT BIT_13
3050 uint8_t port_no; /* Physical port of adapter */
3052 /* Timeout timers. */
3053 uint8_t loop_down_abort_time; /* port down timer */
3054 atomic_t loop_down_timer; /* loop down timer */
3055 uint8_t link_down_timeout; /* link down timeout */
3056 uint16_t max_loop_id;
3057 uint16_t max_fibre_devices; /* Maximum number of targets */
3060 uint16_t min_external_loopid; /* First external loop Id */
3062 #define PORT_SPEED_UNKNOWN 0xFFFF
3063 #define PORT_SPEED_1GB 0x00
3064 #define PORT_SPEED_2GB 0x01
3065 #define PORT_SPEED_4GB 0x03
3066 #define PORT_SPEED_8GB 0x04
3067 #define PORT_SPEED_16GB 0x05
3068 #define PORT_SPEED_32GB 0x06
3069 #define PORT_SPEED_10GB 0x13
3070 uint16_t link_data_rate; /* F/W operating speed */
3072 uint8_t current_topology;
3073 uint8_t prev_topology;
3074 #define ISP_CFG_NL 1
3076 #define ISP_CFG_FL 4
3079 uint8_t operating_mode; /* F/W operating mode */
3084 uint8_t interrupts_on;
3085 uint32_t isp_abort_cnt;
3087 #define PCI_DEVICE_ID_QLOGIC_ISP2532 0x2532
3088 #define PCI_DEVICE_ID_QLOGIC_ISP8432 0x8432
3089 #define PCI_DEVICE_ID_QLOGIC_ISP8001 0x8001
3090 #define PCI_DEVICE_ID_QLOGIC_ISP8031 0x8031
3091 #define PCI_DEVICE_ID_QLOGIC_ISP2031 0x2031
3092 #define PCI_DEVICE_ID_QLOGIC_ISP2071 0x2071
3093 #define PCI_DEVICE_ID_QLOGIC_ISP2271 0x2271
3094 #define PCI_DEVICE_ID_QLOGIC_ISP2261 0x2261
3096 uint32_t device_type;
3097 #define DT_ISP2100 BIT_0
3098 #define DT_ISP2200 BIT_1
3099 #define DT_ISP2300 BIT_2
3100 #define DT_ISP2312 BIT_3
3101 #define DT_ISP2322 BIT_4
3102 #define DT_ISP6312 BIT_5
3103 #define DT_ISP6322 BIT_6
3104 #define DT_ISP2422 BIT_7
3105 #define DT_ISP2432 BIT_8
3106 #define DT_ISP5422 BIT_9
3107 #define DT_ISP5432 BIT_10
3108 #define DT_ISP2532 BIT_11
3109 #define DT_ISP8432 BIT_12
3110 #define DT_ISP8001 BIT_13
3111 #define DT_ISP8021 BIT_14
3112 #define DT_ISP2031 BIT_15
3113 #define DT_ISP8031 BIT_16
3114 #define DT_ISPFX00 BIT_17
3115 #define DT_ISP8044 BIT_18
3116 #define DT_ISP2071 BIT_19
3117 #define DT_ISP2271 BIT_20
3118 #define DT_ISP2261 BIT_21
3119 #define DT_ISP_LAST (DT_ISP2261 << 1)
3121 #define DT_T10_PI BIT_25
3122 #define DT_IIDMA BIT_26
3123 #define DT_FWI2 BIT_27
3124 #define DT_ZIO_SUPPORTED BIT_28
3125 #define DT_OEM_001 BIT_29
3126 #define DT_ISP2200A BIT_30
3127 #define DT_EXTENDED_IDS BIT_31
3128 #define DT_MASK(ha) ((ha)->device_type & (DT_ISP_LAST - 1))
3129 #define IS_QLA2100(ha) (DT_MASK(ha) & DT_ISP2100)
3130 #define IS_QLA2200(ha) (DT_MASK(ha) & DT_ISP2200)
3131 #define IS_QLA2300(ha) (DT_MASK(ha) & DT_ISP2300)
3132 #define IS_QLA2312(ha) (DT_MASK(ha) & DT_ISP2312)
3133 #define IS_QLA2322(ha) (DT_MASK(ha) & DT_ISP2322)
3134 #define IS_QLA6312(ha) (DT_MASK(ha) & DT_ISP6312)
3135 #define IS_QLA6322(ha) (DT_MASK(ha) & DT_ISP6322)
3136 #define IS_QLA2422(ha) (DT_MASK(ha) & DT_ISP2422)
3137 #define IS_QLA2432(ha) (DT_MASK(ha) & DT_ISP2432)
3138 #define IS_QLA5422(ha) (DT_MASK(ha) & DT_ISP5422)
3139 #define IS_QLA5432(ha) (DT_MASK(ha) & DT_ISP5432)
3140 #define IS_QLA2532(ha) (DT_MASK(ha) & DT_ISP2532)
3141 #define IS_QLA8432(ha) (DT_MASK(ha) & DT_ISP8432)
3142 #define IS_QLA8001(ha) (DT_MASK(ha) & DT_ISP8001)
3143 #define IS_QLA81XX(ha) (IS_QLA8001(ha))
3144 #define IS_QLA82XX(ha) (DT_MASK(ha) & DT_ISP8021)
3145 #define IS_QLA8044(ha) (DT_MASK(ha) & DT_ISP8044)
3146 #define IS_QLA2031(ha) (DT_MASK(ha) & DT_ISP2031)
3147 #define IS_QLA8031(ha) (DT_MASK(ha) & DT_ISP8031)
3148 #define IS_QLAFX00(ha) (DT_MASK(ha) & DT_ISPFX00)
3149 #define IS_QLA2071(ha) (DT_MASK(ha) & DT_ISP2071)
3150 #define IS_QLA2271(ha) (DT_MASK(ha) & DT_ISP2271)
3151 #define IS_QLA2261(ha) (DT_MASK(ha) & DT_ISP2261)
3153 #define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \
3154 IS_QLA6312(ha) || IS_QLA6322(ha))
3155 #define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha))
3156 #define IS_QLA54XX(ha) (IS_QLA5422(ha) || IS_QLA5432(ha))
3157 #define IS_QLA25XX(ha) (IS_QLA2532(ha))
3158 #define IS_QLA83XX(ha) (IS_QLA2031(ha) || IS_QLA8031(ha))
3159 #define IS_QLA84XX(ha) (IS_QLA8432(ha))
3160 #define IS_QLA27XX(ha) (IS_QLA2071(ha) || IS_QLA2271(ha) || IS_QLA2261(ha))
3161 #define IS_QLA24XX_TYPE(ha) (IS_QLA24XX(ha) || IS_QLA54XX(ha) || \
3163 #define IS_CNA_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA82XX(ha) || \
3164 IS_QLA8031(ha) || IS_QLA8044(ha))
3165 #define IS_P3P_TYPE(ha) (IS_QLA82XX(ha) || IS_QLA8044(ha))
3166 #define IS_QLA2XXX_MIDTYPE(ha) (IS_QLA24XX(ha) || IS_QLA84XX(ha) || \
3167 IS_QLA25XX(ha) || IS_QLA81XX(ha) || \
3168 IS_QLA82XX(ha) || IS_QLA83XX(ha) || \
3169 IS_QLA8044(ha) || IS_QLA27XX(ha))
3170 #define IS_MSIX_NACK_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
3172 #define IS_NOPOLLING_TYPE(ha) (IS_QLA81XX(ha) && (ha)->flags.msix_enabled)
3173 #define IS_FAC_REQUIRED(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
3175 #define IS_NOCACHE_VPD_TYPE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
3177 #define IS_ALOGIO_CAPABLE(ha) (IS_QLA23XX(ha) || IS_FWI2_CAPABLE(ha))
3179 #define IS_T10_PI_CAPABLE(ha) ((ha)->device_type & DT_T10_PI)
3180 #define IS_IIDMA_CAPABLE(ha) ((ha)->device_type & DT_IIDMA)
3181 #define IS_FWI2_CAPABLE(ha) ((ha)->device_type & DT_FWI2)
3182 #define IS_ZIO_SUPPORTED(ha) ((ha)->device_type & DT_ZIO_SUPPORTED)
3183 #define IS_OEM_001(ha) ((ha)->device_type & DT_OEM_001)
3184 #define HAS_EXTENDED_IDS(ha) ((ha)->device_type & DT_EXTENDED_IDS)
3185 #define IS_CT6_SUPPORTED(ha) ((ha)->device_type & DT_CT6_SUPPORTED)
3186 #define IS_MQUE_CAPABLE(ha) ((ha)->mqenable || IS_QLA83XX(ha) || \
3188 #define IS_BIDI_CAPABLE(ha) ((IS_QLA25XX(ha) || IS_QLA2031(ha)))
3189 /* Bit 21 of fw_attributes decides the MCTP capabilities */
3190 #define IS_MCTP_CAPABLE(ha) (IS_QLA2031(ha) && \
3191 ((ha)->fw_attributes_ext[0] & BIT_0))
3192 #define IS_PI_UNINIT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha))
3193 #define IS_PI_IPGUARD_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha))
3194 #define IS_PI_DIFB_DIX0_CAPABLE(ha) (0)
3195 #define IS_PI_SPLIT_DET_CAPABLE_HBA(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha))
3196 #define IS_PI_SPLIT_DET_CAPABLE(ha) (IS_PI_SPLIT_DET_CAPABLE_HBA(ha) && \
3197 (((ha)->fw_attributes_h << 16 | (ha)->fw_attributes) & BIT_22))
3198 #define IS_ATIO_MSIX_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha))
3199 #define IS_TGT_MODE_CAPABLE(ha) (ha->tgt.atio_q_length)
3200 #define IS_SHADOW_REG_CAPABLE(ha) (IS_QLA27XX(ha))
3201 #define IS_DPORT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha))
3202 #define IS_FAWWN_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha))
3204 /* HBA serial number */
3209 /* NVRAM configuration data */
3210 #define MAX_NVRAM_SIZE 4096
3211 #define VPD_OFFSET MAX_NVRAM_SIZE / 2
3212 uint16_t nvram_size;
3213 uint16_t nvram_base;
3219 uint16_t loop_reset_delay;
3220 uint8_t retry_count;
3221 uint8_t login_timeout;
3223 int port_down_retry_count;
3225 uint8_t aen_mbx_count;
3227 uint32_t login_retry_count;
3228 /* SNS command interfaces. */
3229 ms_iocb_entry_t *ms_iocb;
3230 dma_addr_t ms_iocb_dma;
3231 struct ct_sns_pkt *ct_sns;
3232 dma_addr_t ct_sns_dma;
3233 /* SNS command interfaces for 2200. */
3234 struct sns_cmd_pkt *sns_cmd;
3235 dma_addr_t sns_cmd_dma;
3237 #define SFP_DEV_SIZE 256
3238 #define SFP_BLOCK_SIZE 64
3240 dma_addr_t sfp_data_dma;
3242 #define XGMAC_DATA_SIZE 4096
3244 dma_addr_t xgmac_data_dma;
3246 #define DCBX_TLV_DATA_SIZE 4096
3248 dma_addr_t dcbx_tlv_dma;
3250 struct task_struct *dpc_thread;
3251 uint8_t dpc_active; /* DPC routine is active */
3253 dma_addr_t gid_list_dma;
3254 struct gid_list_info *gid_list;
3255 int gid_list_info_size;
3257 /* Small DMA pool allocations -- maximum 256 bytes in length. */
3258 #define DMA_POOL_SIZE 256
3259 struct dma_pool *s_dma_pool;
3261 dma_addr_t init_cb_dma;
3264 dma_addr_t ex_init_cb_dma;
3265 struct ex_init_cb_81xx *ex_init_cb;
3268 dma_addr_t async_pd_dma;
3270 #define ENABLE_EXTENDED_LOGIN BIT_7
3272 /* Extended Logins */
3274 dma_addr_t exlogin_buf_dma;
3277 #define ENABLE_EXCHANGE_OFFLD BIT_2
3279 /* Exchange Offload */
3280 void *exchoffld_buf;
3281 dma_addr_t exchoffld_buf_dma;
3283 int exchoffld_count;
3287 /* These are used by mailbox operations. */
3288 uint16_t mailbox_out[MAILBOX_REGISTER_COUNT];
3289 uint32_t mailbox_out32[MAILBOX_REGISTER_COUNT];
3290 uint32_t aenmb[AEN_MAILBOX_REGISTER_COUNT_FX00];
3293 struct mbx_cmd_32 *mcp32;
3295 unsigned long mbx_cmd_flags;
3296 #define MBX_INTERRUPT 1
3297 #define MBX_INTR_WAIT 2
3298 #define MBX_UPDATE_FLASH_ACTIVE 3
3300 struct mutex vport_lock; /* Virtual port synchronization */
3301 spinlock_t vport_slock; /* order is hardware_lock, then vport_slock */
3302 struct completion mbx_cmd_comp; /* Serialize mbx access */
3303 struct completion mbx_intr_comp; /* Used for completion notification */
3304 struct completion dcbx_comp; /* For set port config notification */
3305 struct completion lb_portup_comp; /* Used to wait for link up during
3307 #define DCBX_COMP_TIMEOUT 20
3308 #define LB_PORTUP_COMP_TIMEOUT 10
3310 int notify_dcbx_comp;
3311 int notify_lb_portup_comp;
3312 struct mutex selflogin_lock;
3314 /* Basic firmware related information. */
3315 uint16_t fw_major_version;
3316 uint16_t fw_minor_version;
3317 uint16_t fw_subminor_version;
3318 uint16_t fw_attributes;
3319 uint16_t fw_attributes_h;
3320 uint16_t fw_attributes_ext[2];
3321 uint32_t fw_memory_size;
3322 uint32_t fw_transfer_size;
3323 uint32_t fw_srisc_address;
3324 #define RISC_START_ADDRESS_2100 0x1000
3325 #define RISC_START_ADDRESS_2300 0x800
3326 #define RISC_START_ADDRESS_2400 0x100000
3328 uint16_t orig_fw_tgt_xcb_count;
3329 uint16_t cur_fw_tgt_xcb_count;
3330 uint16_t orig_fw_xcb_count;
3331 uint16_t cur_fw_xcb_count;
3332 uint16_t orig_fw_iocb_count;
3333 uint16_t cur_fw_iocb_count;
3334 uint16_t fw_max_fcf_count;
3336 uint32_t fw_shared_ram_start;
3337 uint32_t fw_shared_ram_end;
3339 uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */
3340 uint8_t fw_seriallink_options[4];
3341 uint16_t fw_seriallink_options24[4];
3343 uint8_t mpi_version[3];
3344 uint32_t mpi_capabilities;
3345 uint8_t phy_version[3];
3346 uint8_t pep_version[3];
3348 /* Firmware dump template */
3349 void *fw_dump_template;
3350 uint32_t fw_dump_template_len;
3351 /* Firmware dump information. */
3352 struct qla2xxx_fw_dump *fw_dump;
3353 uint32_t fw_dump_len;
3355 unsigned long fw_dump_cap_flags;
3356 #define RISC_PAUSE_CMPL 0
3357 #define DMA_SHUTDOWN_CMPL 1
3358 #define ISP_RESET_CMPL 2
3359 #define RISC_RDY_AFT_RESET 3
3360 #define RISC_SRAM_DUMP_CMPL 4
3361 #define RISC_EXT_MEM_DUMP_CMPL 5
3362 #define ISP_MBX_RDY 6
3363 #define ISP_SOFT_RESET_CMPL 7
3364 int fw_dump_reading;
3365 int prev_minidump_failed;
3368 /* Current size of mctp dump is 0x086064 bytes */
3369 #define MCTP_DUMP_SIZE 0x086064
3370 dma_addr_t mctp_dump_dma;
3373 int mctp_dump_reading;
3374 uint32_t chain_offset;
3375 struct dentry *dfs_dir;
3376 struct dentry *dfs_fce;
3377 struct dentry *dfs_tgt_counters;
3378 struct dentry *dfs_fw_resource_cnt;
3384 uint64_t fce_wr, fce_rd;
3385 struct mutex fce_mutex;
3388 uint16_t chip_revision;
3390 uint16_t product_id[4];
3392 uint8_t model_number[16+1];
3393 #define BINZERO "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0"
3394 char model_desc[80];
3395 uint8_t adapter_id[16+1];
3397 /* Option ROM information. */
3398 char *optrom_buffer;
3399 uint32_t optrom_size;
3401 #define QLA_SWAITING 0
3402 #define QLA_SREADING 1
3403 #define QLA_SWRITING 2
3404 uint32_t optrom_region_start;
3405 uint32_t optrom_region_size;
3406 struct mutex optrom_mutex;
3408 /* PCI expansion ROM image information. */
3409 #define ROM_CODE_TYPE_BIOS 0
3410 #define ROM_CODE_TYPE_FCODE 1
3411 #define ROM_CODE_TYPE_EFI 3
3412 uint8_t bios_revision[2];
3413 uint8_t efi_revision[2];
3414 uint8_t fcode_revision[16];
3415 uint32_t fw_revision[4];
3417 uint32_t gold_fw_version[4];
3419 /* Offsets for flash/nvram access (set to ~0 if not used). */
3420 uint32_t flash_conf_off;
3421 uint32_t flash_data_off;
3422 uint32_t nvram_conf_off;
3423 uint32_t nvram_data_off;
3425 uint32_t fdt_wrt_disable;
3426 uint32_t fdt_wrt_enable;
3427 uint32_t fdt_erase_cmd;
3428 uint32_t fdt_block_size;
3429 uint32_t fdt_unprotect_sec_cmd;
3430 uint32_t fdt_protect_sec_cmd;
3431 uint32_t fdt_wrt_sts_reg_cmd;
3433 uint32_t flt_region_flt;
3434 uint32_t flt_region_fdt;
3435 uint32_t flt_region_boot;
3436 uint32_t flt_region_fw;
3437 uint32_t flt_region_vpd_nvram;
3438 uint32_t flt_region_vpd;
3439 uint32_t flt_region_nvram;
3440 uint32_t flt_region_npiv_conf;
3441 uint32_t flt_region_gold_fw;
3442 uint32_t flt_region_fcp_prio;
3443 uint32_t flt_region_bootload;
3445 /* Needed for BEACON */
3446 uint16_t beacon_blink_led;
3447 uint8_t beacon_color_state;
3448 #define QLA_LED_GRN_ON 0x01
3449 #define QLA_LED_YLW_ON 0x02
3450 #define QLA_LED_ABR_ON 0x04
3451 #define QLA_LED_ALL_ON 0x07 /* yellow, green, amber. */
3452 /* ISP2322: red, green, amber. */
3456 struct qla_msix_entry *msix_entries;
3458 struct list_head vp_list; /* list of VP */
3459 unsigned long vp_idx_map[(MAX_MULTI_ID_FABRIC / 8) /
3460 sizeof(unsigned long)];
3461 uint16_t num_vhosts; /* number of vports created */
3462 uint16_t num_vsans; /* number of vsan created */
3463 uint16_t max_npiv_vports; /* 63 or 125 per topoloty */
3464 int cur_vport_count;
3466 struct qla_chip_state_84xx *cs84xx;
3467 struct qla_statistics qla_stats;
3468 struct isp_operations *isp_ops;
3469 struct workqueue_struct *wq;
3470 struct qlfc_fw fw_buf;
3472 /* FCP_CMND priority support */
3473 struct qla_fcp_prio_cfg *fcp_prio_cfg;
3475 struct dma_pool *dl_dma_pool;
3476 #define DSD_LIST_DMA_POOL_SIZE 512
3478 struct dma_pool *fcp_cmnd_dma_pool;
3479 mempool_t *ctx_mempool;
3480 #define FCP_CMND_DMA_POOL_SIZE 512
3482 void __iomem *nx_pcibase; /* Base I/O address */
3483 void __iomem *nxdb_rd_ptr; /* Doorbell read pointer */
3484 void __iomem *nxdb_wr_ptr; /* Door bell write pointer */
3487 uint32_t curr_window;
3488 uint32_t ddr_mn_window;
3489 unsigned long mn_win_crb;
3490 unsigned long ms_win_crb;
3492 uint32_t fcoe_dev_init_timeout;
3493 uint32_t fcoe_reset_timeout;
3495 uint16_t portnum; /* port number */
3497 struct fw_blob *hablob;
3498 struct qla82xx_legacy_intr_set nx_legacy_intr;
3500 uint16_t gbl_dsd_inuse;
3501 uint16_t gbl_dsd_avail;
3502 struct list_head gbl_dsd_list;
3503 #define NUM_DSD_CHAIN 4096
3506 __le32 file_prd_off; /* File firmware product offset */
3508 uint32_t md_template_size;
3510 dma_addr_t md_tmplt_hdr_dma;
3512 uint32_t md_dump_size;
3516 /* QLA83XX IDC specific fields */
3517 uint32_t idc_audit_ts;
3518 uint32_t idc_extend_tmo;
3520 /* DPC low-priority workqueue */
3521 struct workqueue_struct *dpc_lp_wq;
3522 struct work_struct idc_aen;
3523 /* DPC high-priority workqueue */
3524 struct workqueue_struct *dpc_hp_wq;
3525 struct work_struct nic_core_reset;
3526 struct work_struct idc_state_handler;
3527 struct work_struct nic_core_unrecoverable;
3528 struct work_struct board_disable;
3530 struct mr_data_fx00 mr;
3531 uint32_t chip_reset;
3533 struct qlt_hw_data tgt;
3534 int allow_cna_fw_dump;
3537 struct qla_tgt_counters {
3538 uint64_t qla_core_sbt_cmd;
3539 uint64_t core_qla_que_buf;
3540 uint64_t qla_core_ret_ctio;
3541 uint64_t core_qla_snd_status;
3542 uint64_t qla_core_ret_sta_ctio;
3543 uint64_t core_qla_free_cmd;
3544 uint64_t num_q_full_sent;
3545 uint64_t num_alloc_iocb_failed;
3546 uint64_t num_term_xchg_sent;
3550 * Qlogic scsi host structure
3552 typedef struct scsi_qla_host {
3553 struct list_head list;
3554 struct list_head vp_fcports; /* list of fcports */
3555 struct list_head work_list;
3556 spinlock_t work_lock;
3558 /* Commonly used flags and state information. */
3559 struct Scsi_Host *host;
3560 unsigned long host_no;
3561 uint8_t host_str[16];
3564 uint32_t init_done :1;
3566 uint32_t reset_active :1;
3568 uint32_t management_server_logged_in :1;
3569 uint32_t process_response_queue :1;
3570 uint32_t difdix_supported:1;
3571 uint32_t delete_progress:1;
3573 uint32_t fw_tgt_reported:1;
3576 atomic_t loop_state;
3577 #define LOOP_TIMEOUT 1
3580 #define LOOP_UPDATE 4
3581 #define LOOP_READY 5
3584 unsigned long dpc_flags;
3585 #define RESET_MARKER_NEEDED 0 /* Send marker to ISP. */
3586 #define RESET_ACTIVE 1
3587 #define ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */
3588 #define ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */
3589 #define LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */
3590 #define LOOP_RESYNC_ACTIVE 5
3591 #define LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */
3592 #define RSCN_UPDATE 7 /* Perform an RSCN update. */
3593 #define RELOGIN_NEEDED 8
3594 #define REGISTER_FC4_NEEDED 9 /* SNS FC4 registration required. */
3595 #define ISP_ABORT_RETRY 10 /* ISP aborted. */
3596 #define BEACON_BLINK_NEEDED 11
3597 #define REGISTER_FDMI_NEEDED 12
3598 #define FCPORT_UPDATE_NEEDED 13
3599 #define VP_DPC_NEEDED 14 /* wake up for VP dpc handling */
3600 #define UNLOADING 15
3601 #define NPIV_CONFIG_NEEDED 16
3602 #define ISP_UNRECOVERABLE 17
3603 #define FCOE_CTX_RESET_NEEDED 18 /* Initiate FCoE context reset */
3604 #define MPI_RESET_NEEDED 19 /* Initiate MPI FW reset */
3605 #define ISP_QUIESCE_NEEDED 20 /* Driver need some quiescence */
3606 #define SCR_PENDING 21 /* SCR in target mode */
3607 #define PORT_UPDATE_NEEDED 22
3608 #define FX00_RESET_RECOVERY 23
3609 #define FX00_TARGET_SCAN 24
3610 #define FX00_CRITEMP_RECOVERY 25
3611 #define FX00_HOST_INFO_RESEND 26
3613 unsigned long pci_flags;
3614 #define PFLG_DISCONNECTED 0 /* PCI device removed */
3615 #define PFLG_DRIVER_REMOVING 1 /* PCI driver .remove */
3616 #define PFLG_DRIVER_PROBING 2 /* PCI driver .probe */
3618 uint32_t device_flags;
3619 #define SWITCH_FOUND BIT_0
3620 #define DFLG_NO_CABLE BIT_1
3621 #define DFLG_DEV_FAILED BIT_5
3623 /* ISP configuration data. */
3624 uint16_t loop_id; /* Host adapter loop id */
3625 uint16_t self_login_loop_id; /* host adapter loop id
3626 * get it on self login
3628 fc_port_t bidir_fcport; /* fcport used for bidir cmnds
3629 * no need of allocating it for
3633 port_id_t d_id; /* Host adapter port id */
3634 uint8_t marker_needed;
3635 uint16_t mgmt_svr_loop_id;
3639 /* Timeout timers. */
3640 uint8_t loop_down_abort_time; /* port down timer */
3641 atomic_t loop_down_timer; /* loop down timer */
3642 uint8_t link_down_timeout; /* link down timeout */
3644 uint32_t timer_active;
3645 struct timer_list timer;
3647 uint8_t node_name[WWN_SIZE];
3648 uint8_t port_name[WWN_SIZE];
3649 uint8_t fabric_node_name[WWN_SIZE];
3651 uint16_t fcoe_vlan_id;
3652 uint16_t fcoe_fcf_idx;
3653 uint8_t fcoe_vn_port_mac[6];
3655 /* list of commands waiting on workqueue */
3656 struct list_head qla_cmd_list;
3657 struct list_head qla_sess_op_cmd_list;
3658 spinlock_t cmd_list_lock;
3660 /* Counter to detect races between ELS and RSCN events */
3661 atomic_t generation_tick;
3662 /* Time when global fcport update has been scheduled */
3663 int total_fcport_update_gen;
3664 /* List of pending LOGOs, protected by tgt_mutex */
3665 struct list_head logo_list;
3666 /* List of pending PLOGI acks, protected by hw lock */
3667 struct list_head plogi_ack_list;
3669 uint32_t vp_abort_cnt;
3671 struct fc_vport *fc_vport; /* holds fc_vport * for each vport */
3672 uint16_t vp_idx; /* vport ID */
3674 unsigned long vp_flags;
3675 #define VP_IDX_ACQUIRED 0 /* bit no 0 */
3676 #define VP_CREATE_NEEDED 1
3677 #define VP_BIND_NEEDED 2
3678 #define VP_DELETE_NEEDED 3
3679 #define VP_SCR_NEEDED 4 /* State Change Request registration */
3680 #define VP_CONFIG_OK 5 /* Flag to cfg VP, if FW is ready */
3682 #define VP_OFFLINE 0
3685 // #define VP_DISABLE 3
3686 uint16_t vp_err_state;
3687 uint16_t vp_prev_err_state;
3688 #define VP_ERR_UNKWN 0
3689 #define VP_ERR_PORTDWN 1
3690 #define VP_ERR_FAB_UNSUPPORTED 2
3691 #define VP_ERR_FAB_NORESOURCES 3
3692 #define VP_ERR_FAB_LOGOUT 4
3693 #define VP_ERR_ADAP_NORESOURCES 5
3694 struct qla_hw_data *hw;
3695 struct scsi_qlt_host vha_tgt;
3696 struct req_que *req;
3697 int fw_heartbeat_counter;
3698 int seconds_since_last_heartbeat;
3699 struct fc_host_statistics fc_host_stat;
3700 struct qla_statistics qla_stats;
3701 struct bidi_statistics bidi_stats;
3703 atomic_t vref_count;
3704 struct qla8044_reset_template reset_tmplt;
3705 struct qla_tgt_counters tgt_counters;
3708 #define SET_VP_IDX 1
3710 #define RESET_VP_IDX 3
3711 #define RESET_AL_PA 4
3712 struct qla_tgt_vp_map {
3714 scsi_qla_host_t *vha;
3718 * Macros to help code, maintain, etc.
3720 #define LOOP_TRANSITION(ha) \
3721 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
3722 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \
3723 atomic_read(&ha->loop_state) == LOOP_DOWN)
3725 #define STATE_TRANSITION(ha) \
3726 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
3727 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags))
3729 #define QLA_VHA_MARK_BUSY(__vha, __bail) do { \
3730 atomic_inc(&__vha->vref_count); \
3732 if (__vha->flags.delete_progress) { \
3733 atomic_dec(&__vha->vref_count); \
3740 #define QLA_VHA_MARK_NOT_BUSY(__vha) do { \
3741 atomic_dec(&__vha->vref_count); \
3745 * qla2x00 local function return status codes
3747 #define MBS_MASK 0x3fff
3749 #define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK)
3750 #define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK)
3751 #define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK)
3752 #define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK)
3753 #define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK)
3754 #define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK)
3755 #define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK)
3756 #define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK)
3757 #define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK)
3758 #define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK)
3760 #define QLA_FUNCTION_TIMEOUT 0x100
3761 #define QLA_FUNCTION_PARAMETER_ERROR 0x101
3762 #define QLA_FUNCTION_FAILED 0x102
3763 #define QLA_MEMORY_ALLOC_FAILED 0x103
3764 #define QLA_LOCK_TIMEOUT 0x104
3765 #define QLA_ABORTED 0x105
3766 #define QLA_SUSPENDED 0x106
3767 #define QLA_BUSY 0x107
3768 #define QLA_ALREADY_REGISTERED 0x109
3770 #define NVRAM_DELAY() udelay(10)
3773 * Flash support definitions
3775 #define OPTROM_SIZE_2300 0x20000
3776 #define OPTROM_SIZE_2322 0x100000
3777 #define OPTROM_SIZE_24XX 0x100000
3778 #define OPTROM_SIZE_25XX 0x200000
3779 #define OPTROM_SIZE_81XX 0x400000
3780 #define OPTROM_SIZE_82XX 0x800000
3781 #define OPTROM_SIZE_83XX 0x1000000
3783 #define OPTROM_BURST_SIZE 0x1000
3784 #define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4)
3786 #define QLA_DSDS_PER_IOCB 37
3788 #define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr)
3790 #define QLA_SG_ALL 1024
3792 enum nexus_wait_type {
3798 #include "qla_gbl.h"
3799 #include "qla_dbg.h"
3800 #include "qla_inline.h"
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