2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2014 QLogic Corporation
5 * See LICENSE.qla2xxx for copyright and licensing details.
10 #define MBS_CHECKSUM_ERROR 0x4010
11 #define MBS_INVALID_PRODUCT_KEY 0x4020
16 #define FO1_ENABLE_PUREX BIT_10
17 #define FO1_DISABLE_LED_CTRL BIT_6
18 #define FO1_ENABLE_8016 BIT_0
19 #define FO2_ENABLE_SEL_CLASS2 BIT_5
20 #define FO3_NO_ABTS_ON_LINKDOWN BIT_14
21 #define FO3_HOLD_STS_IOCB BIT_12
24 * Port Database structure definition for ISP 24xx.
26 #define PDO_FORCE_ADISC BIT_1
27 #define PDO_FORCE_PLOGI BIT_0
30 #define PORT_DATABASE_24XX_SIZE 64
31 struct port_database_24xx {
33 #define PDF_TASK_RETRY_ID BIT_14
34 #define PDF_FC_TAPE BIT_7
35 #define PDF_ACK0_CAPABLE BIT_6
36 #define PDF_FCP2_CONF BIT_5
37 #define PDF_CLASS_2 BIT_4
38 #define PDF_HARD_ADDR BIT_1
40 uint8_t current_login_state;
41 uint8_t last_login_state;
42 #define PDS_PLOGI_PENDING 0x03
43 #define PDS_PLOGI_COMPLETE 0x04
44 #define PDS_PRLI_PENDING 0x05
45 #define PDS_PRLI_COMPLETE 0x06
46 #define PDS_PORT_UNAVAILABLE 0x07
47 #define PDS_PRLO_PENDING 0x09
48 #define PDS_LOGO_PENDING 0x11
49 #define PDS_PRLI2_PENDING 0x12
51 uint8_t hard_address[3];
59 uint16_t nport_handle; /* N_PORT handle. */
61 uint16_t receive_data_size;
64 uint8_t prli_svc_param_word_0[2]; /* Big endian */
65 /* Bits 15-0 of word 0 */
66 uint8_t prli_svc_param_word_3[2]; /* Big endian */
67 /* Bits 15-0 of word 3 */
69 uint8_t port_name[WWN_SIZE];
70 uint8_t node_name[WWN_SIZE];
72 uint8_t reserved_3[24];
76 * MB 75h returns a list of DB entries similar to port_database_24xx(64B).
77 * However, in this case it returns 1st 40 bytes.
79 struct get_name_list_extended {
81 u8 current_login_state;
88 __le16 nport_handle; /* N_PORT handle. */
89 __le16 receive_data_size;
92 /* PRLI SVC Param are Big endian */
93 u8 prli_svc_param_word_0[2]; /* Bits 15-0 of word 0 */
94 u8 prli_svc_param_word_3[2]; /* Bits 15-0 of word 3 */
95 u8 port_name[WWN_SIZE];
96 u8 node_name[WWN_SIZE];
99 /* MB 75h: This is the short version of the database */
100 struct get_name_list {
101 u8 port_node_name[WWN_SIZE]; /* B7 most sig, B0 least sig */
106 struct vp_database_24xx {
110 uint8_t port_name[WWN_SIZE];
111 uint8_t node_name[WWN_SIZE];
112 uint16_t port_id_low;
113 uint16_t port_id_high;
119 uint16_t nvram_version;
122 /* Firmware Initialization Control Block. */
125 __le16 frame_payload_size;
126 uint16_t execution_throttle;
127 uint16_t exchange_count;
128 uint16_t hard_address;
130 uint8_t port_name[WWN_SIZE];
131 uint8_t node_name[WWN_SIZE];
133 uint16_t login_retry_count;
134 uint16_t link_down_on_nos;
135 uint16_t interrupt_delay_timer;
136 uint16_t login_timeout;
138 uint32_t firmware_options_1;
139 uint32_t firmware_options_2;
140 uint32_t firmware_options_3;
145 * BIT 0 = Control Enable
149 * BIT 8-10 = Output Swing 1G
150 * BIT 11-13 = Output Emphasis 1G
151 * BIT 14-15 = Reserved
154 * BIT 8-10 = Output Swing 2G
155 * BIT 11-13 = Output Emphasis 2G
156 * BIT 14-15 = Reserved
159 * BIT 8-10 = Output Swing 4G
160 * BIT 11-13 = Output Emphasis 4G
161 * BIT 14-15 = Reserved
163 uint16_t seriallink_options[4];
165 uint16_t reserved_2[16];
168 uint16_t reserved_3[16];
170 /* PCIe table entries. */
171 uint16_t reserved_4[16];
174 uint16_t reserved_5[16];
177 uint16_t reserved_6[16];
180 uint16_t reserved_7[16];
183 * BIT 0 = Enable spinup delay
184 * BIT 1 = Disable BIOS
185 * BIT 2 = Enable Memory Map BIOS
186 * BIT 3 = Enable Selectable Boot
187 * BIT 4 = Disable RISC code load
188 * BIT 5 = Disable Serdes
194 * BIT 10 = Enable lip full login
195 * BIT 11 = Enable target reset
199 * BIT 15 = Enable alternate WWN
205 uint8_t alternate_port_name[WWN_SIZE];
206 uint8_t alternate_node_name[WWN_SIZE];
208 uint8_t boot_port_name[WWN_SIZE];
209 uint16_t boot_lun_number;
212 uint8_t alt1_boot_port_name[WWN_SIZE];
213 uint16_t alt1_boot_lun_number;
216 uint8_t alt2_boot_port_name[WWN_SIZE];
217 uint16_t alt2_boot_lun_number;
218 uint16_t reserved_10;
220 uint8_t alt3_boot_port_name[WWN_SIZE];
221 uint16_t alt3_boot_lun_number;
222 uint16_t reserved_11;
225 * BIT 0 = Selective Login
226 * BIT 1 = Alt-Boot Enable
228 * BIT 3 = Boot Order List
230 * BIT 5 = Selective LUN
234 uint32_t efi_parameters;
238 uint16_t reserved_13;
240 uint16_t boot_id_number;
241 uint16_t reserved_14;
243 uint16_t max_luns_per_target;
244 uint16_t reserved_15;
246 uint16_t port_down_retry_count;
247 uint16_t link_down_timeout;
249 /* FCode parameters. */
250 uint16_t fcode_parameter;
252 uint16_t reserved_16[3];
255 uint8_t prev_drv_ver_major;
256 uint8_t prev_drv_ver_submajob;
257 uint8_t prev_drv_ver_minor;
258 uint8_t prev_drv_ver_subminor;
260 uint16_t prev_bios_ver_major;
261 uint16_t prev_bios_ver_minor;
263 uint16_t prev_efi_ver_major;
264 uint16_t prev_efi_ver_minor;
266 uint16_t prev_fw_ver_major;
267 uint8_t prev_fw_ver_minor;
268 uint8_t prev_fw_ver_subminor;
270 uint16_t reserved_17[8];
273 uint16_t reserved_18[16];
276 uint16_t reserved_19[16];
279 uint16_t reserved_20[16];
282 uint8_t model_name[16];
284 uint16_t reserved_21[2];
287 /* HW Parameter Block. */
288 uint16_t pcie_table_sig;
289 uint16_t pcie_table_offset;
291 uint16_t subsystem_vendor_id;
292 uint16_t subsystem_device_id;
298 * ISP Initialization Control Block.
299 * Little endian except where noted.
301 #define ICB_VERSION 1
302 struct init_cb_24xx {
306 uint16_t frame_payload_size;
307 uint16_t execution_throttle;
308 uint16_t exchange_count;
310 uint16_t hard_address;
312 uint8_t port_name[WWN_SIZE]; /* Big endian. */
313 uint8_t node_name[WWN_SIZE]; /* Big endian. */
315 uint16_t response_q_inpointer;
316 uint16_t request_q_outpointer;
318 uint16_t login_retry_count;
320 uint16_t prio_request_q_outpointer;
322 uint16_t response_q_length;
323 uint16_t request_q_length;
325 uint16_t link_down_on_nos; /* Milliseconds. */
327 uint16_t prio_request_q_length;
329 uint32_t request_q_address[2];
330 uint32_t response_q_address[2];
331 uint32_t prio_request_q_address[2];
335 uint8_t reserved_2[4];
337 uint16_t atio_q_inpointer;
338 uint16_t atio_q_length;
339 uint32_t atio_q_address[2];
341 uint16_t interrupt_delay_timer; /* 100us increments. */
342 uint16_t login_timeout;
345 * BIT 0 = Enable Hard Loop Id
346 * BIT 1 = Enable Fairness
347 * BIT 2 = Enable Full-Duplex
349 * BIT 4 = Enable Target Mode
350 * BIT 5 = Disable Initiator Mode
351 * BIT 6 = Acquire FA-WWN
352 * BIT 7 = Enable D-port Diagnostics
355 * BIT 9 = Non Participating LIP
356 * BIT 10 = Descending Loop ID Search
357 * BIT 11 = Acquire Loop ID in LIPA
359 * BIT 13 = Full Login after LIP
360 * BIT 14 = Node Name Option
361 * BIT 15-31 = Reserved
363 uint32_t firmware_options_1;
366 * BIT 0 = Operation Mode bit 0
367 * BIT 1 = Operation Mode bit 1
368 * BIT 2 = Operation Mode bit 2
369 * BIT 3 = Operation Mode bit 3
370 * BIT 4 = Connection Options bit 0
371 * BIT 5 = Connection Options bit 1
372 * BIT 6 = Connection Options bit 2
373 * BIT 7 = Enable Non part on LIHA failure
375 * BIT 8 = Enable Class 2
376 * BIT 9 = Enable ACK0
378 * BIT 11 = Enable FC-SP Security
379 * BIT 12 = FC Tape Enable
381 * BIT 14 = Enable Target PRLI Control
382 * BIT 15-31 = Reserved
384 uint32_t firmware_options_2;
388 * BIT 1 = Soft ID only
391 * BIT 4 = FCP RSP Payload bit 0
392 * BIT 5 = FCP RSP Payload bit 1
393 * BIT 6 = Enable Receive Out-of-Order data frame handling
394 * BIT 7 = Disable Automatic PLOGI on Local Loop
397 * BIT 9 = Enable Out-of-Order FCP_XFER_RDY relative offset handling
401 * BIT 13 = Data Rate bit 0
402 * BIT 14 = Data Rate bit 1
403 * BIT 15 = Data Rate bit 2
404 * BIT 16 = Enable 75 ohm Termination Select
405 * BIT 17-28 = Reserved
406 * BIT 29 = Enable response queue 0 in index shadowing
407 * BIT 30 = Enable request queue 0 out index shadowing
410 uint32_t firmware_options_3;
413 uint8_t reserved_3[20];
417 * ISP queue - command entry structure definition.
419 #define COMMAND_BIDIRECTIONAL 0x75
421 uint8_t entry_type; /* Entry type. */
422 uint8_t entry_count; /* Entry count. */
423 uint8_t sys_define; /* System defined */
424 uint8_t entry_status; /* Entry status. */
426 uint32_t handle; /* System handle. */
428 uint16_t nport_handle; /* N_PORT hanlde. */
430 uint16_t timeout; /* Commnad timeout. */
432 uint16_t wr_dseg_count; /* Write Data segment count. */
433 uint16_t rd_dseg_count; /* Read Data segment count. */
435 struct scsi_lun lun; /* FCP LUN (BE). */
437 uint16_t control_flags; /* Control flags. */
438 #define BD_WRAP_BACK BIT_3
439 #define BD_READ_DATA BIT_1
440 #define BD_WRITE_DATA BIT_0
442 uint16_t fcp_cmnd_dseg_len; /* Data segment length. */
443 uint32_t fcp_cmnd_dseg_address[2]; /* Data segment address. */
445 uint16_t reserved[2]; /* Reserved */
447 uint32_t rd_byte_count; /* Total Byte count Read. */
448 uint32_t wr_byte_count; /* Total Byte count write. */
450 uint8_t port_id[3]; /* PortID of destination port.*/
453 uint32_t fcp_data_dseg_address[2]; /* Data segment address. */
454 uint16_t fcp_data_dseg_len; /* Data segment length. */
457 #define COMMAND_TYPE_6 0x48 /* Command Type 6 entry */
459 uint8_t entry_type; /* Entry type. */
460 uint8_t entry_count; /* Entry count. */
461 uint8_t sys_define; /* System defined. */
462 uint8_t entry_status; /* Entry Status. */
464 uint32_t handle; /* System handle. */
466 uint16_t nport_handle; /* N_PORT handle. */
467 uint16_t timeout; /* Command timeout. */
469 uint16_t dseg_count; /* Data segment count. */
471 uint16_t fcp_rsp_dsd_len; /* FCP_RSP DSD length. */
473 struct scsi_lun lun; /* FCP LUN (BE). */
475 uint16_t control_flags; /* Control flags. */
476 #define CF_DIF_SEG_DESCR_ENABLE BIT_3
477 #define CF_DATA_SEG_DESCR_ENABLE BIT_2
478 #define CF_READ_DATA BIT_1
479 #define CF_WRITE_DATA BIT_0
481 uint16_t fcp_cmnd_dseg_len; /* Data segment length. */
482 uint32_t fcp_cmnd_dseg_address[2]; /* Data segment address. */
484 uint32_t fcp_rsp_dseg_address[2]; /* Data segment address. */
486 uint32_t byte_count; /* Total byte count. */
488 uint8_t port_id[3]; /* PortID of destination port. */
491 uint32_t fcp_data_dseg_address[2]; /* Data segment address. */
492 uint32_t fcp_data_dseg_len; /* Data segment length. */
495 #define COMMAND_TYPE_7 0x18 /* Command Type 7 entry */
497 uint8_t entry_type; /* Entry type. */
498 uint8_t entry_count; /* Entry count. */
499 uint8_t sys_define; /* System defined. */
500 uint8_t entry_status; /* Entry Status. */
502 uint32_t handle; /* System handle. */
504 uint16_t nport_handle; /* N_PORT handle. */
505 uint16_t timeout; /* Command timeout. */
506 #define FW_MAX_TIMEOUT 0x1999
508 uint16_t dseg_count; /* Data segment count. */
511 struct scsi_lun lun; /* FCP LUN (BE). */
513 uint16_t task_mgmt_flags; /* Task management flags. */
514 #define TMF_CLEAR_ACA BIT_14
515 #define TMF_TARGET_RESET BIT_13
516 #define TMF_LUN_RESET BIT_12
517 #define TMF_CLEAR_TASK_SET BIT_10
518 #define TMF_ABORT_TASK_SET BIT_9
519 #define TMF_DSD_LIST_ENABLE BIT_2
520 #define TMF_READ_DATA BIT_1
521 #define TMF_WRITE_DATA BIT_0
525 #define TSK_HEAD_OF_QUEUE 1
526 #define TSK_ORDERED 2
528 #define TSK_UNTAGGED 5
532 uint8_t fcp_cdb[MAX_CMDSZ]; /* SCSI command words. */
533 uint32_t byte_count; /* Total byte count. */
535 uint8_t port_id[3]; /* PortID of destination port. */
538 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
539 uint32_t dseg_0_len; /* Data segment 0 length. */
542 #define COMMAND_TYPE_CRC_2 0x6A /* Command Type CRC_2 (Type 6)
544 struct cmd_type_crc_2 {
545 uint8_t entry_type; /* Entry type. */
546 uint8_t entry_count; /* Entry count. */
547 uint8_t sys_define; /* System defined. */
548 uint8_t entry_status; /* Entry Status. */
550 uint32_t handle; /* System handle. */
552 uint16_t nport_handle; /* N_PORT handle. */
553 uint16_t timeout; /* Command timeout. */
555 uint16_t dseg_count; /* Data segment count. */
557 uint16_t fcp_rsp_dseg_len; /* FCP_RSP DSD length. */
559 struct scsi_lun lun; /* FCP LUN (BE). */
561 uint16_t control_flags; /* Control flags. */
563 uint16_t fcp_cmnd_dseg_len; /* Data segment length. */
564 uint32_t fcp_cmnd_dseg_address[2]; /* Data segment address. */
566 uint32_t fcp_rsp_dseg_address[2]; /* Data segment address. */
568 uint32_t byte_count; /* Total byte count. */
570 uint8_t port_id[3]; /* PortID of destination port. */
573 uint32_t crc_context_address[2]; /* Data segment address. */
574 uint16_t crc_context_len; /* Data segment length. */
575 uint16_t reserved_1; /* MUST be set to 0. */
580 * ISP queue - status entry structure definition.
582 #define STATUS_TYPE 0x03 /* Status entry. */
583 struct sts_entry_24xx {
584 uint8_t entry_type; /* Entry type. */
585 uint8_t entry_count; /* Entry count. */
586 uint8_t sys_define; /* System defined. */
587 uint8_t entry_status; /* Entry Status. */
589 uint32_t handle; /* System handle. */
591 uint16_t comp_status; /* Completion status. */
592 uint16_t ox_id; /* OX_ID used by the firmware. */
594 uint32_t residual_len; /* FW calc residual transfer length. */
597 uint16_t state_flags; /* State flags. */
598 #define SF_TRANSFERRED_DATA BIT_11
599 #define SF_FCP_RSP_DMA BIT_0
601 uint16_t retry_delay;
602 uint16_t scsi_status; /* SCSI status. */
603 #define SS_CONFIRMATION_REQ BIT_12
605 uint32_t rsp_residual_count; /* FCP RSP residual count. */
607 uint32_t sense_len; /* FCP SENSE length. */
608 uint32_t rsp_data_len; /* FCP response data length. */
609 uint8_t data[28]; /* FCP response/sense information. */
611 * If DIF Error is set in comp_status, these additional fields are
614 * !!! NOTE: Firmware sends expected/actual DIF data in big endian
615 * format; but all of the "data" field gets swab32-d in the beginning
616 * of qla2x00_status_entry().
618 * &data[10] : uint8_t report_runt_bg[2]; - computed guard
619 * &data[12] : uint8_t actual_dif[8]; - DIF Data received
620 * &data[20] : uint8_t expected_dif[8]; - DIF Data computed
626 * Status entry completion status
628 #define CS_DATA_REASSEMBLY_ERROR 0x11 /* Data Reassembly Error.. */
629 #define CS_ABTS_BY_TARGET 0x13 /* Target send ABTS to abort IOCB. */
630 #define CS_FW_RESOURCE 0x2C /* Firmware Resource Unavailable. */
631 #define CS_TASK_MGMT_OVERRUN 0x30 /* Task management overrun (8+). */
632 #define CS_ABORT_BY_TARGET 0x47 /* Abort By Target. */
635 * ISP queue - marker entry structure definition.
637 #define MARKER_TYPE 0x04 /* Marker entry. */
638 struct mrk_entry_24xx {
639 uint8_t entry_type; /* Entry type. */
640 uint8_t entry_count; /* Entry count. */
641 uint8_t handle_count; /* Handle count. */
642 uint8_t entry_status; /* Entry Status. */
644 uint32_t handle; /* System handle. */
646 uint16_t nport_handle; /* N_PORT handle. */
648 uint8_t modifier; /* Modifier (7-0). */
649 #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */
650 #define MK_SYNC_ID 1 /* Synchronize ID */
651 #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */
659 uint8_t lun[8]; /* FCP LUN (BE). */
660 uint8_t reserved_4[40];
664 * ISP queue - CT Pass-Through entry structure definition.
666 #define CT_IOCB_TYPE 0x29 /* CT Pass-Through IOCB entry */
667 struct ct_entry_24xx {
668 uint8_t entry_type; /* Entry type. */
669 uint8_t entry_count; /* Entry count. */
670 uint8_t sys_define; /* System Defined. */
671 uint8_t entry_status; /* Entry Status. */
673 uint32_t handle; /* System handle. */
675 uint16_t comp_status; /* Completion status. */
677 uint16_t nport_handle; /* N_PORT handle. */
679 uint16_t cmd_dsd_count;
684 uint16_t timeout; /* Command timeout. */
687 uint16_t rsp_dsd_count;
689 uint8_t reserved_3[10];
691 uint32_t rsp_byte_count;
692 uint32_t cmd_byte_count;
694 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
695 uint32_t dseg_0_len; /* Data segment 0 length. */
696 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
697 uint32_t dseg_1_len; /* Data segment 1 length. */
701 * ISP queue - ELS Pass-Through entry structure definition.
703 #define ELS_IOCB_TYPE 0x53 /* ELS Pass-Through IOCB entry */
704 struct els_entry_24xx {
705 uint8_t entry_type; /* Entry type. */
706 uint8_t entry_count; /* Entry count. */
707 uint8_t sys_define; /* System Defined. */
708 uint8_t entry_status; /* Entry Status. */
710 uint32_t handle; /* System handle. */
714 uint16_t nport_handle; /* N_PORT handle. */
716 uint16_t tx_dsd_count;
720 #define EST_SOFI3 (1 << 4)
721 #define EST_SOFI2 (3 << 4)
723 uint32_t rx_xchg_address; /* Receive exchange address. */
724 uint16_t rx_dsd_count;
734 uint16_t control_flags; /* Control flags. */
735 #define ECF_PAYLOAD_DESCR_MASK (BIT_15|BIT_14|BIT_13)
736 #define EPD_ELS_COMMAND (0 << 13)
737 #define EPD_ELS_ACC (1 << 13)
738 #define EPD_ELS_RJT (2 << 13)
739 #define EPD_RX_XCHG (3 << 13)
740 #define ECF_CLR_PASSTHRU_PEND BIT_12
741 #define ECF_INCL_FRAME_HDR BIT_11
743 uint32_t rx_byte_count;
744 uint32_t tx_byte_count;
746 uint32_t tx_address[2]; /* Data segment 0 address. */
747 uint32_t tx_len; /* Data segment 0 length. */
748 uint32_t rx_address[2]; /* Data segment 1 address. */
749 uint32_t rx_len; /* Data segment 1 length. */
752 struct els_sts_entry_24xx {
753 uint8_t entry_type; /* Entry type. */
754 uint8_t entry_count; /* Entry count. */
755 uint8_t sys_define; /* System Defined. */
756 uint8_t entry_status; /* Entry Status. */
758 uint32_t handle; /* System handle. */
760 uint16_t comp_status;
762 uint16_t nport_handle; /* N_PORT handle. */
769 uint32_t rx_xchg_address; /* Receive exchange address. */
780 uint16_t control_flags; /* Control flags. */
781 uint32_t total_byte_count;
782 uint32_t error_subcode_1;
783 uint32_t error_subcode_2;
786 * ISP queue - Mailbox Command entry structure definition.
788 #define MBX_IOCB_TYPE 0x39
789 struct mbx_entry_24xx {
790 uint8_t entry_type; /* Entry type. */
791 uint8_t entry_count; /* Entry count. */
792 uint8_t handle_count; /* Handle count. */
793 uint8_t entry_status; /* Entry Status. */
795 uint32_t handle; /* System handle. */
801 #define LOGINOUT_PORT_IOCB_TYPE 0x52 /* Login/Logout Port entry. */
802 struct logio_entry_24xx {
803 uint8_t entry_type; /* Entry type. */
804 uint8_t entry_count; /* Entry count. */
805 uint8_t sys_define; /* System defined. */
806 uint8_t entry_status; /* Entry Status. */
808 uint32_t handle; /* System handle. */
810 uint16_t comp_status; /* Completion status. */
811 #define CS_LOGIO_ERROR 0x31 /* Login/Logout IOCB error. */
813 uint16_t nport_handle; /* N_PORT handle. */
815 uint16_t control_flags; /* Control flags. */
817 #define LCF_INCLUDE_SNS BIT_10 /* Include SNS (FFFFFC) during LOGO. */
818 #define LCF_FCP2_OVERRIDE BIT_9 /* Set/Reset word 3 of PRLI. */
819 #define LCF_CLASS_2 BIT_8 /* Enable class 2 during PLOGI. */
820 #define LCF_FREE_NPORT BIT_7 /* Release NPORT handle after LOGO. */
821 #define LCF_EXPL_LOGO BIT_6 /* Perform an explicit LOGO. */
822 #define LCF_SKIP_PRLI BIT_5 /* Skip PRLI after PLOGI. */
823 #define LCF_IMPL_LOGO_ALL BIT_5 /* Implicit LOGO to all ports. */
824 #define LCF_COND_PLOGI BIT_4 /* PLOGI only if not logged-in. */
825 #define LCF_IMPL_LOGO BIT_4 /* Perform an implicit LOGO. */
826 #define LCF_IMPL_PRLO BIT_4 /* Perform an implicit PRLO. */
828 #define LCF_COMMAND_PLOGI 0x00 /* PLOGI. */
829 #define LCF_COMMAND_PRLI 0x01 /* PRLI. */
830 #define LCF_COMMAND_PDISC 0x02 /* PDISC. */
831 #define LCF_COMMAND_ADISC 0x03 /* ADISC. */
832 #define LCF_COMMAND_LOGO 0x08 /* LOGO. */
833 #define LCF_COMMAND_PRLO 0x09 /* PRLO. */
834 #define LCF_COMMAND_TPRLO 0x0A /* TPRLO. */
839 uint8_t port_id[3]; /* PortID of destination port. */
841 uint8_t rsp_size; /* Response size in 32bit words. */
843 uint32_t io_parameter[11]; /* General I/O parameters. */
844 #define LSC_SCODE_NOLINK 0x01
845 #define LSC_SCODE_NOIOCB 0x02
846 #define LSC_SCODE_NOXCB 0x03
847 #define LSC_SCODE_CMD_FAILED 0x04
848 #define LSC_SCODE_NOFABRIC 0x05
849 #define LSC_SCODE_FW_NOT_READY 0x07
850 #define LSC_SCODE_NOT_LOGGED_IN 0x09
851 #define LSC_SCODE_NOPCB 0x0A
853 #define LSC_SCODE_ELS_REJECT 0x18
854 #define LSC_SCODE_CMD_PARAM_ERR 0x19
855 #define LSC_SCODE_PORTID_USED 0x1A
856 #define LSC_SCODE_NPORT_USED 0x1B
857 #define LSC_SCODE_NONPORT 0x1C
858 #define LSC_SCODE_LOGGED_IN 0x1D
859 #define LSC_SCODE_NOFLOGI_ACC 0x1F
862 #define TSK_MGMT_IOCB_TYPE 0x14
863 struct tsk_mgmt_entry {
864 uint8_t entry_type; /* Entry type. */
865 uint8_t entry_count; /* Entry count. */
866 uint8_t handle_count; /* Handle count. */
867 uint8_t entry_status; /* Entry Status. */
869 uint32_t handle; /* System handle. */
871 uint16_t nport_handle; /* N_PORT handle. */
875 uint16_t delay; /* Activity delay in seconds. */
877 uint16_t timeout; /* Command timeout. */
879 struct scsi_lun lun; /* FCP LUN (BE). */
881 uint32_t control_flags; /* Control Flags. */
882 #define TCF_NOTMCMD_TO_TARGET BIT_31
883 #define TCF_LUN_RESET BIT_4
884 #define TCF_ABORT_TASK_SET BIT_3
885 #define TCF_CLEAR_TASK_SET BIT_2
886 #define TCF_TARGET_RESET BIT_1
887 #define TCF_CLEAR_ACA BIT_0
889 uint8_t reserved_2[20];
891 uint8_t port_id[3]; /* PortID of destination port. */
894 uint8_t reserved_3[12];
897 #define ABORT_IOCB_TYPE 0x33
898 struct abort_entry_24xx {
899 uint8_t entry_type; /* Entry type. */
900 uint8_t entry_count; /* Entry count. */
901 uint8_t handle_count; /* Handle count. */
902 uint8_t entry_status; /* Entry Status. */
904 uint32_t handle; /* System handle. */
906 uint16_t nport_handle; /* N_PORT handle. */
907 /* or Completion status. */
909 uint16_t options; /* Options. */
910 #define AOF_NO_ABTS BIT_0 /* Do not send any ABTS. */
912 uint32_t handle_to_abort; /* System handle to abort. */
915 uint8_t reserved_1[30];
917 uint8_t port_id[3]; /* PortID of destination port. */
920 uint8_t reserved_2[12];
924 * ISP I/O Register Set structure definitions.
926 struct device_reg_24xx {
927 uint32_t flash_addr; /* Flash/NVRAM BIOS address. */
928 #define FARX_DATA_FLAG BIT_31
929 #define FARX_ACCESS_FLASH_CONF 0x7FFD0000
930 #define FARX_ACCESS_FLASH_DATA 0x7FF00000
931 #define FARX_ACCESS_NVRAM_CONF 0x7FFF0000
932 #define FARX_ACCESS_NVRAM_DATA 0x7FFE0000
934 #define FA_NVRAM_FUNC0_ADDR 0x80
935 #define FA_NVRAM_FUNC1_ADDR 0x180
937 #define FA_NVRAM_VPD_SIZE 0x200
938 #define FA_NVRAM_VPD0_ADDR 0x00
939 #define FA_NVRAM_VPD1_ADDR 0x100
941 #define FA_BOOT_CODE_ADDR 0x00000
943 * RISC code begins at offset 512KB
944 * within flash. Consisting of two
945 * contiguous RISC code segments.
947 #define FA_RISC_CODE_ADDR 0x20000
948 #define FA_RISC_CODE_SEGMENTS 2
950 #define FA_FLASH_DESCR_ADDR_24 0x11000
951 #define FA_FLASH_LAYOUT_ADDR_24 0x11400
952 #define FA_NPIV_CONF0_ADDR_24 0x16000
953 #define FA_NPIV_CONF1_ADDR_24 0x17000
955 #define FA_FW_AREA_ADDR 0x40000
956 #define FA_VPD_NVRAM_ADDR 0x48000
957 #define FA_FEATURE_ADDR 0x4C000
958 #define FA_FLASH_DESCR_ADDR 0x50000
959 #define FA_FLASH_LAYOUT_ADDR 0x50400
960 #define FA_HW_EVENT0_ADDR 0x54000
961 #define FA_HW_EVENT1_ADDR 0x54400
962 #define FA_HW_EVENT_SIZE 0x200
963 #define FA_HW_EVENT_ENTRY_SIZE 4
964 #define FA_NPIV_CONF0_ADDR 0x5C000
965 #define FA_NPIV_CONF1_ADDR 0x5D000
966 #define FA_FCP_PRIO0_ADDR 0x10000
967 #define FA_FCP_PRIO1_ADDR 0x12000
970 * Flash Error Log Event Codes.
972 #define HW_EVENT_RESET_ERR 0xF00B
973 #define HW_EVENT_ISP_ERR 0xF020
974 #define HW_EVENT_PARITY_ERR 0xF022
975 #define HW_EVENT_NVRAM_CHKSUM_ERR 0xF023
976 #define HW_EVENT_FLASH_FW_ERR 0xF024
978 uint32_t flash_data; /* Flash/NVRAM BIOS data. */
980 uint32_t ctrl_status; /* Control/Status. */
981 #define CSRX_FLASH_ACCESS_ERROR BIT_18 /* Flash/NVRAM Access Error. */
982 #define CSRX_DMA_ACTIVE BIT_17 /* DMA Active status. */
983 #define CSRX_DMA_SHUTDOWN BIT_16 /* DMA Shutdown control status. */
984 #define CSRX_FUNCTION BIT_15 /* Function number. */
985 /* PCI-X Bus Mode. */
986 #define CSRX_PCIX_BUS_MODE_MASK (BIT_11|BIT_10|BIT_9|BIT_8)
987 #define PBM_PCI_33MHZ (0 << 8)
988 #define PBM_PCIX_M1_66MHZ (1 << 8)
989 #define PBM_PCIX_M1_100MHZ (2 << 8)
990 #define PBM_PCIX_M1_133MHZ (3 << 8)
991 #define PBM_PCIX_M2_66MHZ (5 << 8)
992 #define PBM_PCIX_M2_100MHZ (6 << 8)
993 #define PBM_PCIX_M2_133MHZ (7 << 8)
994 #define PBM_PCI_66MHZ (8 << 8)
995 /* Max Write Burst byte count. */
996 #define CSRX_MAX_WRT_BURST_MASK (BIT_5|BIT_4)
997 #define MWB_512_BYTES (0 << 4)
998 #define MWB_1024_BYTES (1 << 4)
999 #define MWB_2048_BYTES (2 << 4)
1000 #define MWB_4096_BYTES (3 << 4)
1002 #define CSRX_64BIT_SLOT BIT_2 /* PCI 64-Bit Bus Slot. */
1003 #define CSRX_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable. */
1004 #define CSRX_ISP_SOFT_RESET BIT_0 /* ISP soft reset. */
1006 uint32_t ictrl; /* Interrupt control. */
1007 #define ICRX_EN_RISC_INT BIT_3 /* Enable RISC interrupts on PCI. */
1009 uint32_t istatus; /* Interrupt status. */
1010 #define ISRX_RISC_INT BIT_3 /* RISC interrupt. */
1012 uint32_t unused_1[2]; /* Gap. */
1014 /* Request Queue. */
1015 uint32_t req_q_in; /* In-Pointer. */
1016 uint32_t req_q_out; /* Out-Pointer. */
1017 /* Response Queue. */
1018 uint32_t rsp_q_in; /* In-Pointer. */
1019 uint32_t rsp_q_out; /* Out-Pointer. */
1020 /* Priority Request Queue. */
1021 uint32_t preq_q_in; /* In-Pointer. */
1022 uint32_t preq_q_out; /* Out-Pointer. */
1024 uint32_t unused_2[2]; /* Gap. */
1027 uint32_t atio_q_in; /* In-Pointer. */
1028 uint32_t atio_q_out; /* Out-Pointer. */
1030 uint32_t host_status;
1031 #define HSRX_RISC_INT BIT_15 /* RISC to Host interrupt. */
1032 #define HSRX_RISC_PAUSED BIT_8 /* RISC Paused. */
1034 uint32_t hccr; /* Host command & control register. */
1035 /* HCCR statuses. */
1036 #define HCCRX_HOST_INT BIT_6 /* Host to RISC interrupt bit. */
1037 #define HCCRX_RISC_RESET BIT_5 /* RISC Reset mode bit. */
1038 /* HCCR commands. */
1040 #define HCCRX_NOOP 0x00000000
1041 /* Set RISC Reset. */
1042 #define HCCRX_SET_RISC_RESET 0x10000000
1043 /* Clear RISC Reset. */
1044 #define HCCRX_CLR_RISC_RESET 0x20000000
1045 /* Set RISC Pause. */
1046 #define HCCRX_SET_RISC_PAUSE 0x30000000
1047 /* Releases RISC Pause. */
1048 #define HCCRX_REL_RISC_PAUSE 0x40000000
1049 /* Set HOST to RISC interrupt. */
1050 #define HCCRX_SET_HOST_INT 0x50000000
1051 /* Clear HOST to RISC interrupt. */
1052 #define HCCRX_CLR_HOST_INT 0x60000000
1053 /* Clear RISC to PCI interrupt. */
1054 #define HCCRX_CLR_RISC_INT 0xA0000000
1056 uint32_t gpiod; /* GPIO Data register. */
1058 /* LED update mask. */
1059 #define GPDX_LED_UPDATE_MASK (BIT_20|BIT_19|BIT_18)
1060 /* Data update mask. */
1061 #define GPDX_DATA_UPDATE_MASK (BIT_17|BIT_16)
1062 /* Data update mask. */
1063 #define GPDX_DATA_UPDATE_2_MASK (BIT_28|BIT_27|BIT_26|BIT_17|BIT_16)
1064 /* LED control mask. */
1065 #define GPDX_LED_COLOR_MASK (BIT_4|BIT_3|BIT_2)
1066 /* LED bit values. Color names as
1067 * referenced in fw spec.
1069 #define GPDX_LED_YELLOW_ON BIT_2
1070 #define GPDX_LED_GREEN_ON BIT_3
1071 #define GPDX_LED_AMBER_ON BIT_4
1073 #define GPDX_DATA_INOUT (BIT_1|BIT_0)
1075 uint32_t gpioe; /* GPIO Enable register. */
1076 /* Enable update mask. */
1077 #define GPEX_ENABLE_UPDATE_MASK (BIT_17|BIT_16)
1078 /* Enable update mask. */
1079 #define GPEX_ENABLE_UPDATE_2_MASK (BIT_28|BIT_27|BIT_26|BIT_17|BIT_16)
1081 #define GPEX_ENABLE (BIT_1|BIT_0)
1083 uint32_t iobase_addr; /* I/O Bus Base Address register. */
1085 uint32_t unused_3[10]; /* Gap. */
1120 uint32_t iobase_window;
1123 uint32_t unused_4_1[6]; /* Gap. */
1125 uint32_t unused_5[2]; /* Gap. */
1126 uint32_t iobase_select;
1127 uint32_t unused_6[2]; /* Gap. */
1128 uint32_t iobase_sdata;
1130 /* RISC-RISC semaphore register PCI offet */
1131 #define RISC_REGISTER_BASE_OFFSET 0x7010
1132 #define RISC_REGISTER_WINDOW_OFFET 0x6
1134 /* RISC-RISC semaphore/flag register (risc address 0x7016) */
1136 #define RISC_SEMAPHORE 0x1UL
1137 #define RISC_SEMAPHORE_WE (RISC_SEMAPHORE << 16)
1138 #define RISC_SEMAPHORE_CLR (RISC_SEMAPHORE_WE | 0x0UL)
1139 #define RISC_SEMAPHORE_SET (RISC_SEMAPHORE_WE | RISC_SEMAPHORE)
1141 #define RISC_SEMAPHORE_FORCE 0x8000UL
1142 #define RISC_SEMAPHORE_FORCE_WE (RISC_SEMAPHORE_FORCE << 16)
1143 #define RISC_SEMAPHORE_FORCE_CLR (RISC_SEMAPHORE_FORCE_WE | 0x0UL)
1144 #define RISC_SEMAPHORE_FORCE_SET \
1145 (RISC_SEMAPHORE_FORCE_WE | RISC_SEMAPHORE_FORCE)
1147 /* RISC semaphore timeouts (ms) */
1148 #define TIMEOUT_SEMAPHORE 2500
1149 #define TIMEOUT_SEMAPHORE_FORCE 2000
1150 #define TIMEOUT_TOTAL_ELAPSED 4500
1152 /* Trace Control *************************************************************/
1154 #define TC_AEN_DISABLE 0
1156 #define TC_EFT_ENABLE 4
1157 #define TC_EFT_DISABLE 5
1159 #define TC_FCE_ENABLE 8
1160 #define TC_FCE_OPTIONS 0
1161 #define TC_FCE_DEFAULT_RX_SIZE 2112
1162 #define TC_FCE_DEFAULT_TX_SIZE 2112
1163 #define TC_FCE_DISABLE 9
1164 #define TC_FCE_DISABLE_TRACE BIT_0
1166 /* MID Support ***************************************************************/
1168 #define MIN_MULTI_ID_FABRIC 64 /* Must be power-of-2. */
1169 #define MAX_MULTI_ID_FABRIC 256 /* ... */
1171 struct mid_conf_entry_24xx {
1172 uint16_t reserved_1;
1175 * BIT 0 = Enable Hard Loop Id
1176 * BIT 1 = Acquire Loop ID in LIPA
1177 * BIT 2 = ID not Acquired
1179 * BIT 4 = Enable Initiator Mode
1180 * BIT 5 = Disable Target Mode
1181 * BIT 6-7 = Reserved
1185 uint8_t hard_address;
1187 uint8_t port_name[WWN_SIZE];
1188 uint8_t node_name[WWN_SIZE];
1191 struct mid_init_cb_24xx {
1192 struct init_cb_24xx init_cb;
1197 struct mid_conf_entry_24xx entries[MAX_MULTI_ID_FABRIC];
1201 struct mid_db_entry_24xx {
1203 #define MDBS_NON_PARTIC BIT_3
1204 #define MDBS_ID_ACQUIRED BIT_1
1205 #define MDBS_ENABLED BIT_0
1208 uint8_t hard_address;
1210 uint8_t port_name[WWN_SIZE];
1211 uint8_t node_name[WWN_SIZE];
1218 * Virtual Port Control IOCB
1220 #define VP_CTRL_IOCB_TYPE 0x30 /* Virtual Port Control entry. */
1221 struct vp_ctrl_entry_24xx {
1222 uint8_t entry_type; /* Entry type. */
1223 uint8_t entry_count; /* Entry count. */
1224 uint8_t sys_define; /* System defined. */
1225 uint8_t entry_status; /* Entry Status. */
1227 uint32_t handle; /* System handle. */
1229 uint16_t vp_idx_failed;
1231 uint16_t comp_status; /* Completion status. */
1232 #define CS_VCE_IOCB_ERROR 0x01 /* Error processing IOCB */
1233 #define CS_VCE_ACQ_ID_ERROR 0x02 /* Error while acquireing ID. */
1234 #define CS_VCE_BUSY 0x05 /* Firmware not ready to accept cmd. */
1237 #define VCE_COMMAND_ENABLE_VPS 0x00 /* Enable VPs. */
1238 #define VCE_COMMAND_DISABLE_VPS 0x08 /* Disable VPs. */
1239 #define VCE_COMMAND_DISABLE_VPS_REINIT 0x09 /* Disable VPs and reinit link. */
1240 #define VCE_COMMAND_DISABLE_VPS_LOGO 0x0a /* Disable VPs and LOGO ports. */
1241 #define VCE_COMMAND_DISABLE_VPS_LOGO_ALL 0x0b /* Disable VPs and LOGO ports. */
1245 uint8_t vp_idx_map[16];
1248 uint16_t reserved_4;
1250 uint8_t reserved_5[24];
1254 * Modify Virtual Port Configuration IOCB
1256 #define VP_CONFIG_IOCB_TYPE 0x31 /* Virtual Port Config entry. */
1257 struct vp_config_entry_24xx {
1258 uint8_t entry_type; /* Entry type. */
1259 uint8_t entry_count; /* Entry count. */
1260 uint8_t handle_count;
1261 uint8_t entry_status; /* Entry Status. */
1263 uint32_t handle; /* System handle. */
1266 #define CS_VF_BIND_VPORTS_TO_VF BIT_0
1267 #define CS_VF_SET_QOS_OF_VPORTS BIT_1
1268 #define CS_VF_SET_HOPS_OF_VPORTS BIT_2
1270 uint16_t comp_status; /* Completion status. */
1271 #define CS_VCT_STS_ERROR 0x01 /* Specified VPs were not disabled. */
1272 #define CS_VCT_CNT_ERROR 0x02 /* Invalid VP count. */
1273 #define CS_VCT_ERROR 0x03 /* Unknown error. */
1274 #define CS_VCT_IDX_ERROR 0x02 /* Invalid VP index. */
1275 #define CS_VCT_BUSY 0x05 /* Firmware not ready to accept cmd. */
1278 #define VCT_COMMAND_MOD_VPS 0x00 /* Modify VP configurations. */
1279 #define VCT_COMMAND_MOD_ENABLE_VPS 0x01 /* Modify configuration & enable VPs. */
1286 uint8_t options_idx1;
1287 uint8_t hard_address_idx1;
1288 uint16_t reserved_vp1;
1289 uint8_t port_name_idx1[WWN_SIZE];
1290 uint8_t node_name_idx1[WWN_SIZE];
1292 uint8_t options_idx2;
1293 uint8_t hard_address_idx2;
1294 uint16_t reserved_vp2;
1295 uint8_t port_name_idx2[WWN_SIZE];
1296 uint8_t node_name_idx2[WWN_SIZE];
1298 uint16_t reserved_4;
1300 uint8_t reserved_5[2];
1303 #define VP_RPT_ID_IOCB_TYPE 0x32 /* Report ID Acquisition entry. */
1308 VP_STAT_SNS_TO, /* timeout */
1310 VP_STAT_SCR_TO, /* timeout */
1315 VP_FLAGS_CON_FLOOP = 1,
1316 VP_FLAGS_CON_P2P = 2,
1317 VP_FLAGS_CON_FABRIC = 3,
1318 VP_FLAGS_NAME_VALID = BIT_5,
1321 struct vp_rpt_id_entry_24xx {
1322 uint8_t entry_type; /* Entry type. */
1323 uint8_t entry_count; /* Entry count. */
1324 uint8_t sys_define; /* System defined. */
1325 uint8_t entry_status; /* Entry Status. */
1327 uint8_t vp_acquired;
1329 uint8_t vp_idx; /* Format 0=reserved */
1330 uint8_t vp_status; /* Format 0=reserved */
1337 uint8_t vp_idx_map[16];
1338 uint8_t reserved_4[32];
1341 /* format 1 fabric */
1342 uint8_t vpstat1_subcode; /* vp_status=1 subcode */
1347 uint8_t ls_rjt_vendor;
1348 uint8_t ls_rjt_explanation;
1349 uint8_t ls_rjt_reason;
1352 uint8_t port_name[8];
1353 uint8_t node_name[8];
1355 uint8_t reserved_5[6];
1357 struct { /* format 2: N2N direct connect */
1358 uint8_t vpstat1_subcode;
1363 uint8_t ls_rjt_vendor;
1364 uint8_t ls_rjt_explanation;
1365 uint8_t ls_rjt_reason;
1368 uint8_t port_name[8];
1369 uint8_t node_name[8];
1370 uint32_t remote_nport_id;
1371 uint32_t reserved_5;
1376 #define VF_EVFP_IOCB_TYPE 0x26 /* Exchange Virtual Fabric Parameters entry. */
1377 struct vf_evfp_entry_24xx {
1378 uint8_t entry_type; /* Entry type. */
1379 uint8_t entry_count; /* Entry count. */
1380 uint8_t sys_define; /* System defined. */
1381 uint8_t entry_status; /* Entry Status. */
1383 uint32_t handle; /* System handle. */
1384 uint16_t comp_status; /* Completion status. */
1385 uint16_t timeout; /* timeout */
1386 uint16_t adim_tagging_mode;
1391 uint16_t nport_handle; /* N_PORT handle. */
1392 uint16_t control_flags;
1393 uint32_t io_parameter_0;
1394 uint32_t io_parameter_1;
1395 uint32_t tx_address[2]; /* Data segment 0 address. */
1396 uint32_t tx_len; /* Data segment 0 length. */
1397 uint32_t rx_address[2]; /* Data segment 1 address. */
1398 uint32_t rx_len; /* Data segment 1 length. */
1401 /* END MID Support ***********************************************************/
1403 /* Flash Description Table ***************************************************/
1405 struct qla_fdt_layout {
1416 uint8_t alt_erase_cmd;
1417 uint8_t wrt_enable_cmd;
1418 uint8_t wrt_enable_bits;
1419 uint8_t wrt_sts_reg_cmd;
1420 uint8_t unprotect_sec_cmd;
1421 uint8_t read_man_id_cmd;
1422 uint32_t block_size;
1423 uint32_t alt_block_size;
1424 uint32_t flash_size;
1425 uint32_t wrt_enable_data;
1426 uint8_t read_id_addr_len;
1427 uint8_t wrt_disable_bits;
1428 uint8_t read_dev_id_len;
1429 uint8_t chip_erase_cmd;
1430 uint16_t read_timeout;
1431 uint8_t protect_sec_cmd;
1432 uint8_t unused2[65];
1435 /* Flash Layout Table ********************************************************/
1437 struct qla_flt_location {
1446 struct qla_flt_header {
1453 #define FLT_REG_FW 0x01
1454 #define FLT_REG_BOOT_CODE 0x07
1455 #define FLT_REG_VPD_0 0x14
1456 #define FLT_REG_NVRAM_0 0x15
1457 #define FLT_REG_VPD_1 0x16
1458 #define FLT_REG_NVRAM_1 0x17
1459 #define FLT_REG_VPD_2 0xD4
1460 #define FLT_REG_NVRAM_2 0xD5
1461 #define FLT_REG_VPD_3 0xD6
1462 #define FLT_REG_NVRAM_3 0xD7
1463 #define FLT_REG_FDT 0x1a
1464 #define FLT_REG_FLT 0x1c
1465 #define FLT_REG_HW_EVENT_0 0x1d
1466 #define FLT_REG_HW_EVENT_1 0x1f
1467 #define FLT_REG_NPIV_CONF_0 0x29
1468 #define FLT_REG_NPIV_CONF_1 0x2a
1469 #define FLT_REG_GOLD_FW 0x2f
1470 #define FLT_REG_FCP_PRIO_0 0x87
1471 #define FLT_REG_FCP_PRIO_1 0x88
1472 #define FLT_REG_CNA_FW 0x97
1473 #define FLT_REG_BOOT_CODE_8044 0xA2
1474 #define FLT_REG_FCOE_FW 0xA4
1475 #define FLT_REG_FCOE_NVRAM_0 0xAA
1476 #define FLT_REG_FCOE_NVRAM_1 0xAC
1479 #define FLT_REG_IMG_PRI_27XX 0x95
1480 #define FLT_REG_IMG_SEC_27XX 0x96
1481 #define FLT_REG_FW_SEC_27XX 0x02
1482 #define FLT_REG_BOOTLOAD_SEC_27XX 0x9
1483 #define FLT_REG_VPD_SEC_27XX_0 0x50
1484 #define FLT_REG_VPD_SEC_27XX_1 0x52
1485 #define FLT_REG_VPD_SEC_27XX_2 0xD8
1486 #define FLT_REG_VPD_SEC_27XX_3 0xDA
1488 struct qla_flt_region {
1495 /* Flash NPIV Configuration Table ********************************************/
1497 struct qla_npiv_header {
1505 struct qla_npiv_entry {
1511 uint8_t port_name[WWN_SIZE];
1512 uint8_t node_name[WWN_SIZE];
1515 /* 84XX Support **************************************************************/
1517 #define MBA_ISP84XX_ALERT 0x800f /* Alert Notification. */
1518 #define A84_PANIC_RECOVERY 0x1
1519 #define A84_OP_LOGIN_COMPLETE 0x2
1520 #define A84_DIAG_LOGIN_COMPLETE 0x3
1521 #define A84_GOLD_LOGIN_COMPLETE 0x4
1523 #define MBC_ISP84XX_RESET 0x3a /* Reset. */
1525 #define FSTATE_REMOTE_FC_DOWN BIT_0
1526 #define FSTATE_NSL_LINK_DOWN BIT_1
1527 #define FSTATE_IS_DIAG_FW BIT_2
1528 #define FSTATE_LOGGED_IN BIT_3
1529 #define FSTATE_WAITING_FOR_VERIFY BIT_4
1531 #define VERIFY_CHIP_IOCB_TYPE 0x1B
1532 struct verify_chip_entry_84xx {
1534 uint8_t entry_count;
1535 uint8_t sys_defined;
1536 uint8_t entry_status;
1541 #define VCO_DONT_UPDATE_FW BIT_0
1542 #define VCO_FORCE_UPDATE BIT_1
1543 #define VCO_DONT_RESET_UPDATE BIT_2
1544 #define VCO_DIAG_FW BIT_3
1545 #define VCO_END_OF_DATA BIT_14
1546 #define VCO_ENABLE_DSD BIT_15
1548 uint16_t reserved_1;
1550 uint16_t data_seg_cnt;
1551 uint16_t reserved_2[3];
1554 uint32_t exchange_address;
1556 uint32_t reserved_3[3];
1558 uint32_t fw_seq_size;
1559 uint32_t relative_offset;
1561 uint32_t dseg_address[2];
1562 uint32_t dseg_length;
1565 struct verify_chip_rsp_84xx {
1567 uint8_t entry_count;
1568 uint8_t sys_defined;
1569 uint8_t entry_status;
1573 uint16_t comp_status;
1574 #define CS_VCS_CHIP_FAILURE 0x3
1575 #define CS_VCS_BAD_EXCHANGE 0x8
1576 #define CS_VCS_SEQ_COMPLETEi 0x40
1578 uint16_t failure_code;
1579 #define VFC_CHECKSUM_ERROR 0x1
1580 #define VFC_INVALID_LEN 0x2
1581 #define VFC_ALREADY_IN_PROGRESS 0x8
1583 uint16_t reserved_1[4];
1586 uint32_t exchange_address;
1588 uint32_t reserved_2[6];
1591 #define ACCESS_CHIP_IOCB_TYPE 0x2B
1592 struct access_chip_84xx {
1594 uint8_t entry_count;
1595 uint8_t sys_defined;
1596 uint8_t entry_status;
1601 #define ACO_DUMP_MEMORY 0x0
1602 #define ACO_LOAD_MEMORY 0x1
1603 #define ACO_CHANGE_CONFIG_PARAM 0x2
1604 #define ACO_REQUEST_INFO 0x3
1608 uint16_t dseg_count;
1609 uint16_t reserved2[3];
1611 uint32_t parameter1;
1612 uint32_t parameter2;
1613 uint32_t parameter3;
1615 uint32_t reserved3[3];
1616 uint32_t total_byte_cnt;
1619 uint32_t dseg_address[2];
1620 uint32_t dseg_length;
1623 struct access_chip_rsp_84xx {
1625 uint8_t entry_count;
1626 uint8_t sys_defined;
1627 uint8_t entry_status;
1631 uint16_t comp_status;
1632 uint16_t failure_code;
1633 uint32_t residual_count;
1635 uint32_t reserved[12];
1638 /* 81XX Support **************************************************************/
1640 #define MBA_DCBX_START 0x8016
1641 #define MBA_DCBX_COMPLETE 0x8030
1642 #define MBA_FCF_CONF_ERR 0x8031
1643 #define MBA_DCBX_PARAM_UPDATE 0x8032
1644 #define MBA_IDC_COMPLETE 0x8100
1645 #define MBA_IDC_NOTIFY 0x8101
1646 #define MBA_IDC_TIME_EXT 0x8102
1648 #define MBC_IDC_ACK 0x101
1649 #define MBC_RESTART_MPI_FW 0x3d
1650 #define MBC_FLASH_ACCESS_CTRL 0x3e /* Control flash access. */
1651 #define MBC_GET_XGMAC_STATS 0x7a
1652 #define MBC_GET_DCBX_PARAMS 0x51
1655 * ISP83xx mailbox commands
1657 #define MBC_WRITE_REMOTE_REG 0x0001 /* Write remote register */
1658 #define MBC_READ_REMOTE_REG 0x0009 /* Read remote register */
1659 #define MBC_RESTART_NIC_FIRMWARE 0x003d /* Restart NIC firmware */
1660 #define MBC_SET_ACCESS_CONTROL 0x003e /* Access control command */
1662 /* Flash access control option field bit definitions */
1663 #define FAC_OPT_FORCE_SEMAPHORE BIT_15
1664 #define FAC_OPT_REQUESTOR_ID BIT_14
1665 #define FAC_OPT_CMD_SUBCODE 0xff
1667 /* Flash access control command subcodes */
1668 #define FAC_OPT_CMD_WRITE_PROTECT 0x00
1669 #define FAC_OPT_CMD_WRITE_ENABLE 0x01
1670 #define FAC_OPT_CMD_ERASE_SECTOR 0x02
1671 #define FAC_OPT_CMD_LOCK_SEMAPHORE 0x03
1672 #define FAC_OPT_CMD_UNLOCK_SEMAPHORE 0x04
1673 #define FAC_OPT_CMD_GET_SECTOR_SIZE 0x05
1678 uint16_t nvram_version;
1679 uint16_t reserved_0;
1681 /* Firmware Initialization Control Block. */
1683 uint16_t reserved_1;
1684 uint16_t frame_payload_size;
1685 uint16_t execution_throttle;
1686 uint16_t exchange_count;
1687 uint16_t reserved_2;
1689 uint8_t port_name[WWN_SIZE];
1690 uint8_t node_name[WWN_SIZE];
1692 uint16_t login_retry_count;
1693 uint16_t reserved_3;
1694 uint16_t interrupt_delay_timer;
1695 uint16_t login_timeout;
1697 uint32_t firmware_options_1;
1698 uint32_t firmware_options_2;
1699 uint32_t firmware_options_3;
1701 uint16_t reserved_4[4];
1704 uint8_t enode_mac[6];
1705 uint16_t reserved_5[5];
1708 uint16_t reserved_6[24];
1711 uint16_t ex_version;
1712 uint8_t prio_fcf_matching_flags;
1713 uint8_t reserved_6_1[3];
1714 uint16_t pri_fcf_vlan_id;
1715 uint8_t pri_fcf_fabric_name[8];
1716 uint16_t reserved_6_2[7];
1717 uint8_t spma_mac_addr[6];
1718 uint16_t reserved_6_3[14];
1721 uint16_t reserved_7[32];
1724 * BIT 0 = Enable spinup delay
1725 * BIT 1 = Disable BIOS
1726 * BIT 2 = Enable Memory Map BIOS
1727 * BIT 3 = Enable Selectable Boot
1728 * BIT 4 = Disable RISC code load
1729 * BIT 5 = Disable Serdes
1730 * BIT 6 = Opt boot mode
1731 * BIT 7 = Interrupt enable
1733 * BIT 8 = EV Control enable
1734 * BIT 9 = Enable lip reset
1735 * BIT 10 = Enable lip full login
1736 * BIT 11 = Enable target reset
1737 * BIT 12 = Stop firmware
1738 * BIT 13 = Enable nodename option
1739 * BIT 14 = Default WWPN valid
1740 * BIT 15 = Enable alternate WWN
1742 * BIT 16 = CLP LUN string
1743 * BIT 17 = CLP Target string
1744 * BIT 18 = CLP BIOS enable string
1745 * BIT 19 = CLP Serdes string
1746 * BIT 20 = CLP WWPN string
1747 * BIT 21 = CLP WWNN string
1750 * BIT 24 = Keep WWPN
1751 * BIT 25 = Temp WWPN
1756 uint8_t alternate_port_name[WWN_SIZE];
1757 uint8_t alternate_node_name[WWN_SIZE];
1759 uint8_t boot_port_name[WWN_SIZE];
1760 uint16_t boot_lun_number;
1761 uint16_t reserved_8;
1763 uint8_t alt1_boot_port_name[WWN_SIZE];
1764 uint16_t alt1_boot_lun_number;
1765 uint16_t reserved_9;
1767 uint8_t alt2_boot_port_name[WWN_SIZE];
1768 uint16_t alt2_boot_lun_number;
1769 uint16_t reserved_10;
1771 uint8_t alt3_boot_port_name[WWN_SIZE];
1772 uint16_t alt3_boot_lun_number;
1773 uint16_t reserved_11;
1776 * BIT 0 = Selective Login
1777 * BIT 1 = Alt-Boot Enable
1779 * BIT 3 = Boot Order List
1781 * BIT 5 = Selective LUN
1785 uint32_t efi_parameters;
1787 uint8_t reset_delay;
1788 uint8_t reserved_12;
1789 uint16_t reserved_13;
1791 uint16_t boot_id_number;
1792 uint16_t reserved_14;
1794 uint16_t max_luns_per_target;
1795 uint16_t reserved_15;
1797 uint16_t port_down_retry_count;
1798 uint16_t link_down_timeout;
1800 /* FCode parameters. */
1801 uint16_t fcode_parameter;
1803 uint16_t reserved_16[3];
1806 uint8_t reserved_17[4];
1807 uint16_t reserved_18[5];
1808 uint8_t reserved_19[2];
1809 uint16_t reserved_20[8];
1812 uint8_t reserved_21[16];
1813 uint16_t reserved_22[3];
1816 * BIT 0 = Extended BB credits for LR
1817 * BIT 1 = Virtual Fabric Enable
1818 * BIT 2 = Enhanced Features Unused
1819 * BIT 3-7 = Enhanced Features Reserved
1821 /* Enhanced Features */
1822 uint8_t enhanced_features;
1824 uint8_t reserved_23;
1825 uint16_t reserved_24[4];
1828 uint16_t reserved_25[32];
1831 uint8_t model_name[16];
1834 uint16_t feature_mask_l;
1835 uint16_t feature_mask_h;
1836 uint16_t reserved_26[2];
1838 uint16_t subsystem_vendor_id;
1839 uint16_t subsystem_device_id;
1845 * ISP Initialization Control Block.
1846 * Little endian except where noted.
1848 #define ICB_VERSION 1
1849 struct init_cb_81xx {
1851 uint16_t reserved_1;
1853 uint16_t frame_payload_size;
1854 uint16_t execution_throttle;
1855 uint16_t exchange_count;
1857 uint16_t reserved_2;
1859 uint8_t port_name[WWN_SIZE]; /* Big endian. */
1860 uint8_t node_name[WWN_SIZE]; /* Big endian. */
1862 uint16_t response_q_inpointer;
1863 uint16_t request_q_outpointer;
1865 uint16_t login_retry_count;
1867 uint16_t prio_request_q_outpointer;
1869 uint16_t response_q_length;
1870 uint16_t request_q_length;
1872 uint16_t reserved_3;
1874 uint16_t prio_request_q_length;
1876 uint32_t request_q_address[2];
1877 uint32_t response_q_address[2];
1878 uint32_t prio_request_q_address[2];
1880 uint8_t reserved_4[8];
1882 uint16_t atio_q_inpointer;
1883 uint16_t atio_q_length;
1884 uint32_t atio_q_address[2];
1886 uint16_t interrupt_delay_timer; /* 100us increments. */
1887 uint16_t login_timeout;
1890 * BIT 0-3 = Reserved
1891 * BIT 4 = Enable Target Mode
1892 * BIT 5 = Disable Initiator Mode
1896 * BIT 8-13 = Reserved
1897 * BIT 14 = Node Name Option
1898 * BIT 15-31 = Reserved
1900 uint32_t firmware_options_1;
1903 * BIT 0 = Operation Mode bit 0
1904 * BIT 1 = Operation Mode bit 1
1905 * BIT 2 = Operation Mode bit 2
1906 * BIT 3 = Operation Mode bit 3
1907 * BIT 4-7 = Reserved
1909 * BIT 8 = Enable Class 2
1910 * BIT 9 = Enable ACK0
1912 * BIT 11 = Enable FC-SP Security
1913 * BIT 12 = FC Tape Enable
1915 * BIT 14 = Enable Target PRLI Control
1916 * BIT 15-31 = Reserved
1918 uint32_t firmware_options_2;
1921 * BIT 0-3 = Reserved
1922 * BIT 4 = FCP RSP Payload bit 0
1923 * BIT 5 = FCP RSP Payload bit 1
1924 * BIT 6 = Enable Receive Out-of-Order data frame handling
1928 * BIT 9 = Enable Out-of-Order FCP_XFER_RDY relative offset handling
1929 * BIT 10-16 = Reserved
1930 * BIT 17 = Enable multiple FCFs
1931 * BIT 18-20 = MAC addressing mode
1932 * BIT 21-25 = Ethernet data rate
1933 * BIT 26 = Enable ethernet header rx IOCB for ATIO q
1934 * BIT 27 = Enable ethernet header rx IOCB for response q
1935 * BIT 28 = SPMA selection bit 0
1936 * BIT 28 = SPMA selection bit 1
1937 * BIT 30-31 = Reserved
1939 uint32_t firmware_options_3;
1941 uint8_t reserved_5[8];
1943 uint8_t enode_mac[6];
1945 uint8_t reserved_6[10];
1948 struct mid_init_cb_81xx {
1949 struct init_cb_81xx init_cb;
1954 struct mid_conf_entry_24xx entries[MAX_MULTI_ID_FABRIC];
1957 struct ex_init_cb_81xx {
1958 uint16_t ex_version;
1959 uint8_t prio_fcf_matching_flags;
1960 uint8_t reserved_1[3];
1961 uint16_t pri_fcf_vlan_id;
1962 uint8_t pri_fcf_fabric_name[8];
1963 uint16_t reserved_2[7];
1964 uint8_t spma_mac_addr[6];
1965 uint16_t reserved_3[14];
1968 #define FARX_ACCESS_FLASH_CONF_81XX 0x7FFD0000
1969 #define FARX_ACCESS_FLASH_DATA_81XX 0x7F800000
1971 /* FCP priority config defines *************************************/
1973 #define QLFC_FCP_PRIO_DISABLE 0x0
1974 #define QLFC_FCP_PRIO_ENABLE 0x1
1975 #define QLFC_FCP_PRIO_GET_CONFIG 0x2
1976 #define QLFC_FCP_PRIO_SET_CONFIG 0x3
1978 struct qla_fcp_prio_entry {
1979 uint16_t flags; /* Describes parameter(s) in FCP */
1980 /* priority entry that are valid */
1981 #define FCP_PRIO_ENTRY_VALID 0x1
1982 #define FCP_PRIO_ENTRY_TAG_VALID 0x2
1983 #define FCP_PRIO_ENTRY_SPID_VALID 0x4
1984 #define FCP_PRIO_ENTRY_DPID_VALID 0x8
1985 #define FCP_PRIO_ENTRY_LUNB_VALID 0x10
1986 #define FCP_PRIO_ENTRY_LUNE_VALID 0x20
1987 #define FCP_PRIO_ENTRY_SWWN_VALID 0x40
1988 #define FCP_PRIO_ENTRY_DWWN_VALID 0x80
1989 uint8_t tag; /* Priority value */
1990 uint8_t reserved; /* Reserved for future use */
1991 uint32_t src_pid; /* Src port id. high order byte */
1992 /* unused; -1 (wild card) */
1993 uint32_t dst_pid; /* Src port id. high order byte */
1994 /* unused; -1 (wild card) */
1995 uint16_t lun_beg; /* 1st lun num of lun range. */
1996 /* -1 (wild card) */
1997 uint16_t lun_end; /* 2nd lun num of lun range. */
1998 /* -1 (wild card) */
1999 uint8_t src_wwpn[8]; /* Source WWPN: -1 (wild card) */
2000 uint8_t dst_wwpn[8]; /* Destination WWPN: -1 (wild card) */
2003 struct qla_fcp_prio_cfg {
2004 uint8_t signature[4]; /* "HQOS" signature of config data */
2005 uint16_t version; /* 1: Initial version */
2006 uint16_t length; /* config data size in num bytes */
2007 uint16_t checksum; /* config data bytes checksum */
2008 uint16_t num_entries; /* Number of entries */
2009 uint16_t size_of_entry; /* Size of each entry in num bytes */
2010 uint8_t attributes; /* enable/disable, persistence */
2011 #define FCP_PRIO_ATTR_DISABLE 0x0
2012 #define FCP_PRIO_ATTR_ENABLE 0x1
2013 #define FCP_PRIO_ATTR_PERSIST 0x2
2014 uint8_t reserved; /* Reserved for future use */
2015 #define FCP_PRIO_CFG_HDR_SIZE 0x10
2016 struct qla_fcp_prio_entry entry[1]; /* fcp priority entries */
2017 #define FCP_PRIO_CFG_ENTRY_SIZE 0x20
2020 #define FCP_PRIO_CFG_SIZE (32*1024) /* fcp prio data per port*/
2022 /* 25XX Support ****************************************************/
2023 #define FA_FCP_PRIO0_ADDR_25 0x3C000
2024 #define FA_FCP_PRIO1_ADDR_25 0x3E000
2026 /* 81XX Flash locations -- occupies second 2MB region. */
2027 #define FA_BOOT_CODE_ADDR_81 0x80000
2028 #define FA_RISC_CODE_ADDR_81 0xA0000
2029 #define FA_FW_AREA_ADDR_81 0xC0000
2030 #define FA_VPD_NVRAM_ADDR_81 0xD0000
2031 #define FA_VPD0_ADDR_81 0xD0000
2032 #define FA_VPD1_ADDR_81 0xD0400
2033 #define FA_NVRAM0_ADDR_81 0xD0080
2034 #define FA_NVRAM1_ADDR_81 0xD0180
2035 #define FA_FEATURE_ADDR_81 0xD4000
2036 #define FA_FLASH_DESCR_ADDR_81 0xD8000
2037 #define FA_FLASH_LAYOUT_ADDR_81 0xD8400
2038 #define FA_HW_EVENT0_ADDR_81 0xDC000
2039 #define FA_HW_EVENT1_ADDR_81 0xDC400
2040 #define FA_NPIV_CONF0_ADDR_81 0xD1000
2041 #define FA_NPIV_CONF1_ADDR_81 0xD2000
2043 /* 83XX Flash locations -- occupies second 8MB region. */
2044 #define FA_FLASH_LAYOUT_ADDR_83 0xFC400