2 * QLogic iSCSI HBA Driver
3 * Copyright (c) 2003-2006 QLogic Corporation
5 * See LICENSE.qla4xxx for copyright and licensing details.
12 #define MAX_PRST_DEV_DB_ENTRIES 64
13 #define MIN_DISC_DEV_DB_ENTRY MAX_PRST_DEV_DB_ENTRIES
14 #define MAX_DEV_DB_ENTRIES 512
16 /*************************************************************************
18 * ISP 4010 I/O Register Set Structure and Definitions
20 *************************************************************************/
22 struct port_ctrl_stat_regs {
23 __le32 ext_hw_conf; /* 0x50 R/W */
24 __le32 rsrvd0; /* 0x54 */
25 __le32 port_ctrl; /* 0x58 */
26 __le32 port_status; /* 0x5c */
27 __le32 rsrvd1[32]; /* 0x60-0xdf */
28 __le32 gp_out; /* 0xe0 */
29 __le32 gp_in; /* 0xe4 */
30 __le32 rsrvd2[5]; /* 0xe8-0xfb */
31 __le32 port_err_status; /* 0xfc */
34 struct host_mem_cfg_regs {
35 __le32 rsrvd0[12]; /* 0x50-0x79 */
36 __le32 req_q_out; /* 0x80 */
37 __le32 rsrvd1[31]; /* 0x84-0xFF */
41 * ISP 82xx I/O Register Set structure definitions.
43 struct device_reg_82xx {
44 __le32 req_q_out; /* 0x0000 (R): Request Queue out-Pointer. */
45 __le32 reserve1[63]; /* Request Queue out-Pointer. (64 * 4) */
46 __le32 rsp_q_in; /* 0x0100 (R/W): Response Queue In-Pointer. */
47 __le32 reserve2[63]; /* Response Queue In-Pointer. */
48 __le32 rsp_q_out; /* 0x0200 (R/W): Response Queue Out-Pointer. */
49 __le32 reserve3[63]; /* Response Queue Out-Pointer. */
51 __le32 mailbox_in[8]; /* 0x0300 (R/W): Mail box In registers */
53 __le32 hint; /* 0x0380 (R/W): Host interrupt register */
54 #define HINT_MBX_INT_PENDING BIT_0
56 __le32 mailbox_out[8]; /* 0x0400 (R): Mail box Out registers */
59 __le32 host_status; /* Offset 0x500 (R): host status */
60 #define HSRX_RISC_MB_INT BIT_0 /* RISC to Host Mailbox interrupt */
61 #define HSRX_RISC_IOCB_INT BIT_1 /* RISC to Host IOCB interrupt */
63 __le32 host_int; /* Offset 0x0504 (R/W): Interrupt status. */
64 #define ISRX_82XX_RISC_INT BIT_0 /* RISC interrupt. */
67 /* remote register set (access via PCI memory read/write) */
69 #define MBOX_REG_COUNT 8
70 __le32 mailbox[MBOX_REG_COUNT];
72 __le32 flash_address; /* 0x20 */
79 __le32 reserved1[2]; /* 0x30 */
80 } __attribute__ ((packed)) isp4010;
83 __le32 nvram; /* 0x30 */
85 } __attribute__ ((packed)) isp4022;
88 __le32 req_q_in; /* SCSI Request Queue Producer Index */
89 __le32 rsp_q_out; /* SCSI Completion Queue Consumer Index */
91 __le32 reserved2[4]; /* 0x40 */
95 __le32 ext_hw_conf; /* 0x50 */
100 __le32 reserved3[8]; /* 0x60 */
102 __le32 req_q_out; /* 0x80 */
104 __le32 reserved4[23]; /* 0x84 */
106 __le32 gp_out; /* 0xe0 */
111 __le32 port_err_status; /* 0xfc */
112 } __attribute__ ((packed)) isp4010;
115 struct port_ctrl_stat_regs p0;
116 struct host_mem_cfg_regs p1;
118 } __attribute__ ((packed)) isp4022;
123 /* Semaphore Defines for 4010 */
124 #define QL4010_DRVR_SEM_BITS 0x00000030
125 #define QL4010_GPIO_SEM_BITS 0x000000c0
126 #define QL4010_SDRAM_SEM_BITS 0x00000300
127 #define QL4010_PHY_SEM_BITS 0x00000c00
128 #define QL4010_NVRAM_SEM_BITS 0x00003000
129 #define QL4010_FLASH_SEM_BITS 0x0000c000
131 #define QL4010_DRVR_SEM_MASK 0x00300000
132 #define QL4010_GPIO_SEM_MASK 0x00c00000
133 #define QL4010_SDRAM_SEM_MASK 0x03000000
134 #define QL4010_PHY_SEM_MASK 0x0c000000
135 #define QL4010_NVRAM_SEM_MASK 0x30000000
136 #define QL4010_FLASH_SEM_MASK 0xc0000000
138 /* Semaphore Defines for 4022 */
139 #define QL4022_RESOURCE_MASK_BASE_CODE 0x7
140 #define QL4022_RESOURCE_BITS_BASE_CODE 0x4
143 #define QL4022_DRVR_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (1+16))
144 #define QL4022_DDR_RAM_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (4+16))
145 #define QL4022_PHY_GIO_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (7+16))
146 #define QL4022_NVRAM_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (10+16))
147 #define QL4022_FLASH_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (13+16))
151 /* Page # defines for 4022 */
152 #define PORT_CTRL_STAT_PAGE 0 /* 4022 */
153 #define HOST_MEM_CFG_PAGE 1 /* 4022 */
154 #define LOCAL_RAM_CFG_PAGE 2 /* 4022 */
155 #define PROT_STAT_PAGE 3 /* 4022 */
157 /* Register Mask - sets corresponding mask bits in the upper word */
158 static inline uint32_t set_rmask(uint32_t val)
160 return (val & 0xffff) | (val << 16);
164 static inline uint32_t clr_rmask(uint32_t val)
166 return 0 | (val << 16);
169 /* ctrl_status definitions */
170 #define CSR_SCSI_PAGE_SELECT 0x00000003
171 #define CSR_SCSI_INTR_ENABLE 0x00000004 /* 4010 */
172 #define CSR_SCSI_RESET_INTR 0x00000008
173 #define CSR_SCSI_COMPLETION_INTR 0x00000010
174 #define CSR_SCSI_PROCESSOR_INTR 0x00000020
175 #define CSR_INTR_RISC 0x00000040
176 #define CSR_BOOT_ENABLE 0x00000080
177 #define CSR_NET_PAGE_SELECT 0x00000300 /* 4010 */
178 #define CSR_FUNC_NUM 0x00000700 /* 4022 */
179 #define CSR_NET_RESET_INTR 0x00000800 /* 4010 */
180 #define CSR_FORCE_SOFT_RESET 0x00002000 /* 4022 */
181 #define CSR_FATAL_ERROR 0x00004000
182 #define CSR_SOFT_RESET 0x00008000
183 #define ISP_CONTROL_FN_MASK CSR_FUNC_NUM
184 #define ISP_CONTROL_FN0_SCSI 0x0500
185 #define ISP_CONTROL_FN1_SCSI 0x0700
187 #define INTR_PENDING (CSR_SCSI_COMPLETION_INTR |\
188 CSR_SCSI_PROCESSOR_INTR |\
191 /* ISP InterruptMask definitions */
192 #define IMR_SCSI_INTR_ENABLE 0x00000004 /* 4022 */
194 /* ISP 4022 nvram definitions */
195 #define NVR_WRITE_ENABLE 0x00000010 /* 4022 */
197 /* ISP port_status definitions */
199 /* ISP Semaphore definitions */
201 /* ISP General Purpose Output definitions */
202 #define GPOR_TOPCAT_RESET 0x00000004
204 /* shadow registers (DMA'd from HA to system memory. read only) */
206 /* SCSI Request Queue Consumer Index */
207 __le32 req_q_out; /* 0 x0 R */
209 /* SCSI Completion Queue Producer Index */
210 __le32 rsp_q_in; /* 4 x4 R */
214 /* External hardware configuration register */
215 union external_hw_config_reg {
217 /* FIXME: Do we even need this? All values are
218 * referred to by 16 bit quantities. Platform and
219 * endianess issues. */
221 __le32 bSDRAMProtectionMethod:2;
222 __le32 bSDRAMBanks:1;
223 __le32 bSDRAMChipWidth:1;
224 __le32 bSDRAMChipSize:2;
225 __le32 bParityDisable:1;
226 __le32 bExternalMemoryType:1;
227 __le32 bFlashBIOSWriteEnable:1;
228 __le32 bFlashUpperBankSelect:1;
229 __le32 bWriteBurst:2;
236 /* 82XX Support start */
237 /* 82xx Default FLT Addresses */
238 #define FA_FLASH_LAYOUT_ADDR_82 0xFC400
239 #define FA_FLASH_DESCR_ADDR_82 0xFC000
240 #define FA_BOOT_LOAD_ADDR_82 0x04000
241 #define FA_BOOT_CODE_ADDR_82 0x20000
242 #define FA_RISC_CODE_ADDR_82 0x40000
243 #define FA_GOLD_RISC_CODE_ADDR_82 0x80000
245 /* Flash Description Table */
246 struct qla_fdt_layout {
257 uint8_t alt_erase_cmd;
258 uint8_t wrt_enable_cmd;
259 uint8_t wrt_enable_bits;
260 uint8_t wrt_sts_reg_cmd;
261 uint8_t unprotect_sec_cmd;
262 uint8_t read_man_id_cmd;
264 uint32_t alt_block_size;
266 uint32_t wrt_enable_data;
267 uint8_t read_id_addr_len;
268 uint8_t wrt_disable_bits;
269 uint8_t read_dev_id_len;
270 uint8_t chip_erase_cmd;
271 uint16_t read_timeout;
272 uint8_t protect_sec_cmd;
276 /* Flash Layout Table */
278 struct qla_flt_location {
287 struct qla_flt_header {
294 /* 82xx FLT Regions */
295 #define FLT_REG_FDT 0x1a
296 #define FLT_REG_FLT 0x1c
297 #define FLT_REG_BOOTLOAD_82 0x72
298 #define FLT_REG_FW_82 0x74
299 #define FLT_REG_GOLD_FW_82 0x75
300 #define FLT_REG_BOOT_CODE_82 0x78
302 struct qla_flt_region {
309 /*************************************************************************
311 * Mailbox Commands Structures and Definitions
313 *************************************************************************/
315 /* Mailbox command definitions */
316 #define MBOX_CMD_ABOUT_FW 0x0009
317 #define MBOX_CMD_PING 0x000B
318 #define MBOX_CMD_ENABLE_INTRS 0x0010
319 #define INTR_DISABLE 0
320 #define INTR_ENABLE 1
321 #define MBOX_CMD_STOP_FW 0x0014
322 #define MBOX_CMD_ABORT_TASK 0x0015
323 #define MBOX_CMD_LUN_RESET 0x0016
324 #define MBOX_CMD_TARGET_WARM_RESET 0x0017
325 #define MBOX_CMD_GET_MANAGEMENT_DATA 0x001E
326 #define MBOX_CMD_GET_FW_STATUS 0x001F
327 #define MBOX_CMD_SET_ISNS_SERVICE 0x0021
328 #define ISNS_DISABLE 0
329 #define ISNS_ENABLE 1
330 #define MBOX_CMD_COPY_FLASH 0x0024
331 #define MBOX_CMD_WRITE_FLASH 0x0025
332 #define MBOX_CMD_READ_FLASH 0x0026
333 #define MBOX_CMD_CLEAR_DATABASE_ENTRY 0x0031
334 #define MBOX_CMD_CONN_CLOSE_SESS_LOGOUT 0x0056
335 #define LOGOUT_OPTION_CLOSE_SESSION 0x01
336 #define LOGOUT_OPTION_RELOGIN 0x02
337 #define MBOX_CMD_EXECUTE_IOCB_A64 0x005A
338 #define MBOX_CMD_INITIALIZE_FIRMWARE 0x0060
339 #define MBOX_CMD_GET_INIT_FW_CTRL_BLOCK 0x0061
340 #define MBOX_CMD_REQUEST_DATABASE_ENTRY 0x0062
341 #define MBOX_CMD_SET_DATABASE_ENTRY 0x0063
342 #define MBOX_CMD_GET_DATABASE_ENTRY 0x0064
343 #define DDB_DS_UNASSIGNED 0x00
344 #define DDB_DS_NO_CONNECTION_ACTIVE 0x01
345 #define DDB_DS_SESSION_ACTIVE 0x04
346 #define DDB_DS_SESSION_FAILED 0x06
347 #define DDB_DS_LOGIN_IN_PROCESS 0x07
348 #define MBOX_CMD_GET_FW_STATE 0x0069
349 #define MBOX_CMD_GET_INIT_FW_CTRL_BLOCK_DEFAULTS 0x006A
350 #define MBOX_CMD_GET_SYS_INFO 0x0078
351 #define MBOX_CMD_RESTORE_FACTORY_DEFAULTS 0x0087
352 #define MBOX_CMD_SET_ACB 0x0088
353 #define MBOX_CMD_GET_ACB 0x0089
354 #define MBOX_CMD_DISABLE_ACB 0x008A
355 #define MBOX_CMD_GET_IPV6_NEIGHBOR_CACHE 0x008B
356 #define MBOX_CMD_GET_IPV6_DEST_CACHE 0x008C
357 #define MBOX_CMD_GET_IPV6_DEF_ROUTER_LIST 0x008D
358 #define MBOX_CMD_GET_IPV6_LCL_PREFIX_LIST 0x008E
359 #define MBOX_CMD_SET_IPV6_NEIGHBOR_CACHE 0x0090
360 #define MBOX_CMD_GET_IP_ADDR_STATE 0x0091
361 #define MBOX_CMD_SEND_IPV6_ROUTER_SOL 0x0092
362 #define MBOX_CMD_GET_DB_ENTRY_CURRENT_IP_ADDR 0x0093
365 #define FW_STATE_READY 0x0000
366 #define FW_STATE_CONFIG_WAIT 0x0001
367 #define FW_STATE_WAIT_AUTOCONNECT 0x0002
368 #define FW_STATE_ERROR 0x0004
369 #define FW_STATE_CONFIGURING_IP 0x0008
372 #define FW_ADDSTATE_OPTICAL_MEDIA 0x0001
373 #define FW_ADDSTATE_DHCPv4_ENABLED 0x0002
374 #define FW_ADDSTATE_DHCPv4_LEASE_ACQUIRED 0x0004
375 #define FW_ADDSTATE_DHCPv4_LEASE_EXPIRED 0x0008
376 #define FW_ADDSTATE_LINK_UP 0x0010
377 #define FW_ADDSTATE_ISNS_SVC_ENABLED 0x0020
378 #define MBOX_CMD_GET_DATABASE_ENTRY_DEFAULTS 0x006B
379 #define MBOX_CMD_CONN_OPEN_SESS_LOGIN 0x0074
380 #define MBOX_CMD_GET_CRASH_RECORD 0x0076 /* 4010 only */
381 #define MBOX_CMD_GET_CONN_EVENT_LOG 0x0077
383 /* Mailbox status definitions */
384 #define MBOX_COMPLETION_STATUS 4
385 #define MBOX_STS_BUSY 0x0007
386 #define MBOX_STS_INTERMEDIATE_COMPLETION 0x1000
387 #define MBOX_STS_COMMAND_COMPLETE 0x4000
388 #define MBOX_STS_COMMAND_ERROR 0x4005
390 #define MBOX_ASYNC_EVENT_STATUS 8
391 #define MBOX_ASTS_SYSTEM_ERROR 0x8002
392 #define MBOX_ASTS_REQUEST_TRANSFER_ERROR 0x8003
393 #define MBOX_ASTS_RESPONSE_TRANSFER_ERROR 0x8004
394 #define MBOX_ASTS_PROTOCOL_STATISTIC_ALARM 0x8005
395 #define MBOX_ASTS_SCSI_COMMAND_PDU_REJECTED 0x8006
396 #define MBOX_ASTS_LINK_UP 0x8010
397 #define MBOX_ASTS_LINK_DOWN 0x8011
398 #define MBOX_ASTS_DATABASE_CHANGED 0x8014
399 #define MBOX_ASTS_UNSOLICITED_PDU_RECEIVED 0x8015
400 #define MBOX_ASTS_SELF_TEST_FAILED 0x8016
401 #define MBOX_ASTS_LOGIN_FAILED 0x8017
402 #define MBOX_ASTS_DNS 0x8018
403 #define MBOX_ASTS_HEARTBEAT 0x8019
404 #define MBOX_ASTS_NVRAM_INVALID 0x801A
405 #define MBOX_ASTS_MAC_ADDRESS_CHANGED 0x801B
406 #define MBOX_ASTS_IP_ADDRESS_CHANGED 0x801C
407 #define MBOX_ASTS_DHCP_LEASE_EXPIRED 0x801D
408 #define MBOX_ASTS_DHCP_LEASE_ACQUIRED 0x801F
409 #define MBOX_ASTS_ISNS_UNSOLICITED_PDU_RECEIVED 0x8021
410 #define MBOX_ASTS_DUPLICATE_IP 0x8025
411 #define MBOX_ASTS_ARP_COMPLETE 0x8026
412 #define MBOX_ASTS_SUBNET_STATE_CHANGE 0x8027
413 #define MBOX_ASTS_RESPONSE_QUEUE_FULL 0x8028
414 #define MBOX_ASTS_IP_ADDR_STATE_CHANGED 0x8029
415 #define MBOX_ASTS_IPV6_PREFIX_EXPIRED 0x802B
416 #define MBOX_ASTS_IPV6_ND_PREFIX_IGNORED 0x802C
417 #define MBOX_ASTS_IPV6_LCL_PREFIX_IGNORED 0x802D
418 #define MBOX_ASTS_ICMPV6_ERROR_MSG_RCVD 0x802E
420 #define ISNS_EVENT_DATA_RECEIVED 0x0000
421 #define ISNS_EVENT_CONNECTION_OPENED 0x0001
422 #define ISNS_EVENT_CONNECTION_FAILED 0x0002
423 #define MBOX_ASTS_IPSEC_SYSTEM_FATAL_ERROR 0x8022
424 #define MBOX_ASTS_SUBNET_STATE_CHANGE 0x8027
426 /* ACB State Defines */
427 #define ACB_STATE_UNCONFIGURED 0x00
428 #define ACB_STATE_INVALID 0x01
429 #define ACB_STATE_ACQUIRING 0x02
430 #define ACB_STATE_TENTATIVE 0x03
431 #define ACB_STATE_DEPRICATED 0x04
432 #define ACB_STATE_VALID 0x05
433 #define ACB_STATE_DISABLING 0x06
435 /*************************************************************************/
437 /* Host Adapter Initialization Control Block (from host) */
438 struct addr_ctrl_blk {
439 uint8_t version; /* 00 */
440 #define IFCB_VER_MIN 0x01
441 #define IFCB_VER_MAX 0x02
442 uint8_t control; /* 01 */
444 uint16_t fw_options; /* 02-03 */
445 #define FWOPT_HEARTBEAT_ENABLE 0x1000
446 #define FWOPT_SESSION_MODE 0x0040
447 #define FWOPT_INITIATOR_MODE 0x0020
448 #define FWOPT_TARGET_MODE 0x0010
450 uint16_t exec_throttle; /* 04-05 */
451 uint8_t zio_count; /* 06 */
452 uint8_t res0; /* 07 */
453 uint16_t eth_mtu_size; /* 08-09 */
454 uint16_t add_fw_options; /* 0A-0B */
456 uint8_t hb_interval; /* 0C */
457 uint8_t inst_num; /* 0D */
458 uint16_t res1; /* 0E-0F */
459 uint16_t rqq_consumer_idx; /* 10-11 */
460 uint16_t compq_producer_idx; /* 12-13 */
461 uint16_t rqq_len; /* 14-15 */
462 uint16_t compq_len; /* 16-17 */
463 uint32_t rqq_addr_lo; /* 18-1B */
464 uint32_t rqq_addr_hi; /* 1C-1F */
465 uint32_t compq_addr_lo; /* 20-23 */
466 uint32_t compq_addr_hi; /* 24-27 */
467 uint32_t shdwreg_addr_lo; /* 28-2B */
468 uint32_t shdwreg_addr_hi; /* 2C-2F */
470 uint16_t iscsi_opts; /* 30-31 */
471 uint16_t ipv4_tcp_opts; /* 32-33 */
472 uint16_t ipv4_ip_opts; /* 34-35 */
473 #define IPOPT_IPv4_PROTOCOL_ENABLE 0x8000
475 uint16_t iscsi_max_pdu_size; /* 36-37 */
476 uint8_t ipv4_tos; /* 38 */
477 uint8_t ipv4_ttl; /* 39 */
478 uint8_t acb_version; /* 3A */
479 #define ACB_NOT_SUPPORTED 0x00
480 #define ACB_SUPPORTED 0x02 /* Capable of ACB Version 2
483 uint8_t res2; /* 3B */
484 uint16_t def_timeout; /* 3C-3D */
485 uint16_t iscsi_fburst_len; /* 3E-3F */
486 uint16_t iscsi_def_time2wait; /* 40-41 */
487 uint16_t iscsi_def_time2retain; /* 42-43 */
488 uint16_t iscsi_max_outstnd_r2t; /* 44-45 */
489 uint16_t conn_ka_timeout; /* 46-47 */
490 uint16_t ipv4_port; /* 48-49 */
491 uint16_t iscsi_max_burst_len; /* 4A-4B */
492 uint32_t res5; /* 4C-4F */
493 uint8_t ipv4_addr[4]; /* 50-53 */
494 uint16_t ipv4_vlan_tag; /* 54-55 */
495 uint8_t ipv4_addr_state; /* 56 */
496 uint8_t ipv4_cacheid; /* 57 */
497 uint8_t res6[8]; /* 58-5F */
498 uint8_t ipv4_subnet[4]; /* 60-63 */
499 uint8_t res7[12]; /* 64-6F */
500 uint8_t ipv4_gw_addr[4]; /* 70-73 */
501 uint8_t res8[0xc]; /* 74-7F */
502 uint8_t pri_dns_srvr_ip[4];/* 80-83 */
503 uint8_t sec_dns_srvr_ip[4];/* 84-87 */
504 uint16_t min_eph_port; /* 88-89 */
505 uint16_t max_eph_port; /* 8A-8B */
506 uint8_t res9[4]; /* 8C-8F */
507 uint8_t iscsi_alias[32];/* 90-AF */
508 uint8_t res9_1[0x16]; /* B0-C5 */
509 uint16_t tgt_portal_grp;/* C6-C7 */
510 uint8_t abort_timer; /* C8 */
511 uint8_t ipv4_tcp_wsf; /* C9 */
512 uint8_t res10[6]; /* CA-CF */
513 uint8_t ipv4_sec_ip_addr[4]; /* D0-D3 */
514 uint8_t ipv4_dhcp_vid_len; /* D4 */
515 uint8_t ipv4_dhcp_vid[11]; /* D5-DF */
516 uint8_t res11[20]; /* E0-F3 */
517 uint8_t ipv4_dhcp_alt_cid_len; /* F4 */
518 uint8_t ipv4_dhcp_alt_cid[11]; /* F5-FF */
519 uint8_t iscsi_name[224]; /* 100-1DF */
520 uint8_t res12[32]; /* 1E0-1FF */
521 uint32_t cookie; /* 200-203 */
522 uint16_t ipv6_port; /* 204-205 */
523 uint16_t ipv6_opts; /* 206-207 */
524 #define IPV6_OPT_IPV6_PROTOCOL_ENABLE 0x8000
526 uint16_t ipv6_addtl_opts; /* 208-209 */
527 #define IPV6_ADDOPT_NEIGHBOR_DISCOVERY_ADDR_ENABLE 0x0002 /* Pri ACB
529 #define IPV6_ADDOPT_AUTOCONFIG_LINK_LOCAL_ADDR 0x0001
531 uint16_t ipv6_tcp_opts; /* 20A-20B */
532 uint8_t ipv6_tcp_wsf; /* 20C */
533 uint16_t ipv6_flow_lbl; /* 20D-20F */
534 uint8_t ipv6_dflt_rtr_addr[16]; /* 210-21F */
535 uint16_t ipv6_vlan_tag; /* 220-221 */
536 uint8_t ipv6_lnk_lcl_addr_state;/* 222 */
537 uint8_t ipv6_addr0_state; /* 223 */
538 uint8_t ipv6_addr1_state; /* 224 */
539 #define IP_ADDRSTATE_UNCONFIGURED 0
540 #define IP_ADDRSTATE_INVALID 1
541 #define IP_ADDRSTATE_ACQUIRING 2
542 #define IP_ADDRSTATE_TENTATIVE 3
543 #define IP_ADDRSTATE_DEPRICATED 4
544 #define IP_ADDRSTATE_PREFERRED 5
545 #define IP_ADDRSTATE_DISABLING 6
547 uint8_t ipv6_dflt_rtr_state; /* 225 */
548 #define IPV6_RTRSTATE_UNKNOWN 0
549 #define IPV6_RTRSTATE_MANUAL 1
550 #define IPV6_RTRSTATE_ADVERTISED 3
551 #define IPV6_RTRSTATE_STALE 4
553 uint8_t ipv6_traffic_class; /* 226 */
554 uint8_t ipv6_hop_limit; /* 227 */
555 uint8_t ipv6_if_id[8]; /* 228-22F */
556 uint8_t ipv6_addr0[16]; /* 230-23F */
557 uint8_t ipv6_addr1[16]; /* 240-24F */
558 uint32_t ipv6_nd_reach_time; /* 250-253 */
559 uint32_t ipv6_nd_rexmit_timer; /* 254-257 */
560 uint32_t ipv6_nd_stale_timeout; /* 258-25B */
561 uint8_t ipv6_dup_addr_detect_count; /* 25C */
562 uint8_t ipv6_cache_id; /* 25D */
563 uint8_t res13[18]; /* 25E-26F */
564 uint32_t ipv6_gw_advrt_mtu; /* 270-273 */
565 uint8_t res14[140]; /* 274-2FF */
568 struct init_fw_ctrl_blk {
569 struct addr_ctrl_blk pri;
570 /* struct addr_ctrl_blk sec;*/
573 /*************************************************************************/
575 struct dev_db_entry {
576 uint16_t options; /* 00-01 */
577 #define DDB_OPT_DISC_SESSION 0x10
578 #define DDB_OPT_TARGET 0x02 /* device is a target */
579 #define DDB_OPT_IPV6_DEVICE 0x100
580 #define DDB_OPT_IPV6_NULL_LINK_LOCAL 0x800 /* post connection */
581 #define DDB_OPT_IPV6_FW_DEFINED_LINK_LOCAL 0x800 /* pre connection */
583 uint16_t exec_throttle; /* 02-03 */
584 uint16_t exec_count; /* 04-05 */
585 uint16_t res0; /* 06-07 */
586 uint16_t iscsi_options; /* 08-09 */
587 uint16_t tcp_options; /* 0A-0B */
588 uint16_t ip_options; /* 0C-0D */
589 uint16_t iscsi_max_rcv_data_seg_len; /* 0E-0F */
590 uint32_t res1; /* 10-13 */
591 uint16_t iscsi_max_snd_data_seg_len; /* 14-15 */
592 uint16_t iscsi_first_burst_len; /* 16-17 */
593 uint16_t iscsi_def_time2wait; /* 18-19 */
594 uint16_t iscsi_def_time2retain; /* 1A-1B */
595 uint16_t iscsi_max_outsnd_r2t; /* 1C-1D */
596 uint16_t ka_timeout; /* 1E-1F */
597 uint8_t isid[6]; /* 20-25 big-endian, must be converted
598 * to little-endian */
599 uint16_t tsid; /* 26-27 */
600 uint16_t port; /* 28-29 */
601 uint16_t iscsi_max_burst_len; /* 2A-2B */
602 uint16_t def_timeout; /* 2C-2D */
603 uint16_t res2; /* 2E-2F */
604 uint8_t ip_addr[0x10]; /* 30-3F */
605 uint8_t iscsi_alias[0x20]; /* 40-5F */
606 uint8_t tgt_addr[0x20]; /* 60-7F */
607 uint16_t mss; /* 80-81 */
608 uint16_t res3; /* 82-83 */
609 uint16_t lcl_port; /* 84-85 */
610 uint8_t ipv4_tos; /* 86 */
611 uint16_t ipv6_flow_lbl; /* 87-89 */
612 uint8_t res4[0x36]; /* 8A-BF */
613 uint8_t iscsi_name[0xE0]; /* C0-19F : xxzzy Make this a
614 * pointer to a string so we
615 * don't have to reserve soooo
617 uint8_t link_local_ipv6_addr[0x10]; /* 1A0-1AF */
618 uint8_t res5[0x10]; /* 1B0-1BF */
619 uint16_t ddb_link; /* 1C0-1C1 */
620 uint16_t chap_tbl_idx; /* 1C2-1C3 */
621 uint16_t tgt_portal_grp; /* 1C4-1C5 */
622 uint8_t tcp_xmt_wsf; /* 1C6 */
623 uint8_t tcp_rcv_wsf; /* 1C7 */
624 uint32_t stat_sn; /* 1C8-1CB */
625 uint32_t exp_stat_sn; /* 1CC-1CF */
626 uint8_t res6[0x30]; /* 1D0-1FF */
629 /*************************************************************************/
631 /* Flash definitions */
633 #define FLASH_OFFSET_SYS_INFO 0x02000000
634 #define FLASH_DEFAULTBLOCKSIZE 0x20000
635 #define FLASH_EOF_OFFSET (FLASH_DEFAULTBLOCKSIZE-8) /* 4 bytes
639 struct sys_info_phys_addr {
640 uint8_t address[6]; /* 00-05 */
641 uint8_t filler[2]; /* 06-07 */
644 struct flash_sys_info {
645 uint32_t cookie; /* 00-03 */
646 uint32_t physAddrCount; /* 04-07 */
647 struct sys_info_phys_addr physAddr[4]; /* 08-27 */
648 uint8_t vendorId[128]; /* 28-A7 */
649 uint8_t productId[128]; /* A8-127 */
650 uint32_t serialNumber; /* 128-12B */
652 /* PCI Configuration values */
653 uint32_t pciDeviceVendor; /* 12C-12F */
654 uint32_t pciDeviceId; /* 130-133 */
655 uint32_t pciSubsysVendor; /* 134-137 */
656 uint32_t pciSubsysId; /* 138-13B */
658 /* This validates version 1. */
659 uint32_t crumbs; /* 13C-13F */
661 uint32_t enterpriseNumber; /* 140-143 */
663 uint32_t mtu; /* 144-147 */
664 uint32_t reserved0; /* 148-14b */
665 uint32_t crumbs2; /* 14c-14f */
666 uint8_t acSerialNumber[16]; /* 150-15f */
667 uint32_t crumbs3; /* 160-16f */
669 /* Leave this last in the struct so it is declared invalid if
670 * any new items are added.
672 uint32_t reserved1[39]; /* 170-1ff */
675 struct mbx_sys_info {
676 uint8_t board_id_str[16]; /* 0-f Keep board ID string first */
677 /* in this structure for GUI. */
678 uint16_t board_id; /* 10-11 board ID code */
679 uint16_t phys_port_cnt; /* 12-13 number of physical network ports */
680 uint16_t port_num; /* 14-15 network port for this PCI function */
681 /* (port 0 is first port) */
682 uint8_t mac_addr[6]; /* 16-1b MAC address for this PCI function */
683 uint32_t iscsi_pci_func_cnt; /* 1c-1f number of iSCSI PCI functions */
684 uint32_t pci_func; /* 20-23 this PCI function */
685 unsigned char serial_number[16]; /* 24-33 serial number string */
686 uint8_t reserved[12]; /* 34-3f */
689 struct crash_record {
690 uint16_t fw_major_version; /* 00 - 01 */
691 uint16_t fw_minor_version; /* 02 - 03 */
692 uint16_t fw_patch_version; /* 04 - 05 */
693 uint16_t fw_build_version; /* 06 - 07 */
695 uint8_t build_date[16]; /* 08 - 17 */
696 uint8_t build_time[16]; /* 18 - 27 */
697 uint8_t build_user[16]; /* 28 - 37 */
698 uint8_t card_serial_num[16]; /* 38 - 47 */
700 uint32_t time_of_crash_in_secs; /* 48 - 4B */
701 uint32_t time_of_crash_in_ms; /* 4C - 4F */
703 uint16_t out_RISC_sd_num_frames; /* 50 - 51 */
704 uint16_t OAP_sd_num_words; /* 52 - 53 */
705 uint16_t IAP_sd_num_frames; /* 54 - 55 */
706 uint16_t in_RISC_sd_num_words; /* 56 - 57 */
708 uint8_t reserved1[28]; /* 58 - 7F */
710 uint8_t out_RISC_reg_dump[256]; /* 80 -17F */
711 uint8_t in_RISC_reg_dump[256]; /*180 -27F */
712 uint8_t in_out_RISC_stack_dump[0]; /*280 - ??? */
715 struct conn_event_log_entry {
716 #define MAX_CONN_EVENT_LOG_ENTRIES 100
717 uint32_t timestamp_sec; /* 00 - 03 seconds since boot */
718 uint32_t timestamp_ms; /* 04 - 07 milliseconds since boot */
719 uint16_t device_index; /* 08 - 09 */
720 uint16_t fw_conn_state; /* 0A - 0B */
721 uint8_t event_type; /* 0C - 0C */
722 uint8_t error_code; /* 0D - 0D */
723 uint16_t error_code_detail; /* 0E - 0F */
724 uint8_t num_consecutive_events; /* 10 - 10 */
725 uint8_t rsvd[3]; /* 11 - 13 */
728 /*************************************************************************
730 * IOCB Commands Structures and Definitions
732 *************************************************************************/
733 #define IOCB_MAX_CDB_LEN 16 /* Bytes in a CBD */
734 #define IOCB_MAX_SENSEDATA_LEN 32 /* Bytes of sense data */
735 #define IOCB_MAX_EXT_SENSEDATA_LEN 60 /* Bytes of extended sense data */
737 /* IOCB header structure */
740 #define ET_STATUS 0x03
741 #define ET_MARKER 0x04
742 #define ET_CONT_T1 0x0A
743 #define ET_STATUS_CONTINUATION 0x10
744 #define ET_CMND_T3 0x19
745 #define ET_PASSTHRU0 0x3A
746 #define ET_PASSTHRU_STATUS 0x3C
749 uint8_t systemDefined;
752 /* SyetemDefined definition */
755 /* Generic queue entry structure*/
762 /* 64 bit addressing segment counts*/
764 #define COMMAND_SEG_A64 1
765 #define CONTINUE_SEG_A64 5
767 /* 64 bit addressing segment definition*/
769 struct data_seg_a64 {
780 /* Command Type 3 entry structure*/
782 struct command_t3_entry {
783 struct qla4_header hdr; /* 00-03 */
785 uint32_t handle; /* 04-07 */
786 uint16_t target; /* 08-09 */
787 uint16_t connection_id; /* 0A-0B */
789 uint8_t control_flags; /* 0C */
791 /* data direction (bits 5-6) */
792 #define CF_WRITE 0x20
794 #define CF_NO_DATA 0x00
796 /* task attributes (bits 2-0) */
797 #define CF_HEAD_TAG 0x03
798 #define CF_ORDERED_TAG 0x02
799 #define CF_SIMPLE_TAG 0x01
801 /* STATE FLAGS FIELD IS A PLACE HOLDER. THE FW WILL SET BITS
802 * IN THIS FIELD AS THE COMMAND IS PROCESSED. WHEN THE IOCB IS
803 * CHANGED TO AN IOSB THIS FIELD WILL HAVE THE STATE FLAGS SET
806 uint8_t state_flags; /* 0D */
807 uint8_t cmdRefNum; /* 0E */
808 uint8_t reserved1; /* 0F */
809 uint8_t cdb[IOCB_MAX_CDB_LEN]; /* 10-1F */
810 struct scsi_lun lun; /* FCP LUN (BE). */
811 uint32_t cmdSeqNum; /* 28-2B */
812 uint16_t timeout; /* 2C-2D */
813 uint16_t dataSegCnt; /* 2E-2F */
814 uint32_t ttlByteCnt; /* 30-33 */
815 struct data_seg_a64 dataseg[COMMAND_SEG_A64]; /* 34-3F */
820 /* Continuation Type 1 entry structure*/
821 struct continuation_t1_entry {
822 struct qla4_header hdr;
824 struct data_seg_a64 dataseg[CONTINUE_SEG_A64];
828 /* Parameterize for 64 or 32 bits */
829 #define COMMAND_SEG COMMAND_SEG_A64
830 #define CONTINUE_SEG CONTINUE_SEG_A64
832 #define ET_COMMAND ET_CMND_T3
833 #define ET_CONTINUE ET_CONT_T1
835 /* Marker entry structure*/
836 struct qla4_marker_entry {
837 struct qla4_header hdr; /* 00-03 */
839 uint32_t system_defined; /* 04-07 */
840 uint16_t target; /* 08-09 */
841 uint16_t modifier; /* 0A-0B */
842 #define MM_LUN_RESET 0
843 #define MM_TGT_WARM_RESET 1
845 uint16_t flags; /* 0C-0D */
846 uint16_t reserved1; /* 0E-0F */
847 struct scsi_lun lun; /* FCP LUN (BE). */
848 uint64_t reserved2; /* 18-1F */
849 uint64_t reserved3; /* 20-27 */
850 uint64_t reserved4; /* 28-2F */
851 uint64_t reserved5; /* 30-37 */
852 uint64_t reserved6; /* 38-3F */
855 /* Status entry structure*/
856 struct status_entry {
857 struct qla4_header hdr; /* 00-03 */
859 uint32_t handle; /* 04-07 */
861 uint8_t scsiStatus; /* 08 */
862 #define SCSI_CHECK_CONDITION 0x02
864 uint8_t iscsiFlags; /* 09 */
865 #define ISCSI_FLAG_RESIDUAL_UNDER 0x02
866 #define ISCSI_FLAG_RESIDUAL_OVER 0x04
868 uint8_t iscsiResponse; /* 0A */
870 uint8_t completionStatus; /* 0B */
871 #define SCS_COMPLETE 0x00
872 #define SCS_INCOMPLETE 0x01
873 #define SCS_RESET_OCCURRED 0x04
874 #define SCS_ABORTED 0x05
875 #define SCS_TIMEOUT 0x06
876 #define SCS_DATA_OVERRUN 0x07
877 #define SCS_DATA_UNDERRUN 0x15
878 #define SCS_QUEUE_FULL 0x1C
879 #define SCS_DEVICE_UNAVAILABLE 0x28
880 #define SCS_DEVICE_LOGGED_OUT 0x29
882 uint8_t reserved1; /* 0C */
884 /* state_flags MUST be at the same location as state_flags in
885 * the Command_T3/4_Entry */
886 uint8_t state_flags; /* 0D */
888 uint16_t senseDataByteCnt; /* 0E-0F */
889 uint32_t residualByteCnt; /* 10-13 */
890 uint32_t bidiResidualByteCnt; /* 14-17 */
891 uint32_t expSeqNum; /* 18-1B */
892 uint32_t maxCmdSeqNum; /* 1C-1F */
893 uint8_t senseData[IOCB_MAX_SENSEDATA_LEN]; /* 20-3F */
897 /* Status Continuation entry */
898 struct status_cont_entry {
899 struct qla4_header hdr; /* 00-03 */
900 uint8_t ext_sense_data[IOCB_MAX_EXT_SENSEDATA_LEN]; /* 04-63 */
904 struct qla4_header hdr; /* 00-03 */
905 uint32_t handle; /* 04-07 */
906 uint16_t target; /* 08-09 */
907 uint16_t connectionID; /* 0A-0B */
908 #define ISNS_DEFAULT_SERVER_CONN_ID ((uint16_t)0x8000)
910 uint16_t controlFlags; /* 0C-0D */
911 #define PT_FLAG_ETHERNET_FRAME 0x8000
912 #define PT_FLAG_ISNS_PDU 0x8000
913 #define PT_FLAG_SEND_BUFFER 0x0200
914 #define PT_FLAG_WAIT_4_RESPONSE 0x0100
916 uint16_t timeout; /* 0E-0F */
917 #define PT_DEFAULT_TIMEOUT 30 /* seconds */
919 struct data_seg_a64 outDataSeg64; /* 10-1B */
920 uint32_t res1; /* 1C-1F */
921 struct data_seg_a64 inDataSeg64; /* 20-2B */
922 uint8_t res2[20]; /* 2C-3F */
925 struct passthru_status {
926 struct qla4_header hdr; /* 00-03 */
927 uint32_t handle; /* 04-07 */
928 uint16_t target; /* 08-09 */
929 uint16_t connectionID; /* 0A-0B */
931 uint8_t completionStatus; /* 0C */
932 #define PASSTHRU_STATUS_COMPLETE 0x01
934 uint8_t residualFlags; /* 0D */
936 uint16_t timeout; /* 0E-0F */
937 uint16_t portNumber; /* 10-11 */
938 uint8_t res1[10]; /* 12-1B */
939 uint32_t outResidual; /* 1C-1F */
940 uint8_t res2[12]; /* 20-2B */
941 uint32_t inResidual; /* 2C-2F */
942 uint8_t res4[16]; /* 30-3F */
946 * ISP queue - response queue entry definition.
951 #define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */
954 #endif /* _QLA4X_FW_H */