drivers/scsi/qla4xxx/ql4_nx.c

   1 /*
   2  * QLogic iSCSI HBA Driver
   3  * Copyright (c)  2003-2013 QLogic Corporation
   4  *
   5  * See LICENSE.qla4xxx for copyright and licensing details.
   6  */
   7 #include <linux/delay.h>
   8 #include <linux/io.h>
   9 #include <linux/pci.h>
  10 #include <linux/ratelimit.h>
  11 #include "ql4_def.h"
  12 #include "ql4_glbl.h"
  13 #include "ql4_inline.h"
  14
  15 #include <asm-generic/io-64-nonatomic-lo-hi.h>
  16
  17 #define MASK(n)         DMA_BIT_MASK(n)
  18 #define MN_WIN(addr)    (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff))
  19 #define OCM_WIN(addr)   (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff))
  20 #define MS_WIN(addr)    (addr & 0x0ffc0000)
  21 #define QLA82XX_PCI_MN_2M       (0)
  22 #define QLA82XX_PCI_MS_2M       (0x80000)
  23 #define QLA82XX_PCI_OCM0_2M     (0xc0000)
  24 #define VALID_OCM_ADDR(addr)    (((addr) & 0x3f800) != 0x3f800)
  25 #define GET_MEM_OFFS_2M(addr)   (addr & MASK(18))
  26
  27 /* CRB window related */
  28 #define CRB_BLK(off)    ((off >> 20) & 0x3f)
  29 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
  30 #define CRB_WINDOW_2M   (0x130060)
  31 #define CRB_HI(off)     ((qla4_82xx_crb_hub_agt[CRB_BLK(off)] << 20) | \
  32                         ((off) & 0xf0000))
  33 #define QLA82XX_PCI_CAMQM_2M_END        (0x04800800UL)
  34 #define QLA82XX_PCI_CAMQM_2M_BASE       (0x000ff800UL)
  35 #define CRB_INDIRECT_2M                 (0x1e0000UL)
  36
  37 static inline void __iomem *
  38 qla4_8xxx_pci_base_offsetfset(struct scsi_qla_host *ha, unsigned long off)
  39 {
  40         if ((off < ha->first_page_group_end) &&
  41             (off >= ha->first_page_group_start))
  42                 return (void __iomem *)(ha->nx_pcibase + off);
  43
  44         return NULL;
  45 }
  46
  47 #define MAX_CRB_XFORM 60
  48 static unsigned long crb_addr_xform[MAX_CRB_XFORM];
  49 static int qla4_8xxx_crb_table_initialized;
  50
  51 #define qla4_8xxx_crb_addr_transform(name) \
  52         (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \
  53          QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20)
  54 static void
  55 qla4_82xx_crb_addr_transform_setup(void)
  56 {
  57         qla4_8xxx_crb_addr_transform(XDMA);
  58         qla4_8xxx_crb_addr_transform(TIMR);
  59         qla4_8xxx_crb_addr_transform(SRE);
  60         qla4_8xxx_crb_addr_transform(SQN3);
  61         qla4_8xxx_crb_addr_transform(SQN2);
  62         qla4_8xxx_crb_addr_transform(SQN1);
  63         qla4_8xxx_crb_addr_transform(SQN0);
  64         qla4_8xxx_crb_addr_transform(SQS3);
  65         qla4_8xxx_crb_addr_transform(SQS2);
  66         qla4_8xxx_crb_addr_transform(SQS1);
  67         qla4_8xxx_crb_addr_transform(SQS0);
  68         qla4_8xxx_crb_addr_transform(RPMX7);
  69         qla4_8xxx_crb_addr_transform(RPMX6);
  70         qla4_8xxx_crb_addr_transform(RPMX5);
  71         qla4_8xxx_crb_addr_transform(RPMX4);
  72         qla4_8xxx_crb_addr_transform(RPMX3);
  73         qla4_8xxx_crb_addr_transform(RPMX2);
  74         qla4_8xxx_crb_addr_transform(RPMX1);
  75         qla4_8xxx_crb_addr_transform(RPMX0);
  76         qla4_8xxx_crb_addr_transform(ROMUSB);
  77         qla4_8xxx_crb_addr_transform(SN);
  78         qla4_8xxx_crb_addr_transform(QMN);
  79         qla4_8xxx_crb_addr_transform(QMS);
  80         qla4_8xxx_crb_addr_transform(PGNI);
  81         qla4_8xxx_crb_addr_transform(PGND);
  82         qla4_8xxx_crb_addr_transform(PGN3);
  83         qla4_8xxx_crb_addr_transform(PGN2);
  84         qla4_8xxx_crb_addr_transform(PGN1);
  85         qla4_8xxx_crb_addr_transform(PGN0);
  86         qla4_8xxx_crb_addr_transform(PGSI);
  87         qla4_8xxx_crb_addr_transform(PGSD);
  88         qla4_8xxx_crb_addr_transform(PGS3);
  89         qla4_8xxx_crb_addr_transform(PGS2);
  90         qla4_8xxx_crb_addr_transform(PGS1);
  91         qla4_8xxx_crb_addr_transform(PGS0);
  92         qla4_8xxx_crb_addr_transform(PS);
  93         qla4_8xxx_crb_addr_transform(PH);
  94         qla4_8xxx_crb_addr_transform(NIU);
  95         qla4_8xxx_crb_addr_transform(I2Q);
  96         qla4_8xxx_crb_addr_transform(EG);
  97         qla4_8xxx_crb_addr_transform(MN);
  98         qla4_8xxx_crb_addr_transform(MS);
  99         qla4_8xxx_crb_addr_transform(CAS2);
 100         qla4_8xxx_crb_addr_transform(CAS1);
 101         qla4_8xxx_crb_addr_transform(CAS0);
 102         qla4_8xxx_crb_addr_transform(CAM);
 103         qla4_8xxx_crb_addr_transform(C2C1);
 104         qla4_8xxx_crb_addr_transform(C2C0);
 105         qla4_8xxx_crb_addr_transform(SMB);
 106         qla4_8xxx_crb_addr_transform(OCM0);
 107         qla4_8xxx_crb_addr_transform(I2C0);
 108
 109         qla4_8xxx_crb_table_initialized = 1;
 110 }
 111
 112 static struct crb_128M_2M_block_map crb_128M_2M_map[64] = {
 113         {{{0, 0,         0,         0} } },             /* 0: PCI */
 114         {{{1, 0x0100000, 0x0102000, 0x120000},  /* 1: PCIE */
 115                 {1, 0x0110000, 0x0120000, 0x130000},
 116                 {1, 0x0120000, 0x0122000, 0x124000},
 117                 {1, 0x0130000, 0x0132000, 0x126000},
 118                 {1, 0x0140000, 0x0142000, 0x128000},
 119                 {1, 0x0150000, 0x0152000, 0x12a000},
 120                 {1, 0x0160000, 0x0170000, 0x110000},
 121                 {1, 0x0170000, 0x0172000, 0x12e000},
 122                 {0, 0x0000000, 0x0000000, 0x000000},
 123                 {0, 0x0000000, 0x0000000, 0x000000},
 124                 {0, 0x0000000, 0x0000000, 0x000000},
 125                 {0, 0x0000000, 0x0000000, 0x000000},
 126                 {0, 0x0000000, 0x0000000, 0x000000},
 127                 {0, 0x0000000, 0x0000000, 0x000000},
 128                 {1, 0x01e0000, 0x01e0800, 0x122000},
 129                 {0, 0x0000000, 0x0000000, 0x000000} } },
 130         {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
 131         {{{0, 0,         0,         0} } },         /* 3: */
 132         {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
 133         {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE   */
 134         {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU   */
 135         {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM    */
 136         {{{1, 0x0800000, 0x0802000, 0x170000},  /* 8: SQM0  */
 137                 {0, 0x0000000, 0x0000000, 0x000000},
 138                 {0, 0x0000000, 0x0000000, 0x000000},
 139                 {0, 0x0000000, 0x0000000, 0x000000},
 140                 {0, 0x0000000, 0x0000000, 0x000000},
 141                 {0, 0x0000000, 0x0000000, 0x000000},
 142                 {0, 0x0000000, 0x0000000, 0x000000},
 143                 {0, 0x0000000, 0x0000000, 0x000000},
 144                 {0, 0x0000000, 0x0000000, 0x000000},
 145                 {0, 0x0000000, 0x0000000, 0x000000},
 146                 {0, 0x0000000, 0x0000000, 0x000000},
 147                 {0, 0x0000000, 0x0000000, 0x000000},
 148                 {0, 0x0000000, 0x0000000, 0x000000},
 149                 {0, 0x0000000, 0x0000000, 0x000000},
 150                 {0, 0x0000000, 0x0000000, 0x000000},
 151                 {1, 0x08f0000, 0x08f2000, 0x172000} } },
 152         {{{1, 0x0900000, 0x0902000, 0x174000},  /* 9: SQM1*/
 153                 {0, 0x0000000, 0x0000000, 0x000000},
 154                 {0, 0x0000000, 0x0000000, 0x000000},
 155                 {0, 0x0000000, 0x0000000, 0x000000},
 156                 {0, 0x0000000, 0x0000000, 0x000000},
 157                 {0, 0x0000000, 0x0000000, 0x000000},
 158                 {0, 0x0000000, 0x0000000, 0x000000},
 159                 {0, 0x0000000, 0x0000000, 0x000000},
 160                 {0, 0x0000000, 0x0000000, 0x000000},
 161                 {0, 0x0000000, 0x0000000, 0x000000},
 162                 {0, 0x0000000, 0x0000000, 0x000000},
 163                 {0, 0x0000000, 0x0000000, 0x000000},
 164                 {0, 0x0000000, 0x0000000, 0x000000},
 165                 {0, 0x0000000, 0x0000000, 0x000000},
 166                 {0, 0x0000000, 0x0000000, 0x000000},
 167                 {1, 0x09f0000, 0x09f2000, 0x176000} } },
 168         {{{0, 0x0a00000, 0x0a02000, 0x178000},  /* 10: SQM2*/
 169                 {0, 0x0000000, 0x0000000, 0x000000},
 170                 {0, 0x0000000, 0x0000000, 0x000000},
 171                 {0, 0x0000000, 0x0000000, 0x000000},
 172                 {0, 0x0000000, 0x0000000, 0x000000},
 173                 {0, 0x0000000, 0x0000000, 0x000000},
 174                 {0, 0x0000000, 0x0000000, 0x000000},
 175                 {0, 0x0000000, 0x0000000, 0x000000},
 176                 {0, 0x0000000, 0x0000000, 0x000000},
 177                 {0, 0x0000000, 0x0000000, 0x000000},
 178                 {0, 0x0000000, 0x0000000, 0x000000},
 179                 {0, 0x0000000, 0x0000000, 0x000000},
 180                 {0, 0x0000000, 0x0000000, 0x000000},
 181                 {0, 0x0000000, 0x0000000, 0x000000},
 182                 {0, 0x0000000, 0x0000000, 0x000000},
 183                 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
 184         {{{0, 0x0b00000, 0x0b02000, 0x17c000},  /* 11: SQM3*/
 185                 {0, 0x0000000, 0x0000000, 0x000000},
 186                 {0, 0x0000000, 0x0000000, 0x000000},
 187                 {0, 0x0000000, 0x0000000, 0x000000},
 188                 {0, 0x0000000, 0x0000000, 0x000000},
 189                 {0, 0x0000000, 0x0000000, 0x000000},
 190                 {0, 0x0000000, 0x0000000, 0x000000},
 191                 {0, 0x0000000, 0x0000000, 0x000000},
 192                 {0, 0x0000000, 0x0000000, 0x000000},
 193                 {0, 0x0000000, 0x0000000, 0x000000},
 194                 {0, 0x0000000, 0x0000000, 0x000000},
 195                 {0, 0x0000000, 0x0000000, 0x000000},
 196                 {0, 0x0000000, 0x0000000, 0x000000},
 197                 {0, 0x0000000, 0x0000000, 0x000000},
 198                 {0, 0x0000000, 0x0000000, 0x000000},
 199                 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
 200         {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
 201         {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
 202         {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
 203         {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
 204         {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
 205         {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
 206         {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
 207         {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
 208         {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
 209         {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
 210         {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
 211         {{{0, 0,         0,         0} } },     /* 23: */
 212         {{{0, 0,         0,         0} } },     /* 24: */
 213         {{{0, 0,         0,         0} } },     /* 25: */
 214         {{{0, 0,         0,         0} } },     /* 26: */
 215         {{{0, 0,         0,         0} } },     /* 27: */
 216         {{{0, 0,         0,         0} } },     /* 28: */
 217         {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
 218         {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
 219         {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
 220         {{{0} } },                              /* 32: PCI */
 221         {{{1, 0x2100000, 0x2102000, 0x120000},  /* 33: PCIE */
 222                 {1, 0x2110000, 0x2120000, 0x130000},
 223                 {1, 0x2120000, 0x2122000, 0x124000},
 224                 {1, 0x2130000, 0x2132000, 0x126000},
 225                 {1, 0x2140000, 0x2142000, 0x128000},
 226                 {1, 0x2150000, 0x2152000, 0x12a000},
 227                 {1, 0x2160000, 0x2170000, 0x110000},
 228                 {1, 0x2170000, 0x2172000, 0x12e000},
 229                 {0, 0x0000000, 0x0000000, 0x000000},
 230                 {0, 0x0000000, 0x0000000, 0x000000},
 231                 {0, 0x0000000, 0x0000000, 0x000000},
 232                 {0, 0x0000000, 0x0000000, 0x000000},
 233                 {0, 0x0000000, 0x0000000, 0x000000},
 234                 {0, 0x0000000, 0x0000000, 0x000000},
 235                 {0, 0x0000000, 0x0000000, 0x000000},
 236                 {0, 0x0000000, 0x0000000, 0x000000} } },
 237         {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
 238         {{{0} } },                              /* 35: */
 239         {{{0} } },                              /* 36: */
 240         {{{0} } },                              /* 37: */
 241         {{{0} } },                              /* 38: */
 242         {{{0} } },                              /* 39: */
 243         {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
 244         {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
 245         {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
 246         {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
 247         {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
 248         {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
 249         {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
 250         {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
 251         {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
 252         {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
 253         {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
 254         {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
 255         {{{0} } },                              /* 52: */
 256         {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
 257         {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
 258         {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
 259         {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
 260         {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
 261         {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
 262         {{{0} } },                              /* 59: I2C0 */
 263         {{{0} } },                              /* 60: I2C1 */
 264         {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } },/* 61: LPC */
 265         {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
 266         {{{1, 0x3f00000, 0x3f01000, 0x168000} } }       /* 63: P2NR0 */
 267 };
 268
 269 /*
 270  * top 12 bits of crb internal address (hub, agent)
 271  */
 272 static unsigned qla4_82xx_crb_hub_agt[64] = {
 273         0,
 274         QLA82XX_HW_CRB_HUB_AGT_ADR_PS,
 275         QLA82XX_HW_CRB_HUB_AGT_ADR_MN,
 276         QLA82XX_HW_CRB_HUB_AGT_ADR_MS,
 277         0,
 278         QLA82XX_HW_CRB_HUB_AGT_ADR_SRE,
 279         QLA82XX_HW_CRB_HUB_AGT_ADR_NIU,
 280         QLA82XX_HW_CRB_HUB_AGT_ADR_QMN,
 281         QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0,
 282         QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1,
 283         QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2,
 284         QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3,
 285         QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q,
 286         QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR,
 287         QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB,
 288         QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4,
 289         QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA,
 290         QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0,
 291         QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1,
 292         QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2,
 293         QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3,
 294         QLA82XX_HW_CRB_HUB_AGT_ADR_PGND,
 295         QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI,
 296         QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0,
 297         QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1,
 298         QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2,
 299         QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3,
 300         0,
 301         QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI,
 302         QLA82XX_HW_CRB_HUB_AGT_ADR_SN,
 303         0,
 304         QLA82XX_HW_CRB_HUB_AGT_ADR_EG,
 305         0,
 306         QLA82XX_HW_CRB_HUB_AGT_ADR_PS,
 307         QLA82XX_HW_CRB_HUB_AGT_ADR_CAM,
 308         0,
 309         0,
 310         0,
 311         0,
 312         0,
 313         QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR,
 314         0,
 315         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1,
 316         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2,
 317         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3,
 318         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4,
 319         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5,
 320         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6,
 321         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7,
 322         QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA,
 323         QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q,
 324         QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB,
 325         0,
 326         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0,
 327         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8,
 328         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9,
 329         QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0,
 330         0,
 331         QLA82XX_HW_CRB_HUB_AGT_ADR_SMB,
 332         QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0,
 333         QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1,
 334         0,
 335         QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC,
 336         0,
 337 };
 338
 339 /* Device states */
 340 static char *qdev_state[] = {
 341         "Unknown",
 342         "Cold",
 343         "Initializing",
 344         "Ready",
 345         "Need Reset",
 346         "Need Quiescent",
 347         "Failed",
 348         "Quiescent",
 349 };
 350
 351 /*
 352  * In: 'off' is offset from CRB space in 128M pci map
 353  * Out: 'off' is 2M pci map addr
 354  * side effect: lock crb window
 355  */
 356 static void
 357 qla4_82xx_pci_set_crbwindow_2M(struct scsi_qla_host *ha, ulong *off)
 358 {
 359         u32 win_read;
 360
 361         ha->crb_win = CRB_HI(*off);
 362         writel(ha->crb_win,
 363                 (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
 364
 365         /* Read back value to make sure write has gone through before trying
 366         * to use it. */
 367         win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
 368         if (win_read != ha->crb_win) {
 369                 DEBUG2(ql4_printk(KERN_INFO, ha,
 370                     "%s: Written crbwin (0x%x) != Read crbwin (0x%x),"
 371                     " off=0x%lx\n", __func__, ha->crb_win, win_read, *off));
 372         }
 373         *off = (*off & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase;
 374 }
 375
 376 void
 377 qla4_82xx_wr_32(struct scsi_qla_host *ha, ulong off, u32 data)
 378 {
 379         unsigned long flags = 0;
 380         int rv;
 381
 382         rv = qla4_82xx_pci_get_crb_addr_2M(ha, &off);
 383
 384         BUG_ON(rv == -1);
 385
 386         if (rv == 1) {
 387                 write_lock_irqsave(&ha->hw_lock, flags);
 388                 qla4_82xx_crb_win_lock(ha);
 389                 qla4_82xx_pci_set_crbwindow_2M(ha, &off);
 390         }
 391
 392         writel(data, (void __iomem *)off);
 393
 394         if (rv == 1) {
 395                 qla4_82xx_crb_win_unlock(ha);
 396                 write_unlock_irqrestore(&ha->hw_lock, flags);
 397         }
 398 }
 399
 400 uint32_t qla4_82xx_rd_32(struct scsi_qla_host *ha, ulong off)
 401 {
 402         unsigned long flags = 0;
 403         int rv;
 404         u32 data;
 405
 406         rv = qla4_82xx_pci_get_crb_addr_2M(ha, &off);
 407
 408         BUG_ON(rv == -1);
 409
 410         if (rv == 1) {
 411                 write_lock_irqsave(&ha->hw_lock, flags);
 412                 qla4_82xx_crb_win_lock(ha);
 413                 qla4_82xx_pci_set_crbwindow_2M(ha, &off);
 414         }
 415         data = readl((void __iomem *)off);
 416
 417         if (rv == 1) {
 418                 qla4_82xx_crb_win_unlock(ha);
 419                 write_unlock_irqrestore(&ha->hw_lock, flags);
 420         }
 421         return data;
 422 }
 423
 424 /* Minidump related functions */
 425 int qla4_82xx_md_rd_32(struct scsi_qla_host *ha, uint32_t off, uint32_t *data)
 426 {
 427         uint32_t win_read, off_value;
 428         int rval = QLA_SUCCESS;
 429
 430         off_value  = off & 0xFFFF0000;
 431         writel(off_value, (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
 432
 433         /*
 434          * Read back value to make sure write has gone through before trying
 435          * to use it.
 436          */
 437         win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
 438         if (win_read != off_value) {
 439                 DEBUG2(ql4_printk(KERN_INFO, ha,
 440                                   "%s: Written (0x%x) != Read (0x%x), off=0x%x\n",
 441                                   __func__, off_value, win_read, off));
 442                 rval = QLA_ERROR;
 443         } else {
 444                 off_value  = off & 0x0000FFFF;
 445                 *data = readl((void __iomem *)(off_value + CRB_INDIRECT_2M +
 446                                                ha->nx_pcibase));
 447         }
 448         return rval;
 449 }
 450
 451 int qla4_82xx_md_wr_32(struct scsi_qla_host *ha, uint32_t off, uint32_t data)
 452 {
 453         uint32_t win_read, off_value;
 454         int rval = QLA_SUCCESS;
 455
 456         off_value  = off & 0xFFFF0000;
 457         writel(off_value, (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
 458
 459         /* Read back value to make sure write has gone through before trying
 460          * to use it.
 461          */
 462         win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
 463         if (win_read != off_value) {
 464                 DEBUG2(ql4_printk(KERN_INFO, ha,
 465                                   "%s: Written (0x%x) != Read (0x%x), off=0x%x\n",
 466                                   __func__, off_value, win_read, off));
 467                 rval = QLA_ERROR;
 468         } else {
 469                 off_value  = off & 0x0000FFFF;
 470                 writel(data, (void __iomem *)(off_value + CRB_INDIRECT_2M +
 471                                               ha->nx_pcibase));
 472         }
 473         return rval;
 474 }
 475
 476 #define CRB_WIN_LOCK_TIMEOUT 100000000
 477
 478 int qla4_82xx_crb_win_lock(struct scsi_qla_host *ha)
 479 {
 480         int i;
 481         int done = 0, timeout = 0;
 482
 483         while (!done) {
 484                 /* acquire semaphore3 from PCI HW block */
 485                 done = qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK));
 486                 if (done == 1)
 487                         break;
 488                 if (timeout >= CRB_WIN_LOCK_TIMEOUT)
 489                         return -1;
 490
 491                 timeout++;
 492
 493                 /* Yield CPU */
 494                 if (!in_interrupt())
 495                         schedule();
 496                 else {
 497                         for (i = 0; i < 20; i++)
 498                                 cpu_relax();    /*This a nop instr on i386*/
 499                 }
 500         }
 501         qla4_82xx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->func_num);
 502         return 0;
 503 }
 504
 505 void qla4_82xx_crb_win_unlock(struct scsi_qla_host *ha)
 506 {
 507         qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK));
 508 }
 509
 510 #define IDC_LOCK_TIMEOUT 100000000
 511
 512 /**
 513  * qla4_82xx_idc_lock - hw_lock
 514  * @ha: pointer to adapter structure
 515  *
 516  * General purpose lock used to synchronize access to
 517  * CRB_DEV_STATE, CRB_DEV_REF_COUNT, etc.
 518  **/
 519 int qla4_82xx_idc_lock(struct scsi_qla_host *ha)
 520 {
 521         int i;
 522         int done = 0, timeout = 0;
 523
 524         while (!done) {
 525                 /* acquire semaphore5 from PCI HW block */
 526                 done = qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK));
 527                 if (done == 1)
 528                         break;
 529                 if (timeout >= IDC_LOCK_TIMEOUT)
 530                         return -1;
 531
 532                 timeout++;
 533
 534                 /* Yield CPU */
 535                 if (!in_interrupt())
 536                         schedule();
 537                 else {
 538                         for (i = 0; i < 20; i++)
 539                                 cpu_relax();    /*This a nop instr on i386*/
 540                 }
 541         }
 542         return 0;
 543 }
 544
 545 void qla4_82xx_idc_unlock(struct scsi_qla_host *ha)
 546 {
 547         qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK));
 548 }
 549
 550 int
 551 qla4_82xx_pci_get_crb_addr_2M(struct scsi_qla_host *ha, ulong *off)
 552 {
 553         struct crb_128M_2M_sub_block_map *m;
 554
 555         if (*off >= QLA82XX_CRB_MAX)
 556                 return -1;
 557
 558         if (*off >= QLA82XX_PCI_CAMQM && (*off < QLA82XX_PCI_CAMQM_2M_END)) {
 559                 *off = (*off - QLA82XX_PCI_CAMQM) +
 560                     QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase;
 561                 return 0;
 562         }
 563
 564         if (*off < QLA82XX_PCI_CRBSPACE)
 565                 return -1;
 566
 567         *off -= QLA82XX_PCI_CRBSPACE;
 568         /*
 569          * Try direct map
 570          */
 571
 572         m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)];
 573
 574         if (m->valid && (m->start_128M <= *off) && (m->end_128M > *off)) {
 575                 *off = *off + m->start_2M - m->start_128M + ha->nx_pcibase;
 576                 return 0;
 577         }
 578
 579         /*
 580          * Not in direct map, use crb window
 581          */
 582         return 1;
 583 }
 584
 585 /*
 586 * check memory access boundary.
 587 * used by test agent. support ddr access only for now
 588 */
 589 static unsigned long
 590 qla4_82xx_pci_mem_bound_check(struct scsi_qla_host *ha,
 591                 unsigned long long addr, int size)
 592 {
 593         if (!QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_DDR_NET,
 594             QLA8XXX_ADDR_DDR_NET_MAX) ||
 595             !QLA8XXX_ADDR_IN_RANGE(addr + size - 1,
 596             QLA8XXX_ADDR_DDR_NET, QLA8XXX_ADDR_DDR_NET_MAX) ||
 597             ((size != 1) && (size != 2) && (size != 4) && (size != 8))) {
 598                 return 0;
 599         }
 600         return 1;
 601 }
 602
 603 static int qla4_82xx_pci_set_window_warning_count;
 604
 605 static unsigned long
 606 qla4_82xx_pci_set_window(struct scsi_qla_host *ha, unsigned long long addr)
 607 {
 608         int window;
 609         u32 win_read;
 610
 611         if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_DDR_NET,
 612             QLA8XXX_ADDR_DDR_NET_MAX)) {
 613                 /* DDR network side */
 614                 window = MN_WIN(addr);
 615                 ha->ddr_mn_window = window;
 616                 qla4_82xx_wr_32(ha, ha->mn_win_crb |
 617                     QLA82XX_PCI_CRBSPACE, window);
 618                 win_read = qla4_82xx_rd_32(ha, ha->mn_win_crb |
 619                     QLA82XX_PCI_CRBSPACE);
 620                 if ((win_read << 17) != window) {
 621                         ql4_printk(KERN_WARNING, ha,
 622                         "%s: Written MNwin (0x%x) != Read MNwin (0x%x)\n",
 623                         __func__, window, win_read);
 624                 }
 625                 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET;
 626         } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_OCM0,
 627                                 QLA8XXX_ADDR_OCM0_MAX)) {
 628                 unsigned int temp1;
 629                 /* if bits 19:18&17:11 are on */
 630                 if ((addr & 0x00ff800) == 0xff800) {
 631                         printk("%s: QM access not handled.\n", __func__);
 632                         addr = -1UL;
 633                 }
 634
 635                 window = OCM_WIN(addr);
 636                 ha->ddr_mn_window = window;
 637                 qla4_82xx_wr_32(ha, ha->mn_win_crb |
 638                     QLA82XX_PCI_CRBSPACE, window);
 639                 win_read = qla4_82xx_rd_32(ha, ha->mn_win_crb |
 640                     QLA82XX_PCI_CRBSPACE);
 641                 temp1 = ((window & 0x1FF) << 7) |
 642                     ((window & 0x0FFFE0000) >> 17);
 643                 if (win_read != temp1) {
 644                         printk("%s: Written OCMwin (0x%x) != Read"
 645                             " OCMwin (0x%x)\n", __func__, temp1, win_read);
 646                 }
 647                 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M;
 648
 649         } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_QDR_NET,
 650                                 QLA82XX_P3_ADDR_QDR_NET_MAX)) {
 651                 /* QDR network side */
 652                 window = MS_WIN(addr);
 653                 ha->qdr_sn_window = window;
 654                 qla4_82xx_wr_32(ha, ha->ms_win_crb |
 655                     QLA82XX_PCI_CRBSPACE, window);
 656                 win_read = qla4_82xx_rd_32(ha,
 657                      ha->ms_win_crb | QLA82XX_PCI_CRBSPACE);
 658                 if (win_read != window) {
 659                         printk("%s: Written MSwin (0x%x) != Read "
 660                             "MSwin (0x%x)\n", __func__, window, win_read);
 661                 }
 662                 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_QDR_NET;
 663
 664         } else {
 665                 /*
 666                  * peg gdb frequently accesses memory that doesn't exist,
 667                  * this limits the chit chat so debugging isn't slowed down.
 668                  */
 669                 if ((qla4_82xx_pci_set_window_warning_count++ < 8) ||
 670                     (qla4_82xx_pci_set_window_warning_count%64 == 0)) {
 671                         printk("%s: Warning:%s Unknown address range!\n",
 672                             __func__, DRIVER_NAME);
 673                 }
 674                 addr = -1UL;
 675         }
 676         return addr;
 677 }
 678
 679 /* check if address is in the same windows as the previous access */
 680 static int qla4_82xx_pci_is_same_window(struct scsi_qla_host *ha,
 681                 unsigned long long addr)
 682 {
 683         int window;
 684         unsigned long long qdr_max;
 685
 686         qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX;
 687
 688         if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_DDR_NET,
 689             QLA8XXX_ADDR_DDR_NET_MAX)) {
 690                 /* DDR network side */
 691                 BUG();  /* MN access can not come here */
 692         } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_OCM0,
 693              QLA8XXX_ADDR_OCM0_MAX)) {
 694                 return 1;
 695         } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_OCM1,
 696              QLA8XXX_ADDR_OCM1_MAX)) {
 697                 return 1;
 698         } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_QDR_NET,
 699             qdr_max)) {
 700                 /* QDR network side */
 701                 window = ((addr - QLA8XXX_ADDR_QDR_NET) >> 22) & 0x3f;
 702                 if (ha->qdr_sn_window == window)
 703                         return 1;
 704         }
 705
 706         return 0;
 707 }
 708
 709 static int qla4_82xx_pci_mem_read_direct(struct scsi_qla_host *ha,
 710                 u64 off, void *data, int size)
 711 {
 712         unsigned long flags;
 713         void __iomem *addr;
 714         int ret = 0;
 715         u64 start;
 716         void __iomem *mem_ptr = NULL;
 717         unsigned long mem_base;
 718         unsigned long mem_page;
 719
 720         write_lock_irqsave(&ha->hw_lock, flags);
 721
 722         /*
 723          * If attempting to access unknown address or straddle hw windows,
 724          * do not access.
 725          */
 726         start = qla4_82xx_pci_set_window(ha, off);
 727         if ((start == -1UL) ||
 728             (qla4_82xx_pci_is_same_window(ha, off + size - 1) == 0)) {
 729                 write_unlock_irqrestore(&ha->hw_lock, flags);
 730                 printk(KERN_ERR"%s out of bound pci memory access. "
 731                                 "offset is 0x%llx\n", DRIVER_NAME, off);
 732                 return -1;
 733         }
 734
 735         addr = qla4_8xxx_pci_base_offsetfset(ha, start);
 736         if (!addr) {
 737                 write_unlock_irqrestore(&ha->hw_lock, flags);
 738                 mem_base = pci_resource_start(ha->pdev, 0);
 739                 mem_page = start & PAGE_MASK;
 740                 /* Map two pages whenever user tries to access addresses in two
 741                    consecutive pages.
 742                  */
 743                 if (mem_page != ((start + size - 1) & PAGE_MASK))
 744                         mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2);
 745                 else
 746                         mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
 747
 748                 if (mem_ptr == NULL) {
 749                         *(u8 *)data = 0;
 750                         return -1;
 751                 }
 752                 addr = mem_ptr;
 753                 addr += start & (PAGE_SIZE - 1);
 754                 write_lock_irqsave(&ha->hw_lock, flags);
 755         }
 756
 757         switch (size) {
 758         case 1:
 759                 *(u8  *)data = readb(addr);
 760                 break;
 761         case 2:
 762                 *(u16 *)data = readw(addr);
 763                 break;
 764         case 4:
 765                 *(u32 *)data = readl(addr);
 766                 break;
 767         case 8:
 768                 *(u64 *)data = readq(addr);
 769                 break;
 770         default:
 771                 ret = -1;
 772                 break;
 773         }
 774         write_unlock_irqrestore(&ha->hw_lock, flags);
 775
 776         if (mem_ptr)
 777                 iounmap(mem_ptr);
 778         return ret;
 779 }
 780
 781 static int
 782 qla4_82xx_pci_mem_write_direct(struct scsi_qla_host *ha, u64 off,
 783                 void *data, int size)
 784 {
 785         unsigned long flags;
 786         void __iomem *addr;
 787         int ret = 0;
 788         u64 start;
 789         void __iomem *mem_ptr = NULL;
 790         unsigned long mem_base;
 791         unsigned long mem_page;
 792
 793         write_lock_irqsave(&ha->hw_lock, flags);
 794
 795         /*
 796          * If attempting to access unknown address or straddle hw windows,
 797          * do not access.
 798          */
 799         start = qla4_82xx_pci_set_window(ha, off);
 800         if ((start == -1UL) ||
 801             (qla4_82xx_pci_is_same_window(ha, off + size - 1) == 0)) {
 802                 write_unlock_irqrestore(&ha->hw_lock, flags);
 803                 printk(KERN_ERR"%s out of bound pci memory access. "
 804                                 "offset is 0x%llx\n", DRIVER_NAME, off);
 805                 return -1;
 806         }
 807
 808         addr = qla4_8xxx_pci_base_offsetfset(ha, start);
 809         if (!addr) {
 810                 write_unlock_irqrestore(&ha->hw_lock, flags);
 811                 mem_base = pci_resource_start(ha->pdev, 0);
 812                 mem_page = start & PAGE_MASK;
 813                 /* Map two pages whenever user tries to access addresses in two
 814                    consecutive pages.
 815                  */
 816                 if (mem_page != ((start + size - 1) & PAGE_MASK))
 817                         mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2);
 818                 else
 819                         mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
 820                 if (mem_ptr == NULL)
 821                         return -1;
 822
 823                 addr = mem_ptr;
 824                 addr += start & (PAGE_SIZE - 1);
 825                 write_lock_irqsave(&ha->hw_lock, flags);
 826         }
 827
 828         switch (size) {
 829         case 1:
 830                 writeb(*(u8 *)data, addr);
 831                 break;
 832         case 2:
 833                 writew(*(u16 *)data, addr);
 834                 break;
 835         case 4:
 836                 writel(*(u32 *)data, addr);
 837                 break;
 838         case 8:
 839                 writeq(*(u64 *)data, addr);
 840                 break;
 841         default:
 842                 ret = -1;
 843                 break;
 844         }
 845         write_unlock_irqrestore(&ha->hw_lock, flags);
 846         if (mem_ptr)
 847                 iounmap(mem_ptr);
 848         return ret;
 849 }
 850
 851 #define MTU_FUDGE_FACTOR 100
 852
 853 static unsigned long
 854 qla4_82xx_decode_crb_addr(unsigned long addr)
 855 {
 856         int i;
 857         unsigned long base_addr, offset, pci_base;
 858
 859         if (!qla4_8xxx_crb_table_initialized)
 860                 qla4_82xx_crb_addr_transform_setup();
 861
 862         pci_base = ADDR_ERROR;
 863         base_addr = addr & 0xfff00000;
 864         offset = addr & 0x000fffff;
 865
 866         for (i = 0; i < MAX_CRB_XFORM; i++) {
 867                 if (crb_addr_xform[i] == base_addr) {
 868                         pci_base = i << 20;
 869                         break;
 870                 }
 871         }
 872         if (pci_base == ADDR_ERROR)
 873                 return pci_base;
 874         else
 875                 return pci_base + offset;
 876 }
 877
 878 static long rom_max_timeout = 100;
 879 static long qla4_82xx_rom_lock_timeout = 100;
 880
 881 static int
 882 qla4_82xx_rom_lock(struct scsi_qla_host *ha)
 883 {
 884         int i;
 885         int done = 0, timeout = 0;
 886
 887         while (!done) {
 888                 /* acquire semaphore2 from PCI HW block */
 889
 890                 done = qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK));
 891                 if (done == 1)
 892                         break;
 893                 if (timeout >= qla4_82xx_rom_lock_timeout)
 894                         return -1;
 895
 896                 timeout++;
 897
 898                 /* Yield CPU */
 899                 if (!in_interrupt())
 900                         schedule();
 901                 else {
 902                         for (i = 0; i < 20; i++)
 903                                 cpu_relax();    /*This a nop instr on i386*/
 904                 }
 905         }
 906         qla4_82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ROM_LOCK_DRIVER);
 907         return 0;
 908 }
 909
 910 static void
 911 qla4_82xx_rom_unlock(struct scsi_qla_host *ha)
 912 {
 913         qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK));
 914 }
 915
 916 static int
 917 qla4_82xx_wait_rom_done(struct scsi_qla_host *ha)
 918 {
 919         long timeout = 0;
 920         long done = 0 ;
 921
 922         while (done == 0) {
 923                 done = qla4_82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS);
 924                 done &= 2;
 925                 timeout++;
 926                 if (timeout >= rom_max_timeout) {
 927                         printk("%s: Timeout reached  waiting for rom done",
 928                                         DRIVER_NAME);
 929                         return -1;
 930                 }
 931         }
 932         return 0;
 933 }
 934
 935 static int
 936 qla4_82xx_do_rom_fast_read(struct scsi_qla_host *ha, int addr, int *valp)
 937 {
 938         qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr);
 939         qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
 940         qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3);
 941         qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0xb);
 942         if (qla4_82xx_wait_rom_done(ha)) {
 943                 printk("%s: Error waiting for rom done\n", DRIVER_NAME);
 944                 return -1;
 945         }
 946         /* reset abyte_cnt and dummy_byte_cnt */
 947         qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
 948         udelay(10);
 949         qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0);
 950
 951         *valp = qla4_82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA);
 952         return 0;
 953 }
 954
 955 static int
 956 qla4_82xx_rom_fast_read(struct scsi_qla_host *ha, int addr, int *valp)
 957 {
 958         int ret, loops = 0;
 959
 960         while ((qla4_82xx_rom_lock(ha) != 0) && (loops < 50000)) {
 961                 udelay(100);
 962                 loops++;
 963         }
 964         if (loops >= 50000) {
 965                 ql4_printk(KERN_WARNING, ha, "%s: qla4_82xx_rom_lock failed\n",
 966                            DRIVER_NAME);
 967                 return -1;
 968         }
 969         ret = qla4_82xx_do_rom_fast_read(ha, addr, valp);
 970         qla4_82xx_rom_unlock(ha);
 971         return ret;
 972 }
 973
 974 /**
 975  * This routine does CRB initialize sequence
 976  * to put the ISP into operational state
 977  **/
 978 static int
 979 qla4_82xx_pinit_from_rom(struct scsi_qla_host *ha, int verbose)
 980 {
 981         int addr, val;
 982         int i ;
 983         struct crb_addr_pair *buf;
 984         unsigned long off;
 985         unsigned offset, n;
 986
 987         struct crb_addr_pair {
 988                 long addr;
 989                 long data;
 990         };
 991
 992         /* Halt all the indiviual PEGs and other blocks of the ISP */
 993         qla4_82xx_rom_lock(ha);
 994
 995         /* disable all I2Q */
 996         qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x10, 0x0);
 997         qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x14, 0x0);
 998         qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x18, 0x0);
 999         qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x1c, 0x0);
1000         qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x20, 0x0);
1001         qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x24, 0x0);
1002
1003         /* disable all niu interrupts */
1004         qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x40, 0xff);
1005         /* disable xge rx/tx */
1006         qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x70000, 0x00);
1007         /* disable xg1 rx/tx */
1008         qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x80000, 0x00);
1009         /* disable sideband mac */
1010         qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x90000, 0x00);
1011         /* disable ap0 mac */
1012         qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xa0000, 0x00);
1013         /* disable ap1 mac */
1014         qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xb0000, 0x00);
1015
1016         /* halt sre */
1017         val = qla4_82xx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000);
1018         qla4_82xx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1)));
1019
1020         /* halt epg */
1021         qla4_82xx_wr_32(ha, QLA82XX_CRB_EPG + 0x1300, 0x1);
1022
1023         /* halt timers */
1024         qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x0, 0x0);
1025         qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x8, 0x0);
1026         qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x10, 0x0);
1027         qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x18, 0x0);
1028         qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x100, 0x0);
1029         qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x200, 0x0);
1030
1031         /* halt pegs */
1032         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c, 1);
1033         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c, 1);
1034         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c, 1);
1035         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c, 1);
1036         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c, 1);
1037         msleep(5);
1038
1039         /* big hammer */
1040         if (test_bit(DPC_RESET_HA, &ha->dpc_flags))
1041                 /* don't reset CAM block on reset */
1042                 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff);
1043         else
1044                 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff);
1045
1046         qla4_82xx_rom_unlock(ha);
1047
1048         /* Read the signature value from the flash.
1049          * Offset 0: Contain signature (0xcafecafe)
1050          * Offset 4: Offset and number of addr/value pairs
1051          * that present in CRB initialize sequence
1052          */
1053         if (qla4_82xx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL ||
1054             qla4_82xx_rom_fast_read(ha, 4, &n) != 0) {
1055                 ql4_printk(KERN_WARNING, ha,
1056                         "[ERROR] Reading crb_init area: n: %08x\n", n);
1057                 return -1;
1058         }
1059
1060         /* Offset in flash = lower 16 bits
1061          * Number of enteries = upper 16 bits
1062          */
1063         offset = n & 0xffffU;
1064         n = (n >> 16) & 0xffffU;
1065
1066         /* number of addr/value pair should not exceed 1024 enteries */
1067         if (n  >= 1024) {
1068                 ql4_printk(KERN_WARNING, ha,
1069                     "%s: %s:n=0x%x [ERROR] Card flash not initialized.\n",
1070                     DRIVER_NAME, __func__, n);
1071                 return -1;
1072         }
1073
1074         ql4_printk(KERN_INFO, ha,
1075                 "%s: %d CRB init values found in ROM.\n", DRIVER_NAME, n);
1076
1077         buf = kmalloc(n * sizeof(struct crb_addr_pair), GFP_KERNEL);
1078         if (buf == NULL) {
1079                 ql4_printk(KERN_WARNING, ha,
1080                     "%s: [ERROR] Unable to malloc memory.\n", DRIVER_NAME);
1081                 return -1;
1082         }
1083
1084         for (i = 0; i < n; i++) {
1085                 if (qla4_82xx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 ||
1086                     qla4_82xx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) !=
1087                     0) {
1088                         kfree(buf);
1089                         return -1;
1090                 }
1091
1092                 buf[i].addr = addr;
1093                 buf[i].data = val;
1094         }
1095
1096         for (i = 0; i < n; i++) {
1097                 /* Translate internal CRB initialization
1098                  * address to PCI bus address
1099                  */
1100                 off = qla4_82xx_decode_crb_addr((unsigned long)buf[i].addr) +
1101                     QLA82XX_PCI_CRBSPACE;
1102                 /* Not all CRB  addr/value pair to be written,
1103                  * some of them are skipped
1104                  */
1105
1106                 /* skip if LS bit is set*/
1107                 if (off & 0x1) {
1108                         DEBUG2(ql4_printk(KERN_WARNING, ha,
1109                             "Skip CRB init replay for offset = 0x%lx\n", off));
1110                         continue;
1111                 }
1112
1113                 /* skipping cold reboot MAGIC */
1114                 if (off == QLA82XX_CAM_RAM(0x1fc))
1115                         continue;
1116
1117                 /* do not reset PCI */
1118                 if (off == (ROMUSB_GLB + 0xbc))
1119                         continue;
1120
1121                 /* skip core clock, so that firmware can increase the clock */
1122                 if (off == (ROMUSB_GLB + 0xc8))
1123                         continue;
1124
1125                 /* skip the function enable register */
1126                 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION))
1127                         continue;
1128
1129                 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION2))
1130                         continue;
1131
1132                 if ((off & 0x0ff00000) == QLA82XX_CRB_SMB)
1133                         continue;
1134
1135                 if ((off & 0x0ff00000) == QLA82XX_CRB_DDR_NET)
1136                         continue;
1137
1138                 if (off == ADDR_ERROR) {
1139                         ql4_printk(KERN_WARNING, ha,
1140                             "%s: [ERROR] Unknown addr: 0x%08lx\n",
1141                             DRIVER_NAME, buf[i].addr);
1142                         continue;
1143                 }
1144
1145                 qla4_82xx_wr_32(ha, off, buf[i].data);
1146
1147                 /* ISP requires much bigger delay to settle down,
1148                  * else crb_window returns 0xffffffff
1149                  */
1150                 if (off == QLA82XX_ROMUSB_GLB_SW_RESET)
1151                         msleep(1000);
1152
1153                 /* ISP requires millisec delay between
1154                  * successive CRB register updation
1155                  */
1156                 msleep(1);
1157         }
1158
1159         kfree(buf);
1160
1161         /* Resetting the data and instruction cache */
1162         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e);
1163         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8);
1164         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8);
1165
1166         /* Clear all protocol processing engines */
1167         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0);
1168         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0);
1169         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0);
1170         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0);
1171         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0);
1172         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0);
1173         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0);
1174         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0);
1175
1176         return 0;
1177 }
1178
1179 static int
1180 qla4_82xx_load_from_flash(struct scsi_qla_host *ha, uint32_t image_start)
1181 {
1182         int  i, rval = 0;
1183         long size = 0;
1184         long flashaddr, memaddr;
1185         u64 data;
1186         u32 high, low;
1187
1188         flashaddr = memaddr = ha->hw.flt_region_bootload;
1189         size = (image_start - flashaddr) / 8;
1190
1191         DEBUG2(printk("scsi%ld: %s: bootldr=0x%lx, fw_image=0x%x\n",
1192             ha->host_no, __func__, flashaddr, image_start));
1193
1194         for (i = 0; i < size; i++) {
1195                 if ((qla4_82xx_rom_fast_read(ha, flashaddr, (int *)&low)) ||
1196                     (qla4_82xx_rom_fast_read(ha, flashaddr + 4,
1197                     (int *)&high))) {
1198                         rval = -1;
1199                         goto exit_load_from_flash;
1200                 }
1201                 data = ((u64)high << 32) | low ;
1202                 rval = qla4_82xx_pci_mem_write_2M(ha, memaddr, &data, 8);
1203                 if (rval)
1204                         goto exit_load_from_flash;
1205
1206                 flashaddr += 8;
1207                 memaddr   += 8;
1208
1209                 if (i % 0x1000 == 0)
1210                         msleep(1);
1211
1212         }
1213
1214         udelay(100);
1215
1216         read_lock(&ha->hw_lock);
1217         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020);
1218         qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e);
1219         read_unlock(&ha->hw_lock);
1220
1221 exit_load_from_flash:
1222         return rval;
1223 }
1224
1225 static int qla4_82xx_load_fw(struct scsi_qla_host *ha, uint32_t image_start)
1226 {
1227         u32 rst;
1228
1229         qla4_82xx_wr_32(ha, CRB_CMDPEG_STATE, 0);
1230         if (qla4_82xx_pinit_from_rom(ha, 0) != QLA_SUCCESS) {
1231                 printk(KERN_WARNING "%s: Error during CRB Initialization\n",
1232                     __func__);
1233                 return QLA_ERROR;
1234         }
1235
1236         udelay(500);
1237
1238         /* at this point, QM is in reset. This could be a problem if there are
1239          * incoming d* transition queue messages. QM/PCIE could wedge.
1240          * To get around this, QM is brought out of reset.
1241          */
1242
1243         rst = qla4_82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET);
1244         /* unreset qm */
1245         rst &= ~(1 << 28);
1246         qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst);
1247
1248         if (qla4_82xx_load_from_flash(ha, image_start)) {
1249                 printk("%s: Error trying to load fw from flash!\n", __func__);
1250                 return QLA_ERROR;
1251         }
1252
1253         return QLA_SUCCESS;
1254 }
1255
1256 int
1257 qla4_82xx_pci_mem_read_2M(struct scsi_qla_host *ha,
1258                 u64 off, void *data, int size)
1259 {
1260         int i, j = 0, k, start, end, loop, sz[2], off0[2];
1261         int shift_amount;
1262         uint32_t temp;
1263         uint64_t off8, val, mem_crb, word[2] = {0, 0};
1264
1265         /*
1266          * If not MN, go check for MS or invalid.
1267          */
1268
1269         if (off >= QLA8XXX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
1270                 mem_crb = QLA82XX_CRB_QDR_NET;
1271         else {
1272                 mem_crb = QLA82XX_CRB_DDR_NET;
1273                 if (qla4_82xx_pci_mem_bound_check(ha, off, size) == 0)
1274                         return qla4_82xx_pci_mem_read_direct(ha,
1275                                         off, data, size);
1276         }
1277
1278
1279         off8 = off & 0xfffffff0;
1280         off0[0] = off & 0xf;
1281         sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]);
1282         shift_amount = 4;
1283
1284         loop = ((off0[0] + size - 1) >> shift_amount) + 1;
1285         off0[1] = 0;
1286         sz[1] = size - sz[0];
1287
1288         for (i = 0; i < loop; i++) {
1289                 temp = off8 + (i << shift_amount);
1290                 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp);
1291                 temp = 0;
1292                 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp);
1293                 temp = MIU_TA_CTL_ENABLE;
1294                 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1295                 temp = MIU_TA_CTL_START_ENABLE;
1296                 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1297
1298                 for (j = 0; j < MAX_CTL_CHECK; j++) {
1299                         temp = qla4_82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
1300                         if ((temp & MIU_TA_CTL_BUSY) == 0)
1301                                 break;
1302                 }
1303
1304                 if (j >= MAX_CTL_CHECK) {
1305                         printk_ratelimited(KERN_ERR
1306                                            "%s: failed to read through agent\n",
1307                                            __func__);
1308                         break;
1309                 }
1310
1311                 start = off0[i] >> 2;
1312                 end   = (off0[i] + sz[i] - 1) >> 2;
1313                 for (k = start; k <= end; k++) {
1314                         temp = qla4_82xx_rd_32(ha,
1315                                 mem_crb + MIU_TEST_AGT_RDDATA(k));
1316                         word[i] |= ((uint64_t)temp << (32 * (k & 1)));
1317                 }
1318         }
1319
1320         if (j >= MAX_CTL_CHECK)
1321                 return -1;
1322
1323         if ((off0[0] & 7) == 0) {
1324                 val = word[0];
1325         } else {
1326                 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1327                 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1328         }
1329
1330         switch (size) {
1331         case 1:
1332                 *(uint8_t  *)data = val;
1333                 break;
1334         case 2:
1335                 *(uint16_t *)data = val;
1336                 break;
1337         case 4:
1338                 *(uint32_t *)data = val;
1339                 break;
1340         case 8:
1341                 *(uint64_t *)data = val;
1342                 break;
1343         }
1344         return 0;
1345 }
1346
1347 int
1348 qla4_82xx_pci_mem_write_2M(struct scsi_qla_host *ha,
1349                 u64 off, void *data, int size)
1350 {
1351         int i, j, ret = 0, loop, sz[2], off0;
1352         int scale, shift_amount, startword;
1353         uint32_t temp;
1354         uint64_t off8, mem_crb, tmpw, word[2] = {0, 0};
1355
1356         /*
1357          * If not MN, go check for MS or invalid.
1358          */
1359         if (off >= QLA8XXX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
1360                 mem_crb = QLA82XX_CRB_QDR_NET;
1361         else {
1362                 mem_crb = QLA82XX_CRB_DDR_NET;
1363                 if (qla4_82xx_pci_mem_bound_check(ha, off, size) == 0)
1364                         return qla4_82xx_pci_mem_write_direct(ha,
1365                                         off, data, size);
1366         }
1367
1368         off0 = off & 0x7;
1369         sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1370         sz[1] = size - sz[0];
1371
1372         off8 = off & 0xfffffff0;
1373         loop = (((off & 0xf) + size - 1) >> 4) + 1;
1374         shift_amount = 4;
1375         scale = 2;
1376         startword = (off & 0xf)/8;
1377
1378         for (i = 0; i < loop; i++) {
1379                 if (qla4_82xx_pci_mem_read_2M(ha, off8 +
1380                     (i << shift_amount), &word[i * scale], 8))
1381                         return -1;
1382         }
1383
1384         switch (size) {
1385         case 1:
1386                 tmpw = *((uint8_t *)data);
1387                 break;
1388         case 2:
1389                 tmpw = *((uint16_t *)data);
1390                 break;
1391         case 4:
1392                 tmpw = *((uint32_t *)data);
1393                 break;
1394         case 8:
1395         default:
1396                 tmpw = *((uint64_t *)data);
1397                 break;
1398         }
1399
1400         if (sz[0] == 8)
1401                 word[startword] = tmpw;
1402         else {
1403                 word[startword] &=
1404                     ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1405                 word[startword] |= tmpw << (off0 * 8);
1406         }
1407
1408         if (sz[1] != 0) {
1409                 word[startword+1] &= ~(~0ULL << (sz[1] * 8));
1410                 word[startword+1] |= tmpw >> (sz[0] * 8);
1411         }
1412
1413         for (i = 0; i < loop; i++) {
1414                 temp = off8 + (i << shift_amount);
1415                 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp);
1416                 temp = 0;
1417                 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp);
1418                 temp = word[i * scale] & 0xffffffff;
1419                 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp);
1420                 temp = (word[i * scale] >> 32) & 0xffffffff;
1421                 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp);
1422                 temp = word[i*scale + 1] & 0xffffffff;
1423                 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_WRDATA_UPPER_LO,
1424                     temp);
1425                 temp = (word[i*scale + 1] >> 32) & 0xffffffff;
1426                 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_WRDATA_UPPER_HI,
1427                     temp);
1428
1429                 temp = MIU_TA_CTL_WRITE_ENABLE;
1430                 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp);
1431                 temp = MIU_TA_CTL_WRITE_START;
1432                 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp);
1433
1434                 for (j = 0; j < MAX_CTL_CHECK; j++) {
1435                         temp = qla4_82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
1436                         if ((temp & MIU_TA_CTL_BUSY) == 0)
1437                                 break;
1438                 }
1439
1440                 if (j >= MAX_CTL_CHECK) {
1441                         if (printk_ratelimit())
1442                                 ql4_printk(KERN_ERR, ha,
1443                                            "%s: failed to read through agent\n",
1444                                            __func__);
1445                         ret = -1;
1446                         break;
1447                 }
1448         }
1449
1450         return ret;
1451 }
1452
1453 static int qla4_82xx_cmdpeg_ready(struct scsi_qla_host *ha, int pegtune_val)
1454 {
1455         u32 val = 0;
1456         int retries = 60;
1457
1458         if (!pegtune_val) {
1459                 do {
1460                         val = qla4_82xx_rd_32(ha, CRB_CMDPEG_STATE);
1461                         if ((val == PHAN_INITIALIZE_COMPLETE) ||
1462                             (val == PHAN_INITIALIZE_ACK))
1463                                 return 0;
1464                         set_current_state(TASK_UNINTERRUPTIBLE);
1465                         schedule_timeout(500);
1466
1467                 } while (--retries);
1468
1469                 if (!retries) {
1470                         pegtune_val = qla4_82xx_rd_32(ha,
1471                                 QLA82XX_ROMUSB_GLB_PEGTUNE_DONE);
1472                         printk(KERN_WARNING "%s: init failed, "
1473                                 "pegtune_val = %x\n", __func__, pegtune_val);
1474                         return -1;
1475                 }
1476         }
1477         return 0;
1478 }
1479
1480 static int qla4_82xx_rcvpeg_ready(struct scsi_qla_host *ha)
1481 {
1482         uint32_t state = 0;
1483         int loops = 0;
1484
1485         /* Window 1 call */
1486         read_lock(&ha->hw_lock);
1487         state = qla4_82xx_rd_32(ha, CRB_RCVPEG_STATE);
1488         read_unlock(&ha->hw_lock);
1489
1490         while ((state != PHAN_PEG_RCV_INITIALIZED) && (loops < 30000)) {
1491                 udelay(100);
1492                 /* Window 1 call */
1493                 read_lock(&ha->hw_lock);
1494                 state = qla4_82xx_rd_32(ha, CRB_RCVPEG_STATE);
1495                 read_unlock(&ha->hw_lock);
1496
1497                 loops++;
1498         }
1499
1500         if (loops >= 30000) {
1501                 DEBUG2(ql4_printk(KERN_INFO, ha,
1502                     "Receive Peg initialization not complete: 0x%x.\n", state));
1503                 return QLA_ERROR;
1504         }
1505
1506         return QLA_SUCCESS;
1507 }
1508
1509 void
1510 qla4_8xxx_set_drv_active(struct scsi_qla_host *ha)
1511 {
1512         uint32_t drv_active;
1513
1514         drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
1515
1516         /*
1517          * For ISP8324 and ISP8042, drv_active register has 1 bit per function,
1518          * shift 1 by func_num to set a bit for the function.
1519          * For ISP8022, drv_active has 4 bits per function
1520          */
1521         if (is_qla8032(ha) || is_qla8042(ha))
1522                 drv_active |= (1 << ha->func_num);
1523         else
1524                 drv_active |= (1 << (ha->func_num * 4));
1525
1526         ql4_printk(KERN_INFO, ha, "%s(%ld): drv_active: 0x%08x\n",
1527                    __func__, ha->host_no, drv_active);
1528         qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_ACTIVE, drv_active);
1529 }
1530
1531 void
1532 qla4_8xxx_clear_drv_active(struct scsi_qla_host *ha)
1533 {
1534         uint32_t drv_active;
1535
1536         drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
1537
1538         /*
1539          * For ISP8324 and ISP8042, drv_active register has 1 bit per function,
1540          * shift 1 by func_num to set a bit for the function.
1541          * For ISP8022, drv_active has 4 bits per function
1542          */
1543         if (is_qla8032(ha) || is_qla8042(ha))
1544                 drv_active &= ~(1 << (ha->func_num));
1545         else
1546                 drv_active &= ~(1 << (ha->func_num * 4));
1547
1548         ql4_printk(KERN_INFO, ha, "%s(%ld): drv_active: 0x%08x\n",
1549                    __func__, ha->host_no, drv_active);
1550         qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_ACTIVE, drv_active);
1551 }
1552
1553 inline int qla4_8xxx_need_reset(struct scsi_qla_host *ha)
1554 {
1555         uint32_t drv_state, drv_active;
1556         int rval;
1557
1558         drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
1559         drv_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE);
1560
1561         /*
1562          * For ISP8324 and ISP8042, drv_active register has 1 bit per function,
1563          * shift 1 by func_num to set a bit for the function.
1564          * For ISP8022, drv_active has 4 bits per function
1565          */
1566         if (is_qla8032(ha) || is_qla8042(ha))
1567                 rval = drv_state & (1 << ha->func_num);
1568         else
1569                 rval = drv_state & (1 << (ha->func_num * 4));
1570
1571         if ((test_bit(AF_EEH_BUSY, &ha->flags)) && drv_active)
1572                 rval = 1;
1573
1574         return rval;
1575 }
1576
1577 void qla4_8xxx_set_rst_ready(struct scsi_qla_host *ha)
1578 {
1579         uint32_t drv_state;
1580
1581         drv_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE);
1582
1583         /*
1584          * For ISP8324 and ISP8042, drv_active register has 1 bit per function,
1585          * shift 1 by func_num to set a bit for the function.
1586          * For ISP8022, drv_active has 4 bits per function
1587          */
1588         if (is_qla8032(ha) || is_qla8042(ha))
1589                 drv_state |= (1 << ha->func_num);
1590         else
1591                 drv_state |= (1 << (ha->func_num * 4));
1592
1593         ql4_printk(KERN_INFO, ha, "%s(%ld): drv_state: 0x%08x\n",
1594                    __func__, ha->host_no, drv_state);
1595         qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_STATE, drv_state);
1596 }
1597
1598 void qla4_8xxx_clear_rst_ready(struct scsi_qla_host *ha)
1599 {
1600         uint32_t drv_state;
1601
1602         drv_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE);
1603
1604         /*
1605          * For ISP8324 and ISP8042, drv_active register has 1 bit per function,
1606          * shift 1 by func_num to set a bit for the function.
1607          * For ISP8022, drv_active has 4 bits per function
1608          */
1609         if (is_qla8032(ha) || is_qla8042(ha))
1610                 drv_state &= ~(1 << ha->func_num);
1611         else
1612                 drv_state &= ~(1 << (ha->func_num * 4));
1613
1614         ql4_printk(KERN_INFO, ha, "%s(%ld): drv_state: 0x%08x\n",
1615                    __func__, ha->host_no, drv_state);
1616         qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_STATE, drv_state);
1617 }
1618
1619 static inline void
1620 qla4_8xxx_set_qsnt_ready(struct scsi_qla_host *ha)
1621 {
1622         uint32_t qsnt_state;
1623
1624         qsnt_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE);
1625
1626         /*
1627          * For ISP8324 and ISP8042, drv_active register has 1 bit per function,
1628          * shift 1 by func_num to set a bit for the function.
1629          * For ISP8022, drv_active has 4 bits per function.
1630          */
1631         if (is_qla8032(ha) || is_qla8042(ha))
1632                 qsnt_state |= (1 << ha->func_num);
1633         else
1634                 qsnt_state |= (2 << (ha->func_num * 4));
1635
1636         qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_STATE, qsnt_state);
1637 }
1638
1639
1640 static int
1641 qla4_82xx_start_firmware(struct scsi_qla_host *ha, uint32_t image_start)
1642 {
1643         uint16_t lnk;
1644
1645         /* scrub dma mask expansion register */
1646         qla4_82xx_wr_32(ha, CRB_DMA_SHIFT, 0x55555555);
1647
1648         /* Overwrite stale initialization register values */
1649         qla4_82xx_wr_32(ha, CRB_CMDPEG_STATE, 0);
1650         qla4_82xx_wr_32(ha, CRB_RCVPEG_STATE, 0);
1651         qla4_82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0);
1652         qla4_82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0);
1653
1654         if (qla4_82xx_load_fw(ha, image_start) != QLA_SUCCESS) {
1655                 printk("%s: Error trying to start fw!\n", __func__);
1656                 return QLA_ERROR;
1657         }
1658
1659         /* Handshake with the card before we register the devices. */
1660         if (qla4_82xx_cmdpeg_ready(ha, 0) != QLA_SUCCESS) {
1661                 printk("%s: Error during card handshake!\n", __func__);
1662                 return QLA_ERROR;
1663         }
1664
1665         /* Negotiated Link width */
1666         pcie_capability_read_word(ha->pdev, PCI_EXP_LNKSTA, &lnk);
1667         ha->link_width = (lnk >> 4) & 0x3f;
1668
1669         /* Synchronize with Receive peg */
1670         return qla4_82xx_rcvpeg_ready(ha);
1671 }
1672
1673 int qla4_82xx_try_start_fw(struct scsi_qla_host *ha)
1674 {
1675         int rval = QLA_ERROR;
1676
1677         /*
1678          * FW Load priority:
1679          * 1) Operational firmware residing in flash.
1680          * 2) Fail
1681          */
1682
1683         ql4_printk(KERN_INFO, ha,
1684             "FW: Retrieving flash offsets from FLT/FDT ...\n");
1685         rval = qla4_8xxx_get_flash_info(ha);
1686         if (rval != QLA_SUCCESS)
1687                 return rval;
1688
1689         ql4_printk(KERN_INFO, ha,
1690             "FW: Attempting to load firmware from flash...\n");
1691         rval = qla4_82xx_start_firmware(ha, ha->hw.flt_region_fw);
1692
1693         if (rval != QLA_SUCCESS) {
1694                 ql4_printk(KERN_ERR, ha, "FW: Load firmware from flash"
1695                     " FAILED...\n");
1696                 return rval;
1697         }
1698
1699         return rval;
1700 }
1701
1702 void qla4_82xx_rom_lock_recovery(struct scsi_qla_host *ha)
1703 {
1704         if (qla4_82xx_rom_lock(ha)) {
1705                 /* Someone else is holding the lock. */
1706                 dev_info(&ha->pdev->dev, "Resetting rom_lock\n");
1707         }
1708
1709         /*
1710          * Either we got the lock, or someone
1711          * else died while holding it.
1712          * In either case, unlock.
1713          */
1714         qla4_82xx_rom_unlock(ha);
1715 }
1716
1717 static void qla4_8xxx_minidump_process_rdcrb(struct scsi_qla_host *ha,
1718                                 struct qla8xxx_minidump_entry_hdr *entry_hdr,
1719                                 uint32_t **d_ptr)
1720 {
1721         uint32_t r_addr, r_stride, loop_cnt, i, r_value;
1722         struct qla8xxx_minidump_entry_crb *crb_hdr;
1723         uint32_t *data_ptr = *d_ptr;
1724
1725         DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
1726         crb_hdr = (struct qla8xxx_minidump_entry_crb *)entry_hdr;
1727         r_addr = crb_hdr->addr;
1728         r_stride = crb_hdr->crb_strd.addr_stride;
1729         loop_cnt = crb_hdr->op_count;
1730
1731         for (i = 0; i < loop_cnt; i++) {
1732                 ha->isp_ops->rd_reg_indirect(ha, r_addr, &r_value);
1733                 *data_ptr++ = cpu_to_le32(r_addr);
1734                 *data_ptr++ = cpu_to_le32(r_value);
1735                 r_addr += r_stride;
1736         }
1737         *d_ptr = data_ptr;
1738 }
1739
1740 static int qla4_83xx_check_dma_engine_state(struct scsi_qla_host *ha)
1741 {
1742         int rval = QLA_SUCCESS;
1743         uint32_t dma_eng_num = 0, cmd_sts_and_cntrl = 0;
1744         uint64_t dma_base_addr = 0;
1745         struct qla4_8xxx_minidump_template_hdr *tmplt_hdr = NULL;
1746
1747         tmplt_hdr = (struct qla4_8xxx_minidump_template_hdr *)
1748                                                         ha->fw_dump_tmplt_hdr;
1749         dma_eng_num =
1750                 tmplt_hdr->saved_state_array[QLA83XX_PEX_DMA_ENGINE_INDEX];
1751         dma_base_addr = QLA83XX_PEX_DMA_BASE_ADDRESS +
1752                                 (dma_eng_num * QLA83XX_PEX_DMA_NUM_OFFSET);
1753
1754         /* Read the pex-dma's command-status-and-control register. */
1755         rval = ha->isp_ops->rd_reg_indirect(ha,
1756                         (dma_base_addr + QLA83XX_PEX_DMA_CMD_STS_AND_CNTRL),
1757                         &cmd_sts_and_cntrl);
1758
1759         if (rval)
1760                 return QLA_ERROR;
1761
1762         /* Check if requested pex-dma engine is available. */
1763         if (cmd_sts_and_cntrl & BIT_31)
1764                 return QLA_SUCCESS;
1765         else
1766                 return QLA_ERROR;
1767 }
1768
1769 static int qla4_83xx_start_pex_dma(struct scsi_qla_host *ha,
1770                            struct qla4_83xx_minidump_entry_rdmem_pex_dma *m_hdr)
1771 {
1772         int rval = QLA_SUCCESS, wait = 0;
1773         uint32_t dma_eng_num = 0, cmd_sts_and_cntrl = 0;
1774         uint64_t dma_base_addr = 0;
1775         struct qla4_8xxx_minidump_template_hdr *tmplt_hdr = NULL;
1776
1777         tmplt_hdr = (struct qla4_8xxx_minidump_template_hdr *)
1778                                                         ha->fw_dump_tmplt_hdr;
1779         dma_eng_num =
1780                 tmplt_hdr->saved_state_array[QLA83XX_PEX_DMA_ENGINE_INDEX];
1781         dma_base_addr = QLA83XX_PEX_DMA_BASE_ADDRESS +
1782                                 (dma_eng_num * QLA83XX_PEX_DMA_NUM_OFFSET);
1783
1784         rval = ha->isp_ops->wr_reg_indirect(ha,
1785                                 dma_base_addr + QLA83XX_PEX_DMA_CMD_ADDR_LOW,
1786                                 m_hdr->desc_card_addr);
1787         if (rval)
1788                 goto error_exit;
1789
1790         rval = ha->isp_ops->wr_reg_indirect(ha,
1791                               dma_base_addr + QLA83XX_PEX_DMA_CMD_ADDR_HIGH, 0);
1792         if (rval)
1793                 goto error_exit;
1794
1795         rval = ha->isp_ops->wr_reg_indirect(ha,
1796                               dma_base_addr + QLA83XX_PEX_DMA_CMD_STS_AND_CNTRL,
1797                               m_hdr->start_dma_cmd);
1798         if (rval)
1799                 goto error_exit;
1800
1801         /* Wait for dma operation to complete. */
1802         for (wait = 0; wait < QLA83XX_PEX_DMA_MAX_WAIT; wait++) {
1803                 rval = ha->isp_ops->rd_reg_indirect(ha,
1804                             (dma_base_addr + QLA83XX_PEX_DMA_CMD_STS_AND_CNTRL),
1805                             &cmd_sts_and_cntrl);
1806                 if (rval)
1807                         goto error_exit;
1808
1809                 if ((cmd_sts_and_cntrl & BIT_1) == 0)
1810                         break;
1811                 else
1812                         udelay(10);
1813         }
1814
1815         /* Wait a max of 100 ms, otherwise fallback to rdmem entry read */
1816         if (wait >= QLA83XX_PEX_DMA_MAX_WAIT) {
1817                 rval = QLA_ERROR;
1818                 goto error_exit;
1819         }
1820
1821 error_exit:
1822         return rval;
1823 }
1824
1825 static int qla4_83xx_minidump_pex_dma_read(struct scsi_qla_host *ha,
1826                                 struct qla8xxx_minidump_entry_hdr *entry_hdr,
1827                                 uint32_t **d_ptr)
1828 {
1829         int rval = QLA_SUCCESS;
1830         struct qla4_83xx_minidump_entry_rdmem_pex_dma *m_hdr = NULL;
1831         uint32_t size, read_size;
1832         uint8_t *data_ptr = (uint8_t *)*d_ptr;
1833         void *rdmem_buffer = NULL;
1834         dma_addr_t rdmem_dma;
1835         struct qla4_83xx_pex_dma_descriptor dma_desc;
1836
1837         DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
1838
1839         rval = qla4_83xx_check_dma_engine_state(ha);
1840         if (rval != QLA_SUCCESS) {
1841                 DEBUG2(ql4_printk(KERN_INFO, ha,
1842                                   "%s: DMA engine not available. Fallback to rdmem-read.\n",
1843                                   __func__));
1844                 return QLA_ERROR;
1845         }
1846
1847         m_hdr = (struct qla4_83xx_minidump_entry_rdmem_pex_dma *)entry_hdr;
1848         rdmem_buffer = dma_alloc_coherent(&ha->pdev->dev,
1849                                           QLA83XX_PEX_DMA_READ_SIZE,
1850                                           &rdmem_dma, GFP_KERNEL);
1851         if (!rdmem_buffer) {
1852                 DEBUG2(ql4_printk(KERN_INFO, ha,
1853                                   "%s: Unable to allocate rdmem dma buffer\n",
1854                                   __func__));
1855                 return QLA_ERROR;
1856         }
1857
1858         /* Prepare pex-dma descriptor to be written to MS memory. */
1859         /* dma-desc-cmd layout:
1860          *              0-3: dma-desc-cmd 0-3
1861          *              4-7: pcid function number
1862          *              8-15: dma-desc-cmd 8-15
1863          */
1864         dma_desc.cmd.dma_desc_cmd = (m_hdr->dma_desc_cmd & 0xff0f);
1865         dma_desc.cmd.dma_desc_cmd |= ((PCI_FUNC(ha->pdev->devfn) & 0xf) << 0x4);
1866         dma_desc.dma_bus_addr = rdmem_dma;
1867
1868         size = 0;
1869         read_size = 0;
1870         /*
1871          * Perform rdmem operation using pex-dma.
1872          * Prepare dma in chunks of QLA83XX_PEX_DMA_READ_SIZE.
1873          */
1874         while (read_size < m_hdr->read_data_size) {
1875                 if (m_hdr->read_data_size - read_size >=
1876                     QLA83XX_PEX_DMA_READ_SIZE)
1877                         size = QLA83XX_PEX_DMA_READ_SIZE;
1878                 else {
1879                         size = (m_hdr->read_data_size - read_size);
1880
1881                         if (rdmem_buffer)
1882                                 dma_free_coherent(&ha->pdev->dev,
1883                                                   QLA83XX_PEX_DMA_READ_SIZE,
1884                                                   rdmem_buffer, rdmem_dma);
1885
1886                         rdmem_buffer = dma_alloc_coherent(&ha->pdev->dev, size,
1887                                                           &rdmem_dma,
1888                                                           GFP_KERNEL);
1889                         if (!rdmem_buffer) {
1890                                 DEBUG2(ql4_printk(KERN_INFO, ha,
1891                                                   "%s: Unable to allocate rdmem dma buffer\n",
1892                                                   __func__));
1893                                 return QLA_ERROR;
1894                         }
1895                         dma_desc.dma_bus_addr = rdmem_dma;
1896                 }
1897
1898                 dma_desc.src_addr = m_hdr->read_addr + read_size;
1899                 dma_desc.cmd.read_data_size = size;
1900
1901                 /* Prepare: Write pex-dma descriptor to MS memory. */
1902                 rval = qla4_83xx_ms_mem_write_128b(ha,
1903                               (uint64_t)m_hdr->desc_card_addr,
1904                               (uint32_t *)&dma_desc,
1905                               (sizeof(struct qla4_83xx_pex_dma_descriptor)/16));
1906                 if (rval == -1) {
1907                         ql4_printk(KERN_INFO, ha,
1908                                    "%s: Error writing rdmem-dma-init to MS !!!\n",
1909                                    __func__);
1910                         goto error_exit;
1911                 }
1912
1913                 DEBUG2(ql4_printk(KERN_INFO, ha,
1914                                   "%s: Dma-desc: Instruct for rdmem dma (size 0x%x).\n",
1915                                   __func__, size));
1916                 /* Execute: Start pex-dma operation. */
1917                 rval = qla4_83xx_start_pex_dma(ha, m_hdr);
1918                 if (rval != QLA_SUCCESS) {
1919                         DEBUG2(ql4_printk(KERN_INFO, ha,
1920                                           "scsi(%ld): start-pex-dma failed rval=0x%x\n",
1921                                           ha->host_no, rval));
1922                         goto error_exit;
1923                 }
1924
1925                 memcpy(data_ptr, rdmem_buffer, size);
1926                 data_ptr += size;
1927                 read_size += size;
1928         }
1929
1930         DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s\n", __func__));
1931
1932         *d_ptr = (uint32_t *)data_ptr;
1933
1934 error_exit:
1935         if (rdmem_buffer)
1936                 dma_free_coherent(&ha->pdev->dev, size, rdmem_buffer,
1937                                   rdmem_dma);
1938
1939         return rval;
1940 }
1941
1942 static int qla4_8xxx_minidump_process_l2tag(struct scsi_qla_host *ha,
1943                                  struct qla8xxx_minidump_entry_hdr *entry_hdr,
1944                                  uint32_t **d_ptr)
1945 {
1946         uint32_t addr, r_addr, c_addr, t_r_addr;
1947         uint32_t i, k, loop_count, t_value, r_cnt, r_value;
1948         unsigned long p_wait, w_time, p_mask;
1949         uint32_t c_value_w, c_value_r;
1950         struct qla8xxx_minidump_entry_cache *cache_hdr;
1951         int rval = QLA_ERROR;
1952         uint32_t *data_ptr = *d_ptr;
1953
1954         DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
1955         cache_hdr = (struct qla8xxx_minidump_entry_cache *)entry_hdr;
1956
1957         loop_count = cache_hdr->op_count;
1958         r_addr = cache_hdr->read_addr;
1959         c_addr = cache_hdr->control_addr;
1960         c_value_w = cache_hdr->cache_ctrl.write_value;
1961
1962         t_r_addr = cache_hdr->tag_reg_addr;
1963         t_value = cache_hdr->addr_ctrl.init_tag_value;
1964         r_cnt = cache_hdr->read_ctrl.read_addr_cnt;
1965         p_wait = cache_hdr->cache_ctrl.poll_wait;
1966         p_mask = cache_hdr->cache_ctrl.poll_mask;
1967
1968         for (i = 0; i < loop_count; i++) {
1969                 ha->isp_ops->wr_reg_indirect(ha, t_r_addr, t_value);
1970
1971                 if (c_value_w)
1972                         ha->isp_ops->wr_reg_indirect(ha, c_addr, c_value_w);
1973
1974                 if (p_mask) {
1975                         w_time = jiffies + p_wait;
1976                         do {
1977                                 ha->isp_ops->rd_reg_indirect(ha, c_addr,
1978                                                              &c_value_r);
1979                                 if ((c_value_r & p_mask) == 0) {
1980                                         break;
1981                                 } else if (time_after_eq(jiffies, w_time)) {
1982                                         /* capturing dump failed */
1983                                         return rval;
1984                                 }
1985                         } while (1);
1986                 }
1987
1988                 addr = r_addr;
1989                 for (k = 0; k < r_cnt; k++) {
1990                         ha->isp_ops->rd_reg_indirect(ha, addr, &r_value);
1991                         *data_ptr++ = cpu_to_le32(r_value);
1992                         addr += cache_hdr->read_ctrl.read_addr_stride;
1993                 }
1994
1995                 t_value += cache_hdr->addr_ctrl.tag_value_stride;
1996         }
1997         *d_ptr = data_ptr;
1998         return QLA_SUCCESS;
1999 }
2000
2001 static int qla4_8xxx_minidump_process_control(struct scsi_qla_host *ha,
2002                                 struct qla8xxx_minidump_entry_hdr *entry_hdr)
2003 {
2004         struct qla8xxx_minidump_entry_crb *crb_entry;
2005         uint32_t read_value, opcode, poll_time, addr, index, rval = QLA_SUCCESS;
2006         uint32_t crb_addr;
2007         unsigned long wtime;
2008         struct qla4_8xxx_minidump_template_hdr *tmplt_hdr;
2009         int i;
2010
2011         DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
2012         tmplt_hdr = (struct qla4_8xxx_minidump_template_hdr *)
2013                                                 ha->fw_dump_tmplt_hdr;
2014         crb_entry = (struct qla8xxx_minidump_entry_crb *)entry_hdr;
2015
2016         crb_addr = crb_entry->addr;
2017         for (i = 0; i < crb_entry->op_count; i++) {
2018                 opcode = crb_entry->crb_ctrl.opcode;
2019                 if (opcode & QLA8XXX_DBG_OPCODE_WR) {
2020                         ha->isp_ops->wr_reg_indirect(ha, crb_addr,
2021                                                      crb_entry->value_1);
2022                         opcode &= ~QLA8XXX_DBG_OPCODE_WR;
2023                 }
2024                 if (opcode & QLA8XXX_DBG_OPCODE_RW) {
2025                         ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value);
2026                         ha->isp_ops->wr_reg_indirect(ha, crb_addr, read_value);
2027                         opcode &= ~QLA8XXX_DBG_OPCODE_RW;
2028                 }
2029                 if (opcode & QLA8XXX_DBG_OPCODE_AND) {
2030                         ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value);
2031                         read_value &= crb_entry->value_2;
2032                         opcode &= ~QLA8XXX_DBG_OPCODE_AND;
2033                         if (opcode & QLA8XXX_DBG_OPCODE_OR) {
2034                                 read_value |= crb_entry->value_3;
2035                                 opcode &= ~QLA8XXX_DBG_OPCODE_OR;
2036                         }
2037                         ha->isp_ops->wr_reg_indirect(ha, crb_addr, read_value);
2038                 }
2039                 if (opcode & QLA8XXX_DBG_OPCODE_OR) {
2040                         ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value);
2041                         read_value |= crb_entry->value_3;
2042                         ha->isp_ops->wr_reg_indirect(ha, crb_addr, read_value);
2043                         opcode &= ~QLA8XXX_DBG_OPCODE_OR;
2044                 }
2045                 if (opcode & QLA8XXX_DBG_OPCODE_POLL) {
2046                         poll_time = crb_entry->crb_strd.poll_timeout;
2047                         wtime = jiffies + poll_time;
2048                         ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value);
2049
2050                         do {
2051                                 if ((read_value & crb_entry->value_2) ==
2052                                     crb_entry->value_1) {
2053                                         break;
2054                                 } else if (time_after_eq(jiffies, wtime)) {
2055                                         /* capturing dump failed */
2056                                         rval = QLA_ERROR;
2057                                         break;
2058                                 } else {
2059                                         ha->isp_ops->rd_reg_indirect(ha,
2060                                                         crb_addr, &read_value);
2061                                 }
2062                         } while (1);
2063                         opcode &= ~QLA8XXX_DBG_OPCODE_POLL;
2064                 }
2065
2066                 if (opcode & QLA8XXX_DBG_OPCODE_RDSTATE) {
2067                         if (crb_entry->crb_strd.state_index_a) {
2068                                 index = crb_entry->crb_strd.state_index_a;
2069                                 addr = tmplt_hdr->saved_state_array[index];
2070                         } else {
2071                                 addr = crb_addr;
2072                         }
2073
2074                         ha->isp_ops->rd_reg_indirect(ha, addr, &read_value);
2075                         index = crb_entry->crb_ctrl.state_index_v;
2076                         tmplt_hdr->saved_state_array[index] = read_value;
2077                         opcode &= ~QLA8XXX_DBG_OPCODE_RDSTATE;
2078                 }
2079
2080                 if (opcode & QLA8XXX_DBG_OPCODE_WRSTATE) {
2081                         if (crb_entry->crb_strd.state_index_a) {
2082                                 index = crb_entry->crb_strd.state_index_a;
2083                                 addr = tmplt_hdr->saved_state_array[index];
2084                         } else {
2085                                 addr = crb_addr;
2086                         }
2087
2088                         if (crb_entry->crb_ctrl.state_index_v) {
2089                                 index = crb_entry->crb_ctrl.state_index_v;
2090                                 read_value =
2091                                         tmplt_hdr->saved_state_array[index];
2092                         } else {
2093                                 read_value = crb_entry->value_1;
2094                         }
2095
2096                         ha->isp_ops->wr_reg_indirect(ha, addr, read_value);
2097                         opcode &= ~QLA8XXX_DBG_OPCODE_WRSTATE;
2098                 }
2099
2100                 if (opcode & QLA8XXX_DBG_OPCODE_MDSTATE) {
2101                         index = crb_entry->crb_ctrl.state_index_v;
2102                         read_value = tmplt_hdr->saved_state_array[index];
2103                         read_value <<= crb_entry->crb_ctrl.shl;
2104                         read_value >>= crb_entry->crb_ctrl.shr;
2105                         if (crb_entry->value_2)
2106                                 read_value &= crb_entry->value_2;
2107                         read_value |= crb_entry->value_3;
2108                         read_value += crb_entry->value_1;
2109                         tmplt_hdr->saved_state_array[index] = read_value;
2110                         opcode &= ~QLA8XXX_DBG_OPCODE_MDSTATE;
2111                 }
2112                 crb_addr += crb_entry->crb_strd.addr_stride;
2113         }
2114         DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s\n", __func__));
2115         return rval;
2116 }
2117
2118 static void qla4_8xxx_minidump_process_rdocm(struct scsi_qla_host *ha,
2119                                 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2120                                 uint32_t **d_ptr)
2121 {
2122         uint32_t r_addr, r_stride, loop_cnt, i, r_value;
2123         struct qla8xxx_minidump_entry_rdocm *ocm_hdr;
2124         uint32_t *data_ptr = *d_ptr;
2125
2126         DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
2127         ocm_hdr = (struct qla8xxx_minidump_entry_rdocm *)entry_hdr;
2128         r_addr = ocm_hdr->read_addr;
2129         r_stride = ocm_hdr->read_addr_stride;
2130         loop_cnt = ocm_hdr->op_count;
2131
2132         DEBUG2(ql4_printk(KERN_INFO, ha,
2133                           "[%s]: r_addr: 0x%x, r_stride: 0x%x, loop_cnt: 0x%x\n",
2134                           __func__, r_addr, r_stride, loop_cnt));
2135
2136         for (i = 0; i < loop_cnt; i++) {
2137                 r_value = readl((void __iomem *)(r_addr + ha->nx_pcibase));
2138                 *data_ptr++ = cpu_to_le32(r_value);
2139                 r_addr += r_stride;
2140         }
2141         DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s datacount: 0x%lx\n",
2142                 __func__, (long unsigned int) (loop_cnt * sizeof(uint32_t))));
2143         *d_ptr = data_ptr;
2144 }
2145
2146 static void qla4_8xxx_minidump_process_rdmux(struct scsi_qla_host *ha,
2147                                 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2148                                 uint32_t **d_ptr)
2149 {
2150         uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value;
2151         struct qla8xxx_minidump_entry_mux *mux_hdr;
2152         uint32_t *data_ptr = *d_ptr;
2153
2154         DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
2155         mux_hdr = (struct qla8xxx_minidump_entry_mux *)entry_hdr;
2156         r_addr = mux_hdr->read_addr;
2157         s_addr = mux_hdr->select_addr;
2158         s_stride = mux_hdr->select_value_stride;
2159         s_value = mux_hdr->select_value;
2160         loop_cnt = mux_hdr->op_count;
2161
2162         for (i = 0; i < loop_cnt; i++) {
2163                 ha->isp_ops->wr_reg_indirect(ha, s_addr, s_value);
2164                 ha->isp_ops->rd_reg_indirect(ha, r_addr, &r_value);
2165                 *data_ptr++ = cpu_to_le32(s_value);
2166                 *data_ptr++ = cpu_to_le32(r_value);
2167                 s_value += s_stride;
2168         }
2169         *d_ptr = data_ptr;
2170 }
2171
2172 static void qla4_8xxx_minidump_process_l1cache(struct scsi_qla_host *ha,
2173                                 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2174                                 uint32_t **d_ptr)
2175 {
2176         uint32_t addr, r_addr, c_addr, t_r_addr;
2177         uint32_t i, k, loop_count, t_value, r_cnt, r_value;
2178         uint32_t c_value_w;
2179         struct qla8xxx_minidump_entry_cache *cache_hdr;
2180         uint32_t *data_ptr = *d_ptr;
2181
2182         cache_hdr = (struct qla8xxx_minidump_entry_cache *)entry_hdr;
2183         loop_count = cache_hdr->op_count;
2184         r_addr = cache_hdr->read_addr;
2185         c_addr = cache_hdr->control_addr;
2186         c_value_w = cache_hdr->cache_ctrl.write_value;
2187
2188         t_r_addr = cache_hdr->tag_reg_addr;
2189         t_value = cache_hdr->addr_ctrl.init_tag_value;
2190         r_cnt = cache_hdr->read_ctrl.read_addr_cnt;
2191
2192         for (i = 0; i < loop_count; i++) {
2193                 ha->isp_ops->wr_reg_indirect(ha, t_r_addr, t_value);
2194                 ha->isp_ops->wr_reg_indirect(ha, c_addr, c_value_w);
2195                 addr = r_addr;
2196                 for (k = 0; k < r_cnt; k++) {
2197                         ha->isp_ops->rd_reg_indirect(ha, addr, &r_value);
2198                         *data_ptr++ = cpu_to_le32(r_value);
2199                         addr += cache_hdr->read_ctrl.read_addr_stride;
2200                 }
2201                 t_value += cache_hdr->addr_ctrl.tag_value_stride;
2202         }
2203         *d_ptr = data_ptr;
2204 }
2205
2206 static void qla4_8xxx_minidump_process_queue(struct scsi_qla_host *ha,
2207                                 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2208                                 uint32_t **d_ptr)
2209 {
2210         uint32_t s_addr, r_addr;
2211         uint32_t r_stride, r_value, r_cnt, qid = 0;
2212         uint32_t i, k, loop_cnt;
2213         struct qla8xxx_minidump_entry_queue *q_hdr;
2214         uint32_t *data_ptr = *d_ptr;
2215
2216         DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
2217         q_hdr = (struct qla8xxx_minidump_entry_queue *)entry_hdr;
2218         s_addr = q_hdr->select_addr;
2219         r_cnt = q_hdr->rd_strd.read_addr_cnt;
2220         r_stride = q_hdr->rd_strd.read_addr_stride;
2221         loop_cnt = q_hdr->op_count;
2222
2223         for (i = 0; i < loop_cnt; i++) {
2224                 ha->isp_ops->wr_reg_indirect(ha, s_addr, qid);
2225                 r_addr = q_hdr->read_addr;
2226                 for (k = 0; k < r_cnt; k++) {
2227                         ha->isp_ops->rd_reg_indirect(ha, r_addr, &r_value);
2228                         *data_ptr++ = cpu_to_le32(r_value);
2229                         r_addr += r_stride;
2230                 }
2231                 qid += q_hdr->q_strd.queue_id_stride;
2232         }
2233         *d_ptr = data_ptr;
2234 }
2235
2236 #define MD_DIRECT_ROM_WINDOW            0x42110030
2237 #define MD_DIRECT_ROM_READ_BASE         0x42150000
2238
2239 static void qla4_82xx_minidump_process_rdrom(struct scsi_qla_host *ha,
2240                                 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2241                                 uint32_t **d_ptr)
2242 {
2243         uint32_t r_addr, r_value;
2244         uint32_t i, loop_cnt;
2245         struct qla8xxx_minidump_entry_rdrom *rom_hdr;
2246         uint32_t *data_ptr = *d_ptr;
2247
2248         DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
2249         rom_hdr = (struct qla8xxx_minidump_entry_rdrom *)entry_hdr;
2250         r_addr = rom_hdr->read_addr;
2251         loop_cnt = rom_hdr->read_data_size/sizeof(uint32_t);
2252
2253         DEBUG2(ql4_printk(KERN_INFO, ha,
2254                           "[%s]: flash_addr: 0x%x, read_data_size: 0x%x\n",
2255                            __func__, r_addr, loop_cnt));
2256
2257         for (i = 0; i < loop_cnt; i++) {
2258                 ha->isp_ops->wr_reg_indirect(ha, MD_DIRECT_ROM_WINDOW,
2259                                              (r_addr & 0xFFFF0000));
2260                 ha->isp_ops->rd_reg_indirect(ha,
2261                                 MD_DIRECT_ROM_READ_BASE + (r_addr & 0x0000FFFF),
2262                                 &r_value);
2263                 *data_ptr++ = cpu_to_le32(r_value);
2264                 r_addr += sizeof(uint32_t);
2265         }
2266         *d_ptr = data_ptr;
2267 }
2268
2269 #define MD_MIU_TEST_AGT_CTRL            0x41000090
2270 #define MD_MIU_TEST_AGT_ADDR_LO         0x41000094
2271 #define MD_MIU_TEST_AGT_ADDR_HI         0x41000098
2272
2273 static int __qla4_8xxx_minidump_process_rdmem(struct scsi_qla_host *ha,
2274                                 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2275                                 uint32_t **d_ptr)
2276 {
2277         uint32_t r_addr, r_value, r_data;
2278         uint32_t i, j, loop_cnt;
2279         struct qla8xxx_minidump_entry_rdmem *m_hdr;
2280         unsigned long flags;
2281         uint32_t *data_ptr = *d_ptr;
2282
2283         DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
2284         m_hdr = (struct qla8xxx_minidump_entry_rdmem *)entry_hdr;
2285         r_addr = m_hdr->read_addr;
2286         loop_cnt = m_hdr->read_data_size/16;
2287
2288         DEBUG2(ql4_printk(KERN_INFO, ha,
2289                           "[%s]: Read addr: 0x%x, read_data_size: 0x%x\n",
2290                           __func__, r_addr, m_hdr->read_data_size));
2291
2292         if (r_addr & 0xf) {
2293                 DEBUG2(ql4_printk(KERN_INFO, ha,
2294                                   "[%s]: Read addr 0x%x not 16 bytes aligned\n",
2295                                   __func__, r_addr));
2296                 return QLA_ERROR;
2297         }
2298
2299         if (m_hdr->read_data_size % 16) {
2300                 DEBUG2(ql4_printk(KERN_INFO, ha,
2301                                   "[%s]: Read data[0x%x] not multiple of 16 bytes\n",
2302                                   __func__, m_hdr->read_data_size));
2303                 return QLA_ERROR;
2304         }
2305
2306         DEBUG2(ql4_printk(KERN_INFO, ha,
2307                           "[%s]: rdmem_addr: 0x%x, read_data_size: 0x%x, loop_cnt: 0x%x\n",
2308                           __func__, r_addr, m_hdr->read_data_size, loop_cnt));
2309
2310         write_lock_irqsave(&ha->hw_lock, flags);
2311         for (i = 0; i < loop_cnt; i++) {
2312                 ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_ADDR_LO,
2313                                              r_addr);
2314                 r_value = 0;
2315                 ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_ADDR_HI,
2316                                              r_value);
2317                 r_value = MIU_TA_CTL_ENABLE;
2318                 ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_CTRL, r_value);
2319                 r_value = MIU_TA_CTL_START_ENABLE;
2320                 ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_CTRL, r_value);
2321
2322                 for (j = 0; j < MAX_CTL_CHECK; j++) {
2323                         ha->isp_ops->rd_reg_indirect(ha, MD_MIU_TEST_AGT_CTRL,
2324                                                      &r_value);
2325                         if ((r_value & MIU_TA_CTL_BUSY) == 0)
2326                                 break;
2327                 }
2328
2329                 if (j >= MAX_CTL_CHECK) {
2330                         printk_ratelimited(KERN_ERR
2331                                            "%s: failed to read through agent\n",
2332                                             __func__);
2333                         write_unlock_irqrestore(&ha->hw_lock, flags);
2334                         return QLA_SUCCESS;
2335                 }
2336
2337                 for (j = 0; j < 4; j++) {
2338                         ha->isp_ops->rd_reg_indirect(ha,
2339                                                      MD_MIU_TEST_AGT_RDDATA[j],
2340                                                      &r_data);
2341                         *data_ptr++ = cpu_to_le32(r_data);
2342                 }
2343
2344                 r_addr += 16;
2345         }
2346         write_unlock_irqrestore(&ha->hw_lock, flags);
2347
2348         DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s datacount: 0x%x\n",
2349                           __func__, (loop_cnt * 16)));
2350
2351         *d_ptr = data_ptr;
2352         return QLA_SUCCESS;
2353 }
2354
2355 static int qla4_8xxx_minidump_process_rdmem(struct scsi_qla_host *ha,
2356                                 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2357                                 uint32_t **d_ptr)
2358 {
2359         uint32_t *data_ptr = *d_ptr;
2360         int rval = QLA_SUCCESS;
2361
2362         if (is_qla8032(ha) || is_qla8042(ha)) {
2363                 rval = qla4_83xx_minidump_pex_dma_read(ha, entry_hdr,
2364                                                        &data_ptr);
2365                 if (rval != QLA_SUCCESS) {
2366                         rval = __qla4_8xxx_minidump_process_rdmem(ha, entry_hdr,
2367                                                                   &data_ptr);
2368                 }
2369         } else {
2370                 rval = __qla4_8xxx_minidump_process_rdmem(ha, entry_hdr,
2371                                                           &data_ptr);
2372         }
2373         *d_ptr = data_ptr;
2374         return rval;
2375 }
2376
2377 static void qla4_8xxx_mark_entry_skipped(struct scsi_qla_host *ha,
2378                                 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2379                                 int index)
2380 {
2381         entry_hdr->d_ctrl.driver_flags |= QLA8XXX_DBG_SKIPPED_FLAG;
2382         DEBUG2(ql4_printk(KERN_INFO, ha,
2383                           "scsi(%ld): Skipping entry[%d]: ETYPE[0x%x]-ELEVEL[0x%x]\n",
2384                           ha->host_no, index, entry_hdr->entry_type,
2385                           entry_hdr->d_ctrl.entry_capture_mask));
2386 }
2387
2388 /* ISP83xx functions to process new minidump entries... */
2389 static uint32_t qla83xx_minidump_process_pollrd(struct scsi_qla_host *ha,
2390                                 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2391                                 uint32_t **d_ptr)
2392 {
2393         uint32_t r_addr, s_addr, s_value, r_value, poll_wait, poll_mask;
2394         uint16_t s_stride, i;
2395         uint32_t *data_ptr = *d_ptr;
2396         uint32_t rval = QLA_SUCCESS;
2397         struct qla83xx_minidump_entry_pollrd *pollrd_hdr;
2398
2399         pollrd_hdr = (struct qla83xx_minidump_entry_pollrd *)entry_hdr;
2400         s_addr = le32_to_cpu(pollrd_hdr->select_addr);
2401         r_addr = le32_to_cpu(pollrd_hdr->read_addr);
2402         s_value = le32_to_cpu(pollrd_hdr->select_value);
2403         s_stride = le32_to_cpu(pollrd_hdr->select_value_stride);
2404
2405         poll_wait = le32_to_cpu(pollrd_hdr->poll_wait);
2406         poll_mask = le32_to_cpu(pollrd_hdr->poll_mask);
2407
2408         for (i = 0; i < le32_to_cpu(pollrd_hdr->op_count); i++) {
2409                 ha->isp_ops->wr_reg_indirect(ha, s_addr, s_value);
2410                 poll_wait = le32_to_cpu(pollrd_hdr->poll_wait);
2411                 while (1) {
2412                         ha->isp_ops->rd_reg_indirect(ha, s_addr, &r_value);
2413
2414                         if ((r_value & poll_mask) != 0) {
2415                                 break;
2416                         } else {
2417                                 msleep(1);
2418                                 if (--poll_wait == 0) {
2419                                         ql4_printk(KERN_ERR, ha, "%s: TIMEOUT\n",
2420                                                    __func__);
2421                                         rval = QLA_ERROR;
2422                                         goto exit_process_pollrd;
2423                                 }
2424                         }
2425                 }
2426                 ha->isp_ops->rd_reg_indirect(ha, r_addr, &r_value);
2427                 *data_ptr++ = cpu_to_le32(s_value);
2428                 *data_ptr++ = cpu_to_le32(r_value);
2429                 s_value += s_stride;
2430         }
2431
2432         *d_ptr = data_ptr;
2433
2434 exit_process_pollrd:
2435         return rval;
2436 }
2437
2438 static void qla83xx_minidump_process_rdmux2(struct scsi_qla_host *ha,
2439                                 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2440                                 uint32_t **d_ptr)
2441 {
2442         uint32_t sel_val1, sel_val2, t_sel_val, data, i;
2443         uint32_t sel_addr1, sel_addr2, sel_val_mask, read_addr;
2444         struct qla83xx_minidump_entry_rdmux2 *rdmux2_hdr;
2445         uint32_t *data_ptr = *d_ptr;
2446
2447         rdmux2_hdr = (struct qla83xx_minidump_entry_rdmux2 *)entry_hdr;
2448         sel_val1 = le32_to_cpu(rdmux2_hdr->select_value_1);
2449         sel_val2 = le32_to_cpu(rdmux2_hdr->select_value_2);
2450         sel_addr1 = le32_to_cpu(rdmux2_hdr->select_addr_1);
2451         sel_addr2 = le32_to_cpu(rdmux2_hdr->select_addr_2);
2452         sel_val_mask = le32_to_cpu(rdmux2_hdr->select_value_mask);
2453         read_addr = le32_to_cpu(rdmux2_hdr->read_addr);
2454
2455         for (i = 0; i < rdmux2_hdr->op_count; i++) {
2456                 ha->isp_ops->wr_reg_indirect(ha, sel_addr1, sel_val1);
2457                 t_sel_val = sel_val1 & sel_val_mask;
2458                 *data_ptr++ = cpu_to_le32(t_sel_val);
2459
2460                 ha->isp_ops->wr_reg_indirect(ha, sel_addr2, t_sel_val);
2461                 ha->isp_ops->rd_reg_indirect(ha, read_addr, &data);
2462
2463                 *data_ptr++ = cpu_to_le32(data);
2464
2465                 ha->isp_ops->wr_reg_indirect(ha, sel_addr1, sel_val2);
2466                 t_sel_val = sel_val2 & sel_val_mask;
2467                 *data_ptr++ = cpu_to_le32(t_sel_val);
2468
2469                 ha->isp_ops->wr_reg_indirect(ha, sel_addr2, t_sel_val);
2470                 ha->isp_ops->rd_reg_indirect(ha, read_addr, &data);
2471
2472                 *data_ptr++ = cpu_to_le32(data);
2473
2474                 sel_val1 += rdmux2_hdr->select_value_stride;
2475                 sel_val2 += rdmux2_hdr->select_value_stride;
2476         }
2477
2478         *d_ptr = data_ptr;
2479 }
2480
2481 static uint32_t qla83xx_minidump_process_pollrdmwr(struct scsi_qla_host *ha,
2482                                 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2483                                 uint32_t **d_ptr)
2484 {
2485         uint32_t poll_wait, poll_mask, r_value, data;
2486         uint32_t addr_1, addr_2, value_1, value_2;
2487         uint32_t *data_ptr = *d_ptr;
2488         uint32_t rval = QLA_SUCCESS;
2489         struct qla83xx_minidump_entry_pollrdmwr *poll_hdr;
2490
2491         poll_hdr = (struct qla83xx_minidump_entry_pollrdmwr *)entry_hdr;
2492         addr_1 = le32_to_cpu(poll_hdr->addr_1);
2493         addr_2 = le32_to_cpu(poll_hdr->addr_2);
2494         value_1 = le32_to_cpu(poll_hdr->value_1);
2495         value_2 = le32_to_cpu(poll_hdr->value_2);
2496         poll_mask = le32_to_cpu(poll_hdr->poll_mask);
2497
2498         ha->isp_ops->wr_reg_indirect(ha, addr_1, value_1);
2499
2500         poll_wait = le32_to_cpu(poll_hdr->poll_wait);
2501         while (1) {
2502                 ha->isp_ops->rd_reg_indirect(ha, addr_1, &r_value);
2503
2504                 if ((r_value & poll_mask) != 0) {
2505                         break;
2506                 } else {
2507                         msleep(1);
2508                         if (--poll_wait == 0) {
2509                                 ql4_printk(KERN_ERR, ha, "%s: TIMEOUT_1\n",
2510                                            __func__);
2511                                 rval = QLA_ERROR;
2512                                 goto exit_process_pollrdmwr;
2513                         }
2514                 }
2515         }
2516
2517         ha->isp_ops->rd_reg_indirect(ha, addr_2, &data);
2518         data &= le32_to_cpu(poll_hdr->modify_mask);
2519         ha->isp_ops->wr_reg_indirect(ha, addr_2, data);
2520         ha->isp_ops->wr_reg_indirect(ha, addr_1, value_2);
2521
2522         poll_wait = le32_to_cpu(poll_hdr->poll_wait);
2523         while (1) {
2524                 ha->isp_ops->rd_reg_indirect(ha, addr_1, &r_value);
2525
2526                 if ((r_value & poll_mask) != 0) {
2527                         break;
2528                 } else {
2529                         msleep(1);
2530                         if (--poll_wait == 0) {
2531                                 ql4_printk(KERN_ERR, ha, "%s: TIMEOUT_2\n",
2532                                            __func__);
2533                                 rval = QLA_ERROR;
2534                                 goto exit_process_pollrdmwr;
2535                         }
2536                 }
2537         }
2538
2539         *data_ptr++ = cpu_to_le32(addr_2);
2540         *data_ptr++ = cpu_to_le32(data);
2541         *d_ptr = data_ptr;
2542
2543 exit_process_pollrdmwr:
2544         return rval;
2545 }
2546
2547 static uint32_t qla4_83xx_minidump_process_rdrom(struct scsi_qla_host *ha,
2548                                 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2549                                 uint32_t **d_ptr)
2550 {
2551         uint32_t fl_addr, u32_count, rval;
2552         struct qla8xxx_minidump_entry_rdrom *rom_hdr;
2553         uint32_t *data_ptr = *d_ptr;
2554
2555         rom_hdr = (struct qla8xxx_minidump_entry_rdrom *)entry_hdr;
2556         fl_addr = le32_to_cpu(rom_hdr->read_addr);
2557         u32_count = le32_to_cpu(rom_hdr->read_data_size)/sizeof(uint32_t);
2558
2559         DEBUG2(ql4_printk(KERN_INFO, ha, "[%s]: fl_addr: 0x%x, count: 0x%x\n",
2560                           __func__, fl_addr, u32_count));
2561
2562         rval = qla4_83xx_lockless_flash_read_u32(ha, fl_addr,
2563                                                  (u8 *)(data_ptr), u32_count);
2564
2565         if (rval == QLA_ERROR) {
2566                 ql4_printk(KERN_ERR, ha, "%s: Flash Read Error,Count=%d\n",
2567                            __func__, u32_count);
2568                 goto exit_process_rdrom;
2569         }
2570
2571         data_ptr += u32_count;
2572         *d_ptr = data_ptr;
2573
2574 exit_process_rdrom:
2575         return rval;
2576 }
2577
2578 /**
2579  * qla4_8xxx_collect_md_data - Retrieve firmware minidump data.
2580  * @ha: pointer to adapter structure
2581  **/
2582 static int qla4_8xxx_collect_md_data(struct scsi_qla_host *ha)
2583 {
2584         int num_entry_hdr = 0;
2585         struct qla8xxx_minidump_entry_hdr *entry_hdr;
2586         struct qla4_8xxx_minidump_template_hdr *tmplt_hdr;
2587         uint32_t *data_ptr;
2588         uint32_t data_collected = 0;
2589         int i, rval = QLA_ERROR;
2590         uint64_t now;
2591         uint32_t timestamp;
2592
2593         if (!ha->fw_dump) {
2594                 ql4_printk(KERN_INFO, ha, "%s(%ld) No buffer to dump\n",
2595                            __func__, ha->host_no);
2596                 return rval;
2597         }
2598
2599         tmplt_hdr = (struct qla4_8xxx_minidump_template_hdr *)
2600                                                 ha->fw_dump_tmplt_hdr;
2601         data_ptr = (uint32_t *)((uint8_t *)ha->fw_dump +
2602                                                 ha->fw_dump_tmplt_size);
2603         data_collected += ha->fw_dump_tmplt_size;
2604
2605         num_entry_hdr = tmplt_hdr->num_of_entries;
2606         ql4_printk(KERN_INFO, ha, "[%s]: starting data ptr: %p\n",
2607                    __func__, data_ptr);
2608         ql4_printk(KERN_INFO, ha,
2609                    "[%s]: no of entry headers in Template: 0x%x\n",
2610                    __func__, num_entry_hdr);
2611         ql4_printk(KERN_INFO, ha, "[%s]: Capture Mask obtained: 0x%x\n",
2612                    __func__, ha->fw_dump_capture_mask);
2613         ql4_printk(KERN_INFO, ha, "[%s]: Total_data_size 0x%x, %d obtained\n",
2614                    __func__, ha->fw_dump_size, ha->fw_dump_size);
2615
2616         /* Update current timestamp before taking dump */
2617         now = get_jiffies_64();
2618         timestamp = (u32)(jiffies_to_msecs(now) / 1000);
2619         tmplt_hdr->driver_timestamp = timestamp;
2620
2621         entry_hdr = (struct qla8xxx_minidump_entry_hdr *)
2622                                         (((uint8_t *)ha->fw_dump_tmplt_hdr) +
2623                                          tmplt_hdr->first_entry_offset);
2624
2625         if (is_qla8032(ha) || is_qla8042(ha))
2626                 tmplt_hdr->saved_state_array[QLA83XX_SS_OCM_WNDREG_INDEX] =
2627                                         tmplt_hdr->ocm_window_reg[ha->func_num];
2628
2629         /* Walk through the entry headers - validate/perform required action */
2630         for (i = 0; i < num_entry_hdr; i++) {
2631                 if (data_collected > ha->fw_dump_size) {
2632                         ql4_printk(KERN_INFO, ha,
2633                                    "Data collected: [0x%x], Total Dump size: [0x%x]\n",
2634                                    data_collected, ha->fw_dump_size);
2635                         return rval;
2636                 }
2637
2638                 if (!(entry_hdr->d_ctrl.entry_capture_mask &
2639                       ha->fw_dump_capture_mask)) {
2640                         entry_hdr->d_ctrl.driver_flags |=
2641                                                 QLA8XXX_DBG_SKIPPED_FLAG;
2642                         goto skip_nxt_entry;
2643                 }
2644
2645                 DEBUG2(ql4_printk(KERN_INFO, ha,
2646                                   "Data collected: [0x%x], Dump size left:[0x%x]\n",
2647                                   data_collected,
2648                                   (ha->fw_dump_size - data_collected)));
2649
2650                 /* Decode the entry type and take required action to capture
2651                  * debug data
2652                  */
2653                 switch (entry_hdr->entry_type) {
2654                 case QLA8XXX_RDEND:
2655                         qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
2656                         break;
2657                 case QLA8XXX_CNTRL:
2658                         rval = qla4_8xxx_minidump_process_control(ha,
2659                                                                   entry_hdr);
2660                         if (rval != QLA_SUCCESS) {
2661                                 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
2662                                 goto md_failed;
2663                         }
2664                         break;
2665                 case QLA8XXX_RDCRB:
2666                         qla4_8xxx_minidump_process_rdcrb(ha, entry_hdr,
2667                                                          &data_ptr);
2668                         break;
2669                 case QLA8XXX_RDMEM:
2670                         rval = qla4_8xxx_minidump_process_rdmem(ha, entry_hdr,
2671                                                                 &data_ptr);
2672                         if (rval != QLA_SUCCESS) {
2673                                 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
2674                                 goto md_failed;
2675                         }
2676                         break;
2677                 case QLA8XXX_BOARD:
2678                 case QLA8XXX_RDROM:
2679                         if (is_qla8022(ha)) {
2680                                 qla4_82xx_minidump_process_rdrom(ha, entry_hdr,
2681                                                                  &data_ptr);
2682                         } else if (is_qla8032(ha) || is_qla8042(ha)) {
2683                                 rval = qla4_83xx_minidump_process_rdrom(ha,
2684                                                                     entry_hdr,
2685                                                                     &data_ptr);
2686                                 if (rval != QLA_SUCCESS)
2687                                         qla4_8xxx_mark_entry_skipped(ha,
2688                                                                      entry_hdr,
2689                                                                      i);
2690                         }
2691                         break;
2692                 case QLA8XXX_L2DTG:
2693                 case QLA8XXX_L2ITG:
2694                 case QLA8XXX_L2DAT:
2695                 case QLA8XXX_L2INS:
2696                         rval = qla4_8xxx_minidump_process_l2tag(ha, entry_hdr,
2697                                                                 &data_ptr);
2698                         if (rval != QLA_SUCCESS) {
2699                                 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
2700                                 goto md_failed;
2701                         }
2702                         break;
2703                 case QLA8XXX_L1DTG:
2704                 case QLA8XXX_L1ITG:
2705                 case QLA8XXX_L1DAT:
2706                 case QLA8XXX_L1INS:
2707                         qla4_8xxx_minidump_process_l1cache(ha, entry_hdr,
2708                                                            &data_ptr);
2709                         break;
2710                 case QLA8XXX_RDOCM:
2711                         qla4_8xxx_minidump_process_rdocm(ha, entry_hdr,
2712                                                          &data_ptr);
2713                         break;
2714                 case QLA8XXX_RDMUX:
2715                         qla4_8xxx_minidump_process_rdmux(ha, entry_hdr,
2716                                                          &data_ptr);
2717                         break;
2718                 case QLA8XXX_QUEUE:
2719                         qla4_8xxx_minidump_process_queue(ha, entry_hdr,
2720                                                          &data_ptr);
2721                         break;
2722                 case QLA83XX_POLLRD:
2723                         if (is_qla8022(ha)) {
2724                                 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
2725                                 break;
2726                         }
2727                         rval = qla83xx_minidump_process_pollrd(ha, entry_hdr,
2728                                                                &data_ptr);
2729                         if (rval != QLA_SUCCESS)
2730                                 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
2731                         break;
2732                 case QLA83XX_RDMUX2:
2733                         if (is_qla8022(ha)) {
2734                                 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
2735                                 break;
2736                         }
2737                         qla83xx_minidump_process_rdmux2(ha, entry_hdr,
2738                                                         &data_ptr);
2739                         break;
2740                 case QLA83XX_POLLRDMWR:
2741                         if (is_qla8022(ha)) {
2742                                 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
2743                                 break;
2744                         }
2745                         rval = qla83xx_minidump_process_pollrdmwr(ha, entry_hdr,
2746                                                                   &data_ptr);
2747                         if (rval != QLA_SUCCESS)
2748                                 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
2749                         break;
2750                 case QLA8XXX_RDNOP:
2751                 default:
2752                         qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
2753                         break;
2754                 }
2755
2756                 data_collected = (uint8_t *)data_ptr - (uint8_t *)ha->fw_dump;
2757 skip_nxt_entry:
2758                 /*  next entry in the template */
2759                 entry_hdr = (struct qla8xxx_minidump_entry_hdr *)
2760                                 (((uint8_t *)entry_hdr) +
2761                                  entry_hdr->entry_size);
2762         }
2763
2764         if (data_collected != ha->fw_dump_size) {
2765                 ql4_printk(KERN_INFO, ha,
2766                            "Dump data mismatch: Data collected: [0x%x], total_data_size:[0x%x]\n",
2767                            data_collected, ha->fw_dump_size);
2768                 rval = QLA_ERROR;
2769                 goto md_failed;
2770         }
2771
2772         DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s Last entry: 0x%x\n",
2773                           __func__, i));
2774 md_failed:
2775         return rval;
2776 }
2777
2778 /**
2779  * qla4_8xxx_uevent_emit - Send uevent when the firmware dump is ready.
2780  * @ha: pointer to adapter structure
2781  **/
2782 static void qla4_8xxx_uevent_emit(struct scsi_qla_host *ha, u32 code)
2783 {
2784         char event_string[40];
2785         char *envp[] = { event_string, NULL };
2786
2787         switch (code) {
2788         case QL4_UEVENT_CODE_FW_DUMP:
2789                 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
2790                          ha->host_no);
2791                 break;
2792         default:
2793                 /*do nothing*/
2794                 break;
2795         }
2796
2797         kobject_uevent_env(&(&ha->pdev->dev)->kobj, KOBJ_CHANGE, envp);
2798 }
2799
2800 void qla4_8xxx_get_minidump(struct scsi_qla_host *ha)
2801 {
2802         if (ql4xenablemd && test_bit(AF_FW_RECOVERY, &ha->flags) &&
2803             !test_bit(AF_82XX_FW_DUMPED, &ha->flags)) {
2804                 if (!qla4_8xxx_collect_md_data(ha)) {
2805                         qla4_8xxx_uevent_emit(ha, QL4_UEVENT_CODE_FW_DUMP);
2806                         set_bit(AF_82XX_FW_DUMPED, &ha->flags);
2807                 } else {
2808                         ql4_printk(KERN_INFO, ha, "%s: Unable to collect minidump\n",
2809                                    __func__);
2810                 }
2811         }
2812 }
2813
2814 /**
2815  * qla4_8xxx_device_bootstrap - Initialize device, set DEV_READY, start fw
2816  * @ha: pointer to adapter structure
2817  *
2818  * Note: IDC lock must be held upon entry
2819  **/
2820 int qla4_8xxx_device_bootstrap(struct scsi_qla_host *ha)
2821 {
2822         int rval = QLA_ERROR;
2823         int i, timeout;
2824         uint32_t old_count, count, idc_ctrl;
2825         int need_reset = 0, peg_stuck = 1;
2826
2827         need_reset = ha->isp_ops->need_reset(ha);
2828         old_count = qla4_8xxx_rd_direct(ha, QLA8XXX_PEG_ALIVE_COUNTER);
2829
2830         for (i = 0; i < 10; i++) {
2831                 timeout = msleep_interruptible(200);
2832                 if (timeout) {
2833                         qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE,
2834                                             QLA8XXX_DEV_FAILED);
2835                         return rval;
2836                 }
2837
2838                 count = qla4_8xxx_rd_direct(ha, QLA8XXX_PEG_ALIVE_COUNTER);
2839                 if (count != old_count)
2840                         peg_stuck = 0;
2841         }
2842
2843         if (need_reset) {
2844                 /* We are trying to perform a recovery here. */
2845                 if (peg_stuck)
2846                         ha->isp_ops->rom_lock_recovery(ha);
2847                 goto dev_initialize;
2848         } else  {
2849                 /* Start of day for this ha context. */
2850                 if (peg_stuck) {
2851                         /* Either we are the first or recovery in progress. */
2852                         ha->isp_ops->rom_lock_recovery(ha);
2853                         goto dev_initialize;
2854                 } else {
2855                         /* Firmware already running. */
2856                         rval = QLA_SUCCESS;
2857                         goto dev_ready;
2858                 }
2859         }
2860
2861 dev_initialize:
2862         /* set to DEV_INITIALIZING */
2863         ql4_printk(KERN_INFO, ha, "HW State: INITIALIZING\n");
2864         qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE,
2865                             QLA8XXX_DEV_INITIALIZING);
2866
2867         /*
2868          * For ISP8324 and ISP8042, if IDC_CTRL GRACEFUL_RESET_BIT1 is set,
2869          * reset it after device goes to INIT state.
2870          */
2871         if (is_qla8032(ha) || is_qla8042(ha)) {
2872                 idc_ctrl = qla4_83xx_rd_reg(ha, QLA83XX_IDC_DRV_CTRL);
2873                 if (idc_ctrl & GRACEFUL_RESET_BIT1) {
2874                         qla4_83xx_wr_reg(ha, QLA83XX_IDC_DRV_CTRL,
2875                                          (idc_ctrl & ~GRACEFUL_RESET_BIT1));
2876                         set_bit(AF_83XX_NO_FW_DUMP, &ha->flags);
2877                 }
2878         }
2879
2880         ha->isp_ops->idc_unlock(ha);
2881
2882         if (is_qla8022(ha))
2883                 qla4_8xxx_get_minidump(ha);
2884
2885         rval = ha->isp_ops->restart_firmware(ha);
2886         ha->isp_ops->idc_lock(ha);
2887
2888         if (rval != QLA_SUCCESS) {
2889                 ql4_printk(KERN_INFO, ha, "HW State: FAILED\n");
2890                 qla4_8xxx_clear_drv_active(ha);
2891                 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE,
2892                                     QLA8XXX_DEV_FAILED);
2893                 return rval;
2894         }
2895
2896 dev_ready:
2897         ql4_printk(KERN_INFO, ha, "HW State: READY\n");
2898         qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE, QLA8XXX_DEV_READY);
2899
2900         return rval;
2901 }
2902
2903 /**
2904  * qla4_82xx_need_reset_handler - Code to start reset sequence
2905  * @ha: pointer to adapter structure
2906  *
2907  * Note: IDC lock must be held upon entry
2908  **/
2909 static void
2910 qla4_82xx_need_reset_handler(struct scsi_qla_host *ha)
2911 {
2912         uint32_t dev_state, drv_state, drv_active;
2913         uint32_t active_mask = 0xFFFFFFFF;
2914         unsigned long reset_timeout;
2915
2916         ql4_printk(KERN_INFO, ha,
2917                 "Performing ISP error recovery\n");
2918
2919         if (test_and_clear_bit(AF_ONLINE, &ha->flags)) {
2920                 qla4_82xx_idc_unlock(ha);
2921                 ha->isp_ops->disable_intrs(ha);
2922                 qla4_82xx_idc_lock(ha);
2923         }
2924
2925         if (!test_bit(AF_8XXX_RST_OWNER, &ha->flags)) {
2926                 DEBUG2(ql4_printk(KERN_INFO, ha,
2927                                   "%s(%ld): reset acknowledged\n",
2928                                   __func__, ha->host_no));
2929                 qla4_8xxx_set_rst_ready(ha);
2930         } else {
2931                 active_mask = (~(1 << (ha->func_num * 4)));
2932         }
2933
2934         /* wait for 10 seconds for reset ack from all functions */
2935         reset_timeout = jiffies + (ha->nx_reset_timeout * HZ);
2936
2937         drv_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2938         drv_active = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2939
2940         ql4_printk(KERN_INFO, ha,
2941                 "%s(%ld): drv_state = 0x%x, drv_active = 0x%x\n",
2942                 __func__, ha->host_no, drv_state, drv_active);
2943
2944         while (drv_state != (drv_active & active_mask)) {
2945                 if (time_after_eq(jiffies, reset_timeout)) {
2946                         ql4_printk(KERN_INFO, ha,
2947                                    "%s: RESET TIMEOUT! drv_state: 0x%08x, drv_active: 0x%08x\n",
2948                                    DRIVER_NAME, drv_state, drv_active);
2949                         break;
2950                 }
2951
2952                 /*
2953                  * When reset_owner times out, check which functions
2954                  * acked/did not ack
2955                  */
2956                 if (test_bit(AF_8XXX_RST_OWNER, &ha->flags)) {
2957                         ql4_printk(KERN_INFO, ha,
2958                                    "%s(%ld): drv_state = 0x%x, drv_active = 0x%x\n",
2959                                    __func__, ha->host_no, drv_state,
2960                                    drv_active);
2961                 }
2962                 qla4_82xx_idc_unlock(ha);
2963                 msleep(1000);
2964                 qla4_82xx_idc_lock(ha);
2965
2966                 drv_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2967                 drv_active = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2968         }
2969
2970         /* Clear RESET OWNER as we are not going to use it any further */
2971         clear_bit(AF_8XXX_RST_OWNER, &ha->flags);
2972
2973         dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
2974         ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n", dev_state,
2975                    dev_state < MAX_STATES ? qdev_state[dev_state] : "Unknown");
2976
2977         /* Force to DEV_COLD unless someone else is starting a reset */
2978         if (dev_state != QLA8XXX_DEV_INITIALIZING) {
2979                 ql4_printk(KERN_INFO, ha, "HW State: COLD/RE-INIT\n");
2980                 qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_COLD);
2981                 qla4_8xxx_set_rst_ready(ha);
2982         }
2983 }
2984
2985 /**
2986  * qla4_8xxx_need_qsnt_handler - Code to start qsnt
2987  * @ha: pointer to adapter structure
2988  **/
2989 void
2990 qla4_8xxx_need_qsnt_handler(struct scsi_qla_host *ha)
2991 {
2992         ha->isp_ops->idc_lock(ha);
2993         qla4_8xxx_set_qsnt_ready(ha);
2994         ha->isp_ops->idc_unlock(ha);
2995 }
2996
2997 static void qla4_82xx_set_idc_ver(struct scsi_qla_host *ha)
2998 {
2999         int idc_ver;
3000         uint32_t drv_active;
3001
3002         drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
3003         if (drv_active == (1 << (ha->func_num * 4))) {
3004                 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION,
3005                                     QLA82XX_IDC_VERSION);
3006                 ql4_printk(KERN_INFO, ha,
3007                            "%s: IDC version updated to %d\n", __func__,
3008                            QLA82XX_IDC_VERSION);
3009         } else {
3010                 idc_ver = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION);
3011                 if (QLA82XX_IDC_VERSION != idc_ver) {
3012                         ql4_printk(KERN_INFO, ha,
3013                                    "%s: qla4xxx driver IDC version %d is not compatible with IDC version %d of other drivers!\n",
3014                                    __func__, QLA82XX_IDC_VERSION, idc_ver);
3015                 }
3016         }
3017 }
3018
3019 static int qla4_83xx_set_idc_ver(struct scsi_qla_host *ha)
3020 {
3021         int idc_ver;
3022         uint32_t drv_active;
3023         int rval = QLA_SUCCESS;
3024
3025         drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
3026         if (drv_active == (1 << ha->func_num)) {
3027                 idc_ver = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION);
3028                 idc_ver &= (~0xFF);
3029                 idc_ver |= QLA83XX_IDC_VER_MAJ_VALUE;
3030                 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION, idc_ver);
3031                 ql4_printk(KERN_INFO, ha,
3032                            "%s: IDC version updated to %d\n", __func__,
3033                            idc_ver);
3034         } else {
3035                 idc_ver = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION);
3036                 idc_ver &= 0xFF;
3037                 if (QLA83XX_IDC_VER_MAJ_VALUE != idc_ver) {
3038                         ql4_printk(KERN_INFO, ha,
3039                                    "%s: qla4xxx driver IDC version %d is not compatible with IDC version %d of other drivers!\n",
3040                                    __func__, QLA83XX_IDC_VER_MAJ_VALUE,
3041                                    idc_ver);
3042                         rval = QLA_ERROR;
3043                         goto exit_set_idc_ver;
3044                 }
3045         }
3046
3047         /* Update IDC_MINOR_VERSION */
3048         idc_ver = qla4_83xx_rd_reg(ha, QLA83XX_CRB_IDC_VER_MINOR);
3049         idc_ver &= ~(0x03 << (ha->func_num * 2));
3050         idc_ver |= (QLA83XX_IDC_VER_MIN_VALUE << (ha->func_num * 2));
3051         qla4_83xx_wr_reg(ha, QLA83XX_CRB_IDC_VER_MINOR, idc_ver);
3052
3053 exit_set_idc_ver:
3054         return rval;
3055 }
3056
3057 int qla4_8xxx_update_idc_reg(struct scsi_qla_host *ha)
3058 {
3059         uint32_t drv_active;
3060         int rval = QLA_SUCCESS;
3061
3062         if (test_bit(AF_INIT_DONE, &ha->flags))
3063                 goto exit_update_idc_reg;
3064
3065         ha->isp_ops->idc_lock(ha);
3066         qla4_8xxx_set_drv_active(ha);
3067
3068         /*
3069          * If we are the first driver to load and
3070          * ql4xdontresethba is not set, clear IDC_CTRL BIT0.
3071          */
3072         if (is_qla8032(ha) || is_qla8042(ha)) {
3073                 drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
3074                 if ((drv_active == (1 << ha->func_num)) && !ql4xdontresethba)
3075                         qla4_83xx_clear_idc_dontreset(ha);
3076         }
3077
3078         if (is_qla8022(ha)) {
3079                 qla4_82xx_set_idc_ver(ha);
3080         } else if (is_qla8032(ha) || is_qla8042(ha)) {
3081                 rval = qla4_83xx_set_idc_ver(ha);
3082                 if (rval == QLA_ERROR)
3083                         qla4_8xxx_clear_drv_active(ha);
3084         }
3085
3086         ha->isp_ops->idc_unlock(ha);
3087
3088 exit_update_idc_reg:
3089         return rval;
3090 }
3091
3092 /**
3093  * qla4_8xxx_device_state_handler - Adapter state machine
3094  * @ha: pointer to host adapter structure.
3095  *
3096  * Note: IDC lock must be UNLOCKED upon entry
3097  **/
3098 int qla4_8xxx_device_state_handler(struct scsi_qla_host *ha)
3099 {
3100         uint32_t dev_state;
3101         int rval = QLA_SUCCESS;
3102         unsigned long dev_init_timeout;
3103
3104         rval = qla4_8xxx_update_idc_reg(ha);
3105         if (rval == QLA_ERROR)
3106                 goto exit_state_handler;
3107
3108         dev_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DEV_STATE);
3109         DEBUG2(ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n",
3110                           dev_state, dev_state < MAX_STATES ?
3111                           qdev_state[dev_state] : "Unknown"));
3112
3113         /* wait for 30 seconds for device to go ready */
3114         dev_init_timeout = jiffies + (ha->nx_dev_init_timeout * HZ);
3115
3116         ha->isp_ops->idc_lock(ha);
3117         while (1) {
3118
3119                 if (time_after_eq(jiffies, dev_init_timeout)) {
3120                         ql4_printk(KERN_WARNING, ha,
3121                                    "%s: Device Init Failed 0x%x = %s\n",
3122                                    DRIVER_NAME,
3123                                    dev_state, dev_state < MAX_STATES ?
3124                                    qdev_state[dev_state] : "Unknown");
3125                         qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE,
3126                                             QLA8XXX_DEV_FAILED);
3127                 }
3128
3129                 dev_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DEV_STATE);
3130                 ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n",
3131                            dev_state, dev_state < MAX_STATES ?
3132                            qdev_state[dev_state] : "Unknown");
3133
3134                 /* NOTE: Make sure idc unlocked upon exit of switch statement */
3135                 switch (dev_state) {
3136                 case QLA8XXX_DEV_READY:
3137                         goto exit;
3138                 case QLA8XXX_DEV_COLD:
3139                         rval = qla4_8xxx_device_bootstrap(ha);
3140                         goto exit;
3141                 case QLA8XXX_DEV_INITIALIZING:
3142                         ha->isp_ops->idc_unlock(ha);
3143                         msleep(1000);
3144                         ha->isp_ops->idc_lock(ha);
3145                         break;
3146                 case QLA8XXX_DEV_NEED_RESET:
3147                         /*
3148                          * For ISP8324 and ISP8042, if NEED_RESET is set by any
3149                          * driver, it should be honored, irrespective of
3150                          * IDC_CTRL DONTRESET_BIT0
3151                          */
3152                         if (is_qla8032(ha) || is_qla8042(ha)) {
3153                                 qla4_83xx_need_reset_handler(ha);
3154                         } else if (is_qla8022(ha)) {
3155                                 if (!ql4xdontresethba) {
3156                                         qla4_82xx_need_reset_handler(ha);
3157                                         /* Update timeout value after need
3158                                          * reset handler */
3159                                         dev_init_timeout = jiffies +
3160                                                 (ha->nx_dev_init_timeout * HZ);
3161                                 } else {
3162                                         ha->isp_ops->idc_unlock(ha);
3163                                         msleep(1000);
3164                                         ha->isp_ops->idc_lock(ha);
3165                                 }
3166                         }
3167                         break;
3168                 case QLA8XXX_DEV_NEED_QUIESCENT:
3169                         /* idc locked/unlocked in handler */
3170                         qla4_8xxx_need_qsnt_handler(ha);
3171                         break;
3172                 case QLA8XXX_DEV_QUIESCENT:
3173                         ha->isp_ops->idc_unlock(ha);
3174                         msleep(1000);
3175                         ha->isp_ops->idc_lock(ha);
3176                         break;
3177                 case QLA8XXX_DEV_FAILED:
3178                         ha->isp_ops->idc_unlock(ha);
3179                         qla4xxx_dead_adapter_cleanup(ha);
3180                         rval = QLA_ERROR;
3181                         ha->isp_ops->idc_lock(ha);
3182                         goto exit;
3183                 default:
3184                         ha->isp_ops->idc_unlock(ha);
3185                         qla4xxx_dead_adapter_cleanup(ha);
3186                         rval = QLA_ERROR;
3187                         ha->isp_ops->idc_lock(ha);
3188                         goto exit;
3189                 }
3190         }
3191 exit:
3192         ha->isp_ops->idc_unlock(ha);
3193 exit_state_handler:
3194         return rval;
3195 }
3196
3197 int qla4_8xxx_load_risc(struct scsi_qla_host *ha)
3198 {
3199         int retval;
3200
3201         /* clear the interrupt */
3202         if (is_qla8032(ha) || is_qla8042(ha)) {
3203                 writel(0, &ha->qla4_83xx_reg->risc_intr);
3204                 readl(&ha->qla4_83xx_reg->risc_intr);
3205         } else if (is_qla8022(ha)) {
3206                 writel(0, &ha->qla4_82xx_reg->host_int);
3207                 readl(&ha->qla4_82xx_reg->host_int);
3208         }
3209
3210         retval = qla4_8xxx_device_state_handler(ha);
3211
3212         if (retval == QLA_SUCCESS && !test_bit(AF_IRQ_ATTACHED, &ha->flags))
3213                 retval = qla4xxx_request_irqs(ha);
3214
3215         return retval;
3216 }
3217
3218 /*****************************************************************************/
3219 /* Flash Manipulation Routines                                               */
3220 /*****************************************************************************/
3221
3222 #define OPTROM_BURST_SIZE       0x1000
3223 #define OPTROM_BURST_DWORDS     (OPTROM_BURST_SIZE / 4)
3224
3225 #define FARX_DATA_FLAG  BIT_31
3226 #define FARX_ACCESS_FLASH_CONF  0x7FFD0000
3227 #define FARX_ACCESS_FLASH_DATA  0x7FF00000
3228
3229 static inline uint32_t
3230 flash_conf_addr(struct ql82xx_hw_data *hw, uint32_t faddr)
3231 {
3232         return hw->flash_conf_off | faddr;
3233 }
3234
3235 static inline uint32_t
3236 flash_data_addr(struct ql82xx_hw_data *hw, uint32_t faddr)
3237 {
3238         return hw->flash_data_off | faddr;
3239 }
3240
3241 static uint32_t *
3242 qla4_82xx_read_flash_data(struct scsi_qla_host *ha, uint32_t *dwptr,
3243     uint32_t faddr, uint32_t length)
3244 {
3245         uint32_t i;
3246         uint32_t val;
3247         int loops = 0;
3248         while ((qla4_82xx_rom_lock(ha) != 0) && (loops < 50000)) {
3249                 udelay(100);
3250                 cond_resched();
3251                 loops++;
3252         }
3253         if (loops >= 50000) {
3254                 ql4_printk(KERN_WARNING, ha, "ROM lock failed\n");
3255                 return dwptr;
3256         }
3257
3258         /* Dword reads to flash. */
3259         for (i = 0; i < length/4; i++, faddr += 4) {
3260                 if (qla4_82xx_do_rom_fast_read(ha, faddr, &val)) {
3261                         ql4_printk(KERN_WARNING, ha,
3262                             "Do ROM fast read failed\n");
3263                         goto done_read;
3264                 }
3265                 dwptr[i] = __constant_cpu_to_le32(val);
3266         }
3267
3268 done_read:
3269         qla4_82xx_rom_unlock(ha);
3270         return dwptr;
3271 }
3272
3273 /**
3274  * Address and length are byte address
3275  **/
3276 static uint8_t *
3277 qla4_82xx_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
3278                 uint32_t offset, uint32_t length)
3279 {
3280         qla4_82xx_read_flash_data(ha, (uint32_t *)buf, offset, length);
3281         return buf;
3282 }
3283
3284 static int
3285 qla4_8xxx_find_flt_start(struct scsi_qla_host *ha, uint32_t *start)
3286 {
3287         const char *loc, *locations[] = { "DEF", "PCI" };
3288
3289         /*
3290          * FLT-location structure resides after the last PCI region.
3291          */
3292
3293         /* Begin with sane defaults. */
3294         loc = locations[0];
3295         *start = FA_FLASH_LAYOUT_ADDR_82;
3296
3297         DEBUG2(ql4_printk(KERN_INFO, ha, "FLTL[%s] = 0x%x.\n", loc, *start));
3298         return QLA_SUCCESS;
3299 }
3300
3301 static void
3302 qla4_8xxx_get_flt_info(struct scsi_qla_host *ha, uint32_t flt_addr)
3303 {
3304         const char *loc, *locations[] = { "DEF", "FLT" };
3305         uint16_t *wptr;
3306         uint16_t cnt, chksum;
3307         uint32_t start, status;
3308         struct qla_flt_header *flt;
3309         struct qla_flt_region *region;
3310         struct ql82xx_hw_data *hw = &ha->hw;
3311
3312         hw->flt_region_flt = flt_addr;
3313         wptr = (uint16_t *)ha->request_ring;
3314         flt = (struct qla_flt_header *)ha->request_ring;
3315         region = (struct qla_flt_region *)&flt[1];
3316
3317         if (is_qla8022(ha)) {
3318                 qla4_82xx_read_optrom_data(ha, (uint8_t *)ha->request_ring,
3319                                            flt_addr << 2, OPTROM_BURST_SIZE);
3320         } else if (is_qla8032(ha) || is_qla8042(ha)) {
3321                 status = qla4_83xx_flash_read_u32(ha, flt_addr << 2,
3322                                                   (uint8_t *)ha->request_ring,
3323                                                   0x400);
3324                 if (status != QLA_SUCCESS)
3325                         goto no_flash_data;
3326         }
3327
3328         if (*wptr == __constant_cpu_to_le16(0xffff))
3329                 goto no_flash_data;
3330         if (flt->version != __constant_cpu_to_le16(1)) {
3331                 DEBUG2(ql4_printk(KERN_INFO, ha, "Unsupported FLT detected: "
3332                         "version=0x%x length=0x%x checksum=0x%x.\n",
3333                         le16_to_cpu(flt->version), le16_to_cpu(flt->length),
3334                         le16_to_cpu(flt->checksum)));
3335                 goto no_flash_data;
3336         }
3337
3338         cnt = (sizeof(struct qla_flt_header) + le16_to_cpu(flt->length)) >> 1;
3339         for (chksum = 0; cnt; cnt--)
3340                 chksum += le16_to_cpu(*wptr++);
3341         if (chksum) {
3342                 DEBUG2(ql4_printk(KERN_INFO, ha, "Inconsistent FLT detected: "
3343                         "version=0x%x length=0x%x checksum=0x%x.\n",
3344                         le16_to_cpu(flt->version), le16_to_cpu(flt->length),
3345                         chksum));
3346                 goto no_flash_data;
3347         }
3348
3349         loc = locations[1];
3350         cnt = le16_to_cpu(flt->length) / sizeof(struct qla_flt_region);
3351         for ( ; cnt; cnt--, region++) {
3352                 /* Store addresses as DWORD offsets. */
3353                 start = le32_to_cpu(region->start) >> 2;
3354
3355                 DEBUG3(ql4_printk(KERN_DEBUG, ha, "FLT[%02x]: start=0x%x "
3356                     "end=0x%x size=0x%x.\n", le32_to_cpu(region->code), start,
3357                     le32_to_cpu(region->end) >> 2, le32_to_cpu(region->size)));
3358
3359                 switch (le32_to_cpu(region->code) & 0xff) {
3360                 case FLT_REG_FDT:
3361                         hw->flt_region_fdt = start;
3362                         break;
3363                 case FLT_REG_BOOT_CODE_82:
3364                         hw->flt_region_boot = start;
3365                         break;
3366                 case FLT_REG_FW_82:
3367                 case FLT_REG_FW_82_1:
3368                         hw->flt_region_fw = start;
3369                         break;
3370                 case FLT_REG_BOOTLOAD_82:
3371                         hw->flt_region_bootload = start;
3372                         break;
3373                 case FLT_REG_ISCSI_PARAM:
3374                         hw->flt_iscsi_param =  start;
3375                         break;
3376                 case FLT_REG_ISCSI_CHAP:
3377                         hw->flt_region_chap =  start;
3378                         hw->flt_chap_size =  le32_to_cpu(region->size);
3379                         break;
3380                 case FLT_REG_ISCSI_DDB:
3381                         hw->flt_region_ddb =  start;
3382                         hw->flt_ddb_size =  le32_to_cpu(region->size);
3383                         break;
3384                 }
3385         }
3386         goto done;
3387
3388 no_flash_data:
3389         /* Use hardcoded defaults. */
3390         loc = locations[0];
3391
3392         hw->flt_region_fdt      = FA_FLASH_DESCR_ADDR_82;
3393         hw->flt_region_boot     = FA_BOOT_CODE_ADDR_82;
3394         hw->flt_region_bootload = FA_BOOT_LOAD_ADDR_82;
3395         hw->flt_region_fw       = FA_RISC_CODE_ADDR_82;
3396         hw->flt_region_chap     = FA_FLASH_ISCSI_CHAP >> 2;
3397         hw->flt_chap_size       = FA_FLASH_CHAP_SIZE;
3398         hw->flt_region_ddb      = FA_FLASH_ISCSI_DDB >> 2;
3399         hw->flt_ddb_size        = FA_FLASH_DDB_SIZE;
3400
3401 done:
3402         DEBUG2(ql4_printk(KERN_INFO, ha,
3403                           "FLT[%s]: flt=0x%x fdt=0x%x boot=0x%x bootload=0x%x fw=0x%x chap=0x%x chap_size=0x%x ddb=0x%x  ddb_size=0x%x\n",
3404                           loc, hw->flt_region_flt, hw->flt_region_fdt,
3405                           hw->flt_region_boot, hw->flt_region_bootload,
3406                           hw->flt_region_fw, hw->flt_region_chap,
3407                           hw->flt_chap_size, hw->flt_region_ddb,
3408                           hw->flt_ddb_size));
3409 }
3410
3411 static void
3412 qla4_82xx_get_fdt_info(struct scsi_qla_host *ha)
3413 {
3414 #define FLASH_BLK_SIZE_4K       0x1000
3415 #define FLASH_BLK_SIZE_32K      0x8000
3416 #define FLASH_BLK_SIZE_64K      0x10000
3417         const char *loc, *locations[] = { "MID", "FDT" };
3418         uint16_t cnt, chksum;
3419         uint16_t *wptr;
3420         struct qla_fdt_layout *fdt;
3421         uint16_t mid = 0;
3422         uint16_t fid = 0;
3423         struct ql82xx_hw_data *hw = &ha->hw;
3424
3425         hw->flash_conf_off = FARX_ACCESS_FLASH_CONF;
3426         hw->flash_data_off = FARX_ACCESS_FLASH_DATA;
3427
3428         wptr = (uint16_t *)ha->request_ring;
3429         fdt = (struct qla_fdt_layout *)ha->request_ring;
3430         qla4_82xx_read_optrom_data(ha, (uint8_t *)ha->request_ring,
3431             hw->flt_region_fdt << 2, OPTROM_BURST_SIZE);
3432
3433         if (*wptr == __constant_cpu_to_le16(0xffff))
3434                 goto no_flash_data;
3435
3436         if (fdt->sig[0] != 'Q' || fdt->sig[1] != 'L' || fdt->sig[2] != 'I' ||
3437             fdt->sig[3] != 'D')
3438                 goto no_flash_data;
3439
3440         for (cnt = 0, chksum = 0; cnt < sizeof(struct qla_fdt_layout) >> 1;
3441             cnt++)
3442                 chksum += le16_to_cpu(*wptr++);
3443
3444         if (chksum) {
3445                 DEBUG2(ql4_printk(KERN_INFO, ha, "Inconsistent FDT detected: "
3446                     "checksum=0x%x id=%c version=0x%x.\n", chksum, fdt->sig[0],
3447                     le16_to_cpu(fdt->version)));
3448                 goto no_flash_data;
3449         }
3450
3451         loc = locations[1];
3452         mid = le16_to_cpu(fdt->man_id);
3453         fid = le16_to_cpu(fdt->id);
3454         hw->fdt_wrt_disable = fdt->wrt_disable_bits;
3455         hw->fdt_erase_cmd = flash_conf_addr(hw, 0x0300 | fdt->erase_cmd);
3456         hw->fdt_block_size = le32_to_cpu(fdt->block_size);
3457
3458         if (fdt->unprotect_sec_cmd) {
3459                 hw->fdt_unprotect_sec_cmd = flash_conf_addr(hw, 0x0300 |
3460                     fdt->unprotect_sec_cmd);
3461                 hw->fdt_protect_sec_cmd = fdt->protect_sec_cmd ?
3462                     flash_conf_addr(hw, 0x0300 | fdt->protect_sec_cmd) :
3463                     flash_conf_addr(hw, 0x0336);
3464         }
3465         goto done;
3466
3467 no_flash_data:
3468         loc = locations[0];
3469         hw->fdt_block_size = FLASH_BLK_SIZE_64K;
3470 done:
3471         DEBUG2(ql4_printk(KERN_INFO, ha, "FDT[%s]: (0x%x/0x%x) erase=0x%x "
3472                 "pro=%x upro=%x wrtd=0x%x blk=0x%x.\n", loc, mid, fid,
3473                 hw->fdt_erase_cmd, hw->fdt_protect_sec_cmd,
3474                 hw->fdt_unprotect_sec_cmd, hw->fdt_wrt_disable,
3475                 hw->fdt_block_size));
3476 }
3477
3478 static void
3479 qla4_82xx_get_idc_param(struct scsi_qla_host *ha)
3480 {
3481 #define QLA82XX_IDC_PARAM_ADDR      0x003e885c
3482         uint32_t *wptr;
3483
3484         if (!is_qla8022(ha))
3485                 return;
3486         wptr = (uint32_t *)ha->request_ring;
3487         qla4_82xx_read_optrom_data(ha, (uint8_t *)ha->request_ring,
3488                         QLA82XX_IDC_PARAM_ADDR , 8);
3489
3490         if (*wptr == __constant_cpu_to_le32(0xffffffff)) {
3491                 ha->nx_dev_init_timeout = ROM_DEV_INIT_TIMEOUT;
3492                 ha->nx_reset_timeout = ROM_DRV_RESET_ACK_TIMEOUT;
3493         } else {
3494                 ha->nx_dev_init_timeout = le32_to_cpu(*wptr++);
3495                 ha->nx_reset_timeout = le32_to_cpu(*wptr);
3496         }
3497
3498         DEBUG2(ql4_printk(KERN_DEBUG, ha,
3499                 "ha->nx_dev_init_timeout = %d\n", ha->nx_dev_init_timeout));
3500         DEBUG2(ql4_printk(KERN_DEBUG, ha,
3501                 "ha->nx_reset_timeout = %d\n", ha->nx_reset_timeout));
3502         return;
3503 }
3504
3505 void qla4_82xx_queue_mbox_cmd(struct scsi_qla_host *ha, uint32_t *mbx_cmd,
3506                               int in_count)
3507 {
3508         int i;
3509
3510         /* Load all mailbox registers, except mailbox 0. */
3511         for (i = 1; i < in_count; i++)
3512                 writel(mbx_cmd[i], &ha->qla4_82xx_reg->mailbox_in[i]);
3513
3514         /* Wakeup firmware  */
3515         writel(mbx_cmd[0], &ha->qla4_82xx_reg->mailbox_in[0]);
3516         readl(&ha->qla4_82xx_reg->mailbox_in[0]);
3517         writel(HINT_MBX_INT_PENDING, &ha->qla4_82xx_reg->hint);
3518         readl(&ha->qla4_82xx_reg->hint);
3519 }
3520
3521 void qla4_82xx_process_mbox_intr(struct scsi_qla_host *ha, int out_count)
3522 {
3523         int intr_status;
3524
3525         intr_status = readl(&ha->qla4_82xx_reg->host_int);
3526         if (intr_status & ISRX_82XX_RISC_INT) {
3527                 ha->mbox_status_count = out_count;
3528                 intr_status = readl(&ha->qla4_82xx_reg->host_status);
3529                 ha->isp_ops->interrupt_service_routine(ha, intr_status);
3530
3531                 if (test_bit(AF_INTERRUPTS_ON, &ha->flags) &&
3532                     test_bit(AF_INTx_ENABLED, &ha->flags))
3533                         qla4_82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg,
3534                                         0xfbff);
3535         }
3536 }
3537
3538 int
3539 qla4_8xxx_get_flash_info(struct scsi_qla_host *ha)
3540 {
3541         int ret;
3542         uint32_t flt_addr;
3543
3544         ret = qla4_8xxx_find_flt_start(ha, &flt_addr);
3545         if (ret != QLA_SUCCESS)
3546                 return ret;
3547
3548         qla4_8xxx_get_flt_info(ha, flt_addr);
3549         if (is_qla8022(ha)) {
3550                 qla4_82xx_get_fdt_info(ha);
3551                 qla4_82xx_get_idc_param(ha);
3552         } else if (is_qla8032(ha) || is_qla8042(ha)) {
3553                 qla4_83xx_get_idc_param(ha);
3554         }
3555
3556         return QLA_SUCCESS;
3557 }
3558
3559 /**
3560  * qla4_8xxx_stop_firmware - stops firmware on specified adapter instance
3561  * @ha: pointer to host adapter structure.
3562  *
3563  * Remarks:
3564  * For iSCSI, throws away all I/O and AENs into bit bucket, so they will
3565  * not be available after successful return.  Driver must cleanup potential
3566  * outstanding I/O's after calling this funcion.
3567  **/
3568 int
3569 qla4_8xxx_stop_firmware(struct scsi_qla_host *ha)
3570 {
3571         int status;
3572         uint32_t mbox_cmd[MBOX_REG_COUNT];
3573         uint32_t mbox_sts[MBOX_REG_COUNT];
3574
3575         memset(&mbox_cmd, 0, sizeof(mbox_cmd));
3576         memset(&mbox_sts, 0, sizeof(mbox_sts));
3577
3578         mbox_cmd[0] = MBOX_CMD_STOP_FW;
3579         status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1,
3580             &mbox_cmd[0], &mbox_sts[0]);
3581
3582         DEBUG2(printk("scsi%ld: %s: status = %d\n", ha->host_no,
3583             __func__, status));
3584         return status;
3585 }
3586
3587 /**
3588  * qla4_82xx_isp_reset - Resets ISP and aborts all outstanding commands.
3589  * @ha: pointer to host adapter structure.
3590  **/
3591 int
3592 qla4_82xx_isp_reset(struct scsi_qla_host *ha)
3593 {
3594         int rval;
3595         uint32_t dev_state;
3596
3597         qla4_82xx_idc_lock(ha);
3598         dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3599
3600         if (dev_state == QLA8XXX_DEV_READY) {
3601                 ql4_printk(KERN_INFO, ha, "HW State: NEED RESET\n");
3602                 qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
3603                     QLA8XXX_DEV_NEED_RESET);
3604                 set_bit(AF_8XXX_RST_OWNER, &ha->flags);
3605         } else
3606                 ql4_printk(KERN_INFO, ha, "HW State: DEVICE INITIALIZING\n");
3607
3608         qla4_82xx_idc_unlock(ha);
3609
3610         rval = qla4_8xxx_device_state_handler(ha);
3611
3612         qla4_82xx_idc_lock(ha);
3613         qla4_8xxx_clear_rst_ready(ha);
3614         qla4_82xx_idc_unlock(ha);
3615
3616         if (rval == QLA_SUCCESS) {
3617                 ql4_printk(KERN_INFO, ha, "Clearing AF_RECOVERY in qla4_82xx_isp_reset\n");
3618                 clear_bit(AF_FW_RECOVERY, &ha->flags);
3619         }
3620
3621         return rval;
3622 }
3623
3624 /**
3625  * qla4_8xxx_get_sys_info - get adapter MAC address(es) and serial number
3626  * @ha: pointer to host adapter structure.
3627  *
3628  **/
3629 int qla4_8xxx_get_sys_info(struct scsi_qla_host *ha)
3630 {
3631         uint32_t mbox_cmd[MBOX_REG_COUNT];
3632         uint32_t mbox_sts[MBOX_REG_COUNT];
3633         struct mbx_sys_info *sys_info;
3634         dma_addr_t sys_info_dma;
3635         int status = QLA_ERROR;
3636
3637         sys_info = dma_alloc_coherent(&ha->pdev->dev, sizeof(*sys_info),
3638                                       &sys_info_dma, GFP_KERNEL);
3639         if (sys_info == NULL) {
3640                 DEBUG2(printk("scsi%ld: %s: Unable to allocate dma buffer.\n",
3641                     ha->host_no, __func__));
3642                 return status;
3643         }
3644
3645         memset(sys_info, 0, sizeof(*sys_info));
3646         memset(&mbox_cmd, 0, sizeof(mbox_cmd));
3647         memset(&mbox_sts, 0, sizeof(mbox_sts));
3648
3649         mbox_cmd[0] = MBOX_CMD_GET_SYS_INFO;
3650         mbox_cmd[1] = LSDW(sys_info_dma);
3651         mbox_cmd[2] = MSDW(sys_info_dma);
3652         mbox_cmd[4] = sizeof(*sys_info);
3653
3654         if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 6, &mbox_cmd[0],
3655             &mbox_sts[0]) != QLA_SUCCESS) {
3656                 DEBUG2(printk("scsi%ld: %s: GET_SYS_INFO failed\n",
3657                     ha->host_no, __func__));
3658                 goto exit_validate_mac82;
3659         }
3660
3661         /* Make sure we receive the minimum required data to cache internally */
3662         if (((is_qla8032(ha) || is_qla8042(ha)) ? mbox_sts[3] : mbox_sts[4]) <
3663             offsetof(struct mbx_sys_info, reserved)) {
3664                 DEBUG2(printk("scsi%ld: %s: GET_SYS_INFO data receive"
3665                     " error (%x)\n", ha->host_no, __func__, mbox_sts[4]));
3666                 goto exit_validate_mac82;
3667         }
3668
3669         /* Save M.A.C. address & serial_number */
3670         ha->port_num = sys_info->port_num;
3671         memcpy(ha->my_mac, &sys_info->mac_addr[0],
3672             min(sizeof(ha->my_mac), sizeof(sys_info->mac_addr)));
3673         memcpy(ha->serial_number, &sys_info->serial_number,
3674             min(sizeof(ha->serial_number), sizeof(sys_info->serial_number)));
3675         memcpy(ha->model_name, &sys_info->board_id_str,
3676                min(sizeof(ha->model_name), sizeof(sys_info->board_id_str)));
3677         ha->phy_port_cnt = sys_info->phys_port_cnt;
3678         ha->phy_port_num = sys_info->port_num;
3679         ha->iscsi_pci_func_cnt = sys_info->iscsi_pci_func_cnt;
3680
3681         DEBUG2(printk("scsi%ld: %s: "
3682             "mac %02x:%02x:%02x:%02x:%02x:%02x "
3683             "serial %s\n", ha->host_no, __func__,
3684             ha->my_mac[0], ha->my_mac[1], ha->my_mac[2],
3685             ha->my_mac[3], ha->my_mac[4], ha->my_mac[5],
3686             ha->serial_number));
3687
3688         status = QLA_SUCCESS;
3689
3690 exit_validate_mac82:
3691         dma_free_coherent(&ha->pdev->dev, sizeof(*sys_info), sys_info,
3692                           sys_info_dma);
3693         return status;
3694 }
3695
3696 /* Interrupt handling helpers. */
3697
3698 int qla4_8xxx_intr_enable(struct scsi_qla_host *ha)
3699 {
3700         uint32_t mbox_cmd[MBOX_REG_COUNT];
3701         uint32_t mbox_sts[MBOX_REG_COUNT];
3702
3703         DEBUG2(ql4_printk(KERN_INFO, ha, "%s\n", __func__));
3704
3705         memset(&mbox_cmd, 0, sizeof(mbox_cmd));
3706         memset(&mbox_sts, 0, sizeof(mbox_sts));
3707         mbox_cmd[0] = MBOX_CMD_ENABLE_INTRS;
3708         mbox_cmd[1] = INTR_ENABLE;
3709         if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
3710                 &mbox_sts[0]) != QLA_SUCCESS) {
3711                 DEBUG2(ql4_printk(KERN_INFO, ha,
3712                     "%s: MBOX_CMD_ENABLE_INTRS failed (0x%04x)\n",
3713                     __func__, mbox_sts[0]));
3714                 return QLA_ERROR;
3715         }
3716         return QLA_SUCCESS;
3717 }
3718
3719 int qla4_8xxx_intr_disable(struct scsi_qla_host *ha)
3720 {
3721         uint32_t mbox_cmd[MBOX_REG_COUNT];
3722         uint32_t mbox_sts[MBOX_REG_COUNT];
3723
3724         DEBUG2(ql4_printk(KERN_INFO, ha, "%s\n", __func__));
3725
3726         memset(&mbox_cmd, 0, sizeof(mbox_cmd));
3727         memset(&mbox_sts, 0, sizeof(mbox_sts));
3728         mbox_cmd[0] = MBOX_CMD_ENABLE_INTRS;
3729         mbox_cmd[1] = INTR_DISABLE;
3730         if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
3731             &mbox_sts[0]) != QLA_SUCCESS) {
3732                 DEBUG2(ql4_printk(KERN_INFO, ha,
3733                         "%s: MBOX_CMD_ENABLE_INTRS failed (0x%04x)\n",
3734                         __func__, mbox_sts[0]));
3735                 return QLA_ERROR;
3736         }
3737
3738         return QLA_SUCCESS;
3739 }
3740
3741 void
3742 qla4_82xx_enable_intrs(struct scsi_qla_host *ha)
3743 {
3744         qla4_8xxx_intr_enable(ha);
3745
3746         spin_lock_irq(&ha->hardware_lock);
3747         /* BIT 10 - reset */
3748         qla4_82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff);
3749         spin_unlock_irq(&ha->hardware_lock);
3750         set_bit(AF_INTERRUPTS_ON, &ha->flags);
3751 }
3752
3753 void
3754 qla4_82xx_disable_intrs(struct scsi_qla_host *ha)
3755 {
3756         if (test_and_clear_bit(AF_INTERRUPTS_ON, &ha->flags))
3757                 qla4_8xxx_intr_disable(ha);
3758
3759         spin_lock_irq(&ha->hardware_lock);
3760         /* BIT 10 - set */
3761         qla4_82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400);
3762         spin_unlock_irq(&ha->hardware_lock);
3763 }
3764
3765 struct ql4_init_msix_entry {
3766         uint16_t entry;
3767         uint16_t index;
3768         const char *name;
3769         irq_handler_t handler;
3770 };
3771
3772 static struct ql4_init_msix_entry qla4_8xxx_msix_entries[QLA_MSIX_ENTRIES] = {
3773         { QLA_MSIX_DEFAULT, QLA_MIDX_DEFAULT,
3774             "qla4xxx (default)",
3775             (irq_handler_t)qla4_8xxx_default_intr_handler },
3776         { QLA_MSIX_RSP_Q, QLA_MIDX_RSP_Q,
3777             "qla4xxx (rsp_q)", (irq_handler_t)qla4_8xxx_msix_rsp_q },
3778 };
3779
3780 void
3781 qla4_8xxx_disable_msix(struct scsi_qla_host *ha)
3782 {
3783         int i;
3784         struct ql4_msix_entry *qentry;
3785
3786         for (i = 0; i < QLA_MSIX_ENTRIES; i++) {
3787                 qentry = &ha->msix_entries[qla4_8xxx_msix_entries[i].index];
3788                 if (qentry->have_irq) {
3789                         free_irq(qentry->msix_vector, ha);
3790                         DEBUG2(ql4_printk(KERN_INFO, ha, "%s: %s\n",
3791                                 __func__, qla4_8xxx_msix_entries[i].name));
3792                 }
3793         }
3794         pci_disable_msix(ha->pdev);
3795         clear_bit(AF_MSIX_ENABLED, &ha->flags);
3796 }
3797
3798 int
3799 qla4_8xxx_enable_msix(struct scsi_qla_host *ha)
3800 {
3801         int i, ret;
3802         struct msix_entry entries[QLA_MSIX_ENTRIES];
3803         struct ql4_msix_entry *qentry;
3804
3805         for (i = 0; i < QLA_MSIX_ENTRIES; i++)
3806                 entries[i].entry = qla4_8xxx_msix_entries[i].entry;
3807
3808         ret = pci_enable_msix(ha->pdev, entries, ARRAY_SIZE(entries));
3809         if (ret) {
3810                 ql4_printk(KERN_WARNING, ha,
3811                     "MSI-X: Failed to enable support -- %d/%d\n",
3812                     QLA_MSIX_ENTRIES, ret);
3813                 goto msix_out;
3814         }
3815         set_bit(AF_MSIX_ENABLED, &ha->flags);
3816
3817         for (i = 0; i < QLA_MSIX_ENTRIES; i++) {
3818                 qentry = &ha->msix_entries[qla4_8xxx_msix_entries[i].index];
3819                 qentry->msix_vector = entries[i].vector;
3820                 qentry->msix_entry = entries[i].entry;
3821                 qentry->have_irq = 0;
3822                 ret = request_irq(qentry->msix_vector,
3823                     qla4_8xxx_msix_entries[i].handler, 0,
3824                     qla4_8xxx_msix_entries[i].name, ha);
3825                 if (ret) {
3826                         ql4_printk(KERN_WARNING, ha,
3827                             "MSI-X: Unable to register handler -- %x/%d.\n",
3828                             qla4_8xxx_msix_entries[i].index, ret);
3829                         qla4_8xxx_disable_msix(ha);
3830                         goto msix_out;
3831                 }
3832                 qentry->have_irq = 1;
3833                 DEBUG2(ql4_printk(KERN_INFO, ha, "%s: %s\n",
3834                         __func__, qla4_8xxx_msix_entries[i].name));
3835         }
3836 msix_out:
3837         return ret;
3838 }