drivers/scsi/qla4xxx/ql4_nx.c

   1 /*
   2  * QLogic iSCSI HBA Driver
   3  * Copyright (c)  2003-2012 QLogic Corporation
   4  *
   5  * See LICENSE.qla4xxx for copyright and licensing details.
   6  */
   7 #include <linux/delay.h>
   8 #include <linux/io.h>
   9 #include <linux/pci.h>
  10 #include <linux/ratelimit.h>
  11 #include "ql4_def.h"
  12 #include "ql4_glbl.h"
  13 #include "ql4_inline.h"
  14
  15 #include <asm-generic/io-64-nonatomic-lo-hi.h>
  16
  17 #define MASK(n)         DMA_BIT_MASK(n)
  18 #define MN_WIN(addr)    (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff))
  19 #define OCM_WIN(addr)   (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff))
  20 #define MS_WIN(addr)    (addr & 0x0ffc0000)
  21 #define QLA82XX_PCI_MN_2M       (0)
  22 #define QLA82XX_PCI_MS_2M       (0x80000)
  23 #define QLA82XX_PCI_OCM0_2M     (0xc0000)
  24 #define VALID_OCM_ADDR(addr)    (((addr) & 0x3f800) != 0x3f800)
  25 #define GET_MEM_OFFS_2M(addr)   (addr & MASK(18))
  26
  27 /* CRB window related */
  28 #define CRB_BLK(off)    ((off >> 20) & 0x3f)
  29 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
  30 #define CRB_WINDOW_2M   (0x130060)
  31 #define CRB_HI(off)     ((qla4_82xx_crb_hub_agt[CRB_BLK(off)] << 20) | \
  32                         ((off) & 0xf0000))
  33 #define QLA82XX_PCI_CAMQM_2M_END        (0x04800800UL)
  34 #define QLA82XX_PCI_CAMQM_2M_BASE       (0x000ff800UL)
  35 #define CRB_INDIRECT_2M                 (0x1e0000UL)
  36
  37 static inline void __iomem *
  38 qla4_8xxx_pci_base_offsetfset(struct scsi_qla_host *ha, unsigned long off)
  39 {
  40         if ((off < ha->first_page_group_end) &&
  41             (off >= ha->first_page_group_start))
  42                 return (void __iomem *)(ha->nx_pcibase + off);
  43
  44         return NULL;
  45 }
  46
  47 #define MAX_CRB_XFORM 60
  48 static unsigned long crb_addr_xform[MAX_CRB_XFORM];
  49 static int qla4_8xxx_crb_table_initialized;
  50
  51 #define qla4_8xxx_crb_addr_transform(name) \
  52         (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \
  53          QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20)
  54 static void
  55 qla4_82xx_crb_addr_transform_setup(void)
  56 {
  57         qla4_8xxx_crb_addr_transform(XDMA);
  58         qla4_8xxx_crb_addr_transform(TIMR);
  59         qla4_8xxx_crb_addr_transform(SRE);
  60         qla4_8xxx_crb_addr_transform(SQN3);
  61         qla4_8xxx_crb_addr_transform(SQN2);
  62         qla4_8xxx_crb_addr_transform(SQN1);
  63         qla4_8xxx_crb_addr_transform(SQN0);
  64         qla4_8xxx_crb_addr_transform(SQS3);
  65         qla4_8xxx_crb_addr_transform(SQS2);
  66         qla4_8xxx_crb_addr_transform(SQS1);
  67         qla4_8xxx_crb_addr_transform(SQS0);
  68         qla4_8xxx_crb_addr_transform(RPMX7);
  69         qla4_8xxx_crb_addr_transform(RPMX6);
  70         qla4_8xxx_crb_addr_transform(RPMX5);
  71         qla4_8xxx_crb_addr_transform(RPMX4);
  72         qla4_8xxx_crb_addr_transform(RPMX3);
  73         qla4_8xxx_crb_addr_transform(RPMX2);
  74         qla4_8xxx_crb_addr_transform(RPMX1);
  75         qla4_8xxx_crb_addr_transform(RPMX0);
  76         qla4_8xxx_crb_addr_transform(ROMUSB);
  77         qla4_8xxx_crb_addr_transform(SN);
  78         qla4_8xxx_crb_addr_transform(QMN);
  79         qla4_8xxx_crb_addr_transform(QMS);
  80         qla4_8xxx_crb_addr_transform(PGNI);
  81         qla4_8xxx_crb_addr_transform(PGND);
  82         qla4_8xxx_crb_addr_transform(PGN3);
  83         qla4_8xxx_crb_addr_transform(PGN2);
  84         qla4_8xxx_crb_addr_transform(PGN1);
  85         qla4_8xxx_crb_addr_transform(PGN0);
  86         qla4_8xxx_crb_addr_transform(PGSI);
  87         qla4_8xxx_crb_addr_transform(PGSD);
  88         qla4_8xxx_crb_addr_transform(PGS3);
  89         qla4_8xxx_crb_addr_transform(PGS2);
  90         qla4_8xxx_crb_addr_transform(PGS1);
  91         qla4_8xxx_crb_addr_transform(PGS0);
  92         qla4_8xxx_crb_addr_transform(PS);
  93         qla4_8xxx_crb_addr_transform(PH);
  94         qla4_8xxx_crb_addr_transform(NIU);
  95         qla4_8xxx_crb_addr_transform(I2Q);
  96         qla4_8xxx_crb_addr_transform(EG);
  97         qla4_8xxx_crb_addr_transform(MN);
  98         qla4_8xxx_crb_addr_transform(MS);
  99         qla4_8xxx_crb_addr_transform(CAS2);
 100         qla4_8xxx_crb_addr_transform(CAS1);
 101         qla4_8xxx_crb_addr_transform(CAS0);
 102         qla4_8xxx_crb_addr_transform(CAM);
 103         qla4_8xxx_crb_addr_transform(C2C1);
 104         qla4_8xxx_crb_addr_transform(C2C0);
 105         qla4_8xxx_crb_addr_transform(SMB);
 106         qla4_8xxx_crb_addr_transform(OCM0);
 107         qla4_8xxx_crb_addr_transform(I2C0);
 108
 109         qla4_8xxx_crb_table_initialized = 1;
 110 }
 111
 112 static struct crb_128M_2M_block_map crb_128M_2M_map[64] = {
 113         {{{0, 0,         0,         0} } },             /* 0: PCI */
 114         {{{1, 0x0100000, 0x0102000, 0x120000},  /* 1: PCIE */
 115                 {1, 0x0110000, 0x0120000, 0x130000},
 116                 {1, 0x0120000, 0x0122000, 0x124000},
 117                 {1, 0x0130000, 0x0132000, 0x126000},
 118                 {1, 0x0140000, 0x0142000, 0x128000},
 119                 {1, 0x0150000, 0x0152000, 0x12a000},
 120                 {1, 0x0160000, 0x0170000, 0x110000},
 121                 {1, 0x0170000, 0x0172000, 0x12e000},
 122                 {0, 0x0000000, 0x0000000, 0x000000},
 123                 {0, 0x0000000, 0x0000000, 0x000000},
 124                 {0, 0x0000000, 0x0000000, 0x000000},
 125                 {0, 0x0000000, 0x0000000, 0x000000},
 126                 {0, 0x0000000, 0x0000000, 0x000000},
 127                 {0, 0x0000000, 0x0000000, 0x000000},
 128                 {1, 0x01e0000, 0x01e0800, 0x122000},
 129                 {0, 0x0000000, 0x0000000, 0x000000} } },
 130         {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
 131         {{{0, 0,         0,         0} } },         /* 3: */
 132         {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
 133         {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE   */
 134         {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU   */
 135         {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM    */
 136         {{{1, 0x0800000, 0x0802000, 0x170000},  /* 8: SQM0  */
 137                 {0, 0x0000000, 0x0000000, 0x000000},
 138                 {0, 0x0000000, 0x0000000, 0x000000},
 139                 {0, 0x0000000, 0x0000000, 0x000000},
 140                 {0, 0x0000000, 0x0000000, 0x000000},
 141                 {0, 0x0000000, 0x0000000, 0x000000},
 142                 {0, 0x0000000, 0x0000000, 0x000000},
 143                 {0, 0x0000000, 0x0000000, 0x000000},
 144                 {0, 0x0000000, 0x0000000, 0x000000},
 145                 {0, 0x0000000, 0x0000000, 0x000000},
 146                 {0, 0x0000000, 0x0000000, 0x000000},
 147                 {0, 0x0000000, 0x0000000, 0x000000},
 148                 {0, 0x0000000, 0x0000000, 0x000000},
 149                 {0, 0x0000000, 0x0000000, 0x000000},
 150                 {0, 0x0000000, 0x0000000, 0x000000},
 151                 {1, 0x08f0000, 0x08f2000, 0x172000} } },
 152         {{{1, 0x0900000, 0x0902000, 0x174000},  /* 9: SQM1*/
 153                 {0, 0x0000000, 0x0000000, 0x000000},
 154                 {0, 0x0000000, 0x0000000, 0x000000},
 155                 {0, 0x0000000, 0x0000000, 0x000000},
 156                 {0, 0x0000000, 0x0000000, 0x000000},
 157                 {0, 0x0000000, 0x0000000, 0x000000},
 158                 {0, 0x0000000, 0x0000000, 0x000000},
 159                 {0, 0x0000000, 0x0000000, 0x000000},
 160                 {0, 0x0000000, 0x0000000, 0x000000},
 161                 {0, 0x0000000, 0x0000000, 0x000000},
 162                 {0, 0x0000000, 0x0000000, 0x000000},
 163                 {0, 0x0000000, 0x0000000, 0x000000},
 164                 {0, 0x0000000, 0x0000000, 0x000000},
 165                 {0, 0x0000000, 0x0000000, 0x000000},
 166                 {0, 0x0000000, 0x0000000, 0x000000},
 167                 {1, 0x09f0000, 0x09f2000, 0x176000} } },
 168         {{{0, 0x0a00000, 0x0a02000, 0x178000},  /* 10: SQM2*/
 169                 {0, 0x0000000, 0x0000000, 0x000000},
 170                 {0, 0x0000000, 0x0000000, 0x000000},
 171                 {0, 0x0000000, 0x0000000, 0x000000},
 172                 {0, 0x0000000, 0x0000000, 0x000000},
 173                 {0, 0x0000000, 0x0000000, 0x000000},
 174                 {0, 0x0000000, 0x0000000, 0x000000},
 175                 {0, 0x0000000, 0x0000000, 0x000000},
 176                 {0, 0x0000000, 0x0000000, 0x000000},
 177                 {0, 0x0000000, 0x0000000, 0x000000},
 178                 {0, 0x0000000, 0x0000000, 0x000000},
 179                 {0, 0x0000000, 0x0000000, 0x000000},
 180                 {0, 0x0000000, 0x0000000, 0x000000},
 181                 {0, 0x0000000, 0x0000000, 0x000000},
 182                 {0, 0x0000000, 0x0000000, 0x000000},
 183                 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
 184         {{{0, 0x0b00000, 0x0b02000, 0x17c000},  /* 11: SQM3*/
 185                 {0, 0x0000000, 0x0000000, 0x000000},
 186                 {0, 0x0000000, 0x0000000, 0x000000},
 187                 {0, 0x0000000, 0x0000000, 0x000000},
 188                 {0, 0x0000000, 0x0000000, 0x000000},
 189                 {0, 0x0000000, 0x0000000, 0x000000},
 190                 {0, 0x0000000, 0x0000000, 0x000000},
 191                 {0, 0x0000000, 0x0000000, 0x000000},
 192                 {0, 0x0000000, 0x0000000, 0x000000},
 193                 {0, 0x0000000, 0x0000000, 0x000000},
 194                 {0, 0x0000000, 0x0000000, 0x000000},
 195                 {0, 0x0000000, 0x0000000, 0x000000},
 196                 {0, 0x0000000, 0x0000000, 0x000000},
 197                 {0, 0x0000000, 0x0000000, 0x000000},
 198                 {0, 0x0000000, 0x0000000, 0x000000},
 199                 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
 200         {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
 201         {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
 202         {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
 203         {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
 204         {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
 205         {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
 206         {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
 207         {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
 208         {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
 209         {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
 210         {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
 211         {{{0, 0,         0,         0} } },     /* 23: */
 212         {{{0, 0,         0,         0} } },     /* 24: */
 213         {{{0, 0,         0,         0} } },     /* 25: */
 214         {{{0, 0,         0,         0} } },     /* 26: */
 215         {{{0, 0,         0,         0} } },     /* 27: */
 216         {{{0, 0,         0,         0} } },     /* 28: */
 217         {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
 218         {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
 219         {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
 220         {{{0} } },                              /* 32: PCI */
 221         {{{1, 0x2100000, 0x2102000, 0x120000},  /* 33: PCIE */
 222                 {1, 0x2110000, 0x2120000, 0x130000},
 223                 {1, 0x2120000, 0x2122000, 0x124000},
 224                 {1, 0x2130000, 0x2132000, 0x126000},
 225                 {1, 0x2140000, 0x2142000, 0x128000},
 226                 {1, 0x2150000, 0x2152000, 0x12a000},
 227                 {1, 0x2160000, 0x2170000, 0x110000},
 228                 {1, 0x2170000, 0x2172000, 0x12e000},
 229                 {0, 0x0000000, 0x0000000, 0x000000},
 230                 {0, 0x0000000, 0x0000000, 0x000000},
 231                 {0, 0x0000000, 0x0000000, 0x000000},
 232                 {0, 0x0000000, 0x0000000, 0x000000},
 233                 {0, 0x0000000, 0x0000000, 0x000000},
 234                 {0, 0x0000000, 0x0000000, 0x000000},
 235                 {0, 0x0000000, 0x0000000, 0x000000},
 236                 {0, 0x0000000, 0x0000000, 0x000000} } },
 237         {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
 238         {{{0} } },                              /* 35: */
 239         {{{0} } },                              /* 36: */
 240         {{{0} } },                              /* 37: */
 241         {{{0} } },                              /* 38: */
 242         {{{0} } },                              /* 39: */
 243         {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
 244         {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
 245         {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
 246         {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
 247         {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
 248         {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
 249         {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
 250         {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
 251         {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
 252         {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
 253         {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
 254         {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
 255         {{{0} } },                              /* 52: */
 256         {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
 257         {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
 258         {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
 259         {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
 260         {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
 261         {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
 262         {{{0} } },                              /* 59: I2C0 */
 263         {{{0} } },                              /* 60: I2C1 */
 264         {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } },/* 61: LPC */
 265         {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
 266         {{{1, 0x3f00000, 0x3f01000, 0x168000} } }       /* 63: P2NR0 */
 267 };
 268
 269 /*
 270  * top 12 bits of crb internal address (hub, agent)
 271  */
 272 static unsigned qla4_82xx_crb_hub_agt[64] = {
 273         0,
 274         QLA82XX_HW_CRB_HUB_AGT_ADR_PS,
 275         QLA82XX_HW_CRB_HUB_AGT_ADR_MN,
 276         QLA82XX_HW_CRB_HUB_AGT_ADR_MS,
 277         0,
 278         QLA82XX_HW_CRB_HUB_AGT_ADR_SRE,
 279         QLA82XX_HW_CRB_HUB_AGT_ADR_NIU,
 280         QLA82XX_HW_CRB_HUB_AGT_ADR_QMN,
 281         QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0,
 282         QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1,
 283         QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2,
 284         QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3,
 285         QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q,
 286         QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR,
 287         QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB,
 288         QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4,
 289         QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA,
 290         QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0,
 291         QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1,
 292         QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2,
 293         QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3,
 294         QLA82XX_HW_CRB_HUB_AGT_ADR_PGND,
 295         QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI,
 296         QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0,
 297         QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1,
 298         QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2,
 299         QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3,
 300         0,
 301         QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI,
 302         QLA82XX_HW_CRB_HUB_AGT_ADR_SN,
 303         0,
 304         QLA82XX_HW_CRB_HUB_AGT_ADR_EG,
 305         0,
 306         QLA82XX_HW_CRB_HUB_AGT_ADR_PS,
 307         QLA82XX_HW_CRB_HUB_AGT_ADR_CAM,
 308         0,
 309         0,
 310         0,
 311         0,
 312         0,
 313         QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR,
 314         0,
 315         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1,
 316         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2,
 317         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3,
 318         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4,
 319         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5,
 320         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6,
 321         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7,
 322         QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA,
 323         QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q,
 324         QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB,
 325         0,
 326         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0,
 327         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8,
 328         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9,
 329         QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0,
 330         0,
 331         QLA82XX_HW_CRB_HUB_AGT_ADR_SMB,
 332         QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0,
 333         QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1,
 334         0,
 335         QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC,
 336         0,
 337 };
 338
 339 /* Device states */
 340 static char *qdev_state[] = {
 341         "Unknown",
 342         "Cold",
 343         "Initializing",
 344         "Ready",
 345         "Need Reset",
 346         "Need Quiescent",
 347         "Failed",
 348         "Quiescent",
 349 };
 350
 351 /*
 352  * In: 'off' is offset from CRB space in 128M pci map
 353  * Out: 'off' is 2M pci map addr
 354  * side effect: lock crb window
 355  */
 356 static void
 357 qla4_82xx_pci_set_crbwindow_2M(struct scsi_qla_host *ha, ulong *off)
 358 {
 359         u32 win_read;
 360
 361         ha->crb_win = CRB_HI(*off);
 362         writel(ha->crb_win,
 363                 (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
 364
 365         /* Read back value to make sure write has gone through before trying
 366         * to use it. */
 367         win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
 368         if (win_read != ha->crb_win) {
 369                 DEBUG2(ql4_printk(KERN_INFO, ha,
 370                     "%s: Written crbwin (0x%x) != Read crbwin (0x%x),"
 371                     " off=0x%lx\n", __func__, ha->crb_win, win_read, *off));
 372         }
 373         *off = (*off & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase;
 374 }
 375
 376 void
 377 qla4_82xx_wr_32(struct scsi_qla_host *ha, ulong off, u32 data)
 378 {
 379         unsigned long flags = 0;
 380         int rv;
 381
 382         rv = qla4_82xx_pci_get_crb_addr_2M(ha, &off);
 383
 384         BUG_ON(rv == -1);
 385
 386         if (rv == 1) {
 387                 write_lock_irqsave(&ha->hw_lock, flags);
 388                 qla4_82xx_crb_win_lock(ha);
 389                 qla4_82xx_pci_set_crbwindow_2M(ha, &off);
 390         }
 391
 392         writel(data, (void __iomem *)off);
 393
 394         if (rv == 1) {
 395                 qla4_82xx_crb_win_unlock(ha);
 396                 write_unlock_irqrestore(&ha->hw_lock, flags);
 397         }
 398 }
 399
 400 uint32_t qla4_82xx_rd_32(struct scsi_qla_host *ha, ulong off)
 401 {
 402         unsigned long flags = 0;
 403         int rv;
 404         u32 data;
 405
 406         rv = qla4_82xx_pci_get_crb_addr_2M(ha, &off);
 407
 408         BUG_ON(rv == -1);
 409
 410         if (rv == 1) {
 411                 write_lock_irqsave(&ha->hw_lock, flags);
 412                 qla4_82xx_crb_win_lock(ha);
 413                 qla4_82xx_pci_set_crbwindow_2M(ha, &off);
 414         }
 415         data = readl((void __iomem *)off);
 416
 417         if (rv == 1) {
 418                 qla4_82xx_crb_win_unlock(ha);
 419                 write_unlock_irqrestore(&ha->hw_lock, flags);
 420         }
 421         return data;
 422 }
 423
 424 /* Minidump related functions */
 425 int qla4_82xx_md_rd_32(struct scsi_qla_host *ha, uint32_t off, uint32_t *data)
 426 {
 427         uint32_t win_read, off_value;
 428         int rval = QLA_SUCCESS;
 429
 430         off_value  = off & 0xFFFF0000;
 431         writel(off_value, (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
 432
 433         /*
 434          * Read back value to make sure write has gone through before trying
 435          * to use it.
 436          */
 437         win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
 438         if (win_read != off_value) {
 439                 DEBUG2(ql4_printk(KERN_INFO, ha,
 440                                   "%s: Written (0x%x) != Read (0x%x), off=0x%x\n",
 441                                   __func__, off_value, win_read, off));
 442                 rval = QLA_ERROR;
 443         } else {
 444                 off_value  = off & 0x0000FFFF;
 445                 *data = readl((void __iomem *)(off_value + CRB_INDIRECT_2M +
 446                                                ha->nx_pcibase));
 447         }
 448         return rval;
 449 }
 450
 451 int qla4_82xx_md_wr_32(struct scsi_qla_host *ha, uint32_t off, uint32_t data)
 452 {
 453         uint32_t win_read, off_value;
 454         int rval = QLA_SUCCESS;
 455
 456         off_value  = off & 0xFFFF0000;
 457         writel(off_value, (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
 458
 459         /* Read back value to make sure write has gone through before trying
 460          * to use it.
 461          */
 462         win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
 463         if (win_read != off_value) {
 464                 DEBUG2(ql4_printk(KERN_INFO, ha,
 465                                   "%s: Written (0x%x) != Read (0x%x), off=0x%x\n",
 466                                   __func__, off_value, win_read, off));
 467                 rval = QLA_ERROR;
 468         } else {
 469                 off_value  = off & 0x0000FFFF;
 470                 writel(data, (void __iomem *)(off_value + CRB_INDIRECT_2M +
 471                                               ha->nx_pcibase));
 472         }
 473         return rval;
 474 }
 475
 476 #define CRB_WIN_LOCK_TIMEOUT 100000000
 477
 478 int qla4_82xx_crb_win_lock(struct scsi_qla_host *ha)
 479 {
 480         int i;
 481         int done = 0, timeout = 0;
 482
 483         while (!done) {
 484                 /* acquire semaphore3 from PCI HW block */
 485                 done = qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK));
 486                 if (done == 1)
 487                         break;
 488                 if (timeout >= CRB_WIN_LOCK_TIMEOUT)
 489                         return -1;
 490
 491                 timeout++;
 492
 493                 /* Yield CPU */
 494                 if (!in_interrupt())
 495                         schedule();
 496                 else {
 497                         for (i = 0; i < 20; i++)
 498                                 cpu_relax();    /*This a nop instr on i386*/
 499                 }
 500         }
 501         qla4_82xx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->func_num);
 502         return 0;
 503 }
 504
 505 void qla4_82xx_crb_win_unlock(struct scsi_qla_host *ha)
 506 {
 507         qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK));
 508 }
 509
 510 #define IDC_LOCK_TIMEOUT 100000000
 511
 512 /**
 513  * qla4_82xx_idc_lock - hw_lock
 514  * @ha: pointer to adapter structure
 515  *
 516  * General purpose lock used to synchronize access to
 517  * CRB_DEV_STATE, CRB_DEV_REF_COUNT, etc.
 518  **/
 519 int qla4_82xx_idc_lock(struct scsi_qla_host *ha)
 520 {
 521         int i;
 522         int done = 0, timeout = 0;
 523
 524         while (!done) {
 525                 /* acquire semaphore5 from PCI HW block */
 526                 done = qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK));
 527                 if (done == 1)
 528                         break;
 529                 if (timeout >= IDC_LOCK_TIMEOUT)
 530                         return -1;
 531
 532                 timeout++;
 533
 534                 /* Yield CPU */
 535                 if (!in_interrupt())
 536                         schedule();
 537                 else {
 538                         for (i = 0; i < 20; i++)
 539                                 cpu_relax();    /*This a nop instr on i386*/
 540                 }
 541         }
 542         return 0;
 543 }
 544
 545 void qla4_82xx_idc_unlock(struct scsi_qla_host *ha)
 546 {
 547         qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK));
 548 }
 549
 550 int
 551 qla4_82xx_pci_get_crb_addr_2M(struct scsi_qla_host *ha, ulong *off)
 552 {
 553         struct crb_128M_2M_sub_block_map *m;
 554
 555         if (*off >= QLA82XX_CRB_MAX)
 556                 return -1;
 557
 558         if (*off >= QLA82XX_PCI_CAMQM && (*off < QLA82XX_PCI_CAMQM_2M_END)) {
 559                 *off = (*off - QLA82XX_PCI_CAMQM) +
 560                     QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase;
 561                 return 0;
 562         }
 563
 564         if (*off < QLA82XX_PCI_CRBSPACE)
 565                 return -1;
 566
 567         *off -= QLA82XX_PCI_CRBSPACE;
 568         /*
 569          * Try direct map
 570          */
 571
 572         m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)];
 573
 574         if (m->valid && (m->start_128M <= *off) && (m->end_128M > *off)) {
 575                 *off = *off + m->start_2M - m->start_128M + ha->nx_pcibase;
 576                 return 0;
 577         }
 578
 579         /*
 580          * Not in direct map, use crb window
 581          */
 582         return 1;
 583 }
 584
 585 /*
 586 * check memory access boundary.
 587 * used by test agent. support ddr access only for now
 588 */
 589 static unsigned long
 590 qla4_82xx_pci_mem_bound_check(struct scsi_qla_host *ha,
 591                 unsigned long long addr, int size)
 592 {
 593         if (!QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_DDR_NET,
 594             QLA8XXX_ADDR_DDR_NET_MAX) ||
 595             !QLA8XXX_ADDR_IN_RANGE(addr + size - 1,
 596             QLA8XXX_ADDR_DDR_NET, QLA8XXX_ADDR_DDR_NET_MAX) ||
 597             ((size != 1) && (size != 2) && (size != 4) && (size != 8))) {
 598                 return 0;
 599         }
 600         return 1;
 601 }
 602
 603 static int qla4_82xx_pci_set_window_warning_count;
 604
 605 static unsigned long
 606 qla4_82xx_pci_set_window(struct scsi_qla_host *ha, unsigned long long addr)
 607 {
 608         int window;
 609         u32 win_read;
 610
 611         if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_DDR_NET,
 612             QLA8XXX_ADDR_DDR_NET_MAX)) {
 613                 /* DDR network side */
 614                 window = MN_WIN(addr);
 615                 ha->ddr_mn_window = window;
 616                 qla4_82xx_wr_32(ha, ha->mn_win_crb |
 617                     QLA82XX_PCI_CRBSPACE, window);
 618                 win_read = qla4_82xx_rd_32(ha, ha->mn_win_crb |
 619                     QLA82XX_PCI_CRBSPACE);
 620                 if ((win_read << 17) != window) {
 621                         ql4_printk(KERN_WARNING, ha,
 622                         "%s: Written MNwin (0x%x) != Read MNwin (0x%x)\n",
 623                         __func__, window, win_read);
 624                 }
 625                 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET;
 626         } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_OCM0,
 627                                 QLA8XXX_ADDR_OCM0_MAX)) {
 628                 unsigned int temp1;
 629                 /* if bits 19:18&17:11 are on */
 630                 if ((addr & 0x00ff800) == 0xff800) {
 631                         printk("%s: QM access not handled.\n", __func__);
 632                         addr = -1UL;
 633                 }
 634
 635                 window = OCM_WIN(addr);
 636                 ha->ddr_mn_window = window;
 637                 qla4_82xx_wr_32(ha, ha->mn_win_crb |
 638                     QLA82XX_PCI_CRBSPACE, window);
 639                 win_read = qla4_82xx_rd_32(ha, ha->mn_win_crb |
 640                     QLA82XX_PCI_CRBSPACE);
 641                 temp1 = ((window & 0x1FF) << 7) |
 642                     ((window & 0x0FFFE0000) >> 17);
 643                 if (win_read != temp1) {
 644                         printk("%s: Written OCMwin (0x%x) != Read"
 645                             " OCMwin (0x%x)\n", __func__, temp1, win_read);
 646                 }
 647                 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M;
 648
 649         } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_QDR_NET,
 650                                 QLA82XX_P3_ADDR_QDR_NET_MAX)) {
 651                 /* QDR network side */
 652                 window = MS_WIN(addr);
 653                 ha->qdr_sn_window = window;
 654                 qla4_82xx_wr_32(ha, ha->ms_win_crb |
 655                     QLA82XX_PCI_CRBSPACE, window);
 656                 win_read = qla4_82xx_rd_32(ha,
 657                      ha->ms_win_crb | QLA82XX_PCI_CRBSPACE);
 658                 if (win_read != window) {
 659                         printk("%s: Written MSwin (0x%x) != Read "
 660                             "MSwin (0x%x)\n", __func__, window, win_read);
 661                 }
 662                 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_QDR_NET;
 663
 664         } else {
 665                 /*
 666                  * peg gdb frequently accesses memory that doesn't exist,
 667                  * this limits the chit chat so debugging isn't slowed down.
 668                  */
 669                 if ((qla4_82xx_pci_set_window_warning_count++ < 8) ||
 670                     (qla4_82xx_pci_set_window_warning_count%64 == 0)) {
 671                         printk("%s: Warning:%s Unknown address range!\n",
 672                             __func__, DRIVER_NAME);
 673                 }
 674                 addr = -1UL;
 675         }
 676         return addr;
 677 }
 678
 679 /* check if address is in the same windows as the previous access */
 680 static int qla4_82xx_pci_is_same_window(struct scsi_qla_host *ha,
 681                 unsigned long long addr)
 682 {
 683         int window;
 684         unsigned long long qdr_max;
 685
 686         qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX;
 687
 688         if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_DDR_NET,
 689             QLA8XXX_ADDR_DDR_NET_MAX)) {
 690                 /* DDR network side */
 691                 BUG();  /* MN access can not come here */
 692         } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_OCM0,
 693              QLA8XXX_ADDR_OCM0_MAX)) {
 694                 return 1;
 695         } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_OCM1,
 696              QLA8XXX_ADDR_OCM1_MAX)) {
 697                 return 1;
 698         } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_QDR_NET,
 699             qdr_max)) {
 700                 /* QDR network side */
 701                 window = ((addr - QLA8XXX_ADDR_QDR_NET) >> 22) & 0x3f;
 702                 if (ha->qdr_sn_window == window)
 703                         return 1;
 704         }
 705
 706         return 0;
 707 }
 708
 709 static int qla4_82xx_pci_mem_read_direct(struct scsi_qla_host *ha,
 710                 u64 off, void *data, int size)
 711 {
 712         unsigned long flags;
 713         void __iomem *addr;
 714         int ret = 0;
 715         u64 start;
 716         void __iomem *mem_ptr = NULL;
 717         unsigned long mem_base;
 718         unsigned long mem_page;
 719
 720         write_lock_irqsave(&ha->hw_lock, flags);
 721
 722         /*
 723          * If attempting to access unknown address or straddle hw windows,
 724          * do not access.
 725          */
 726         start = qla4_82xx_pci_set_window(ha, off);
 727         if ((start == -1UL) ||
 728             (qla4_82xx_pci_is_same_window(ha, off + size - 1) == 0)) {
 729                 write_unlock_irqrestore(&ha->hw_lock, flags);
 730                 printk(KERN_ERR"%s out of bound pci memory access. "
 731                                 "offset is 0x%llx\n", DRIVER_NAME, off);
 732                 return -1;
 733         }
 734
 735         addr = qla4_8xxx_pci_base_offsetfset(ha, start);
 736         if (!addr) {
 737                 write_unlock_irqrestore(&ha->hw_lock, flags);
 738                 mem_base = pci_resource_start(ha->pdev, 0);
 739                 mem_page = start & PAGE_MASK;
 740                 /* Map two pages whenever user tries to access addresses in two
 741                    consecutive pages.
 742                  */
 743                 if (mem_page != ((start + size - 1) & PAGE_MASK))
 744                         mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2);
 745                 else
 746                         mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
 747
 748                 if (mem_ptr == NULL) {
 749                         *(u8 *)data = 0;
 750                         return -1;
 751                 }
 752                 addr = mem_ptr;
 753                 addr += start & (PAGE_SIZE - 1);
 754                 write_lock_irqsave(&ha->hw_lock, flags);
 755         }
 756
 757         switch (size) {
 758         case 1:
 759                 *(u8  *)data = readb(addr);
 760                 break;
 761         case 2:
 762                 *(u16 *)data = readw(addr);
 763                 break;
 764         case 4:
 765                 *(u32 *)data = readl(addr);
 766                 break;
 767         case 8:
 768                 *(u64 *)data = readq(addr);
 769                 break;
 770         default:
 771                 ret = -1;
 772                 break;
 773         }
 774         write_unlock_irqrestore(&ha->hw_lock, flags);
 775
 776         if (mem_ptr)
 777                 iounmap(mem_ptr);
 778         return ret;
 779 }
 780
 781 static int
 782 qla4_82xx_pci_mem_write_direct(struct scsi_qla_host *ha, u64 off,
 783                 void *data, int size)
 784 {
 785         unsigned long flags;
 786         void __iomem *addr;
 787         int ret = 0;
 788         u64 start;
 789         void __iomem *mem_ptr = NULL;
 790         unsigned long mem_base;
 791         unsigned long mem_page;
 792
 793         write_lock_irqsave(&ha->hw_lock, flags);
 794
 795         /*
 796          * If attempting to access unknown address or straddle hw windows,
 797          * do not access.
 798          */
 799         start = qla4_82xx_pci_set_window(ha, off);
 800         if ((start == -1UL) ||
 801             (qla4_82xx_pci_is_same_window(ha, off + size - 1) == 0)) {
 802                 write_unlock_irqrestore(&ha->hw_lock, flags);
 803                 printk(KERN_ERR"%s out of bound pci memory access. "
 804                                 "offset is 0x%llx\n", DRIVER_NAME, off);
 805                 return -1;
 806         }
 807
 808         addr = qla4_8xxx_pci_base_offsetfset(ha, start);
 809         if (!addr) {
 810                 write_unlock_irqrestore(&ha->hw_lock, flags);
 811                 mem_base = pci_resource_start(ha->pdev, 0);
 812                 mem_page = start & PAGE_MASK;
 813                 /* Map two pages whenever user tries to access addresses in two
 814                    consecutive pages.
 815                  */
 816                 if (mem_page != ((start + size - 1) & PAGE_MASK))
 817                         mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2);
 818                 else
 819                         mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
 820                 if (mem_ptr == NULL)
 821                         return -1;
 822
 823                 addr = mem_ptr;
 824                 addr += start & (PAGE_SIZE - 1);
 825                 write_lock_irqsave(&ha->hw_lock, flags);
 826         }
 827
 828         switch (size) {
 829         case 1:
 830                 writeb(*(u8 *)data, addr);
 831                 break;
 832         case 2:
 833                 writew(*(u16 *)data, addr);
 834                 break;
 835         case 4:
 836                 writel(*(u32 *)data, addr);
 837                 break;
 838         case 8:
 839                 writeq(*(u64 *)data, addr);
 840                 break;
 841         default:
 842                 ret = -1;
 843                 break;
 844         }
 845         write_unlock_irqrestore(&ha->hw_lock, flags);
 846         if (mem_ptr)
 847                 iounmap(mem_ptr);
 848         return ret;
 849 }
 850
 851 #define MTU_FUDGE_FACTOR 100
 852
 853 static unsigned long
 854 qla4_82xx_decode_crb_addr(unsigned long addr)
 855 {
 856         int i;
 857         unsigned long base_addr, offset, pci_base;
 858
 859         if (!qla4_8xxx_crb_table_initialized)
 860                 qla4_82xx_crb_addr_transform_setup();
 861
 862         pci_base = ADDR_ERROR;
 863         base_addr = addr & 0xfff00000;
 864         offset = addr & 0x000fffff;
 865
 866         for (i = 0; i < MAX_CRB_XFORM; i++) {
 867                 if (crb_addr_xform[i] == base_addr) {
 868                         pci_base = i << 20;
 869                         break;
 870                 }
 871         }
 872         if (pci_base == ADDR_ERROR)
 873                 return pci_base;
 874         else
 875                 return pci_base + offset;
 876 }
 877
 878 static long rom_max_timeout = 100;
 879 static long qla4_82xx_rom_lock_timeout = 100;
 880
 881 static int
 882 qla4_82xx_rom_lock(struct scsi_qla_host *ha)
 883 {
 884         int i;
 885         int done = 0, timeout = 0;
 886
 887         while (!done) {
 888                 /* acquire semaphore2 from PCI HW block */
 889
 890                 done = qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK));
 891                 if (done == 1)
 892                         break;
 893                 if (timeout >= qla4_82xx_rom_lock_timeout)
 894                         return -1;
 895
 896                 timeout++;
 897
 898                 /* Yield CPU */
 899                 if (!in_interrupt())
 900                         schedule();
 901                 else {
 902                         for (i = 0; i < 20; i++)
 903                                 cpu_relax();    /*This a nop instr on i386*/
 904                 }
 905         }
 906         qla4_82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ROM_LOCK_DRIVER);
 907         return 0;
 908 }
 909
 910 static void
 911 qla4_82xx_rom_unlock(struct scsi_qla_host *ha)
 912 {
 913         qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK));
 914 }
 915
 916 static int
 917 qla4_82xx_wait_rom_done(struct scsi_qla_host *ha)
 918 {
 919         long timeout = 0;
 920         long done = 0 ;
 921
 922         while (done == 0) {
 923                 done = qla4_82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS);
 924                 done &= 2;
 925                 timeout++;
 926                 if (timeout >= rom_max_timeout) {
 927                         printk("%s: Timeout reached  waiting for rom done",
 928                                         DRIVER_NAME);
 929                         return -1;
 930                 }
 931         }
 932         return 0;
 933 }
 934
 935 static int
 936 qla4_82xx_do_rom_fast_read(struct scsi_qla_host *ha, int addr, int *valp)
 937 {
 938         qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr);
 939         qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
 940         qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3);
 941         qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0xb);
 942         if (qla4_82xx_wait_rom_done(ha)) {
 943                 printk("%s: Error waiting for rom done\n", DRIVER_NAME);
 944                 return -1;
 945         }
 946         /* reset abyte_cnt and dummy_byte_cnt */
 947         qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
 948         udelay(10);
 949         qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0);
 950
 951         *valp = qla4_82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA);
 952         return 0;
 953 }
 954
 955 static int
 956 qla4_82xx_rom_fast_read(struct scsi_qla_host *ha, int addr, int *valp)
 957 {
 958         int ret, loops = 0;
 959
 960         while ((qla4_82xx_rom_lock(ha) != 0) && (loops < 50000)) {
 961                 udelay(100);
 962                 loops++;
 963         }
 964         if (loops >= 50000) {
 965                 ql4_printk(KERN_WARNING, ha, "%s: qla4_82xx_rom_lock failed\n",
 966                            DRIVER_NAME);
 967                 return -1;
 968         }
 969         ret = qla4_82xx_do_rom_fast_read(ha, addr, valp);
 970         qla4_82xx_rom_unlock(ha);
 971         return ret;
 972 }
 973
 974 /**
 975  * This routine does CRB initialize sequence
 976  * to put the ISP into operational state
 977  **/
 978 static int
 979 qla4_82xx_pinit_from_rom(struct scsi_qla_host *ha, int verbose)
 980 {
 981         int addr, val;
 982         int i ;
 983         struct crb_addr_pair *buf;
 984         unsigned long off;
 985         unsigned offset, n;
 986
 987         struct crb_addr_pair {
 988                 long addr;
 989                 long data;
 990         };
 991
 992         /* Halt all the indiviual PEGs and other blocks of the ISP */
 993         qla4_82xx_rom_lock(ha);
 994
 995         /* disable all I2Q */
 996         qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x10, 0x0);
 997         qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x14, 0x0);
 998         qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x18, 0x0);
 999         qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x1c, 0x0);
1000         qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x20, 0x0);
1001         qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x24, 0x0);
1002
1003         /* disable all niu interrupts */
1004         qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x40, 0xff);
1005         /* disable xge rx/tx */
1006         qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x70000, 0x00);
1007         /* disable xg1 rx/tx */
1008         qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x80000, 0x00);
1009         /* disable sideband mac */
1010         qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x90000, 0x00);
1011         /* disable ap0 mac */
1012         qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xa0000, 0x00);
1013         /* disable ap1 mac */
1014         qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xb0000, 0x00);
1015
1016         /* halt sre */
1017         val = qla4_82xx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000);
1018         qla4_82xx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1)));
1019
1020         /* halt epg */
1021         qla4_82xx_wr_32(ha, QLA82XX_CRB_EPG + 0x1300, 0x1);
1022
1023         /* halt timers */
1024         qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x0, 0x0);
1025         qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x8, 0x0);
1026         qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x10, 0x0);
1027         qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x18, 0x0);
1028         qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x100, 0x0);
1029         qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x200, 0x0);
1030
1031         /* halt pegs */
1032         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c, 1);
1033         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c, 1);
1034         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c, 1);
1035         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c, 1);
1036         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c, 1);
1037         msleep(5);
1038
1039         /* big hammer */
1040         if (test_bit(DPC_RESET_HA, &ha->dpc_flags))
1041                 /* don't reset CAM block on reset */
1042                 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff);
1043         else
1044                 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff);
1045
1046         qla4_82xx_rom_unlock(ha);
1047
1048         /* Read the signature value from the flash.
1049          * Offset 0: Contain signature (0xcafecafe)
1050          * Offset 4: Offset and number of addr/value pairs
1051          * that present in CRB initialize sequence
1052          */
1053         if (qla4_82xx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL ||
1054             qla4_82xx_rom_fast_read(ha, 4, &n) != 0) {
1055                 ql4_printk(KERN_WARNING, ha,
1056                         "[ERROR] Reading crb_init area: n: %08x\n", n);
1057                 return -1;
1058         }
1059
1060         /* Offset in flash = lower 16 bits
1061          * Number of enteries = upper 16 bits
1062          */
1063         offset = n & 0xffffU;
1064         n = (n >> 16) & 0xffffU;
1065
1066         /* number of addr/value pair should not exceed 1024 enteries */
1067         if (n  >= 1024) {
1068                 ql4_printk(KERN_WARNING, ha,
1069                     "%s: %s:n=0x%x [ERROR] Card flash not initialized.\n",
1070                     DRIVER_NAME, __func__, n);
1071                 return -1;
1072         }
1073
1074         ql4_printk(KERN_INFO, ha,
1075                 "%s: %d CRB init values found in ROM.\n", DRIVER_NAME, n);
1076
1077         buf = kmalloc(n * sizeof(struct crb_addr_pair), GFP_KERNEL);
1078         if (buf == NULL) {
1079                 ql4_printk(KERN_WARNING, ha,
1080                     "%s: [ERROR] Unable to malloc memory.\n", DRIVER_NAME);
1081                 return -1;
1082         }
1083
1084         for (i = 0; i < n; i++) {
1085                 if (qla4_82xx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 ||
1086                     qla4_82xx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) !=
1087                     0) {
1088                         kfree(buf);
1089                         return -1;
1090                 }
1091
1092                 buf[i].addr = addr;
1093                 buf[i].data = val;
1094         }
1095
1096         for (i = 0; i < n; i++) {
1097                 /* Translate internal CRB initialization
1098                  * address to PCI bus address
1099                  */
1100                 off = qla4_82xx_decode_crb_addr((unsigned long)buf[i].addr) +
1101                     QLA82XX_PCI_CRBSPACE;
1102                 /* Not all CRB  addr/value pair to be written,
1103                  * some of them are skipped
1104                  */
1105
1106                 /* skip if LS bit is set*/
1107                 if (off & 0x1) {
1108                         DEBUG2(ql4_printk(KERN_WARNING, ha,
1109                             "Skip CRB init replay for offset = 0x%lx\n", off));
1110                         continue;
1111                 }
1112
1113                 /* skipping cold reboot MAGIC */
1114                 if (off == QLA82XX_CAM_RAM(0x1fc))
1115                         continue;
1116
1117                 /* do not reset PCI */
1118                 if (off == (ROMUSB_GLB + 0xbc))
1119                         continue;
1120
1121                 /* skip core clock, so that firmware can increase the clock */
1122                 if (off == (ROMUSB_GLB + 0xc8))
1123                         continue;
1124
1125                 /* skip the function enable register */
1126                 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION))
1127                         continue;
1128
1129                 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION2))
1130                         continue;
1131
1132                 if ((off & 0x0ff00000) == QLA82XX_CRB_SMB)
1133                         continue;
1134
1135                 if ((off & 0x0ff00000) == QLA82XX_CRB_DDR_NET)
1136                         continue;
1137
1138                 if (off == ADDR_ERROR) {
1139                         ql4_printk(KERN_WARNING, ha,
1140                             "%s: [ERROR] Unknown addr: 0x%08lx\n",
1141                             DRIVER_NAME, buf[i].addr);
1142                         continue;
1143                 }
1144
1145                 qla4_82xx_wr_32(ha, off, buf[i].data);
1146
1147                 /* ISP requires much bigger delay to settle down,
1148                  * else crb_window returns 0xffffffff
1149                  */
1150                 if (off == QLA82XX_ROMUSB_GLB_SW_RESET)
1151                         msleep(1000);
1152
1153                 /* ISP requires millisec delay between
1154                  * successive CRB register updation
1155                  */
1156                 msleep(1);
1157         }
1158
1159         kfree(buf);
1160
1161         /* Resetting the data and instruction cache */
1162         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e);
1163         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8);
1164         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8);
1165
1166         /* Clear all protocol processing engines */
1167         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0);
1168         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0);
1169         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0);
1170         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0);
1171         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0);
1172         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0);
1173         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0);
1174         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0);
1175
1176         return 0;
1177 }
1178
1179 static int
1180 qla4_82xx_load_from_flash(struct scsi_qla_host *ha, uint32_t image_start)
1181 {
1182         int  i, rval = 0;
1183         long size = 0;
1184         long flashaddr, memaddr;
1185         u64 data;
1186         u32 high, low;
1187
1188         flashaddr = memaddr = ha->hw.flt_region_bootload;
1189         size = (image_start - flashaddr) / 8;
1190
1191         DEBUG2(printk("scsi%ld: %s: bootldr=0x%lx, fw_image=0x%x\n",
1192             ha->host_no, __func__, flashaddr, image_start));
1193
1194         for (i = 0; i < size; i++) {
1195                 if ((qla4_82xx_rom_fast_read(ha, flashaddr, (int *)&low)) ||
1196                     (qla4_82xx_rom_fast_read(ha, flashaddr + 4,
1197                     (int *)&high))) {
1198                         rval = -1;
1199                         goto exit_load_from_flash;
1200                 }
1201                 data = ((u64)high << 32) | low ;
1202                 rval = qla4_82xx_pci_mem_write_2M(ha, memaddr, &data, 8);
1203                 if (rval)
1204                         goto exit_load_from_flash;
1205
1206                 flashaddr += 8;
1207                 memaddr   += 8;
1208
1209                 if (i % 0x1000 == 0)
1210                         msleep(1);
1211
1212         }
1213
1214         udelay(100);
1215
1216         read_lock(&ha->hw_lock);
1217         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020);
1218         qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e);
1219         read_unlock(&ha->hw_lock);
1220
1221 exit_load_from_flash:
1222         return rval;
1223 }
1224
1225 static int qla4_82xx_load_fw(struct scsi_qla_host *ha, uint32_t image_start)
1226 {
1227         u32 rst;
1228
1229         qla4_82xx_wr_32(ha, CRB_CMDPEG_STATE, 0);
1230         if (qla4_82xx_pinit_from_rom(ha, 0) != QLA_SUCCESS) {
1231                 printk(KERN_WARNING "%s: Error during CRB Initialization\n",
1232                     __func__);
1233                 return QLA_ERROR;
1234         }
1235
1236         udelay(500);
1237
1238         /* at this point, QM is in reset. This could be a problem if there are
1239          * incoming d* transition queue messages. QM/PCIE could wedge.
1240          * To get around this, QM is brought out of reset.
1241          */
1242
1243         rst = qla4_82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET);
1244         /* unreset qm */
1245         rst &= ~(1 << 28);
1246         qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst);
1247
1248         if (qla4_82xx_load_from_flash(ha, image_start)) {
1249                 printk("%s: Error trying to load fw from flash!\n", __func__);
1250                 return QLA_ERROR;
1251         }
1252
1253         return QLA_SUCCESS;
1254 }
1255
1256 int
1257 qla4_82xx_pci_mem_read_2M(struct scsi_qla_host *ha,
1258                 u64 off, void *data, int size)
1259 {
1260         int i, j = 0, k, start, end, loop, sz[2], off0[2];
1261         int shift_amount;
1262         uint32_t temp;
1263         uint64_t off8, val, mem_crb, word[2] = {0, 0};
1264
1265         /*
1266          * If not MN, go check for MS or invalid.
1267          */
1268
1269         if (off >= QLA8XXX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
1270                 mem_crb = QLA82XX_CRB_QDR_NET;
1271         else {
1272                 mem_crb = QLA82XX_CRB_DDR_NET;
1273                 if (qla4_82xx_pci_mem_bound_check(ha, off, size) == 0)
1274                         return qla4_82xx_pci_mem_read_direct(ha,
1275                                         off, data, size);
1276         }
1277
1278
1279         off8 = off & 0xfffffff0;
1280         off0[0] = off & 0xf;
1281         sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]);
1282         shift_amount = 4;
1283
1284         loop = ((off0[0] + size - 1) >> shift_amount) + 1;
1285         off0[1] = 0;
1286         sz[1] = size - sz[0];
1287
1288         for (i = 0; i < loop; i++) {
1289                 temp = off8 + (i << shift_amount);
1290                 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp);
1291                 temp = 0;
1292                 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp);
1293                 temp = MIU_TA_CTL_ENABLE;
1294                 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1295                 temp = MIU_TA_CTL_START_ENABLE;
1296                 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1297
1298                 for (j = 0; j < MAX_CTL_CHECK; j++) {
1299                         temp = qla4_82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
1300                         if ((temp & MIU_TA_CTL_BUSY) == 0)
1301                                 break;
1302                 }
1303
1304                 if (j >= MAX_CTL_CHECK) {
1305                         printk_ratelimited(KERN_ERR
1306                                            "%s: failed to read through agent\n",
1307                                            __func__);
1308                         break;
1309                 }
1310
1311                 start = off0[i] >> 2;
1312                 end   = (off0[i] + sz[i] - 1) >> 2;
1313                 for (k = start; k <= end; k++) {
1314                         temp = qla4_82xx_rd_32(ha,
1315                                 mem_crb + MIU_TEST_AGT_RDDATA(k));
1316                         word[i] |= ((uint64_t)temp << (32 * (k & 1)));
1317                 }
1318         }
1319
1320         if (j >= MAX_CTL_CHECK)
1321                 return -1;
1322
1323         if ((off0[0] & 7) == 0) {
1324                 val = word[0];
1325         } else {
1326                 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1327                 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1328         }
1329
1330         switch (size) {
1331         case 1:
1332                 *(uint8_t  *)data = val;
1333                 break;
1334         case 2:
1335                 *(uint16_t *)data = val;
1336                 break;
1337         case 4:
1338                 *(uint32_t *)data = val;
1339                 break;
1340         case 8:
1341                 *(uint64_t *)data = val;
1342                 break;
1343         }
1344         return 0;
1345 }
1346
1347 int
1348 qla4_82xx_pci_mem_write_2M(struct scsi_qla_host *ha,
1349                 u64 off, void *data, int size)
1350 {
1351         int i, j, ret = 0, loop, sz[2], off0;
1352         int scale, shift_amount, startword;
1353         uint32_t temp;
1354         uint64_t off8, mem_crb, tmpw, word[2] = {0, 0};
1355
1356         /*
1357          * If not MN, go check for MS or invalid.
1358          */
1359         if (off >= QLA8XXX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
1360                 mem_crb = QLA82XX_CRB_QDR_NET;
1361         else {
1362                 mem_crb = QLA82XX_CRB_DDR_NET;
1363                 if (qla4_82xx_pci_mem_bound_check(ha, off, size) == 0)
1364                         return qla4_82xx_pci_mem_write_direct(ha,
1365                                         off, data, size);
1366         }
1367
1368         off0 = off & 0x7;
1369         sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1370         sz[1] = size - sz[0];
1371
1372         off8 = off & 0xfffffff0;
1373         loop = (((off & 0xf) + size - 1) >> 4) + 1;
1374         shift_amount = 4;
1375         scale = 2;
1376         startword = (off & 0xf)/8;
1377
1378         for (i = 0; i < loop; i++) {
1379                 if (qla4_82xx_pci_mem_read_2M(ha, off8 +
1380                     (i << shift_amount), &word[i * scale], 8))
1381                         return -1;
1382         }
1383
1384         switch (size) {
1385         case 1:
1386                 tmpw = *((uint8_t *)data);
1387                 break;
1388         case 2:
1389                 tmpw = *((uint16_t *)data);
1390                 break;
1391         case 4:
1392                 tmpw = *((uint32_t *)data);
1393                 break;
1394         case 8:
1395         default:
1396                 tmpw = *((uint64_t *)data);
1397                 break;
1398         }
1399
1400         if (sz[0] == 8)
1401                 word[startword] = tmpw;
1402         else {
1403                 word[startword] &=
1404                     ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1405                 word[startword] |= tmpw << (off0 * 8);
1406         }
1407
1408         if (sz[1] != 0) {
1409                 word[startword+1] &= ~(~0ULL << (sz[1] * 8));
1410                 word[startword+1] |= tmpw >> (sz[0] * 8);
1411         }
1412
1413         for (i = 0; i < loop; i++) {
1414                 temp = off8 + (i << shift_amount);
1415                 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp);
1416                 temp = 0;
1417                 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp);
1418                 temp = word[i * scale] & 0xffffffff;
1419                 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp);
1420                 temp = (word[i * scale] >> 32) & 0xffffffff;
1421                 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp);
1422                 temp = word[i*scale + 1] & 0xffffffff;
1423                 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_WRDATA_UPPER_LO,
1424                     temp);
1425                 temp = (word[i*scale + 1] >> 32) & 0xffffffff;
1426                 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_WRDATA_UPPER_HI,
1427                     temp);
1428
1429                 temp = MIU_TA_CTL_WRITE_ENABLE;
1430                 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp);
1431                 temp = MIU_TA_CTL_WRITE_START;
1432                 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp);
1433
1434                 for (j = 0; j < MAX_CTL_CHECK; j++) {
1435                         temp = qla4_82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
1436                         if ((temp & MIU_TA_CTL_BUSY) == 0)
1437                                 break;
1438                 }
1439
1440                 if (j >= MAX_CTL_CHECK) {
1441                         if (printk_ratelimit())
1442                                 ql4_printk(KERN_ERR, ha,
1443                                            "%s: failed to read through agent\n",
1444                                            __func__);
1445                         ret = -1;
1446                         break;
1447                 }
1448         }
1449
1450         return ret;
1451 }
1452
1453 static int qla4_82xx_cmdpeg_ready(struct scsi_qla_host *ha, int pegtune_val)
1454 {
1455         u32 val = 0;
1456         int retries = 60;
1457
1458         if (!pegtune_val) {
1459                 do {
1460                         val = qla4_82xx_rd_32(ha, CRB_CMDPEG_STATE);
1461                         if ((val == PHAN_INITIALIZE_COMPLETE) ||
1462                             (val == PHAN_INITIALIZE_ACK))
1463                                 return 0;
1464                         set_current_state(TASK_UNINTERRUPTIBLE);
1465                         schedule_timeout(500);
1466
1467                 } while (--retries);
1468
1469                 if (!retries) {
1470                         pegtune_val = qla4_82xx_rd_32(ha,
1471                                 QLA82XX_ROMUSB_GLB_PEGTUNE_DONE);
1472                         printk(KERN_WARNING "%s: init failed, "
1473                                 "pegtune_val = %x\n", __func__, pegtune_val);
1474                         return -1;
1475                 }
1476         }
1477         return 0;
1478 }
1479
1480 static int qla4_82xx_rcvpeg_ready(struct scsi_qla_host *ha)
1481 {
1482         uint32_t state = 0;
1483         int loops = 0;
1484
1485         /* Window 1 call */
1486         read_lock(&ha->hw_lock);
1487         state = qla4_82xx_rd_32(ha, CRB_RCVPEG_STATE);
1488         read_unlock(&ha->hw_lock);
1489
1490         while ((state != PHAN_PEG_RCV_INITIALIZED) && (loops < 30000)) {
1491                 udelay(100);
1492                 /* Window 1 call */
1493                 read_lock(&ha->hw_lock);
1494                 state = qla4_82xx_rd_32(ha, CRB_RCVPEG_STATE);
1495                 read_unlock(&ha->hw_lock);
1496
1497                 loops++;
1498         }
1499
1500         if (loops >= 30000) {
1501                 DEBUG2(ql4_printk(KERN_INFO, ha,
1502                     "Receive Peg initialization not complete: 0x%x.\n", state));
1503                 return QLA_ERROR;
1504         }
1505
1506         return QLA_SUCCESS;
1507 }
1508
1509 void
1510 qla4_8xxx_set_drv_active(struct scsi_qla_host *ha)
1511 {
1512         uint32_t drv_active;
1513
1514         drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
1515
1516         /*
1517          * For ISP8324, drv_active register has 1 bit per function,
1518          * shift 1 by func_num to set a bit for the function.
1519          * For ISP8022, drv_active has 4 bits per function
1520          */
1521         if (is_qla8032(ha))
1522                 drv_active |= (1 << ha->func_num);
1523         else
1524                 drv_active |= (1 << (ha->func_num * 4));
1525
1526         ql4_printk(KERN_INFO, ha, "%s(%ld): drv_active: 0x%08x\n",
1527                    __func__, ha->host_no, drv_active);
1528         qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_ACTIVE, drv_active);
1529 }
1530
1531 void
1532 qla4_8xxx_clear_drv_active(struct scsi_qla_host *ha)
1533 {
1534         uint32_t drv_active;
1535
1536         drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
1537
1538         /*
1539          * For ISP8324, drv_active register has 1 bit per function,
1540          * shift 1 by func_num to set a bit for the function.
1541          * For ISP8022, drv_active has 4 bits per function
1542          */
1543         if (is_qla8032(ha))
1544                 drv_active &= ~(1 << (ha->func_num));
1545         else
1546                 drv_active &= ~(1 << (ha->func_num * 4));
1547
1548         ql4_printk(KERN_INFO, ha, "%s(%ld): drv_active: 0x%08x\n",
1549                    __func__, ha->host_no, drv_active);
1550         qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_ACTIVE, drv_active);
1551 }
1552
1553 inline int qla4_8xxx_need_reset(struct scsi_qla_host *ha)
1554 {
1555         uint32_t drv_state, drv_active;
1556         int rval;
1557
1558         drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
1559         drv_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE);
1560
1561         /*
1562          * For ISP8324, drv_active register has 1 bit per function,
1563          * shift 1 by func_num to set a bit for the function.
1564          * For ISP8022, drv_active has 4 bits per function
1565          */
1566         if (is_qla8032(ha))
1567                 rval = drv_state & (1 << ha->func_num);
1568         else
1569                 rval = drv_state & (1 << (ha->func_num * 4));
1570
1571         if ((test_bit(AF_EEH_BUSY, &ha->flags)) && drv_active)
1572                 rval = 1;
1573
1574         return rval;
1575 }
1576
1577 void qla4_8xxx_set_rst_ready(struct scsi_qla_host *ha)
1578 {
1579         uint32_t drv_state;
1580
1581         drv_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE);
1582
1583         /*
1584          * For ISP8324, drv_active register has 1 bit per function,
1585          * shift 1 by func_num to set a bit for the function.
1586          * For ISP8022, drv_active has 4 bits per function
1587          */
1588         if (is_qla8032(ha))
1589                 drv_state |= (1 << ha->func_num);
1590         else
1591                 drv_state |= (1 << (ha->func_num * 4));
1592
1593         ql4_printk(KERN_INFO, ha, "%s(%ld): drv_state: 0x%08x\n",
1594                    __func__, ha->host_no, drv_state);
1595         qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_STATE, drv_state);
1596 }
1597
1598 void qla4_8xxx_clear_rst_ready(struct scsi_qla_host *ha)
1599 {
1600         uint32_t drv_state;
1601
1602         drv_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE);
1603
1604         /*
1605          * For ISP8324, drv_active register has 1 bit per function,
1606          * shift 1 by func_num to set a bit for the function.
1607          * For ISP8022, drv_active has 4 bits per function
1608          */
1609         if (is_qla8032(ha))
1610                 drv_state &= ~(1 << ha->func_num);
1611         else
1612                 drv_state &= ~(1 << (ha->func_num * 4));
1613
1614         ql4_printk(KERN_INFO, ha, "%s(%ld): drv_state: 0x%08x\n",
1615                    __func__, ha->host_no, drv_state);
1616         qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_STATE, drv_state);
1617 }
1618
1619 static inline void
1620 qla4_8xxx_set_qsnt_ready(struct scsi_qla_host *ha)
1621 {
1622         uint32_t qsnt_state;
1623
1624         qsnt_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE);
1625
1626         /*
1627          * For ISP8324, drv_active register has 1 bit per function,
1628          * shift 1 by func_num to set a bit for the function.
1629          * For ISP8022, drv_active has 4 bits per function.
1630          */
1631         if (is_qla8032(ha))
1632                 qsnt_state |= (1 << ha->func_num);
1633         else
1634                 qsnt_state |= (2 << (ha->func_num * 4));
1635
1636         qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_STATE, qsnt_state);
1637 }
1638
1639
1640 static int
1641 qla4_82xx_start_firmware(struct scsi_qla_host *ha, uint32_t image_start)
1642 {
1643         uint16_t lnk;
1644
1645         /* scrub dma mask expansion register */
1646         qla4_82xx_wr_32(ha, CRB_DMA_SHIFT, 0x55555555);
1647
1648         /* Overwrite stale initialization register values */
1649         qla4_82xx_wr_32(ha, CRB_CMDPEG_STATE, 0);
1650         qla4_82xx_wr_32(ha, CRB_RCVPEG_STATE, 0);
1651         qla4_82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0);
1652         qla4_82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0);
1653
1654         if (qla4_82xx_load_fw(ha, image_start) != QLA_SUCCESS) {
1655                 printk("%s: Error trying to start fw!\n", __func__);
1656                 return QLA_ERROR;
1657         }
1658
1659         /* Handshake with the card before we register the devices. */
1660         if (qla4_82xx_cmdpeg_ready(ha, 0) != QLA_SUCCESS) {
1661                 printk("%s: Error during card handshake!\n", __func__);
1662                 return QLA_ERROR;
1663         }
1664
1665         /* Negotiated Link width */
1666         pcie_capability_read_word(ha->pdev, PCI_EXP_LNKSTA, &lnk);
1667         ha->link_width = (lnk >> 4) & 0x3f;
1668
1669         /* Synchronize with Receive peg */
1670         return qla4_82xx_rcvpeg_ready(ha);
1671 }
1672
1673 int qla4_82xx_try_start_fw(struct scsi_qla_host *ha)
1674 {
1675         int rval = QLA_ERROR;
1676
1677         /*
1678          * FW Load priority:
1679          * 1) Operational firmware residing in flash.
1680          * 2) Fail
1681          */
1682
1683         ql4_printk(KERN_INFO, ha,
1684             "FW: Retrieving flash offsets from FLT/FDT ...\n");
1685         rval = qla4_8xxx_get_flash_info(ha);
1686         if (rval != QLA_SUCCESS)
1687                 return rval;
1688
1689         ql4_printk(KERN_INFO, ha,
1690             "FW: Attempting to load firmware from flash...\n");
1691         rval = qla4_82xx_start_firmware(ha, ha->hw.flt_region_fw);
1692
1693         if (rval != QLA_SUCCESS) {
1694                 ql4_printk(KERN_ERR, ha, "FW: Load firmware from flash"
1695                     " FAILED...\n");
1696                 return rval;
1697         }
1698
1699         return rval;
1700 }
1701
1702 void qla4_82xx_rom_lock_recovery(struct scsi_qla_host *ha)
1703 {
1704         if (qla4_82xx_rom_lock(ha)) {
1705                 /* Someone else is holding the lock. */
1706                 dev_info(&ha->pdev->dev, "Resetting rom_lock\n");
1707         }
1708
1709         /*
1710          * Either we got the lock, or someone
1711          * else died while holding it.
1712          * In either case, unlock.
1713          */
1714         qla4_82xx_rom_unlock(ha);
1715 }
1716
1717 static void qla4_8xxx_minidump_process_rdcrb(struct scsi_qla_host *ha,
1718                                 struct qla8xxx_minidump_entry_hdr *entry_hdr,
1719                                 uint32_t **d_ptr)
1720 {
1721         uint32_t r_addr, r_stride, loop_cnt, i, r_value;
1722         struct qla8xxx_minidump_entry_crb *crb_hdr;
1723         uint32_t *data_ptr = *d_ptr;
1724
1725         DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
1726         crb_hdr = (struct qla8xxx_minidump_entry_crb *)entry_hdr;
1727         r_addr = crb_hdr->addr;
1728         r_stride = crb_hdr->crb_strd.addr_stride;
1729         loop_cnt = crb_hdr->op_count;
1730
1731         for (i = 0; i < loop_cnt; i++) {
1732                 ha->isp_ops->rd_reg_indirect(ha, r_addr, &r_value);
1733                 *data_ptr++ = cpu_to_le32(r_addr);
1734                 *data_ptr++ = cpu_to_le32(r_value);
1735                 r_addr += r_stride;
1736         }
1737         *d_ptr = data_ptr;
1738 }
1739
1740 static int qla4_8xxx_minidump_process_l2tag(struct scsi_qla_host *ha,
1741                                  struct qla8xxx_minidump_entry_hdr *entry_hdr,
1742                                  uint32_t **d_ptr)
1743 {
1744         uint32_t addr, r_addr, c_addr, t_r_addr;
1745         uint32_t i, k, loop_count, t_value, r_cnt, r_value;
1746         unsigned long p_wait, w_time, p_mask;
1747         uint32_t c_value_w, c_value_r;
1748         struct qla8xxx_minidump_entry_cache *cache_hdr;
1749         int rval = QLA_ERROR;
1750         uint32_t *data_ptr = *d_ptr;
1751
1752         DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
1753         cache_hdr = (struct qla8xxx_minidump_entry_cache *)entry_hdr;
1754
1755         loop_count = cache_hdr->op_count;
1756         r_addr = cache_hdr->read_addr;
1757         c_addr = cache_hdr->control_addr;
1758         c_value_w = cache_hdr->cache_ctrl.write_value;
1759
1760         t_r_addr = cache_hdr->tag_reg_addr;
1761         t_value = cache_hdr->addr_ctrl.init_tag_value;
1762         r_cnt = cache_hdr->read_ctrl.read_addr_cnt;
1763         p_wait = cache_hdr->cache_ctrl.poll_wait;
1764         p_mask = cache_hdr->cache_ctrl.poll_mask;
1765
1766         for (i = 0; i < loop_count; i++) {
1767                 ha->isp_ops->wr_reg_indirect(ha, t_r_addr, t_value);
1768
1769                 if (c_value_w)
1770                         ha->isp_ops->wr_reg_indirect(ha, c_addr, c_value_w);
1771
1772                 if (p_mask) {
1773                         w_time = jiffies + p_wait;
1774                         do {
1775                                 ha->isp_ops->rd_reg_indirect(ha, c_addr,
1776                                                              &c_value_r);
1777                                 if ((c_value_r & p_mask) == 0) {
1778                                         break;
1779                                 } else if (time_after_eq(jiffies, w_time)) {
1780                                         /* capturing dump failed */
1781                                         return rval;
1782                                 }
1783                         } while (1);
1784                 }
1785
1786                 addr = r_addr;
1787                 for (k = 0; k < r_cnt; k++) {
1788                         ha->isp_ops->rd_reg_indirect(ha, addr, &r_value);
1789                         *data_ptr++ = cpu_to_le32(r_value);
1790                         addr += cache_hdr->read_ctrl.read_addr_stride;
1791                 }
1792
1793                 t_value += cache_hdr->addr_ctrl.tag_value_stride;
1794         }
1795         *d_ptr = data_ptr;
1796         return QLA_SUCCESS;
1797 }
1798
1799 static int qla4_8xxx_minidump_process_control(struct scsi_qla_host *ha,
1800                                 struct qla8xxx_minidump_entry_hdr *entry_hdr)
1801 {
1802         struct qla8xxx_minidump_entry_crb *crb_entry;
1803         uint32_t read_value, opcode, poll_time, addr, index, rval = QLA_SUCCESS;
1804         uint32_t crb_addr;
1805         unsigned long wtime;
1806         struct qla4_8xxx_minidump_template_hdr *tmplt_hdr;
1807         int i;
1808
1809         DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
1810         tmplt_hdr = (struct qla4_8xxx_minidump_template_hdr *)
1811                                                 ha->fw_dump_tmplt_hdr;
1812         crb_entry = (struct qla8xxx_minidump_entry_crb *)entry_hdr;
1813
1814         crb_addr = crb_entry->addr;
1815         for (i = 0; i < crb_entry->op_count; i++) {
1816                 opcode = crb_entry->crb_ctrl.opcode;
1817                 if (opcode & QLA8XXX_DBG_OPCODE_WR) {
1818                         ha->isp_ops->wr_reg_indirect(ha, crb_addr,
1819                                                      crb_entry->value_1);
1820                         opcode &= ~QLA8XXX_DBG_OPCODE_WR;
1821                 }
1822                 if (opcode & QLA8XXX_DBG_OPCODE_RW) {
1823                         ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value);
1824                         ha->isp_ops->wr_reg_indirect(ha, crb_addr, read_value);
1825                         opcode &= ~QLA8XXX_DBG_OPCODE_RW;
1826                 }
1827                 if (opcode & QLA8XXX_DBG_OPCODE_AND) {
1828                         ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value);
1829                         read_value &= crb_entry->value_2;
1830                         opcode &= ~QLA8XXX_DBG_OPCODE_AND;
1831                         if (opcode & QLA8XXX_DBG_OPCODE_OR) {
1832                                 read_value |= crb_entry->value_3;
1833                                 opcode &= ~QLA8XXX_DBG_OPCODE_OR;
1834                         }
1835                         ha->isp_ops->wr_reg_indirect(ha, crb_addr, read_value);
1836                 }
1837                 if (opcode & QLA8XXX_DBG_OPCODE_OR) {
1838                         ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value);
1839                         read_value |= crb_entry->value_3;
1840                         ha->isp_ops->wr_reg_indirect(ha, crb_addr, read_value);
1841                         opcode &= ~QLA8XXX_DBG_OPCODE_OR;
1842                 }
1843                 if (opcode & QLA8XXX_DBG_OPCODE_POLL) {
1844                         poll_time = crb_entry->crb_strd.poll_timeout;
1845                         wtime = jiffies + poll_time;
1846                         ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value);
1847
1848                         do {
1849                                 if ((read_value & crb_entry->value_2) ==
1850                                     crb_entry->value_1) {
1851                                         break;
1852                                 } else if (time_after_eq(jiffies, wtime)) {
1853                                         /* capturing dump failed */
1854                                         rval = QLA_ERROR;
1855                                         break;
1856                                 } else {
1857                                         ha->isp_ops->rd_reg_indirect(ha,
1858                                                         crb_addr, &read_value);
1859                                 }
1860                         } while (1);
1861                         opcode &= ~QLA8XXX_DBG_OPCODE_POLL;
1862                 }
1863
1864                 if (opcode & QLA8XXX_DBG_OPCODE_RDSTATE) {
1865                         if (crb_entry->crb_strd.state_index_a) {
1866                                 index = crb_entry->crb_strd.state_index_a;
1867                                 addr = tmplt_hdr->saved_state_array[index];
1868                         } else {
1869                                 addr = crb_addr;
1870                         }
1871
1872                         ha->isp_ops->rd_reg_indirect(ha, addr, &read_value);
1873                         index = crb_entry->crb_ctrl.state_index_v;
1874                         tmplt_hdr->saved_state_array[index] = read_value;
1875                         opcode &= ~QLA8XXX_DBG_OPCODE_RDSTATE;
1876                 }
1877
1878                 if (opcode & QLA8XXX_DBG_OPCODE_WRSTATE) {
1879                         if (crb_entry->crb_strd.state_index_a) {
1880                                 index = crb_entry->crb_strd.state_index_a;
1881                                 addr = tmplt_hdr->saved_state_array[index];
1882                         } else {
1883                                 addr = crb_addr;
1884                         }
1885
1886                         if (crb_entry->crb_ctrl.state_index_v) {
1887                                 index = crb_entry->crb_ctrl.state_index_v;
1888                                 read_value =
1889                                         tmplt_hdr->saved_state_array[index];
1890                         } else {
1891                                 read_value = crb_entry->value_1;
1892                         }
1893
1894                         ha->isp_ops->wr_reg_indirect(ha, addr, read_value);
1895                         opcode &= ~QLA8XXX_DBG_OPCODE_WRSTATE;
1896                 }
1897
1898                 if (opcode & QLA8XXX_DBG_OPCODE_MDSTATE) {
1899                         index = crb_entry->crb_ctrl.state_index_v;
1900                         read_value = tmplt_hdr->saved_state_array[index];
1901                         read_value <<= crb_entry->crb_ctrl.shl;
1902                         read_value >>= crb_entry->crb_ctrl.shr;
1903                         if (crb_entry->value_2)
1904                                 read_value &= crb_entry->value_2;
1905                         read_value |= crb_entry->value_3;
1906                         read_value += crb_entry->value_1;
1907                         tmplt_hdr->saved_state_array[index] = read_value;
1908                         opcode &= ~QLA8XXX_DBG_OPCODE_MDSTATE;
1909                 }
1910                 crb_addr += crb_entry->crb_strd.addr_stride;
1911         }
1912         DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s\n", __func__));
1913         return rval;
1914 }
1915
1916 static void qla4_8xxx_minidump_process_rdocm(struct scsi_qla_host *ha,
1917                                 struct qla8xxx_minidump_entry_hdr *entry_hdr,
1918                                 uint32_t **d_ptr)
1919 {
1920         uint32_t r_addr, r_stride, loop_cnt, i, r_value;
1921         struct qla8xxx_minidump_entry_rdocm *ocm_hdr;
1922         uint32_t *data_ptr = *d_ptr;
1923
1924         DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
1925         ocm_hdr = (struct qla8xxx_minidump_entry_rdocm *)entry_hdr;
1926         r_addr = ocm_hdr->read_addr;
1927         r_stride = ocm_hdr->read_addr_stride;
1928         loop_cnt = ocm_hdr->op_count;
1929
1930         DEBUG2(ql4_printk(KERN_INFO, ha,
1931                           "[%s]: r_addr: 0x%x, r_stride: 0x%x, loop_cnt: 0x%x\n",
1932                           __func__, r_addr, r_stride, loop_cnt));
1933
1934         for (i = 0; i < loop_cnt; i++) {
1935                 r_value = readl((void __iomem *)(r_addr + ha->nx_pcibase));
1936                 *data_ptr++ = cpu_to_le32(r_value);
1937                 r_addr += r_stride;
1938         }
1939         DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s datacount: 0x%lx\n",
1940                 __func__, (long unsigned int) (loop_cnt * sizeof(uint32_t))));
1941         *d_ptr = data_ptr;
1942 }
1943
1944 static void qla4_8xxx_minidump_process_rdmux(struct scsi_qla_host *ha,
1945                                 struct qla8xxx_minidump_entry_hdr *entry_hdr,
1946                                 uint32_t **d_ptr)
1947 {
1948         uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value;
1949         struct qla8xxx_minidump_entry_mux *mux_hdr;
1950         uint32_t *data_ptr = *d_ptr;
1951
1952         DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
1953         mux_hdr = (struct qla8xxx_minidump_entry_mux *)entry_hdr;
1954         r_addr = mux_hdr->read_addr;
1955         s_addr = mux_hdr->select_addr;
1956         s_stride = mux_hdr->select_value_stride;
1957         s_value = mux_hdr->select_value;
1958         loop_cnt = mux_hdr->op_count;
1959
1960         for (i = 0; i < loop_cnt; i++) {
1961                 ha->isp_ops->wr_reg_indirect(ha, s_addr, s_value);
1962                 ha->isp_ops->rd_reg_indirect(ha, r_addr, &r_value);
1963                 *data_ptr++ = cpu_to_le32(s_value);
1964                 *data_ptr++ = cpu_to_le32(r_value);
1965                 s_value += s_stride;
1966         }
1967         *d_ptr = data_ptr;
1968 }
1969
1970 static void qla4_8xxx_minidump_process_l1cache(struct scsi_qla_host *ha,
1971                                 struct qla8xxx_minidump_entry_hdr *entry_hdr,
1972                                 uint32_t **d_ptr)
1973 {
1974         uint32_t addr, r_addr, c_addr, t_r_addr;
1975         uint32_t i, k, loop_count, t_value, r_cnt, r_value;
1976         uint32_t c_value_w;
1977         struct qla8xxx_minidump_entry_cache *cache_hdr;
1978         uint32_t *data_ptr = *d_ptr;
1979
1980         cache_hdr = (struct qla8xxx_minidump_entry_cache *)entry_hdr;
1981         loop_count = cache_hdr->op_count;
1982         r_addr = cache_hdr->read_addr;
1983         c_addr = cache_hdr->control_addr;
1984         c_value_w = cache_hdr->cache_ctrl.write_value;
1985
1986         t_r_addr = cache_hdr->tag_reg_addr;
1987         t_value = cache_hdr->addr_ctrl.init_tag_value;
1988         r_cnt = cache_hdr->read_ctrl.read_addr_cnt;
1989
1990         for (i = 0; i < loop_count; i++) {
1991                 ha->isp_ops->wr_reg_indirect(ha, t_r_addr, t_value);
1992                 ha->isp_ops->wr_reg_indirect(ha, c_addr, c_value_w);
1993                 addr = r_addr;
1994                 for (k = 0; k < r_cnt; k++) {
1995                         ha->isp_ops->rd_reg_indirect(ha, addr, &r_value);
1996                         *data_ptr++ = cpu_to_le32(r_value);
1997                         addr += cache_hdr->read_ctrl.read_addr_stride;
1998                 }
1999                 t_value += cache_hdr->addr_ctrl.tag_value_stride;
2000         }
2001         *d_ptr = data_ptr;
2002 }
2003
2004 static void qla4_8xxx_minidump_process_queue(struct scsi_qla_host *ha,
2005                                 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2006                                 uint32_t **d_ptr)
2007 {
2008         uint32_t s_addr, r_addr;
2009         uint32_t r_stride, r_value, r_cnt, qid = 0;
2010         uint32_t i, k, loop_cnt;
2011         struct qla8xxx_minidump_entry_queue *q_hdr;
2012         uint32_t *data_ptr = *d_ptr;
2013
2014         DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
2015         q_hdr = (struct qla8xxx_minidump_entry_queue *)entry_hdr;
2016         s_addr = q_hdr->select_addr;
2017         r_cnt = q_hdr->rd_strd.read_addr_cnt;
2018         r_stride = q_hdr->rd_strd.read_addr_stride;
2019         loop_cnt = q_hdr->op_count;
2020
2021         for (i = 0; i < loop_cnt; i++) {
2022                 ha->isp_ops->wr_reg_indirect(ha, s_addr, qid);
2023                 r_addr = q_hdr->read_addr;
2024                 for (k = 0; k < r_cnt; k++) {
2025                         ha->isp_ops->rd_reg_indirect(ha, r_addr, &r_value);
2026                         *data_ptr++ = cpu_to_le32(r_value);
2027                         r_addr += r_stride;
2028                 }
2029                 qid += q_hdr->q_strd.queue_id_stride;
2030         }
2031         *d_ptr = data_ptr;
2032 }
2033
2034 #define MD_DIRECT_ROM_WINDOW            0x42110030
2035 #define MD_DIRECT_ROM_READ_BASE         0x42150000
2036
2037 static void qla4_82xx_minidump_process_rdrom(struct scsi_qla_host *ha,
2038                                 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2039                                 uint32_t **d_ptr)
2040 {
2041         uint32_t r_addr, r_value;
2042         uint32_t i, loop_cnt;
2043         struct qla8xxx_minidump_entry_rdrom *rom_hdr;
2044         uint32_t *data_ptr = *d_ptr;
2045
2046         DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
2047         rom_hdr = (struct qla8xxx_minidump_entry_rdrom *)entry_hdr;
2048         r_addr = rom_hdr->read_addr;
2049         loop_cnt = rom_hdr->read_data_size/sizeof(uint32_t);
2050
2051         DEBUG2(ql4_printk(KERN_INFO, ha,
2052                           "[%s]: flash_addr: 0x%x, read_data_size: 0x%x\n",
2053                            __func__, r_addr, loop_cnt));
2054
2055         for (i = 0; i < loop_cnt; i++) {
2056                 ha->isp_ops->wr_reg_indirect(ha, MD_DIRECT_ROM_WINDOW,
2057                                              (r_addr & 0xFFFF0000));
2058                 ha->isp_ops->rd_reg_indirect(ha,
2059                                 MD_DIRECT_ROM_READ_BASE + (r_addr & 0x0000FFFF),
2060                                 &r_value);
2061                 *data_ptr++ = cpu_to_le32(r_value);
2062                 r_addr += sizeof(uint32_t);
2063         }
2064         *d_ptr = data_ptr;
2065 }
2066
2067 #define MD_MIU_TEST_AGT_CTRL            0x41000090
2068 #define MD_MIU_TEST_AGT_ADDR_LO         0x41000094
2069 #define MD_MIU_TEST_AGT_ADDR_HI         0x41000098
2070
2071 static int qla4_8xxx_minidump_process_rdmem(struct scsi_qla_host *ha,
2072                                 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2073                                 uint32_t **d_ptr)
2074 {
2075         uint32_t r_addr, r_value, r_data;
2076         uint32_t i, j, loop_cnt;
2077         struct qla8xxx_minidump_entry_rdmem *m_hdr;
2078         unsigned long flags;
2079         uint32_t *data_ptr = *d_ptr;
2080
2081         DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
2082         m_hdr = (struct qla8xxx_minidump_entry_rdmem *)entry_hdr;
2083         r_addr = m_hdr->read_addr;
2084         loop_cnt = m_hdr->read_data_size/16;
2085
2086         DEBUG2(ql4_printk(KERN_INFO, ha,
2087                           "[%s]: Read addr: 0x%x, read_data_size: 0x%x\n",
2088                           __func__, r_addr, m_hdr->read_data_size));
2089
2090         if (r_addr & 0xf) {
2091                 DEBUG2(ql4_printk(KERN_INFO, ha,
2092                                   "[%s]: Read addr 0x%x not 16 bytes aligned\n",
2093                                   __func__, r_addr));
2094                 return QLA_ERROR;
2095         }
2096
2097         if (m_hdr->read_data_size % 16) {
2098                 DEBUG2(ql4_printk(KERN_INFO, ha,
2099                                   "[%s]: Read data[0x%x] not multiple of 16 bytes\n",
2100                                   __func__, m_hdr->read_data_size));
2101                 return QLA_ERROR;
2102         }
2103
2104         DEBUG2(ql4_printk(KERN_INFO, ha,
2105                           "[%s]: rdmem_addr: 0x%x, read_data_size: 0x%x, loop_cnt: 0x%x\n",
2106                           __func__, r_addr, m_hdr->read_data_size, loop_cnt));
2107
2108         write_lock_irqsave(&ha->hw_lock, flags);
2109         for (i = 0; i < loop_cnt; i++) {
2110                 ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_ADDR_LO,
2111                                              r_addr);
2112                 r_value = 0;
2113                 ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_ADDR_HI,
2114                                              r_value);
2115                 r_value = MIU_TA_CTL_ENABLE;
2116                 ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_CTRL, r_value);
2117                 r_value = MIU_TA_CTL_START_ENABLE;
2118                 ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_CTRL, r_value);
2119
2120                 for (j = 0; j < MAX_CTL_CHECK; j++) {
2121                         ha->isp_ops->rd_reg_indirect(ha, MD_MIU_TEST_AGT_CTRL,
2122                                                      &r_value);
2123                         if ((r_value & MIU_TA_CTL_BUSY) == 0)
2124                                 break;
2125                 }
2126
2127                 if (j >= MAX_CTL_CHECK) {
2128                         printk_ratelimited(KERN_ERR
2129                                            "%s: failed to read through agent\n",
2130                                             __func__);
2131                         write_unlock_irqrestore(&ha->hw_lock, flags);
2132                         return QLA_SUCCESS;
2133                 }
2134
2135                 for (j = 0; j < 4; j++) {
2136                         ha->isp_ops->rd_reg_indirect(ha,
2137                                                      MD_MIU_TEST_AGT_RDDATA[j],
2138                                                      &r_data);
2139                         *data_ptr++ = cpu_to_le32(r_data);
2140                 }
2141
2142                 r_addr += 16;
2143         }
2144         write_unlock_irqrestore(&ha->hw_lock, flags);
2145
2146         DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s datacount: 0x%x\n",
2147                           __func__, (loop_cnt * 16)));
2148
2149         *d_ptr = data_ptr;
2150         return QLA_SUCCESS;
2151 }
2152
2153 static void qla4_8xxx_mark_entry_skipped(struct scsi_qla_host *ha,
2154                                 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2155                                 int index)
2156 {
2157         entry_hdr->d_ctrl.driver_flags |= QLA8XXX_DBG_SKIPPED_FLAG;
2158         DEBUG2(ql4_printk(KERN_INFO, ha,
2159                           "scsi(%ld): Skipping entry[%d]: ETYPE[0x%x]-ELEVEL[0x%x]\n",
2160                           ha->host_no, index, entry_hdr->entry_type,
2161                           entry_hdr->d_ctrl.entry_capture_mask));
2162 }
2163
2164 /* ISP83xx functions to process new minidump entries... */
2165 static uint32_t qla83xx_minidump_process_pollrd(struct scsi_qla_host *ha,
2166                                 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2167                                 uint32_t **d_ptr)
2168 {
2169         uint32_t r_addr, s_addr, s_value, r_value, poll_wait, poll_mask;
2170         uint16_t s_stride, i;
2171         uint32_t *data_ptr = *d_ptr;
2172         uint32_t rval = QLA_SUCCESS;
2173         struct qla83xx_minidump_entry_pollrd *pollrd_hdr;
2174
2175         pollrd_hdr = (struct qla83xx_minidump_entry_pollrd *)entry_hdr;
2176         s_addr = le32_to_cpu(pollrd_hdr->select_addr);
2177         r_addr = le32_to_cpu(pollrd_hdr->read_addr);
2178         s_value = le32_to_cpu(pollrd_hdr->select_value);
2179         s_stride = le32_to_cpu(pollrd_hdr->select_value_stride);
2180
2181         poll_wait = le32_to_cpu(pollrd_hdr->poll_wait);
2182         poll_mask = le32_to_cpu(pollrd_hdr->poll_mask);
2183
2184         for (i = 0; i < le32_to_cpu(pollrd_hdr->op_count); i++) {
2185                 ha->isp_ops->wr_reg_indirect(ha, s_addr, s_value);
2186                 poll_wait = le32_to_cpu(pollrd_hdr->poll_wait);
2187                 while (1) {
2188                         ha->isp_ops->rd_reg_indirect(ha, s_addr, &r_value);
2189
2190                         if ((r_value & poll_mask) != 0) {
2191                                 break;
2192                         } else {
2193                                 msleep(1);
2194                                 if (--poll_wait == 0) {
2195                                         ql4_printk(KERN_ERR, ha, "%s: TIMEOUT\n",
2196                                                    __func__);
2197                                         rval = QLA_ERROR;
2198                                         goto exit_process_pollrd;
2199                                 }
2200                         }
2201                 }
2202                 ha->isp_ops->rd_reg_indirect(ha, r_addr, &r_value);
2203                 *data_ptr++ = cpu_to_le32(s_value);
2204                 *data_ptr++ = cpu_to_le32(r_value);
2205                 s_value += s_stride;
2206         }
2207
2208         *d_ptr = data_ptr;
2209
2210 exit_process_pollrd:
2211         return rval;
2212 }
2213
2214 static void qla83xx_minidump_process_rdmux2(struct scsi_qla_host *ha,
2215                                 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2216                                 uint32_t **d_ptr)
2217 {
2218         uint32_t sel_val1, sel_val2, t_sel_val, data, i;
2219         uint32_t sel_addr1, sel_addr2, sel_val_mask, read_addr;
2220         struct qla83xx_minidump_entry_rdmux2 *rdmux2_hdr;
2221         uint32_t *data_ptr = *d_ptr;
2222
2223         rdmux2_hdr = (struct qla83xx_minidump_entry_rdmux2 *)entry_hdr;
2224         sel_val1 = le32_to_cpu(rdmux2_hdr->select_value_1);
2225         sel_val2 = le32_to_cpu(rdmux2_hdr->select_value_2);
2226         sel_addr1 = le32_to_cpu(rdmux2_hdr->select_addr_1);
2227         sel_addr2 = le32_to_cpu(rdmux2_hdr->select_addr_2);
2228         sel_val_mask = le32_to_cpu(rdmux2_hdr->select_value_mask);
2229         read_addr = le32_to_cpu(rdmux2_hdr->read_addr);
2230
2231         for (i = 0; i < rdmux2_hdr->op_count; i++) {
2232                 ha->isp_ops->wr_reg_indirect(ha, sel_addr1, sel_val1);
2233                 t_sel_val = sel_val1 & sel_val_mask;
2234                 *data_ptr++ = cpu_to_le32(t_sel_val);
2235
2236                 ha->isp_ops->wr_reg_indirect(ha, sel_addr2, t_sel_val);
2237                 ha->isp_ops->rd_reg_indirect(ha, read_addr, &data);
2238
2239                 *data_ptr++ = cpu_to_le32(data);
2240
2241                 ha->isp_ops->wr_reg_indirect(ha, sel_addr1, sel_val2);
2242                 t_sel_val = sel_val2 & sel_val_mask;
2243                 *data_ptr++ = cpu_to_le32(t_sel_val);
2244
2245                 ha->isp_ops->wr_reg_indirect(ha, sel_addr2, t_sel_val);
2246                 ha->isp_ops->rd_reg_indirect(ha, read_addr, &data);
2247
2248                 *data_ptr++ = cpu_to_le32(data);
2249
2250                 sel_val1 += rdmux2_hdr->select_value_stride;
2251                 sel_val2 += rdmux2_hdr->select_value_stride;
2252         }
2253
2254         *d_ptr = data_ptr;
2255 }
2256
2257 static uint32_t qla83xx_minidump_process_pollrdmwr(struct scsi_qla_host *ha,
2258                                 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2259                                 uint32_t **d_ptr)
2260 {
2261         uint32_t poll_wait, poll_mask, r_value, data;
2262         uint32_t addr_1, addr_2, value_1, value_2;
2263         uint32_t *data_ptr = *d_ptr;
2264         uint32_t rval = QLA_SUCCESS;
2265         struct qla83xx_minidump_entry_pollrdmwr *poll_hdr;
2266
2267         poll_hdr = (struct qla83xx_minidump_entry_pollrdmwr *)entry_hdr;
2268         addr_1 = le32_to_cpu(poll_hdr->addr_1);
2269         addr_2 = le32_to_cpu(poll_hdr->addr_2);
2270         value_1 = le32_to_cpu(poll_hdr->value_1);
2271         value_2 = le32_to_cpu(poll_hdr->value_2);
2272         poll_mask = le32_to_cpu(poll_hdr->poll_mask);
2273
2274         ha->isp_ops->wr_reg_indirect(ha, addr_1, value_1);
2275
2276         poll_wait = le32_to_cpu(poll_hdr->poll_wait);
2277         while (1) {
2278                 ha->isp_ops->rd_reg_indirect(ha, addr_1, &r_value);
2279
2280                 if ((r_value & poll_mask) != 0) {
2281                         break;
2282                 } else {
2283                         msleep(1);
2284                         if (--poll_wait == 0) {
2285                                 ql4_printk(KERN_ERR, ha, "%s: TIMEOUT_1\n",
2286                                            __func__);
2287                                 rval = QLA_ERROR;
2288                                 goto exit_process_pollrdmwr;
2289                         }
2290                 }
2291         }
2292
2293         ha->isp_ops->rd_reg_indirect(ha, addr_2, &data);
2294         data &= le32_to_cpu(poll_hdr->modify_mask);
2295         ha->isp_ops->wr_reg_indirect(ha, addr_2, data);
2296         ha->isp_ops->wr_reg_indirect(ha, addr_1, value_2);
2297
2298         poll_wait = le32_to_cpu(poll_hdr->poll_wait);
2299         while (1) {
2300                 ha->isp_ops->rd_reg_indirect(ha, addr_1, &r_value);
2301
2302                 if ((r_value & poll_mask) != 0) {
2303                         break;
2304                 } else {
2305                         msleep(1);
2306                         if (--poll_wait == 0) {
2307                                 ql4_printk(KERN_ERR, ha, "%s: TIMEOUT_2\n",
2308                                            __func__);
2309                                 rval = QLA_ERROR;
2310                                 goto exit_process_pollrdmwr;
2311                         }
2312                 }
2313         }
2314
2315         *data_ptr++ = cpu_to_le32(addr_2);
2316         *data_ptr++ = cpu_to_le32(data);
2317         *d_ptr = data_ptr;
2318
2319 exit_process_pollrdmwr:
2320         return rval;
2321 }
2322
2323 static uint32_t qla4_83xx_minidump_process_rdrom(struct scsi_qla_host *ha,
2324                                 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2325                                 uint32_t **d_ptr)
2326 {
2327         uint32_t fl_addr, u32_count, rval;
2328         struct qla8xxx_minidump_entry_rdrom *rom_hdr;
2329         uint32_t *data_ptr = *d_ptr;
2330
2331         rom_hdr = (struct qla8xxx_minidump_entry_rdrom *)entry_hdr;
2332         fl_addr = le32_to_cpu(rom_hdr->read_addr);
2333         u32_count = le32_to_cpu(rom_hdr->read_data_size)/sizeof(uint32_t);
2334
2335         DEBUG2(ql4_printk(KERN_INFO, ha, "[%s]: fl_addr: 0x%x, count: 0x%x\n",
2336                           __func__, fl_addr, u32_count));
2337
2338         rval = qla4_83xx_lockless_flash_read_u32(ha, fl_addr,
2339                                                  (u8 *)(data_ptr), u32_count);
2340
2341         if (rval == QLA_ERROR) {
2342                 ql4_printk(KERN_ERR, ha, "%s: Flash Read Error,Count=%d\n",
2343                            __func__, u32_count);
2344                 goto exit_process_rdrom;
2345         }
2346
2347         data_ptr += u32_count;
2348         *d_ptr = data_ptr;
2349
2350 exit_process_rdrom:
2351         return rval;
2352 }
2353
2354 /**
2355  * qla4_8xxx_collect_md_data - Retrieve firmware minidump data.
2356  * @ha: pointer to adapter structure
2357  **/
2358 static int qla4_8xxx_collect_md_data(struct scsi_qla_host *ha)
2359 {
2360         int num_entry_hdr = 0;
2361         struct qla8xxx_minidump_entry_hdr *entry_hdr;
2362         struct qla4_8xxx_minidump_template_hdr *tmplt_hdr;
2363         uint32_t *data_ptr;
2364         uint32_t data_collected = 0;
2365         int i, rval = QLA_ERROR;
2366         uint64_t now;
2367         uint32_t timestamp;
2368
2369         if (!ha->fw_dump) {
2370                 ql4_printk(KERN_INFO, ha, "%s(%ld) No buffer to dump\n",
2371                            __func__, ha->host_no);
2372                 return rval;
2373         }
2374
2375         tmplt_hdr = (struct qla4_8xxx_minidump_template_hdr *)
2376                                                 ha->fw_dump_tmplt_hdr;
2377         data_ptr = (uint32_t *)((uint8_t *)ha->fw_dump +
2378                                                 ha->fw_dump_tmplt_size);
2379         data_collected += ha->fw_dump_tmplt_size;
2380
2381         num_entry_hdr = tmplt_hdr->num_of_entries;
2382         ql4_printk(KERN_INFO, ha, "[%s]: starting data ptr: %p\n",
2383                    __func__, data_ptr);
2384         ql4_printk(KERN_INFO, ha,
2385                    "[%s]: no of entry headers in Template: 0x%x\n",
2386                    __func__, num_entry_hdr);
2387         ql4_printk(KERN_INFO, ha, "[%s]: Capture Mask obtained: 0x%x\n",
2388                    __func__, ha->fw_dump_capture_mask);
2389         ql4_printk(KERN_INFO, ha, "[%s]: Total_data_size 0x%x, %d obtained\n",
2390                    __func__, ha->fw_dump_size, ha->fw_dump_size);
2391
2392         /* Update current timestamp before taking dump */
2393         now = get_jiffies_64();
2394         timestamp = (u32)(jiffies_to_msecs(now) / 1000);
2395         tmplt_hdr->driver_timestamp = timestamp;
2396
2397         entry_hdr = (struct qla8xxx_minidump_entry_hdr *)
2398                                         (((uint8_t *)ha->fw_dump_tmplt_hdr) +
2399                                          tmplt_hdr->first_entry_offset);
2400
2401         if (is_qla8032(ha))
2402                 tmplt_hdr->saved_state_array[QLA83XX_SS_OCM_WNDREG_INDEX] =
2403                                         tmplt_hdr->ocm_window_reg[ha->func_num];
2404
2405         /* Walk through the entry headers - validate/perform required action */
2406         for (i = 0; i < num_entry_hdr; i++) {
2407                 if (data_collected >= ha->fw_dump_size) {
2408                         ql4_printk(KERN_INFO, ha,
2409                                    "Data collected: [0x%x], Total Dump size: [0x%x]\n",
2410                                    data_collected, ha->fw_dump_size);
2411                         return rval;
2412                 }
2413
2414                 if (!(entry_hdr->d_ctrl.entry_capture_mask &
2415                       ha->fw_dump_capture_mask)) {
2416                         entry_hdr->d_ctrl.driver_flags |=
2417                                                 QLA8XXX_DBG_SKIPPED_FLAG;
2418                         goto skip_nxt_entry;
2419                 }
2420
2421                 DEBUG2(ql4_printk(KERN_INFO, ha,
2422                                   "Data collected: [0x%x], Dump size left:[0x%x]\n",
2423                                   data_collected,
2424                                   (ha->fw_dump_size - data_collected)));
2425
2426                 /* Decode the entry type and take required action to capture
2427                  * debug data
2428                  */
2429                 switch (entry_hdr->entry_type) {
2430                 case QLA8XXX_RDEND:
2431                         qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
2432                         break;
2433                 case QLA8XXX_CNTRL:
2434                         rval = qla4_8xxx_minidump_process_control(ha,
2435                                                                   entry_hdr);
2436                         if (rval != QLA_SUCCESS) {
2437                                 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
2438                                 goto md_failed;
2439                         }
2440                         break;
2441                 case QLA8XXX_RDCRB:
2442                         qla4_8xxx_minidump_process_rdcrb(ha, entry_hdr,
2443                                                          &data_ptr);
2444                         break;
2445                 case QLA8XXX_RDMEM:
2446                         rval = qla4_8xxx_minidump_process_rdmem(ha, entry_hdr,
2447                                                                 &data_ptr);
2448                         if (rval != QLA_SUCCESS) {
2449                                 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
2450                                 goto md_failed;
2451                         }
2452                         break;
2453                 case QLA8XXX_BOARD:
2454                 case QLA8XXX_RDROM:
2455                         if (is_qla8022(ha)) {
2456                                 qla4_82xx_minidump_process_rdrom(ha, entry_hdr,
2457                                                                  &data_ptr);
2458                         } else if (is_qla8032(ha)) {
2459                                 rval = qla4_83xx_minidump_process_rdrom(ha,
2460                                                                     entry_hdr,
2461                                                                     &data_ptr);
2462                                 if (rval != QLA_SUCCESS)
2463                                         qla4_8xxx_mark_entry_skipped(ha,
2464                                                                      entry_hdr,
2465                                                                      i);
2466                         }
2467                         break;
2468                 case QLA8XXX_L2DTG:
2469                 case QLA8XXX_L2ITG:
2470                 case QLA8XXX_L2DAT:
2471                 case QLA8XXX_L2INS:
2472                         rval = qla4_8xxx_minidump_process_l2tag(ha, entry_hdr,
2473                                                                 &data_ptr);
2474                         if (rval != QLA_SUCCESS) {
2475                                 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
2476                                 goto md_failed;
2477                         }
2478                         break;
2479                 case QLA8XXX_L1DTG:
2480                 case QLA8XXX_L1ITG:
2481                 case QLA8XXX_L1DAT:
2482                 case QLA8XXX_L1INS:
2483                         qla4_8xxx_minidump_process_l1cache(ha, entry_hdr,
2484                                                            &data_ptr);
2485                         break;
2486                 case QLA8XXX_RDOCM:
2487                         qla4_8xxx_minidump_process_rdocm(ha, entry_hdr,
2488                                                          &data_ptr);
2489                         break;
2490                 case QLA8XXX_RDMUX:
2491                         qla4_8xxx_minidump_process_rdmux(ha, entry_hdr,
2492                                                          &data_ptr);
2493                         break;
2494                 case QLA8XXX_QUEUE:
2495                         qla4_8xxx_minidump_process_queue(ha, entry_hdr,
2496                                                          &data_ptr);
2497                         break;
2498                 case QLA83XX_POLLRD:
2499                         if (!is_qla8032(ha)) {
2500                                 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
2501                                 break;
2502                         }
2503                         rval = qla83xx_minidump_process_pollrd(ha, entry_hdr,
2504                                                                &data_ptr);
2505                         if (rval != QLA_SUCCESS)
2506                                 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
2507                         break;
2508                 case QLA83XX_RDMUX2:
2509                         if (!is_qla8032(ha)) {
2510                                 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
2511                                 break;
2512                         }
2513                         qla83xx_minidump_process_rdmux2(ha, entry_hdr,
2514                                                         &data_ptr);
2515                         break;
2516                 case QLA83XX_POLLRDMWR:
2517                         if (!is_qla8032(ha)) {
2518                                 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
2519                                 break;
2520                         }
2521                         rval = qla83xx_minidump_process_pollrdmwr(ha, entry_hdr,
2522                                                                   &data_ptr);
2523                         if (rval != QLA_SUCCESS)
2524                                 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
2525                         break;
2526                 case QLA8XXX_RDNOP:
2527                 default:
2528                         qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
2529                         break;
2530                 }
2531
2532                 data_collected = (uint8_t *)data_ptr -
2533                                  ((uint8_t *)((uint8_t *)ha->fw_dump +
2534                                                 ha->fw_dump_tmplt_size));
2535 skip_nxt_entry:
2536                 /*  next entry in the template */
2537                 entry_hdr = (struct qla8xxx_minidump_entry_hdr *)
2538                                 (((uint8_t *)entry_hdr) +
2539                                  entry_hdr->entry_size);
2540         }
2541
2542         if ((data_collected + ha->fw_dump_tmplt_size) != ha->fw_dump_size) {
2543                 ql4_printk(KERN_INFO, ha,
2544                            "Dump data mismatch: Data collected: [0x%x], total_data_size:[0x%x]\n",
2545                            data_collected, ha->fw_dump_size);
2546                 goto md_failed;
2547         }
2548
2549         DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s Last entry: 0x%x\n",
2550                           __func__, i));
2551 md_failed:
2552         return rval;
2553 }
2554
2555 /**
2556  * qla4_8xxx_uevent_emit - Send uevent when the firmware dump is ready.
2557  * @ha: pointer to adapter structure
2558  **/
2559 static void qla4_8xxx_uevent_emit(struct scsi_qla_host *ha, u32 code)
2560 {
2561         char event_string[40];
2562         char *envp[] = { event_string, NULL };
2563
2564         switch (code) {
2565         case QL4_UEVENT_CODE_FW_DUMP:
2566                 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
2567                          ha->host_no);
2568                 break;
2569         default:
2570                 /*do nothing*/
2571                 break;
2572         }
2573
2574         kobject_uevent_env(&(&ha->pdev->dev)->kobj, KOBJ_CHANGE, envp);
2575 }
2576
2577 void qla4_8xxx_get_minidump(struct scsi_qla_host *ha)
2578 {
2579         if (ql4xenablemd && test_bit(AF_FW_RECOVERY, &ha->flags) &&
2580             !test_bit(AF_82XX_FW_DUMPED, &ha->flags)) {
2581                 if (!qla4_8xxx_collect_md_data(ha)) {
2582                         qla4_8xxx_uevent_emit(ha, QL4_UEVENT_CODE_FW_DUMP);
2583                         set_bit(AF_82XX_FW_DUMPED, &ha->flags);
2584                 } else {
2585                         ql4_printk(KERN_INFO, ha, "%s: Unable to collect minidump\n",
2586                                    __func__);
2587                 }
2588         }
2589 }
2590
2591 /**
2592  * qla4_8xxx_device_bootstrap - Initialize device, set DEV_READY, start fw
2593  * @ha: pointer to adapter structure
2594  *
2595  * Note: IDC lock must be held upon entry
2596  **/
2597 int qla4_8xxx_device_bootstrap(struct scsi_qla_host *ha)
2598 {
2599         int rval = QLA_ERROR;
2600         int i, timeout;
2601         uint32_t old_count, count, idc_ctrl;
2602         int need_reset = 0, peg_stuck = 1;
2603
2604         need_reset = ha->isp_ops->need_reset(ha);
2605         old_count = qla4_8xxx_rd_direct(ha, QLA8XXX_PEG_ALIVE_COUNTER);
2606
2607         for (i = 0; i < 10; i++) {
2608                 timeout = msleep_interruptible(200);
2609                 if (timeout) {
2610                         qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE,
2611                                             QLA8XXX_DEV_FAILED);
2612                         return rval;
2613                 }
2614
2615                 count = qla4_8xxx_rd_direct(ha, QLA8XXX_PEG_ALIVE_COUNTER);
2616                 if (count != old_count)
2617                         peg_stuck = 0;
2618         }
2619
2620         if (need_reset) {
2621                 /* We are trying to perform a recovery here. */
2622                 if (peg_stuck)
2623                         ha->isp_ops->rom_lock_recovery(ha);
2624                 goto dev_initialize;
2625         } else  {
2626                 /* Start of day for this ha context. */
2627                 if (peg_stuck) {
2628                         /* Either we are the first or recovery in progress. */
2629                         ha->isp_ops->rom_lock_recovery(ha);
2630                         goto dev_initialize;
2631                 } else {
2632                         /* Firmware already running. */
2633                         rval = QLA_SUCCESS;
2634                         goto dev_ready;
2635                 }
2636         }
2637
2638 dev_initialize:
2639         /* set to DEV_INITIALIZING */
2640         ql4_printk(KERN_INFO, ha, "HW State: INITIALIZING\n");
2641         qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE,
2642                             QLA8XXX_DEV_INITIALIZING);
2643
2644         /*
2645          * For ISP8324, if IDC_CTRL GRACEFUL_RESET_BIT1 is set, reset it after
2646          * device goes to INIT state.
2647          */
2648         if (is_qla8032(ha)) {
2649                 idc_ctrl = qla4_83xx_rd_reg(ha, QLA83XX_IDC_DRV_CTRL);
2650                 if (idc_ctrl & GRACEFUL_RESET_BIT1) {
2651                         qla4_83xx_wr_reg(ha, QLA83XX_IDC_DRV_CTRL,
2652                                          (idc_ctrl & ~GRACEFUL_RESET_BIT1));
2653                         set_bit(AF_83XX_NO_FW_DUMP, &ha->flags);
2654                 }
2655         }
2656
2657         ha->isp_ops->idc_unlock(ha);
2658
2659         if (is_qla8022(ha))
2660                 qla4_8xxx_get_minidump(ha);
2661
2662         rval = ha->isp_ops->restart_firmware(ha);
2663         ha->isp_ops->idc_lock(ha);
2664
2665         if (rval != QLA_SUCCESS) {
2666                 ql4_printk(KERN_INFO, ha, "HW State: FAILED\n");
2667                 qla4_8xxx_clear_drv_active(ha);
2668                 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE,
2669                                     QLA8XXX_DEV_FAILED);
2670                 return rval;
2671         }
2672
2673 dev_ready:
2674         ql4_printk(KERN_INFO, ha, "HW State: READY\n");
2675         qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE, QLA8XXX_DEV_READY);
2676
2677         return rval;
2678 }
2679
2680 /**
2681  * qla4_82xx_need_reset_handler - Code to start reset sequence
2682  * @ha: pointer to adapter structure
2683  *
2684  * Note: IDC lock must be held upon entry
2685  **/
2686 static void
2687 qla4_82xx_need_reset_handler(struct scsi_qla_host *ha)
2688 {
2689         uint32_t dev_state, drv_state, drv_active;
2690         uint32_t active_mask = 0xFFFFFFFF;
2691         unsigned long reset_timeout;
2692
2693         ql4_printk(KERN_INFO, ha,
2694                 "Performing ISP error recovery\n");
2695
2696         if (test_and_clear_bit(AF_ONLINE, &ha->flags)) {
2697                 qla4_82xx_idc_unlock(ha);
2698                 ha->isp_ops->disable_intrs(ha);
2699                 qla4_82xx_idc_lock(ha);
2700         }
2701
2702         if (!test_bit(AF_8XXX_RST_OWNER, &ha->flags)) {
2703                 DEBUG2(ql4_printk(KERN_INFO, ha,
2704                                   "%s(%ld): reset acknowledged\n",
2705                                   __func__, ha->host_no));
2706                 qla4_8xxx_set_rst_ready(ha);
2707         } else {
2708                 active_mask = (~(1 << (ha->func_num * 4)));
2709         }
2710
2711         /* wait for 10 seconds for reset ack from all functions */
2712         reset_timeout = jiffies + (ha->nx_reset_timeout * HZ);
2713
2714         drv_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2715         drv_active = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2716
2717         ql4_printk(KERN_INFO, ha,
2718                 "%s(%ld): drv_state = 0x%x, drv_active = 0x%x\n",
2719                 __func__, ha->host_no, drv_state, drv_active);
2720
2721         while (drv_state != (drv_active & active_mask)) {
2722                 if (time_after_eq(jiffies, reset_timeout)) {
2723                         ql4_printk(KERN_INFO, ha,
2724                                    "%s: RESET TIMEOUT! drv_state: 0x%08x, drv_active: 0x%08x\n",
2725                                    DRIVER_NAME, drv_state, drv_active);
2726                         break;
2727                 }
2728
2729                 /*
2730                  * When reset_owner times out, check which functions
2731                  * acked/did not ack
2732                  */
2733                 if (test_bit(AF_8XXX_RST_OWNER, &ha->flags)) {
2734                         ql4_printk(KERN_INFO, ha,
2735                                    "%s(%ld): drv_state = 0x%x, drv_active = 0x%x\n",
2736                                    __func__, ha->host_no, drv_state,
2737                                    drv_active);
2738                 }
2739                 qla4_82xx_idc_unlock(ha);
2740                 msleep(1000);
2741                 qla4_82xx_idc_lock(ha);
2742
2743                 drv_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2744                 drv_active = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2745         }
2746
2747         /* Clear RESET OWNER as we are not going to use it any further */
2748         clear_bit(AF_8XXX_RST_OWNER, &ha->flags);
2749
2750         dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
2751         ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n", dev_state,
2752                    dev_state < MAX_STATES ? qdev_state[dev_state] : "Unknown");
2753
2754         /* Force to DEV_COLD unless someone else is starting a reset */
2755         if (dev_state != QLA8XXX_DEV_INITIALIZING) {
2756                 ql4_printk(KERN_INFO, ha, "HW State: COLD/RE-INIT\n");
2757                 qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_COLD);
2758                 qla4_8xxx_set_rst_ready(ha);
2759         }
2760 }
2761
2762 /**
2763  * qla4_8xxx_need_qsnt_handler - Code to start qsnt
2764  * @ha: pointer to adapter structure
2765  **/
2766 void
2767 qla4_8xxx_need_qsnt_handler(struct scsi_qla_host *ha)
2768 {
2769         ha->isp_ops->idc_lock(ha);
2770         qla4_8xxx_set_qsnt_ready(ha);
2771         ha->isp_ops->idc_unlock(ha);
2772 }
2773
2774 static void qla4_82xx_set_idc_ver(struct scsi_qla_host *ha)
2775 {
2776         int idc_ver;
2777         uint32_t drv_active;
2778
2779         drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
2780         if (drv_active == (1 << (ha->func_num * 4))) {
2781                 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION,
2782                                     QLA82XX_IDC_VERSION);
2783                 ql4_printk(KERN_INFO, ha,
2784                            "%s: IDC version updated to %d\n", __func__,
2785                            QLA82XX_IDC_VERSION);
2786         } else {
2787                 idc_ver = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION);
2788                 if (QLA82XX_IDC_VERSION != idc_ver) {
2789                         ql4_printk(KERN_INFO, ha,
2790                                    "%s: qla4xxx driver IDC version %d is not compatible with IDC version %d of other drivers!\n",
2791                                    __func__, QLA82XX_IDC_VERSION, idc_ver);
2792                 }
2793         }
2794 }
2795
2796 static int qla4_83xx_set_idc_ver(struct scsi_qla_host *ha)
2797 {
2798         int idc_ver;
2799         uint32_t drv_active;
2800         int rval = QLA_SUCCESS;
2801
2802         drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
2803         if (drv_active == (1 << ha->func_num)) {
2804                 idc_ver = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION);
2805                 idc_ver &= (~0xFF);
2806                 idc_ver |= QLA83XX_IDC_VER_MAJ_VALUE;
2807                 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION, idc_ver);
2808                 ql4_printk(KERN_INFO, ha,
2809                            "%s: IDC version updated to %d\n", __func__,
2810                            idc_ver);
2811         } else {
2812                 idc_ver = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION);
2813                 idc_ver &= 0xFF;
2814                 if (QLA83XX_IDC_VER_MAJ_VALUE != idc_ver) {
2815                         ql4_printk(KERN_INFO, ha,
2816                                    "%s: qla4xxx driver IDC version %d is not compatible with IDC version %d of other drivers!\n",
2817                                    __func__, QLA83XX_IDC_VER_MAJ_VALUE,
2818                                    idc_ver);
2819                         rval = QLA_ERROR;
2820                         goto exit_set_idc_ver;
2821                 }
2822         }
2823
2824         /* Update IDC_MINOR_VERSION */
2825         idc_ver = qla4_83xx_rd_reg(ha, QLA83XX_CRB_IDC_VER_MINOR);
2826         idc_ver &= ~(0x03 << (ha->func_num * 2));
2827         idc_ver |= (QLA83XX_IDC_VER_MIN_VALUE << (ha->func_num * 2));
2828         qla4_83xx_wr_reg(ha, QLA83XX_CRB_IDC_VER_MINOR, idc_ver);
2829
2830 exit_set_idc_ver:
2831         return rval;
2832 }
2833
2834 int qla4_8xxx_update_idc_reg(struct scsi_qla_host *ha)
2835 {
2836         uint32_t drv_active;
2837         int rval = QLA_SUCCESS;
2838
2839         if (test_bit(AF_INIT_DONE, &ha->flags))
2840                 goto exit_update_idc_reg;
2841
2842         ha->isp_ops->idc_lock(ha);
2843         qla4_8xxx_set_drv_active(ha);
2844
2845         /*
2846          * If we are the first driver to load and
2847          * ql4xdontresethba is not set, clear IDC_CTRL BIT0.
2848          */
2849         if (is_qla8032(ha)) {
2850                 drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
2851                 if ((drv_active == (1 << ha->func_num)) && !ql4xdontresethba)
2852                         qla4_83xx_clear_idc_dontreset(ha);
2853         }
2854
2855         if (is_qla8022(ha)) {
2856                 qla4_82xx_set_idc_ver(ha);
2857         } else if (is_qla8032(ha)) {
2858                 rval = qla4_83xx_set_idc_ver(ha);
2859                 if (rval == QLA_ERROR)
2860                         qla4_8xxx_clear_drv_active(ha);
2861         }
2862
2863         ha->isp_ops->idc_unlock(ha);
2864
2865 exit_update_idc_reg:
2866         return rval;
2867 }
2868
2869 /**
2870  * qla4_8xxx_device_state_handler - Adapter state machine
2871  * @ha: pointer to host adapter structure.
2872  *
2873  * Note: IDC lock must be UNLOCKED upon entry
2874  **/
2875 int qla4_8xxx_device_state_handler(struct scsi_qla_host *ha)
2876 {
2877         uint32_t dev_state;
2878         int rval = QLA_SUCCESS;
2879         unsigned long dev_init_timeout;
2880
2881         rval = qla4_8xxx_update_idc_reg(ha);
2882         if (rval == QLA_ERROR)
2883                 goto exit_state_handler;
2884
2885         dev_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DEV_STATE);
2886         DEBUG2(ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n",
2887                           dev_state, dev_state < MAX_STATES ?
2888                           qdev_state[dev_state] : "Unknown"));
2889
2890         /* wait for 30 seconds for device to go ready */
2891         dev_init_timeout = jiffies + (ha->nx_dev_init_timeout * HZ);
2892
2893         ha->isp_ops->idc_lock(ha);
2894         while (1) {
2895
2896                 if (time_after_eq(jiffies, dev_init_timeout)) {
2897                         ql4_printk(KERN_WARNING, ha,
2898                                    "%s: Device Init Failed 0x%x = %s\n",
2899                                    DRIVER_NAME,
2900                                    dev_state, dev_state < MAX_STATES ?
2901                                    qdev_state[dev_state] : "Unknown");
2902                         qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE,
2903                                             QLA8XXX_DEV_FAILED);
2904                 }
2905
2906                 dev_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DEV_STATE);
2907                 ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n",
2908                            dev_state, dev_state < MAX_STATES ?
2909                            qdev_state[dev_state] : "Unknown");
2910
2911                 /* NOTE: Make sure idc unlocked upon exit of switch statement */
2912                 switch (dev_state) {
2913                 case QLA8XXX_DEV_READY:
2914                         goto exit;
2915                 case QLA8XXX_DEV_COLD:
2916                         rval = qla4_8xxx_device_bootstrap(ha);
2917                         goto exit;
2918                 case QLA8XXX_DEV_INITIALIZING:
2919                         ha->isp_ops->idc_unlock(ha);
2920                         msleep(1000);
2921                         ha->isp_ops->idc_lock(ha);
2922                         break;
2923                 case QLA8XXX_DEV_NEED_RESET:
2924                         /*
2925                          * For ISP8324, if NEED_RESET is set by any driver,
2926                          * it should be honored, irrespective of IDC_CTRL
2927                          * DONTRESET_BIT0
2928                          */
2929                         if (is_qla8032(ha)) {
2930                                 qla4_83xx_need_reset_handler(ha);
2931                         } else if (is_qla8022(ha)) {
2932                                 if (!ql4xdontresethba) {
2933                                         qla4_82xx_need_reset_handler(ha);
2934                                         /* Update timeout value after need
2935                                          * reset handler */
2936                                         dev_init_timeout = jiffies +
2937                                                 (ha->nx_dev_init_timeout * HZ);
2938                                 } else {
2939                                         ha->isp_ops->idc_unlock(ha);
2940                                         msleep(1000);
2941                                         ha->isp_ops->idc_lock(ha);
2942                                 }
2943                         }
2944                         break;
2945                 case QLA8XXX_DEV_NEED_QUIESCENT:
2946                         /* idc locked/unlocked in handler */
2947                         qla4_8xxx_need_qsnt_handler(ha);
2948                         break;
2949                 case QLA8XXX_DEV_QUIESCENT:
2950                         ha->isp_ops->idc_unlock(ha);
2951                         msleep(1000);
2952                         ha->isp_ops->idc_lock(ha);
2953                         break;
2954                 case QLA8XXX_DEV_FAILED:
2955                         ha->isp_ops->idc_unlock(ha);
2956                         qla4xxx_dead_adapter_cleanup(ha);
2957                         rval = QLA_ERROR;
2958                         ha->isp_ops->idc_lock(ha);
2959                         goto exit;
2960                 default:
2961                         ha->isp_ops->idc_unlock(ha);
2962                         qla4xxx_dead_adapter_cleanup(ha);
2963                         rval = QLA_ERROR;
2964                         ha->isp_ops->idc_lock(ha);
2965                         goto exit;
2966                 }
2967         }
2968 exit:
2969         ha->isp_ops->idc_unlock(ha);
2970 exit_state_handler:
2971         return rval;
2972 }
2973
2974 int qla4_8xxx_load_risc(struct scsi_qla_host *ha)
2975 {
2976         int retval;
2977
2978         /* clear the interrupt */
2979         if (is_qla8032(ha)) {
2980                 writel(0, &ha->qla4_83xx_reg->risc_intr);
2981                 readl(&ha->qla4_83xx_reg->risc_intr);
2982         } else if (is_qla8022(ha)) {
2983                 writel(0, &ha->qla4_82xx_reg->host_int);
2984                 readl(&ha->qla4_82xx_reg->host_int);
2985         }
2986
2987         retval = qla4_8xxx_device_state_handler(ha);
2988
2989         if (retval == QLA_SUCCESS && !test_bit(AF_IRQ_ATTACHED, &ha->flags))
2990                 retval = qla4xxx_request_irqs(ha);
2991
2992         return retval;
2993 }
2994
2995 /*****************************************************************************/
2996 /* Flash Manipulation Routines                                               */
2997 /*****************************************************************************/
2998
2999 #define OPTROM_BURST_SIZE       0x1000
3000 #define OPTROM_BURST_DWORDS     (OPTROM_BURST_SIZE / 4)
3001
3002 #define FARX_DATA_FLAG  BIT_31
3003 #define FARX_ACCESS_FLASH_CONF  0x7FFD0000
3004 #define FARX_ACCESS_FLASH_DATA  0x7FF00000
3005
3006 static inline uint32_t
3007 flash_conf_addr(struct ql82xx_hw_data *hw, uint32_t faddr)
3008 {
3009         return hw->flash_conf_off | faddr;
3010 }
3011
3012 static inline uint32_t
3013 flash_data_addr(struct ql82xx_hw_data *hw, uint32_t faddr)
3014 {
3015         return hw->flash_data_off | faddr;
3016 }
3017
3018 static uint32_t *
3019 qla4_82xx_read_flash_data(struct scsi_qla_host *ha, uint32_t *dwptr,
3020     uint32_t faddr, uint32_t length)
3021 {
3022         uint32_t i;
3023         uint32_t val;
3024         int loops = 0;
3025         while ((qla4_82xx_rom_lock(ha) != 0) && (loops < 50000)) {
3026                 udelay(100);
3027                 cond_resched();
3028                 loops++;
3029         }
3030         if (loops >= 50000) {
3031                 ql4_printk(KERN_WARNING, ha, "ROM lock failed\n");
3032                 return dwptr;
3033         }
3034
3035         /* Dword reads to flash. */
3036         for (i = 0; i < length/4; i++, faddr += 4) {
3037                 if (qla4_82xx_do_rom_fast_read(ha, faddr, &val)) {
3038                         ql4_printk(KERN_WARNING, ha,
3039                             "Do ROM fast read failed\n");
3040                         goto done_read;
3041                 }
3042                 dwptr[i] = __constant_cpu_to_le32(val);
3043         }
3044
3045 done_read:
3046         qla4_82xx_rom_unlock(ha);
3047         return dwptr;
3048 }
3049
3050 /**
3051  * Address and length are byte address
3052  **/
3053 static uint8_t *
3054 qla4_82xx_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
3055                 uint32_t offset, uint32_t length)
3056 {
3057         qla4_82xx_read_flash_data(ha, (uint32_t *)buf, offset, length);
3058         return buf;
3059 }
3060
3061 static int
3062 qla4_8xxx_find_flt_start(struct scsi_qla_host *ha, uint32_t *start)
3063 {
3064         const char *loc, *locations[] = { "DEF", "PCI" };
3065
3066         /*
3067          * FLT-location structure resides after the last PCI region.
3068          */
3069
3070         /* Begin with sane defaults. */
3071         loc = locations[0];
3072         *start = FA_FLASH_LAYOUT_ADDR_82;
3073
3074         DEBUG2(ql4_printk(KERN_INFO, ha, "FLTL[%s] = 0x%x.\n", loc, *start));
3075         return QLA_SUCCESS;
3076 }
3077
3078 static void
3079 qla4_8xxx_get_flt_info(struct scsi_qla_host *ha, uint32_t flt_addr)
3080 {
3081         const char *loc, *locations[] = { "DEF", "FLT" };
3082         uint16_t *wptr;
3083         uint16_t cnt, chksum;
3084         uint32_t start, status;
3085         struct qla_flt_header *flt;
3086         struct qla_flt_region *region;
3087         struct ql82xx_hw_data *hw = &ha->hw;
3088
3089         hw->flt_region_flt = flt_addr;
3090         wptr = (uint16_t *)ha->request_ring;
3091         flt = (struct qla_flt_header *)ha->request_ring;
3092         region = (struct qla_flt_region *)&flt[1];
3093
3094         if (is_qla8022(ha)) {
3095                 qla4_82xx_read_optrom_data(ha, (uint8_t *)ha->request_ring,
3096                                            flt_addr << 2, OPTROM_BURST_SIZE);
3097         } else if (is_qla8032(ha)) {
3098                 status = qla4_83xx_flash_read_u32(ha, flt_addr << 2,
3099                                                   (uint8_t *)ha->request_ring,
3100                                                   0x400);
3101                 if (status != QLA_SUCCESS)
3102                         goto no_flash_data;
3103         }
3104
3105         if (*wptr == __constant_cpu_to_le16(0xffff))
3106                 goto no_flash_data;
3107         if (flt->version != __constant_cpu_to_le16(1)) {
3108                 DEBUG2(ql4_printk(KERN_INFO, ha, "Unsupported FLT detected: "
3109                         "version=0x%x length=0x%x checksum=0x%x.\n",
3110                         le16_to_cpu(flt->version), le16_to_cpu(flt->length),
3111                         le16_to_cpu(flt->checksum)));
3112                 goto no_flash_data;
3113         }
3114
3115         cnt = (sizeof(struct qla_flt_header) + le16_to_cpu(flt->length)) >> 1;
3116         for (chksum = 0; cnt; cnt--)
3117                 chksum += le16_to_cpu(*wptr++);
3118         if (chksum) {
3119                 DEBUG2(ql4_printk(KERN_INFO, ha, "Inconsistent FLT detected: "
3120                         "version=0x%x length=0x%x checksum=0x%x.\n",
3121                         le16_to_cpu(flt->version), le16_to_cpu(flt->length),
3122                         chksum));
3123                 goto no_flash_data;
3124         }
3125
3126         loc = locations[1];
3127         cnt = le16_to_cpu(flt->length) / sizeof(struct qla_flt_region);
3128         for ( ; cnt; cnt--, region++) {
3129                 /* Store addresses as DWORD offsets. */
3130                 start = le32_to_cpu(region->start) >> 2;
3131
3132                 DEBUG3(ql4_printk(KERN_DEBUG, ha, "FLT[%02x]: start=0x%x "
3133                     "end=0x%x size=0x%x.\n", le32_to_cpu(region->code), start,
3134                     le32_to_cpu(region->end) >> 2, le32_to_cpu(region->size)));
3135
3136                 switch (le32_to_cpu(region->code) & 0xff) {
3137                 case FLT_REG_FDT:
3138                         hw->flt_region_fdt = start;
3139                         break;
3140                 case FLT_REG_BOOT_CODE_82:
3141                         hw->flt_region_boot = start;
3142                         break;
3143                 case FLT_REG_FW_82:
3144                 case FLT_REG_FW_82_1:
3145                         hw->flt_region_fw = start;
3146                         break;
3147                 case FLT_REG_BOOTLOAD_82:
3148                         hw->flt_region_bootload = start;
3149                         break;
3150                 case FLT_REG_ISCSI_PARAM:
3151                         hw->flt_iscsi_param =  start;
3152                         break;
3153                 case FLT_REG_ISCSI_CHAP:
3154                         hw->flt_region_chap =  start;
3155                         hw->flt_chap_size =  le32_to_cpu(region->size);
3156                         break;
3157                 case FLT_REG_ISCSI_DDB:
3158                         hw->flt_region_ddb =  start;
3159                         hw->flt_ddb_size =  le32_to_cpu(region->size);
3160                         break;
3161                 }
3162         }
3163         goto done;
3164
3165 no_flash_data:
3166         /* Use hardcoded defaults. */
3167         loc = locations[0];
3168
3169         hw->flt_region_fdt      = FA_FLASH_DESCR_ADDR_82;
3170         hw->flt_region_boot     = FA_BOOT_CODE_ADDR_82;
3171         hw->flt_region_bootload = FA_BOOT_LOAD_ADDR_82;
3172         hw->flt_region_fw       = FA_RISC_CODE_ADDR_82;
3173         hw->flt_region_chap     = FA_FLASH_ISCSI_CHAP >> 2;
3174         hw->flt_chap_size       = FA_FLASH_CHAP_SIZE;
3175         hw->flt_region_ddb      = FA_FLASH_ISCSI_DDB >> 2;
3176         hw->flt_ddb_size        = FA_FLASH_DDB_SIZE;
3177
3178 done:
3179         DEBUG2(ql4_printk(KERN_INFO, ha,
3180                           "FLT[%s]: flt=0x%x fdt=0x%x boot=0x%x bootload=0x%x fw=0x%x chap=0x%x chap_size=0x%x ddb=0x%x  ddb_size=0x%x\n",
3181                           loc, hw->flt_region_flt, hw->flt_region_fdt,
3182                           hw->flt_region_boot, hw->flt_region_bootload,
3183                           hw->flt_region_fw, hw->flt_region_chap,
3184                           hw->flt_chap_size, hw->flt_region_ddb,
3185                           hw->flt_ddb_size));
3186 }
3187
3188 static void
3189 qla4_82xx_get_fdt_info(struct scsi_qla_host *ha)
3190 {
3191 #define FLASH_BLK_SIZE_4K       0x1000
3192 #define FLASH_BLK_SIZE_32K      0x8000
3193 #define FLASH_BLK_SIZE_64K      0x10000
3194         const char *loc, *locations[] = { "MID", "FDT" };
3195         uint16_t cnt, chksum;
3196         uint16_t *wptr;
3197         struct qla_fdt_layout *fdt;
3198         uint16_t mid = 0;
3199         uint16_t fid = 0;
3200         struct ql82xx_hw_data *hw = &ha->hw;
3201
3202         hw->flash_conf_off = FARX_ACCESS_FLASH_CONF;
3203         hw->flash_data_off = FARX_ACCESS_FLASH_DATA;
3204
3205         wptr = (uint16_t *)ha->request_ring;
3206         fdt = (struct qla_fdt_layout *)ha->request_ring;
3207         qla4_82xx_read_optrom_data(ha, (uint8_t *)ha->request_ring,
3208             hw->flt_region_fdt << 2, OPTROM_BURST_SIZE);
3209
3210         if (*wptr == __constant_cpu_to_le16(0xffff))
3211                 goto no_flash_data;
3212
3213         if (fdt->sig[0] != 'Q' || fdt->sig[1] != 'L' || fdt->sig[2] != 'I' ||
3214             fdt->sig[3] != 'D')
3215                 goto no_flash_data;
3216
3217         for (cnt = 0, chksum = 0; cnt < sizeof(struct qla_fdt_layout) >> 1;
3218             cnt++)
3219                 chksum += le16_to_cpu(*wptr++);
3220
3221         if (chksum) {
3222                 DEBUG2(ql4_printk(KERN_INFO, ha, "Inconsistent FDT detected: "
3223                     "checksum=0x%x id=%c version=0x%x.\n", chksum, fdt->sig[0],
3224                     le16_to_cpu(fdt->version)));
3225                 goto no_flash_data;
3226         }
3227
3228         loc = locations[1];
3229         mid = le16_to_cpu(fdt->man_id);
3230         fid = le16_to_cpu(fdt->id);
3231         hw->fdt_wrt_disable = fdt->wrt_disable_bits;
3232         hw->fdt_erase_cmd = flash_conf_addr(hw, 0x0300 | fdt->erase_cmd);
3233         hw->fdt_block_size = le32_to_cpu(fdt->block_size);
3234
3235         if (fdt->unprotect_sec_cmd) {
3236                 hw->fdt_unprotect_sec_cmd = flash_conf_addr(hw, 0x0300 |
3237                     fdt->unprotect_sec_cmd);
3238                 hw->fdt_protect_sec_cmd = fdt->protect_sec_cmd ?
3239                     flash_conf_addr(hw, 0x0300 | fdt->protect_sec_cmd) :
3240                     flash_conf_addr(hw, 0x0336);
3241         }
3242         goto done;
3243
3244 no_flash_data:
3245         loc = locations[0];
3246         hw->fdt_block_size = FLASH_BLK_SIZE_64K;
3247 done:
3248         DEBUG2(ql4_printk(KERN_INFO, ha, "FDT[%s]: (0x%x/0x%x) erase=0x%x "
3249                 "pro=%x upro=%x wrtd=0x%x blk=0x%x.\n", loc, mid, fid,
3250                 hw->fdt_erase_cmd, hw->fdt_protect_sec_cmd,
3251                 hw->fdt_unprotect_sec_cmd, hw->fdt_wrt_disable,
3252                 hw->fdt_block_size));
3253 }
3254
3255 static void
3256 qla4_82xx_get_idc_param(struct scsi_qla_host *ha)
3257 {
3258 #define QLA82XX_IDC_PARAM_ADDR      0x003e885c
3259         uint32_t *wptr;
3260
3261         if (!is_qla8022(ha))
3262                 return;
3263         wptr = (uint32_t *)ha->request_ring;
3264         qla4_82xx_read_optrom_data(ha, (uint8_t *)ha->request_ring,
3265                         QLA82XX_IDC_PARAM_ADDR , 8);
3266
3267         if (*wptr == __constant_cpu_to_le32(0xffffffff)) {
3268                 ha->nx_dev_init_timeout = ROM_DEV_INIT_TIMEOUT;
3269                 ha->nx_reset_timeout = ROM_DRV_RESET_ACK_TIMEOUT;
3270         } else {
3271                 ha->nx_dev_init_timeout = le32_to_cpu(*wptr++);
3272                 ha->nx_reset_timeout = le32_to_cpu(*wptr);
3273         }
3274
3275         DEBUG2(ql4_printk(KERN_DEBUG, ha,
3276                 "ha->nx_dev_init_timeout = %d\n", ha->nx_dev_init_timeout));
3277         DEBUG2(ql4_printk(KERN_DEBUG, ha,
3278                 "ha->nx_reset_timeout = %d\n", ha->nx_reset_timeout));
3279         return;
3280 }
3281
3282 void qla4_82xx_queue_mbox_cmd(struct scsi_qla_host *ha, uint32_t *mbx_cmd,
3283                               int in_count)
3284 {
3285         int i;
3286
3287         /* Load all mailbox registers, except mailbox 0. */
3288         for (i = 1; i < in_count; i++)
3289                 writel(mbx_cmd[i], &ha->qla4_82xx_reg->mailbox_in[i]);
3290
3291         /* Wakeup firmware  */
3292         writel(mbx_cmd[0], &ha->qla4_82xx_reg->mailbox_in[0]);
3293         readl(&ha->qla4_82xx_reg->mailbox_in[0]);
3294         writel(HINT_MBX_INT_PENDING, &ha->qla4_82xx_reg->hint);
3295         readl(&ha->qla4_82xx_reg->hint);
3296 }
3297
3298 void qla4_82xx_process_mbox_intr(struct scsi_qla_host *ha, int out_count)
3299 {
3300         int intr_status;
3301
3302         intr_status = readl(&ha->qla4_82xx_reg->host_int);
3303         if (intr_status & ISRX_82XX_RISC_INT) {
3304                 ha->mbox_status_count = out_count;
3305                 intr_status = readl(&ha->qla4_82xx_reg->host_status);
3306                 ha->isp_ops->interrupt_service_routine(ha, intr_status);
3307
3308                 if (test_bit(AF_INTERRUPTS_ON, &ha->flags) &&
3309                     test_bit(AF_INTx_ENABLED, &ha->flags))
3310                         qla4_82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg,
3311                                         0xfbff);
3312         }
3313 }
3314
3315 int
3316 qla4_8xxx_get_flash_info(struct scsi_qla_host *ha)
3317 {
3318         int ret;
3319         uint32_t flt_addr;
3320
3321         ret = qla4_8xxx_find_flt_start(ha, &flt_addr);
3322         if (ret != QLA_SUCCESS)
3323                 return ret;
3324
3325         qla4_8xxx_get_flt_info(ha, flt_addr);
3326         if (is_qla8022(ha)) {
3327                 qla4_82xx_get_fdt_info(ha);
3328                 qla4_82xx_get_idc_param(ha);
3329         } else if (is_qla8032(ha)) {
3330                 qla4_83xx_get_idc_param(ha);
3331         }
3332
3333         return QLA_SUCCESS;
3334 }
3335
3336 /**
3337  * qla4_8xxx_stop_firmware - stops firmware on specified adapter instance
3338  * @ha: pointer to host adapter structure.
3339  *
3340  * Remarks:
3341  * For iSCSI, throws away all I/O and AENs into bit bucket, so they will
3342  * not be available after successful return.  Driver must cleanup potential
3343  * outstanding I/O's after calling this funcion.
3344  **/
3345 int
3346 qla4_8xxx_stop_firmware(struct scsi_qla_host *ha)
3347 {
3348         int status;
3349         uint32_t mbox_cmd[MBOX_REG_COUNT];
3350         uint32_t mbox_sts[MBOX_REG_COUNT];
3351
3352         memset(&mbox_cmd, 0, sizeof(mbox_cmd));
3353         memset(&mbox_sts, 0, sizeof(mbox_sts));
3354
3355         mbox_cmd[0] = MBOX_CMD_STOP_FW;
3356         status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1,
3357             &mbox_cmd[0], &mbox_sts[0]);
3358
3359         DEBUG2(printk("scsi%ld: %s: status = %d\n", ha->host_no,
3360             __func__, status));
3361         return status;
3362 }
3363
3364 /**
3365  * qla4_82xx_isp_reset - Resets ISP and aborts all outstanding commands.
3366  * @ha: pointer to host adapter structure.
3367  **/
3368 int
3369 qla4_82xx_isp_reset(struct scsi_qla_host *ha)
3370 {
3371         int rval;
3372         uint32_t dev_state;
3373
3374         qla4_82xx_idc_lock(ha);
3375         dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3376
3377         if (dev_state == QLA8XXX_DEV_READY) {
3378                 ql4_printk(KERN_INFO, ha, "HW State: NEED RESET\n");
3379                 qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
3380                     QLA8XXX_DEV_NEED_RESET);
3381                 set_bit(AF_8XXX_RST_OWNER, &ha->flags);
3382         } else
3383                 ql4_printk(KERN_INFO, ha, "HW State: DEVICE INITIALIZING\n");
3384
3385         qla4_82xx_idc_unlock(ha);
3386
3387         rval = qla4_8xxx_device_state_handler(ha);
3388
3389         qla4_82xx_idc_lock(ha);
3390         qla4_8xxx_clear_rst_ready(ha);
3391         qla4_82xx_idc_unlock(ha);
3392
3393         if (rval == QLA_SUCCESS) {
3394                 ql4_printk(KERN_INFO, ha, "Clearing AF_RECOVERY in qla4_82xx_isp_reset\n");
3395                 clear_bit(AF_FW_RECOVERY, &ha->flags);
3396         }
3397
3398         return rval;
3399 }
3400
3401 /**
3402  * qla4_8xxx_get_sys_info - get adapter MAC address(es) and serial number
3403  * @ha: pointer to host adapter structure.
3404  *
3405  **/
3406 int qla4_8xxx_get_sys_info(struct scsi_qla_host *ha)
3407 {
3408         uint32_t mbox_cmd[MBOX_REG_COUNT];
3409         uint32_t mbox_sts[MBOX_REG_COUNT];
3410         struct mbx_sys_info *sys_info;
3411         dma_addr_t sys_info_dma;
3412         int status = QLA_ERROR;
3413
3414         sys_info = dma_alloc_coherent(&ha->pdev->dev, sizeof(*sys_info),
3415                                       &sys_info_dma, GFP_KERNEL);
3416         if (sys_info == NULL) {
3417                 DEBUG2(printk("scsi%ld: %s: Unable to allocate dma buffer.\n",
3418                     ha->host_no, __func__));
3419                 return status;
3420         }
3421
3422         memset(sys_info, 0, sizeof(*sys_info));
3423         memset(&mbox_cmd, 0, sizeof(mbox_cmd));
3424         memset(&mbox_sts, 0, sizeof(mbox_sts));
3425
3426         mbox_cmd[0] = MBOX_CMD_GET_SYS_INFO;
3427         mbox_cmd[1] = LSDW(sys_info_dma);
3428         mbox_cmd[2] = MSDW(sys_info_dma);
3429         mbox_cmd[4] = sizeof(*sys_info);
3430
3431         if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 6, &mbox_cmd[0],
3432             &mbox_sts[0]) != QLA_SUCCESS) {
3433                 DEBUG2(printk("scsi%ld: %s: GET_SYS_INFO failed\n",
3434                     ha->host_no, __func__));
3435                 goto exit_validate_mac82;
3436         }
3437
3438         /* Make sure we receive the minimum required data to cache internally */
3439         if ((is_qla8032(ha) ? mbox_sts[3] : mbox_sts[4]) <
3440             offsetof(struct mbx_sys_info, reserved)) {
3441                 DEBUG2(printk("scsi%ld: %s: GET_SYS_INFO data receive"
3442                     " error (%x)\n", ha->host_no, __func__, mbox_sts[4]));
3443                 goto exit_validate_mac82;
3444         }
3445
3446         /* Save M.A.C. address & serial_number */
3447         ha->port_num = sys_info->port_num;
3448         memcpy(ha->my_mac, &sys_info->mac_addr[0],
3449             min(sizeof(ha->my_mac), sizeof(sys_info->mac_addr)));
3450         memcpy(ha->serial_number, &sys_info->serial_number,
3451             min(sizeof(ha->serial_number), sizeof(sys_info->serial_number)));
3452         memcpy(ha->model_name, &sys_info->board_id_str,
3453                min(sizeof(ha->model_name), sizeof(sys_info->board_id_str)));
3454         ha->phy_port_cnt = sys_info->phys_port_cnt;
3455         ha->phy_port_num = sys_info->port_num;
3456         ha->iscsi_pci_func_cnt = sys_info->iscsi_pci_func_cnt;
3457
3458         DEBUG2(printk("scsi%ld: %s: "
3459             "mac %02x:%02x:%02x:%02x:%02x:%02x "
3460             "serial %s\n", ha->host_no, __func__,
3461             ha->my_mac[0], ha->my_mac[1], ha->my_mac[2],
3462             ha->my_mac[3], ha->my_mac[4], ha->my_mac[5],
3463             ha->serial_number));
3464
3465         status = QLA_SUCCESS;
3466
3467 exit_validate_mac82:
3468         dma_free_coherent(&ha->pdev->dev, sizeof(*sys_info), sys_info,
3469                           sys_info_dma);
3470         return status;
3471 }
3472
3473 /* Interrupt handling helpers. */
3474
3475 int qla4_8xxx_intr_enable(struct scsi_qla_host *ha)
3476 {
3477         uint32_t mbox_cmd[MBOX_REG_COUNT];
3478         uint32_t mbox_sts[MBOX_REG_COUNT];
3479
3480         DEBUG2(ql4_printk(KERN_INFO, ha, "%s\n", __func__));
3481
3482         memset(&mbox_cmd, 0, sizeof(mbox_cmd));
3483         memset(&mbox_sts, 0, sizeof(mbox_sts));
3484         mbox_cmd[0] = MBOX_CMD_ENABLE_INTRS;
3485         mbox_cmd[1] = INTR_ENABLE;
3486         if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
3487                 &mbox_sts[0]) != QLA_SUCCESS) {
3488                 DEBUG2(ql4_printk(KERN_INFO, ha,
3489                     "%s: MBOX_CMD_ENABLE_INTRS failed (0x%04x)\n",
3490                     __func__, mbox_sts[0]));
3491                 return QLA_ERROR;
3492         }
3493         return QLA_SUCCESS;
3494 }
3495
3496 int qla4_8xxx_intr_disable(struct scsi_qla_host *ha)
3497 {
3498         uint32_t mbox_cmd[MBOX_REG_COUNT];
3499         uint32_t mbox_sts[MBOX_REG_COUNT];
3500
3501         DEBUG2(ql4_printk(KERN_INFO, ha, "%s\n", __func__));
3502
3503         memset(&mbox_cmd, 0, sizeof(mbox_cmd));
3504         memset(&mbox_sts, 0, sizeof(mbox_sts));
3505         mbox_cmd[0] = MBOX_CMD_ENABLE_INTRS;
3506         mbox_cmd[1] = INTR_DISABLE;
3507         if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
3508             &mbox_sts[0]) != QLA_SUCCESS) {
3509                 DEBUG2(ql4_printk(KERN_INFO, ha,
3510                         "%s: MBOX_CMD_ENABLE_INTRS failed (0x%04x)\n",
3511                         __func__, mbox_sts[0]));
3512                 return QLA_ERROR;
3513         }
3514
3515         return QLA_SUCCESS;
3516 }
3517
3518 void
3519 qla4_82xx_enable_intrs(struct scsi_qla_host *ha)
3520 {
3521         qla4_8xxx_intr_enable(ha);
3522
3523         spin_lock_irq(&ha->hardware_lock);
3524         /* BIT 10 - reset */
3525         qla4_82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff);
3526         spin_unlock_irq(&ha->hardware_lock);
3527         set_bit(AF_INTERRUPTS_ON, &ha->flags);
3528 }
3529
3530 void
3531 qla4_82xx_disable_intrs(struct scsi_qla_host *ha)
3532 {
3533         if (test_and_clear_bit(AF_INTERRUPTS_ON, &ha->flags))
3534                 qla4_8xxx_intr_disable(ha);
3535
3536         spin_lock_irq(&ha->hardware_lock);
3537         /* BIT 10 - set */
3538         qla4_82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400);
3539         spin_unlock_irq(&ha->hardware_lock);
3540 }
3541
3542 struct ql4_init_msix_entry {
3543         uint16_t entry;
3544         uint16_t index;
3545         const char *name;
3546         irq_handler_t handler;
3547 };
3548
3549 static struct ql4_init_msix_entry qla4_8xxx_msix_entries[QLA_MSIX_ENTRIES] = {
3550         { QLA_MSIX_DEFAULT, QLA_MIDX_DEFAULT,
3551             "qla4xxx (default)",
3552             (irq_handler_t)qla4_8xxx_default_intr_handler },
3553         { QLA_MSIX_RSP_Q, QLA_MIDX_RSP_Q,
3554             "qla4xxx (rsp_q)", (irq_handler_t)qla4_8xxx_msix_rsp_q },
3555 };
3556
3557 void
3558 qla4_8xxx_disable_msix(struct scsi_qla_host *ha)
3559 {
3560         int i;
3561         struct ql4_msix_entry *qentry;
3562
3563         for (i = 0; i < QLA_MSIX_ENTRIES; i++) {
3564                 qentry = &ha->msix_entries[qla4_8xxx_msix_entries[i].index];
3565                 if (qentry->have_irq) {
3566                         free_irq(qentry->msix_vector, ha);
3567                         DEBUG2(ql4_printk(KERN_INFO, ha, "%s: %s\n",
3568                                 __func__, qla4_8xxx_msix_entries[i].name));
3569                 }
3570         }
3571         pci_disable_msix(ha->pdev);
3572         clear_bit(AF_MSIX_ENABLED, &ha->flags);
3573 }
3574
3575 int
3576 qla4_8xxx_enable_msix(struct scsi_qla_host *ha)
3577 {
3578         int i, ret;
3579         struct msix_entry entries[QLA_MSIX_ENTRIES];
3580         struct ql4_msix_entry *qentry;
3581
3582         for (i = 0; i < QLA_MSIX_ENTRIES; i++)
3583                 entries[i].entry = qla4_8xxx_msix_entries[i].entry;
3584
3585         ret = pci_enable_msix(ha->pdev, entries, ARRAY_SIZE(entries));
3586         if (ret) {
3587                 ql4_printk(KERN_WARNING, ha,
3588                     "MSI-X: Failed to enable support -- %d/%d\n",
3589                     QLA_MSIX_ENTRIES, ret);
3590                 goto msix_out;
3591         }
3592         set_bit(AF_MSIX_ENABLED, &ha->flags);
3593
3594         for (i = 0; i < QLA_MSIX_ENTRIES; i++) {
3595                 qentry = &ha->msix_entries[qla4_8xxx_msix_entries[i].index];
3596                 qentry->msix_vector = entries[i].vector;
3597                 qentry->msix_entry = entries[i].entry;
3598                 qentry->have_irq = 0;
3599                 ret = request_irq(qentry->msix_vector,
3600                     qla4_8xxx_msix_entries[i].handler, 0,
3601                     qla4_8xxx_msix_entries[i].name, ha);
3602                 if (ret) {
3603                         ql4_printk(KERN_WARNING, ha,
3604                             "MSI-X: Unable to register handler -- %x/%d.\n",
3605                             qla4_8xxx_msix_entries[i].index, ret);
3606                         qla4_8xxx_disable_msix(ha);
3607                         goto msix_out;
3608                 }
3609                 qentry->have_irq = 1;
3610                 DEBUG2(ql4_printk(KERN_INFO, ha, "%s: %s\n",
3611                         __func__, qla4_8xxx_msix_entries[i].name));
3612         }
3613 msix_out:
3614         return ret;
3615 }