2 * QLogic iSCSI HBA Driver
3 * Copyright (c) 2003-2013 QLogic Corporation
5 * See LICENSE.qla4xxx for copyright and licensing details.
7 #include <linux/delay.h>
10 #include <linux/ratelimit.h>
13 #include "ql4_inline.h"
15 #include <asm-generic/io-64-nonatomic-lo-hi.h>
17 #define MASK(n) DMA_BIT_MASK(n)
18 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff))
19 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff))
20 #define MS_WIN(addr) (addr & 0x0ffc0000)
21 #define QLA82XX_PCI_MN_2M (0)
22 #define QLA82XX_PCI_MS_2M (0x80000)
23 #define QLA82XX_PCI_OCM0_2M (0xc0000)
24 #define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800)
25 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
27 /* CRB window related */
28 #define CRB_BLK(off) ((off >> 20) & 0x3f)
29 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
30 #define CRB_WINDOW_2M (0x130060)
31 #define CRB_HI(off) ((qla4_82xx_crb_hub_agt[CRB_BLK(off)] << 20) | \
33 #define QLA82XX_PCI_CAMQM_2M_END (0x04800800UL)
34 #define QLA82XX_PCI_CAMQM_2M_BASE (0x000ff800UL)
35 #define CRB_INDIRECT_2M (0x1e0000UL)
37 static inline void __iomem *
38 qla4_8xxx_pci_base_offsetfset(struct scsi_qla_host *ha, unsigned long off)
40 if ((off < ha->first_page_group_end) &&
41 (off >= ha->first_page_group_start))
42 return (void __iomem *)(ha->nx_pcibase + off);
47 #define MAX_CRB_XFORM 60
48 static unsigned long crb_addr_xform[MAX_CRB_XFORM];
49 static int qla4_8xxx_crb_table_initialized;
51 #define qla4_8xxx_crb_addr_transform(name) \
52 (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \
53 QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20)
55 qla4_82xx_crb_addr_transform_setup(void)
57 qla4_8xxx_crb_addr_transform(XDMA);
58 qla4_8xxx_crb_addr_transform(TIMR);
59 qla4_8xxx_crb_addr_transform(SRE);
60 qla4_8xxx_crb_addr_transform(SQN3);
61 qla4_8xxx_crb_addr_transform(SQN2);
62 qla4_8xxx_crb_addr_transform(SQN1);
63 qla4_8xxx_crb_addr_transform(SQN0);
64 qla4_8xxx_crb_addr_transform(SQS3);
65 qla4_8xxx_crb_addr_transform(SQS2);
66 qla4_8xxx_crb_addr_transform(SQS1);
67 qla4_8xxx_crb_addr_transform(SQS0);
68 qla4_8xxx_crb_addr_transform(RPMX7);
69 qla4_8xxx_crb_addr_transform(RPMX6);
70 qla4_8xxx_crb_addr_transform(RPMX5);
71 qla4_8xxx_crb_addr_transform(RPMX4);
72 qla4_8xxx_crb_addr_transform(RPMX3);
73 qla4_8xxx_crb_addr_transform(RPMX2);
74 qla4_8xxx_crb_addr_transform(RPMX1);
75 qla4_8xxx_crb_addr_transform(RPMX0);
76 qla4_8xxx_crb_addr_transform(ROMUSB);
77 qla4_8xxx_crb_addr_transform(SN);
78 qla4_8xxx_crb_addr_transform(QMN);
79 qla4_8xxx_crb_addr_transform(QMS);
80 qla4_8xxx_crb_addr_transform(PGNI);
81 qla4_8xxx_crb_addr_transform(PGND);
82 qla4_8xxx_crb_addr_transform(PGN3);
83 qla4_8xxx_crb_addr_transform(PGN2);
84 qla4_8xxx_crb_addr_transform(PGN1);
85 qla4_8xxx_crb_addr_transform(PGN0);
86 qla4_8xxx_crb_addr_transform(PGSI);
87 qla4_8xxx_crb_addr_transform(PGSD);
88 qla4_8xxx_crb_addr_transform(PGS3);
89 qla4_8xxx_crb_addr_transform(PGS2);
90 qla4_8xxx_crb_addr_transform(PGS1);
91 qla4_8xxx_crb_addr_transform(PGS0);
92 qla4_8xxx_crb_addr_transform(PS);
93 qla4_8xxx_crb_addr_transform(PH);
94 qla4_8xxx_crb_addr_transform(NIU);
95 qla4_8xxx_crb_addr_transform(I2Q);
96 qla4_8xxx_crb_addr_transform(EG);
97 qla4_8xxx_crb_addr_transform(MN);
98 qla4_8xxx_crb_addr_transform(MS);
99 qla4_8xxx_crb_addr_transform(CAS2);
100 qla4_8xxx_crb_addr_transform(CAS1);
101 qla4_8xxx_crb_addr_transform(CAS0);
102 qla4_8xxx_crb_addr_transform(CAM);
103 qla4_8xxx_crb_addr_transform(C2C1);
104 qla4_8xxx_crb_addr_transform(C2C0);
105 qla4_8xxx_crb_addr_transform(SMB);
106 qla4_8xxx_crb_addr_transform(OCM0);
107 qla4_8xxx_crb_addr_transform(I2C0);
109 qla4_8xxx_crb_table_initialized = 1;
112 static struct crb_128M_2M_block_map crb_128M_2M_map[64] = {
113 {{{0, 0, 0, 0} } }, /* 0: PCI */
114 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
115 {1, 0x0110000, 0x0120000, 0x130000},
116 {1, 0x0120000, 0x0122000, 0x124000},
117 {1, 0x0130000, 0x0132000, 0x126000},
118 {1, 0x0140000, 0x0142000, 0x128000},
119 {1, 0x0150000, 0x0152000, 0x12a000},
120 {1, 0x0160000, 0x0170000, 0x110000},
121 {1, 0x0170000, 0x0172000, 0x12e000},
122 {0, 0x0000000, 0x0000000, 0x000000},
123 {0, 0x0000000, 0x0000000, 0x000000},
124 {0, 0x0000000, 0x0000000, 0x000000},
125 {0, 0x0000000, 0x0000000, 0x000000},
126 {0, 0x0000000, 0x0000000, 0x000000},
127 {0, 0x0000000, 0x0000000, 0x000000},
128 {1, 0x01e0000, 0x01e0800, 0x122000},
129 {0, 0x0000000, 0x0000000, 0x000000} } },
130 {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
131 {{{0, 0, 0, 0} } }, /* 3: */
132 {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
133 {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */
134 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */
135 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */
136 {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {0, 0x0000000, 0x0000000, 0x000000},
140 {0, 0x0000000, 0x0000000, 0x000000},
141 {0, 0x0000000, 0x0000000, 0x000000},
142 {0, 0x0000000, 0x0000000, 0x000000},
143 {0, 0x0000000, 0x0000000, 0x000000},
144 {0, 0x0000000, 0x0000000, 0x000000},
145 {0, 0x0000000, 0x0000000, 0x000000},
146 {0, 0x0000000, 0x0000000, 0x000000},
147 {0, 0x0000000, 0x0000000, 0x000000},
148 {0, 0x0000000, 0x0000000, 0x000000},
149 {0, 0x0000000, 0x0000000, 0x000000},
150 {0, 0x0000000, 0x0000000, 0x000000},
151 {1, 0x08f0000, 0x08f2000, 0x172000} } },
152 {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/
153 {0, 0x0000000, 0x0000000, 0x000000},
154 {0, 0x0000000, 0x0000000, 0x000000},
155 {0, 0x0000000, 0x0000000, 0x000000},
156 {0, 0x0000000, 0x0000000, 0x000000},
157 {0, 0x0000000, 0x0000000, 0x000000},
158 {0, 0x0000000, 0x0000000, 0x000000},
159 {0, 0x0000000, 0x0000000, 0x000000},
160 {0, 0x0000000, 0x0000000, 0x000000},
161 {0, 0x0000000, 0x0000000, 0x000000},
162 {0, 0x0000000, 0x0000000, 0x000000},
163 {0, 0x0000000, 0x0000000, 0x000000},
164 {0, 0x0000000, 0x0000000, 0x000000},
165 {0, 0x0000000, 0x0000000, 0x000000},
166 {0, 0x0000000, 0x0000000, 0x000000},
167 {1, 0x09f0000, 0x09f2000, 0x176000} } },
168 {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/
169 {0, 0x0000000, 0x0000000, 0x000000},
170 {0, 0x0000000, 0x0000000, 0x000000},
171 {0, 0x0000000, 0x0000000, 0x000000},
172 {0, 0x0000000, 0x0000000, 0x000000},
173 {0, 0x0000000, 0x0000000, 0x000000},
174 {0, 0x0000000, 0x0000000, 0x000000},
175 {0, 0x0000000, 0x0000000, 0x000000},
176 {0, 0x0000000, 0x0000000, 0x000000},
177 {0, 0x0000000, 0x0000000, 0x000000},
178 {0, 0x0000000, 0x0000000, 0x000000},
179 {0, 0x0000000, 0x0000000, 0x000000},
180 {0, 0x0000000, 0x0000000, 0x000000},
181 {0, 0x0000000, 0x0000000, 0x000000},
182 {0, 0x0000000, 0x0000000, 0x000000},
183 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
184 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/
185 {0, 0x0000000, 0x0000000, 0x000000},
186 {0, 0x0000000, 0x0000000, 0x000000},
187 {0, 0x0000000, 0x0000000, 0x000000},
188 {0, 0x0000000, 0x0000000, 0x000000},
189 {0, 0x0000000, 0x0000000, 0x000000},
190 {0, 0x0000000, 0x0000000, 0x000000},
191 {0, 0x0000000, 0x0000000, 0x000000},
192 {0, 0x0000000, 0x0000000, 0x000000},
193 {0, 0x0000000, 0x0000000, 0x000000},
194 {0, 0x0000000, 0x0000000, 0x000000},
195 {0, 0x0000000, 0x0000000, 0x000000},
196 {0, 0x0000000, 0x0000000, 0x000000},
197 {0, 0x0000000, 0x0000000, 0x000000},
198 {0, 0x0000000, 0x0000000, 0x000000},
199 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
200 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
201 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
202 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
203 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
204 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
205 {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
206 {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
207 {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
208 {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
209 {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
210 {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
211 {{{0, 0, 0, 0} } }, /* 23: */
212 {{{0, 0, 0, 0} } }, /* 24: */
213 {{{0, 0, 0, 0} } }, /* 25: */
214 {{{0, 0, 0, 0} } }, /* 26: */
215 {{{0, 0, 0, 0} } }, /* 27: */
216 {{{0, 0, 0, 0} } }, /* 28: */
217 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
218 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
219 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
220 {{{0} } }, /* 32: PCI */
221 {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */
222 {1, 0x2110000, 0x2120000, 0x130000},
223 {1, 0x2120000, 0x2122000, 0x124000},
224 {1, 0x2130000, 0x2132000, 0x126000},
225 {1, 0x2140000, 0x2142000, 0x128000},
226 {1, 0x2150000, 0x2152000, 0x12a000},
227 {1, 0x2160000, 0x2170000, 0x110000},
228 {1, 0x2170000, 0x2172000, 0x12e000},
229 {0, 0x0000000, 0x0000000, 0x000000},
230 {0, 0x0000000, 0x0000000, 0x000000},
231 {0, 0x0000000, 0x0000000, 0x000000},
232 {0, 0x0000000, 0x0000000, 0x000000},
233 {0, 0x0000000, 0x0000000, 0x000000},
234 {0, 0x0000000, 0x0000000, 0x000000},
235 {0, 0x0000000, 0x0000000, 0x000000},
236 {0, 0x0000000, 0x0000000, 0x000000} } },
237 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
243 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
244 {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
245 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
246 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
247 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
248 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
249 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
250 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
251 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
252 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
253 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
254 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
256 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
257 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
258 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
259 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
260 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
261 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
262 {{{0} } }, /* 59: I2C0 */
263 {{{0} } }, /* 60: I2C1 */
264 {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } },/* 61: LPC */
265 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
266 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */
270 * top 12 bits of crb internal address (hub, agent)
272 static unsigned qla4_82xx_crb_hub_agt[64] = {
274 QLA82XX_HW_CRB_HUB_AGT_ADR_PS,
275 QLA82XX_HW_CRB_HUB_AGT_ADR_MN,
276 QLA82XX_HW_CRB_HUB_AGT_ADR_MS,
278 QLA82XX_HW_CRB_HUB_AGT_ADR_SRE,
279 QLA82XX_HW_CRB_HUB_AGT_ADR_NIU,
280 QLA82XX_HW_CRB_HUB_AGT_ADR_QMN,
281 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0,
282 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1,
283 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2,
284 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3,
285 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q,
286 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR,
287 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB,
288 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4,
289 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA,
290 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0,
291 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1,
292 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2,
293 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3,
294 QLA82XX_HW_CRB_HUB_AGT_ADR_PGND,
295 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI,
296 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0,
297 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1,
298 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2,
299 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3,
301 QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI,
302 QLA82XX_HW_CRB_HUB_AGT_ADR_SN,
304 QLA82XX_HW_CRB_HUB_AGT_ADR_EG,
306 QLA82XX_HW_CRB_HUB_AGT_ADR_PS,
307 QLA82XX_HW_CRB_HUB_AGT_ADR_CAM,
313 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR,
315 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1,
316 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2,
317 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3,
318 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4,
319 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5,
320 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6,
321 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7,
322 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA,
323 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q,
324 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB,
326 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0,
327 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8,
328 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9,
329 QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0,
331 QLA82XX_HW_CRB_HUB_AGT_ADR_SMB,
332 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0,
333 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1,
335 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC,
340 static char *qdev_state[] = {
352 * In: 'off' is offset from CRB space in 128M pci map
353 * Out: 'off' is 2M pci map addr
354 * side effect: lock crb window
357 qla4_82xx_pci_set_crbwindow_2M(struct scsi_qla_host *ha, ulong *off)
361 ha->crb_win = CRB_HI(*off);
363 (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
365 /* Read back value to make sure write has gone through before trying
367 win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
368 if (win_read != ha->crb_win) {
369 DEBUG2(ql4_printk(KERN_INFO, ha,
370 "%s: Written crbwin (0x%x) != Read crbwin (0x%x),"
371 " off=0x%lx\n", __func__, ha->crb_win, win_read, *off));
373 *off = (*off & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase;
377 qla4_82xx_wr_32(struct scsi_qla_host *ha, ulong off, u32 data)
379 unsigned long flags = 0;
382 rv = qla4_82xx_pci_get_crb_addr_2M(ha, &off);
387 write_lock_irqsave(&ha->hw_lock, flags);
388 qla4_82xx_crb_win_lock(ha);
389 qla4_82xx_pci_set_crbwindow_2M(ha, &off);
392 writel(data, (void __iomem *)off);
395 qla4_82xx_crb_win_unlock(ha);
396 write_unlock_irqrestore(&ha->hw_lock, flags);
400 uint32_t qla4_82xx_rd_32(struct scsi_qla_host *ha, ulong off)
402 unsigned long flags = 0;
406 rv = qla4_82xx_pci_get_crb_addr_2M(ha, &off);
411 write_lock_irqsave(&ha->hw_lock, flags);
412 qla4_82xx_crb_win_lock(ha);
413 qla4_82xx_pci_set_crbwindow_2M(ha, &off);
415 data = readl((void __iomem *)off);
418 qla4_82xx_crb_win_unlock(ha);
419 write_unlock_irqrestore(&ha->hw_lock, flags);
424 /* Minidump related functions */
425 int qla4_82xx_md_rd_32(struct scsi_qla_host *ha, uint32_t off, uint32_t *data)
427 uint32_t win_read, off_value;
428 int rval = QLA_SUCCESS;
430 off_value = off & 0xFFFF0000;
431 writel(off_value, (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
434 * Read back value to make sure write has gone through before trying
437 win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
438 if (win_read != off_value) {
439 DEBUG2(ql4_printk(KERN_INFO, ha,
440 "%s: Written (0x%x) != Read (0x%x), off=0x%x\n",
441 __func__, off_value, win_read, off));
444 off_value = off & 0x0000FFFF;
445 *data = readl((void __iomem *)(off_value + CRB_INDIRECT_2M +
451 int qla4_82xx_md_wr_32(struct scsi_qla_host *ha, uint32_t off, uint32_t data)
453 uint32_t win_read, off_value;
454 int rval = QLA_SUCCESS;
456 off_value = off & 0xFFFF0000;
457 writel(off_value, (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
459 /* Read back value to make sure write has gone through before trying
462 win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
463 if (win_read != off_value) {
464 DEBUG2(ql4_printk(KERN_INFO, ha,
465 "%s: Written (0x%x) != Read (0x%x), off=0x%x\n",
466 __func__, off_value, win_read, off));
469 off_value = off & 0x0000FFFF;
470 writel(data, (void __iomem *)(off_value + CRB_INDIRECT_2M +
476 #define CRB_WIN_LOCK_TIMEOUT 100000000
478 int qla4_82xx_crb_win_lock(struct scsi_qla_host *ha)
481 int done = 0, timeout = 0;
484 /* acquire semaphore3 from PCI HW block */
485 done = qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK));
488 if (timeout >= CRB_WIN_LOCK_TIMEOUT)
497 for (i = 0; i < 20; i++)
498 cpu_relax(); /*This a nop instr on i386*/
501 qla4_82xx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->func_num);
505 void qla4_82xx_crb_win_unlock(struct scsi_qla_host *ha)
507 qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK));
510 #define IDC_LOCK_TIMEOUT 100000000
513 * qla4_82xx_idc_lock - hw_lock
514 * @ha: pointer to adapter structure
516 * General purpose lock used to synchronize access to
517 * CRB_DEV_STATE, CRB_DEV_REF_COUNT, etc.
519 int qla4_82xx_idc_lock(struct scsi_qla_host *ha)
522 int done = 0, timeout = 0;
525 /* acquire semaphore5 from PCI HW block */
526 done = qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK));
529 if (timeout >= IDC_LOCK_TIMEOUT)
538 for (i = 0; i < 20; i++)
539 cpu_relax(); /*This a nop instr on i386*/
545 void qla4_82xx_idc_unlock(struct scsi_qla_host *ha)
547 qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK));
551 qla4_82xx_pci_get_crb_addr_2M(struct scsi_qla_host *ha, ulong *off)
553 struct crb_128M_2M_sub_block_map *m;
555 if (*off >= QLA82XX_CRB_MAX)
558 if (*off >= QLA82XX_PCI_CAMQM && (*off < QLA82XX_PCI_CAMQM_2M_END)) {
559 *off = (*off - QLA82XX_PCI_CAMQM) +
560 QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase;
564 if (*off < QLA82XX_PCI_CRBSPACE)
567 *off -= QLA82XX_PCI_CRBSPACE;
572 m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)];
574 if (m->valid && (m->start_128M <= *off) && (m->end_128M > *off)) {
575 *off = *off + m->start_2M - m->start_128M + ha->nx_pcibase;
580 * Not in direct map, use crb window
586 * check memory access boundary.
587 * used by test agent. support ddr access only for now
590 qla4_82xx_pci_mem_bound_check(struct scsi_qla_host *ha,
591 unsigned long long addr, int size)
593 if (!QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_DDR_NET,
594 QLA8XXX_ADDR_DDR_NET_MAX) ||
595 !QLA8XXX_ADDR_IN_RANGE(addr + size - 1,
596 QLA8XXX_ADDR_DDR_NET, QLA8XXX_ADDR_DDR_NET_MAX) ||
597 ((size != 1) && (size != 2) && (size != 4) && (size != 8))) {
603 static int qla4_82xx_pci_set_window_warning_count;
606 qla4_82xx_pci_set_window(struct scsi_qla_host *ha, unsigned long long addr)
611 if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_DDR_NET,
612 QLA8XXX_ADDR_DDR_NET_MAX)) {
613 /* DDR network side */
614 window = MN_WIN(addr);
615 ha->ddr_mn_window = window;
616 qla4_82xx_wr_32(ha, ha->mn_win_crb |
617 QLA82XX_PCI_CRBSPACE, window);
618 win_read = qla4_82xx_rd_32(ha, ha->mn_win_crb |
619 QLA82XX_PCI_CRBSPACE);
620 if ((win_read << 17) != window) {
621 ql4_printk(KERN_WARNING, ha,
622 "%s: Written MNwin (0x%x) != Read MNwin (0x%x)\n",
623 __func__, window, win_read);
625 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET;
626 } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_OCM0,
627 QLA8XXX_ADDR_OCM0_MAX)) {
629 /* if bits 19:18&17:11 are on */
630 if ((addr & 0x00ff800) == 0xff800) {
631 printk("%s: QM access not handled.\n", __func__);
635 window = OCM_WIN(addr);
636 ha->ddr_mn_window = window;
637 qla4_82xx_wr_32(ha, ha->mn_win_crb |
638 QLA82XX_PCI_CRBSPACE, window);
639 win_read = qla4_82xx_rd_32(ha, ha->mn_win_crb |
640 QLA82XX_PCI_CRBSPACE);
641 temp1 = ((window & 0x1FF) << 7) |
642 ((window & 0x0FFFE0000) >> 17);
643 if (win_read != temp1) {
644 printk("%s: Written OCMwin (0x%x) != Read"
645 " OCMwin (0x%x)\n", __func__, temp1, win_read);
647 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M;
649 } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_QDR_NET,
650 QLA82XX_P3_ADDR_QDR_NET_MAX)) {
651 /* QDR network side */
652 window = MS_WIN(addr);
653 ha->qdr_sn_window = window;
654 qla4_82xx_wr_32(ha, ha->ms_win_crb |
655 QLA82XX_PCI_CRBSPACE, window);
656 win_read = qla4_82xx_rd_32(ha,
657 ha->ms_win_crb | QLA82XX_PCI_CRBSPACE);
658 if (win_read != window) {
659 printk("%s: Written MSwin (0x%x) != Read "
660 "MSwin (0x%x)\n", __func__, window, win_read);
662 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_QDR_NET;
666 * peg gdb frequently accesses memory that doesn't exist,
667 * this limits the chit chat so debugging isn't slowed down.
669 if ((qla4_82xx_pci_set_window_warning_count++ < 8) ||
670 (qla4_82xx_pci_set_window_warning_count%64 == 0)) {
671 printk("%s: Warning:%s Unknown address range!\n",
672 __func__, DRIVER_NAME);
679 /* check if address is in the same windows as the previous access */
680 static int qla4_82xx_pci_is_same_window(struct scsi_qla_host *ha,
681 unsigned long long addr)
684 unsigned long long qdr_max;
686 qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX;
688 if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_DDR_NET,
689 QLA8XXX_ADDR_DDR_NET_MAX)) {
690 /* DDR network side */
691 BUG(); /* MN access can not come here */
692 } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_OCM0,
693 QLA8XXX_ADDR_OCM0_MAX)) {
695 } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_OCM1,
696 QLA8XXX_ADDR_OCM1_MAX)) {
698 } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_QDR_NET,
700 /* QDR network side */
701 window = ((addr - QLA8XXX_ADDR_QDR_NET) >> 22) & 0x3f;
702 if (ha->qdr_sn_window == window)
709 static int qla4_82xx_pci_mem_read_direct(struct scsi_qla_host *ha,
710 u64 off, void *data, int size)
716 void __iomem *mem_ptr = NULL;
717 unsigned long mem_base;
718 unsigned long mem_page;
720 write_lock_irqsave(&ha->hw_lock, flags);
723 * If attempting to access unknown address or straddle hw windows,
726 start = qla4_82xx_pci_set_window(ha, off);
727 if ((start == -1UL) ||
728 (qla4_82xx_pci_is_same_window(ha, off + size - 1) == 0)) {
729 write_unlock_irqrestore(&ha->hw_lock, flags);
730 printk(KERN_ERR"%s out of bound pci memory access. "
731 "offset is 0x%llx\n", DRIVER_NAME, off);
735 addr = qla4_8xxx_pci_base_offsetfset(ha, start);
737 write_unlock_irqrestore(&ha->hw_lock, flags);
738 mem_base = pci_resource_start(ha->pdev, 0);
739 mem_page = start & PAGE_MASK;
740 /* Map two pages whenever user tries to access addresses in two
743 if (mem_page != ((start + size - 1) & PAGE_MASK))
744 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2);
746 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
748 if (mem_ptr == NULL) {
753 addr += start & (PAGE_SIZE - 1);
754 write_lock_irqsave(&ha->hw_lock, flags);
759 *(u8 *)data = readb(addr);
762 *(u16 *)data = readw(addr);
765 *(u32 *)data = readl(addr);
768 *(u64 *)data = readq(addr);
774 write_unlock_irqrestore(&ha->hw_lock, flags);
782 qla4_82xx_pci_mem_write_direct(struct scsi_qla_host *ha, u64 off,
783 void *data, int size)
789 void __iomem *mem_ptr = NULL;
790 unsigned long mem_base;
791 unsigned long mem_page;
793 write_lock_irqsave(&ha->hw_lock, flags);
796 * If attempting to access unknown address or straddle hw windows,
799 start = qla4_82xx_pci_set_window(ha, off);
800 if ((start == -1UL) ||
801 (qla4_82xx_pci_is_same_window(ha, off + size - 1) == 0)) {
802 write_unlock_irqrestore(&ha->hw_lock, flags);
803 printk(KERN_ERR"%s out of bound pci memory access. "
804 "offset is 0x%llx\n", DRIVER_NAME, off);
808 addr = qla4_8xxx_pci_base_offsetfset(ha, start);
810 write_unlock_irqrestore(&ha->hw_lock, flags);
811 mem_base = pci_resource_start(ha->pdev, 0);
812 mem_page = start & PAGE_MASK;
813 /* Map two pages whenever user tries to access addresses in two
816 if (mem_page != ((start + size - 1) & PAGE_MASK))
817 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2);
819 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
824 addr += start & (PAGE_SIZE - 1);
825 write_lock_irqsave(&ha->hw_lock, flags);
830 writeb(*(u8 *)data, addr);
833 writew(*(u16 *)data, addr);
836 writel(*(u32 *)data, addr);
839 writeq(*(u64 *)data, addr);
845 write_unlock_irqrestore(&ha->hw_lock, flags);
851 #define MTU_FUDGE_FACTOR 100
854 qla4_82xx_decode_crb_addr(unsigned long addr)
857 unsigned long base_addr, offset, pci_base;
859 if (!qla4_8xxx_crb_table_initialized)
860 qla4_82xx_crb_addr_transform_setup();
862 pci_base = ADDR_ERROR;
863 base_addr = addr & 0xfff00000;
864 offset = addr & 0x000fffff;
866 for (i = 0; i < MAX_CRB_XFORM; i++) {
867 if (crb_addr_xform[i] == base_addr) {
872 if (pci_base == ADDR_ERROR)
875 return pci_base + offset;
878 static long rom_max_timeout = 100;
879 static long qla4_82xx_rom_lock_timeout = 100;
882 qla4_82xx_rom_lock(struct scsi_qla_host *ha)
885 int done = 0, timeout = 0;
888 /* acquire semaphore2 from PCI HW block */
890 done = qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK));
893 if (timeout >= qla4_82xx_rom_lock_timeout)
902 for (i = 0; i < 20; i++)
903 cpu_relax(); /*This a nop instr on i386*/
906 qla4_82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ROM_LOCK_DRIVER);
911 qla4_82xx_rom_unlock(struct scsi_qla_host *ha)
913 qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK));
917 qla4_82xx_wait_rom_done(struct scsi_qla_host *ha)
923 done = qla4_82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS);
926 if (timeout >= rom_max_timeout) {
927 printk("%s: Timeout reached waiting for rom done",
936 qla4_82xx_do_rom_fast_read(struct scsi_qla_host *ha, int addr, int *valp)
938 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr);
939 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
940 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3);
941 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0xb);
942 if (qla4_82xx_wait_rom_done(ha)) {
943 printk("%s: Error waiting for rom done\n", DRIVER_NAME);
946 /* reset abyte_cnt and dummy_byte_cnt */
947 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
949 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0);
951 *valp = qla4_82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA);
956 qla4_82xx_rom_fast_read(struct scsi_qla_host *ha, int addr, int *valp)
960 while ((qla4_82xx_rom_lock(ha) != 0) && (loops < 50000)) {
964 if (loops >= 50000) {
965 ql4_printk(KERN_WARNING, ha, "%s: qla4_82xx_rom_lock failed\n",
969 ret = qla4_82xx_do_rom_fast_read(ha, addr, valp);
970 qla4_82xx_rom_unlock(ha);
975 * This routine does CRB initialize sequence
976 * to put the ISP into operational state
979 qla4_82xx_pinit_from_rom(struct scsi_qla_host *ha, int verbose)
983 struct crb_addr_pair *buf;
987 struct crb_addr_pair {
992 /* Halt all the indiviual PEGs and other blocks of the ISP */
993 qla4_82xx_rom_lock(ha);
995 /* disable all I2Q */
996 qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x10, 0x0);
997 qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x14, 0x0);
998 qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x18, 0x0);
999 qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x1c, 0x0);
1000 qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x20, 0x0);
1001 qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x24, 0x0);
1003 /* disable all niu interrupts */
1004 qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x40, 0xff);
1005 /* disable xge rx/tx */
1006 qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x70000, 0x00);
1007 /* disable xg1 rx/tx */
1008 qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x80000, 0x00);
1009 /* disable sideband mac */
1010 qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x90000, 0x00);
1011 /* disable ap0 mac */
1012 qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xa0000, 0x00);
1013 /* disable ap1 mac */
1014 qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xb0000, 0x00);
1017 val = qla4_82xx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000);
1018 qla4_82xx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1)));
1021 qla4_82xx_wr_32(ha, QLA82XX_CRB_EPG + 0x1300, 0x1);
1024 qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x0, 0x0);
1025 qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x8, 0x0);
1026 qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x10, 0x0);
1027 qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x18, 0x0);
1028 qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x100, 0x0);
1029 qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x200, 0x0);
1032 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c, 1);
1033 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c, 1);
1034 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c, 1);
1035 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c, 1);
1036 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c, 1);
1040 if (test_bit(DPC_RESET_HA, &ha->dpc_flags))
1041 /* don't reset CAM block on reset */
1042 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff);
1044 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff);
1046 qla4_82xx_rom_unlock(ha);
1048 /* Read the signature value from the flash.
1049 * Offset 0: Contain signature (0xcafecafe)
1050 * Offset 4: Offset and number of addr/value pairs
1051 * that present in CRB initialize sequence
1053 if (qla4_82xx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL ||
1054 qla4_82xx_rom_fast_read(ha, 4, &n) != 0) {
1055 ql4_printk(KERN_WARNING, ha,
1056 "[ERROR] Reading crb_init area: n: %08x\n", n);
1060 /* Offset in flash = lower 16 bits
1061 * Number of enteries = upper 16 bits
1063 offset = n & 0xffffU;
1064 n = (n >> 16) & 0xffffU;
1066 /* number of addr/value pair should not exceed 1024 enteries */
1068 ql4_printk(KERN_WARNING, ha,
1069 "%s: %s:n=0x%x [ERROR] Card flash not initialized.\n",
1070 DRIVER_NAME, __func__, n);
1074 ql4_printk(KERN_INFO, ha,
1075 "%s: %d CRB init values found in ROM.\n", DRIVER_NAME, n);
1077 buf = kmalloc(n * sizeof(struct crb_addr_pair), GFP_KERNEL);
1079 ql4_printk(KERN_WARNING, ha,
1080 "%s: [ERROR] Unable to malloc memory.\n", DRIVER_NAME);
1084 for (i = 0; i < n; i++) {
1085 if (qla4_82xx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 ||
1086 qla4_82xx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) !=
1096 for (i = 0; i < n; i++) {
1097 /* Translate internal CRB initialization
1098 * address to PCI bus address
1100 off = qla4_82xx_decode_crb_addr((unsigned long)buf[i].addr) +
1101 QLA82XX_PCI_CRBSPACE;
1102 /* Not all CRB addr/value pair to be written,
1103 * some of them are skipped
1106 /* skip if LS bit is set*/
1108 DEBUG2(ql4_printk(KERN_WARNING, ha,
1109 "Skip CRB init replay for offset = 0x%lx\n", off));
1113 /* skipping cold reboot MAGIC */
1114 if (off == QLA82XX_CAM_RAM(0x1fc))
1117 /* do not reset PCI */
1118 if (off == (ROMUSB_GLB + 0xbc))
1121 /* skip core clock, so that firmware can increase the clock */
1122 if (off == (ROMUSB_GLB + 0xc8))
1125 /* skip the function enable register */
1126 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION))
1129 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION2))
1132 if ((off & 0x0ff00000) == QLA82XX_CRB_SMB)
1135 if ((off & 0x0ff00000) == QLA82XX_CRB_DDR_NET)
1138 if (off == ADDR_ERROR) {
1139 ql4_printk(KERN_WARNING, ha,
1140 "%s: [ERROR] Unknown addr: 0x%08lx\n",
1141 DRIVER_NAME, buf[i].addr);
1145 qla4_82xx_wr_32(ha, off, buf[i].data);
1147 /* ISP requires much bigger delay to settle down,
1148 * else crb_window returns 0xffffffff
1150 if (off == QLA82XX_ROMUSB_GLB_SW_RESET)
1153 /* ISP requires millisec delay between
1154 * successive CRB register updation
1161 /* Resetting the data and instruction cache */
1162 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e);
1163 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8);
1164 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8);
1166 /* Clear all protocol processing engines */
1167 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0);
1168 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0);
1169 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0);
1170 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0);
1171 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0);
1172 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0);
1173 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0);
1174 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0);
1180 qla4_82xx_load_from_flash(struct scsi_qla_host *ha, uint32_t image_start)
1184 long flashaddr, memaddr;
1188 flashaddr = memaddr = ha->hw.flt_region_bootload;
1189 size = (image_start - flashaddr) / 8;
1191 DEBUG2(printk("scsi%ld: %s: bootldr=0x%lx, fw_image=0x%x\n",
1192 ha->host_no, __func__, flashaddr, image_start));
1194 for (i = 0; i < size; i++) {
1195 if ((qla4_82xx_rom_fast_read(ha, flashaddr, (int *)&low)) ||
1196 (qla4_82xx_rom_fast_read(ha, flashaddr + 4,
1199 goto exit_load_from_flash;
1201 data = ((u64)high << 32) | low ;
1202 rval = qla4_82xx_pci_mem_write_2M(ha, memaddr, &data, 8);
1204 goto exit_load_from_flash;
1209 if (i % 0x1000 == 0)
1216 read_lock(&ha->hw_lock);
1217 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020);
1218 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e);
1219 read_unlock(&ha->hw_lock);
1221 exit_load_from_flash:
1225 static int qla4_82xx_load_fw(struct scsi_qla_host *ha, uint32_t image_start)
1229 qla4_82xx_wr_32(ha, CRB_CMDPEG_STATE, 0);
1230 if (qla4_82xx_pinit_from_rom(ha, 0) != QLA_SUCCESS) {
1231 printk(KERN_WARNING "%s: Error during CRB Initialization\n",
1238 /* at this point, QM is in reset. This could be a problem if there are
1239 * incoming d* transition queue messages. QM/PCIE could wedge.
1240 * To get around this, QM is brought out of reset.
1243 rst = qla4_82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET);
1246 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst);
1248 if (qla4_82xx_load_from_flash(ha, image_start)) {
1249 printk("%s: Error trying to load fw from flash!\n", __func__);
1257 qla4_82xx_pci_mem_read_2M(struct scsi_qla_host *ha,
1258 u64 off, void *data, int size)
1260 int i, j = 0, k, start, end, loop, sz[2], off0[2];
1263 uint64_t off8, val, mem_crb, word[2] = {0, 0};
1266 * If not MN, go check for MS or invalid.
1269 if (off >= QLA8XXX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
1270 mem_crb = QLA82XX_CRB_QDR_NET;
1272 mem_crb = QLA82XX_CRB_DDR_NET;
1273 if (qla4_82xx_pci_mem_bound_check(ha, off, size) == 0)
1274 return qla4_82xx_pci_mem_read_direct(ha,
1279 off8 = off & 0xfffffff0;
1280 off0[0] = off & 0xf;
1281 sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]);
1284 loop = ((off0[0] + size - 1) >> shift_amount) + 1;
1286 sz[1] = size - sz[0];
1288 for (i = 0; i < loop; i++) {
1289 temp = off8 + (i << shift_amount);
1290 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp);
1292 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp);
1293 temp = MIU_TA_CTL_ENABLE;
1294 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1295 temp = MIU_TA_CTL_START_ENABLE;
1296 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1298 for (j = 0; j < MAX_CTL_CHECK; j++) {
1299 temp = qla4_82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
1300 if ((temp & MIU_TA_CTL_BUSY) == 0)
1304 if (j >= MAX_CTL_CHECK) {
1305 printk_ratelimited(KERN_ERR
1306 "%s: failed to read through agent\n",
1311 start = off0[i] >> 2;
1312 end = (off0[i] + sz[i] - 1) >> 2;
1313 for (k = start; k <= end; k++) {
1314 temp = qla4_82xx_rd_32(ha,
1315 mem_crb + MIU_TEST_AGT_RDDATA(k));
1316 word[i] |= ((uint64_t)temp << (32 * (k & 1)));
1320 if (j >= MAX_CTL_CHECK)
1323 if ((off0[0] & 7) == 0) {
1326 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1327 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1332 *(uint8_t *)data = val;
1335 *(uint16_t *)data = val;
1338 *(uint32_t *)data = val;
1341 *(uint64_t *)data = val;
1348 qla4_82xx_pci_mem_write_2M(struct scsi_qla_host *ha,
1349 u64 off, void *data, int size)
1351 int i, j, ret = 0, loop, sz[2], off0;
1352 int scale, shift_amount, startword;
1354 uint64_t off8, mem_crb, tmpw, word[2] = {0, 0};
1357 * If not MN, go check for MS or invalid.
1359 if (off >= QLA8XXX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
1360 mem_crb = QLA82XX_CRB_QDR_NET;
1362 mem_crb = QLA82XX_CRB_DDR_NET;
1363 if (qla4_82xx_pci_mem_bound_check(ha, off, size) == 0)
1364 return qla4_82xx_pci_mem_write_direct(ha,
1369 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1370 sz[1] = size - sz[0];
1372 off8 = off & 0xfffffff0;
1373 loop = (((off & 0xf) + size - 1) >> 4) + 1;
1376 startword = (off & 0xf)/8;
1378 for (i = 0; i < loop; i++) {
1379 if (qla4_82xx_pci_mem_read_2M(ha, off8 +
1380 (i << shift_amount), &word[i * scale], 8))
1386 tmpw = *((uint8_t *)data);
1389 tmpw = *((uint16_t *)data);
1392 tmpw = *((uint32_t *)data);
1396 tmpw = *((uint64_t *)data);
1401 word[startword] = tmpw;
1404 ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1405 word[startword] |= tmpw << (off0 * 8);
1409 word[startword+1] &= ~(~0ULL << (sz[1] * 8));
1410 word[startword+1] |= tmpw >> (sz[0] * 8);
1413 for (i = 0; i < loop; i++) {
1414 temp = off8 + (i << shift_amount);
1415 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp);
1417 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp);
1418 temp = word[i * scale] & 0xffffffff;
1419 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp);
1420 temp = (word[i * scale] >> 32) & 0xffffffff;
1421 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp);
1422 temp = word[i*scale + 1] & 0xffffffff;
1423 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_WRDATA_UPPER_LO,
1425 temp = (word[i*scale + 1] >> 32) & 0xffffffff;
1426 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_WRDATA_UPPER_HI,
1429 temp = MIU_TA_CTL_WRITE_ENABLE;
1430 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp);
1431 temp = MIU_TA_CTL_WRITE_START;
1432 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp);
1434 for (j = 0; j < MAX_CTL_CHECK; j++) {
1435 temp = qla4_82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
1436 if ((temp & MIU_TA_CTL_BUSY) == 0)
1440 if (j >= MAX_CTL_CHECK) {
1441 if (printk_ratelimit())
1442 ql4_printk(KERN_ERR, ha,
1443 "%s: failed to read through agent\n",
1453 static int qla4_82xx_cmdpeg_ready(struct scsi_qla_host *ha, int pegtune_val)
1460 val = qla4_82xx_rd_32(ha, CRB_CMDPEG_STATE);
1461 if ((val == PHAN_INITIALIZE_COMPLETE) ||
1462 (val == PHAN_INITIALIZE_ACK))
1464 set_current_state(TASK_UNINTERRUPTIBLE);
1465 schedule_timeout(500);
1467 } while (--retries);
1470 pegtune_val = qla4_82xx_rd_32(ha,
1471 QLA82XX_ROMUSB_GLB_PEGTUNE_DONE);
1472 printk(KERN_WARNING "%s: init failed, "
1473 "pegtune_val = %x\n", __func__, pegtune_val);
1480 static int qla4_82xx_rcvpeg_ready(struct scsi_qla_host *ha)
1486 read_lock(&ha->hw_lock);
1487 state = qla4_82xx_rd_32(ha, CRB_RCVPEG_STATE);
1488 read_unlock(&ha->hw_lock);
1490 while ((state != PHAN_PEG_RCV_INITIALIZED) && (loops < 30000)) {
1493 read_lock(&ha->hw_lock);
1494 state = qla4_82xx_rd_32(ha, CRB_RCVPEG_STATE);
1495 read_unlock(&ha->hw_lock);
1500 if (loops >= 30000) {
1501 DEBUG2(ql4_printk(KERN_INFO, ha,
1502 "Receive Peg initialization not complete: 0x%x.\n", state));
1510 qla4_8xxx_set_drv_active(struct scsi_qla_host *ha)
1512 uint32_t drv_active;
1514 drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
1517 * For ISP8324 and ISP8042, drv_active register has 1 bit per function,
1518 * shift 1 by func_num to set a bit for the function.
1519 * For ISP8022, drv_active has 4 bits per function
1521 if (is_qla8032(ha) || is_qla8042(ha))
1522 drv_active |= (1 << ha->func_num);
1524 drv_active |= (1 << (ha->func_num * 4));
1526 ql4_printk(KERN_INFO, ha, "%s(%ld): drv_active: 0x%08x\n",
1527 __func__, ha->host_no, drv_active);
1528 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_ACTIVE, drv_active);
1532 qla4_8xxx_clear_drv_active(struct scsi_qla_host *ha)
1534 uint32_t drv_active;
1536 drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
1539 * For ISP8324 and ISP8042, drv_active register has 1 bit per function,
1540 * shift 1 by func_num to set a bit for the function.
1541 * For ISP8022, drv_active has 4 bits per function
1543 if (is_qla8032(ha) || is_qla8042(ha))
1544 drv_active &= ~(1 << (ha->func_num));
1546 drv_active &= ~(1 << (ha->func_num * 4));
1548 ql4_printk(KERN_INFO, ha, "%s(%ld): drv_active: 0x%08x\n",
1549 __func__, ha->host_no, drv_active);
1550 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_ACTIVE, drv_active);
1553 inline int qla4_8xxx_need_reset(struct scsi_qla_host *ha)
1555 uint32_t drv_state, drv_active;
1558 drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
1559 drv_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE);
1562 * For ISP8324 and ISP8042, drv_active register has 1 bit per function,
1563 * shift 1 by func_num to set a bit for the function.
1564 * For ISP8022, drv_active has 4 bits per function
1566 if (is_qla8032(ha) || is_qla8042(ha))
1567 rval = drv_state & (1 << ha->func_num);
1569 rval = drv_state & (1 << (ha->func_num * 4));
1571 if ((test_bit(AF_EEH_BUSY, &ha->flags)) && drv_active)
1577 void qla4_8xxx_set_rst_ready(struct scsi_qla_host *ha)
1581 drv_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE);
1584 * For ISP8324 and ISP8042, drv_active register has 1 bit per function,
1585 * shift 1 by func_num to set a bit for the function.
1586 * For ISP8022, drv_active has 4 bits per function
1588 if (is_qla8032(ha) || is_qla8042(ha))
1589 drv_state |= (1 << ha->func_num);
1591 drv_state |= (1 << (ha->func_num * 4));
1593 ql4_printk(KERN_INFO, ha, "%s(%ld): drv_state: 0x%08x\n",
1594 __func__, ha->host_no, drv_state);
1595 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_STATE, drv_state);
1598 void qla4_8xxx_clear_rst_ready(struct scsi_qla_host *ha)
1602 drv_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE);
1605 * For ISP8324 and ISP8042, drv_active register has 1 bit per function,
1606 * shift 1 by func_num to set a bit for the function.
1607 * For ISP8022, drv_active has 4 bits per function
1609 if (is_qla8032(ha) || is_qla8042(ha))
1610 drv_state &= ~(1 << ha->func_num);
1612 drv_state &= ~(1 << (ha->func_num * 4));
1614 ql4_printk(KERN_INFO, ha, "%s(%ld): drv_state: 0x%08x\n",
1615 __func__, ha->host_no, drv_state);
1616 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_STATE, drv_state);
1620 qla4_8xxx_set_qsnt_ready(struct scsi_qla_host *ha)
1622 uint32_t qsnt_state;
1624 qsnt_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE);
1627 * For ISP8324 and ISP8042, drv_active register has 1 bit per function,
1628 * shift 1 by func_num to set a bit for the function.
1629 * For ISP8022, drv_active has 4 bits per function.
1631 if (is_qla8032(ha) || is_qla8042(ha))
1632 qsnt_state |= (1 << ha->func_num);
1634 qsnt_state |= (2 << (ha->func_num * 4));
1636 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_STATE, qsnt_state);
1641 qla4_82xx_start_firmware(struct scsi_qla_host *ha, uint32_t image_start)
1645 /* scrub dma mask expansion register */
1646 qla4_82xx_wr_32(ha, CRB_DMA_SHIFT, 0x55555555);
1648 /* Overwrite stale initialization register values */
1649 qla4_82xx_wr_32(ha, CRB_CMDPEG_STATE, 0);
1650 qla4_82xx_wr_32(ha, CRB_RCVPEG_STATE, 0);
1651 qla4_82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0);
1652 qla4_82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0);
1654 if (qla4_82xx_load_fw(ha, image_start) != QLA_SUCCESS) {
1655 printk("%s: Error trying to start fw!\n", __func__);
1659 /* Handshake with the card before we register the devices. */
1660 if (qla4_82xx_cmdpeg_ready(ha, 0) != QLA_SUCCESS) {
1661 printk("%s: Error during card handshake!\n", __func__);
1665 /* Negotiated Link width */
1666 pcie_capability_read_word(ha->pdev, PCI_EXP_LNKSTA, &lnk);
1667 ha->link_width = (lnk >> 4) & 0x3f;
1669 /* Synchronize with Receive peg */
1670 return qla4_82xx_rcvpeg_ready(ha);
1673 int qla4_82xx_try_start_fw(struct scsi_qla_host *ha)
1675 int rval = QLA_ERROR;
1679 * 1) Operational firmware residing in flash.
1683 ql4_printk(KERN_INFO, ha,
1684 "FW: Retrieving flash offsets from FLT/FDT ...\n");
1685 rval = qla4_8xxx_get_flash_info(ha);
1686 if (rval != QLA_SUCCESS)
1689 ql4_printk(KERN_INFO, ha,
1690 "FW: Attempting to load firmware from flash...\n");
1691 rval = qla4_82xx_start_firmware(ha, ha->hw.flt_region_fw);
1693 if (rval != QLA_SUCCESS) {
1694 ql4_printk(KERN_ERR, ha, "FW: Load firmware from flash"
1702 void qla4_82xx_rom_lock_recovery(struct scsi_qla_host *ha)
1704 if (qla4_82xx_rom_lock(ha)) {
1705 /* Someone else is holding the lock. */
1706 dev_info(&ha->pdev->dev, "Resetting rom_lock\n");
1710 * Either we got the lock, or someone
1711 * else died while holding it.
1712 * In either case, unlock.
1714 qla4_82xx_rom_unlock(ha);
1717 static void qla4_8xxx_minidump_process_rdcrb(struct scsi_qla_host *ha,
1718 struct qla8xxx_minidump_entry_hdr *entry_hdr,
1721 uint32_t r_addr, r_stride, loop_cnt, i, r_value;
1722 struct qla8xxx_minidump_entry_crb *crb_hdr;
1723 uint32_t *data_ptr = *d_ptr;
1725 DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
1726 crb_hdr = (struct qla8xxx_minidump_entry_crb *)entry_hdr;
1727 r_addr = crb_hdr->addr;
1728 r_stride = crb_hdr->crb_strd.addr_stride;
1729 loop_cnt = crb_hdr->op_count;
1731 for (i = 0; i < loop_cnt; i++) {
1732 ha->isp_ops->rd_reg_indirect(ha, r_addr, &r_value);
1733 *data_ptr++ = cpu_to_le32(r_addr);
1734 *data_ptr++ = cpu_to_le32(r_value);
1740 static int qla4_83xx_check_dma_engine_state(struct scsi_qla_host *ha)
1742 int rval = QLA_SUCCESS;
1743 uint32_t dma_eng_num = 0, cmd_sts_and_cntrl = 0;
1744 uint64_t dma_base_addr = 0;
1745 struct qla4_8xxx_minidump_template_hdr *tmplt_hdr = NULL;
1747 tmplt_hdr = (struct qla4_8xxx_minidump_template_hdr *)
1748 ha->fw_dump_tmplt_hdr;
1750 tmplt_hdr->saved_state_array[QLA83XX_PEX_DMA_ENGINE_INDEX];
1751 dma_base_addr = QLA83XX_PEX_DMA_BASE_ADDRESS +
1752 (dma_eng_num * QLA83XX_PEX_DMA_NUM_OFFSET);
1754 /* Read the pex-dma's command-status-and-control register. */
1755 rval = ha->isp_ops->rd_reg_indirect(ha,
1756 (dma_base_addr + QLA83XX_PEX_DMA_CMD_STS_AND_CNTRL),
1757 &cmd_sts_and_cntrl);
1762 /* Check if requested pex-dma engine is available. */
1763 if (cmd_sts_and_cntrl & BIT_31)
1769 static int qla4_83xx_start_pex_dma(struct scsi_qla_host *ha,
1770 struct qla4_83xx_minidump_entry_rdmem_pex_dma *m_hdr)
1772 int rval = QLA_SUCCESS, wait = 0;
1773 uint32_t dma_eng_num = 0, cmd_sts_and_cntrl = 0;
1774 uint64_t dma_base_addr = 0;
1775 struct qla4_8xxx_minidump_template_hdr *tmplt_hdr = NULL;
1777 tmplt_hdr = (struct qla4_8xxx_minidump_template_hdr *)
1778 ha->fw_dump_tmplt_hdr;
1780 tmplt_hdr->saved_state_array[QLA83XX_PEX_DMA_ENGINE_INDEX];
1781 dma_base_addr = QLA83XX_PEX_DMA_BASE_ADDRESS +
1782 (dma_eng_num * QLA83XX_PEX_DMA_NUM_OFFSET);
1784 rval = ha->isp_ops->wr_reg_indirect(ha,
1785 dma_base_addr + QLA83XX_PEX_DMA_CMD_ADDR_LOW,
1786 m_hdr->desc_card_addr);
1790 rval = ha->isp_ops->wr_reg_indirect(ha,
1791 dma_base_addr + QLA83XX_PEX_DMA_CMD_ADDR_HIGH, 0);
1795 rval = ha->isp_ops->wr_reg_indirect(ha,
1796 dma_base_addr + QLA83XX_PEX_DMA_CMD_STS_AND_CNTRL,
1797 m_hdr->start_dma_cmd);
1801 /* Wait for dma operation to complete. */
1802 for (wait = 0; wait < QLA83XX_PEX_DMA_MAX_WAIT; wait++) {
1803 rval = ha->isp_ops->rd_reg_indirect(ha,
1804 (dma_base_addr + QLA83XX_PEX_DMA_CMD_STS_AND_CNTRL),
1805 &cmd_sts_and_cntrl);
1809 if ((cmd_sts_and_cntrl & BIT_1) == 0)
1815 /* Wait a max of 100 ms, otherwise fallback to rdmem entry read */
1816 if (wait >= QLA83XX_PEX_DMA_MAX_WAIT) {
1825 static int qla4_83xx_minidump_pex_dma_read(struct scsi_qla_host *ha,
1826 struct qla8xxx_minidump_entry_hdr *entry_hdr,
1829 int rval = QLA_SUCCESS;
1830 struct qla4_83xx_minidump_entry_rdmem_pex_dma *m_hdr = NULL;
1831 uint32_t size, read_size;
1832 uint8_t *data_ptr = (uint8_t *)*d_ptr;
1833 void *rdmem_buffer = NULL;
1834 dma_addr_t rdmem_dma;
1835 struct qla4_83xx_pex_dma_descriptor dma_desc;
1837 DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
1839 rval = qla4_83xx_check_dma_engine_state(ha);
1840 if (rval != QLA_SUCCESS) {
1841 DEBUG2(ql4_printk(KERN_INFO, ha,
1842 "%s: DMA engine not available. Fallback to rdmem-read.\n",
1847 m_hdr = (struct qla4_83xx_minidump_entry_rdmem_pex_dma *)entry_hdr;
1848 rdmem_buffer = dma_alloc_coherent(&ha->pdev->dev,
1849 QLA83XX_PEX_DMA_READ_SIZE,
1850 &rdmem_dma, GFP_KERNEL);
1851 if (!rdmem_buffer) {
1852 DEBUG2(ql4_printk(KERN_INFO, ha,
1853 "%s: Unable to allocate rdmem dma buffer\n",
1858 /* Prepare pex-dma descriptor to be written to MS memory. */
1859 /* dma-desc-cmd layout:
1860 * 0-3: dma-desc-cmd 0-3
1861 * 4-7: pcid function number
1862 * 8-15: dma-desc-cmd 8-15
1864 dma_desc.cmd.dma_desc_cmd = (m_hdr->dma_desc_cmd & 0xff0f);
1865 dma_desc.cmd.dma_desc_cmd |= ((PCI_FUNC(ha->pdev->devfn) & 0xf) << 0x4);
1866 dma_desc.dma_bus_addr = rdmem_dma;
1871 * Perform rdmem operation using pex-dma.
1872 * Prepare dma in chunks of QLA83XX_PEX_DMA_READ_SIZE.
1874 while (read_size < m_hdr->read_data_size) {
1875 if (m_hdr->read_data_size - read_size >=
1876 QLA83XX_PEX_DMA_READ_SIZE)
1877 size = QLA83XX_PEX_DMA_READ_SIZE;
1879 size = (m_hdr->read_data_size - read_size);
1882 dma_free_coherent(&ha->pdev->dev,
1883 QLA83XX_PEX_DMA_READ_SIZE,
1884 rdmem_buffer, rdmem_dma);
1886 rdmem_buffer = dma_alloc_coherent(&ha->pdev->dev, size,
1889 if (!rdmem_buffer) {
1890 DEBUG2(ql4_printk(KERN_INFO, ha,
1891 "%s: Unable to allocate rdmem dma buffer\n",
1895 dma_desc.dma_bus_addr = rdmem_dma;
1898 dma_desc.src_addr = m_hdr->read_addr + read_size;
1899 dma_desc.cmd.read_data_size = size;
1901 /* Prepare: Write pex-dma descriptor to MS memory. */
1902 rval = qla4_83xx_ms_mem_write_128b(ha,
1903 (uint64_t)m_hdr->desc_card_addr,
1904 (uint32_t *)&dma_desc,
1905 (sizeof(struct qla4_83xx_pex_dma_descriptor)/16));
1907 ql4_printk(KERN_INFO, ha,
1908 "%s: Error writing rdmem-dma-init to MS !!!\n",
1913 DEBUG2(ql4_printk(KERN_INFO, ha,
1914 "%s: Dma-desc: Instruct for rdmem dma (size 0x%x).\n",
1916 /* Execute: Start pex-dma operation. */
1917 rval = qla4_83xx_start_pex_dma(ha, m_hdr);
1918 if (rval != QLA_SUCCESS) {
1919 DEBUG2(ql4_printk(KERN_INFO, ha,
1920 "scsi(%ld): start-pex-dma failed rval=0x%x\n",
1921 ha->host_no, rval));
1925 memcpy(data_ptr, rdmem_buffer, size);
1930 DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s\n", __func__));
1932 *d_ptr = (uint32_t *)data_ptr;
1936 dma_free_coherent(&ha->pdev->dev, size, rdmem_buffer,
1942 static int qla4_8xxx_minidump_process_l2tag(struct scsi_qla_host *ha,
1943 struct qla8xxx_minidump_entry_hdr *entry_hdr,
1946 uint32_t addr, r_addr, c_addr, t_r_addr;
1947 uint32_t i, k, loop_count, t_value, r_cnt, r_value;
1948 unsigned long p_wait, w_time, p_mask;
1949 uint32_t c_value_w, c_value_r;
1950 struct qla8xxx_minidump_entry_cache *cache_hdr;
1951 int rval = QLA_ERROR;
1952 uint32_t *data_ptr = *d_ptr;
1954 DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
1955 cache_hdr = (struct qla8xxx_minidump_entry_cache *)entry_hdr;
1957 loop_count = cache_hdr->op_count;
1958 r_addr = cache_hdr->read_addr;
1959 c_addr = cache_hdr->control_addr;
1960 c_value_w = cache_hdr->cache_ctrl.write_value;
1962 t_r_addr = cache_hdr->tag_reg_addr;
1963 t_value = cache_hdr->addr_ctrl.init_tag_value;
1964 r_cnt = cache_hdr->read_ctrl.read_addr_cnt;
1965 p_wait = cache_hdr->cache_ctrl.poll_wait;
1966 p_mask = cache_hdr->cache_ctrl.poll_mask;
1968 for (i = 0; i < loop_count; i++) {
1969 ha->isp_ops->wr_reg_indirect(ha, t_r_addr, t_value);
1972 ha->isp_ops->wr_reg_indirect(ha, c_addr, c_value_w);
1975 w_time = jiffies + p_wait;
1977 ha->isp_ops->rd_reg_indirect(ha, c_addr,
1979 if ((c_value_r & p_mask) == 0) {
1981 } else if (time_after_eq(jiffies, w_time)) {
1982 /* capturing dump failed */
1989 for (k = 0; k < r_cnt; k++) {
1990 ha->isp_ops->rd_reg_indirect(ha, addr, &r_value);
1991 *data_ptr++ = cpu_to_le32(r_value);
1992 addr += cache_hdr->read_ctrl.read_addr_stride;
1995 t_value += cache_hdr->addr_ctrl.tag_value_stride;
2001 static int qla4_8xxx_minidump_process_control(struct scsi_qla_host *ha,
2002 struct qla8xxx_minidump_entry_hdr *entry_hdr)
2004 struct qla8xxx_minidump_entry_crb *crb_entry;
2005 uint32_t read_value, opcode, poll_time, addr, index, rval = QLA_SUCCESS;
2007 unsigned long wtime;
2008 struct qla4_8xxx_minidump_template_hdr *tmplt_hdr;
2011 DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
2012 tmplt_hdr = (struct qla4_8xxx_minidump_template_hdr *)
2013 ha->fw_dump_tmplt_hdr;
2014 crb_entry = (struct qla8xxx_minidump_entry_crb *)entry_hdr;
2016 crb_addr = crb_entry->addr;
2017 for (i = 0; i < crb_entry->op_count; i++) {
2018 opcode = crb_entry->crb_ctrl.opcode;
2019 if (opcode & QLA8XXX_DBG_OPCODE_WR) {
2020 ha->isp_ops->wr_reg_indirect(ha, crb_addr,
2021 crb_entry->value_1);
2022 opcode &= ~QLA8XXX_DBG_OPCODE_WR;
2024 if (opcode & QLA8XXX_DBG_OPCODE_RW) {
2025 ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value);
2026 ha->isp_ops->wr_reg_indirect(ha, crb_addr, read_value);
2027 opcode &= ~QLA8XXX_DBG_OPCODE_RW;
2029 if (opcode & QLA8XXX_DBG_OPCODE_AND) {
2030 ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value);
2031 read_value &= crb_entry->value_2;
2032 opcode &= ~QLA8XXX_DBG_OPCODE_AND;
2033 if (opcode & QLA8XXX_DBG_OPCODE_OR) {
2034 read_value |= crb_entry->value_3;
2035 opcode &= ~QLA8XXX_DBG_OPCODE_OR;
2037 ha->isp_ops->wr_reg_indirect(ha, crb_addr, read_value);
2039 if (opcode & QLA8XXX_DBG_OPCODE_OR) {
2040 ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value);
2041 read_value |= crb_entry->value_3;
2042 ha->isp_ops->wr_reg_indirect(ha, crb_addr, read_value);
2043 opcode &= ~QLA8XXX_DBG_OPCODE_OR;
2045 if (opcode & QLA8XXX_DBG_OPCODE_POLL) {
2046 poll_time = crb_entry->crb_strd.poll_timeout;
2047 wtime = jiffies + poll_time;
2048 ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value);
2051 if ((read_value & crb_entry->value_2) ==
2052 crb_entry->value_1) {
2054 } else if (time_after_eq(jiffies, wtime)) {
2055 /* capturing dump failed */
2059 ha->isp_ops->rd_reg_indirect(ha,
2060 crb_addr, &read_value);
2063 opcode &= ~QLA8XXX_DBG_OPCODE_POLL;
2066 if (opcode & QLA8XXX_DBG_OPCODE_RDSTATE) {
2067 if (crb_entry->crb_strd.state_index_a) {
2068 index = crb_entry->crb_strd.state_index_a;
2069 addr = tmplt_hdr->saved_state_array[index];
2074 ha->isp_ops->rd_reg_indirect(ha, addr, &read_value);
2075 index = crb_entry->crb_ctrl.state_index_v;
2076 tmplt_hdr->saved_state_array[index] = read_value;
2077 opcode &= ~QLA8XXX_DBG_OPCODE_RDSTATE;
2080 if (opcode & QLA8XXX_DBG_OPCODE_WRSTATE) {
2081 if (crb_entry->crb_strd.state_index_a) {
2082 index = crb_entry->crb_strd.state_index_a;
2083 addr = tmplt_hdr->saved_state_array[index];
2088 if (crb_entry->crb_ctrl.state_index_v) {
2089 index = crb_entry->crb_ctrl.state_index_v;
2091 tmplt_hdr->saved_state_array[index];
2093 read_value = crb_entry->value_1;
2096 ha->isp_ops->wr_reg_indirect(ha, addr, read_value);
2097 opcode &= ~QLA8XXX_DBG_OPCODE_WRSTATE;
2100 if (opcode & QLA8XXX_DBG_OPCODE_MDSTATE) {
2101 index = crb_entry->crb_ctrl.state_index_v;
2102 read_value = tmplt_hdr->saved_state_array[index];
2103 read_value <<= crb_entry->crb_ctrl.shl;
2104 read_value >>= crb_entry->crb_ctrl.shr;
2105 if (crb_entry->value_2)
2106 read_value &= crb_entry->value_2;
2107 read_value |= crb_entry->value_3;
2108 read_value += crb_entry->value_1;
2109 tmplt_hdr->saved_state_array[index] = read_value;
2110 opcode &= ~QLA8XXX_DBG_OPCODE_MDSTATE;
2112 crb_addr += crb_entry->crb_strd.addr_stride;
2114 DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s\n", __func__));
2118 static void qla4_8xxx_minidump_process_rdocm(struct scsi_qla_host *ha,
2119 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2122 uint32_t r_addr, r_stride, loop_cnt, i, r_value;
2123 struct qla8xxx_minidump_entry_rdocm *ocm_hdr;
2124 uint32_t *data_ptr = *d_ptr;
2126 DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
2127 ocm_hdr = (struct qla8xxx_minidump_entry_rdocm *)entry_hdr;
2128 r_addr = ocm_hdr->read_addr;
2129 r_stride = ocm_hdr->read_addr_stride;
2130 loop_cnt = ocm_hdr->op_count;
2132 DEBUG2(ql4_printk(KERN_INFO, ha,
2133 "[%s]: r_addr: 0x%x, r_stride: 0x%x, loop_cnt: 0x%x\n",
2134 __func__, r_addr, r_stride, loop_cnt));
2136 for (i = 0; i < loop_cnt; i++) {
2137 r_value = readl((void __iomem *)(r_addr + ha->nx_pcibase));
2138 *data_ptr++ = cpu_to_le32(r_value);
2141 DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s datacount: 0x%lx\n",
2142 __func__, (long unsigned int) (loop_cnt * sizeof(uint32_t))));
2146 static void qla4_8xxx_minidump_process_rdmux(struct scsi_qla_host *ha,
2147 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2150 uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value;
2151 struct qla8xxx_minidump_entry_mux *mux_hdr;
2152 uint32_t *data_ptr = *d_ptr;
2154 DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
2155 mux_hdr = (struct qla8xxx_minidump_entry_mux *)entry_hdr;
2156 r_addr = mux_hdr->read_addr;
2157 s_addr = mux_hdr->select_addr;
2158 s_stride = mux_hdr->select_value_stride;
2159 s_value = mux_hdr->select_value;
2160 loop_cnt = mux_hdr->op_count;
2162 for (i = 0; i < loop_cnt; i++) {
2163 ha->isp_ops->wr_reg_indirect(ha, s_addr, s_value);
2164 ha->isp_ops->rd_reg_indirect(ha, r_addr, &r_value);
2165 *data_ptr++ = cpu_to_le32(s_value);
2166 *data_ptr++ = cpu_to_le32(r_value);
2167 s_value += s_stride;
2172 static void qla4_8xxx_minidump_process_l1cache(struct scsi_qla_host *ha,
2173 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2176 uint32_t addr, r_addr, c_addr, t_r_addr;
2177 uint32_t i, k, loop_count, t_value, r_cnt, r_value;
2179 struct qla8xxx_minidump_entry_cache *cache_hdr;
2180 uint32_t *data_ptr = *d_ptr;
2182 cache_hdr = (struct qla8xxx_minidump_entry_cache *)entry_hdr;
2183 loop_count = cache_hdr->op_count;
2184 r_addr = cache_hdr->read_addr;
2185 c_addr = cache_hdr->control_addr;
2186 c_value_w = cache_hdr->cache_ctrl.write_value;
2188 t_r_addr = cache_hdr->tag_reg_addr;
2189 t_value = cache_hdr->addr_ctrl.init_tag_value;
2190 r_cnt = cache_hdr->read_ctrl.read_addr_cnt;
2192 for (i = 0; i < loop_count; i++) {
2193 ha->isp_ops->wr_reg_indirect(ha, t_r_addr, t_value);
2194 ha->isp_ops->wr_reg_indirect(ha, c_addr, c_value_w);
2196 for (k = 0; k < r_cnt; k++) {
2197 ha->isp_ops->rd_reg_indirect(ha, addr, &r_value);
2198 *data_ptr++ = cpu_to_le32(r_value);
2199 addr += cache_hdr->read_ctrl.read_addr_stride;
2201 t_value += cache_hdr->addr_ctrl.tag_value_stride;
2206 static void qla4_8xxx_minidump_process_queue(struct scsi_qla_host *ha,
2207 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2210 uint32_t s_addr, r_addr;
2211 uint32_t r_stride, r_value, r_cnt, qid = 0;
2212 uint32_t i, k, loop_cnt;
2213 struct qla8xxx_minidump_entry_queue *q_hdr;
2214 uint32_t *data_ptr = *d_ptr;
2216 DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
2217 q_hdr = (struct qla8xxx_minidump_entry_queue *)entry_hdr;
2218 s_addr = q_hdr->select_addr;
2219 r_cnt = q_hdr->rd_strd.read_addr_cnt;
2220 r_stride = q_hdr->rd_strd.read_addr_stride;
2221 loop_cnt = q_hdr->op_count;
2223 for (i = 0; i < loop_cnt; i++) {
2224 ha->isp_ops->wr_reg_indirect(ha, s_addr, qid);
2225 r_addr = q_hdr->read_addr;
2226 for (k = 0; k < r_cnt; k++) {
2227 ha->isp_ops->rd_reg_indirect(ha, r_addr, &r_value);
2228 *data_ptr++ = cpu_to_le32(r_value);
2231 qid += q_hdr->q_strd.queue_id_stride;
2236 #define MD_DIRECT_ROM_WINDOW 0x42110030
2237 #define MD_DIRECT_ROM_READ_BASE 0x42150000
2239 static void qla4_82xx_minidump_process_rdrom(struct scsi_qla_host *ha,
2240 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2243 uint32_t r_addr, r_value;
2244 uint32_t i, loop_cnt;
2245 struct qla8xxx_minidump_entry_rdrom *rom_hdr;
2246 uint32_t *data_ptr = *d_ptr;
2248 DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
2249 rom_hdr = (struct qla8xxx_minidump_entry_rdrom *)entry_hdr;
2250 r_addr = rom_hdr->read_addr;
2251 loop_cnt = rom_hdr->read_data_size/sizeof(uint32_t);
2253 DEBUG2(ql4_printk(KERN_INFO, ha,
2254 "[%s]: flash_addr: 0x%x, read_data_size: 0x%x\n",
2255 __func__, r_addr, loop_cnt));
2257 for (i = 0; i < loop_cnt; i++) {
2258 ha->isp_ops->wr_reg_indirect(ha, MD_DIRECT_ROM_WINDOW,
2259 (r_addr & 0xFFFF0000));
2260 ha->isp_ops->rd_reg_indirect(ha,
2261 MD_DIRECT_ROM_READ_BASE + (r_addr & 0x0000FFFF),
2263 *data_ptr++ = cpu_to_le32(r_value);
2264 r_addr += sizeof(uint32_t);
2269 #define MD_MIU_TEST_AGT_CTRL 0x41000090
2270 #define MD_MIU_TEST_AGT_ADDR_LO 0x41000094
2271 #define MD_MIU_TEST_AGT_ADDR_HI 0x41000098
2273 static int __qla4_8xxx_minidump_process_rdmem(struct scsi_qla_host *ha,
2274 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2277 uint32_t r_addr, r_value, r_data;
2278 uint32_t i, j, loop_cnt;
2279 struct qla8xxx_minidump_entry_rdmem *m_hdr;
2280 unsigned long flags;
2281 uint32_t *data_ptr = *d_ptr;
2283 DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
2284 m_hdr = (struct qla8xxx_minidump_entry_rdmem *)entry_hdr;
2285 r_addr = m_hdr->read_addr;
2286 loop_cnt = m_hdr->read_data_size/16;
2288 DEBUG2(ql4_printk(KERN_INFO, ha,
2289 "[%s]: Read addr: 0x%x, read_data_size: 0x%x\n",
2290 __func__, r_addr, m_hdr->read_data_size));
2293 DEBUG2(ql4_printk(KERN_INFO, ha,
2294 "[%s]: Read addr 0x%x not 16 bytes aligned\n",
2299 if (m_hdr->read_data_size % 16) {
2300 DEBUG2(ql4_printk(KERN_INFO, ha,
2301 "[%s]: Read data[0x%x] not multiple of 16 bytes\n",
2302 __func__, m_hdr->read_data_size));
2306 DEBUG2(ql4_printk(KERN_INFO, ha,
2307 "[%s]: rdmem_addr: 0x%x, read_data_size: 0x%x, loop_cnt: 0x%x\n",
2308 __func__, r_addr, m_hdr->read_data_size, loop_cnt));
2310 write_lock_irqsave(&ha->hw_lock, flags);
2311 for (i = 0; i < loop_cnt; i++) {
2312 ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_ADDR_LO,
2315 ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_ADDR_HI,
2317 r_value = MIU_TA_CTL_ENABLE;
2318 ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_CTRL, r_value);
2319 r_value = MIU_TA_CTL_START_ENABLE;
2320 ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_CTRL, r_value);
2322 for (j = 0; j < MAX_CTL_CHECK; j++) {
2323 ha->isp_ops->rd_reg_indirect(ha, MD_MIU_TEST_AGT_CTRL,
2325 if ((r_value & MIU_TA_CTL_BUSY) == 0)
2329 if (j >= MAX_CTL_CHECK) {
2330 printk_ratelimited(KERN_ERR
2331 "%s: failed to read through agent\n",
2333 write_unlock_irqrestore(&ha->hw_lock, flags);
2337 for (j = 0; j < 4; j++) {
2338 ha->isp_ops->rd_reg_indirect(ha,
2339 MD_MIU_TEST_AGT_RDDATA[j],
2341 *data_ptr++ = cpu_to_le32(r_data);
2346 write_unlock_irqrestore(&ha->hw_lock, flags);
2348 DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s datacount: 0x%x\n",
2349 __func__, (loop_cnt * 16)));
2355 static int qla4_8xxx_minidump_process_rdmem(struct scsi_qla_host *ha,
2356 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2359 uint32_t *data_ptr = *d_ptr;
2360 int rval = QLA_SUCCESS;
2362 if (is_qla8032(ha) || is_qla8042(ha)) {
2363 rval = qla4_83xx_minidump_pex_dma_read(ha, entry_hdr,
2365 if (rval != QLA_SUCCESS) {
2366 rval = __qla4_8xxx_minidump_process_rdmem(ha, entry_hdr,
2370 rval = __qla4_8xxx_minidump_process_rdmem(ha, entry_hdr,
2377 static void qla4_8xxx_mark_entry_skipped(struct scsi_qla_host *ha,
2378 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2381 entry_hdr->d_ctrl.driver_flags |= QLA8XXX_DBG_SKIPPED_FLAG;
2382 DEBUG2(ql4_printk(KERN_INFO, ha,
2383 "scsi(%ld): Skipping entry[%d]: ETYPE[0x%x]-ELEVEL[0x%x]\n",
2384 ha->host_no, index, entry_hdr->entry_type,
2385 entry_hdr->d_ctrl.entry_capture_mask));
2386 /* If driver encounters a new entry type that it cannot process,
2387 * it should just skip the entry and adjust the total buffer size by
2388 * from subtracting the skipped bytes from it
2390 ha->fw_dump_skip_size += entry_hdr->entry_capture_size;
2393 /* ISP83xx functions to process new minidump entries... */
2394 static uint32_t qla83xx_minidump_process_pollrd(struct scsi_qla_host *ha,
2395 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2398 uint32_t r_addr, s_addr, s_value, r_value, poll_wait, poll_mask;
2399 uint16_t s_stride, i;
2400 uint32_t *data_ptr = *d_ptr;
2401 uint32_t rval = QLA_SUCCESS;
2402 struct qla83xx_minidump_entry_pollrd *pollrd_hdr;
2404 pollrd_hdr = (struct qla83xx_minidump_entry_pollrd *)entry_hdr;
2405 s_addr = le32_to_cpu(pollrd_hdr->select_addr);
2406 r_addr = le32_to_cpu(pollrd_hdr->read_addr);
2407 s_value = le32_to_cpu(pollrd_hdr->select_value);
2408 s_stride = le32_to_cpu(pollrd_hdr->select_value_stride);
2410 poll_wait = le32_to_cpu(pollrd_hdr->poll_wait);
2411 poll_mask = le32_to_cpu(pollrd_hdr->poll_mask);
2413 for (i = 0; i < le32_to_cpu(pollrd_hdr->op_count); i++) {
2414 ha->isp_ops->wr_reg_indirect(ha, s_addr, s_value);
2415 poll_wait = le32_to_cpu(pollrd_hdr->poll_wait);
2417 ha->isp_ops->rd_reg_indirect(ha, s_addr, &r_value);
2419 if ((r_value & poll_mask) != 0) {
2423 if (--poll_wait == 0) {
2424 ql4_printk(KERN_ERR, ha, "%s: TIMEOUT\n",
2427 goto exit_process_pollrd;
2431 ha->isp_ops->rd_reg_indirect(ha, r_addr, &r_value);
2432 *data_ptr++ = cpu_to_le32(s_value);
2433 *data_ptr++ = cpu_to_le32(r_value);
2434 s_value += s_stride;
2439 exit_process_pollrd:
2443 static void qla83xx_minidump_process_rdmux2(struct scsi_qla_host *ha,
2444 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2447 uint32_t sel_val1, sel_val2, t_sel_val, data, i;
2448 uint32_t sel_addr1, sel_addr2, sel_val_mask, read_addr;
2449 struct qla83xx_minidump_entry_rdmux2 *rdmux2_hdr;
2450 uint32_t *data_ptr = *d_ptr;
2452 rdmux2_hdr = (struct qla83xx_minidump_entry_rdmux2 *)entry_hdr;
2453 sel_val1 = le32_to_cpu(rdmux2_hdr->select_value_1);
2454 sel_val2 = le32_to_cpu(rdmux2_hdr->select_value_2);
2455 sel_addr1 = le32_to_cpu(rdmux2_hdr->select_addr_1);
2456 sel_addr2 = le32_to_cpu(rdmux2_hdr->select_addr_2);
2457 sel_val_mask = le32_to_cpu(rdmux2_hdr->select_value_mask);
2458 read_addr = le32_to_cpu(rdmux2_hdr->read_addr);
2460 for (i = 0; i < rdmux2_hdr->op_count; i++) {
2461 ha->isp_ops->wr_reg_indirect(ha, sel_addr1, sel_val1);
2462 t_sel_val = sel_val1 & sel_val_mask;
2463 *data_ptr++ = cpu_to_le32(t_sel_val);
2465 ha->isp_ops->wr_reg_indirect(ha, sel_addr2, t_sel_val);
2466 ha->isp_ops->rd_reg_indirect(ha, read_addr, &data);
2468 *data_ptr++ = cpu_to_le32(data);
2470 ha->isp_ops->wr_reg_indirect(ha, sel_addr1, sel_val2);
2471 t_sel_val = sel_val2 & sel_val_mask;
2472 *data_ptr++ = cpu_to_le32(t_sel_val);
2474 ha->isp_ops->wr_reg_indirect(ha, sel_addr2, t_sel_val);
2475 ha->isp_ops->rd_reg_indirect(ha, read_addr, &data);
2477 *data_ptr++ = cpu_to_le32(data);
2479 sel_val1 += rdmux2_hdr->select_value_stride;
2480 sel_val2 += rdmux2_hdr->select_value_stride;
2486 static uint32_t qla83xx_minidump_process_pollrdmwr(struct scsi_qla_host *ha,
2487 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2490 uint32_t poll_wait, poll_mask, r_value, data;
2491 uint32_t addr_1, addr_2, value_1, value_2;
2492 uint32_t *data_ptr = *d_ptr;
2493 uint32_t rval = QLA_SUCCESS;
2494 struct qla83xx_minidump_entry_pollrdmwr *poll_hdr;
2496 poll_hdr = (struct qla83xx_minidump_entry_pollrdmwr *)entry_hdr;
2497 addr_1 = le32_to_cpu(poll_hdr->addr_1);
2498 addr_2 = le32_to_cpu(poll_hdr->addr_2);
2499 value_1 = le32_to_cpu(poll_hdr->value_1);
2500 value_2 = le32_to_cpu(poll_hdr->value_2);
2501 poll_mask = le32_to_cpu(poll_hdr->poll_mask);
2503 ha->isp_ops->wr_reg_indirect(ha, addr_1, value_1);
2505 poll_wait = le32_to_cpu(poll_hdr->poll_wait);
2507 ha->isp_ops->rd_reg_indirect(ha, addr_1, &r_value);
2509 if ((r_value & poll_mask) != 0) {
2513 if (--poll_wait == 0) {
2514 ql4_printk(KERN_ERR, ha, "%s: TIMEOUT_1\n",
2517 goto exit_process_pollrdmwr;
2522 ha->isp_ops->rd_reg_indirect(ha, addr_2, &data);
2523 data &= le32_to_cpu(poll_hdr->modify_mask);
2524 ha->isp_ops->wr_reg_indirect(ha, addr_2, data);
2525 ha->isp_ops->wr_reg_indirect(ha, addr_1, value_2);
2527 poll_wait = le32_to_cpu(poll_hdr->poll_wait);
2529 ha->isp_ops->rd_reg_indirect(ha, addr_1, &r_value);
2531 if ((r_value & poll_mask) != 0) {
2535 if (--poll_wait == 0) {
2536 ql4_printk(KERN_ERR, ha, "%s: TIMEOUT_2\n",
2539 goto exit_process_pollrdmwr;
2544 *data_ptr++ = cpu_to_le32(addr_2);
2545 *data_ptr++ = cpu_to_le32(data);
2548 exit_process_pollrdmwr:
2552 static uint32_t qla4_83xx_minidump_process_rdrom(struct scsi_qla_host *ha,
2553 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2556 uint32_t fl_addr, u32_count, rval;
2557 struct qla8xxx_minidump_entry_rdrom *rom_hdr;
2558 uint32_t *data_ptr = *d_ptr;
2560 rom_hdr = (struct qla8xxx_minidump_entry_rdrom *)entry_hdr;
2561 fl_addr = le32_to_cpu(rom_hdr->read_addr);
2562 u32_count = le32_to_cpu(rom_hdr->read_data_size)/sizeof(uint32_t);
2564 DEBUG2(ql4_printk(KERN_INFO, ha, "[%s]: fl_addr: 0x%x, count: 0x%x\n",
2565 __func__, fl_addr, u32_count));
2567 rval = qla4_83xx_lockless_flash_read_u32(ha, fl_addr,
2568 (u8 *)(data_ptr), u32_count);
2570 if (rval == QLA_ERROR) {
2571 ql4_printk(KERN_ERR, ha, "%s: Flash Read Error,Count=%d\n",
2572 __func__, u32_count);
2573 goto exit_process_rdrom;
2576 data_ptr += u32_count;
2584 * qla4_8xxx_collect_md_data - Retrieve firmware minidump data.
2585 * @ha: pointer to adapter structure
2587 static int qla4_8xxx_collect_md_data(struct scsi_qla_host *ha)
2589 int num_entry_hdr = 0;
2590 struct qla8xxx_minidump_entry_hdr *entry_hdr;
2591 struct qla4_8xxx_minidump_template_hdr *tmplt_hdr;
2593 uint32_t data_collected = 0;
2594 int i, rval = QLA_ERROR;
2598 ha->fw_dump_skip_size = 0;
2600 ql4_printk(KERN_INFO, ha, "%s(%ld) No buffer to dump\n",
2601 __func__, ha->host_no);
2605 tmplt_hdr = (struct qla4_8xxx_minidump_template_hdr *)
2606 ha->fw_dump_tmplt_hdr;
2607 data_ptr = (uint32_t *)((uint8_t *)ha->fw_dump +
2608 ha->fw_dump_tmplt_size);
2609 data_collected += ha->fw_dump_tmplt_size;
2611 num_entry_hdr = tmplt_hdr->num_of_entries;
2612 ql4_printk(KERN_INFO, ha, "[%s]: starting data ptr: %p\n",
2613 __func__, data_ptr);
2614 ql4_printk(KERN_INFO, ha,
2615 "[%s]: no of entry headers in Template: 0x%x\n",
2616 __func__, num_entry_hdr);
2617 ql4_printk(KERN_INFO, ha, "[%s]: Capture Mask obtained: 0x%x\n",
2618 __func__, ha->fw_dump_capture_mask);
2619 ql4_printk(KERN_INFO, ha, "[%s]: Total_data_size 0x%x, %d obtained\n",
2620 __func__, ha->fw_dump_size, ha->fw_dump_size);
2622 /* Update current timestamp before taking dump */
2623 now = get_jiffies_64();
2624 timestamp = (u32)(jiffies_to_msecs(now) / 1000);
2625 tmplt_hdr->driver_timestamp = timestamp;
2627 entry_hdr = (struct qla8xxx_minidump_entry_hdr *)
2628 (((uint8_t *)ha->fw_dump_tmplt_hdr) +
2629 tmplt_hdr->first_entry_offset);
2631 if (is_qla8032(ha) || is_qla8042(ha))
2632 tmplt_hdr->saved_state_array[QLA83XX_SS_OCM_WNDREG_INDEX] =
2633 tmplt_hdr->ocm_window_reg[ha->func_num];
2635 /* Walk through the entry headers - validate/perform required action */
2636 for (i = 0; i < num_entry_hdr; i++) {
2637 if (data_collected > ha->fw_dump_size) {
2638 ql4_printk(KERN_INFO, ha,
2639 "Data collected: [0x%x], Total Dump size: [0x%x]\n",
2640 data_collected, ha->fw_dump_size);
2644 if (!(entry_hdr->d_ctrl.entry_capture_mask &
2645 ha->fw_dump_capture_mask)) {
2646 entry_hdr->d_ctrl.driver_flags |=
2647 QLA8XXX_DBG_SKIPPED_FLAG;
2648 goto skip_nxt_entry;
2651 DEBUG2(ql4_printk(KERN_INFO, ha,
2652 "Data collected: [0x%x], Dump size left:[0x%x]\n",
2654 (ha->fw_dump_size - data_collected)));
2656 /* Decode the entry type and take required action to capture
2659 switch (entry_hdr->entry_type) {
2661 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
2664 rval = qla4_8xxx_minidump_process_control(ha,
2666 if (rval != QLA_SUCCESS) {
2667 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
2672 qla4_8xxx_minidump_process_rdcrb(ha, entry_hdr,
2676 rval = qla4_8xxx_minidump_process_rdmem(ha, entry_hdr,
2678 if (rval != QLA_SUCCESS) {
2679 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
2685 if (is_qla8022(ha)) {
2686 qla4_82xx_minidump_process_rdrom(ha, entry_hdr,
2688 } else if (is_qla8032(ha) || is_qla8042(ha)) {
2689 rval = qla4_83xx_minidump_process_rdrom(ha,
2692 if (rval != QLA_SUCCESS)
2693 qla4_8xxx_mark_entry_skipped(ha,
2702 rval = qla4_8xxx_minidump_process_l2tag(ha, entry_hdr,
2704 if (rval != QLA_SUCCESS) {
2705 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
2713 qla4_8xxx_minidump_process_l1cache(ha, entry_hdr,
2717 qla4_8xxx_minidump_process_rdocm(ha, entry_hdr,
2721 qla4_8xxx_minidump_process_rdmux(ha, entry_hdr,
2725 qla4_8xxx_minidump_process_queue(ha, entry_hdr,
2728 case QLA83XX_POLLRD:
2729 if (is_qla8022(ha)) {
2730 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
2733 rval = qla83xx_minidump_process_pollrd(ha, entry_hdr,
2735 if (rval != QLA_SUCCESS)
2736 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
2738 case QLA83XX_RDMUX2:
2739 if (is_qla8022(ha)) {
2740 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
2743 qla83xx_minidump_process_rdmux2(ha, entry_hdr,
2746 case QLA83XX_POLLRDMWR:
2747 if (is_qla8022(ha)) {
2748 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
2751 rval = qla83xx_minidump_process_pollrdmwr(ha, entry_hdr,
2753 if (rval != QLA_SUCCESS)
2754 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
2758 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
2762 data_collected = (uint8_t *)data_ptr - (uint8_t *)ha->fw_dump;
2764 /* next entry in the template */
2765 entry_hdr = (struct qla8xxx_minidump_entry_hdr *)
2766 (((uint8_t *)entry_hdr) +
2767 entry_hdr->entry_size);
2770 if ((data_collected + ha->fw_dump_skip_size) != ha->fw_dump_size) {
2771 ql4_printk(KERN_INFO, ha,
2772 "Dump data mismatch: Data collected: [0x%x], total_data_size:[0x%x]\n",
2773 data_collected, ha->fw_dump_size);
2778 DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s Last entry: 0x%x\n",
2785 * qla4_8xxx_uevent_emit - Send uevent when the firmware dump is ready.
2786 * @ha: pointer to adapter structure
2788 static void qla4_8xxx_uevent_emit(struct scsi_qla_host *ha, u32 code)
2790 char event_string[40];
2791 char *envp[] = { event_string, NULL };
2794 case QL4_UEVENT_CODE_FW_DUMP:
2795 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
2803 kobject_uevent_env(&(&ha->pdev->dev)->kobj, KOBJ_CHANGE, envp);
2806 void qla4_8xxx_get_minidump(struct scsi_qla_host *ha)
2808 if (ql4xenablemd && test_bit(AF_FW_RECOVERY, &ha->flags) &&
2809 !test_bit(AF_82XX_FW_DUMPED, &ha->flags)) {
2810 if (!qla4_8xxx_collect_md_data(ha)) {
2811 qla4_8xxx_uevent_emit(ha, QL4_UEVENT_CODE_FW_DUMP);
2812 set_bit(AF_82XX_FW_DUMPED, &ha->flags);
2814 ql4_printk(KERN_INFO, ha, "%s: Unable to collect minidump\n",
2821 * qla4_8xxx_device_bootstrap - Initialize device, set DEV_READY, start fw
2822 * @ha: pointer to adapter structure
2824 * Note: IDC lock must be held upon entry
2826 int qla4_8xxx_device_bootstrap(struct scsi_qla_host *ha)
2828 int rval = QLA_ERROR;
2830 uint32_t old_count, count;
2833 need_reset = ha->isp_ops->need_reset(ha);
2836 /* We are trying to perform a recovery here. */
2837 if (test_bit(AF_FW_RECOVERY, &ha->flags))
2838 ha->isp_ops->rom_lock_recovery(ha);
2840 old_count = qla4_8xxx_rd_direct(ha, QLA8XXX_PEG_ALIVE_COUNTER);
2841 for (i = 0; i < 10; i++) {
2843 count = qla4_8xxx_rd_direct(ha,
2844 QLA8XXX_PEG_ALIVE_COUNTER);
2845 if (count != old_count) {
2850 ha->isp_ops->rom_lock_recovery(ha);
2853 /* set to DEV_INITIALIZING */
2854 ql4_printk(KERN_INFO, ha, "HW State: INITIALIZING\n");
2855 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE,
2856 QLA8XXX_DEV_INITIALIZING);
2858 ha->isp_ops->idc_unlock(ha);
2861 qla4_8xxx_get_minidump(ha);
2863 rval = ha->isp_ops->restart_firmware(ha);
2864 ha->isp_ops->idc_lock(ha);
2866 if (rval != QLA_SUCCESS) {
2867 ql4_printk(KERN_INFO, ha, "HW State: FAILED\n");
2868 qla4_8xxx_clear_drv_active(ha);
2869 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE,
2870 QLA8XXX_DEV_FAILED);
2875 ql4_printk(KERN_INFO, ha, "HW State: READY\n");
2876 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE, QLA8XXX_DEV_READY);
2882 * qla4_82xx_need_reset_handler - Code to start reset sequence
2883 * @ha: pointer to adapter structure
2885 * Note: IDC lock must be held upon entry
2888 qla4_82xx_need_reset_handler(struct scsi_qla_host *ha)
2890 uint32_t dev_state, drv_state, drv_active;
2891 uint32_t active_mask = 0xFFFFFFFF;
2892 unsigned long reset_timeout;
2894 ql4_printk(KERN_INFO, ha,
2895 "Performing ISP error recovery\n");
2897 if (test_and_clear_bit(AF_ONLINE, &ha->flags)) {
2898 qla4_82xx_idc_unlock(ha);
2899 ha->isp_ops->disable_intrs(ha);
2900 qla4_82xx_idc_lock(ha);
2903 if (!test_bit(AF_8XXX_RST_OWNER, &ha->flags)) {
2904 DEBUG2(ql4_printk(KERN_INFO, ha,
2905 "%s(%ld): reset acknowledged\n",
2906 __func__, ha->host_no));
2907 qla4_8xxx_set_rst_ready(ha);
2909 active_mask = (~(1 << (ha->func_num * 4)));
2912 /* wait for 10 seconds for reset ack from all functions */
2913 reset_timeout = jiffies + (ha->nx_reset_timeout * HZ);
2915 drv_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2916 drv_active = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2918 ql4_printk(KERN_INFO, ha,
2919 "%s(%ld): drv_state = 0x%x, drv_active = 0x%x\n",
2920 __func__, ha->host_no, drv_state, drv_active);
2922 while (drv_state != (drv_active & active_mask)) {
2923 if (time_after_eq(jiffies, reset_timeout)) {
2924 ql4_printk(KERN_INFO, ha,
2925 "%s: RESET TIMEOUT! drv_state: 0x%08x, drv_active: 0x%08x\n",
2926 DRIVER_NAME, drv_state, drv_active);
2931 * When reset_owner times out, check which functions
2934 if (test_bit(AF_8XXX_RST_OWNER, &ha->flags)) {
2935 ql4_printk(KERN_INFO, ha,
2936 "%s(%ld): drv_state = 0x%x, drv_active = 0x%x\n",
2937 __func__, ha->host_no, drv_state,
2940 qla4_82xx_idc_unlock(ha);
2942 qla4_82xx_idc_lock(ha);
2944 drv_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2945 drv_active = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2948 /* Clear RESET OWNER as we are not going to use it any further */
2949 clear_bit(AF_8XXX_RST_OWNER, &ha->flags);
2951 dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
2952 ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n", dev_state,
2953 dev_state < MAX_STATES ? qdev_state[dev_state] : "Unknown");
2955 /* Force to DEV_COLD unless someone else is starting a reset */
2956 if (dev_state != QLA8XXX_DEV_INITIALIZING) {
2957 ql4_printk(KERN_INFO, ha, "HW State: COLD/RE-INIT\n");
2958 qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_COLD);
2959 qla4_8xxx_set_rst_ready(ha);
2964 * qla4_8xxx_need_qsnt_handler - Code to start qsnt
2965 * @ha: pointer to adapter structure
2968 qla4_8xxx_need_qsnt_handler(struct scsi_qla_host *ha)
2970 ha->isp_ops->idc_lock(ha);
2971 qla4_8xxx_set_qsnt_ready(ha);
2972 ha->isp_ops->idc_unlock(ha);
2975 static void qla4_82xx_set_idc_ver(struct scsi_qla_host *ha)
2978 uint32_t drv_active;
2980 drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
2981 if (drv_active == (1 << (ha->func_num * 4))) {
2982 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION,
2983 QLA82XX_IDC_VERSION);
2984 ql4_printk(KERN_INFO, ha,
2985 "%s: IDC version updated to %d\n", __func__,
2986 QLA82XX_IDC_VERSION);
2988 idc_ver = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION);
2989 if (QLA82XX_IDC_VERSION != idc_ver) {
2990 ql4_printk(KERN_INFO, ha,
2991 "%s: qla4xxx driver IDC version %d is not compatible with IDC version %d of other drivers!\n",
2992 __func__, QLA82XX_IDC_VERSION, idc_ver);
2997 static int qla4_83xx_set_idc_ver(struct scsi_qla_host *ha)
3000 uint32_t drv_active;
3001 int rval = QLA_SUCCESS;
3003 drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
3004 if (drv_active == (1 << ha->func_num)) {
3005 idc_ver = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION);
3007 idc_ver |= QLA83XX_IDC_VER_MAJ_VALUE;
3008 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION, idc_ver);
3009 ql4_printk(KERN_INFO, ha,
3010 "%s: IDC version updated to %d\n", __func__,
3013 idc_ver = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION);
3015 if (QLA83XX_IDC_VER_MAJ_VALUE != idc_ver) {
3016 ql4_printk(KERN_INFO, ha,
3017 "%s: qla4xxx driver IDC version %d is not compatible with IDC version %d of other drivers!\n",
3018 __func__, QLA83XX_IDC_VER_MAJ_VALUE,
3021 goto exit_set_idc_ver;
3025 /* Update IDC_MINOR_VERSION */
3026 idc_ver = qla4_83xx_rd_reg(ha, QLA83XX_CRB_IDC_VER_MINOR);
3027 idc_ver &= ~(0x03 << (ha->func_num * 2));
3028 idc_ver |= (QLA83XX_IDC_VER_MIN_VALUE << (ha->func_num * 2));
3029 qla4_83xx_wr_reg(ha, QLA83XX_CRB_IDC_VER_MINOR, idc_ver);
3035 int qla4_8xxx_update_idc_reg(struct scsi_qla_host *ha)
3037 uint32_t drv_active;
3038 int rval = QLA_SUCCESS;
3040 if (test_bit(AF_INIT_DONE, &ha->flags))
3041 goto exit_update_idc_reg;
3043 ha->isp_ops->idc_lock(ha);
3044 qla4_8xxx_set_drv_active(ha);
3047 * If we are the first driver to load and
3048 * ql4xdontresethba is not set, clear IDC_CTRL BIT0.
3050 if (is_qla8032(ha) || is_qla8042(ha)) {
3051 drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
3052 if ((drv_active == (1 << ha->func_num)) && !ql4xdontresethba)
3053 qla4_83xx_clear_idc_dontreset(ha);
3056 if (is_qla8022(ha)) {
3057 qla4_82xx_set_idc_ver(ha);
3058 } else if (is_qla8032(ha) || is_qla8042(ha)) {
3059 rval = qla4_83xx_set_idc_ver(ha);
3060 if (rval == QLA_ERROR)
3061 qla4_8xxx_clear_drv_active(ha);
3064 ha->isp_ops->idc_unlock(ha);
3066 exit_update_idc_reg:
3071 * qla4_8xxx_device_state_handler - Adapter state machine
3072 * @ha: pointer to host adapter structure.
3074 * Note: IDC lock must be UNLOCKED upon entry
3076 int qla4_8xxx_device_state_handler(struct scsi_qla_host *ha)
3079 int rval = QLA_SUCCESS;
3080 unsigned long dev_init_timeout;
3082 rval = qla4_8xxx_update_idc_reg(ha);
3083 if (rval == QLA_ERROR)
3084 goto exit_state_handler;
3086 dev_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DEV_STATE);
3087 DEBUG2(ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n",
3088 dev_state, dev_state < MAX_STATES ?
3089 qdev_state[dev_state] : "Unknown"));
3091 /* wait for 30 seconds for device to go ready */
3092 dev_init_timeout = jiffies + (ha->nx_dev_init_timeout * HZ);
3094 ha->isp_ops->idc_lock(ha);
3097 if (time_after_eq(jiffies, dev_init_timeout)) {
3098 ql4_printk(KERN_WARNING, ha,
3099 "%s: Device Init Failed 0x%x = %s\n",
3101 dev_state, dev_state < MAX_STATES ?
3102 qdev_state[dev_state] : "Unknown");
3103 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE,
3104 QLA8XXX_DEV_FAILED);
3107 dev_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DEV_STATE);
3108 ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n",
3109 dev_state, dev_state < MAX_STATES ?
3110 qdev_state[dev_state] : "Unknown");
3112 /* NOTE: Make sure idc unlocked upon exit of switch statement */
3113 switch (dev_state) {
3114 case QLA8XXX_DEV_READY:
3116 case QLA8XXX_DEV_COLD:
3117 rval = qla4_8xxx_device_bootstrap(ha);
3119 case QLA8XXX_DEV_INITIALIZING:
3120 ha->isp_ops->idc_unlock(ha);
3122 ha->isp_ops->idc_lock(ha);
3124 case QLA8XXX_DEV_NEED_RESET:
3126 * For ISP8324 and ISP8042, if NEED_RESET is set by any
3127 * driver, it should be honored, irrespective of
3128 * IDC_CTRL DONTRESET_BIT0
3130 if (is_qla8032(ha) || is_qla8042(ha)) {
3131 qla4_83xx_need_reset_handler(ha);
3132 } else if (is_qla8022(ha)) {
3133 if (!ql4xdontresethba) {
3134 qla4_82xx_need_reset_handler(ha);
3135 /* Update timeout value after need
3137 dev_init_timeout = jiffies +
3138 (ha->nx_dev_init_timeout * HZ);
3140 ha->isp_ops->idc_unlock(ha);
3142 ha->isp_ops->idc_lock(ha);
3146 case QLA8XXX_DEV_NEED_QUIESCENT:
3147 /* idc locked/unlocked in handler */
3148 qla4_8xxx_need_qsnt_handler(ha);
3150 case QLA8XXX_DEV_QUIESCENT:
3151 ha->isp_ops->idc_unlock(ha);
3153 ha->isp_ops->idc_lock(ha);
3155 case QLA8XXX_DEV_FAILED:
3156 ha->isp_ops->idc_unlock(ha);
3157 qla4xxx_dead_adapter_cleanup(ha);
3159 ha->isp_ops->idc_lock(ha);
3162 ha->isp_ops->idc_unlock(ha);
3163 qla4xxx_dead_adapter_cleanup(ha);
3165 ha->isp_ops->idc_lock(ha);
3170 ha->isp_ops->idc_unlock(ha);
3175 int qla4_8xxx_load_risc(struct scsi_qla_host *ha)
3179 /* clear the interrupt */
3180 if (is_qla8032(ha) || is_qla8042(ha)) {
3181 writel(0, &ha->qla4_83xx_reg->risc_intr);
3182 readl(&ha->qla4_83xx_reg->risc_intr);
3183 } else if (is_qla8022(ha)) {
3184 writel(0, &ha->qla4_82xx_reg->host_int);
3185 readl(&ha->qla4_82xx_reg->host_int);
3188 retval = qla4_8xxx_device_state_handler(ha);
3190 /* Initialize request and response queues. */
3191 if (retval == QLA_SUCCESS)
3192 qla4xxx_init_rings(ha);
3194 if (retval == QLA_SUCCESS && !test_bit(AF_IRQ_ATTACHED, &ha->flags))
3195 retval = qla4xxx_request_irqs(ha);
3200 /*****************************************************************************/
3201 /* Flash Manipulation Routines */
3202 /*****************************************************************************/
3204 #define OPTROM_BURST_SIZE 0x1000
3205 #define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4)
3207 #define FARX_DATA_FLAG BIT_31
3208 #define FARX_ACCESS_FLASH_CONF 0x7FFD0000
3209 #define FARX_ACCESS_FLASH_DATA 0x7FF00000
3211 static inline uint32_t
3212 flash_conf_addr(struct ql82xx_hw_data *hw, uint32_t faddr)
3214 return hw->flash_conf_off | faddr;
3217 static inline uint32_t
3218 flash_data_addr(struct ql82xx_hw_data *hw, uint32_t faddr)
3220 return hw->flash_data_off | faddr;
3224 qla4_82xx_read_flash_data(struct scsi_qla_host *ha, uint32_t *dwptr,
3225 uint32_t faddr, uint32_t length)
3230 while ((qla4_82xx_rom_lock(ha) != 0) && (loops < 50000)) {
3235 if (loops >= 50000) {
3236 ql4_printk(KERN_WARNING, ha, "ROM lock failed\n");
3240 /* Dword reads to flash. */
3241 for (i = 0; i < length/4; i++, faddr += 4) {
3242 if (qla4_82xx_do_rom_fast_read(ha, faddr, &val)) {
3243 ql4_printk(KERN_WARNING, ha,
3244 "Do ROM fast read failed\n");
3247 dwptr[i] = __constant_cpu_to_le32(val);
3251 qla4_82xx_rom_unlock(ha);
3256 * Address and length are byte address
3259 qla4_82xx_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
3260 uint32_t offset, uint32_t length)
3262 qla4_82xx_read_flash_data(ha, (uint32_t *)buf, offset, length);
3267 qla4_8xxx_find_flt_start(struct scsi_qla_host *ha, uint32_t *start)
3269 const char *loc, *locations[] = { "DEF", "PCI" };
3272 * FLT-location structure resides after the last PCI region.
3275 /* Begin with sane defaults. */
3277 *start = FA_FLASH_LAYOUT_ADDR_82;
3279 DEBUG2(ql4_printk(KERN_INFO, ha, "FLTL[%s] = 0x%x.\n", loc, *start));
3284 qla4_8xxx_get_flt_info(struct scsi_qla_host *ha, uint32_t flt_addr)
3286 const char *loc, *locations[] = { "DEF", "FLT" };
3288 uint16_t cnt, chksum;
3289 uint32_t start, status;
3290 struct qla_flt_header *flt;
3291 struct qla_flt_region *region;
3292 struct ql82xx_hw_data *hw = &ha->hw;
3294 hw->flt_region_flt = flt_addr;
3295 wptr = (uint16_t *)ha->request_ring;
3296 flt = (struct qla_flt_header *)ha->request_ring;
3297 region = (struct qla_flt_region *)&flt[1];
3299 if (is_qla8022(ha)) {
3300 qla4_82xx_read_optrom_data(ha, (uint8_t *)ha->request_ring,
3301 flt_addr << 2, OPTROM_BURST_SIZE);
3302 } else if (is_qla8032(ha) || is_qla8042(ha)) {
3303 status = qla4_83xx_flash_read_u32(ha, flt_addr << 2,
3304 (uint8_t *)ha->request_ring,
3306 if (status != QLA_SUCCESS)
3310 if (*wptr == __constant_cpu_to_le16(0xffff))
3312 if (flt->version != __constant_cpu_to_le16(1)) {
3313 DEBUG2(ql4_printk(KERN_INFO, ha, "Unsupported FLT detected: "
3314 "version=0x%x length=0x%x checksum=0x%x.\n",
3315 le16_to_cpu(flt->version), le16_to_cpu(flt->length),
3316 le16_to_cpu(flt->checksum)));
3320 cnt = (sizeof(struct qla_flt_header) + le16_to_cpu(flt->length)) >> 1;
3321 for (chksum = 0; cnt; cnt--)
3322 chksum += le16_to_cpu(*wptr++);
3324 DEBUG2(ql4_printk(KERN_INFO, ha, "Inconsistent FLT detected: "
3325 "version=0x%x length=0x%x checksum=0x%x.\n",
3326 le16_to_cpu(flt->version), le16_to_cpu(flt->length),
3332 cnt = le16_to_cpu(flt->length) / sizeof(struct qla_flt_region);
3333 for ( ; cnt; cnt--, region++) {
3334 /* Store addresses as DWORD offsets. */
3335 start = le32_to_cpu(region->start) >> 2;
3337 DEBUG3(ql4_printk(KERN_DEBUG, ha, "FLT[%02x]: start=0x%x "
3338 "end=0x%x size=0x%x.\n", le32_to_cpu(region->code), start,
3339 le32_to_cpu(region->end) >> 2, le32_to_cpu(region->size)));
3341 switch (le32_to_cpu(region->code) & 0xff) {
3343 hw->flt_region_fdt = start;
3345 case FLT_REG_BOOT_CODE_82:
3346 hw->flt_region_boot = start;
3349 case FLT_REG_FW_82_1:
3350 hw->flt_region_fw = start;
3352 case FLT_REG_BOOTLOAD_82:
3353 hw->flt_region_bootload = start;
3355 case FLT_REG_ISCSI_PARAM:
3356 hw->flt_iscsi_param = start;
3358 case FLT_REG_ISCSI_CHAP:
3359 hw->flt_region_chap = start;
3360 hw->flt_chap_size = le32_to_cpu(region->size);
3362 case FLT_REG_ISCSI_DDB:
3363 hw->flt_region_ddb = start;
3364 hw->flt_ddb_size = le32_to_cpu(region->size);
3371 /* Use hardcoded defaults. */
3374 hw->flt_region_fdt = FA_FLASH_DESCR_ADDR_82;
3375 hw->flt_region_boot = FA_BOOT_CODE_ADDR_82;
3376 hw->flt_region_bootload = FA_BOOT_LOAD_ADDR_82;
3377 hw->flt_region_fw = FA_RISC_CODE_ADDR_82;
3378 hw->flt_region_chap = FA_FLASH_ISCSI_CHAP >> 2;
3379 hw->flt_chap_size = FA_FLASH_CHAP_SIZE;
3380 hw->flt_region_ddb = FA_FLASH_ISCSI_DDB >> 2;
3381 hw->flt_ddb_size = FA_FLASH_DDB_SIZE;
3384 DEBUG2(ql4_printk(KERN_INFO, ha,
3385 "FLT[%s]: flt=0x%x fdt=0x%x boot=0x%x bootload=0x%x fw=0x%x chap=0x%x chap_size=0x%x ddb=0x%x ddb_size=0x%x\n",
3386 loc, hw->flt_region_flt, hw->flt_region_fdt,
3387 hw->flt_region_boot, hw->flt_region_bootload,
3388 hw->flt_region_fw, hw->flt_region_chap,
3389 hw->flt_chap_size, hw->flt_region_ddb,
3394 qla4_82xx_get_fdt_info(struct scsi_qla_host *ha)
3396 #define FLASH_BLK_SIZE_4K 0x1000
3397 #define FLASH_BLK_SIZE_32K 0x8000
3398 #define FLASH_BLK_SIZE_64K 0x10000
3399 const char *loc, *locations[] = { "MID", "FDT" };
3400 uint16_t cnt, chksum;
3402 struct qla_fdt_layout *fdt;
3405 struct ql82xx_hw_data *hw = &ha->hw;
3407 hw->flash_conf_off = FARX_ACCESS_FLASH_CONF;
3408 hw->flash_data_off = FARX_ACCESS_FLASH_DATA;
3410 wptr = (uint16_t *)ha->request_ring;
3411 fdt = (struct qla_fdt_layout *)ha->request_ring;
3412 qla4_82xx_read_optrom_data(ha, (uint8_t *)ha->request_ring,
3413 hw->flt_region_fdt << 2, OPTROM_BURST_SIZE);
3415 if (*wptr == __constant_cpu_to_le16(0xffff))
3418 if (fdt->sig[0] != 'Q' || fdt->sig[1] != 'L' || fdt->sig[2] != 'I' ||
3422 for (cnt = 0, chksum = 0; cnt < sizeof(struct qla_fdt_layout) >> 1;
3424 chksum += le16_to_cpu(*wptr++);
3427 DEBUG2(ql4_printk(KERN_INFO, ha, "Inconsistent FDT detected: "
3428 "checksum=0x%x id=%c version=0x%x.\n", chksum, fdt->sig[0],
3429 le16_to_cpu(fdt->version)));
3434 mid = le16_to_cpu(fdt->man_id);
3435 fid = le16_to_cpu(fdt->id);
3436 hw->fdt_wrt_disable = fdt->wrt_disable_bits;
3437 hw->fdt_erase_cmd = flash_conf_addr(hw, 0x0300 | fdt->erase_cmd);
3438 hw->fdt_block_size = le32_to_cpu(fdt->block_size);
3440 if (fdt->unprotect_sec_cmd) {
3441 hw->fdt_unprotect_sec_cmd = flash_conf_addr(hw, 0x0300 |
3442 fdt->unprotect_sec_cmd);
3443 hw->fdt_protect_sec_cmd = fdt->protect_sec_cmd ?
3444 flash_conf_addr(hw, 0x0300 | fdt->protect_sec_cmd) :
3445 flash_conf_addr(hw, 0x0336);
3451 hw->fdt_block_size = FLASH_BLK_SIZE_64K;
3453 DEBUG2(ql4_printk(KERN_INFO, ha, "FDT[%s]: (0x%x/0x%x) erase=0x%x "
3454 "pro=%x upro=%x wrtd=0x%x blk=0x%x.\n", loc, mid, fid,
3455 hw->fdt_erase_cmd, hw->fdt_protect_sec_cmd,
3456 hw->fdt_unprotect_sec_cmd, hw->fdt_wrt_disable,
3457 hw->fdt_block_size));
3461 qla4_82xx_get_idc_param(struct scsi_qla_host *ha)
3463 #define QLA82XX_IDC_PARAM_ADDR 0x003e885c
3466 if (!is_qla8022(ha))
3468 wptr = (uint32_t *)ha->request_ring;
3469 qla4_82xx_read_optrom_data(ha, (uint8_t *)ha->request_ring,
3470 QLA82XX_IDC_PARAM_ADDR , 8);
3472 if (*wptr == __constant_cpu_to_le32(0xffffffff)) {
3473 ha->nx_dev_init_timeout = ROM_DEV_INIT_TIMEOUT;
3474 ha->nx_reset_timeout = ROM_DRV_RESET_ACK_TIMEOUT;
3476 ha->nx_dev_init_timeout = le32_to_cpu(*wptr++);
3477 ha->nx_reset_timeout = le32_to_cpu(*wptr);
3480 DEBUG2(ql4_printk(KERN_DEBUG, ha,
3481 "ha->nx_dev_init_timeout = %d\n", ha->nx_dev_init_timeout));
3482 DEBUG2(ql4_printk(KERN_DEBUG, ha,
3483 "ha->nx_reset_timeout = %d\n", ha->nx_reset_timeout));
3487 void qla4_82xx_queue_mbox_cmd(struct scsi_qla_host *ha, uint32_t *mbx_cmd,
3492 /* Load all mailbox registers, except mailbox 0. */
3493 for (i = 1; i < in_count; i++)
3494 writel(mbx_cmd[i], &ha->qla4_82xx_reg->mailbox_in[i]);
3496 /* Wakeup firmware */
3497 writel(mbx_cmd[0], &ha->qla4_82xx_reg->mailbox_in[0]);
3498 readl(&ha->qla4_82xx_reg->mailbox_in[0]);
3499 writel(HINT_MBX_INT_PENDING, &ha->qla4_82xx_reg->hint);
3500 readl(&ha->qla4_82xx_reg->hint);
3503 void qla4_82xx_process_mbox_intr(struct scsi_qla_host *ha, int out_count)
3507 intr_status = readl(&ha->qla4_82xx_reg->host_int);
3508 if (intr_status & ISRX_82XX_RISC_INT) {
3509 ha->mbox_status_count = out_count;
3510 intr_status = readl(&ha->qla4_82xx_reg->host_status);
3511 ha->isp_ops->interrupt_service_routine(ha, intr_status);
3513 if (test_bit(AF_INTERRUPTS_ON, &ha->flags) &&
3514 test_bit(AF_INTx_ENABLED, &ha->flags))
3515 qla4_82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg,
3521 qla4_8xxx_get_flash_info(struct scsi_qla_host *ha)
3526 ret = qla4_8xxx_find_flt_start(ha, &flt_addr);
3527 if (ret != QLA_SUCCESS)
3530 qla4_8xxx_get_flt_info(ha, flt_addr);
3531 if (is_qla8022(ha)) {
3532 qla4_82xx_get_fdt_info(ha);
3533 qla4_82xx_get_idc_param(ha);
3534 } else if (is_qla8032(ha) || is_qla8042(ha)) {
3535 qla4_83xx_get_idc_param(ha);
3542 * qla4_8xxx_stop_firmware - stops firmware on specified adapter instance
3543 * @ha: pointer to host adapter structure.
3546 * For iSCSI, throws away all I/O and AENs into bit bucket, so they will
3547 * not be available after successful return. Driver must cleanup potential
3548 * outstanding I/O's after calling this funcion.
3551 qla4_8xxx_stop_firmware(struct scsi_qla_host *ha)
3554 uint32_t mbox_cmd[MBOX_REG_COUNT];
3555 uint32_t mbox_sts[MBOX_REG_COUNT];
3557 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
3558 memset(&mbox_sts, 0, sizeof(mbox_sts));
3560 mbox_cmd[0] = MBOX_CMD_STOP_FW;
3561 status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1,
3562 &mbox_cmd[0], &mbox_sts[0]);
3564 DEBUG2(printk("scsi%ld: %s: status = %d\n", ha->host_no,
3570 * qla4_82xx_isp_reset - Resets ISP and aborts all outstanding commands.
3571 * @ha: pointer to host adapter structure.
3574 qla4_82xx_isp_reset(struct scsi_qla_host *ha)
3579 qla4_82xx_idc_lock(ha);
3580 dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3582 if (dev_state == QLA8XXX_DEV_READY) {
3583 ql4_printk(KERN_INFO, ha, "HW State: NEED RESET\n");
3584 qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
3585 QLA8XXX_DEV_NEED_RESET);
3586 set_bit(AF_8XXX_RST_OWNER, &ha->flags);
3588 ql4_printk(KERN_INFO, ha, "HW State: DEVICE INITIALIZING\n");
3590 qla4_82xx_idc_unlock(ha);
3592 rval = qla4_8xxx_device_state_handler(ha);
3594 qla4_82xx_idc_lock(ha);
3595 qla4_8xxx_clear_rst_ready(ha);
3596 qla4_82xx_idc_unlock(ha);
3598 if (rval == QLA_SUCCESS) {
3599 ql4_printk(KERN_INFO, ha, "Clearing AF_RECOVERY in qla4_82xx_isp_reset\n");
3600 clear_bit(AF_FW_RECOVERY, &ha->flags);
3607 * qla4_8xxx_get_sys_info - get adapter MAC address(es) and serial number
3608 * @ha: pointer to host adapter structure.
3611 int qla4_8xxx_get_sys_info(struct scsi_qla_host *ha)
3613 uint32_t mbox_cmd[MBOX_REG_COUNT];
3614 uint32_t mbox_sts[MBOX_REG_COUNT];
3615 struct mbx_sys_info *sys_info;
3616 dma_addr_t sys_info_dma;
3617 int status = QLA_ERROR;
3619 sys_info = dma_alloc_coherent(&ha->pdev->dev, sizeof(*sys_info),
3620 &sys_info_dma, GFP_KERNEL);
3621 if (sys_info == NULL) {
3622 DEBUG2(printk("scsi%ld: %s: Unable to allocate dma buffer.\n",
3623 ha->host_no, __func__));
3627 memset(sys_info, 0, sizeof(*sys_info));
3628 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
3629 memset(&mbox_sts, 0, sizeof(mbox_sts));
3631 mbox_cmd[0] = MBOX_CMD_GET_SYS_INFO;
3632 mbox_cmd[1] = LSDW(sys_info_dma);
3633 mbox_cmd[2] = MSDW(sys_info_dma);
3634 mbox_cmd[4] = sizeof(*sys_info);
3636 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 6, &mbox_cmd[0],
3637 &mbox_sts[0]) != QLA_SUCCESS) {
3638 DEBUG2(printk("scsi%ld: %s: GET_SYS_INFO failed\n",
3639 ha->host_no, __func__));
3640 goto exit_validate_mac82;
3643 /* Make sure we receive the minimum required data to cache internally */
3644 if (((is_qla8032(ha) || is_qla8042(ha)) ? mbox_sts[3] : mbox_sts[4]) <
3645 offsetof(struct mbx_sys_info, reserved)) {
3646 DEBUG2(printk("scsi%ld: %s: GET_SYS_INFO data receive"
3647 " error (%x)\n", ha->host_no, __func__, mbox_sts[4]));
3648 goto exit_validate_mac82;
3651 /* Save M.A.C. address & serial_number */
3652 ha->port_num = sys_info->port_num;
3653 memcpy(ha->my_mac, &sys_info->mac_addr[0],
3654 min(sizeof(ha->my_mac), sizeof(sys_info->mac_addr)));
3655 memcpy(ha->serial_number, &sys_info->serial_number,
3656 min(sizeof(ha->serial_number), sizeof(sys_info->serial_number)));
3657 memcpy(ha->model_name, &sys_info->board_id_str,
3658 min(sizeof(ha->model_name), sizeof(sys_info->board_id_str)));
3659 ha->phy_port_cnt = sys_info->phys_port_cnt;
3660 ha->phy_port_num = sys_info->port_num;
3661 ha->iscsi_pci_func_cnt = sys_info->iscsi_pci_func_cnt;
3663 DEBUG2(printk("scsi%ld: %s: "
3664 "mac %02x:%02x:%02x:%02x:%02x:%02x "
3665 "serial %s\n", ha->host_no, __func__,
3666 ha->my_mac[0], ha->my_mac[1], ha->my_mac[2],
3667 ha->my_mac[3], ha->my_mac[4], ha->my_mac[5],
3668 ha->serial_number));
3670 status = QLA_SUCCESS;
3672 exit_validate_mac82:
3673 dma_free_coherent(&ha->pdev->dev, sizeof(*sys_info), sys_info,
3678 /* Interrupt handling helpers. */
3680 int qla4_8xxx_intr_enable(struct scsi_qla_host *ha)
3682 uint32_t mbox_cmd[MBOX_REG_COUNT];
3683 uint32_t mbox_sts[MBOX_REG_COUNT];
3685 DEBUG2(ql4_printk(KERN_INFO, ha, "%s\n", __func__));
3687 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
3688 memset(&mbox_sts, 0, sizeof(mbox_sts));
3689 mbox_cmd[0] = MBOX_CMD_ENABLE_INTRS;
3690 mbox_cmd[1] = INTR_ENABLE;
3691 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
3692 &mbox_sts[0]) != QLA_SUCCESS) {
3693 DEBUG2(ql4_printk(KERN_INFO, ha,
3694 "%s: MBOX_CMD_ENABLE_INTRS failed (0x%04x)\n",
3695 __func__, mbox_sts[0]));
3701 int qla4_8xxx_intr_disable(struct scsi_qla_host *ha)
3703 uint32_t mbox_cmd[MBOX_REG_COUNT];
3704 uint32_t mbox_sts[MBOX_REG_COUNT];
3706 DEBUG2(ql4_printk(KERN_INFO, ha, "%s\n", __func__));
3708 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
3709 memset(&mbox_sts, 0, sizeof(mbox_sts));
3710 mbox_cmd[0] = MBOX_CMD_ENABLE_INTRS;
3711 mbox_cmd[1] = INTR_DISABLE;
3712 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
3713 &mbox_sts[0]) != QLA_SUCCESS) {
3714 DEBUG2(ql4_printk(KERN_INFO, ha,
3715 "%s: MBOX_CMD_ENABLE_INTRS failed (0x%04x)\n",
3716 __func__, mbox_sts[0]));
3724 qla4_82xx_enable_intrs(struct scsi_qla_host *ha)
3726 qla4_8xxx_intr_enable(ha);
3728 spin_lock_irq(&ha->hardware_lock);
3729 /* BIT 10 - reset */
3730 qla4_82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff);
3731 spin_unlock_irq(&ha->hardware_lock);
3732 set_bit(AF_INTERRUPTS_ON, &ha->flags);
3736 qla4_82xx_disable_intrs(struct scsi_qla_host *ha)
3738 if (test_and_clear_bit(AF_INTERRUPTS_ON, &ha->flags))
3739 qla4_8xxx_intr_disable(ha);
3741 spin_lock_irq(&ha->hardware_lock);
3743 qla4_82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400);
3744 spin_unlock_irq(&ha->hardware_lock);
3747 struct ql4_init_msix_entry {
3751 irq_handler_t handler;
3754 static struct ql4_init_msix_entry qla4_8xxx_msix_entries[QLA_MSIX_ENTRIES] = {
3755 { QLA_MSIX_DEFAULT, QLA_MIDX_DEFAULT,
3756 "qla4xxx (default)",
3757 (irq_handler_t)qla4_8xxx_default_intr_handler },
3758 { QLA_MSIX_RSP_Q, QLA_MIDX_RSP_Q,
3759 "qla4xxx (rsp_q)", (irq_handler_t)qla4_8xxx_msix_rsp_q },
3763 qla4_8xxx_disable_msix(struct scsi_qla_host *ha)
3766 struct ql4_msix_entry *qentry;
3768 for (i = 0; i < QLA_MSIX_ENTRIES; i++) {
3769 qentry = &ha->msix_entries[qla4_8xxx_msix_entries[i].index];
3770 if (qentry->have_irq) {
3771 free_irq(qentry->msix_vector, ha);
3772 DEBUG2(ql4_printk(KERN_INFO, ha, "%s: %s\n",
3773 __func__, qla4_8xxx_msix_entries[i].name));
3776 pci_disable_msix(ha->pdev);
3777 clear_bit(AF_MSIX_ENABLED, &ha->flags);
3781 qla4_8xxx_enable_msix(struct scsi_qla_host *ha)
3784 struct msix_entry entries[QLA_MSIX_ENTRIES];
3785 struct ql4_msix_entry *qentry;
3787 for (i = 0; i < QLA_MSIX_ENTRIES; i++)
3788 entries[i].entry = qla4_8xxx_msix_entries[i].entry;
3790 ret = pci_enable_msix(ha->pdev, entries, ARRAY_SIZE(entries));
3792 ql4_printk(KERN_WARNING, ha,
3793 "MSI-X: Failed to enable support -- %d/%d\n",
3794 QLA_MSIX_ENTRIES, ret);
3797 set_bit(AF_MSIX_ENABLED, &ha->flags);
3799 for (i = 0; i < QLA_MSIX_ENTRIES; i++) {
3800 qentry = &ha->msix_entries[qla4_8xxx_msix_entries[i].index];
3801 qentry->msix_vector = entries[i].vector;
3802 qentry->msix_entry = entries[i].entry;
3803 qentry->have_irq = 0;
3804 ret = request_irq(qentry->msix_vector,
3805 qla4_8xxx_msix_entries[i].handler, 0,
3806 qla4_8xxx_msix_entries[i].name, ha);
3808 ql4_printk(KERN_WARNING, ha,
3809 "MSI-X: Unable to register handler -- %x/%d.\n",
3810 qla4_8xxx_msix_entries[i].index, ret);
3811 qla4_8xxx_disable_msix(ha);
3814 qentry->have_irq = 1;
3815 DEBUG2(ql4_printk(KERN_INFO, ha, "%s: %s\n",
3816 __func__, qla4_8xxx_msix_entries[i].name));
3822 int qla4_8xxx_check_init_adapter_retry(struct scsi_qla_host *ha)
3824 int status = QLA_SUCCESS;
3826 /* Dont retry adapter initialization if IRQ allocation failed */
3827 if (!test_bit(AF_IRQ_ATTACHED, &ha->flags)) {
3828 ql4_printk(KERN_WARNING, ha, "%s: Skipping retry of adapter initialization as IRQs are not attached\n",
3831 goto exit_init_adapter_failure;
3834 /* Since interrupts are registered in start_firmware for
3835 * 8xxx, release them here if initialize_adapter fails
3836 * and retry adapter initialization */
3837 qla4xxx_free_irqs(ha);
3839 exit_init_adapter_failure: