2 * sata_promise.c - Promise SATA
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2003-2004 Red Hat, Inc.
10 * The contents of this file are subject to the Open
11 * Software License version 1.1 that can be found at
12 * http://www.opensource.org/licenses/osl-1.1.txt and is included herein
15 * Alternatively, the contents of this file may be used under the terms
16 * of the GNU General Public License version 2 (the "GPL") as distributed
17 * in the kernel source COPYING file, in which case the provisions of
18 * the GPL are applicable instead of the above. If you wish to allow
19 * the use of your version of this file only under the terms of the
20 * GPL and not to allow others to use your version of this file under
21 * the OSL, indicate your decision by deleting the provisions above and
22 * replace them with the notice and other provisions required by the GPL.
23 * If you do not delete the provisions above, a recipient may use your
24 * version of this file under either the OSL or the GPL.
28 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/init.h>
32 #include <linux/blkdev.h>
33 #include <linux/delay.h>
34 #include <linux/interrupt.h>
35 #include <linux/sched.h>
37 #include <scsi/scsi_host.h>
38 #include <linux/libata.h>
40 #include "sata_promise.h"
42 #define DRV_NAME "sata_promise"
43 #define DRV_VERSION "1.01"
47 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
48 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
49 PDC_TBG_MODE = 0x41, /* TBG mode */
50 PDC_FLASH_CTL = 0x44, /* Flash control register */
51 PDC_PCI_CTL = 0x48, /* PCI control and status register */
52 PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */
53 PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */
54 PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */
55 PDC_SLEW_CTL = 0x470, /* slew rate control reg */
57 PDC_ERR_MASK = (1<<19) | (1<<20) | (1<<21) | (1<<22) |
58 (1<<8) | (1<<9) | (1<<10),
60 board_2037x = 0, /* FastTrak S150 TX2plus */
61 board_20319 = 1, /* FastTrak S150 TX4 */
62 board_20619 = 2, /* FastTrak TX4000 */
64 PDC_HAS_PATA = (1 << 1), /* PDC20375 has PATA */
66 PDC_RESET = (1 << 11), /* HDMA reset */
70 struct pdc_port_priv {
75 static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg);
76 static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
77 static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
78 static irqreturn_t pdc_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
79 static void pdc_eng_timeout(struct ata_port *ap);
80 static int pdc_port_start(struct ata_port *ap);
81 static void pdc_port_stop(struct ata_port *ap);
82 static void pdc_phy_reset(struct ata_port *ap);
83 static void pdc_qc_prep(struct ata_queued_cmd *qc);
84 static void pdc_tf_load_mmio(struct ata_port *ap, struct ata_taskfile *tf);
85 static void pdc_exec_command_mmio(struct ata_port *ap, struct ata_taskfile *tf);
86 static void pdc_irq_clear(struct ata_port *ap);
87 static int pdc_qc_issue_prot(struct ata_queued_cmd *qc);
89 static Scsi_Host_Template pdc_ata_sht = {
90 .module = THIS_MODULE,
92 .ioctl = ata_scsi_ioctl,
93 .queuecommand = ata_scsi_queuecmd,
94 .eh_strategy_handler = ata_scsi_error,
95 .can_queue = ATA_DEF_QUEUE,
96 .this_id = ATA_SHT_THIS_ID,
97 .sg_tablesize = LIBATA_MAX_PRD,
98 .max_sectors = ATA_MAX_SECTORS,
99 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
100 .emulated = ATA_SHT_EMULATED,
101 .use_clustering = ATA_SHT_USE_CLUSTERING,
102 .proc_name = DRV_NAME,
103 .dma_boundary = ATA_DMA_BOUNDARY,
104 .slave_configure = ata_scsi_slave_config,
105 .bios_param = ata_std_bios_param,
109 static struct ata_port_operations pdc_ata_ops = {
110 .port_disable = ata_port_disable,
111 .tf_load = pdc_tf_load_mmio,
112 .tf_read = ata_tf_read,
113 .check_status = ata_check_status,
114 .exec_command = pdc_exec_command_mmio,
115 .dev_select = ata_std_dev_select,
116 .phy_reset = pdc_phy_reset,
117 .qc_prep = pdc_qc_prep,
118 .qc_issue = pdc_qc_issue_prot,
119 .eng_timeout = pdc_eng_timeout,
120 .irq_handler = pdc_interrupt,
121 .irq_clear = pdc_irq_clear,
122 .scr_read = pdc_sata_scr_read,
123 .scr_write = pdc_sata_scr_write,
124 .port_start = pdc_port_start,
125 .port_stop = pdc_port_stop,
126 .host_stop = ata_host_stop,
129 static struct ata_port_info pdc_port_info[] = {
133 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
134 ATA_FLAG_SRST | ATA_FLAG_MMIO,
135 .pio_mask = 0x1f, /* pio0-4 */
136 .mwdma_mask = 0x07, /* mwdma0-2 */
137 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
138 .port_ops = &pdc_ata_ops,
144 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
145 ATA_FLAG_SRST | ATA_FLAG_MMIO,
146 .pio_mask = 0x1f, /* pio0-4 */
147 .mwdma_mask = 0x07, /* mwdma0-2 */
148 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
149 .port_ops = &pdc_ata_ops,
155 .host_flags = ATA_FLAG_NO_LEGACY | ATA_FLAG_SRST |
156 ATA_FLAG_MMIO | ATA_FLAG_SLAVE_POSS,
157 .pio_mask = 0x1f, /* pio0-4 */
158 .mwdma_mask = 0x07, /* mwdma0-2 */
159 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
160 .port_ops = &pdc_ata_ops,
164 static struct pci_device_id pdc_ata_pci_tbl[] = {
165 { PCI_VENDOR_ID_PROMISE, 0x3371, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
167 { PCI_VENDOR_ID_PROMISE, 0x3571, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
169 { PCI_VENDOR_ID_PROMISE, 0x3373, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
171 { PCI_VENDOR_ID_PROMISE, 0x3375, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
173 { PCI_VENDOR_ID_PROMISE, 0x3376, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
175 { PCI_VENDOR_ID_PROMISE, 0x3574, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
177 { PCI_VENDOR_ID_PROMISE, 0x3d75, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
180 { PCI_VENDOR_ID_PROMISE, 0x3318, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
182 { PCI_VENDOR_ID_PROMISE, 0x3319, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
184 { PCI_VENDOR_ID_PROMISE, 0x3d17, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
186 { PCI_VENDOR_ID_PROMISE, 0x3d18, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
189 { PCI_VENDOR_ID_PROMISE, 0x6629, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
192 { } /* terminate list */
196 static struct pci_driver pdc_ata_pci_driver = {
198 .id_table = pdc_ata_pci_tbl,
199 .probe = pdc_ata_init_one,
200 .remove = ata_pci_remove_one,
204 static int pdc_port_start(struct ata_port *ap)
206 struct device *dev = ap->host_set->dev;
207 struct pdc_port_priv *pp;
210 rc = ata_port_start(ap);
214 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
219 memset(pp, 0, sizeof(*pp));
221 pp->pkt = dma_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
227 ap->private_data = pp;
239 static void pdc_port_stop(struct ata_port *ap)
241 struct device *dev = ap->host_set->dev;
242 struct pdc_port_priv *pp = ap->private_data;
244 ap->private_data = NULL;
245 dma_free_coherent(dev, 128, pp->pkt, pp->pkt_dma);
251 static void pdc_reset_port(struct ata_port *ap)
253 void *mmio = (void *) ap->ioaddr.cmd_addr + PDC_CTLSTAT;
257 for (i = 11; i > 0; i--) {
270 readl(mmio); /* flush */
273 static void pdc_phy_reset(struct ata_port *ap)
279 static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
281 if (sc_reg > SCR_CONTROL)
283 return readl((void *) ap->ioaddr.scr_addr + (sc_reg * 4));
287 static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
290 if (sc_reg > SCR_CONTROL)
292 writel(val, (void *) ap->ioaddr.scr_addr + (sc_reg * 4));
295 static void pdc_qc_prep(struct ata_queued_cmd *qc)
297 struct pdc_port_priv *pp = qc->ap->private_data;
302 switch (qc->tf.protocol) {
307 case ATA_PROT_NODATA:
308 i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma,
309 qc->dev->devno, pp->pkt);
311 if (qc->tf.flags & ATA_TFLAG_LBA48)
312 i = pdc_prep_lba48(&qc->tf, pp->pkt, i);
314 i = pdc_prep_lba28(&qc->tf, pp->pkt, i);
316 pdc_pkt_footer(&qc->tf, pp->pkt, i);
324 static void pdc_eng_timeout(struct ata_port *ap)
327 struct ata_queued_cmd *qc;
331 qc = ata_qc_from_tag(ap, ap->active_tag);
333 printk(KERN_ERR "ata%u: BUG: timeout without command\n",
338 /* hack alert! We cannot use the supplied completion
339 * function from inside the ->eh_strategy_handler() thread.
340 * libata is the only user of ->eh_strategy_handler() in
341 * any kernel, so the default scsi_done() assumes it is
342 * not being called from the SCSI EH.
344 qc->scsidone = scsi_finish_command;
346 switch (qc->tf.protocol) {
348 case ATA_PROT_NODATA:
349 printk(KERN_ERR "ata%u: command timeout\n", ap->id);
350 ata_qc_complete(qc, ata_wait_idle(ap) | ATA_ERR);
354 drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
356 printk(KERN_ERR "ata%u: unknown timeout, cmd 0x%x stat 0x%x\n",
357 ap->id, qc->tf.command, drv_stat);
359 ata_qc_complete(qc, drv_stat);
367 static inline unsigned int pdc_host_intr( struct ata_port *ap,
368 struct ata_queued_cmd *qc)
371 unsigned int handled = 0, have_err = 0;
373 void *mmio = (void *) ap->ioaddr.cmd_addr + PDC_GLOBAL_CTL;
376 if (tmp & PDC_ERR_MASK) {
381 switch (qc->tf.protocol) {
383 case ATA_PROT_NODATA:
384 status = ata_wait_idle(ap);
387 ata_qc_complete(qc, status);
392 ap->stats.idle_irq++;
399 static void pdc_irq_clear(struct ata_port *ap)
401 struct ata_host_set *host_set = ap->host_set;
402 void *mmio = host_set->mmio_base;
404 readl(mmio + PDC_INT_SEQMASK);
407 static irqreturn_t pdc_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
409 struct ata_host_set *host_set = dev_instance;
413 unsigned int handled = 0;
418 if (!host_set || !host_set->mmio_base) {
419 VPRINTK("QUICK EXIT\n");
423 mmio_base = host_set->mmio_base;
425 /* reading should also clear interrupts */
426 mask = readl(mmio_base + PDC_INT_SEQMASK);
428 if (mask == 0xffffffff) {
429 VPRINTK("QUICK EXIT 2\n");
432 mask &= 0xffff; /* only 16 tags possible */
434 VPRINTK("QUICK EXIT 3\n");
438 spin_lock(&host_set->lock);
440 writel(mask, mmio_base + PDC_INT_SEQMASK);
442 for (i = 0; i < host_set->n_ports; i++) {
443 VPRINTK("port %u\n", i);
444 ap = host_set->ports[i];
445 tmp = mask & (1 << (i + 1));
446 if (tmp && ap && (!(ap->flags & ATA_FLAG_PORT_DISABLED))) {
447 struct ata_queued_cmd *qc;
449 qc = ata_qc_from_tag(ap, ap->active_tag);
450 if (qc && (!(qc->tf.ctl & ATA_NIEN)))
451 handled += pdc_host_intr(ap, qc);
455 spin_unlock(&host_set->lock);
459 return IRQ_RETVAL(handled);
462 static inline void pdc_packet_start(struct ata_queued_cmd *qc)
464 struct ata_port *ap = qc->ap;
465 struct pdc_port_priv *pp = ap->private_data;
466 unsigned int port_no = ap->port_no;
467 u8 seq = (u8) (port_no + 1);
469 VPRINTK("ENTER, ap %p\n", ap);
471 writel(0x00000001, ap->host_set->mmio_base + (seq * 4));
472 readl(ap->host_set->mmio_base + (seq * 4)); /* flush */
475 wmb(); /* flush PRD, pkt writes */
476 writel(pp->pkt_dma, (void *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
477 readl((void *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); /* flush */
480 static int pdc_qc_issue_prot(struct ata_queued_cmd *qc)
482 switch (qc->tf.protocol) {
484 case ATA_PROT_NODATA:
485 pdc_packet_start(qc);
488 case ATA_PROT_ATAPI_DMA:
496 return ata_qc_issue_prot(qc);
499 static void pdc_tf_load_mmio(struct ata_port *ap, struct ata_taskfile *tf)
501 WARN_ON (tf->protocol == ATA_PROT_DMA ||
502 tf->protocol == ATA_PROT_NODATA);
507 static void pdc_exec_command_mmio(struct ata_port *ap, struct ata_taskfile *tf)
509 WARN_ON (tf->protocol == ATA_PROT_DMA ||
510 tf->protocol == ATA_PROT_NODATA);
511 ata_exec_command(ap, tf);
515 static void pdc_ata_setup_port(struct ata_ioports *port, unsigned long base)
517 port->cmd_addr = base;
518 port->data_addr = base;
520 port->error_addr = base + 0x4;
521 port->nsect_addr = base + 0x8;
522 port->lbal_addr = base + 0xc;
523 port->lbam_addr = base + 0x10;
524 port->lbah_addr = base + 0x14;
525 port->device_addr = base + 0x18;
527 port->status_addr = base + 0x1c;
528 port->altstatus_addr =
529 port->ctl_addr = base + 0x38;
533 static void pdc_host_init(unsigned int chip_id, struct ata_probe_ent *pe)
535 void *mmio = pe->mmio_base;
539 * Except for the hotplug stuff, this is voodoo from the
540 * Promise driver. Label this entire section
541 * "TODO: figure out why we do this"
544 /* change FIFO_SHD to 8 dwords, enable BMR_BURST */
545 tmp = readl(mmio + PDC_FLASH_CTL);
546 tmp |= 0x12000; /* bit 16 (fifo 8 dw) and 13 (bmr burst?) */
547 writel(tmp, mmio + PDC_FLASH_CTL);
549 /* clear plug/unplug flags for all ports */
550 tmp = readl(mmio + PDC_SATA_PLUG_CSR);
551 writel(tmp | 0xff, mmio + PDC_SATA_PLUG_CSR);
553 /* mask plug/unplug ints */
554 tmp = readl(mmio + PDC_SATA_PLUG_CSR);
555 writel(tmp | 0xff0000, mmio + PDC_SATA_PLUG_CSR);
557 /* reduce TBG clock to 133 Mhz. */
558 tmp = readl(mmio + PDC_TBG_MODE);
559 tmp &= ~0x30000; /* clear bit 17, 16*/
560 tmp |= 0x10000; /* set bit 17:16 = 0:1 */
561 writel(tmp, mmio + PDC_TBG_MODE);
563 readl(mmio + PDC_TBG_MODE); /* flush */
566 /* adjust slew rate control register. */
567 tmp = readl(mmio + PDC_SLEW_CTL);
568 tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */
569 tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */
570 writel(tmp, mmio + PDC_SLEW_CTL);
573 static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
575 static int printed_version;
576 struct ata_probe_ent *probe_ent = NULL;
579 unsigned int board_idx = (unsigned int) ent->driver_data;
580 int pci_dev_busy = 0;
583 if (!printed_version++)
584 printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
587 * If this driver happens to only be useful on Apple's K2, then
588 * we should check that here as it has a normal Serverworks ID
590 rc = pci_enable_device(pdev);
594 rc = pci_request_regions(pdev, DRV_NAME);
600 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
602 goto err_out_regions;
603 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
605 goto err_out_regions;
607 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
608 if (probe_ent == NULL) {
610 goto err_out_regions;
613 memset(probe_ent, 0, sizeof(*probe_ent));
614 probe_ent->dev = pci_dev_to_dev(pdev);
615 INIT_LIST_HEAD(&probe_ent->node);
617 mmio_base = ioremap(pci_resource_start(pdev, 3),
618 pci_resource_len(pdev, 3));
619 if (mmio_base == NULL) {
621 goto err_out_free_ent;
623 base = (unsigned long) mmio_base;
625 probe_ent->sht = pdc_port_info[board_idx].sht;
626 probe_ent->host_flags = pdc_port_info[board_idx].host_flags;
627 probe_ent->pio_mask = pdc_port_info[board_idx].pio_mask;
628 probe_ent->mwdma_mask = pdc_port_info[board_idx].mwdma_mask;
629 probe_ent->udma_mask = pdc_port_info[board_idx].udma_mask;
630 probe_ent->port_ops = pdc_port_info[board_idx].port_ops;
632 probe_ent->irq = pdev->irq;
633 probe_ent->irq_flags = SA_SHIRQ;
634 probe_ent->mmio_base = mmio_base;
636 pdc_ata_setup_port(&probe_ent->port[0], base + 0x200);
637 pdc_ata_setup_port(&probe_ent->port[1], base + 0x280);
639 probe_ent->port[0].scr_addr = base + 0x400;
640 probe_ent->port[1].scr_addr = base + 0x500;
642 /* notice 4-port boards */
645 probe_ent->n_ports = 4;
647 pdc_ata_setup_port(&probe_ent->port[2], base + 0x300);
648 pdc_ata_setup_port(&probe_ent->port[3], base + 0x380);
650 probe_ent->port[2].scr_addr = base + 0x600;
651 probe_ent->port[3].scr_addr = base + 0x700;
654 probe_ent->n_ports = 2;
657 probe_ent->n_ports = 4;
659 pdc_ata_setup_port(&probe_ent->port[2], base + 0x300);
660 pdc_ata_setup_port(&probe_ent->port[3], base + 0x380);
662 probe_ent->port[2].scr_addr = base + 0x600;
663 probe_ent->port[3].scr_addr = base + 0x700;
670 pci_set_master(pdev);
672 /* initialize adapter */
673 pdc_host_init(board_idx, probe_ent);
675 /* FIXME: check ata_device_add return value */
676 ata_device_add(probe_ent);
684 pci_release_regions(pdev);
687 pci_disable_device(pdev);
692 static int __init pdc_ata_init(void)
694 return pci_module_init(&pdc_ata_pci_driver);
698 static void __exit pdc_ata_exit(void)
700 pci_unregister_driver(&pdc_ata_pci_driver);
704 MODULE_AUTHOR("Jeff Garzik");
705 MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver");
706 MODULE_LICENSE("GPL");
707 MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl);
708 MODULE_VERSION(DRV_VERSION);
710 module_init(pdc_ata_init);
711 module_exit(pdc_ata_exit);