2 * sata_vsc.c - Vitesse VSC7174 4 port DPA SATA
4 * Maintained by: Jeremy Higdon @ SGI
5 * Please ALWAYS copy linux-ide@vger.kernel.org
10 * Bits from Jeff Garzik, Copyright RedHat, Inc.
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2, or (at your option)
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; see the file COPYING. If not, write to
25 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
28 * libata documentation is available via 'make {ps|pdf}docs',
29 * as Documentation/DocBook/libata.*
31 * Vitesse hardware documentation presumably available under NDA.
32 * Intel 31244 (same hardware interface) documentation presumably
33 * available from http://developer.intel.com/
37 #include <linux/kernel.h>
38 #include <linux/module.h>
39 #include <linux/pci.h>
40 #include <linux/init.h>
41 #include <linux/blkdev.h>
42 #include <linux/delay.h>
43 #include <linux/interrupt.h>
44 #include <linux/dma-mapping.h>
45 #include <linux/device.h>
46 #include <scsi/scsi_host.h>
47 #include <linux/libata.h>
49 #define DRV_NAME "sata_vsc"
50 #define DRV_VERSION "1.1"
52 /* Interrupt register offsets (from chip base address) */
53 #define VSC_SATA_INT_STAT_OFFSET 0x00
54 #define VSC_SATA_INT_MASK_OFFSET 0x04
56 /* Taskfile registers offsets */
57 #define VSC_SATA_TF_CMD_OFFSET 0x00
58 #define VSC_SATA_TF_DATA_OFFSET 0x00
59 #define VSC_SATA_TF_ERROR_OFFSET 0x04
60 #define VSC_SATA_TF_FEATURE_OFFSET 0x06
61 #define VSC_SATA_TF_NSECT_OFFSET 0x08
62 #define VSC_SATA_TF_LBAL_OFFSET 0x0c
63 #define VSC_SATA_TF_LBAM_OFFSET 0x10
64 #define VSC_SATA_TF_LBAH_OFFSET 0x14
65 #define VSC_SATA_TF_DEVICE_OFFSET 0x18
66 #define VSC_SATA_TF_STATUS_OFFSET 0x1c
67 #define VSC_SATA_TF_COMMAND_OFFSET 0x1d
68 #define VSC_SATA_TF_ALTSTATUS_OFFSET 0x28
69 #define VSC_SATA_TF_CTL_OFFSET 0x29
72 #define VSC_SATA_UP_DESCRIPTOR_OFFSET 0x64
73 #define VSC_SATA_UP_DATA_BUFFER_OFFSET 0x6C
74 #define VSC_SATA_DMA_CMD_OFFSET 0x70
77 #define VSC_SATA_SCR_STATUS_OFFSET 0x100
78 #define VSC_SATA_SCR_ERROR_OFFSET 0x104
79 #define VSC_SATA_SCR_CONTROL_OFFSET 0x108
82 #define VSC_SATA_PORT_OFFSET 0x200
84 /* Error interrupt status bit offsets */
85 #define VSC_SATA_INT_ERROR_CRC 0x40
86 #define VSC_SATA_INT_ERROR_T 0x20
87 #define VSC_SATA_INT_ERROR_P 0x10
88 #define VSC_SATA_INT_ERROR_R 0x8
89 #define VSC_SATA_INT_ERROR_E 0x4
90 #define VSC_SATA_INT_ERROR_M 0x2
91 #define VSC_SATA_INT_PHY_CHANGE 0x1
92 #define VSC_SATA_INT_ERROR (VSC_SATA_INT_ERROR_CRC | VSC_SATA_INT_ERROR_T | \
93 VSC_SATA_INT_ERROR_P | VSC_SATA_INT_ERROR_R | \
94 VSC_SATA_INT_ERROR_E | VSC_SATA_INT_ERROR_M | \
95 VSC_SATA_INT_PHY_CHANGE)
97 #define is_vsc_sata_int_err(port_idx, int_status) \
98 (int_status & (VSC_SATA_INT_ERROR << (8 * port_idx)))
101 static u32 vsc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
103 if (sc_reg > SCR_CONTROL)
105 return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
109 static void vsc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
112 if (sc_reg > SCR_CONTROL)
114 writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
118 static void vsc_intr_mask_update(struct ata_port *ap, u8 ctl)
120 void __iomem *mask_addr;
123 mask_addr = ap->host_set->mmio_base +
124 VSC_SATA_INT_MASK_OFFSET + ap->port_no;
125 mask = readb(mask_addr);
130 writeb(mask, mask_addr);
134 static void vsc_sata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
136 struct ata_ioports *ioaddr = &ap->ioaddr;
137 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
140 * The only thing the ctl register is used for is SRST.
141 * That is not enabled or disabled via tf_load.
142 * However, if ATA_NIEN is changed, then we need to change the interrupt register.
144 if ((tf->ctl & ATA_NIEN) != (ap->last_ctl & ATA_NIEN)) {
145 ap->last_ctl = tf->ctl;
146 vsc_intr_mask_update(ap, tf->ctl & ATA_NIEN);
148 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
149 writew(tf->feature | (((u16)tf->hob_feature) << 8), ioaddr->feature_addr);
150 writew(tf->nsect | (((u16)tf->hob_nsect) << 8), ioaddr->nsect_addr);
151 writew(tf->lbal | (((u16)tf->hob_lbal) << 8), ioaddr->lbal_addr);
152 writew(tf->lbam | (((u16)tf->hob_lbam) << 8), ioaddr->lbam_addr);
153 writew(tf->lbah | (((u16)tf->hob_lbah) << 8), ioaddr->lbah_addr);
154 } else if (is_addr) {
155 writew(tf->feature, ioaddr->feature_addr);
156 writew(tf->nsect, ioaddr->nsect_addr);
157 writew(tf->lbal, ioaddr->lbal_addr);
158 writew(tf->lbam, ioaddr->lbam_addr);
159 writew(tf->lbah, ioaddr->lbah_addr);
162 if (tf->flags & ATA_TFLAG_DEVICE)
163 writeb(tf->device, ioaddr->device_addr);
169 static void vsc_sata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
171 struct ata_ioports *ioaddr = &ap->ioaddr;
172 u16 nsect, lbal, lbam, lbah, feature;
174 tf->command = ata_check_status(ap);
175 tf->device = readw(ioaddr->device_addr);
176 feature = readw(ioaddr->error_addr);
177 nsect = readw(ioaddr->nsect_addr);
178 lbal = readw(ioaddr->lbal_addr);
179 lbam = readw(ioaddr->lbam_addr);
180 lbah = readw(ioaddr->lbah_addr);
182 tf->feature = feature;
188 if (tf->flags & ATA_TFLAG_LBA48) {
189 tf->hob_feature = feature >> 8;
190 tf->hob_nsect = nsect >> 8;
191 tf->hob_lbal = lbal >> 8;
192 tf->hob_lbam = lbam >> 8;
193 tf->hob_lbah = lbah >> 8;
201 * Read the interrupt register and process for the devices that have them pending.
203 static irqreturn_t vsc_sata_interrupt (int irq, void *dev_instance,
204 struct pt_regs *regs)
206 struct ata_host_set *host_set = dev_instance;
208 unsigned int handled = 0;
211 spin_lock(&host_set->lock);
213 int_status = readl(host_set->mmio_base + VSC_SATA_INT_STAT_OFFSET);
215 for (i = 0; i < host_set->n_ports; i++) {
216 if (int_status & ((u32) 0xFF << (8 * i))) {
219 ap = host_set->ports[i];
221 if (ap && !(ap->flags &
222 (ATA_FLAG_PORT_DISABLED|ATA_FLAG_NOINTR))) {
223 struct ata_queued_cmd *qc;
225 qc = ata_qc_from_tag(ap, ap->active_tag);
226 if (qc && (!(qc->tf.ctl & ATA_NIEN))) {
227 handled += ata_host_intr(ap, qc);
228 } else if (is_vsc_sata_int_err(i, int_status)) {
230 * On some chips (i.e. Intel 31244), an error
231 * interrupt will sneak in at initialization
232 * time (phy state changes). Clearing the SCR
233 * error register is not required, but it prevents
234 * the phy state change interrupts from recurring
238 err_status = vsc_sata_scr_read(ap, SCR_ERROR);
239 printk(KERN_DEBUG "%s: clearing interrupt, "
240 "status %x; sata err status %x\n",
242 int_status, err_status);
243 vsc_sata_scr_write(ap, SCR_ERROR, err_status);
244 /* Clear interrupt status */
252 spin_unlock(&host_set->lock);
254 return IRQ_RETVAL(handled);
258 static struct scsi_host_template vsc_sata_sht = {
259 .module = THIS_MODULE,
261 .ioctl = ata_scsi_ioctl,
262 .queuecommand = ata_scsi_queuecmd,
263 .eh_timed_out = ata_scsi_timed_out,
264 .eh_strategy_handler = ata_scsi_error,
265 .can_queue = ATA_DEF_QUEUE,
266 .this_id = ATA_SHT_THIS_ID,
267 .sg_tablesize = LIBATA_MAX_PRD,
268 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
269 .emulated = ATA_SHT_EMULATED,
270 .use_clustering = ATA_SHT_USE_CLUSTERING,
271 .proc_name = DRV_NAME,
272 .dma_boundary = ATA_DMA_BOUNDARY,
273 .slave_configure = ata_scsi_slave_config,
274 .bios_param = ata_std_bios_param,
278 static const struct ata_port_operations vsc_sata_ops = {
279 .port_disable = ata_port_disable,
280 .tf_load = vsc_sata_tf_load,
281 .tf_read = vsc_sata_tf_read,
282 .exec_command = ata_exec_command,
283 .check_status = ata_check_status,
284 .dev_select = ata_std_dev_select,
285 .phy_reset = sata_phy_reset,
286 .bmdma_setup = ata_bmdma_setup,
287 .bmdma_start = ata_bmdma_start,
288 .bmdma_stop = ata_bmdma_stop,
289 .bmdma_status = ata_bmdma_status,
290 .qc_prep = ata_qc_prep,
291 .qc_issue = ata_qc_issue_prot,
292 .eng_timeout = ata_eng_timeout,
293 .irq_handler = vsc_sata_interrupt,
294 .irq_clear = ata_bmdma_irq_clear,
295 .scr_read = vsc_sata_scr_read,
296 .scr_write = vsc_sata_scr_write,
297 .port_start = ata_port_start,
298 .port_stop = ata_port_stop,
299 .host_stop = ata_pci_host_stop,
302 static void __devinit vsc_sata_setup_port(struct ata_ioports *port, unsigned long base)
304 port->cmd_addr = base + VSC_SATA_TF_CMD_OFFSET;
305 port->data_addr = base + VSC_SATA_TF_DATA_OFFSET;
306 port->error_addr = base + VSC_SATA_TF_ERROR_OFFSET;
307 port->feature_addr = base + VSC_SATA_TF_FEATURE_OFFSET;
308 port->nsect_addr = base + VSC_SATA_TF_NSECT_OFFSET;
309 port->lbal_addr = base + VSC_SATA_TF_LBAL_OFFSET;
310 port->lbam_addr = base + VSC_SATA_TF_LBAM_OFFSET;
311 port->lbah_addr = base + VSC_SATA_TF_LBAH_OFFSET;
312 port->device_addr = base + VSC_SATA_TF_DEVICE_OFFSET;
313 port->status_addr = base + VSC_SATA_TF_STATUS_OFFSET;
314 port->command_addr = base + VSC_SATA_TF_COMMAND_OFFSET;
315 port->altstatus_addr = base + VSC_SATA_TF_ALTSTATUS_OFFSET;
316 port->ctl_addr = base + VSC_SATA_TF_CTL_OFFSET;
317 port->bmdma_addr = base + VSC_SATA_DMA_CMD_OFFSET;
318 port->scr_addr = base + VSC_SATA_SCR_STATUS_OFFSET;
319 writel(0, base + VSC_SATA_UP_DESCRIPTOR_OFFSET);
320 writel(0, base + VSC_SATA_UP_DATA_BUFFER_OFFSET);
324 static int __devinit vsc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
326 static int printed_version;
327 struct ata_probe_ent *probe_ent = NULL;
329 int pci_dev_busy = 0;
330 void __iomem *mmio_base;
333 if (!printed_version++)
334 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
336 rc = pci_enable_device(pdev);
341 * Check if we have needed resource mapped.
343 if (pci_resource_len(pdev, 0) == 0) {
348 rc = pci_request_regions(pdev, DRV_NAME);
355 * Use 32 bit DMA mask, because 64 bit address support is poor.
357 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
359 goto err_out_regions;
360 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
362 goto err_out_regions;
364 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
365 if (probe_ent == NULL) {
367 goto err_out_regions;
369 memset(probe_ent, 0, sizeof(*probe_ent));
370 probe_ent->dev = pci_dev_to_dev(pdev);
371 INIT_LIST_HEAD(&probe_ent->node);
373 mmio_base = pci_iomap(pdev, 0, 0);
374 if (mmio_base == NULL) {
376 goto err_out_free_ent;
378 base = (unsigned long) mmio_base;
381 * Due to a bug in the chip, the default cache line size can't be used
383 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x80);
385 probe_ent->sht = &vsc_sata_sht;
386 probe_ent->host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
387 ATA_FLAG_MMIO | ATA_FLAG_SATA_RESET;
388 probe_ent->port_ops = &vsc_sata_ops;
389 probe_ent->n_ports = 4;
390 probe_ent->irq = pdev->irq;
391 probe_ent->irq_flags = SA_SHIRQ;
392 probe_ent->mmio_base = mmio_base;
394 /* We don't care much about the PIO/UDMA masks, but the core won't like us
395 * if we don't fill these
397 probe_ent->pio_mask = 0x1f;
398 probe_ent->mwdma_mask = 0x07;
399 probe_ent->udma_mask = 0x7f;
401 /* We have 4 ports per PCI function */
402 vsc_sata_setup_port(&probe_ent->port[0], base + 1 * VSC_SATA_PORT_OFFSET);
403 vsc_sata_setup_port(&probe_ent->port[1], base + 2 * VSC_SATA_PORT_OFFSET);
404 vsc_sata_setup_port(&probe_ent->port[2], base + 3 * VSC_SATA_PORT_OFFSET);
405 vsc_sata_setup_port(&probe_ent->port[3], base + 4 * VSC_SATA_PORT_OFFSET);
407 pci_set_master(pdev);
410 * Config offset 0x98 is "Extended Control and Status Register 0"
411 * Default value is (1 << 28). All bits except bit 28 are reserved in
412 * DPA mode. If bit 28 is set, LED 0 reflects all ports' activity.
413 * If bit 28 is clear, each port has its own LED.
415 pci_write_config_dword(pdev, 0x98, 0);
417 /* FIXME: check ata_device_add return value */
418 ata_device_add(probe_ent);
426 pci_release_regions(pdev);
429 pci_disable_device(pdev);
435 * 0x1725/0x7174 is the Vitesse VSC-7174
436 * 0x8086/0x3200 is the Intel 31244, which is supposed to be identical
437 * compatibility is untested as of yet
439 static const struct pci_device_id vsc_sata_pci_tbl[] = {
440 { 0x1725, 0x7174, PCI_ANY_ID, PCI_ANY_ID, 0x10600, 0xFFFFFF, 0 },
441 { 0x8086, 0x3200, PCI_ANY_ID, PCI_ANY_ID, 0x10600, 0xFFFFFF, 0 },
446 static struct pci_driver vsc_sata_pci_driver = {
448 .id_table = vsc_sata_pci_tbl,
449 .probe = vsc_sata_init_one,
450 .remove = ata_pci_remove_one,
454 static int __init vsc_sata_init(void)
456 return pci_module_init(&vsc_sata_pci_driver);
460 static void __exit vsc_sata_exit(void)
462 pci_unregister_driver(&vsc_sata_pci_driver);
466 MODULE_AUTHOR("Jeremy Higdon");
467 MODULE_DESCRIPTION("low-level driver for Vitesse VSC7174 SATA controller");
468 MODULE_LICENSE("GPL");
469 MODULE_DEVICE_TABLE(pci, vsc_sata_pci_tbl);
470 MODULE_VERSION(DRV_VERSION);
472 module_init(vsc_sata_init);
473 module_exit(vsc_sata_exit);