drivers/scsi/stex.c

   1 /*
   2  * SuperTrak EX Series Storage Controller driver for Linux
   3  *
   4  *      Copyright (C) 2005, 2006 Promise Technology Inc.
   5  *
   6  *      This program is free software; you can redistribute it and/or
   7  *      modify it under the terms of the GNU General Public License
   8  *      as published by the Free Software Foundation; either version
   9  *      2 of the License, or (at your option) any later version.
  10  *
  11  *      Written By:
  12  *              Ed Lin <promise_linux@promise.com>
  13  *
  14  *      Version: 3.0.0.1
  15  *
  16  */
  17
  18 #include <linux/init.h>
  19 #include <linux/errno.h>
  20 #include <linux/kernel.h>
  21 #include <linux/delay.h>
  22 #include <linux/sched.h>
  23 #include <linux/time.h>
  24 #include <linux/pci.h>
  25 #include <linux/blkdev.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/types.h>
  28 #include <linux/module.h>
  29 #include <linux/spinlock.h>
  30 #include <asm/io.h>
  31 #include <asm/irq.h>
  32 #include <asm/byteorder.h>
  33 #include <scsi/scsi.h>
  34 #include <scsi/scsi_device.h>
  35 #include <scsi/scsi_cmnd.h>
  36 #include <scsi/scsi_host.h>
  37 #include <scsi/scsi_tcq.h>
  38
  39 #define DRV_NAME "stex"
  40 #define ST_DRIVER_VERSION "3.0.0.1"
  41 #define ST_VER_MAJOR            3
  42 #define ST_VER_MINOR            0
  43 #define ST_OEM                  0
  44 #define ST_BUILD_VER            1
  45
  46 enum {
  47         /* MU register offset */
  48         IMR0    = 0x10, /* MU_INBOUND_MESSAGE_REG0 */
  49         IMR1    = 0x14, /* MU_INBOUND_MESSAGE_REG1 */
  50         OMR0    = 0x18, /* MU_OUTBOUND_MESSAGE_REG0 */
  51         OMR1    = 0x1c, /* MU_OUTBOUND_MESSAGE_REG1 */
  52         IDBL    = 0x20, /* MU_INBOUND_DOORBELL */
  53         IIS     = 0x24, /* MU_INBOUND_INTERRUPT_STATUS */
  54         IIM     = 0x28, /* MU_INBOUND_INTERRUPT_MASK */
  55         ODBL    = 0x2c, /* MU_OUTBOUND_DOORBELL */
  56         OIS     = 0x30, /* MU_OUTBOUND_INTERRUPT_STATUS */
  57         OIM     = 0x3c, /* MU_OUTBOUND_INTERRUPT_MASK */
  58
  59         /* MU register value */
  60         MU_INBOUND_DOORBELL_HANDSHAKE           = 1,
  61         MU_INBOUND_DOORBELL_REQHEADCHANGED      = 2,
  62         MU_INBOUND_DOORBELL_STATUSTAILCHANGED   = 4,
  63         MU_INBOUND_DOORBELL_HMUSTOPPED          = 8,
  64         MU_INBOUND_DOORBELL_RESET               = 16,
  65
  66         MU_OUTBOUND_DOORBELL_HANDSHAKE          = 1,
  67         MU_OUTBOUND_DOORBELL_REQUESTTAILCHANGED = 2,
  68         MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED  = 4,
  69         MU_OUTBOUND_DOORBELL_BUSCHANGE          = 8,
  70         MU_OUTBOUND_DOORBELL_HASEVENT           = 16,
  71
  72         /* MU status code */
  73         MU_STATE_STARTING                       = 1,
  74         MU_STATE_FMU_READY_FOR_HANDSHAKE        = 2,
  75         MU_STATE_SEND_HANDSHAKE_FRAME           = 3,
  76         MU_STATE_STARTED                        = 4,
  77         MU_STATE_RESETTING                      = 5,
  78
  79         MU_MAX_DELAY_TIME                       = 240000,
  80         MU_HANDSHAKE_SIGNATURE                  = 0x55aaaa55,
  81         MU_HANDSHAKE_SIGNATURE_HALF             = 0x5a5a0000,
  82         HMU_PARTNER_TYPE                        = 2,
  83
  84         /* firmware returned values */
  85         SRB_STATUS_SUCCESS                      = 0x01,
  86         SRB_STATUS_ERROR                        = 0x04,
  87         SRB_STATUS_BUSY                         = 0x05,
  88         SRB_STATUS_INVALID_REQUEST              = 0x06,
  89         SRB_STATUS_SELECTION_TIMEOUT            = 0x0A,
  90         SRB_SEE_SENSE                           = 0x80,
  91
  92         /* task attribute */
  93         TASK_ATTRIBUTE_SIMPLE                   = 0x0,
  94         TASK_ATTRIBUTE_HEADOFQUEUE              = 0x1,
  95         TASK_ATTRIBUTE_ORDERED                  = 0x2,
  96         TASK_ATTRIBUTE_ACA                      = 0x4,
  97
  98         /* request count, etc. */
  99         MU_MAX_REQUEST                          = 32,
 100
 101         /* one message wasted, use MU_MAX_REQUEST+1
 102                 to handle MU_MAX_REQUEST messages */
 103         MU_REQ_COUNT                            = (MU_MAX_REQUEST + 1),
 104         MU_STATUS_COUNT                         = (MU_MAX_REQUEST + 1),
 105
 106         STEX_CDB_LENGTH                         = MAX_COMMAND_SIZE,
 107         REQ_VARIABLE_LEN                        = 1024,
 108         STATUS_VAR_LEN                          = 128,
 109         ST_CAN_QUEUE                            = MU_MAX_REQUEST,
 110         ST_CMD_PER_LUN                          = MU_MAX_REQUEST,
 111         ST_MAX_SG                               = 32,
 112
 113         /* sg flags */
 114         SG_CF_EOT                               = 0x80, /* end of table */
 115         SG_CF_64B                               = 0x40, /* 64 bit item */
 116         SG_CF_HOST                              = 0x20, /* sg in host memory */
 117
 118         ST_MAX_ARRAY_SUPPORTED                  = 16,
 119         ST_MAX_TARGET_NUM                       = (ST_MAX_ARRAY_SUPPORTED+1),
 120         ST_MAX_LUN_PER_TARGET                   = 16,
 121
 122         st_shasta                               = 0,
 123         st_vsc                                  = 1,
 124         st_vsc1                                 = 2,
 125         st_yosemite                             = 3,
 126
 127         PASSTHRU_REQ_TYPE                       = 0x00000001,
 128         PASSTHRU_REQ_NO_WAKEUP                  = 0x00000100,
 129         ST_INTERNAL_TIMEOUT                     = 30,
 130
 131         ST_TO_CMD                               = 0,
 132         ST_FROM_CMD                             = 1,
 133
 134         /* vendor specific commands of Promise */
 135         MGT_CMD                                 = 0xd8,
 136         SINBAND_MGT_CMD                         = 0xd9,
 137         ARRAY_CMD                               = 0xe0,
 138         CONTROLLER_CMD                          = 0xe1,
 139         DEBUGGING_CMD                           = 0xe2,
 140         PASSTHRU_CMD                            = 0xe3,
 141
 142         PASSTHRU_GET_ADAPTER                    = 0x05,
 143         PASSTHRU_GET_DRVVER                     = 0x10,
 144
 145         CTLR_CONFIG_CMD                         = 0x03,
 146         CTLR_SHUTDOWN                           = 0x0d,
 147
 148         CTLR_POWER_STATE_CHANGE                 = 0x0e,
 149         CTLR_POWER_SAVING                       = 0x01,
 150
 151         PASSTHRU_SIGNATURE                      = 0x4e415041,
 152         MGT_CMD_SIGNATURE                       = 0xba,
 153
 154         INQUIRY_EVPD                            = 0x01,
 155
 156         ST_ADDITIONAL_MEM                       = 0x200000,
 157 };
 158
 159 /* SCSI inquiry data */
 160 typedef struct st_inq {
 161         u8 DeviceType                   :5;
 162         u8 DeviceTypeQualifier          :3;
 163         u8 DeviceTypeModifier           :7;
 164         u8 RemovableMedia               :1;
 165         u8 Versions;
 166         u8 ResponseDataFormat           :4;
 167         u8 HiSupport                    :1;
 168         u8 NormACA                      :1;
 169         u8 ReservedBit                  :1;
 170         u8 AERC                         :1;
 171         u8 AdditionalLength;
 172         u8 Reserved[2];
 173         u8 SoftReset                    :1;
 174         u8 CommandQueue                 :1;
 175         u8 Reserved2                    :1;
 176         u8 LinkedCommands               :1;
 177         u8 Synchronous                  :1;
 178         u8 Wide16Bit                    :1;
 179         u8 Wide32Bit                    :1;
 180         u8 RelativeAddressing           :1;
 181         u8 VendorId[8];
 182         u8 ProductId[16];
 183         u8 ProductRevisionLevel[4];
 184         u8 VendorSpecific[20];
 185         u8 Reserved3[40];
 186 } ST_INQ;
 187
 188 struct st_sgitem {
 189         u8 ctrl;        /* SG_CF_xxx */
 190         u8 reserved[3];
 191         __le32 count;
 192         __le32 addr;
 193         __le32 addr_hi;
 194 };
 195
 196 struct st_sgtable {
 197         __le16 sg_count;
 198         __le16 max_sg_count;
 199         __le32 sz_in_byte;
 200         struct st_sgitem table[ST_MAX_SG];
 201 };
 202
 203 struct handshake_frame {
 204         __le32 rb_phy;          /* request payload queue physical address */
 205         __le32 rb_phy_hi;
 206         __le16 req_sz;          /* size of each request payload */
 207         __le16 req_cnt;         /* count of reqs the buffer can hold */
 208         __le16 status_sz;       /* size of each status payload */
 209         __le16 status_cnt;      /* count of status the buffer can hold */
 210         __le32 hosttime;        /* seconds from Jan 1, 1970 (GMT) */
 211         __le32 hosttime_hi;
 212         u8 partner_type;        /* who sends this frame */
 213         u8 reserved0[7];
 214         __le32 partner_ver_major;
 215         __le32 partner_ver_minor;
 216         __le32 partner_ver_oem;
 217         __le32 partner_ver_build;
 218         __le32 extra_offset;    /* NEW */
 219         __le32 extra_size;      /* NEW */
 220         u32 reserved1[2];
 221 };
 222
 223 struct req_msg {
 224         __le16 tag;
 225         u8 lun;
 226         u8 target;
 227         u8 task_attr;
 228         u8 task_manage;
 229         u8 prd_entry;
 230         u8 payload_sz;          /* payload size in 4-byte, not used */
 231         u8 cdb[STEX_CDB_LENGTH];
 232         u8 variable[REQ_VARIABLE_LEN];
 233 };
 234
 235 struct status_msg {
 236         __le16 tag;
 237         u8 lun;
 238         u8 target;
 239         u8 srb_status;
 240         u8 scsi_status;
 241         u8 reserved;
 242         u8 payload_sz;          /* payload size in 4-byte */
 243         u8 variable[STATUS_VAR_LEN];
 244 };
 245
 246 struct ver_info {
 247         u32 major;
 248         u32 minor;
 249         u32 oem;
 250         u32 build;
 251         u32 reserved[2];
 252 };
 253
 254 struct st_frame {
 255         u32 base[6];
 256         u32 rom_addr;
 257
 258         struct ver_info drv_ver;
 259         struct ver_info bios_ver;
 260
 261         u32 bus;
 262         u32 slot;
 263         u32 irq_level;
 264         u32 irq_vec;
 265         u32 id;
 266         u32 subid;
 267
 268         u32 dimm_size;
 269         u8 dimm_type;
 270         u8 reserved[3];
 271
 272         u32 channel;
 273         u32 reserved1;
 274 };
 275
 276 struct st_drvver {
 277         u32 major;
 278         u32 minor;
 279         u32 oem;
 280         u32 build;
 281         u32 signature[2];
 282         u8 console_id;
 283         u8 host_no;
 284         u8 reserved0[2];
 285         u32 reserved[3];
 286 };
 287
 288 #define MU_REQ_BUFFER_SIZE      (MU_REQ_COUNT * sizeof(struct req_msg))
 289 #define MU_STATUS_BUFFER_SIZE   (MU_STATUS_COUNT * sizeof(struct status_msg))
 290 #define MU_BUFFER_SIZE          (MU_REQ_BUFFER_SIZE + MU_STATUS_BUFFER_SIZE)
 291 #define STEX_EXTRA_SIZE         max(sizeof(struct st_frame), sizeof(ST_INQ))
 292 #define STEX_BUFFER_SIZE        (MU_BUFFER_SIZE + STEX_EXTRA_SIZE)
 293
 294 struct st_ccb {
 295         struct req_msg *req;
 296         struct scsi_cmnd *cmd;
 297
 298         void *sense_buffer;
 299         unsigned int sense_bufflen;
 300         int sg_count;
 301
 302         u32 req_type;
 303         u8 srb_status;
 304         u8 scsi_status;
 305 };
 306
 307 struct st_hba {
 308         void __iomem *mmio_base;        /* iomapped PCI memory space */
 309         void *dma_mem;
 310         dma_addr_t dma_handle;
 311         size_t dma_size;
 312
 313         struct Scsi_Host *host;
 314         struct pci_dev *pdev;
 315
 316         u32 req_head;
 317         u32 req_tail;
 318         u32 status_head;
 319         u32 status_tail;
 320
 321         struct status_msg *status_buffer;
 322         void *copy_buffer; /* temp buffer for driver-handled commands */
 323         struct st_ccb ccb[MU_MAX_REQUEST];
 324         struct st_ccb *wait_ccb;
 325         wait_queue_head_t waitq;
 326
 327         unsigned int mu_status;
 328         int out_req_cnt;
 329
 330         unsigned int cardtype;
 331 };
 332
 333 static const char console_inq_page[] =
 334 {
 335         0x03,0x00,0x03,0x03,0xFA,0x00,0x00,0x30,
 336         0x50,0x72,0x6F,0x6D,0x69,0x73,0x65,0x20,        /* "Promise " */
 337         0x52,0x41,0x49,0x44,0x20,0x43,0x6F,0x6E,        /* "RAID Con" */
 338         0x73,0x6F,0x6C,0x65,0x20,0x20,0x20,0x20,        /* "sole    " */
 339         0x31,0x2E,0x30,0x30,0x20,0x20,0x20,0x20,        /* "1.00    " */
 340         0x53,0x58,0x2F,0x52,0x53,0x41,0x46,0x2D,        /* "SX/RSAF-" */
 341         0x54,0x45,0x31,0x2E,0x30,0x30,0x20,0x20,        /* "TE1.00  " */
 342         0x0C,0x20,0x20,0x20,0x20,0x20,0x20,0x20
 343 };
 344
 345 MODULE_AUTHOR("Ed Lin");
 346 MODULE_DESCRIPTION("Promise Technology SuperTrak EX Controllers");
 347 MODULE_LICENSE("GPL");
 348 MODULE_VERSION(ST_DRIVER_VERSION);
 349
 350 static void stex_gettime(__le32 *time)
 351 {
 352         struct timeval tv;
 353         do_gettimeofday(&tv);
 354
 355         *time = cpu_to_le32(tv.tv_sec & 0xffffffff);
 356         *(time + 1) = cpu_to_le32((tv.tv_sec >> 16) >> 16);
 357 }
 358
 359 static struct status_msg *stex_get_status(struct st_hba *hba)
 360 {
 361         struct status_msg *status =
 362                 hba->status_buffer + hba->status_tail;
 363
 364         ++hba->status_tail;
 365         hba->status_tail %= MU_STATUS_COUNT;
 366
 367         return status;
 368 }
 369
 370 static void stex_set_sense(struct scsi_cmnd *cmd, u8 sk, u8 asc, u8 ascq)
 371 {
 372         cmd->result = (DRIVER_SENSE << 24) | SAM_STAT_CHECK_CONDITION;
 373
 374         cmd->sense_buffer[0] = 0x70;    /* fixed format, current */
 375         cmd->sense_buffer[2] = sk;
 376         cmd->sense_buffer[7] = 18 - 8;  /* additional sense length */
 377         cmd->sense_buffer[12] = asc;
 378         cmd->sense_buffer[13] = ascq;
 379 }
 380
 381 static void stex_invalid_field(struct scsi_cmnd *cmd,
 382                                void (*done)(struct scsi_cmnd *))
 383 {
 384         /* "Invalid field in cbd" */
 385         stex_set_sense(cmd, ILLEGAL_REQUEST, 0x24, 0x0);
 386         done(cmd);
 387 }
 388
 389 static struct req_msg *stex_alloc_req(struct st_hba *hba)
 390 {
 391         struct req_msg *req = ((struct req_msg *)hba->dma_mem) +
 392                 hba->req_head;
 393
 394         ++hba->req_head;
 395         hba->req_head %= MU_REQ_COUNT;
 396
 397         return req;
 398 }
 399
 400 static int stex_map_sg(struct st_hba *hba,
 401         struct req_msg *req, struct st_ccb *ccb)
 402 {
 403         struct pci_dev *pdev = hba->pdev;
 404         struct scsi_cmnd *cmd;
 405         dma_addr_t dma_handle;
 406         struct scatterlist *src;
 407         struct st_sgtable *dst;
 408         int i;
 409
 410         cmd = ccb->cmd;
 411         dst = (struct st_sgtable *)req->variable;
 412         dst->max_sg_count = cpu_to_le16(ST_MAX_SG);
 413         dst->sz_in_byte = cpu_to_le32(cmd->request_bufflen);
 414
 415         if (cmd->use_sg) {
 416                 int n_elem;
 417
 418                 src = (struct scatterlist *) cmd->request_buffer;
 419                 n_elem = pci_map_sg(pdev, src,
 420                         cmd->use_sg, cmd->sc_data_direction);
 421                 if (n_elem <= 0)
 422                         return -EIO;
 423
 424                 ccb->sg_count = n_elem;
 425                 dst->sg_count = cpu_to_le16((u16)n_elem);
 426
 427                 for (i = 0; i < n_elem; i++, src++) {
 428                         dst->table[i].count = cpu_to_le32((u32)sg_dma_len(src));
 429                         dst->table[i].addr =
 430                                 cpu_to_le32(sg_dma_address(src) & 0xffffffff);
 431                         dst->table[i].addr_hi =
 432                                 cpu_to_le32((sg_dma_address(src) >> 16) >> 16);
 433                         dst->table[i].ctrl = SG_CF_64B | SG_CF_HOST;
 434                 }
 435                 dst->table[--i].ctrl |= SG_CF_EOT;
 436                 return 0;
 437         }
 438
 439         dma_handle = pci_map_single(pdev, cmd->request_buffer,
 440                 cmd->request_bufflen, cmd->sc_data_direction);
 441         cmd->SCp.dma_handle = dma_handle;
 442
 443         ccb->sg_count = 1;
 444         dst->sg_count = cpu_to_le16(1);
 445         dst->table[0].addr = cpu_to_le32(dma_handle & 0xffffffff);
 446         dst->table[0].addr_hi = cpu_to_le32((dma_handle >> 16) >> 16);
 447         dst->table[0].count = cpu_to_le32((u32)cmd->request_bufflen);
 448         dst->table[0].ctrl = SG_CF_EOT | SG_CF_64B | SG_CF_HOST;
 449
 450         return 0;
 451 }
 452
 453 static void stex_internal_copy(struct scsi_cmnd *cmd,
 454         const void *src, size_t *count, int sg_count, int direction)
 455 {
 456         size_t lcount;
 457         size_t len;
 458         void *s, *d, *base = NULL;
 459         if (*count > cmd->request_bufflen)
 460                 *count = cmd->request_bufflen;
 461         lcount = *count;
 462         while (lcount) {
 463                 len = lcount;
 464                 s = (void *)src;
 465                 if (cmd->use_sg) {
 466                         size_t offset = *count - lcount;
 467                         s += offset;
 468                         base = scsi_kmap_atomic_sg(cmd->request_buffer,
 469                                 sg_count, &offset, &len);
 470                         if (base == NULL) {
 471                                 *count -= lcount;
 472                                 return;
 473                         }
 474                         d = base + offset;
 475                 } else
 476                         d = cmd->request_buffer;
 477
 478                 if (direction == ST_TO_CMD)
 479                         memcpy(d, s, len);
 480                 else
 481                         memcpy(s, d, len);
 482
 483                 lcount -= len;
 484                 if (cmd->use_sg)
 485                         scsi_kunmap_atomic_sg(base);
 486         }
 487 }
 488
 489 static int stex_direct_copy(struct scsi_cmnd *cmd,
 490         const void *src, size_t count)
 491 {
 492         struct st_hba *hba = (struct st_hba *) &cmd->device->host->hostdata[0];
 493         size_t cp_len = count;
 494         int n_elem = 0;
 495
 496         if (cmd->use_sg) {
 497                 n_elem = pci_map_sg(hba->pdev, cmd->request_buffer,
 498                         cmd->use_sg, cmd->sc_data_direction);
 499                 if (n_elem <= 0)
 500                         return 0;
 501         }
 502
 503         stex_internal_copy(cmd, src, &cp_len, n_elem, ST_TO_CMD);
 504
 505         if (cmd->use_sg)
 506                 pci_unmap_sg(hba->pdev, cmd->request_buffer,
 507                         cmd->use_sg, cmd->sc_data_direction);
 508         return cp_len == count;
 509 }
 510
 511 static void stex_controller_info(struct st_hba *hba, struct st_ccb *ccb)
 512 {
 513         struct st_frame *p;
 514         size_t count = sizeof(struct st_frame);
 515
 516         p = hba->copy_buffer;
 517         stex_internal_copy(ccb->cmd, p, &count, ccb->sg_count, ST_FROM_CMD);
 518         memset(p->base, 0, sizeof(u32)*6);
 519         *(unsigned long *)(p->base) = pci_resource_start(hba->pdev, 0);
 520         p->rom_addr = 0;
 521
 522         p->drv_ver.major = ST_VER_MAJOR;
 523         p->drv_ver.minor = ST_VER_MINOR;
 524         p->drv_ver.oem = ST_OEM;
 525         p->drv_ver.build = ST_BUILD_VER;
 526
 527         p->bus = hba->pdev->bus->number;
 528         p->slot = hba->pdev->devfn;
 529         p->irq_level = 0;
 530         p->irq_vec = hba->pdev->irq;
 531         p->id = hba->pdev->vendor << 16 | hba->pdev->device;
 532         p->subid =
 533                 hba->pdev->subsystem_vendor << 16 | hba->pdev->subsystem_device;
 534
 535         stex_internal_copy(ccb->cmd, p, &count, ccb->sg_count, ST_TO_CMD);
 536 }
 537
 538 static void
 539 stex_send_cmd(struct st_hba *hba, struct req_msg *req, u16 tag)
 540 {
 541         req->tag = cpu_to_le16(tag);
 542         req->task_attr = TASK_ATTRIBUTE_SIMPLE;
 543         req->task_manage = 0; /* not supported yet */
 544
 545         hba->ccb[tag].req = req;
 546         hba->out_req_cnt++;
 547
 548         writel(hba->req_head, hba->mmio_base + IMR0);
 549         writel(MU_INBOUND_DOORBELL_REQHEADCHANGED, hba->mmio_base + IDBL);
 550         readl(hba->mmio_base + IDBL); /* flush */
 551 }
 552
 553 static int
 554 stex_slave_alloc(struct scsi_device *sdev)
 555 {
 556         /* Cheat: usually extracted from Inquiry data */
 557         sdev->tagged_supported = 1;
 558
 559         scsi_activate_tcq(sdev, sdev->host->can_queue);
 560
 561         return 0;
 562 }
 563
 564 static int
 565 stex_slave_config(struct scsi_device *sdev)
 566 {
 567         sdev->use_10_for_rw = 1;
 568         sdev->use_10_for_ms = 1;
 569         sdev->timeout = 60 * HZ;
 570         sdev->tagged_supported = 1;
 571
 572         return 0;
 573 }
 574
 575 static void
 576 stex_slave_destroy(struct scsi_device *sdev)
 577 {
 578         scsi_deactivate_tcq(sdev, 1);
 579 }
 580
 581 static int
 582 stex_queuecommand(struct scsi_cmnd *cmd, void (* done)(struct scsi_cmnd *))
 583 {
 584         struct st_hba *hba;
 585         struct Scsi_Host *host;
 586         unsigned int id,lun;
 587         struct req_msg *req;
 588         u16 tag;
 589         host = cmd->device->host;
 590         id = cmd->device->id;
 591         lun = cmd->device->channel; /* firmware lun issue work around */
 592         hba = (struct st_hba *) &host->hostdata[0];
 593
 594         switch (cmd->cmnd[0]) {
 595         case MODE_SENSE_10:
 596         {
 597                 static char ms10_caching_page[12] =
 598                         { 0, 0x12, 0, 0, 0, 0, 0, 0, 0x8, 0xa, 0x4, 0 };
 599                 unsigned char page;
 600                 page = cmd->cmnd[2] & 0x3f;
 601                 if (page == 0x8 || page == 0x3f) {
 602                         stex_direct_copy(cmd, ms10_caching_page,
 603                                         sizeof(ms10_caching_page));
 604                         cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
 605                         done(cmd);
 606                 } else
 607                         stex_invalid_field(cmd, done);
 608                 return 0;
 609         }
 610         case INQUIRY:
 611                 if (id != ST_MAX_ARRAY_SUPPORTED)
 612                         break;
 613                 if (lun == 0 && (cmd->cmnd[1] & INQUIRY_EVPD) == 0) {
 614                         stex_direct_copy(cmd, console_inq_page,
 615                                 sizeof(console_inq_page));
 616                         cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
 617                         done(cmd);
 618                 } else
 619                         stex_invalid_field(cmd, done);
 620                 return 0;
 621         case PASSTHRU_CMD:
 622                 if (cmd->cmnd[1] == PASSTHRU_GET_DRVVER) {
 623                         struct st_drvver ver;
 624                         ver.major = ST_VER_MAJOR;
 625                         ver.minor = ST_VER_MINOR;
 626                         ver.oem = ST_OEM;
 627                         ver.build = ST_BUILD_VER;
 628                         ver.signature[0] = PASSTHRU_SIGNATURE;
 629                         ver.console_id = ST_MAX_ARRAY_SUPPORTED;
 630                         ver.host_no = hba->host->host_no;
 631                         cmd->result = stex_direct_copy(cmd, &ver, sizeof(ver)) ?
 632                                 DID_OK << 16 | COMMAND_COMPLETE << 8 :
 633                                 DID_ERROR << 16 | COMMAND_COMPLETE << 8;
 634                         done(cmd);
 635                         return 0;
 636                 }
 637         default:
 638                 break;
 639         }
 640
 641         cmd->scsi_done = done;
 642
 643         tag = cmd->request->tag;
 644
 645         if (unlikely(tag >= host->can_queue))
 646                 return SCSI_MLQUEUE_HOST_BUSY;
 647
 648         req = stex_alloc_req(hba);
 649
 650         if (hba->cardtype == st_yosemite) {
 651                 req->lun = lun * (ST_MAX_TARGET_NUM - 1) + id;
 652                 req->target = 0;
 653         } else {
 654                 req->lun = lun;
 655                 req->target = id;
 656         }
 657
 658         /* cdb */
 659         memcpy(req->cdb, cmd->cmnd, STEX_CDB_LENGTH);
 660
 661         hba->ccb[tag].cmd = cmd;
 662         hba->ccb[tag].sense_bufflen = SCSI_SENSE_BUFFERSIZE;
 663         hba->ccb[tag].sense_buffer = cmd->sense_buffer;
 664         hba->ccb[tag].req_type = 0;
 665
 666         if (cmd->sc_data_direction != DMA_NONE)
 667                 stex_map_sg(hba, req, &hba->ccb[tag]);
 668
 669         stex_send_cmd(hba, req, tag);
 670         return 0;
 671 }
 672
 673 static void stex_unmap_sg(struct st_hba *hba, struct scsi_cmnd *cmd)
 674 {
 675         if (cmd->sc_data_direction != DMA_NONE) {
 676                 if (cmd->use_sg)
 677                         pci_unmap_sg(hba->pdev, cmd->request_buffer,
 678                                 cmd->use_sg, cmd->sc_data_direction);
 679                 else
 680                         pci_unmap_single(hba->pdev, cmd->SCp.dma_handle,
 681                                 cmd->request_bufflen, cmd->sc_data_direction);
 682         }
 683 }
 684
 685 static void stex_scsi_done(struct st_ccb *ccb)
 686 {
 687         struct scsi_cmnd *cmd = ccb->cmd;
 688         int result;
 689
 690         if (ccb->srb_status == SRB_STATUS_SUCCESS ||  ccb->srb_status == 0) {
 691                 result = ccb->scsi_status;
 692                 switch (ccb->scsi_status) {
 693                 case SAM_STAT_GOOD:
 694                         result |= DID_OK << 16 | COMMAND_COMPLETE << 8;
 695                         break;
 696                 case SAM_STAT_CHECK_CONDITION:
 697                         result |= DRIVER_SENSE << 24;
 698                         break;
 699                 case SAM_STAT_BUSY:
 700                         result |= DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8;
 701                         break;
 702                 default:
 703                         result |= DID_ERROR << 16 | COMMAND_COMPLETE << 8;
 704                         break;
 705                 }
 706         }
 707         else if (ccb->srb_status & SRB_SEE_SENSE)
 708                 result = DRIVER_SENSE << 24 | SAM_STAT_CHECK_CONDITION;
 709         else switch (ccb->srb_status) {
 710                 case SRB_STATUS_SELECTION_TIMEOUT:
 711                         result = DID_NO_CONNECT << 16 | COMMAND_COMPLETE << 8;
 712                         break;
 713                 case SRB_STATUS_BUSY:
 714                         result = DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8;
 715                         break;
 716                 case SRB_STATUS_INVALID_REQUEST:
 717                 case SRB_STATUS_ERROR:
 718                 default:
 719                         result = DID_ERROR << 16 | COMMAND_COMPLETE << 8;
 720                         break;
 721         }
 722
 723         cmd->result = result;
 724         cmd->scsi_done(cmd);
 725 }
 726
 727 static void stex_copy_data(struct st_ccb *ccb,
 728         struct status_msg *resp, unsigned int variable)
 729 {
 730         size_t count = variable;
 731         if (resp->scsi_status != SAM_STAT_GOOD) {
 732                 if (ccb->sense_buffer != NULL)
 733                         memcpy(ccb->sense_buffer, resp->variable,
 734                                 min(variable, ccb->sense_bufflen));
 735                 return;
 736         }
 737
 738         if (ccb->cmd == NULL)
 739                 return;
 740         stex_internal_copy(ccb->cmd,
 741                 resp->variable, &count, ccb->sg_count, ST_TO_CMD);
 742 }
 743
 744 static void stex_ys_commands(struct st_hba *hba,
 745         struct st_ccb *ccb, struct status_msg *resp)
 746 {
 747         size_t count;
 748
 749         if (ccb->cmd->cmnd[0] == MGT_CMD &&
 750                 resp->scsi_status != SAM_STAT_CHECK_CONDITION) {
 751                 ccb->cmd->request_bufflen =
 752                         le32_to_cpu(*(__le32 *)&resp->variable[0]);
 753                 return;
 754         }
 755
 756         if (resp->srb_status != 0)
 757                 return;
 758
 759         /* determine inquiry command status by DeviceTypeQualifier */
 760         if (ccb->cmd->cmnd[0] == INQUIRY &&
 761                 resp->scsi_status == SAM_STAT_GOOD) {
 762                 ST_INQ *inq_data;
 763
 764                 count = STEX_EXTRA_SIZE;
 765                 stex_internal_copy(ccb->cmd, hba->copy_buffer,
 766                         &count, ccb->sg_count, ST_FROM_CMD);
 767                 inq_data = (ST_INQ *)hba->copy_buffer;
 768                 if (inq_data->DeviceTypeQualifier != 0)
 769                         ccb->srb_status = SRB_STATUS_SELECTION_TIMEOUT;
 770                 else
 771                         ccb->srb_status = SRB_STATUS_SUCCESS;
 772         } else if (ccb->cmd->cmnd[0] == REPORT_LUNS) {
 773                 u8 *report_lun_data = (u8 *)hba->copy_buffer;
 774
 775                 count = STEX_EXTRA_SIZE;
 776                 stex_internal_copy(ccb->cmd, report_lun_data,
 777                         &count, ccb->sg_count, ST_FROM_CMD);
 778                 if (report_lun_data[2] || report_lun_data[3]) {
 779                         report_lun_data[2] = 0x00;
 780                         report_lun_data[3] = 0x08;
 781                         stex_internal_copy(ccb->cmd, report_lun_data,
 782                                 &count, ccb->sg_count, ST_TO_CMD);
 783                 }
 784         }
 785 }
 786
 787 static void stex_mu_intr(struct st_hba *hba, u32 doorbell)
 788 {
 789         void __iomem *base = hba->mmio_base;
 790         struct status_msg *resp;
 791         struct st_ccb *ccb;
 792         unsigned int size;
 793         u16 tag;
 794
 795         if (!(doorbell & MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED))
 796                 return;
 797
 798         /* status payloads */
 799         hba->status_head = readl(base + OMR1);
 800         if (unlikely(hba->status_head >= MU_STATUS_COUNT)) {
 801                 printk(KERN_WARNING DRV_NAME "(%s): invalid status head\n",
 802                         pci_name(hba->pdev));
 803                 return;
 804         }
 805
 806         /*
 807          * it's not a valid status payload if:
 808          * 1. there are no pending requests(e.g. during init stage)
 809          * 2. there are some pending requests, but the controller is in
 810          *     reset status, and its type is not st_yosemite
 811          * firmware of st_yosemite in reset status will return pending requests
 812          * to driver, so we allow it to pass
 813          */
 814         if (unlikely(hba->out_req_cnt <= 0 ||
 815                         (hba->mu_status == MU_STATE_RESETTING &&
 816                          hba->cardtype != st_yosemite))) {
 817                 hba->status_tail = hba->status_head;
 818                 goto update_status;
 819         }
 820
 821         while (hba->status_tail != hba->status_head) {
 822                 resp = stex_get_status(hba);
 823                 tag = le16_to_cpu(resp->tag);
 824                 if (unlikely(tag >= hba->host->can_queue)) {
 825                         printk(KERN_WARNING DRV_NAME
 826                                 "(%s): invalid tag\n", pci_name(hba->pdev));
 827                         continue;
 828                 }
 829
 830                 ccb = &hba->ccb[tag];
 831                 if (hba->wait_ccb == ccb)
 832                         hba->wait_ccb = NULL;
 833                 if (unlikely(ccb->req == NULL)) {
 834                         printk(KERN_WARNING DRV_NAME
 835                                 "(%s): lagging req\n", pci_name(hba->pdev));
 836                         hba->out_req_cnt--;
 837                         continue;
 838                 }
 839
 840                 size = resp->payload_sz * sizeof(u32); /* payload size */
 841                 if (unlikely(size < sizeof(*resp) - STATUS_VAR_LEN ||
 842                         size > sizeof(*resp))) {
 843                         printk(KERN_WARNING DRV_NAME "(%s): bad status size\n",
 844                                 pci_name(hba->pdev));
 845                 } else {
 846                         size -= sizeof(*resp) - STATUS_VAR_LEN; /* copy size */
 847                         if (size)
 848                                 stex_copy_data(ccb, resp, size);
 849                 }
 850
 851                 ccb->srb_status = resp->srb_status;
 852                 ccb->scsi_status = resp->scsi_status;
 853
 854                 if (likely(ccb->cmd != NULL)) {
 855                         if (hba->cardtype == st_yosemite)
 856                                 stex_ys_commands(hba, ccb, resp);
 857
 858                         if (unlikely(ccb->cmd->cmnd[0] == PASSTHRU_CMD &&
 859                                 ccb->cmd->cmnd[1] == PASSTHRU_GET_ADAPTER))
 860                                 stex_controller_info(hba, ccb);
 861
 862                         stex_unmap_sg(hba, ccb->cmd);
 863                         stex_scsi_done(ccb);
 864                         hba->out_req_cnt--;
 865                 } else if (ccb->req_type & PASSTHRU_REQ_TYPE) {
 866                         hba->out_req_cnt--;
 867                         if (ccb->req_type & PASSTHRU_REQ_NO_WAKEUP) {
 868                                 ccb->req_type = 0;
 869                                 continue;
 870                         }
 871                         ccb->req_type = 0;
 872                         if (waitqueue_active(&hba->waitq))
 873                                 wake_up(&hba->waitq);
 874                 }
 875         }
 876
 877 update_status:
 878         writel(hba->status_head, base + IMR1);
 879         readl(base + IMR1); /* flush */
 880 }
 881
 882 static irqreturn_t stex_intr(int irq, void *__hba)
 883 {
 884         struct st_hba *hba = __hba;
 885         void __iomem *base = hba->mmio_base;
 886         u32 data;
 887         unsigned long flags;
 888         int handled = 0;
 889
 890         spin_lock_irqsave(hba->host->host_lock, flags);
 891
 892         data = readl(base + ODBL);
 893
 894         if (data && data != 0xffffffff) {
 895                 /* clear the interrupt */
 896                 writel(data, base + ODBL);
 897                 readl(base + ODBL); /* flush */
 898                 stex_mu_intr(hba, data);
 899                 handled = 1;
 900         }
 901
 902         spin_unlock_irqrestore(hba->host->host_lock, flags);
 903
 904         return IRQ_RETVAL(handled);
 905 }
 906
 907 static int stex_handshake(struct st_hba *hba)
 908 {
 909         void __iomem *base = hba->mmio_base;
 910         struct handshake_frame *h;
 911         dma_addr_t status_phys;
 912         u32 data;
 913         int i;
 914
 915         if (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
 916                 writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
 917                 readl(base + IDBL);
 918                 for (i = 0; readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE
 919                         && i < MU_MAX_DELAY_TIME; i++) {
 920                         rmb();
 921                         msleep(1);
 922                 }
 923
 924                 if (i == MU_MAX_DELAY_TIME) {
 925                         printk(KERN_ERR DRV_NAME
 926                                 "(%s): no handshake signature\n",
 927                                 pci_name(hba->pdev));
 928                         return -1;
 929                 }
 930         }
 931
 932         udelay(10);
 933
 934         data = readl(base + OMR1);
 935         if ((data & 0xffff0000) == MU_HANDSHAKE_SIGNATURE_HALF) {
 936                 data &= 0x0000ffff;
 937                 if (hba->host->can_queue > data)
 938                         hba->host->can_queue = data;
 939         }
 940
 941         h = (struct handshake_frame *)(hba->dma_mem + MU_REQ_BUFFER_SIZE);
 942         h->rb_phy = cpu_to_le32(hba->dma_handle);
 943         h->rb_phy_hi = cpu_to_le32((hba->dma_handle >> 16) >> 16);
 944         h->req_sz = cpu_to_le16(sizeof(struct req_msg));
 945         h->req_cnt = cpu_to_le16(MU_REQ_COUNT);
 946         h->status_sz = cpu_to_le16(sizeof(struct status_msg));
 947         h->status_cnt = cpu_to_le16(MU_STATUS_COUNT);
 948         stex_gettime(&h->hosttime);
 949         h->partner_type = HMU_PARTNER_TYPE;
 950         if (hba->dma_size > STEX_BUFFER_SIZE) {
 951                 h->extra_offset = cpu_to_le32(STEX_BUFFER_SIZE);
 952                 h->extra_size = cpu_to_le32(ST_ADDITIONAL_MEM);
 953         } else
 954                 h->extra_offset = h->extra_size = 0;
 955
 956         status_phys = hba->dma_handle + MU_REQ_BUFFER_SIZE;
 957         writel(status_phys, base + IMR0);
 958         readl(base + IMR0);
 959         writel((status_phys >> 16) >> 16, base + IMR1);
 960         readl(base + IMR1);
 961
 962         writel((status_phys >> 16) >> 16, base + OMR0); /* old fw compatible */
 963         readl(base + OMR0);
 964         writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
 965         readl(base + IDBL); /* flush */
 966
 967         udelay(10);
 968         for (i = 0; readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE
 969                 && i < MU_MAX_DELAY_TIME; i++) {
 970                 rmb();
 971                 msleep(1);
 972         }
 973
 974         if (i == MU_MAX_DELAY_TIME) {
 975                 printk(KERN_ERR DRV_NAME
 976                         "(%s): no signature after handshake frame\n",
 977                         pci_name(hba->pdev));
 978                 return -1;
 979         }
 980
 981         writel(0, base + IMR0);
 982         readl(base + IMR0);
 983         writel(0, base + OMR0);
 984         readl(base + OMR0);
 985         writel(0, base + IMR1);
 986         readl(base + IMR1);
 987         writel(0, base + OMR1);
 988         readl(base + OMR1); /* flush */
 989         hba->mu_status = MU_STATE_STARTED;
 990         return 0;
 991 }
 992
 993 static int stex_abort(struct scsi_cmnd *cmd)
 994 {
 995         struct Scsi_Host *host = cmd->device->host;
 996         struct st_hba *hba = (struct st_hba *)host->hostdata;
 997         u16 tag = cmd->request->tag;
 998         void __iomem *base;
 999         u32 data;
1000         int result = SUCCESS;
1001         unsigned long flags;
1002         base = hba->mmio_base;
1003         spin_lock_irqsave(host->host_lock, flags);
1004         if (tag < host->can_queue && hba->ccb[tag].cmd == cmd)
1005                 hba->wait_ccb = &hba->ccb[tag];
1006         else {
1007                 for (tag = 0; tag < host->can_queue; tag++)
1008                         if (hba->ccb[tag].cmd == cmd) {
1009                                 hba->wait_ccb = &hba->ccb[tag];
1010                                 break;
1011                         }
1012                 if (tag >= host->can_queue)
1013                         goto out;
1014         }
1015
1016         data = readl(base + ODBL);
1017         if (data == 0 || data == 0xffffffff)
1018                 goto fail_out;
1019
1020         writel(data, base + ODBL);
1021         readl(base + ODBL); /* flush */
1022
1023         stex_mu_intr(hba, data);
1024
1025         if (hba->wait_ccb == NULL) {
1026                 printk(KERN_WARNING DRV_NAME
1027                         "(%s): lost interrupt\n", pci_name(hba->pdev));
1028                 goto out;
1029         }
1030
1031 fail_out:
1032         stex_unmap_sg(hba, cmd);
1033         hba->wait_ccb->req = NULL; /* nullify the req's future return */
1034         hba->wait_ccb = NULL;
1035         result = FAILED;
1036 out:
1037         spin_unlock_irqrestore(host->host_lock, flags);
1038         return result;
1039 }
1040
1041 static void stex_hard_reset(struct st_hba *hba)
1042 {
1043         struct pci_bus *bus;
1044         int i;
1045         u16 pci_cmd;
1046         u8 pci_bctl;
1047
1048         for (i = 0; i < 16; i++)
1049                 pci_read_config_dword(hba->pdev, i * 4,
1050                         &hba->pdev->saved_config_space[i]);
1051
1052         /* Reset secondary bus. Our controller(MU/ATU) is the only device on
1053            secondary bus. Consult Intel 80331/3 developer's manual for detail */
1054         bus = hba->pdev->bus;
1055         pci_read_config_byte(bus->self, PCI_BRIDGE_CONTROL, &pci_bctl);
1056         pci_bctl |= PCI_BRIDGE_CTL_BUS_RESET;
1057         pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
1058         msleep(1);
1059         pci_bctl &= ~PCI_BRIDGE_CTL_BUS_RESET;
1060         pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
1061
1062         for (i = 0; i < MU_MAX_DELAY_TIME; i++) {
1063                 pci_read_config_word(hba->pdev, PCI_COMMAND, &pci_cmd);
1064                 if (pci_cmd != 0xffff && (pci_cmd & PCI_COMMAND_MASTER))
1065                         break;
1066                 msleep(1);
1067         }
1068
1069         ssleep(5);
1070         for (i = 0; i < 16; i++)
1071                 pci_write_config_dword(hba->pdev, i * 4,
1072                         hba->pdev->saved_config_space[i]);
1073 }
1074
1075 static int stex_reset(struct scsi_cmnd *cmd)
1076 {
1077         struct st_hba *hba;
1078         unsigned long flags;
1079         unsigned long before;
1080         hba = (struct st_hba *) &cmd->device->host->hostdata[0];
1081
1082         hba->mu_status = MU_STATE_RESETTING;
1083
1084         if (hba->cardtype == st_shasta)
1085                 stex_hard_reset(hba);
1086
1087         if (hba->cardtype != st_yosemite) {
1088                 if (stex_handshake(hba)) {
1089                         printk(KERN_WARNING DRV_NAME
1090                                 "(%s): resetting: handshake failed\n",
1091                                 pci_name(hba->pdev));
1092                         return FAILED;
1093                 }
1094                 spin_lock_irqsave(hba->host->host_lock, flags);
1095                 hba->req_head = 0;
1096                 hba->req_tail = 0;
1097                 hba->status_head = 0;
1098                 hba->status_tail = 0;
1099                 hba->out_req_cnt = 0;
1100                 spin_unlock_irqrestore(hba->host->host_lock, flags);
1101                 return SUCCESS;
1102         }
1103
1104         /* st_yosemite */
1105         writel(MU_INBOUND_DOORBELL_RESET, hba->mmio_base + IDBL);
1106         readl(hba->mmio_base + IDBL); /* flush */
1107         before = jiffies;
1108         while (hba->out_req_cnt > 0) {
1109                 if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ)) {
1110                         printk(KERN_WARNING DRV_NAME
1111                                 "(%s): reset timeout\n", pci_name(hba->pdev));
1112                         return FAILED;
1113                 }
1114                 msleep(1);
1115         }
1116
1117         hba->mu_status = MU_STATE_STARTED;
1118         return SUCCESS;
1119 }
1120
1121 static int stex_biosparam(struct scsi_device *sdev,
1122         struct block_device *bdev, sector_t capacity, int geom[])
1123 {
1124         int heads = 255, sectors = 63;
1125
1126         if (capacity < 0x200000) {
1127                 heads = 64;
1128                 sectors = 32;
1129         }
1130
1131         sector_div(capacity, heads * sectors);
1132
1133         geom[0] = heads;
1134         geom[1] = sectors;
1135         geom[2] = capacity;
1136
1137         return 0;
1138 }
1139
1140 static struct scsi_host_template driver_template = {
1141         .module                         = THIS_MODULE,
1142         .name                           = DRV_NAME,
1143         .proc_name                      = DRV_NAME,
1144         .bios_param                     = stex_biosparam,
1145         .queuecommand                   = stex_queuecommand,
1146         .slave_alloc                    = stex_slave_alloc,
1147         .slave_configure                = stex_slave_config,
1148         .slave_destroy                  = stex_slave_destroy,
1149         .eh_abort_handler               = stex_abort,
1150         .eh_host_reset_handler          = stex_reset,
1151         .can_queue                      = ST_CAN_QUEUE,
1152         .this_id                        = -1,
1153         .sg_tablesize                   = ST_MAX_SG,
1154         .cmd_per_lun                    = ST_CMD_PER_LUN,
1155 };
1156
1157 static int stex_set_dma_mask(struct pci_dev * pdev)
1158 {
1159         int ret;
1160         if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)
1161                 && !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))
1162                 return 0;
1163         ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1164         if (!ret)
1165                 ret = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1166         return ret;
1167 }
1168
1169 static int __devinit
1170 stex_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1171 {
1172         struct st_hba *hba;
1173         struct Scsi_Host *host;
1174         int err;
1175
1176         err = pci_enable_device(pdev);
1177         if (err)
1178                 return err;
1179
1180         pci_set_master(pdev);
1181
1182         host = scsi_host_alloc(&driver_template, sizeof(struct st_hba));
1183
1184         if (!host) {
1185                 printk(KERN_ERR DRV_NAME "(%s): scsi_host_alloc failed\n",
1186                         pci_name(pdev));
1187                 err = -ENOMEM;
1188                 goto out_disable;
1189         }
1190
1191         hba = (struct st_hba *)host->hostdata;
1192         memset(hba, 0, sizeof(struct st_hba));
1193
1194         err = pci_request_regions(pdev, DRV_NAME);
1195         if (err < 0) {
1196                 printk(KERN_ERR DRV_NAME "(%s): request regions failed\n",
1197                         pci_name(pdev));
1198                 goto out_scsi_host_put;
1199         }
1200
1201         hba->mmio_base = ioremap(pci_resource_start(pdev, 0),
1202                 pci_resource_len(pdev, 0));
1203         if ( !hba->mmio_base) {
1204                 printk(KERN_ERR DRV_NAME "(%s): memory map failed\n",
1205                         pci_name(pdev));
1206                 err = -ENOMEM;
1207                 goto out_release_regions;
1208         }
1209
1210         err = stex_set_dma_mask(pdev);
1211         if (err) {
1212                 printk(KERN_ERR DRV_NAME "(%s): set dma mask failed\n",
1213                         pci_name(pdev));
1214                 goto out_iounmap;
1215         }
1216
1217         hba->cardtype = (unsigned int) id->driver_data;
1218         if (hba->cardtype == st_vsc && (pdev->subsystem_device & 0xf) == 0x1)
1219                 hba->cardtype = st_vsc1;
1220         hba->dma_size = (hba->cardtype == st_vsc1) ?
1221                 (STEX_BUFFER_SIZE + ST_ADDITIONAL_MEM) : (STEX_BUFFER_SIZE);
1222         hba->dma_mem = dma_alloc_coherent(&pdev->dev,
1223                 hba->dma_size, &hba->dma_handle, GFP_KERNEL);
1224         if (!hba->dma_mem) {
1225                 err = -ENOMEM;
1226                 printk(KERN_ERR DRV_NAME "(%s): dma mem alloc failed\n",
1227                         pci_name(pdev));
1228                 goto out_iounmap;
1229         }
1230
1231         hba->status_buffer =
1232                 (struct status_msg *)(hba->dma_mem + MU_REQ_BUFFER_SIZE);
1233         hba->copy_buffer = hba->dma_mem + MU_BUFFER_SIZE;
1234         hba->mu_status = MU_STATE_STARTING;
1235
1236         /* firmware uses id/lun pair for a logical drive, but lun would be
1237            always 0 if CONFIG_SCSI_MULTI_LUN not configured, so we use
1238            channel to map lun here */
1239         host->max_channel = ST_MAX_LUN_PER_TARGET - 1;
1240         host->max_id = ST_MAX_TARGET_NUM;
1241         host->max_lun = 1;
1242         host->unique_id = host->host_no;
1243         host->max_cmd_len = STEX_CDB_LENGTH;
1244
1245         hba->host = host;
1246         hba->pdev = pdev;
1247         init_waitqueue_head(&hba->waitq);
1248
1249         err = request_irq(pdev->irq, stex_intr, IRQF_SHARED, DRV_NAME, hba);
1250         if (err) {
1251                 printk(KERN_ERR DRV_NAME "(%s): request irq failed\n",
1252                         pci_name(pdev));
1253                 goto out_pci_free;
1254         }
1255
1256         err = stex_handshake(hba);
1257         if (err)
1258                 goto out_free_irq;
1259
1260         err = scsi_init_shared_tag_map(host, host->can_queue);
1261         if (err) {
1262                 printk(KERN_ERR DRV_NAME "(%s): init shared queue failed\n",
1263                         pci_name(pdev));
1264                 goto out_free_irq;
1265         }
1266
1267         pci_set_drvdata(pdev, hba);
1268
1269         err = scsi_add_host(host, &pdev->dev);
1270         if (err) {
1271                 printk(KERN_ERR DRV_NAME "(%s): scsi_add_host failed\n",
1272                         pci_name(pdev));
1273                 goto out_free_irq;
1274         }
1275
1276         scsi_scan_host(host);
1277
1278         return 0;
1279
1280 out_free_irq:
1281         free_irq(pdev->irq, hba);
1282 out_pci_free:
1283         dma_free_coherent(&pdev->dev, hba->dma_size,
1284                           hba->dma_mem, hba->dma_handle);
1285 out_iounmap:
1286         iounmap(hba->mmio_base);
1287 out_release_regions:
1288         pci_release_regions(pdev);
1289 out_scsi_host_put:
1290         scsi_host_put(host);
1291 out_disable:
1292         pci_disable_device(pdev);
1293
1294         return err;
1295 }
1296
1297 static void stex_hba_stop(struct st_hba *hba)
1298 {
1299         struct req_msg *req;
1300         unsigned long flags;
1301         unsigned long before;
1302         u16 tag = 0;
1303
1304         spin_lock_irqsave(hba->host->host_lock, flags);
1305         req = stex_alloc_req(hba);
1306         memset(req->cdb, 0, STEX_CDB_LENGTH);
1307
1308         if (hba->cardtype == st_yosemite) {
1309                 req->cdb[0] = MGT_CMD;
1310                 req->cdb[1] = MGT_CMD_SIGNATURE;
1311                 req->cdb[2] = CTLR_CONFIG_CMD;
1312                 req->cdb[3] = CTLR_SHUTDOWN;
1313         } else {
1314                 req->cdb[0] = CONTROLLER_CMD;
1315                 req->cdb[1] = CTLR_POWER_STATE_CHANGE;
1316                 req->cdb[2] = CTLR_POWER_SAVING;
1317         }
1318
1319         hba->ccb[tag].cmd = NULL;
1320         hba->ccb[tag].sg_count = 0;
1321         hba->ccb[tag].sense_bufflen = 0;
1322         hba->ccb[tag].sense_buffer = NULL;
1323         hba->ccb[tag].req_type |= PASSTHRU_REQ_TYPE;
1324
1325         stex_send_cmd(hba, req, tag);
1326         spin_unlock_irqrestore(hba->host->host_lock, flags);
1327
1328         before = jiffies;
1329         while (hba->ccb[tag].req_type & PASSTHRU_REQ_TYPE) {
1330                 if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ))
1331                         return;
1332                 msleep(10);
1333         }
1334 }
1335
1336 static void stex_hba_free(struct st_hba *hba)
1337 {
1338         free_irq(hba->pdev->irq, hba);
1339
1340         iounmap(hba->mmio_base);
1341
1342         pci_release_regions(hba->pdev);
1343
1344         dma_free_coherent(&hba->pdev->dev, hba->dma_size,
1345                           hba->dma_mem, hba->dma_handle);
1346 }
1347
1348 static void stex_remove(struct pci_dev *pdev)
1349 {
1350         struct st_hba *hba = pci_get_drvdata(pdev);
1351
1352         scsi_remove_host(hba->host);
1353
1354         pci_set_drvdata(pdev, NULL);
1355
1356         stex_hba_stop(hba);
1357
1358         stex_hba_free(hba);
1359
1360         scsi_host_put(hba->host);
1361
1362         pci_disable_device(pdev);
1363 }
1364
1365 static void stex_shutdown(struct pci_dev *pdev)
1366 {
1367         struct st_hba *hba = pci_get_drvdata(pdev);
1368
1369         stex_hba_stop(hba);
1370 }
1371
1372 static struct pci_device_id stex_pci_tbl[] = {
1373         /* st_shasta */
1374         { 0x105a, 0x8350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1375                 st_shasta }, /* SuperTrak EX8350/8300/16350/16300 */
1376         { 0x105a, 0xc350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1377                 st_shasta }, /* SuperTrak EX12350 */
1378         { 0x105a, 0x4302, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1379                 st_shasta }, /* SuperTrak EX4350 */
1380         { 0x105a, 0xe350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1381                 st_shasta }, /* SuperTrak EX24350 */
1382
1383         /* st_vsc */
1384         { 0x105a, 0x7250, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_vsc },
1385
1386         /* st_yosemite */
1387         { 0x105a, 0x8650, PCI_ANY_ID, 0x4600, 0, 0,
1388                 st_yosemite }, /* SuperTrak EX4650 */
1389         { 0x105a, 0x8650, PCI_ANY_ID, 0x4610, 0, 0,
1390                 st_yosemite }, /* SuperTrak EX4650o */
1391         { 0x105a, 0x8650, PCI_ANY_ID, 0x8600, 0, 0,
1392                 st_yosemite }, /* SuperTrak EX8650EL */
1393         { 0x105a, 0x8650, PCI_ANY_ID, 0x8601, 0, 0,
1394                 st_yosemite }, /* SuperTrak EX8650 */
1395         { 0x105a, 0x8650, PCI_ANY_ID, 0x8602, 0, 0,
1396                 st_yosemite }, /* SuperTrak EX8654 */
1397         { 0x105a, 0x8650, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1398                 st_yosemite }, /* generic st_yosemite */
1399         { }     /* terminate list */
1400 };
1401 MODULE_DEVICE_TABLE(pci, stex_pci_tbl);
1402
1403 static struct pci_driver stex_pci_driver = {
1404         .name           = DRV_NAME,
1405         .id_table       = stex_pci_tbl,
1406         .probe          = stex_probe,
1407         .remove         = __devexit_p(stex_remove),
1408         .shutdown       = stex_shutdown,
1409 };
1410
1411 static int __init stex_init(void)
1412 {
1413         printk(KERN_INFO DRV_NAME
1414                 ": Promise SuperTrak EX Driver version: %s\n",
1415                  ST_DRIVER_VERSION);
1416
1417         return pci_register_driver(&stex_pci_driver);
1418 }
1419
1420 static void __exit stex_exit(void)
1421 {
1422         pci_unregister_driver(&stex_pci_driver);
1423 }
1424
1425 module_init(stex_init);
1426 module_exit(stex_exit);