drivers/scsi/stex.c

   1 /*
   2  * SuperTrak EX Series Storage Controller driver for Linux
   3  *
   4  *      Copyright (C) 2005-2009 Promise Technology Inc.
   5  *
   6  *      This program is free software; you can redistribute it and/or
   7  *      modify it under the terms of the GNU General Public License
   8  *      as published by the Free Software Foundation; either version
   9  *      2 of the License, or (at your option) any later version.
  10  *
  11  *      Written By:
  12  *              Ed Lin <promise_linux@promise.com>
  13  *
  14  */
  15
  16 #include <linux/init.h>
  17 #include <linux/errno.h>
  18 #include <linux/kernel.h>
  19 #include <linux/delay.h>
  20 #include <linux/slab.h>
  21 #include <linux/time.h>
  22 #include <linux/pci.h>
  23 #include <linux/blkdev.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/types.h>
  26 #include <linux/module.h>
  27 #include <linux/spinlock.h>
  28 #include <asm/io.h>
  29 #include <asm/irq.h>
  30 #include <asm/byteorder.h>
  31 #include <scsi/scsi.h>
  32 #include <scsi/scsi_device.h>
  33 #include <scsi/scsi_cmnd.h>
  34 #include <scsi/scsi_host.h>
  35 #include <scsi/scsi_tcq.h>
  36 #include <scsi/scsi_dbg.h>
  37 #include <scsi/scsi_eh.h>
  38
  39 #define DRV_NAME "stex"
  40 #define ST_DRIVER_VERSION "4.6.0000.4"
  41 #define ST_VER_MAJOR            4
  42 #define ST_VER_MINOR            6
  43 #define ST_OEM                  0
  44 #define ST_BUILD_VER            4
  45
  46 enum {
  47         /* MU register offset */
  48         IMR0    = 0x10, /* MU_INBOUND_MESSAGE_REG0 */
  49         IMR1    = 0x14, /* MU_INBOUND_MESSAGE_REG1 */
  50         OMR0    = 0x18, /* MU_OUTBOUND_MESSAGE_REG0 */
  51         OMR1    = 0x1c, /* MU_OUTBOUND_MESSAGE_REG1 */
  52         IDBL    = 0x20, /* MU_INBOUND_DOORBELL */
  53         IIS     = 0x24, /* MU_INBOUND_INTERRUPT_STATUS */
  54         IIM     = 0x28, /* MU_INBOUND_INTERRUPT_MASK */
  55         ODBL    = 0x2c, /* MU_OUTBOUND_DOORBELL */
  56         OIS     = 0x30, /* MU_OUTBOUND_INTERRUPT_STATUS */
  57         OIM     = 0x3c, /* MU_OUTBOUND_INTERRUPT_MASK */
  58
  59         YIOA_STATUS                             = 0x00,
  60         YH2I_INT                                = 0x20,
  61         YINT_EN                                 = 0x34,
  62         YI2H_INT                                = 0x9c,
  63         YI2H_INT_C                              = 0xa0,
  64         YH2I_REQ                                = 0xc0,
  65         YH2I_REQ_HI                             = 0xc4,
  66
  67         /* MU register value */
  68         MU_INBOUND_DOORBELL_HANDSHAKE           = (1 << 0),
  69         MU_INBOUND_DOORBELL_REQHEADCHANGED      = (1 << 1),
  70         MU_INBOUND_DOORBELL_STATUSTAILCHANGED   = (1 << 2),
  71         MU_INBOUND_DOORBELL_HMUSTOPPED          = (1 << 3),
  72         MU_INBOUND_DOORBELL_RESET               = (1 << 4),
  73
  74         MU_OUTBOUND_DOORBELL_HANDSHAKE          = (1 << 0),
  75         MU_OUTBOUND_DOORBELL_REQUESTTAILCHANGED = (1 << 1),
  76         MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED  = (1 << 2),
  77         MU_OUTBOUND_DOORBELL_BUSCHANGE          = (1 << 3),
  78         MU_OUTBOUND_DOORBELL_HASEVENT           = (1 << 4),
  79         MU_OUTBOUND_DOORBELL_REQUEST_RESET      = (1 << 27),
  80
  81         /* MU status code */
  82         MU_STATE_STARTING                       = 1,
  83         MU_STATE_STARTED                        = 2,
  84         MU_STATE_RESETTING                      = 3,
  85         MU_STATE_FAILED                         = 4,
  86
  87         MU_MAX_DELAY                            = 120,
  88         MU_HANDSHAKE_SIGNATURE                  = 0x55aaaa55,
  89         MU_HANDSHAKE_SIGNATURE_HALF             = 0x5a5a0000,
  90         MU_HARD_RESET_WAIT                      = 30000,
  91         HMU_PARTNER_TYPE                        = 2,
  92
  93         /* firmware returned values */
  94         SRB_STATUS_SUCCESS                      = 0x01,
  95         SRB_STATUS_ERROR                        = 0x04,
  96         SRB_STATUS_BUSY                         = 0x05,
  97         SRB_STATUS_INVALID_REQUEST              = 0x06,
  98         SRB_STATUS_SELECTION_TIMEOUT            = 0x0A,
  99         SRB_SEE_SENSE                           = 0x80,
 100
 101         /* task attribute */
 102         TASK_ATTRIBUTE_SIMPLE                   = 0x0,
 103         TASK_ATTRIBUTE_HEADOFQUEUE              = 0x1,
 104         TASK_ATTRIBUTE_ORDERED                  = 0x2,
 105         TASK_ATTRIBUTE_ACA                      = 0x4,
 106
 107         SS_STS_NORMAL                           = 0x80000000,
 108         SS_STS_DONE                             = 0x40000000,
 109         SS_STS_HANDSHAKE                        = 0x20000000,
 110
 111         SS_HEAD_HANDSHAKE                       = 0x80,
 112
 113         SS_H2I_INT_RESET                        = 0x100,
 114
 115         SS_I2H_REQUEST_RESET                    = 0x2000,
 116
 117         SS_MU_OPERATIONAL                       = 0x80000000,
 118
 119         STEX_CDB_LENGTH                         = 16,
 120         STATUS_VAR_LEN                          = 128,
 121
 122         /* sg flags */
 123         SG_CF_EOT                               = 0x80, /* end of table */
 124         SG_CF_64B                               = 0x40, /* 64 bit item */
 125         SG_CF_HOST                              = 0x20, /* sg in host memory */
 126         MSG_DATA_DIR_ND                         = 0,
 127         MSG_DATA_DIR_IN                         = 1,
 128         MSG_DATA_DIR_OUT                        = 2,
 129
 130         st_shasta                               = 0,
 131         st_vsc                                  = 1,
 132         st_yosemite                             = 2,
 133         st_seq                                  = 3,
 134         st_yel                                  = 4,
 135
 136         PASSTHRU_REQ_TYPE                       = 0x00000001,
 137         PASSTHRU_REQ_NO_WAKEUP                  = 0x00000100,
 138         ST_INTERNAL_TIMEOUT                     = 180,
 139
 140         ST_TO_CMD                               = 0,
 141         ST_FROM_CMD                             = 1,
 142
 143         /* vendor specific commands of Promise */
 144         MGT_CMD                                 = 0xd8,
 145         SINBAND_MGT_CMD                         = 0xd9,
 146         ARRAY_CMD                               = 0xe0,
 147         CONTROLLER_CMD                          = 0xe1,
 148         DEBUGGING_CMD                           = 0xe2,
 149         PASSTHRU_CMD                            = 0xe3,
 150
 151         PASSTHRU_GET_ADAPTER                    = 0x05,
 152         PASSTHRU_GET_DRVVER                     = 0x10,
 153
 154         CTLR_CONFIG_CMD                         = 0x03,
 155         CTLR_SHUTDOWN                           = 0x0d,
 156
 157         CTLR_POWER_STATE_CHANGE                 = 0x0e,
 158         CTLR_POWER_SAVING                       = 0x01,
 159
 160         PASSTHRU_SIGNATURE                      = 0x4e415041,
 161         MGT_CMD_SIGNATURE                       = 0xba,
 162
 163         INQUIRY_EVPD                            = 0x01,
 164
 165         ST_ADDITIONAL_MEM                       = 0x200000,
 166         ST_ADDITIONAL_MEM_MIN                   = 0x80000,
 167 };
 168
 169 struct st_sgitem {
 170         u8 ctrl;        /* SG_CF_xxx */
 171         u8 reserved[3];
 172         __le32 count;
 173         __le64 addr;
 174 };
 175
 176 struct st_ss_sgitem {
 177         __le32 addr;
 178         __le32 addr_hi;
 179         __le32 count;
 180 };
 181
 182 struct st_sgtable {
 183         __le16 sg_count;
 184         __le16 max_sg_count;
 185         __le32 sz_in_byte;
 186 };
 187
 188 struct st_msg_header {
 189         __le64 handle;
 190         u8 flag;
 191         u8 channel;
 192         __le16 timeout;
 193         u32 reserved;
 194 };
 195
 196 struct handshake_frame {
 197         __le64 rb_phy;          /* request payload queue physical address */
 198         __le16 req_sz;          /* size of each request payload */
 199         __le16 req_cnt;         /* count of reqs the buffer can hold */
 200         __le16 status_sz;       /* size of each status payload */
 201         __le16 status_cnt;      /* count of status the buffer can hold */
 202         __le64 hosttime;        /* seconds from Jan 1, 1970 (GMT) */
 203         u8 partner_type;        /* who sends this frame */
 204         u8 reserved0[7];
 205         __le32 partner_ver_major;
 206         __le32 partner_ver_minor;
 207         __le32 partner_ver_oem;
 208         __le32 partner_ver_build;
 209         __le32 extra_offset;    /* NEW */
 210         __le32 extra_size;      /* NEW */
 211         __le32 scratch_size;
 212         u32 reserved1;
 213 };
 214
 215 struct req_msg {
 216         __le16 tag;
 217         u8 lun;
 218         u8 target;
 219         u8 task_attr;
 220         u8 task_manage;
 221         u8 data_dir;
 222         u8 payload_sz;          /* payload size in 4-byte, not used */
 223         u8 cdb[STEX_CDB_LENGTH];
 224         u32 variable[0];
 225 };
 226
 227 struct status_msg {
 228         __le16 tag;
 229         u8 lun;
 230         u8 target;
 231         u8 srb_status;
 232         u8 scsi_status;
 233         u8 reserved;
 234         u8 payload_sz;          /* payload size in 4-byte */
 235         u8 variable[STATUS_VAR_LEN];
 236 };
 237
 238 struct ver_info {
 239         u32 major;
 240         u32 minor;
 241         u32 oem;
 242         u32 build;
 243         u32 reserved[2];
 244 };
 245
 246 struct st_frame {
 247         u32 base[6];
 248         u32 rom_addr;
 249
 250         struct ver_info drv_ver;
 251         struct ver_info bios_ver;
 252
 253         u32 bus;
 254         u32 slot;
 255         u32 irq_level;
 256         u32 irq_vec;
 257         u32 id;
 258         u32 subid;
 259
 260         u32 dimm_size;
 261         u8 dimm_type;
 262         u8 reserved[3];
 263
 264         u32 channel;
 265         u32 reserved1;
 266 };
 267
 268 struct st_drvver {
 269         u32 major;
 270         u32 minor;
 271         u32 oem;
 272         u32 build;
 273         u32 signature[2];
 274         u8 console_id;
 275         u8 host_no;
 276         u8 reserved0[2];
 277         u32 reserved[3];
 278 };
 279
 280 struct st_ccb {
 281         struct req_msg *req;
 282         struct scsi_cmnd *cmd;
 283
 284         void *sense_buffer;
 285         unsigned int sense_bufflen;
 286         int sg_count;
 287
 288         u32 req_type;
 289         u8 srb_status;
 290         u8 scsi_status;
 291         u8 reserved[2];
 292 };
 293
 294 struct st_hba {
 295         void __iomem *mmio_base;        /* iomapped PCI memory space */
 296         void *dma_mem;
 297         dma_addr_t dma_handle;
 298         size_t dma_size;
 299
 300         struct Scsi_Host *host;
 301         struct pci_dev *pdev;
 302
 303         struct req_msg * (*alloc_rq) (struct st_hba *);
 304         int (*map_sg)(struct st_hba *, struct req_msg *, struct st_ccb *);
 305         void (*send) (struct st_hba *, struct req_msg *, u16);
 306
 307         u32 req_head;
 308         u32 req_tail;
 309         u32 status_head;
 310         u32 status_tail;
 311
 312         struct status_msg *status_buffer;
 313         void *copy_buffer; /* temp buffer for driver-handled commands */
 314         struct st_ccb *ccb;
 315         struct st_ccb *wait_ccb;
 316         __le32 *scratch;
 317
 318         char work_q_name[20];
 319         struct workqueue_struct *work_q;
 320         struct work_struct reset_work;
 321         wait_queue_head_t reset_waitq;
 322         unsigned int mu_status;
 323         unsigned int cardtype;
 324         int msi_enabled;
 325         int out_req_cnt;
 326         u32 extra_offset;
 327         u16 rq_count;
 328         u16 rq_size;
 329         u16 sts_count;
 330 };
 331
 332 struct st_card_info {
 333         struct req_msg * (*alloc_rq) (struct st_hba *);
 334         int (*map_sg)(struct st_hba *, struct req_msg *, struct st_ccb *);
 335         void (*send) (struct st_hba *, struct req_msg *, u16);
 336         unsigned int max_id;
 337         unsigned int max_lun;
 338         unsigned int max_channel;
 339         u16 rq_count;
 340         u16 rq_size;
 341         u16 sts_count;
 342 };
 343
 344 static int msi;
 345 module_param(msi, int, 0);
 346 MODULE_PARM_DESC(msi, "Enable Message Signaled Interrupts(0=off, 1=on)");
 347
 348 static const char console_inq_page[] =
 349 {
 350         0x03,0x00,0x03,0x03,0xFA,0x00,0x00,0x30,
 351         0x50,0x72,0x6F,0x6D,0x69,0x73,0x65,0x20,        /* "Promise " */
 352         0x52,0x41,0x49,0x44,0x20,0x43,0x6F,0x6E,        /* "RAID Con" */
 353         0x73,0x6F,0x6C,0x65,0x20,0x20,0x20,0x20,        /* "sole    " */
 354         0x31,0x2E,0x30,0x30,0x20,0x20,0x20,0x20,        /* "1.00    " */
 355         0x53,0x58,0x2F,0x52,0x53,0x41,0x46,0x2D,        /* "SX/RSAF-" */
 356         0x54,0x45,0x31,0x2E,0x30,0x30,0x20,0x20,        /* "TE1.00  " */
 357         0x0C,0x20,0x20,0x20,0x20,0x20,0x20,0x20
 358 };
 359
 360 MODULE_AUTHOR("Ed Lin");
 361 MODULE_DESCRIPTION("Promise Technology SuperTrak EX Controllers");
 362 MODULE_LICENSE("GPL");
 363 MODULE_VERSION(ST_DRIVER_VERSION);
 364
 365 static void stex_gettime(__le64 *time)
 366 {
 367         struct timeval tv;
 368
 369         do_gettimeofday(&tv);
 370         *time = cpu_to_le64(tv.tv_sec);
 371 }
 372
 373 static struct status_msg *stex_get_status(struct st_hba *hba)
 374 {
 375         struct status_msg *status = hba->status_buffer + hba->status_tail;
 376
 377         ++hba->status_tail;
 378         hba->status_tail %= hba->sts_count+1;
 379
 380         return status;
 381 }
 382
 383 static void stex_invalid_field(struct scsi_cmnd *cmd,
 384                                void (*done)(struct scsi_cmnd *))
 385 {
 386         cmd->result = (DRIVER_SENSE << 24) | SAM_STAT_CHECK_CONDITION;
 387
 388         /* "Invalid field in cdb" */
 389         scsi_build_sense_buffer(0, cmd->sense_buffer, ILLEGAL_REQUEST, 0x24,
 390                                 0x0);
 391         done(cmd);
 392 }
 393
 394 static struct req_msg *stex_alloc_req(struct st_hba *hba)
 395 {
 396         struct req_msg *req = hba->dma_mem + hba->req_head * hba->rq_size;
 397
 398         ++hba->req_head;
 399         hba->req_head %= hba->rq_count+1;
 400
 401         return req;
 402 }
 403
 404 static struct req_msg *stex_ss_alloc_req(struct st_hba *hba)
 405 {
 406         return (struct req_msg *)(hba->dma_mem +
 407                 hba->req_head * hba->rq_size + sizeof(struct st_msg_header));
 408 }
 409
 410 static int stex_map_sg(struct st_hba *hba,
 411         struct req_msg *req, struct st_ccb *ccb)
 412 {
 413         struct scsi_cmnd *cmd;
 414         struct scatterlist *sg;
 415         struct st_sgtable *dst;
 416         struct st_sgitem *table;
 417         int i, nseg;
 418
 419         cmd = ccb->cmd;
 420         nseg = scsi_dma_map(cmd);
 421         BUG_ON(nseg < 0);
 422         if (nseg) {
 423                 dst = (struct st_sgtable *)req->variable;
 424
 425                 ccb->sg_count = nseg;
 426                 dst->sg_count = cpu_to_le16((u16)nseg);
 427                 dst->max_sg_count = cpu_to_le16(hba->host->sg_tablesize);
 428                 dst->sz_in_byte = cpu_to_le32(scsi_bufflen(cmd));
 429
 430                 table = (struct st_sgitem *)(dst + 1);
 431                 scsi_for_each_sg(cmd, sg, nseg, i) {
 432                         table[i].count = cpu_to_le32((u32)sg_dma_len(sg));
 433                         table[i].addr = cpu_to_le64(sg_dma_address(sg));
 434                         table[i].ctrl = SG_CF_64B | SG_CF_HOST;
 435                 }
 436                 table[--i].ctrl |= SG_CF_EOT;
 437         }
 438
 439         return nseg;
 440 }
 441
 442 static int stex_ss_map_sg(struct st_hba *hba,
 443         struct req_msg *req, struct st_ccb *ccb)
 444 {
 445         struct scsi_cmnd *cmd;
 446         struct scatterlist *sg;
 447         struct st_sgtable *dst;
 448         struct st_ss_sgitem *table;
 449         int i, nseg;
 450
 451         cmd = ccb->cmd;
 452         nseg = scsi_dma_map(cmd);
 453         BUG_ON(nseg < 0);
 454         if (nseg) {
 455                 dst = (struct st_sgtable *)req->variable;
 456
 457                 ccb->sg_count = nseg;
 458                 dst->sg_count = cpu_to_le16((u16)nseg);
 459                 dst->max_sg_count = cpu_to_le16(hba->host->sg_tablesize);
 460                 dst->sz_in_byte = cpu_to_le32(scsi_bufflen(cmd));
 461
 462                 table = (struct st_ss_sgitem *)(dst + 1);
 463                 scsi_for_each_sg(cmd, sg, nseg, i) {
 464                         table[i].count = cpu_to_le32((u32)sg_dma_len(sg));
 465                         table[i].addr =
 466                                 cpu_to_le32(sg_dma_address(sg) & 0xffffffff);
 467                         table[i].addr_hi =
 468                                 cpu_to_le32((sg_dma_address(sg) >> 16) >> 16);
 469                 }
 470         }
 471
 472         return nseg;
 473 }
 474
 475 static void stex_controller_info(struct st_hba *hba, struct st_ccb *ccb)
 476 {
 477         struct st_frame *p;
 478         size_t count = sizeof(struct st_frame);
 479
 480         p = hba->copy_buffer;
 481         scsi_sg_copy_to_buffer(ccb->cmd, p, count);
 482         memset(p->base, 0, sizeof(u32)*6);
 483         *(unsigned long *)(p->base) = pci_resource_start(hba->pdev, 0);
 484         p->rom_addr = 0;
 485
 486         p->drv_ver.major = ST_VER_MAJOR;
 487         p->drv_ver.minor = ST_VER_MINOR;
 488         p->drv_ver.oem = ST_OEM;
 489         p->drv_ver.build = ST_BUILD_VER;
 490
 491         p->bus = hba->pdev->bus->number;
 492         p->slot = hba->pdev->devfn;
 493         p->irq_level = 0;
 494         p->irq_vec = hba->pdev->irq;
 495         p->id = hba->pdev->vendor << 16 | hba->pdev->device;
 496         p->subid =
 497                 hba->pdev->subsystem_vendor << 16 | hba->pdev->subsystem_device;
 498
 499         scsi_sg_copy_from_buffer(ccb->cmd, p, count);
 500 }
 501
 502 static void
 503 stex_send_cmd(struct st_hba *hba, struct req_msg *req, u16 tag)
 504 {
 505         req->tag = cpu_to_le16(tag);
 506
 507         hba->ccb[tag].req = req;
 508         hba->out_req_cnt++;
 509
 510         writel(hba->req_head, hba->mmio_base + IMR0);
 511         writel(MU_INBOUND_DOORBELL_REQHEADCHANGED, hba->mmio_base + IDBL);
 512         readl(hba->mmio_base + IDBL); /* flush */
 513 }
 514
 515 static void
 516 stex_ss_send_cmd(struct st_hba *hba, struct req_msg *req, u16 tag)
 517 {
 518         struct scsi_cmnd *cmd;
 519         struct st_msg_header *msg_h;
 520         dma_addr_t addr;
 521
 522         req->tag = cpu_to_le16(tag);
 523
 524         hba->ccb[tag].req = req;
 525         hba->out_req_cnt++;
 526
 527         cmd = hba->ccb[tag].cmd;
 528         msg_h = (struct st_msg_header *)req - 1;
 529         if (likely(cmd)) {
 530                 msg_h->channel = (u8)cmd->device->channel;
 531                 msg_h->timeout = cpu_to_le16(cmd->request->timeout/HZ);
 532         }
 533         addr = hba->dma_handle + hba->req_head * hba->rq_size;
 534         addr += (hba->ccb[tag].sg_count+4)/11;
 535         msg_h->handle = cpu_to_le64(addr);
 536
 537         ++hba->req_head;
 538         hba->req_head %= hba->rq_count+1;
 539
 540         writel((addr >> 16) >> 16, hba->mmio_base + YH2I_REQ_HI);
 541         readl(hba->mmio_base + YH2I_REQ_HI); /* flush */
 542         writel(addr, hba->mmio_base + YH2I_REQ);
 543         readl(hba->mmio_base + YH2I_REQ); /* flush */
 544 }
 545
 546 static int
 547 stex_slave_alloc(struct scsi_device *sdev)
 548 {
 549         /* Cheat: usually extracted from Inquiry data */
 550         sdev->tagged_supported = 1;
 551
 552         return 0;
 553 }
 554
 555 static int
 556 stex_slave_config(struct scsi_device *sdev)
 557 {
 558         sdev->use_10_for_rw = 1;
 559         sdev->use_10_for_ms = 1;
 560         blk_queue_rq_timeout(sdev->request_queue, 60 * HZ);
 561         sdev->tagged_supported = 1;
 562
 563         return 0;
 564 }
 565
 566 static int
 567 stex_queuecommand_lck(struct scsi_cmnd *cmd, void (*done)(struct scsi_cmnd *))
 568 {
 569         struct st_hba *hba;
 570         struct Scsi_Host *host;
 571         unsigned int id, lun;
 572         struct req_msg *req;
 573         u16 tag;
 574
 575         host = cmd->device->host;
 576         id = cmd->device->id;
 577         lun = cmd->device->lun;
 578         hba = (struct st_hba *) &host->hostdata[0];
 579
 580         if (unlikely(hba->mu_status == MU_STATE_RESETTING))
 581                 return SCSI_MLQUEUE_HOST_BUSY;
 582
 583         switch (cmd->cmnd[0]) {
 584         case MODE_SENSE_10:
 585         {
 586                 static char ms10_caching_page[12] =
 587                         { 0, 0x12, 0, 0, 0, 0, 0, 0, 0x8, 0xa, 0x4, 0 };
 588                 unsigned char page;
 589
 590                 page = cmd->cmnd[2] & 0x3f;
 591                 if (page == 0x8 || page == 0x3f) {
 592                         scsi_sg_copy_from_buffer(cmd, ms10_caching_page,
 593                                                  sizeof(ms10_caching_page));
 594                         cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
 595                         done(cmd);
 596                 } else
 597                         stex_invalid_field(cmd, done);
 598                 return 0;
 599         }
 600         case REPORT_LUNS:
 601                 /*
 602                  * The shasta firmware does not report actual luns in the
 603                  * target, so fail the command to force sequential lun scan.
 604                  * Also, the console device does not support this command.
 605                  */
 606                 if (hba->cardtype == st_shasta || id == host->max_id - 1) {
 607                         stex_invalid_field(cmd, done);
 608                         return 0;
 609                 }
 610                 break;
 611         case TEST_UNIT_READY:
 612                 if (id == host->max_id - 1) {
 613                         cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
 614                         done(cmd);
 615                         return 0;
 616                 }
 617                 break;
 618         case INQUIRY:
 619                 if (lun >= host->max_lun) {
 620                         cmd->result = DID_NO_CONNECT << 16;
 621                         done(cmd);
 622                         return 0;
 623                 }
 624                 if (id != host->max_id - 1)
 625                         break;
 626                 if (!lun && !cmd->device->channel &&
 627                         (cmd->cmnd[1] & INQUIRY_EVPD) == 0) {
 628                         scsi_sg_copy_from_buffer(cmd, (void *)console_inq_page,
 629                                                  sizeof(console_inq_page));
 630                         cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
 631                         done(cmd);
 632                 } else
 633                         stex_invalid_field(cmd, done);
 634                 return 0;
 635         case PASSTHRU_CMD:
 636                 if (cmd->cmnd[1] == PASSTHRU_GET_DRVVER) {
 637                         struct st_drvver ver;
 638                         size_t cp_len = sizeof(ver);
 639
 640                         ver.major = ST_VER_MAJOR;
 641                         ver.minor = ST_VER_MINOR;
 642                         ver.oem = ST_OEM;
 643                         ver.build = ST_BUILD_VER;
 644                         ver.signature[0] = PASSTHRU_SIGNATURE;
 645                         ver.console_id = host->max_id - 1;
 646                         ver.host_no = hba->host->host_no;
 647                         cp_len = scsi_sg_copy_from_buffer(cmd, &ver, cp_len);
 648                         cmd->result = sizeof(ver) == cp_len ?
 649                                 DID_OK << 16 | COMMAND_COMPLETE << 8 :
 650                                 DID_ERROR << 16 | COMMAND_COMPLETE << 8;
 651                         done(cmd);
 652                         return 0;
 653                 }
 654         default:
 655                 break;
 656         }
 657
 658         cmd->scsi_done = done;
 659
 660         tag = cmd->request->tag;
 661
 662         if (unlikely(tag >= host->can_queue))
 663                 return SCSI_MLQUEUE_HOST_BUSY;
 664
 665         req = hba->alloc_rq(hba);
 666
 667         req->lun = lun;
 668         req->target = id;
 669
 670         /* cdb */
 671         memcpy(req->cdb, cmd->cmnd, STEX_CDB_LENGTH);
 672
 673         if (cmd->sc_data_direction == DMA_FROM_DEVICE)
 674                 req->data_dir = MSG_DATA_DIR_IN;
 675         else if (cmd->sc_data_direction == DMA_TO_DEVICE)
 676                 req->data_dir = MSG_DATA_DIR_OUT;
 677         else
 678                 req->data_dir = MSG_DATA_DIR_ND;
 679
 680         hba->ccb[tag].cmd = cmd;
 681         hba->ccb[tag].sense_bufflen = SCSI_SENSE_BUFFERSIZE;
 682         hba->ccb[tag].sense_buffer = cmd->sense_buffer;
 683
 684         if (!hba->map_sg(hba, req, &hba->ccb[tag])) {
 685                 hba->ccb[tag].sg_count = 0;
 686                 memset(&req->variable[0], 0, 8);
 687         }
 688
 689         hba->send(hba, req, tag);
 690         return 0;
 691 }
 692
 693 static DEF_SCSI_QCMD(stex_queuecommand)
 694
 695 static void stex_scsi_done(struct st_ccb *ccb)
 696 {
 697         struct scsi_cmnd *cmd = ccb->cmd;
 698         int result;
 699
 700         if (ccb->srb_status == SRB_STATUS_SUCCESS || ccb->srb_status == 0) {
 701                 result = ccb->scsi_status;
 702                 switch (ccb->scsi_status) {
 703                 case SAM_STAT_GOOD:
 704                         result |= DID_OK << 16 | COMMAND_COMPLETE << 8;
 705                         break;
 706                 case SAM_STAT_CHECK_CONDITION:
 707                         result |= DRIVER_SENSE << 24;
 708                         break;
 709                 case SAM_STAT_BUSY:
 710                         result |= DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8;
 711                         break;
 712                 default:
 713                         result |= DID_ERROR << 16 | COMMAND_COMPLETE << 8;
 714                         break;
 715                 }
 716         }
 717         else if (ccb->srb_status & SRB_SEE_SENSE)
 718                 result = DRIVER_SENSE << 24 | SAM_STAT_CHECK_CONDITION;
 719         else switch (ccb->srb_status) {
 720                 case SRB_STATUS_SELECTION_TIMEOUT:
 721                         result = DID_NO_CONNECT << 16 | COMMAND_COMPLETE << 8;
 722                         break;
 723                 case SRB_STATUS_BUSY:
 724                         result = DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8;
 725                         break;
 726                 case SRB_STATUS_INVALID_REQUEST:
 727                 case SRB_STATUS_ERROR:
 728                 default:
 729                         result = DID_ERROR << 16 | COMMAND_COMPLETE << 8;
 730                         break;
 731         }
 732
 733         cmd->result = result;
 734         cmd->scsi_done(cmd);
 735 }
 736
 737 static void stex_copy_data(struct st_ccb *ccb,
 738         struct status_msg *resp, unsigned int variable)
 739 {
 740         if (resp->scsi_status != SAM_STAT_GOOD) {
 741                 if (ccb->sense_buffer != NULL)
 742                         memcpy(ccb->sense_buffer, resp->variable,
 743                                 min(variable, ccb->sense_bufflen));
 744                 return;
 745         }
 746
 747         if (ccb->cmd == NULL)
 748                 return;
 749         scsi_sg_copy_from_buffer(ccb->cmd, resp->variable, variable);
 750 }
 751
 752 static void stex_check_cmd(struct st_hba *hba,
 753         struct st_ccb *ccb, struct status_msg *resp)
 754 {
 755         if (ccb->cmd->cmnd[0] == MGT_CMD &&
 756                 resp->scsi_status != SAM_STAT_CHECK_CONDITION)
 757                 scsi_set_resid(ccb->cmd, scsi_bufflen(ccb->cmd) -
 758                         le32_to_cpu(*(__le32 *)&resp->variable[0]));
 759 }
 760
 761 static void stex_mu_intr(struct st_hba *hba, u32 doorbell)
 762 {
 763         void __iomem *base = hba->mmio_base;
 764         struct status_msg *resp;
 765         struct st_ccb *ccb;
 766         unsigned int size;
 767         u16 tag;
 768
 769         if (unlikely(!(doorbell & MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED)))
 770                 return;
 771
 772         /* status payloads */
 773         hba->status_head = readl(base + OMR1);
 774         if (unlikely(hba->status_head > hba->sts_count)) {
 775                 printk(KERN_WARNING DRV_NAME "(%s): invalid status head\n",
 776                         pci_name(hba->pdev));
 777                 return;
 778         }
 779
 780         /*
 781          * it's not a valid status payload if:
 782          * 1. there are no pending requests(e.g. during init stage)
 783          * 2. there are some pending requests, but the controller is in
 784          *     reset status, and its type is not st_yosemite
 785          * firmware of st_yosemite in reset status will return pending requests
 786          * to driver, so we allow it to pass
 787          */
 788         if (unlikely(hba->out_req_cnt <= 0 ||
 789                         (hba->mu_status == MU_STATE_RESETTING &&
 790                          hba->cardtype != st_yosemite))) {
 791                 hba->status_tail = hba->status_head;
 792                 goto update_status;
 793         }
 794
 795         while (hba->status_tail != hba->status_head) {
 796                 resp = stex_get_status(hba);
 797                 tag = le16_to_cpu(resp->tag);
 798                 if (unlikely(tag >= hba->host->can_queue)) {
 799                         printk(KERN_WARNING DRV_NAME
 800                                 "(%s): invalid tag\n", pci_name(hba->pdev));
 801                         continue;
 802                 }
 803
 804                 hba->out_req_cnt--;
 805                 ccb = &hba->ccb[tag];
 806                 if (unlikely(hba->wait_ccb == ccb))
 807                         hba->wait_ccb = NULL;
 808                 if (unlikely(ccb->req == NULL)) {
 809                         printk(KERN_WARNING DRV_NAME
 810                                 "(%s): lagging req\n", pci_name(hba->pdev));
 811                         continue;
 812                 }
 813
 814                 size = resp->payload_sz * sizeof(u32); /* payload size */
 815                 if (unlikely(size < sizeof(*resp) - STATUS_VAR_LEN ||
 816                         size > sizeof(*resp))) {
 817                         printk(KERN_WARNING DRV_NAME "(%s): bad status size\n",
 818                                 pci_name(hba->pdev));
 819                 } else {
 820                         size -= sizeof(*resp) - STATUS_VAR_LEN; /* copy size */
 821                         if (size)
 822                                 stex_copy_data(ccb, resp, size);
 823                 }
 824
 825                 ccb->req = NULL;
 826                 ccb->srb_status = resp->srb_status;
 827                 ccb->scsi_status = resp->scsi_status;
 828
 829                 if (likely(ccb->cmd != NULL)) {
 830                         if (hba->cardtype == st_yosemite)
 831                                 stex_check_cmd(hba, ccb, resp);
 832
 833                         if (unlikely(ccb->cmd->cmnd[0] == PASSTHRU_CMD &&
 834                                 ccb->cmd->cmnd[1] == PASSTHRU_GET_ADAPTER))
 835                                 stex_controller_info(hba, ccb);
 836
 837                         scsi_dma_unmap(ccb->cmd);
 838                         stex_scsi_done(ccb);
 839                 } else
 840                         ccb->req_type = 0;
 841         }
 842
 843 update_status:
 844         writel(hba->status_head, base + IMR1);
 845         readl(base + IMR1); /* flush */
 846 }
 847
 848 static irqreturn_t stex_intr(int irq, void *__hba)
 849 {
 850         struct st_hba *hba = __hba;
 851         void __iomem *base = hba->mmio_base;
 852         u32 data;
 853         unsigned long flags;
 854
 855         spin_lock_irqsave(hba->host->host_lock, flags);
 856
 857         data = readl(base + ODBL);
 858
 859         if (data && data != 0xffffffff) {
 860                 /* clear the interrupt */
 861                 writel(data, base + ODBL);
 862                 readl(base + ODBL); /* flush */
 863                 stex_mu_intr(hba, data);
 864                 spin_unlock_irqrestore(hba->host->host_lock, flags);
 865                 if (unlikely(data & MU_OUTBOUND_DOORBELL_REQUEST_RESET &&
 866                         hba->cardtype == st_shasta))
 867                         queue_work(hba->work_q, &hba->reset_work);
 868                 return IRQ_HANDLED;
 869         }
 870
 871         spin_unlock_irqrestore(hba->host->host_lock, flags);
 872
 873         return IRQ_NONE;
 874 }
 875
 876 static void stex_ss_mu_intr(struct st_hba *hba)
 877 {
 878         struct status_msg *resp;
 879         struct st_ccb *ccb;
 880         __le32 *scratch;
 881         unsigned int size;
 882         int count = 0;
 883         u32 value;
 884         u16 tag;
 885
 886         if (unlikely(hba->out_req_cnt <= 0 ||
 887                         hba->mu_status == MU_STATE_RESETTING))
 888                 return;
 889
 890         while (count < hba->sts_count) {
 891                 scratch = hba->scratch + hba->status_tail;
 892                 value = le32_to_cpu(*scratch);
 893                 if (unlikely(!(value & SS_STS_NORMAL)))
 894                         return;
 895
 896                 resp = hba->status_buffer + hba->status_tail;
 897                 *scratch = 0;
 898                 ++count;
 899                 ++hba->status_tail;
 900                 hba->status_tail %= hba->sts_count+1;
 901
 902                 tag = (u16)value;
 903                 if (unlikely(tag >= hba->host->can_queue)) {
 904                         printk(KERN_WARNING DRV_NAME
 905                                 "(%s): invalid tag\n", pci_name(hba->pdev));
 906                         continue;
 907                 }
 908
 909                 hba->out_req_cnt--;
 910                 ccb = &hba->ccb[tag];
 911                 if (unlikely(hba->wait_ccb == ccb))
 912                         hba->wait_ccb = NULL;
 913                 if (unlikely(ccb->req == NULL)) {
 914                         printk(KERN_WARNING DRV_NAME
 915                                 "(%s): lagging req\n", pci_name(hba->pdev));
 916                         continue;
 917                 }
 918
 919                 ccb->req = NULL;
 920                 if (likely(value & SS_STS_DONE)) { /* normal case */
 921                         ccb->srb_status = SRB_STATUS_SUCCESS;
 922                         ccb->scsi_status = SAM_STAT_GOOD;
 923                 } else {
 924                         ccb->srb_status = resp->srb_status;
 925                         ccb->scsi_status = resp->scsi_status;
 926                         size = resp->payload_sz * sizeof(u32);
 927                         if (unlikely(size < sizeof(*resp) - STATUS_VAR_LEN ||
 928                                 size > sizeof(*resp))) {
 929                                 printk(KERN_WARNING DRV_NAME
 930                                         "(%s): bad status size\n",
 931                                         pci_name(hba->pdev));
 932                         } else {
 933                                 size -= sizeof(*resp) - STATUS_VAR_LEN;
 934                                 if (size)
 935                                         stex_copy_data(ccb, resp, size);
 936                         }
 937                         if (likely(ccb->cmd != NULL))
 938                                 stex_check_cmd(hba, ccb, resp);
 939                 }
 940
 941                 if (likely(ccb->cmd != NULL)) {
 942                         scsi_dma_unmap(ccb->cmd);
 943                         stex_scsi_done(ccb);
 944                 } else
 945                         ccb->req_type = 0;
 946         }
 947 }
 948
 949 static irqreturn_t stex_ss_intr(int irq, void *__hba)
 950 {
 951         struct st_hba *hba = __hba;
 952         void __iomem *base = hba->mmio_base;
 953         u32 data;
 954         unsigned long flags;
 955
 956         spin_lock_irqsave(hba->host->host_lock, flags);
 957
 958         data = readl(base + YI2H_INT);
 959         if (data && data != 0xffffffff) {
 960                 /* clear the interrupt */
 961                 writel(data, base + YI2H_INT_C);
 962                 stex_ss_mu_intr(hba);
 963                 spin_unlock_irqrestore(hba->host->host_lock, flags);
 964                 if (unlikely(data & SS_I2H_REQUEST_RESET))
 965                         queue_work(hba->work_q, &hba->reset_work);
 966                 return IRQ_HANDLED;
 967         }
 968
 969         spin_unlock_irqrestore(hba->host->host_lock, flags);
 970
 971         return IRQ_NONE;
 972 }
 973
 974 static int stex_common_handshake(struct st_hba *hba)
 975 {
 976         void __iomem *base = hba->mmio_base;
 977         struct handshake_frame *h;
 978         dma_addr_t status_phys;
 979         u32 data;
 980         unsigned long before;
 981
 982         if (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
 983                 writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
 984                 readl(base + IDBL);
 985                 before = jiffies;
 986                 while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
 987                         if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
 988                                 printk(KERN_ERR DRV_NAME
 989                                         "(%s): no handshake signature\n",
 990                                         pci_name(hba->pdev));
 991                                 return -1;
 992                         }
 993                         rmb();
 994                         msleep(1);
 995                 }
 996         }
 997
 998         udelay(10);
 999
1000         data = readl(base + OMR1);
1001         if ((data & 0xffff0000) == MU_HANDSHAKE_SIGNATURE_HALF) {
1002                 data &= 0x0000ffff;
1003                 if (hba->host->can_queue > data) {
1004                         hba->host->can_queue = data;
1005                         hba->host->cmd_per_lun = data;
1006                 }
1007         }
1008
1009         h = (struct handshake_frame *)hba->status_buffer;
1010         h->rb_phy = cpu_to_le64(hba->dma_handle);
1011         h->req_sz = cpu_to_le16(hba->rq_size);
1012         h->req_cnt = cpu_to_le16(hba->rq_count+1);
1013         h->status_sz = cpu_to_le16(sizeof(struct status_msg));
1014         h->status_cnt = cpu_to_le16(hba->sts_count+1);
1015         stex_gettime(&h->hosttime);
1016         h->partner_type = HMU_PARTNER_TYPE;
1017         if (hba->extra_offset) {
1018                 h->extra_offset = cpu_to_le32(hba->extra_offset);
1019                 h->extra_size = cpu_to_le32(hba->dma_size - hba->extra_offset);
1020         } else
1021                 h->extra_offset = h->extra_size = 0;
1022
1023         status_phys = hba->dma_handle + (hba->rq_count+1) * hba->rq_size;
1024         writel(status_phys, base + IMR0);
1025         readl(base + IMR0);
1026         writel((status_phys >> 16) >> 16, base + IMR1);
1027         readl(base + IMR1);
1028
1029         writel((status_phys >> 16) >> 16, base + OMR0); /* old fw compatible */
1030         readl(base + OMR0);
1031         writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
1032         readl(base + IDBL); /* flush */
1033
1034         udelay(10);
1035         before = jiffies;
1036         while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
1037                 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
1038                         printk(KERN_ERR DRV_NAME
1039                                 "(%s): no signature after handshake frame\n",
1040                                 pci_name(hba->pdev));
1041                         return -1;
1042                 }
1043                 rmb();
1044                 msleep(1);
1045         }
1046
1047         writel(0, base + IMR0);
1048         readl(base + IMR0);
1049         writel(0, base + OMR0);
1050         readl(base + OMR0);
1051         writel(0, base + IMR1);
1052         readl(base + IMR1);
1053         writel(0, base + OMR1);
1054         readl(base + OMR1); /* flush */
1055         return 0;
1056 }
1057
1058 static int stex_ss_handshake(struct st_hba *hba)
1059 {
1060         void __iomem *base = hba->mmio_base;
1061         struct st_msg_header *msg_h;
1062         struct handshake_frame *h;
1063         __le32 *scratch;
1064         u32 data, scratch_size;
1065         unsigned long before;
1066         int ret = 0;
1067
1068         before = jiffies;
1069         while ((readl(base + YIOA_STATUS) & SS_MU_OPERATIONAL) == 0) {
1070                 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
1071                         printk(KERN_ERR DRV_NAME
1072                                 "(%s): firmware not operational\n",
1073                                 pci_name(hba->pdev));
1074                         return -1;
1075                 }
1076                 msleep(1);
1077         }
1078
1079         msg_h = (struct st_msg_header *)hba->dma_mem;
1080         msg_h->handle = cpu_to_le64(hba->dma_handle);
1081         msg_h->flag = SS_HEAD_HANDSHAKE;
1082
1083         h = (struct handshake_frame *)(msg_h + 1);
1084         h->rb_phy = cpu_to_le64(hba->dma_handle);
1085         h->req_sz = cpu_to_le16(hba->rq_size);
1086         h->req_cnt = cpu_to_le16(hba->rq_count+1);
1087         h->status_sz = cpu_to_le16(sizeof(struct status_msg));
1088         h->status_cnt = cpu_to_le16(hba->sts_count+1);
1089         stex_gettime(&h->hosttime);
1090         h->partner_type = HMU_PARTNER_TYPE;
1091         h->extra_offset = h->extra_size = 0;
1092         scratch_size = (hba->sts_count+1)*sizeof(u32);
1093         h->scratch_size = cpu_to_le32(scratch_size);
1094
1095         data = readl(base + YINT_EN);
1096         data &= ~4;
1097         writel(data, base + YINT_EN);
1098         writel((hba->dma_handle >> 16) >> 16, base + YH2I_REQ_HI);
1099         readl(base + YH2I_REQ_HI);
1100         writel(hba->dma_handle, base + YH2I_REQ);
1101         readl(base + YH2I_REQ); /* flush */
1102
1103         scratch = hba->scratch;
1104         before = jiffies;
1105         while (!(le32_to_cpu(*scratch) & SS_STS_HANDSHAKE)) {
1106                 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
1107                         printk(KERN_ERR DRV_NAME
1108                                 "(%s): no signature after handshake frame\n",
1109                                 pci_name(hba->pdev));
1110                         ret = -1;
1111                         break;
1112                 }
1113                 rmb();
1114                 msleep(1);
1115         }
1116
1117         memset(scratch, 0, scratch_size);
1118         msg_h->flag = 0;
1119         return ret;
1120 }
1121
1122 static int stex_handshake(struct st_hba *hba)
1123 {
1124         int err;
1125         unsigned long flags;
1126         unsigned int mu_status;
1127
1128         err = (hba->cardtype == st_yel) ?
1129                 stex_ss_handshake(hba) : stex_common_handshake(hba);
1130         spin_lock_irqsave(hba->host->host_lock, flags);
1131         mu_status = hba->mu_status;
1132         if (err == 0) {
1133                 hba->req_head = 0;
1134                 hba->req_tail = 0;
1135                 hba->status_head = 0;
1136                 hba->status_tail = 0;
1137                 hba->out_req_cnt = 0;
1138                 hba->mu_status = MU_STATE_STARTED;
1139         } else
1140                 hba->mu_status = MU_STATE_FAILED;
1141         if (mu_status == MU_STATE_RESETTING)
1142                 wake_up_all(&hba->reset_waitq);
1143         spin_unlock_irqrestore(hba->host->host_lock, flags);
1144         return err;
1145 }
1146
1147 static int stex_abort(struct scsi_cmnd *cmd)
1148 {
1149         struct Scsi_Host *host = cmd->device->host;
1150         struct st_hba *hba = (struct st_hba *)host->hostdata;
1151         u16 tag = cmd->request->tag;
1152         void __iomem *base;
1153         u32 data;
1154         int result = SUCCESS;
1155         unsigned long flags;
1156
1157         scmd_printk(KERN_INFO, cmd, "aborting command\n");
1158
1159         base = hba->mmio_base;
1160         spin_lock_irqsave(host->host_lock, flags);
1161         if (tag < host->can_queue &&
1162                 hba->ccb[tag].req && hba->ccb[tag].cmd == cmd)
1163                 hba->wait_ccb = &hba->ccb[tag];
1164         else
1165                 goto out;
1166
1167         if (hba->cardtype == st_yel) {
1168                 data = readl(base + YI2H_INT);
1169                 if (data == 0 || data == 0xffffffff)
1170                         goto fail_out;
1171
1172                 writel(data, base + YI2H_INT_C);
1173                 stex_ss_mu_intr(hba);
1174         } else {
1175                 data = readl(base + ODBL);
1176                 if (data == 0 || data == 0xffffffff)
1177                         goto fail_out;
1178
1179                 writel(data, base + ODBL);
1180                 readl(base + ODBL); /* flush */
1181
1182                 stex_mu_intr(hba, data);
1183         }
1184         if (hba->wait_ccb == NULL) {
1185                 printk(KERN_WARNING DRV_NAME
1186                         "(%s): lost interrupt\n", pci_name(hba->pdev));
1187                 goto out;
1188         }
1189
1190 fail_out:
1191         scsi_dma_unmap(cmd);
1192         hba->wait_ccb->req = NULL; /* nullify the req's future return */
1193         hba->wait_ccb = NULL;
1194         result = FAILED;
1195 out:
1196         spin_unlock_irqrestore(host->host_lock, flags);
1197         return result;
1198 }
1199
1200 static void stex_hard_reset(struct st_hba *hba)
1201 {
1202         struct pci_bus *bus;
1203         int i;
1204         u16 pci_cmd;
1205         u8 pci_bctl;
1206
1207         for (i = 0; i < 16; i++)
1208                 pci_read_config_dword(hba->pdev, i * 4,
1209                         &hba->pdev->saved_config_space[i]);
1210
1211         /* Reset secondary bus. Our controller(MU/ATU) is the only device on
1212            secondary bus. Consult Intel 80331/3 developer's manual for detail */
1213         bus = hba->pdev->bus;
1214         pci_read_config_byte(bus->self, PCI_BRIDGE_CONTROL, &pci_bctl);
1215         pci_bctl |= PCI_BRIDGE_CTL_BUS_RESET;
1216         pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
1217
1218         /*
1219          * 1 ms may be enough for 8-port controllers. But 16-port controllers
1220          * require more time to finish bus reset. Use 100 ms here for safety
1221          */
1222         msleep(100);
1223         pci_bctl &= ~PCI_BRIDGE_CTL_BUS_RESET;
1224         pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
1225
1226         for (i = 0; i < MU_HARD_RESET_WAIT; i++) {
1227                 pci_read_config_word(hba->pdev, PCI_COMMAND, &pci_cmd);
1228                 if (pci_cmd != 0xffff && (pci_cmd & PCI_COMMAND_MASTER))
1229                         break;
1230                 msleep(1);
1231         }
1232
1233         ssleep(5);
1234         for (i = 0; i < 16; i++)
1235                 pci_write_config_dword(hba->pdev, i * 4,
1236                         hba->pdev->saved_config_space[i]);
1237 }
1238
1239 static int stex_yos_reset(struct st_hba *hba)
1240 {
1241         void __iomem *base;
1242         unsigned long flags, before;
1243         int ret = 0;
1244
1245         base = hba->mmio_base;
1246         writel(MU_INBOUND_DOORBELL_RESET, base + IDBL);
1247         readl(base + IDBL); /* flush */
1248         before = jiffies;
1249         while (hba->out_req_cnt > 0) {
1250                 if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ)) {
1251                         printk(KERN_WARNING DRV_NAME
1252                                 "(%s): reset timeout\n", pci_name(hba->pdev));
1253                         ret = -1;
1254                         break;
1255                 }
1256                 msleep(1);
1257         }
1258
1259         spin_lock_irqsave(hba->host->host_lock, flags);
1260         if (ret == -1)
1261                 hba->mu_status = MU_STATE_FAILED;
1262         else
1263                 hba->mu_status = MU_STATE_STARTED;
1264         wake_up_all(&hba->reset_waitq);
1265         spin_unlock_irqrestore(hba->host->host_lock, flags);
1266
1267         return ret;
1268 }
1269
1270 static void stex_ss_reset(struct st_hba *hba)
1271 {
1272         writel(SS_H2I_INT_RESET, hba->mmio_base + YH2I_INT);
1273         readl(hba->mmio_base + YH2I_INT);
1274         ssleep(5);
1275 }
1276
1277 static int stex_do_reset(struct st_hba *hba)
1278 {
1279         struct st_ccb *ccb;
1280         unsigned long flags;
1281         unsigned int mu_status = MU_STATE_RESETTING;
1282         u16 tag;
1283
1284         spin_lock_irqsave(hba->host->host_lock, flags);
1285         if (hba->mu_status == MU_STATE_STARTING) {
1286                 spin_unlock_irqrestore(hba->host->host_lock, flags);
1287                 printk(KERN_INFO DRV_NAME "(%s): request reset during init\n",
1288                         pci_name(hba->pdev));
1289                 return 0;
1290         }
1291         while (hba->mu_status == MU_STATE_RESETTING) {
1292                 spin_unlock_irqrestore(hba->host->host_lock, flags);
1293                 wait_event_timeout(hba->reset_waitq,
1294                                    hba->mu_status != MU_STATE_RESETTING,
1295                                    MU_MAX_DELAY * HZ);
1296                 spin_lock_irqsave(hba->host->host_lock, flags);
1297                 mu_status = hba->mu_status;
1298         }
1299
1300         if (mu_status != MU_STATE_RESETTING) {
1301                 spin_unlock_irqrestore(hba->host->host_lock, flags);
1302                 return (mu_status == MU_STATE_STARTED) ? 0 : -1;
1303         }
1304
1305         hba->mu_status = MU_STATE_RESETTING;
1306         spin_unlock_irqrestore(hba->host->host_lock, flags);
1307
1308         if (hba->cardtype == st_yosemite)
1309                 return stex_yos_reset(hba);
1310
1311         if (hba->cardtype == st_shasta)
1312                 stex_hard_reset(hba);
1313         else if (hba->cardtype == st_yel)
1314                 stex_ss_reset(hba);
1315
1316         spin_lock_irqsave(hba->host->host_lock, flags);
1317         for (tag = 0; tag < hba->host->can_queue; tag++) {
1318                 ccb = &hba->ccb[tag];
1319                 if (ccb->req == NULL)
1320                         continue;
1321                 ccb->req = NULL;
1322                 if (ccb->cmd) {
1323                         scsi_dma_unmap(ccb->cmd);
1324                         ccb->cmd->result = DID_RESET << 16;
1325                         ccb->cmd->scsi_done(ccb->cmd);
1326                         ccb->cmd = NULL;
1327                 }
1328         }
1329         spin_unlock_irqrestore(hba->host->host_lock, flags);
1330
1331         if (stex_handshake(hba) == 0)
1332                 return 0;
1333
1334         printk(KERN_WARNING DRV_NAME "(%s): resetting: handshake failed\n",
1335                 pci_name(hba->pdev));
1336         return -1;
1337 }
1338
1339 static int stex_reset(struct scsi_cmnd *cmd)
1340 {
1341         struct st_hba *hba;
1342
1343         hba = (struct st_hba *) &cmd->device->host->hostdata[0];
1344
1345         shost_printk(KERN_INFO, cmd->device->host,
1346                      "resetting host\n");
1347
1348         return stex_do_reset(hba) ? FAILED : SUCCESS;
1349 }
1350
1351 static void stex_reset_work(struct work_struct *work)
1352 {
1353         struct st_hba *hba = container_of(work, struct st_hba, reset_work);
1354
1355         stex_do_reset(hba);
1356 }
1357
1358 static int stex_biosparam(struct scsi_device *sdev,
1359         struct block_device *bdev, sector_t capacity, int geom[])
1360 {
1361         int heads = 255, sectors = 63;
1362
1363         if (capacity < 0x200000) {
1364                 heads = 64;
1365                 sectors = 32;
1366         }
1367
1368         sector_div(capacity, heads * sectors);
1369
1370         geom[0] = heads;
1371         geom[1] = sectors;
1372         geom[2] = capacity;
1373
1374         return 0;
1375 }
1376
1377 static struct scsi_host_template driver_template = {
1378         .module                         = THIS_MODULE,
1379         .name                           = DRV_NAME,
1380         .proc_name                      = DRV_NAME,
1381         .bios_param                     = stex_biosparam,
1382         .queuecommand                   = stex_queuecommand,
1383         .slave_alloc                    = stex_slave_alloc,
1384         .slave_configure                = stex_slave_config,
1385         .eh_abort_handler               = stex_abort,
1386         .eh_host_reset_handler          = stex_reset,
1387         .this_id                        = -1,
1388         .use_blk_tags                   = 1,
1389 };
1390
1391 static struct pci_device_id stex_pci_tbl[] = {
1392         /* st_shasta */
1393         { 0x105a, 0x8350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1394                 st_shasta }, /* SuperTrak EX8350/8300/16350/16300 */
1395         { 0x105a, 0xc350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1396                 st_shasta }, /* SuperTrak EX12350 */
1397         { 0x105a, 0x4302, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1398                 st_shasta }, /* SuperTrak EX4350 */
1399         { 0x105a, 0xe350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1400                 st_shasta }, /* SuperTrak EX24350 */
1401
1402         /* st_vsc */
1403         { 0x105a, 0x7250, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_vsc },
1404
1405         /* st_yosemite */
1406         { 0x105a, 0x8650, 0x105a, PCI_ANY_ID, 0, 0, st_yosemite },
1407
1408         /* st_seq */
1409         { 0x105a, 0x3360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_seq },
1410
1411         /* st_yel */
1412         { 0x105a, 0x8650, 0x1033, PCI_ANY_ID, 0, 0, st_yel },
1413         { 0x105a, 0x8760, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_yel },
1414         { }     /* terminate list */
1415 };
1416
1417 static struct st_card_info stex_card_info[] = {
1418         /* st_shasta */
1419         {
1420                 .max_id         = 17,
1421                 .max_lun        = 8,
1422                 .max_channel    = 0,
1423                 .rq_count       = 32,
1424                 .rq_size        = 1048,
1425                 .sts_count      = 32,
1426                 .alloc_rq       = stex_alloc_req,
1427                 .map_sg         = stex_map_sg,
1428                 .send           = stex_send_cmd,
1429         },
1430
1431         /* st_vsc */
1432         {
1433                 .max_id         = 129,
1434                 .max_lun        = 1,
1435                 .max_channel    = 0,
1436                 .rq_count       = 32,
1437                 .rq_size        = 1048,
1438                 .sts_count      = 32,
1439                 .alloc_rq       = stex_alloc_req,
1440                 .map_sg         = stex_map_sg,
1441                 .send           = stex_send_cmd,
1442         },
1443
1444         /* st_yosemite */
1445         {
1446                 .max_id         = 2,
1447                 .max_lun        = 256,
1448                 .max_channel    = 0,
1449                 .rq_count       = 256,
1450                 .rq_size        = 1048,
1451                 .sts_count      = 256,
1452                 .alloc_rq       = stex_alloc_req,
1453                 .map_sg         = stex_map_sg,
1454                 .send           = stex_send_cmd,
1455         },
1456
1457         /* st_seq */
1458         {
1459                 .max_id         = 129,
1460                 .max_lun        = 1,
1461                 .max_channel    = 0,
1462                 .rq_count       = 32,
1463                 .rq_size        = 1048,
1464                 .sts_count      = 32,
1465                 .alloc_rq       = stex_alloc_req,
1466                 .map_sg         = stex_map_sg,
1467                 .send           = stex_send_cmd,
1468         },
1469
1470         /* st_yel */
1471         {
1472                 .max_id         = 129,
1473                 .max_lun        = 256,
1474                 .max_channel    = 3,
1475                 .rq_count       = 801,
1476                 .rq_size        = 512,
1477                 .sts_count      = 801,
1478                 .alloc_rq       = stex_ss_alloc_req,
1479                 .map_sg         = stex_ss_map_sg,
1480                 .send           = stex_ss_send_cmd,
1481         },
1482 };
1483
1484 static int stex_set_dma_mask(struct pci_dev * pdev)
1485 {
1486         int ret;
1487
1488         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))
1489                 && !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
1490                 return 0;
1491         ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1492         if (!ret)
1493                 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1494         return ret;
1495 }
1496
1497 static int stex_request_irq(struct st_hba *hba)
1498 {
1499         struct pci_dev *pdev = hba->pdev;
1500         int status;
1501
1502         if (msi) {
1503                 status = pci_enable_msi(pdev);
1504                 if (status != 0)
1505                         printk(KERN_ERR DRV_NAME
1506                                 "(%s): error %d setting up MSI\n",
1507                                 pci_name(pdev), status);
1508                 else
1509                         hba->msi_enabled = 1;
1510         } else
1511                 hba->msi_enabled = 0;
1512
1513         status = request_irq(pdev->irq, hba->cardtype == st_yel ?
1514                 stex_ss_intr : stex_intr, IRQF_SHARED, DRV_NAME, hba);
1515
1516         if (status != 0) {
1517                 if (hba->msi_enabled)
1518                         pci_disable_msi(pdev);
1519         }
1520         return status;
1521 }
1522
1523 static void stex_free_irq(struct st_hba *hba)
1524 {
1525         struct pci_dev *pdev = hba->pdev;
1526
1527         free_irq(pdev->irq, hba);
1528         if (hba->msi_enabled)
1529                 pci_disable_msi(pdev);
1530 }
1531
1532 static int stex_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1533 {
1534         struct st_hba *hba;
1535         struct Scsi_Host *host;
1536         const struct st_card_info *ci = NULL;
1537         u32 sts_offset, cp_offset, scratch_offset;
1538         int err;
1539
1540         err = pci_enable_device(pdev);
1541         if (err)
1542                 return err;
1543
1544         pci_set_master(pdev);
1545
1546         host = scsi_host_alloc(&driver_template, sizeof(struct st_hba));
1547
1548         if (!host) {
1549                 printk(KERN_ERR DRV_NAME "(%s): scsi_host_alloc failed\n",
1550                         pci_name(pdev));
1551                 err = -ENOMEM;
1552                 goto out_disable;
1553         }
1554
1555         hba = (struct st_hba *)host->hostdata;
1556         memset(hba, 0, sizeof(struct st_hba));
1557
1558         err = pci_request_regions(pdev, DRV_NAME);
1559         if (err < 0) {
1560                 printk(KERN_ERR DRV_NAME "(%s): request regions failed\n",
1561                         pci_name(pdev));
1562                 goto out_scsi_host_put;
1563         }
1564
1565         hba->mmio_base = pci_ioremap_bar(pdev, 0);
1566         if ( !hba->mmio_base) {
1567                 printk(KERN_ERR DRV_NAME "(%s): memory map failed\n",
1568                         pci_name(pdev));
1569                 err = -ENOMEM;
1570                 goto out_release_regions;
1571         }
1572
1573         err = stex_set_dma_mask(pdev);
1574         if (err) {
1575                 printk(KERN_ERR DRV_NAME "(%s): set dma mask failed\n",
1576                         pci_name(pdev));
1577                 goto out_iounmap;
1578         }
1579
1580         hba->cardtype = (unsigned int) id->driver_data;
1581         ci = &stex_card_info[hba->cardtype];
1582         sts_offset = scratch_offset = (ci->rq_count+1) * ci->rq_size;
1583         if (hba->cardtype == st_yel)
1584                 sts_offset += (ci->sts_count+1) * sizeof(u32);
1585         cp_offset = sts_offset + (ci->sts_count+1) * sizeof(struct status_msg);
1586         hba->dma_size = cp_offset + sizeof(struct st_frame);
1587         if (hba->cardtype == st_seq ||
1588                 (hba->cardtype == st_vsc && (pdev->subsystem_device & 1))) {
1589                 hba->extra_offset = hba->dma_size;
1590                 hba->dma_size += ST_ADDITIONAL_MEM;
1591         }
1592         hba->dma_mem = dma_alloc_coherent(&pdev->dev,
1593                 hba->dma_size, &hba->dma_handle, GFP_KERNEL);
1594         if (!hba->dma_mem) {
1595                 /* Retry minimum coherent mapping for st_seq and st_vsc */
1596                 if (hba->cardtype == st_seq ||
1597                     (hba->cardtype == st_vsc && (pdev->subsystem_device & 1))) {
1598                         printk(KERN_WARNING DRV_NAME
1599                                 "(%s): allocating min buffer for controller\n",
1600                                 pci_name(pdev));
1601                         hba->dma_size = hba->extra_offset
1602                                 + ST_ADDITIONAL_MEM_MIN;
1603                         hba->dma_mem = dma_alloc_coherent(&pdev->dev,
1604                                 hba->dma_size, &hba->dma_handle, GFP_KERNEL);
1605                 }
1606
1607                 if (!hba->dma_mem) {
1608                         err = -ENOMEM;
1609                         printk(KERN_ERR DRV_NAME "(%s): dma mem alloc failed\n",
1610                                 pci_name(pdev));
1611                         goto out_iounmap;
1612                 }
1613         }
1614
1615         hba->ccb = kcalloc(ci->rq_count, sizeof(struct st_ccb), GFP_KERNEL);
1616         if (!hba->ccb) {
1617                 err = -ENOMEM;
1618                 printk(KERN_ERR DRV_NAME "(%s): ccb alloc failed\n",
1619                         pci_name(pdev));
1620                 goto out_pci_free;
1621         }
1622
1623         if (hba->cardtype == st_yel)
1624                 hba->scratch = (__le32 *)(hba->dma_mem + scratch_offset);
1625         hba->status_buffer = (struct status_msg *)(hba->dma_mem + sts_offset);
1626         hba->copy_buffer = hba->dma_mem + cp_offset;
1627         hba->rq_count = ci->rq_count;
1628         hba->rq_size = ci->rq_size;
1629         hba->sts_count = ci->sts_count;
1630         hba->alloc_rq = ci->alloc_rq;
1631         hba->map_sg = ci->map_sg;
1632         hba->send = ci->send;
1633         hba->mu_status = MU_STATE_STARTING;
1634
1635         if (hba->cardtype == st_yel)
1636                 host->sg_tablesize = 38;
1637         else
1638                 host->sg_tablesize = 32;
1639         host->can_queue = ci->rq_count;
1640         host->cmd_per_lun = ci->rq_count;
1641         host->max_id = ci->max_id;
1642         host->max_lun = ci->max_lun;
1643         host->max_channel = ci->max_channel;
1644         host->unique_id = host->host_no;
1645         host->max_cmd_len = STEX_CDB_LENGTH;
1646
1647         hba->host = host;
1648         hba->pdev = pdev;
1649         init_waitqueue_head(&hba->reset_waitq);
1650
1651         snprintf(hba->work_q_name, sizeof(hba->work_q_name),
1652                  "stex_wq_%d", host->host_no);
1653         hba->work_q = create_singlethread_workqueue(hba->work_q_name);
1654         if (!hba->work_q) {
1655                 printk(KERN_ERR DRV_NAME "(%s): create workqueue failed\n",
1656                         pci_name(pdev));
1657                 err = -ENOMEM;
1658                 goto out_ccb_free;
1659         }
1660         INIT_WORK(&hba->reset_work, stex_reset_work);
1661
1662         err = stex_request_irq(hba);
1663         if (err) {
1664                 printk(KERN_ERR DRV_NAME "(%s): request irq failed\n",
1665                         pci_name(pdev));
1666                 goto out_free_wq;
1667         }
1668
1669         err = stex_handshake(hba);
1670         if (err)
1671                 goto out_free_irq;
1672
1673         err = scsi_init_shared_tag_map(host, host->can_queue);
1674         if (err) {
1675                 printk(KERN_ERR DRV_NAME "(%s): init shared queue failed\n",
1676                         pci_name(pdev));
1677                 goto out_free_irq;
1678         }
1679
1680         pci_set_drvdata(pdev, hba);
1681
1682         err = scsi_add_host(host, &pdev->dev);
1683         if (err) {
1684                 printk(KERN_ERR DRV_NAME "(%s): scsi_add_host failed\n",
1685                         pci_name(pdev));
1686                 goto out_free_irq;
1687         }
1688
1689         scsi_scan_host(host);
1690
1691         return 0;
1692
1693 out_free_irq:
1694         stex_free_irq(hba);
1695 out_free_wq:
1696         destroy_workqueue(hba->work_q);
1697 out_ccb_free:
1698         kfree(hba->ccb);
1699 out_pci_free:
1700         dma_free_coherent(&pdev->dev, hba->dma_size,
1701                           hba->dma_mem, hba->dma_handle);
1702 out_iounmap:
1703         iounmap(hba->mmio_base);
1704 out_release_regions:
1705         pci_release_regions(pdev);
1706 out_scsi_host_put:
1707         scsi_host_put(host);
1708 out_disable:
1709         pci_disable_device(pdev);
1710
1711         return err;
1712 }
1713
1714 static void stex_hba_stop(struct st_hba *hba)
1715 {
1716         struct req_msg *req;
1717         struct st_msg_header *msg_h;
1718         unsigned long flags;
1719         unsigned long before;
1720         u16 tag = 0;
1721
1722         spin_lock_irqsave(hba->host->host_lock, flags);
1723         req = hba->alloc_rq(hba);
1724         if (hba->cardtype == st_yel) {
1725                 msg_h = (struct st_msg_header *)req - 1;
1726                 memset(msg_h, 0, hba->rq_size);
1727         } else
1728                 memset(req, 0, hba->rq_size);
1729
1730         if (hba->cardtype == st_yosemite || hba->cardtype == st_yel) {
1731                 req->cdb[0] = MGT_CMD;
1732                 req->cdb[1] = MGT_CMD_SIGNATURE;
1733                 req->cdb[2] = CTLR_CONFIG_CMD;
1734                 req->cdb[3] = CTLR_SHUTDOWN;
1735         } else {
1736                 req->cdb[0] = CONTROLLER_CMD;
1737                 req->cdb[1] = CTLR_POWER_STATE_CHANGE;
1738                 req->cdb[2] = CTLR_POWER_SAVING;
1739         }
1740
1741         hba->ccb[tag].cmd = NULL;
1742         hba->ccb[tag].sg_count = 0;
1743         hba->ccb[tag].sense_bufflen = 0;
1744         hba->ccb[tag].sense_buffer = NULL;
1745         hba->ccb[tag].req_type = PASSTHRU_REQ_TYPE;
1746
1747         hba->send(hba, req, tag);
1748         spin_unlock_irqrestore(hba->host->host_lock, flags);
1749
1750         before = jiffies;
1751         while (hba->ccb[tag].req_type & PASSTHRU_REQ_TYPE) {
1752                 if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ)) {
1753                         hba->ccb[tag].req_type = 0;
1754                         return;
1755                 }
1756                 msleep(1);
1757         }
1758 }
1759
1760 static void stex_hba_free(struct st_hba *hba)
1761 {
1762         stex_free_irq(hba);
1763
1764         destroy_workqueue(hba->work_q);
1765
1766         iounmap(hba->mmio_base);
1767
1768         pci_release_regions(hba->pdev);
1769
1770         kfree(hba->ccb);
1771
1772         dma_free_coherent(&hba->pdev->dev, hba->dma_size,
1773                           hba->dma_mem, hba->dma_handle);
1774 }
1775
1776 static void stex_remove(struct pci_dev *pdev)
1777 {
1778         struct st_hba *hba = pci_get_drvdata(pdev);
1779
1780         scsi_remove_host(hba->host);
1781
1782         stex_hba_stop(hba);
1783
1784         stex_hba_free(hba);
1785
1786         scsi_host_put(hba->host);
1787
1788         pci_disable_device(pdev);
1789 }
1790
1791 static void stex_shutdown(struct pci_dev *pdev)
1792 {
1793         struct st_hba *hba = pci_get_drvdata(pdev);
1794
1795         stex_hba_stop(hba);
1796 }
1797
1798 MODULE_DEVICE_TABLE(pci, stex_pci_tbl);
1799
1800 static struct pci_driver stex_pci_driver = {
1801         .name           = DRV_NAME,
1802         .id_table       = stex_pci_tbl,
1803         .probe          = stex_probe,
1804         .remove         = stex_remove,
1805         .shutdown       = stex_shutdown,
1806 };
1807
1808 static int __init stex_init(void)
1809 {
1810         printk(KERN_INFO DRV_NAME
1811                 ": Promise SuperTrak EX Driver version: %s\n",
1812                  ST_DRIVER_VERSION);
1813
1814         return pci_register_driver(&stex_pci_driver);
1815 }
1816
1817 static void __exit stex_exit(void)
1818 {
1819         pci_unregister_driver(&stex_pci_driver);
1820 }
1821
1822 module_init(stex_init);
1823 module_exit(stex_exit);