2 * linux/drivers/char/8250.c
4 * Driver for 8250/16550-type serial ports
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
8 * Copyright (C) 2001 Russell King.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * A note about mapbase / membase
17 * mapbase is the physical address of the IO port.
18 * membase is an 'ioremapped' cookie.
21 #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
25 #include <linux/module.h>
26 #include <linux/moduleparam.h>
27 #include <linux/ioport.h>
28 #include <linux/init.h>
29 #include <linux/console.h>
30 #include <linux/sysrq.h>
31 #include <linux/delay.h>
32 #include <linux/platform_device.h>
33 #include <linux/tty.h>
34 #include <linux/tty_flip.h>
35 #include <linux/serial_reg.h>
36 #include <linux/serial_core.h>
37 #include <linux/serial.h>
38 #include <linux/serial_8250.h>
39 #include <linux/nmi.h>
40 #include <linux/mutex.h>
41 #include <linux/slab.h>
54 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
55 * is unsafe when used on edge-triggered interrupts.
57 static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
59 static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
61 static struct uart_driver serial8250_reg;
63 static int serial_index(struct uart_port *port)
65 return (serial8250_reg.minor - 64) + port->line;
68 static unsigned int skip_txen_test; /* force skip of txen test at init time */
74 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
76 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
80 #define DEBUG_INTR(fmt...) printk(fmt)
82 #define DEBUG_INTR(fmt...) do { } while (0)
85 #define PASS_LIMIT 256
87 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
91 * We default to IRQ0 for the "no irq" hack. Some
92 * machine types want others as well - they're free
93 * to redefine this in their header file.
95 #define is_real_interrupt(irq) ((irq) != 0)
97 #ifdef CONFIG_SERIAL_8250_DETECT_IRQ
98 #define CONFIG_SERIAL_DETECT_IRQ 1
100 #ifdef CONFIG_SERIAL_8250_MANY_PORTS
101 #define CONFIG_SERIAL_MANY_PORTS 1
105 * HUB6 is always on. This will be removed once the header
106 * files have been cleaned.
108 #define CONFIG_HUB6 1
110 #include <asm/serial.h>
112 * SERIAL_PORT_DFNS tells us about built-in ports that have no
113 * standard enumeration mechanism. Platforms that can find all
114 * serial ports via mechanisms like ACPI or PCI need not supply it.
116 #ifndef SERIAL_PORT_DFNS
117 #define SERIAL_PORT_DFNS
120 static const struct old_serial_port old_serial_port[] = {
121 SERIAL_PORT_DFNS /* defined in asm/serial.h */
124 #define UART_NR CONFIG_SERIAL_8250_NR_UARTS
126 #ifdef CONFIG_SERIAL_8250_RSA
128 #define PORT_RSA_MAX 4
129 static unsigned long probe_rsa[PORT_RSA_MAX];
130 static unsigned int probe_rsa_count;
131 #endif /* CONFIG_SERIAL_8250_RSA */
133 struct uart_8250_port {
134 struct uart_port port;
135 struct timer_list timer; /* "no irq" timer */
136 struct list_head list; /* ports on this IRQ */
137 unsigned short capabilities; /* port capabilities */
138 unsigned short bugs; /* port bugs */
139 unsigned int tx_loadsz; /* transmit fifo load size */
144 unsigned char mcr_mask; /* mask of user bits */
145 unsigned char mcr_force; /* mask of forced bits */
146 unsigned char cur_iotype; /* Running I/O type */
149 * Some bits in registers are cleared on a read, so they must
150 * be saved whenever the register is read but the bits will not
151 * be immediately processed.
153 #define LSR_SAVE_FLAGS UART_LSR_BRK_ERROR_BITS
154 unsigned char lsr_saved_flags;
155 #define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
156 unsigned char msr_saved_flags;
159 * We provide a per-port pm hook.
161 void (*pm)(struct uart_port *port,
162 unsigned int state, unsigned int old);
166 struct hlist_node node;
168 spinlock_t lock; /* Protects list not the hash */
169 struct list_head *head;
172 #define NR_IRQ_HASH 32 /* Can be adjusted later */
173 static struct hlist_head irq_lists[NR_IRQ_HASH];
174 static DEFINE_MUTEX(hash_mutex); /* Used to walk the hash */
177 * Here we define the default xmit fifo size used for each type of UART.
179 static const struct serial8250_config uart_config[] = {
204 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
205 .flags = UART_CAP_FIFO,
216 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
222 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
224 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
230 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
232 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
240 .name = "16C950/954",
243 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
244 .flags = UART_CAP_FIFO,
250 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
252 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
258 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
259 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
265 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
266 .flags = UART_CAP_FIFO,
272 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
273 .flags = UART_CAP_FIFO | UART_NATSEMI,
279 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
280 .flags = UART_CAP_FIFO | UART_CAP_UUE,
286 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
287 .flags = UART_CAP_FIFO,
293 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
294 .flags = UART_CAP_FIFO,
300 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
301 .flags = UART_CAP_FIFO | UART_CAP_AFE,
305 #if defined(CONFIG_MIPS_ALCHEMY)
307 /* Au1x00 UART hardware has a weird register layout */
308 static const u8 au_io_in_map[] = {
318 static const u8 au_io_out_map[] = {
326 /* sane hardware needs no mapping */
327 static inline int map_8250_in_reg(struct uart_port *p, int offset)
329 if (p->iotype != UPIO_AU)
331 return au_io_in_map[offset];
334 static inline int map_8250_out_reg(struct uart_port *p, int offset)
336 if (p->iotype != UPIO_AU)
338 return au_io_out_map[offset];
341 #elif defined(CONFIG_SERIAL_8250_RM9K)
365 static inline int map_8250_in_reg(struct uart_port *p, int offset)
367 if (p->iotype != UPIO_RM9000)
369 return regmap_in[offset];
372 static inline int map_8250_out_reg(struct uart_port *p, int offset)
374 if (p->iotype != UPIO_RM9000)
376 return regmap_out[offset];
381 /* sane hardware needs no mapping */
382 #define map_8250_in_reg(up, offset) (offset)
383 #define map_8250_out_reg(up, offset) (offset)
387 static unsigned int hub6_serial_in(struct uart_port *p, int offset)
389 offset = map_8250_in_reg(p, offset) << p->regshift;
390 outb(p->hub6 - 1 + offset, p->iobase);
391 return inb(p->iobase + 1);
394 static void hub6_serial_out(struct uart_port *p, int offset, int value)
396 offset = map_8250_out_reg(p, offset) << p->regshift;
397 outb(p->hub6 - 1 + offset, p->iobase);
398 outb(value, p->iobase + 1);
401 static unsigned int mem_serial_in(struct uart_port *p, int offset)
403 offset = map_8250_in_reg(p, offset) << p->regshift;
404 return readb(p->membase + offset);
407 static void mem_serial_out(struct uart_port *p, int offset, int value)
409 offset = map_8250_out_reg(p, offset) << p->regshift;
410 writeb(value, p->membase + offset);
413 static void mem32_serial_out(struct uart_port *p, int offset, int value)
415 offset = map_8250_out_reg(p, offset) << p->regshift;
416 writel(value, p->membase + offset);
419 static unsigned int mem32_serial_in(struct uart_port *p, int offset)
421 offset = map_8250_in_reg(p, offset) << p->regshift;
422 return readl(p->membase + offset);
425 static unsigned int au_serial_in(struct uart_port *p, int offset)
427 offset = map_8250_in_reg(p, offset) << p->regshift;
428 return __raw_readl(p->membase + offset);
431 static void au_serial_out(struct uart_port *p, int offset, int value)
433 offset = map_8250_out_reg(p, offset) << p->regshift;
434 __raw_writel(value, p->membase + offset);
437 static unsigned int tsi_serial_in(struct uart_port *p, int offset)
440 offset = map_8250_in_reg(p, offset) << p->regshift;
441 if (offset == UART_IIR) {
442 tmp = readl(p->membase + (UART_IIR & ~3));
443 return (tmp >> 16) & 0xff; /* UART_IIR % 4 == 2 */
445 return readb(p->membase + offset);
448 static void tsi_serial_out(struct uart_port *p, int offset, int value)
450 offset = map_8250_out_reg(p, offset) << p->regshift;
451 if (!((offset == UART_IER) && (value & UART_IER_UUE)))
452 writeb(value, p->membase + offset);
455 static void dwapb_serial_out(struct uart_port *p, int offset, int value)
457 int save_offset = offset;
458 offset = map_8250_out_reg(p, offset) << p->regshift;
459 /* Save the LCR value so it can be re-written when a
460 * Busy Detect interrupt occurs. */
461 if (save_offset == UART_LCR) {
462 struct uart_8250_port *up = (struct uart_8250_port *)p;
465 writeb(value, p->membase + offset);
466 /* Read the IER to ensure any interrupt is cleared before
467 * returning from ISR. */
468 if (save_offset == UART_TX || save_offset == UART_IER)
469 value = p->serial_in(p, UART_IER);
472 static unsigned int io_serial_in(struct uart_port *p, int offset)
474 offset = map_8250_in_reg(p, offset) << p->regshift;
475 return inb(p->iobase + offset);
478 static void io_serial_out(struct uart_port *p, int offset, int value)
480 offset = map_8250_out_reg(p, offset) << p->regshift;
481 outb(value, p->iobase + offset);
484 static void set_io_from_upio(struct uart_port *p)
486 struct uart_8250_port *up = (struct uart_8250_port *)p;
489 p->serial_in = hub6_serial_in;
490 p->serial_out = hub6_serial_out;
494 p->serial_in = mem_serial_in;
495 p->serial_out = mem_serial_out;
500 p->serial_in = mem32_serial_in;
501 p->serial_out = mem32_serial_out;
505 p->serial_in = au_serial_in;
506 p->serial_out = au_serial_out;
510 p->serial_in = tsi_serial_in;
511 p->serial_out = tsi_serial_out;
515 p->serial_in = mem_serial_in;
516 p->serial_out = dwapb_serial_out;
520 p->serial_in = io_serial_in;
521 p->serial_out = io_serial_out;
524 /* Remember loaded iotype */
525 up->cur_iotype = p->iotype;
529 serial_out_sync(struct uart_8250_port *up, int offset, int value)
531 struct uart_port *p = &up->port;
537 p->serial_out(p, offset, value);
538 p->serial_in(p, UART_LCR); /* safe, no side-effects */
541 p->serial_out(p, offset, value);
545 #define serial_in(up, offset) \
546 (up->port.serial_in(&(up)->port, (offset)))
547 #define serial_out(up, offset, value) \
548 (up->port.serial_out(&(up)->port, (offset), (value)))
550 * We used to support using pause I/O for certain machines. We
551 * haven't supported this for a while, but just in case it's badly
552 * needed for certain old 386 machines, I've left these #define's
555 #define serial_inp(up, offset) serial_in(up, offset)
556 #define serial_outp(up, offset, value) serial_out(up, offset, value)
558 /* Uart divisor latch read */
559 static inline int _serial_dl_read(struct uart_8250_port *up)
561 return serial_inp(up, UART_DLL) | serial_inp(up, UART_DLM) << 8;
564 /* Uart divisor latch write */
565 static inline void _serial_dl_write(struct uart_8250_port *up, int value)
567 serial_outp(up, UART_DLL, value & 0xff);
568 serial_outp(up, UART_DLM, value >> 8 & 0xff);
571 #if defined(CONFIG_MIPS_ALCHEMY)
572 /* Au1x00 haven't got a standard divisor latch */
573 static int serial_dl_read(struct uart_8250_port *up)
575 if (up->port.iotype == UPIO_AU)
576 return __raw_readl(up->port.membase + 0x28);
578 return _serial_dl_read(up);
581 static void serial_dl_write(struct uart_8250_port *up, int value)
583 if (up->port.iotype == UPIO_AU)
584 __raw_writel(value, up->port.membase + 0x28);
586 _serial_dl_write(up, value);
588 #elif defined(CONFIG_SERIAL_8250_RM9K)
589 static int serial_dl_read(struct uart_8250_port *up)
591 return (up->port.iotype == UPIO_RM9000) ?
592 (((__raw_readl(up->port.membase + 0x10) << 8) |
593 (__raw_readl(up->port.membase + 0x08) & 0xff)) & 0xffff) :
597 static void serial_dl_write(struct uart_8250_port *up, int value)
599 if (up->port.iotype == UPIO_RM9000) {
600 __raw_writel(value, up->port.membase + 0x08);
601 __raw_writel(value >> 8, up->port.membase + 0x10);
603 _serial_dl_write(up, value);
607 #define serial_dl_read(up) _serial_dl_read(up)
608 #define serial_dl_write(up, value) _serial_dl_write(up, value)
614 static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
616 serial_out(up, UART_SCR, offset);
617 serial_out(up, UART_ICR, value);
620 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
624 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
625 serial_out(up, UART_SCR, offset);
626 value = serial_in(up, UART_ICR);
627 serial_icr_write(up, UART_ACR, up->acr);
635 static void serial8250_clear_fifos(struct uart_8250_port *p)
637 if (p->capabilities & UART_CAP_FIFO) {
638 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO);
639 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO |
640 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
641 serial_outp(p, UART_FCR, 0);
646 * IER sleep support. UARTs which have EFRs need the "extended
647 * capability" bit enabled. Note that on XR16C850s, we need to
648 * reset LCR to write to IER.
650 static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
652 if (p->capabilities & UART_CAP_SLEEP) {
653 if (p->capabilities & UART_CAP_EFR) {
654 serial_outp(p, UART_LCR, 0xBF);
655 serial_outp(p, UART_EFR, UART_EFR_ECB);
656 serial_outp(p, UART_LCR, 0);
658 serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
659 if (p->capabilities & UART_CAP_EFR) {
660 serial_outp(p, UART_LCR, 0xBF);
661 serial_outp(p, UART_EFR, 0);
662 serial_outp(p, UART_LCR, 0);
667 #ifdef CONFIG_SERIAL_8250_RSA
669 * Attempts to turn on the RSA FIFO. Returns zero on failure.
670 * We set the port uart clock rate if we succeed.
672 static int __enable_rsa(struct uart_8250_port *up)
677 mode = serial_inp(up, UART_RSA_MSR);
678 result = mode & UART_RSA_MSR_FIFO;
681 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
682 mode = serial_inp(up, UART_RSA_MSR);
683 result = mode & UART_RSA_MSR_FIFO;
687 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
692 static void enable_rsa(struct uart_8250_port *up)
694 if (up->port.type == PORT_RSA) {
695 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
696 spin_lock_irq(&up->port.lock);
698 spin_unlock_irq(&up->port.lock);
700 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
701 serial_outp(up, UART_RSA_FRR, 0);
706 * Attempts to turn off the RSA FIFO. Returns zero on failure.
707 * It is unknown why interrupts were disabled in here. However,
708 * the caller is expected to preserve this behaviour by grabbing
709 * the spinlock before calling this function.
711 static void disable_rsa(struct uart_8250_port *up)
716 if (up->port.type == PORT_RSA &&
717 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
718 spin_lock_irq(&up->port.lock);
720 mode = serial_inp(up, UART_RSA_MSR);
721 result = !(mode & UART_RSA_MSR_FIFO);
724 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
725 mode = serial_inp(up, UART_RSA_MSR);
726 result = !(mode & UART_RSA_MSR_FIFO);
730 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
731 spin_unlock_irq(&up->port.lock);
734 #endif /* CONFIG_SERIAL_8250_RSA */
737 * This is a quickie test to see how big the FIFO is.
738 * It doesn't work at all the time, more's the pity.
740 static int size_fifo(struct uart_8250_port *up)
742 unsigned char old_fcr, old_mcr, old_lcr;
743 unsigned short old_dl;
746 old_lcr = serial_inp(up, UART_LCR);
747 serial_outp(up, UART_LCR, 0);
748 old_fcr = serial_inp(up, UART_FCR);
749 old_mcr = serial_inp(up, UART_MCR);
750 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
751 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
752 serial_outp(up, UART_MCR, UART_MCR_LOOP);
753 serial_outp(up, UART_LCR, UART_LCR_DLAB);
754 old_dl = serial_dl_read(up);
755 serial_dl_write(up, 0x0001);
756 serial_outp(up, UART_LCR, 0x03);
757 for (count = 0; count < 256; count++)
758 serial_outp(up, UART_TX, count);
759 mdelay(20);/* FIXME - schedule_timeout */
760 for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) &&
761 (count < 256); count++)
762 serial_inp(up, UART_RX);
763 serial_outp(up, UART_FCR, old_fcr);
764 serial_outp(up, UART_MCR, old_mcr);
765 serial_outp(up, UART_LCR, UART_LCR_DLAB);
766 serial_dl_write(up, old_dl);
767 serial_outp(up, UART_LCR, old_lcr);
773 * Read UART ID using the divisor method - set DLL and DLM to zero
774 * and the revision will be in DLL and device type in DLM. We
775 * preserve the device state across this.
777 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
779 unsigned char old_dll, old_dlm, old_lcr;
782 old_lcr = serial_inp(p, UART_LCR);
783 serial_outp(p, UART_LCR, UART_LCR_DLAB);
785 old_dll = serial_inp(p, UART_DLL);
786 old_dlm = serial_inp(p, UART_DLM);
788 serial_outp(p, UART_DLL, 0);
789 serial_outp(p, UART_DLM, 0);
791 id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8;
793 serial_outp(p, UART_DLL, old_dll);
794 serial_outp(p, UART_DLM, old_dlm);
795 serial_outp(p, UART_LCR, old_lcr);
801 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
802 * When this function is called we know it is at least a StarTech
803 * 16650 V2, but it might be one of several StarTech UARTs, or one of
804 * its clones. (We treat the broken original StarTech 16650 V1 as a
805 * 16550, and why not? Startech doesn't seem to even acknowledge its
808 * What evil have men's minds wrought...
810 static void autoconfig_has_efr(struct uart_8250_port *up)
812 unsigned int id1, id2, id3, rev;
815 * Everything with an EFR has SLEEP
817 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
820 * First we check to see if it's an Oxford Semiconductor UART.
822 * If we have to do this here because some non-National
823 * Semiconductor clone chips lock up if you try writing to the
824 * LSR register (which serial_icr_read does)
828 * Check for Oxford Semiconductor 16C950.
830 * EFR [4] must be set else this test fails.
832 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
833 * claims that it's needed for 952 dual UART's (which are not
834 * recommended for new designs).
837 serial_out(up, UART_LCR, 0xBF);
838 serial_out(up, UART_EFR, UART_EFR_ECB);
839 serial_out(up, UART_LCR, 0x00);
840 id1 = serial_icr_read(up, UART_ID1);
841 id2 = serial_icr_read(up, UART_ID2);
842 id3 = serial_icr_read(up, UART_ID3);
843 rev = serial_icr_read(up, UART_REV);
845 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
847 if (id1 == 0x16 && id2 == 0xC9 &&
848 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
849 up->port.type = PORT_16C950;
852 * Enable work around for the Oxford Semiconductor 952 rev B
853 * chip which causes it to seriously miscalculate baud rates
856 if (id3 == 0x52 && rev == 0x01)
857 up->bugs |= UART_BUG_QUOT;
862 * We check for a XR16C850 by setting DLL and DLM to 0, and then
863 * reading back DLL and DLM. The chip type depends on the DLM
865 * 0x10 - XR16C850 and the DLL contains the chip revision.
869 id1 = autoconfig_read_divisor_id(up);
870 DEBUG_AUTOCONF("850id=%04x ", id1);
873 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
874 up->port.type = PORT_16850;
879 * It wasn't an XR16C850.
881 * We distinguish between the '654 and the '650 by counting
882 * how many bytes are in the FIFO. I'm using this for now,
883 * since that's the technique that was sent to me in the
884 * serial driver update, but I'm not convinced this works.
885 * I've had problems doing this in the past. -TYT
887 if (size_fifo(up) == 64)
888 up->port.type = PORT_16654;
890 up->port.type = PORT_16650V2;
894 * We detected a chip without a FIFO. Only two fall into
895 * this category - the original 8250 and the 16450. The
896 * 16450 has a scratch register (accessible with LCR=0)
898 static void autoconfig_8250(struct uart_8250_port *up)
900 unsigned char scratch, status1, status2;
902 up->port.type = PORT_8250;
904 scratch = serial_in(up, UART_SCR);
905 serial_outp(up, UART_SCR, 0xa5);
906 status1 = serial_in(up, UART_SCR);
907 serial_outp(up, UART_SCR, 0x5a);
908 status2 = serial_in(up, UART_SCR);
909 serial_outp(up, UART_SCR, scratch);
911 if (status1 == 0xa5 && status2 == 0x5a)
912 up->port.type = PORT_16450;
915 static int broken_efr(struct uart_8250_port *up)
918 * Exar ST16C2550 "A2" devices incorrectly detect as
919 * having an EFR, and report an ID of 0x0201. See
920 * http://www.exar.com/info.php?pdf=dan180_oct2004.pdf
922 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
929 * We know that the chip has FIFOs. Does it have an EFR? The
930 * EFR is located in the same register position as the IIR and
931 * we know the top two bits of the IIR are currently set. The
932 * EFR should contain zero. Try to read the EFR.
934 static void autoconfig_16550a(struct uart_8250_port *up)
936 unsigned char status1, status2;
937 unsigned int iersave;
939 up->port.type = PORT_16550A;
940 up->capabilities |= UART_CAP_FIFO;
943 * Check for presence of the EFR when DLAB is set.
944 * Only ST16C650V1 UARTs pass this test.
946 serial_outp(up, UART_LCR, UART_LCR_DLAB);
947 if (serial_in(up, UART_EFR) == 0) {
948 serial_outp(up, UART_EFR, 0xA8);
949 if (serial_in(up, UART_EFR) != 0) {
950 DEBUG_AUTOCONF("EFRv1 ");
951 up->port.type = PORT_16650;
952 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
954 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
956 serial_outp(up, UART_EFR, 0);
961 * Maybe it requires 0xbf to be written to the LCR.
962 * (other ST16C650V2 UARTs, TI16C752A, etc)
964 serial_outp(up, UART_LCR, 0xBF);
965 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
966 DEBUG_AUTOCONF("EFRv2 ");
967 autoconfig_has_efr(up);
972 * Check for a National Semiconductor SuperIO chip.
973 * Attempt to switch to bank 2, read the value of the LOOP bit
974 * from EXCR1. Switch back to bank 0, change it in MCR. Then
975 * switch back to bank 2, read it from EXCR1 again and check
976 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
978 serial_outp(up, UART_LCR, 0);
979 status1 = serial_in(up, UART_MCR);
980 serial_outp(up, UART_LCR, 0xE0);
981 status2 = serial_in(up, 0x02); /* EXCR1 */
983 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
984 serial_outp(up, UART_LCR, 0);
985 serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP);
986 serial_outp(up, UART_LCR, 0xE0);
987 status2 = serial_in(up, 0x02); /* EXCR1 */
988 serial_outp(up, UART_LCR, 0);
989 serial_outp(up, UART_MCR, status1);
991 if ((status2 ^ status1) & UART_MCR_LOOP) {
994 serial_outp(up, UART_LCR, 0xE0);
996 quot = serial_dl_read(up);
999 status1 = serial_in(up, 0x04); /* EXCR2 */
1000 status1 &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
1001 status1 |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
1002 serial_outp(up, 0x04, status1);
1004 serial_dl_write(up, quot);
1006 serial_outp(up, UART_LCR, 0);
1008 up->port.uartclk = 921600*16;
1009 up->port.type = PORT_NS16550A;
1010 up->capabilities |= UART_NATSEMI;
1016 * No EFR. Try to detect a TI16750, which only sets bit 5 of
1017 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
1018 * Try setting it with and without DLAB set. Cheap clones
1019 * set bit 5 without DLAB set.
1021 serial_outp(up, UART_LCR, 0);
1022 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1023 status1 = serial_in(up, UART_IIR) >> 5;
1024 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1025 serial_outp(up, UART_LCR, UART_LCR_DLAB);
1026 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1027 status2 = serial_in(up, UART_IIR) >> 5;
1028 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1029 serial_outp(up, UART_LCR, 0);
1031 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1033 if (status1 == 6 && status2 == 7) {
1034 up->port.type = PORT_16750;
1035 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1040 * Try writing and reading the UART_IER_UUE bit (b6).
1041 * If it works, this is probably one of the Xscale platform's
1043 * We're going to explicitly set the UUE bit to 0 before
1044 * trying to write and read a 1 just to make sure it's not
1045 * already a 1 and maybe locked there before we even start start.
1047 iersave = serial_in(up, UART_IER);
1048 serial_outp(up, UART_IER, iersave & ~UART_IER_UUE);
1049 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1051 * OK it's in a known zero state, try writing and reading
1052 * without disturbing the current state of the other bits.
1054 serial_outp(up, UART_IER, iersave | UART_IER_UUE);
1055 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1058 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1060 DEBUG_AUTOCONF("Xscale ");
1061 up->port.type = PORT_XSCALE;
1062 up->capabilities |= UART_CAP_UUE;
1067 * If we got here we couldn't force the IER_UUE bit to 0.
1068 * Log it and continue.
1070 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1072 serial_outp(up, UART_IER, iersave);
1076 * This routine is called by rs_init() to initialize a specific serial
1077 * port. It determines what type of UART chip this serial port is
1078 * using: 8250, 16450, 16550, 16550A. The important question is
1079 * whether or not this UART is a 16550A or not, since this will
1080 * determine whether or not we can use its FIFO features or not.
1082 static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
1084 unsigned char status1, scratch, scratch2, scratch3;
1085 unsigned char save_lcr, save_mcr;
1086 unsigned long flags;
1088 if (!up->port.iobase && !up->port.mapbase && !up->port.membase)
1091 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
1092 serial_index(&up->port), up->port.iobase, up->port.membase);
1095 * We really do need global IRQs disabled here - we're going to
1096 * be frobbing the chips IRQ enable register to see if it exists.
1098 spin_lock_irqsave(&up->port.lock, flags);
1100 up->capabilities = 0;
1103 if (!(up->port.flags & UPF_BUGGY_UART)) {
1105 * Do a simple existence test first; if we fail this,
1106 * there's no point trying anything else.
1108 * 0x80 is used as a nonsense port to prevent against
1109 * false positives due to ISA bus float. The
1110 * assumption is that 0x80 is a non-existent port;
1111 * which should be safe since include/asm/io.h also
1112 * makes this assumption.
1114 * Note: this is safe as long as MCR bit 4 is clear
1115 * and the device is in "PC" mode.
1117 scratch = serial_inp(up, UART_IER);
1118 serial_outp(up, UART_IER, 0);
1123 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1124 * 16C754B) allow only to modify them if an EFR bit is set.
1126 scratch2 = serial_inp(up, UART_IER) & 0x0f;
1127 serial_outp(up, UART_IER, 0x0F);
1131 scratch3 = serial_inp(up, UART_IER) & 0x0f;
1132 serial_outp(up, UART_IER, scratch);
1133 if (scratch2 != 0 || scratch3 != 0x0F) {
1135 * We failed; there's nothing here
1137 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1138 scratch2, scratch3);
1143 save_mcr = serial_in(up, UART_MCR);
1144 save_lcr = serial_in(up, UART_LCR);
1147 * Check to see if a UART is really there. Certain broken
1148 * internal modems based on the Rockwell chipset fail this
1149 * test, because they apparently don't implement the loopback
1150 * test mode. So this test is skipped on the COM 1 through
1151 * COM 4 ports. This *should* be safe, since no board
1152 * manufacturer would be stupid enough to design a board
1153 * that conflicts with COM 1-4 --- we hope!
1155 if (!(up->port.flags & UPF_SKIP_TEST)) {
1156 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1157 status1 = serial_inp(up, UART_MSR) & 0xF0;
1158 serial_outp(up, UART_MCR, save_mcr);
1159 if (status1 != 0x90) {
1160 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1167 * We're pretty sure there's a port here. Lets find out what
1168 * type of port it is. The IIR top two bits allows us to find
1169 * out if it's 8250 or 16450, 16550, 16550A or later. This
1170 * determines what we test for next.
1172 * We also initialise the EFR (if any) to zero for later. The
1173 * EFR occupies the same register location as the FCR and IIR.
1175 serial_outp(up, UART_LCR, 0xBF);
1176 serial_outp(up, UART_EFR, 0);
1177 serial_outp(up, UART_LCR, 0);
1179 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1180 scratch = serial_in(up, UART_IIR) >> 6;
1182 DEBUG_AUTOCONF("iir=%d ", scratch);
1186 autoconfig_8250(up);
1189 up->port.type = PORT_UNKNOWN;
1192 up->port.type = PORT_16550;
1195 autoconfig_16550a(up);
1199 #ifdef CONFIG_SERIAL_8250_RSA
1201 * Only probe for RSA ports if we got the region.
1203 if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) {
1206 for (i = 0 ; i < probe_rsa_count; ++i) {
1207 if (probe_rsa[i] == up->port.iobase &&
1209 up->port.type = PORT_RSA;
1216 serial_outp(up, UART_LCR, save_lcr);
1218 if (up->capabilities != uart_config[up->port.type].flags) {
1220 "ttyS%d: detected caps %08x should be %08x\n",
1221 serial_index(&up->port), up->capabilities,
1222 uart_config[up->port.type].flags);
1225 up->port.fifosize = uart_config[up->port.type].fifo_size;
1226 up->capabilities = uart_config[up->port.type].flags;
1227 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1229 if (up->port.type == PORT_UNKNOWN)
1235 #ifdef CONFIG_SERIAL_8250_RSA
1236 if (up->port.type == PORT_RSA)
1237 serial_outp(up, UART_RSA_FRR, 0);
1239 serial_outp(up, UART_MCR, save_mcr);
1240 serial8250_clear_fifos(up);
1241 serial_in(up, UART_RX);
1242 if (up->capabilities & UART_CAP_UUE)
1243 serial_outp(up, UART_IER, UART_IER_UUE);
1245 serial_outp(up, UART_IER, 0);
1248 spin_unlock_irqrestore(&up->port.lock, flags);
1249 DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name);
1252 static void autoconfig_irq(struct uart_8250_port *up)
1254 unsigned char save_mcr, save_ier;
1255 unsigned char save_ICP = 0;
1256 unsigned int ICP = 0;
1260 if (up->port.flags & UPF_FOURPORT) {
1261 ICP = (up->port.iobase & 0xfe0) | 0x1f;
1262 save_ICP = inb_p(ICP);
1267 /* forget possible initially masked and pending IRQ */
1268 probe_irq_off(probe_irq_on());
1269 save_mcr = serial_inp(up, UART_MCR);
1270 save_ier = serial_inp(up, UART_IER);
1271 serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
1273 irqs = probe_irq_on();
1274 serial_outp(up, UART_MCR, 0);
1276 if (up->port.flags & UPF_FOURPORT) {
1277 serial_outp(up, UART_MCR,
1278 UART_MCR_DTR | UART_MCR_RTS);
1280 serial_outp(up, UART_MCR,
1281 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1283 serial_outp(up, UART_IER, 0x0f); /* enable all intrs */
1284 (void)serial_inp(up, UART_LSR);
1285 (void)serial_inp(up, UART_RX);
1286 (void)serial_inp(up, UART_IIR);
1287 (void)serial_inp(up, UART_MSR);
1288 serial_outp(up, UART_TX, 0xFF);
1290 irq = probe_irq_off(irqs);
1292 serial_outp(up, UART_MCR, save_mcr);
1293 serial_outp(up, UART_IER, save_ier);
1295 if (up->port.flags & UPF_FOURPORT)
1296 outb_p(save_ICP, ICP);
1298 up->port.irq = (irq > 0) ? irq : 0;
1301 static inline void __stop_tx(struct uart_8250_port *p)
1303 if (p->ier & UART_IER_THRI) {
1304 p->ier &= ~UART_IER_THRI;
1305 serial_out(p, UART_IER, p->ier);
1309 static void serial8250_stop_tx(struct uart_port *port)
1311 struct uart_8250_port *up = (struct uart_8250_port *)port;
1316 * We really want to stop the transmitter from sending.
1318 if (up->port.type == PORT_16C950) {
1319 up->acr |= UART_ACR_TXDIS;
1320 serial_icr_write(up, UART_ACR, up->acr);
1324 static void transmit_chars(struct uart_8250_port *up);
1326 static void serial8250_start_tx(struct uart_port *port)
1328 struct uart_8250_port *up = (struct uart_8250_port *)port;
1330 if (!(up->ier & UART_IER_THRI)) {
1331 up->ier |= UART_IER_THRI;
1332 serial_out(up, UART_IER, up->ier);
1334 if (up->bugs & UART_BUG_TXEN) {
1336 lsr = serial_in(up, UART_LSR);
1337 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1338 if ((up->port.type == PORT_RM9000) ?
1339 (lsr & UART_LSR_THRE) :
1340 (lsr & UART_LSR_TEMT))
1346 * Re-enable the transmitter if we disabled it.
1348 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1349 up->acr &= ~UART_ACR_TXDIS;
1350 serial_icr_write(up, UART_ACR, up->acr);
1354 static void serial8250_stop_rx(struct uart_port *port)
1356 struct uart_8250_port *up = (struct uart_8250_port *)port;
1358 up->ier &= ~UART_IER_RLSI;
1359 up->port.read_status_mask &= ~UART_LSR_DR;
1360 serial_out(up, UART_IER, up->ier);
1363 static void serial8250_enable_ms(struct uart_port *port)
1365 struct uart_8250_port *up = (struct uart_8250_port *)port;
1367 /* no MSR capabilities */
1368 if (up->bugs & UART_BUG_NOMSR)
1371 up->ier |= UART_IER_MSI;
1372 serial_out(up, UART_IER, up->ier);
1376 receive_chars(struct uart_8250_port *up, unsigned int *status)
1378 struct tty_struct *tty = up->port.state->port.tty;
1379 unsigned char ch, lsr = *status;
1380 int max_count = 256;
1384 if (likely(lsr & UART_LSR_DR))
1385 ch = serial_inp(up, UART_RX);
1388 * Intel 82571 has a Serial Over Lan device that will
1389 * set UART_LSR_BI without setting UART_LSR_DR when
1390 * it receives a break. To avoid reading from the
1391 * receive buffer without UART_LSR_DR bit set, we
1392 * just force the read character to be 0
1397 up->port.icount.rx++;
1399 lsr |= up->lsr_saved_flags;
1400 up->lsr_saved_flags = 0;
1402 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1404 * For statistics only
1406 if (lsr & UART_LSR_BI) {
1407 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1408 up->port.icount.brk++;
1410 * We do the SysRQ and SAK checking
1411 * here because otherwise the break
1412 * may get masked by ignore_status_mask
1413 * or read_status_mask.
1415 if (uart_handle_break(&up->port))
1417 } else if (lsr & UART_LSR_PE)
1418 up->port.icount.parity++;
1419 else if (lsr & UART_LSR_FE)
1420 up->port.icount.frame++;
1421 if (lsr & UART_LSR_OE)
1422 up->port.icount.overrun++;
1425 * Mask off conditions which should be ignored.
1427 lsr &= up->port.read_status_mask;
1429 if (lsr & UART_LSR_BI) {
1430 DEBUG_INTR("handling break....");
1432 } else if (lsr & UART_LSR_PE)
1434 else if (lsr & UART_LSR_FE)
1437 if (uart_handle_sysrq_char(&up->port, ch))
1440 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
1443 lsr = serial_inp(up, UART_LSR);
1444 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
1445 spin_unlock(&up->port.lock);
1446 tty_flip_buffer_push(tty);
1447 spin_lock(&up->port.lock);
1451 static void transmit_chars(struct uart_8250_port *up)
1453 struct circ_buf *xmit = &up->port.state->xmit;
1456 if (up->port.x_char) {
1457 serial_outp(up, UART_TX, up->port.x_char);
1458 up->port.icount.tx++;
1459 up->port.x_char = 0;
1462 if (uart_tx_stopped(&up->port)) {
1463 serial8250_stop_tx(&up->port);
1466 if (uart_circ_empty(xmit)) {
1471 count = up->tx_loadsz;
1473 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1474 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1475 up->port.icount.tx++;
1476 if (uart_circ_empty(xmit))
1478 } while (--count > 0);
1480 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1481 uart_write_wakeup(&up->port);
1483 DEBUG_INTR("THRE...");
1485 if (uart_circ_empty(xmit))
1489 static unsigned int check_modem_status(struct uart_8250_port *up)
1491 unsigned int status = serial_in(up, UART_MSR);
1493 status |= up->msr_saved_flags;
1494 up->msr_saved_flags = 0;
1495 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1496 up->port.state != NULL) {
1497 if (status & UART_MSR_TERI)
1498 up->port.icount.rng++;
1499 if (status & UART_MSR_DDSR)
1500 up->port.icount.dsr++;
1501 if (status & UART_MSR_DDCD)
1502 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
1503 if (status & UART_MSR_DCTS)
1504 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
1506 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
1513 * This handles the interrupt from one port.
1515 static void serial8250_handle_port(struct uart_8250_port *up)
1517 unsigned int status;
1518 unsigned long flags;
1520 spin_lock_irqsave(&up->port.lock, flags);
1522 status = serial_inp(up, UART_LSR);
1524 DEBUG_INTR("status = %x...", status);
1526 if (status & (UART_LSR_DR | UART_LSR_BI))
1527 receive_chars(up, &status);
1528 check_modem_status(up);
1529 if (status & UART_LSR_THRE)
1532 spin_unlock_irqrestore(&up->port.lock, flags);
1536 * This is the serial driver's interrupt routine.
1538 * Arjan thinks the old way was overly complex, so it got simplified.
1539 * Alan disagrees, saying that need the complexity to handle the weird
1540 * nature of ISA shared interrupts. (This is a special exception.)
1542 * In order to handle ISA shared interrupts properly, we need to check
1543 * that all ports have been serviced, and therefore the ISA interrupt
1544 * line has been de-asserted.
1546 * This means we need to loop through all ports. checking that they
1547 * don't have an interrupt pending.
1549 static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1551 struct irq_info *i = dev_id;
1552 struct list_head *l, *end = NULL;
1553 int pass_counter = 0, handled = 0;
1555 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1557 spin_lock(&i->lock);
1561 struct uart_8250_port *up;
1564 up = list_entry(l, struct uart_8250_port, list);
1566 iir = serial_in(up, UART_IIR);
1567 if (!(iir & UART_IIR_NO_INT)) {
1568 serial8250_handle_port(up);
1573 } else if (up->port.iotype == UPIO_DWAPB &&
1574 (iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
1575 /* The DesignWare APB UART has an Busy Detect (0x07)
1576 * interrupt meaning an LCR write attempt occured while the
1577 * UART was busy. The interrupt must be cleared by reading
1578 * the UART status register (USR) and the LCR re-written. */
1579 unsigned int status;
1580 status = *(volatile u32 *)up->port.private_data;
1581 serial_out(up, UART_LCR, up->lcr);
1586 } else if (end == NULL)
1591 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1592 /* If we hit this, we're dead. */
1593 printk(KERN_ERR "serial8250: too much work for "
1599 spin_unlock(&i->lock);
1601 DEBUG_INTR("end.\n");
1603 return IRQ_RETVAL(handled);
1607 * To support ISA shared interrupts, we need to have one interrupt
1608 * handler that ensures that the IRQ line has been deasserted
1609 * before returning. Failing to do this will result in the IRQ
1610 * line being stuck active, and, since ISA irqs are edge triggered,
1611 * no more IRQs will be seen.
1613 static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1615 spin_lock_irq(&i->lock);
1617 if (!list_empty(i->head)) {
1618 if (i->head == &up->list)
1619 i->head = i->head->next;
1620 list_del(&up->list);
1622 BUG_ON(i->head != &up->list);
1625 spin_unlock_irq(&i->lock);
1626 /* List empty so throw away the hash node */
1627 if (i->head == NULL) {
1628 hlist_del(&i->node);
1633 static int serial_link_irq_chain(struct uart_8250_port *up)
1635 struct hlist_head *h;
1636 struct hlist_node *n;
1638 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1640 mutex_lock(&hash_mutex);
1642 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1644 hlist_for_each(n, h) {
1645 i = hlist_entry(n, struct irq_info, node);
1646 if (i->irq == up->port.irq)
1651 i = kzalloc(sizeof(struct irq_info), GFP_KERNEL);
1653 mutex_unlock(&hash_mutex);
1656 spin_lock_init(&i->lock);
1657 i->irq = up->port.irq;
1658 hlist_add_head(&i->node, h);
1660 mutex_unlock(&hash_mutex);
1662 spin_lock_irq(&i->lock);
1665 list_add(&up->list, i->head);
1666 spin_unlock_irq(&i->lock);
1670 INIT_LIST_HEAD(&up->list);
1671 i->head = &up->list;
1672 spin_unlock_irq(&i->lock);
1673 irq_flags |= up->port.irqflags;
1674 ret = request_irq(up->port.irq, serial8250_interrupt,
1675 irq_flags, "serial", i);
1677 serial_do_unlink(i, up);
1683 static void serial_unlink_irq_chain(struct uart_8250_port *up)
1686 struct hlist_node *n;
1687 struct hlist_head *h;
1689 mutex_lock(&hash_mutex);
1691 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1693 hlist_for_each(n, h) {
1694 i = hlist_entry(n, struct irq_info, node);
1695 if (i->irq == up->port.irq)
1700 BUG_ON(i->head == NULL);
1702 if (list_empty(i->head))
1703 free_irq(up->port.irq, i);
1705 serial_do_unlink(i, up);
1706 mutex_unlock(&hash_mutex);
1709 /* Base timer interval for polling */
1710 static inline int poll_timeout(int timeout)
1712 return timeout > 6 ? (timeout / 2 - 2) : 1;
1716 * This function is used to handle ports that do not have an
1717 * interrupt. This doesn't work very well for 16450's, but gives
1718 * barely passable results for a 16550A. (Although at the expense
1719 * of much CPU overhead).
1721 static void serial8250_timeout(unsigned long data)
1723 struct uart_8250_port *up = (struct uart_8250_port *)data;
1726 iir = serial_in(up, UART_IIR);
1727 if (!(iir & UART_IIR_NO_INT))
1728 serial8250_handle_port(up);
1729 mod_timer(&up->timer, jiffies + poll_timeout(up->port.timeout));
1732 static void serial8250_backup_timeout(unsigned long data)
1734 struct uart_8250_port *up = (struct uart_8250_port *)data;
1735 unsigned int iir, ier = 0, lsr;
1736 unsigned long flags;
1739 * Must disable interrupts or else we risk racing with the interrupt
1742 if (is_real_interrupt(up->port.irq)) {
1743 ier = serial_in(up, UART_IER);
1744 serial_out(up, UART_IER, 0);
1747 iir = serial_in(up, UART_IIR);
1750 * This should be a safe test for anyone who doesn't trust the
1751 * IIR bits on their UART, but it's specifically designed for
1752 * the "Diva" UART used on the management processor on many HP
1753 * ia64 and parisc boxes.
1755 spin_lock_irqsave(&up->port.lock, flags);
1756 lsr = serial_in(up, UART_LSR);
1757 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1758 spin_unlock_irqrestore(&up->port.lock, flags);
1759 if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
1760 (!uart_circ_empty(&up->port.state->xmit) || up->port.x_char) &&
1761 (lsr & UART_LSR_THRE)) {
1762 iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
1763 iir |= UART_IIR_THRI;
1766 if (!(iir & UART_IIR_NO_INT))
1767 serial8250_handle_port(up);
1769 if (is_real_interrupt(up->port.irq))
1770 serial_out(up, UART_IER, ier);
1772 /* Standard timer interval plus 0.2s to keep the port running */
1773 mod_timer(&up->timer,
1774 jiffies + poll_timeout(up->port.timeout) + HZ / 5);
1777 static unsigned int serial8250_tx_empty(struct uart_port *port)
1779 struct uart_8250_port *up = (struct uart_8250_port *)port;
1780 unsigned long flags;
1783 spin_lock_irqsave(&up->port.lock, flags);
1784 lsr = serial_in(up, UART_LSR);
1785 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1786 spin_unlock_irqrestore(&up->port.lock, flags);
1788 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1791 static unsigned int serial8250_get_mctrl(struct uart_port *port)
1793 struct uart_8250_port *up = (struct uart_8250_port *)port;
1794 unsigned int status;
1797 status = check_modem_status(up);
1800 if (status & UART_MSR_DCD)
1802 if (status & UART_MSR_RI)
1804 if (status & UART_MSR_DSR)
1806 if (status & UART_MSR_CTS)
1811 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1813 struct uart_8250_port *up = (struct uart_8250_port *)port;
1814 unsigned char mcr = 0;
1816 if (mctrl & TIOCM_RTS)
1817 mcr |= UART_MCR_RTS;
1818 if (mctrl & TIOCM_DTR)
1819 mcr |= UART_MCR_DTR;
1820 if (mctrl & TIOCM_OUT1)
1821 mcr |= UART_MCR_OUT1;
1822 if (mctrl & TIOCM_OUT2)
1823 mcr |= UART_MCR_OUT2;
1824 if (mctrl & TIOCM_LOOP)
1825 mcr |= UART_MCR_LOOP;
1827 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1829 serial_out(up, UART_MCR, mcr);
1832 static void serial8250_break_ctl(struct uart_port *port, int break_state)
1834 struct uart_8250_port *up = (struct uart_8250_port *)port;
1835 unsigned long flags;
1837 spin_lock_irqsave(&up->port.lock, flags);
1838 if (break_state == -1)
1839 up->lcr |= UART_LCR_SBC;
1841 up->lcr &= ~UART_LCR_SBC;
1842 serial_out(up, UART_LCR, up->lcr);
1843 spin_unlock_irqrestore(&up->port.lock, flags);
1847 * Wait for transmitter & holding register to empty
1849 static void wait_for_xmitr(struct uart_8250_port *up, int bits)
1851 unsigned int status, tmout = 10000;
1853 /* Wait up to 10ms for the character(s) to be sent. */
1855 status = serial_in(up, UART_LSR);
1857 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
1862 } while ((status & bits) != bits);
1864 /* Wait up to 1s for flow control if necessary */
1865 if (up->port.flags & UPF_CONS_FLOW) {
1867 for (tmout = 1000000; tmout; tmout--) {
1868 unsigned int msr = serial_in(up, UART_MSR);
1869 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1870 if (msr & UART_MSR_CTS)
1873 touch_nmi_watchdog();
1878 #ifdef CONFIG_CONSOLE_POLL
1880 * Console polling routines for writing and reading from the uart while
1881 * in an interrupt or debug context.
1884 static int serial8250_get_poll_char(struct uart_port *port)
1886 struct uart_8250_port *up = (struct uart_8250_port *)port;
1887 unsigned char lsr = serial_inp(up, UART_LSR);
1889 if (!(lsr & UART_LSR_DR))
1890 return NO_POLL_CHAR;
1892 return serial_inp(up, UART_RX);
1896 static void serial8250_put_poll_char(struct uart_port *port,
1900 struct uart_8250_port *up = (struct uart_8250_port *)port;
1903 * First save the IER then disable the interrupts
1905 ier = serial_in(up, UART_IER);
1906 if (up->capabilities & UART_CAP_UUE)
1907 serial_out(up, UART_IER, UART_IER_UUE);
1909 serial_out(up, UART_IER, 0);
1911 wait_for_xmitr(up, BOTH_EMPTY);
1913 * Send the character out.
1914 * If a LF, also do CR...
1916 serial_out(up, UART_TX, c);
1918 wait_for_xmitr(up, BOTH_EMPTY);
1919 serial_out(up, UART_TX, 13);
1923 * Finally, wait for transmitter to become empty
1924 * and restore the IER
1926 wait_for_xmitr(up, BOTH_EMPTY);
1927 serial_out(up, UART_IER, ier);
1930 #endif /* CONFIG_CONSOLE_POLL */
1932 static int serial8250_startup(struct uart_port *port)
1934 struct uart_8250_port *up = (struct uart_8250_port *)port;
1935 unsigned long flags;
1936 unsigned char lsr, iir;
1939 up->capabilities = uart_config[up->port.type].flags;
1942 if (up->port.iotype != up->cur_iotype)
1943 set_io_from_upio(port);
1945 if (up->port.type == PORT_16C950) {
1946 /* Wake up and initialize UART */
1948 serial_outp(up, UART_LCR, 0xBF);
1949 serial_outp(up, UART_EFR, UART_EFR_ECB);
1950 serial_outp(up, UART_IER, 0);
1951 serial_outp(up, UART_LCR, 0);
1952 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
1953 serial_outp(up, UART_LCR, 0xBF);
1954 serial_outp(up, UART_EFR, UART_EFR_ECB);
1955 serial_outp(up, UART_LCR, 0);
1958 #ifdef CONFIG_SERIAL_8250_RSA
1960 * If this is an RSA port, see if we can kick it up to the
1961 * higher speed clock.
1967 * Clear the FIFO buffers and disable them.
1968 * (they will be reenabled in set_termios())
1970 serial8250_clear_fifos(up);
1973 * Clear the interrupt registers.
1975 (void) serial_inp(up, UART_LSR);
1976 (void) serial_inp(up, UART_RX);
1977 (void) serial_inp(up, UART_IIR);
1978 (void) serial_inp(up, UART_MSR);
1981 * At this point, there's no way the LSR could still be 0xff;
1982 * if it is, then bail out, because there's likely no UART
1985 if (!(up->port.flags & UPF_BUGGY_UART) &&
1986 (serial_inp(up, UART_LSR) == 0xff)) {
1987 printk(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
1988 serial_index(&up->port));
1993 * For a XR16C850, we need to set the trigger levels
1995 if (up->port.type == PORT_16850) {
1998 serial_outp(up, UART_LCR, 0xbf);
2000 fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2001 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2002 serial_outp(up, UART_TRG, UART_TRG_96);
2003 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2004 serial_outp(up, UART_TRG, UART_TRG_96);
2006 serial_outp(up, UART_LCR, 0);
2009 if (is_real_interrupt(up->port.irq)) {
2012 * Test for UARTs that do not reassert THRE when the
2013 * transmitter is idle and the interrupt has already
2014 * been cleared. Real 16550s should always reassert
2015 * this interrupt whenever the transmitter is idle and
2016 * the interrupt is enabled. Delays are necessary to
2017 * allow register changes to become visible.
2019 spin_lock_irqsave(&up->port.lock, flags);
2020 if (up->port.irqflags & IRQF_SHARED)
2021 disable_irq_nosync(up->port.irq);
2023 wait_for_xmitr(up, UART_LSR_THRE);
2024 serial_out_sync(up, UART_IER, UART_IER_THRI);
2025 udelay(1); /* allow THRE to set */
2026 iir1 = serial_in(up, UART_IIR);
2027 serial_out(up, UART_IER, 0);
2028 serial_out_sync(up, UART_IER, UART_IER_THRI);
2029 udelay(1); /* allow a working UART time to re-assert THRE */
2030 iir = serial_in(up, UART_IIR);
2031 serial_out(up, UART_IER, 0);
2033 if (up->port.irqflags & IRQF_SHARED)
2034 enable_irq(up->port.irq);
2035 spin_unlock_irqrestore(&up->port.lock, flags);
2038 * If the interrupt is not reasserted, setup a timer to
2039 * kick the UART on a regular basis.
2041 if (!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) {
2042 up->bugs |= UART_BUG_THRE;
2043 pr_debug("ttyS%d - using backup timer\n",
2044 serial_index(port));
2049 * The above check will only give an accurate result the first time
2050 * the port is opened so this value needs to be preserved.
2052 if (up->bugs & UART_BUG_THRE) {
2053 up->timer.function = serial8250_backup_timeout;
2054 up->timer.data = (unsigned long)up;
2055 mod_timer(&up->timer, jiffies +
2056 poll_timeout(up->port.timeout) + HZ / 5);
2060 * If the "interrupt" for this port doesn't correspond with any
2061 * hardware interrupt, we use a timer-based system. The original
2062 * driver used to do this with IRQ0.
2064 if (!is_real_interrupt(up->port.irq)) {
2065 up->timer.data = (unsigned long)up;
2066 mod_timer(&up->timer, jiffies + poll_timeout(up->port.timeout));
2068 retval = serial_link_irq_chain(up);
2074 * Now, initialize the UART
2076 serial_outp(up, UART_LCR, UART_LCR_WLEN8);
2078 spin_lock_irqsave(&up->port.lock, flags);
2079 if (up->port.flags & UPF_FOURPORT) {
2080 if (!is_real_interrupt(up->port.irq))
2081 up->port.mctrl |= TIOCM_OUT1;
2084 * Most PC uarts need OUT2 raised to enable interrupts.
2086 if (is_real_interrupt(up->port.irq))
2087 up->port.mctrl |= TIOCM_OUT2;
2089 serial8250_set_mctrl(&up->port, up->port.mctrl);
2091 /* Serial over Lan (SoL) hack:
2092 Intel 8257x Gigabit ethernet chips have a
2093 16550 emulation, to be used for Serial Over Lan.
2094 Those chips take a longer time than a normal
2095 serial device to signalize that a transmission
2096 data was queued. Due to that, the above test generally
2097 fails. One solution would be to delay the reading of
2098 iir. However, this is not reliable, since the timeout
2099 is variable. So, let's just don't test if we receive
2100 TX irq. This way, we'll never enable UART_BUG_TXEN.
2102 if (skip_txen_test || up->port.flags & UPF_NO_TXEN_TEST)
2103 goto dont_test_tx_en;
2106 * Do a quick test to see if we receive an
2107 * interrupt when we enable the TX irq.
2109 serial_outp(up, UART_IER, UART_IER_THRI);
2110 lsr = serial_in(up, UART_LSR);
2111 iir = serial_in(up, UART_IIR);
2112 serial_outp(up, UART_IER, 0);
2114 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2115 if (!(up->bugs & UART_BUG_TXEN)) {
2116 up->bugs |= UART_BUG_TXEN;
2117 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
2118 serial_index(port));
2121 up->bugs &= ~UART_BUG_TXEN;
2125 spin_unlock_irqrestore(&up->port.lock, flags);
2128 * Clear the interrupt registers again for luck, and clear the
2129 * saved flags to avoid getting false values from polling
2130 * routines or the previous session.
2132 serial_inp(up, UART_LSR);
2133 serial_inp(up, UART_RX);
2134 serial_inp(up, UART_IIR);
2135 serial_inp(up, UART_MSR);
2136 up->lsr_saved_flags = 0;
2137 up->msr_saved_flags = 0;
2140 * Finally, enable interrupts. Note: Modem status interrupts
2141 * are set via set_termios(), which will be occurring imminently
2142 * anyway, so we don't enable them here.
2144 up->ier = UART_IER_RLSI | UART_IER_RDI;
2145 serial_outp(up, UART_IER, up->ier);
2147 if (up->port.flags & UPF_FOURPORT) {
2150 * Enable interrupts on the AST Fourport board
2152 icp = (up->port.iobase & 0xfe0) | 0x01f;
2160 static void serial8250_shutdown(struct uart_port *port)
2162 struct uart_8250_port *up = (struct uart_8250_port *)port;
2163 unsigned long flags;
2166 * Disable interrupts from this port
2169 serial_outp(up, UART_IER, 0);
2171 spin_lock_irqsave(&up->port.lock, flags);
2172 if (up->port.flags & UPF_FOURPORT) {
2173 /* reset interrupts on the AST Fourport board */
2174 inb((up->port.iobase & 0xfe0) | 0x1f);
2175 up->port.mctrl |= TIOCM_OUT1;
2177 up->port.mctrl &= ~TIOCM_OUT2;
2179 serial8250_set_mctrl(&up->port, up->port.mctrl);
2180 spin_unlock_irqrestore(&up->port.lock, flags);
2183 * Disable break condition and FIFOs
2185 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
2186 serial8250_clear_fifos(up);
2188 #ifdef CONFIG_SERIAL_8250_RSA
2190 * Reset the RSA board back to 115kbps compat mode.
2196 * Read data port to reset things, and then unlink from
2199 (void) serial_in(up, UART_RX);
2201 del_timer_sync(&up->timer);
2202 up->timer.function = serial8250_timeout;
2203 if (is_real_interrupt(up->port.irq))
2204 serial_unlink_irq_chain(up);
2207 static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
2212 * Handle magic divisors for baud rates above baud_base on
2213 * SMSC SuperIO chips.
2215 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2216 baud == (port->uartclk/4))
2218 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2219 baud == (port->uartclk/8))
2222 quot = uart_get_divisor(port, baud);
2228 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2229 struct ktermios *old)
2231 struct uart_8250_port *up = (struct uart_8250_port *)port;
2232 unsigned char cval, fcr = 0;
2233 unsigned long flags;
2234 unsigned int baud, quot;
2236 switch (termios->c_cflag & CSIZE) {
2238 cval = UART_LCR_WLEN5;
2241 cval = UART_LCR_WLEN6;
2244 cval = UART_LCR_WLEN7;
2248 cval = UART_LCR_WLEN8;
2252 if (termios->c_cflag & CSTOPB)
2253 cval |= UART_LCR_STOP;
2254 if (termios->c_cflag & PARENB)
2255 cval |= UART_LCR_PARITY;
2256 if (!(termios->c_cflag & PARODD))
2257 cval |= UART_LCR_EPAR;
2259 if (termios->c_cflag & CMSPAR)
2260 cval |= UART_LCR_SPAR;
2264 * Ask the core to calculate the divisor for us.
2266 baud = uart_get_baud_rate(port, termios, old,
2267 port->uartclk / 16 / 0xffff,
2268 port->uartclk / 16);
2269 quot = serial8250_get_divisor(port, baud);
2272 * Oxford Semi 952 rev B workaround
2274 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2277 if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) {
2279 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
2281 fcr = uart_config[up->port.type].fcr;
2285 * MCR-based auto flow control. When AFE is enabled, RTS will be
2286 * deasserted when the receive FIFO contains more characters than
2287 * the trigger, or the MCR RTS bit is cleared. In the case where
2288 * the remote UART is not using CTS auto flow control, we must
2289 * have sufficient FIFO entries for the latency of the remote
2290 * UART to respond. IOW, at least 32 bytes of FIFO.
2292 if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {
2293 up->mcr &= ~UART_MCR_AFE;
2294 if (termios->c_cflag & CRTSCTS)
2295 up->mcr |= UART_MCR_AFE;
2299 * Ok, we're now changing the port state. Do it with
2300 * interrupts disabled.
2302 spin_lock_irqsave(&up->port.lock, flags);
2305 * Update the per-port timeout.
2307 uart_update_timeout(port, termios->c_cflag, baud);
2309 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2310 if (termios->c_iflag & INPCK)
2311 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2312 if (termios->c_iflag & (BRKINT | PARMRK))
2313 up->port.read_status_mask |= UART_LSR_BI;
2316 * Characteres to ignore
2318 up->port.ignore_status_mask = 0;
2319 if (termios->c_iflag & IGNPAR)
2320 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2321 if (termios->c_iflag & IGNBRK) {
2322 up->port.ignore_status_mask |= UART_LSR_BI;
2324 * If we're ignoring parity and break indicators,
2325 * ignore overruns too (for real raw support).
2327 if (termios->c_iflag & IGNPAR)
2328 up->port.ignore_status_mask |= UART_LSR_OE;
2332 * ignore all characters if CREAD is not set
2334 if ((termios->c_cflag & CREAD) == 0)
2335 up->port.ignore_status_mask |= UART_LSR_DR;
2338 * CTS flow control flag and modem status interrupts
2340 up->ier &= ~UART_IER_MSI;
2341 if (!(up->bugs & UART_BUG_NOMSR) &&
2342 UART_ENABLE_MS(&up->port, termios->c_cflag))
2343 up->ier |= UART_IER_MSI;
2344 if (up->capabilities & UART_CAP_UUE)
2345 up->ier |= UART_IER_UUE | UART_IER_RTOIE;
2347 serial_out(up, UART_IER, up->ier);
2349 if (up->capabilities & UART_CAP_EFR) {
2350 unsigned char efr = 0;
2352 * TI16C752/Startech hardware flow control. FIXME:
2353 * - TI16C752 requires control thresholds to be set.
2354 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2356 if (termios->c_cflag & CRTSCTS)
2357 efr |= UART_EFR_CTS;
2359 serial_outp(up, UART_LCR, 0xBF);
2360 serial_outp(up, UART_EFR, efr);
2363 #ifdef CONFIG_ARCH_OMAP
2364 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2365 if (cpu_is_omap1510() && is_omap_port(up)) {
2366 if (baud == 115200) {
2368 serial_out(up, UART_OMAP_OSC_12M_SEL, 1);
2370 serial_out(up, UART_OMAP_OSC_12M_SEL, 0);
2374 if (up->capabilities & UART_NATSEMI) {
2375 /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
2376 serial_outp(up, UART_LCR, 0xe0);
2378 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
2381 serial_dl_write(up, quot);
2384 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2385 * is written without DLAB set, this mode will be disabled.
2387 if (up->port.type == PORT_16750)
2388 serial_outp(up, UART_FCR, fcr);
2390 serial_outp(up, UART_LCR, cval); /* reset DLAB */
2391 up->lcr = cval; /* Save LCR */
2392 if (up->port.type != PORT_16750) {
2393 if (fcr & UART_FCR_ENABLE_FIFO) {
2394 /* emulated UARTs (Lucent Venus 167x) need two steps */
2395 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
2397 serial_outp(up, UART_FCR, fcr); /* set fcr */
2399 serial8250_set_mctrl(&up->port, up->port.mctrl);
2400 spin_unlock_irqrestore(&up->port.lock, flags);
2401 /* Don't rewrite B0 */
2402 if (tty_termios_baud_rate(termios))
2403 tty_termios_encode_baud_rate(termios, baud, baud);
2407 serial8250_set_ldisc(struct uart_port *port)
2409 int line = port->line;
2411 if (line >= port->state->port.tty->driver->num)
2414 if (port->state->port.tty->ldisc->ops->num == N_PPS) {
2415 port->flags |= UPF_HARDPPS_CD;
2416 serial8250_enable_ms(port);
2418 port->flags &= ~UPF_HARDPPS_CD;
2422 serial8250_pm(struct uart_port *port, unsigned int state,
2423 unsigned int oldstate)
2425 struct uart_8250_port *p = (struct uart_8250_port *)port;
2427 serial8250_set_sleep(p, state != 0);
2430 p->pm(port, state, oldstate);
2433 static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2435 if (pt->port.iotype == UPIO_AU)
2437 #ifdef CONFIG_ARCH_OMAP
2438 if (is_omap_port(pt))
2439 return 0x16 << pt->port.regshift;
2441 return 8 << pt->port.regshift;
2445 * Resource handling.
2447 static int serial8250_request_std_resource(struct uart_8250_port *up)
2449 unsigned int size = serial8250_port_size(up);
2452 switch (up->port.iotype) {
2458 if (!up->port.mapbase)
2461 if (!request_mem_region(up->port.mapbase, size, "serial")) {
2466 if (up->port.flags & UPF_IOREMAP) {
2467 up->port.membase = ioremap_nocache(up->port.mapbase,
2469 if (!up->port.membase) {
2470 release_mem_region(up->port.mapbase, size);
2478 if (!request_region(up->port.iobase, size, "serial"))
2485 static void serial8250_release_std_resource(struct uart_8250_port *up)
2487 unsigned int size = serial8250_port_size(up);
2489 switch (up->port.iotype) {
2495 if (!up->port.mapbase)
2498 if (up->port.flags & UPF_IOREMAP) {
2499 iounmap(up->port.membase);
2500 up->port.membase = NULL;
2503 release_mem_region(up->port.mapbase, size);
2508 release_region(up->port.iobase, size);
2513 static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2515 unsigned long start = UART_RSA_BASE << up->port.regshift;
2516 unsigned int size = 8 << up->port.regshift;
2519 switch (up->port.iotype) {
2522 start += up->port.iobase;
2523 if (request_region(start, size, "serial-rsa"))
2533 static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2535 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2536 unsigned int size = 8 << up->port.regshift;
2538 switch (up->port.iotype) {
2541 release_region(up->port.iobase + offset, size);
2546 static void serial8250_release_port(struct uart_port *port)
2548 struct uart_8250_port *up = (struct uart_8250_port *)port;
2550 serial8250_release_std_resource(up);
2551 if (up->port.type == PORT_RSA)
2552 serial8250_release_rsa_resource(up);
2555 static int serial8250_request_port(struct uart_port *port)
2557 struct uart_8250_port *up = (struct uart_8250_port *)port;
2560 ret = serial8250_request_std_resource(up);
2561 if (ret == 0 && up->port.type == PORT_RSA) {
2562 ret = serial8250_request_rsa_resource(up);
2564 serial8250_release_std_resource(up);
2570 static void serial8250_config_port(struct uart_port *port, int flags)
2572 struct uart_8250_port *up = (struct uart_8250_port *)port;
2573 int probeflags = PROBE_ANY;
2577 * Find the region that we can probe for. This in turn
2578 * tells us whether we can probe for the type of port.
2580 ret = serial8250_request_std_resource(up);
2584 ret = serial8250_request_rsa_resource(up);
2586 probeflags &= ~PROBE_RSA;
2588 if (up->port.iotype != up->cur_iotype)
2589 set_io_from_upio(port);
2591 if (flags & UART_CONFIG_TYPE)
2592 autoconfig(up, probeflags);
2594 /* if access method is AU, it is a 16550 with a quirk */
2595 if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU)
2596 up->bugs |= UART_BUG_NOMSR;
2598 if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2601 if (up->port.type != PORT_RSA && probeflags & PROBE_RSA)
2602 serial8250_release_rsa_resource(up);
2603 if (up->port.type == PORT_UNKNOWN)
2604 serial8250_release_std_resource(up);
2608 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2610 if (ser->irq >= nr_irqs || ser->irq < 0 ||
2611 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2612 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2613 ser->type == PORT_STARTECH)
2619 serial8250_type(struct uart_port *port)
2621 int type = port->type;
2623 if (type >= ARRAY_SIZE(uart_config))
2625 return uart_config[type].name;
2628 static struct uart_ops serial8250_pops = {
2629 .tx_empty = serial8250_tx_empty,
2630 .set_mctrl = serial8250_set_mctrl,
2631 .get_mctrl = serial8250_get_mctrl,
2632 .stop_tx = serial8250_stop_tx,
2633 .start_tx = serial8250_start_tx,
2634 .stop_rx = serial8250_stop_rx,
2635 .enable_ms = serial8250_enable_ms,
2636 .break_ctl = serial8250_break_ctl,
2637 .startup = serial8250_startup,
2638 .shutdown = serial8250_shutdown,
2639 .set_termios = serial8250_set_termios,
2640 .set_ldisc = serial8250_set_ldisc,
2641 .pm = serial8250_pm,
2642 .type = serial8250_type,
2643 .release_port = serial8250_release_port,
2644 .request_port = serial8250_request_port,
2645 .config_port = serial8250_config_port,
2646 .verify_port = serial8250_verify_port,
2647 #ifdef CONFIG_CONSOLE_POLL
2648 .poll_get_char = serial8250_get_poll_char,
2649 .poll_put_char = serial8250_put_poll_char,
2653 static struct uart_8250_port serial8250_ports[UART_NR];
2655 static void __init serial8250_isa_init_ports(void)
2657 struct uart_8250_port *up;
2658 static int first = 1;
2665 for (i = 0; i < nr_uarts; i++) {
2666 struct uart_8250_port *up = &serial8250_ports[i];
2669 spin_lock_init(&up->port.lock);
2671 init_timer(&up->timer);
2672 up->timer.function = serial8250_timeout;
2675 * ALPHA_KLUDGE_MCR needs to be killed.
2677 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2678 up->mcr_force = ALPHA_KLUDGE_MCR;
2680 up->port.ops = &serial8250_pops;
2684 irqflag = IRQF_SHARED;
2686 for (i = 0, up = serial8250_ports;
2687 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
2689 up->port.iobase = old_serial_port[i].port;
2690 up->port.irq = irq_canonicalize(old_serial_port[i].irq);
2691 up->port.irqflags = old_serial_port[i].irqflags;
2692 up->port.uartclk = old_serial_port[i].baud_base * 16;
2693 up->port.flags = old_serial_port[i].flags;
2694 up->port.hub6 = old_serial_port[i].hub6;
2695 up->port.membase = old_serial_port[i].iomem_base;
2696 up->port.iotype = old_serial_port[i].io_type;
2697 up->port.regshift = old_serial_port[i].iomem_reg_shift;
2698 set_io_from_upio(&up->port);
2699 up->port.irqflags |= irqflag;
2704 serial8250_init_fixed_type_port(struct uart_8250_port *up, unsigned int type)
2706 up->port.type = type;
2707 up->port.fifosize = uart_config[type].fifo_size;
2708 up->capabilities = uart_config[type].flags;
2709 up->tx_loadsz = uart_config[type].tx_loadsz;
2713 serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2717 for (i = 0; i < nr_uarts; i++) {
2718 struct uart_8250_port *up = &serial8250_ports[i];
2719 up->cur_iotype = 0xFF;
2722 serial8250_isa_init_ports();
2724 for (i = 0; i < nr_uarts; i++) {
2725 struct uart_8250_port *up = &serial8250_ports[i];
2729 if (up->port.flags & UPF_FIXED_TYPE)
2730 serial8250_init_fixed_type_port(up, up->port.type);
2732 uart_add_one_port(drv, &up->port);
2736 #ifdef CONFIG_SERIAL_8250_CONSOLE
2738 static void serial8250_console_putchar(struct uart_port *port, int ch)
2740 struct uart_8250_port *up = (struct uart_8250_port *)port;
2742 wait_for_xmitr(up, UART_LSR_THRE);
2743 serial_out(up, UART_TX, ch);
2747 * Print a string to the serial port trying not to disturb
2748 * any possible real use of the port...
2750 * The console_lock must be held when we get here.
2753 serial8250_console_write(struct console *co, const char *s, unsigned int count)
2755 struct uart_8250_port *up = &serial8250_ports[co->index];
2756 unsigned long flags;
2760 touch_nmi_watchdog();
2762 local_irq_save(flags);
2763 if (up->port.sysrq) {
2764 /* serial8250_handle_port() already took the lock */
2766 } else if (oops_in_progress) {
2767 locked = spin_trylock(&up->port.lock);
2769 spin_lock(&up->port.lock);
2772 * First save the IER then disable the interrupts
2774 ier = serial_in(up, UART_IER);
2776 if (up->capabilities & UART_CAP_UUE)
2777 serial_out(up, UART_IER, UART_IER_UUE);
2779 serial_out(up, UART_IER, 0);
2781 uart_console_write(&up->port, s, count, serial8250_console_putchar);
2784 * Finally, wait for transmitter to become empty
2785 * and restore the IER
2787 wait_for_xmitr(up, BOTH_EMPTY);
2788 serial_out(up, UART_IER, ier);
2791 * The receive handling will happen properly because the
2792 * receive ready bit will still be set; it is not cleared
2793 * on read. However, modem control will not, we must
2794 * call it if we have saved something in the saved flags
2795 * while processing with interrupts off.
2797 if (up->msr_saved_flags)
2798 check_modem_status(up);
2801 spin_unlock(&up->port.lock);
2802 local_irq_restore(flags);
2805 static int __init serial8250_console_setup(struct console *co, char *options)
2807 struct uart_port *port;
2814 * Check whether an invalid uart number has been specified, and
2815 * if so, search for the first available port that does have
2818 if (co->index >= nr_uarts)
2820 port = &serial8250_ports[co->index].port;
2821 if (!port->iobase && !port->membase)
2825 uart_parse_options(options, &baud, &parity, &bits, &flow);
2827 return uart_set_options(port, co, baud, parity, bits, flow);
2830 static int serial8250_console_early_setup(void)
2832 return serial8250_find_port_for_earlycon();
2835 static struct console serial8250_console = {
2837 .write = serial8250_console_write,
2838 .device = uart_console_device,
2839 .setup = serial8250_console_setup,
2840 .early_setup = serial8250_console_early_setup,
2841 .flags = CON_PRINTBUFFER,
2843 .data = &serial8250_reg,
2846 static int __init serial8250_console_init(void)
2848 if (nr_uarts > UART_NR)
2851 serial8250_isa_init_ports();
2852 register_console(&serial8250_console);
2855 console_initcall(serial8250_console_init);
2857 int serial8250_find_port(struct uart_port *p)
2860 struct uart_port *port;
2862 for (line = 0; line < nr_uarts; line++) {
2863 port = &serial8250_ports[line].port;
2864 if (uart_match_port(p, port))
2870 #define SERIAL8250_CONSOLE &serial8250_console
2872 #define SERIAL8250_CONSOLE NULL
2875 static struct uart_driver serial8250_reg = {
2876 .owner = THIS_MODULE,
2877 .driver_name = "serial",
2881 .cons = SERIAL8250_CONSOLE,
2885 * early_serial_setup - early registration for 8250 ports
2887 * Setup an 8250 port structure prior to console initialisation. Use
2888 * after console initialisation will cause undefined behaviour.
2890 int __init early_serial_setup(struct uart_port *port)
2892 struct uart_port *p;
2894 if (port->line >= ARRAY_SIZE(serial8250_ports))
2897 serial8250_isa_init_ports();
2898 p = &serial8250_ports[port->line].port;
2899 p->iobase = port->iobase;
2900 p->membase = port->membase;
2902 p->irqflags = port->irqflags;
2903 p->uartclk = port->uartclk;
2904 p->fifosize = port->fifosize;
2905 p->regshift = port->regshift;
2906 p->iotype = port->iotype;
2907 p->flags = port->flags;
2908 p->mapbase = port->mapbase;
2909 p->private_data = port->private_data;
2910 p->type = port->type;
2911 p->line = port->line;
2913 set_io_from_upio(p);
2914 if (port->serial_in)
2915 p->serial_in = port->serial_in;
2916 if (port->serial_out)
2917 p->serial_out = port->serial_out;
2923 * serial8250_suspend_port - suspend one serial port
2924 * @line: serial line number
2926 * Suspend one serial port.
2928 void serial8250_suspend_port(int line)
2930 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
2934 * serial8250_resume_port - resume one serial port
2935 * @line: serial line number
2937 * Resume one serial port.
2939 void serial8250_resume_port(int line)
2941 struct uart_8250_port *up = &serial8250_ports[line];
2943 if (up->capabilities & UART_NATSEMI) {
2946 /* Ensure it's still in high speed mode */
2947 serial_outp(up, UART_LCR, 0xE0);
2949 tmp = serial_in(up, 0x04); /* EXCR2 */
2950 tmp &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
2951 tmp |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
2952 serial_outp(up, 0x04, tmp);
2954 serial_outp(up, UART_LCR, 0);
2956 uart_resume_port(&serial8250_reg, &up->port);
2960 * Register a set of serial devices attached to a platform device. The
2961 * list is terminated with a zero flags entry, which means we expect
2962 * all entries to have at least UPF_BOOT_AUTOCONF set.
2964 static int __devinit serial8250_probe(struct platform_device *dev)
2966 struct plat_serial8250_port *p = dev->dev.platform_data;
2967 struct uart_port port;
2968 int ret, i, irqflag = 0;
2970 memset(&port, 0, sizeof(struct uart_port));
2973 irqflag = IRQF_SHARED;
2975 for (i = 0; p && p->flags != 0; p++, i++) {
2976 port.iobase = p->iobase;
2977 port.membase = p->membase;
2979 port.irqflags = p->irqflags;
2980 port.uartclk = p->uartclk;
2981 port.regshift = p->regshift;
2982 port.iotype = p->iotype;
2983 port.flags = p->flags;
2984 port.mapbase = p->mapbase;
2985 port.hub6 = p->hub6;
2986 port.private_data = p->private_data;
2987 port.type = p->type;
2988 port.serial_in = p->serial_in;
2989 port.serial_out = p->serial_out;
2990 port.dev = &dev->dev;
2991 port.irqflags |= irqflag;
2992 ret = serial8250_register_port(&port);
2994 dev_err(&dev->dev, "unable to register port at index %d "
2995 "(IO%lx MEM%llx IRQ%d): %d\n", i,
2996 p->iobase, (unsigned long long)p->mapbase,
3004 * Remove serial ports registered against a platform device.
3006 static int __devexit serial8250_remove(struct platform_device *dev)
3010 for (i = 0; i < nr_uarts; i++) {
3011 struct uart_8250_port *up = &serial8250_ports[i];
3013 if (up->port.dev == &dev->dev)
3014 serial8250_unregister_port(i);
3019 static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
3023 for (i = 0; i < UART_NR; i++) {
3024 struct uart_8250_port *up = &serial8250_ports[i];
3026 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3027 uart_suspend_port(&serial8250_reg, &up->port);
3033 static int serial8250_resume(struct platform_device *dev)
3037 for (i = 0; i < UART_NR; i++) {
3038 struct uart_8250_port *up = &serial8250_ports[i];
3040 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3041 serial8250_resume_port(i);
3047 static struct platform_driver serial8250_isa_driver = {
3048 .probe = serial8250_probe,
3049 .remove = __devexit_p(serial8250_remove),
3050 .suspend = serial8250_suspend,
3051 .resume = serial8250_resume,
3053 .name = "serial8250",
3054 .owner = THIS_MODULE,
3059 * This "device" covers _all_ ISA 8250-compatible serial devices listed
3060 * in the table in include/asm/serial.h
3062 static struct platform_device *serial8250_isa_devs;
3065 * serial8250_register_port and serial8250_unregister_port allows for
3066 * 16x50 serial ports to be configured at run-time, to support PCMCIA
3067 * modems and PCI multiport cards.
3069 static DEFINE_MUTEX(serial_mutex);
3071 static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
3076 * First, find a port entry which matches.
3078 for (i = 0; i < nr_uarts; i++)
3079 if (uart_match_port(&serial8250_ports[i].port, port))
3080 return &serial8250_ports[i];
3083 * We didn't find a matching entry, so look for the first
3084 * free entry. We look for one which hasn't been previously
3085 * used (indicated by zero iobase).
3087 for (i = 0; i < nr_uarts; i++)
3088 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
3089 serial8250_ports[i].port.iobase == 0)
3090 return &serial8250_ports[i];
3093 * That also failed. Last resort is to find any entry which
3094 * doesn't have a real port associated with it.
3096 for (i = 0; i < nr_uarts; i++)
3097 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
3098 return &serial8250_ports[i];
3104 * serial8250_register_port - register a serial port
3105 * @port: serial port template
3107 * Configure the serial port specified by the request. If the
3108 * port exists and is in use, it is hung up and unregistered
3111 * The port is then probed and if necessary the IRQ is autodetected
3112 * If this fails an error is returned.
3114 * On success the port is ready to use and the line number is returned.
3116 int serial8250_register_port(struct uart_port *port)
3118 struct uart_8250_port *uart;
3121 if (port->uartclk == 0)
3124 mutex_lock(&serial_mutex);
3126 uart = serial8250_find_match_or_unused(port);
3128 uart_remove_one_port(&serial8250_reg, &uart->port);
3130 uart->port.iobase = port->iobase;
3131 uart->port.membase = port->membase;
3132 uart->port.irq = port->irq;
3133 uart->port.irqflags = port->irqflags;
3134 uart->port.uartclk = port->uartclk;
3135 uart->port.fifosize = port->fifosize;
3136 uart->port.regshift = port->regshift;
3137 uart->port.iotype = port->iotype;
3138 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
3139 uart->port.mapbase = port->mapbase;
3140 uart->port.private_data = port->private_data;
3142 uart->port.dev = port->dev;
3144 if (port->flags & UPF_FIXED_TYPE)
3145 serial8250_init_fixed_type_port(uart, port->type);
3147 set_io_from_upio(&uart->port);
3148 /* Possibly override default I/O functions. */
3149 if (port->serial_in)
3150 uart->port.serial_in = port->serial_in;
3151 if (port->serial_out)
3152 uart->port.serial_out = port->serial_out;
3154 ret = uart_add_one_port(&serial8250_reg, &uart->port);
3156 ret = uart->port.line;
3158 mutex_unlock(&serial_mutex);
3162 EXPORT_SYMBOL(serial8250_register_port);
3165 * serial8250_unregister_port - remove a 16x50 serial port at runtime
3166 * @line: serial line number
3168 * Remove one serial port. This may not be called from interrupt
3169 * context. We hand the port back to the our control.
3171 void serial8250_unregister_port(int line)
3173 struct uart_8250_port *uart = &serial8250_ports[line];
3175 mutex_lock(&serial_mutex);
3176 uart_remove_one_port(&serial8250_reg, &uart->port);
3177 if (serial8250_isa_devs) {
3178 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
3179 uart->port.type = PORT_UNKNOWN;
3180 uart->port.dev = &serial8250_isa_devs->dev;
3181 uart_add_one_port(&serial8250_reg, &uart->port);
3183 uart->port.dev = NULL;
3185 mutex_unlock(&serial_mutex);
3187 EXPORT_SYMBOL(serial8250_unregister_port);
3189 static int __init serial8250_init(void)
3193 if (nr_uarts > UART_NR)
3196 printk(KERN_INFO "Serial: 8250/16550 driver, "
3197 "%d ports, IRQ sharing %sabled\n", nr_uarts,
3198 share_irqs ? "en" : "dis");
3201 ret = sunserial_register_minors(&serial8250_reg, UART_NR);
3203 serial8250_reg.nr = UART_NR;
3204 ret = uart_register_driver(&serial8250_reg);
3209 serial8250_isa_devs = platform_device_alloc("serial8250",
3210 PLAT8250_DEV_LEGACY);
3211 if (!serial8250_isa_devs) {
3213 goto unreg_uart_drv;
3216 ret = platform_device_add(serial8250_isa_devs);
3220 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
3222 ret = platform_driver_register(&serial8250_isa_driver);
3226 platform_device_del(serial8250_isa_devs);
3228 platform_device_put(serial8250_isa_devs);
3231 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3233 uart_unregister_driver(&serial8250_reg);
3239 static void __exit serial8250_exit(void)
3241 struct platform_device *isa_dev = serial8250_isa_devs;
3244 * This tells serial8250_unregister_port() not to re-register
3245 * the ports (thereby making serial8250_isa_driver permanently
3248 serial8250_isa_devs = NULL;
3250 platform_driver_unregister(&serial8250_isa_driver);
3251 platform_device_unregister(isa_dev);
3254 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3256 uart_unregister_driver(&serial8250_reg);
3260 module_init(serial8250_init);
3261 module_exit(serial8250_exit);
3263 EXPORT_SYMBOL(serial8250_suspend_port);
3264 EXPORT_SYMBOL(serial8250_resume_port);
3266 MODULE_LICENSE("GPL");
3267 MODULE_DESCRIPTION("Generic 8250/16x50 serial driver");
3269 module_param(share_irqs, uint, 0644);
3270 MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
3273 module_param(nr_uarts, uint, 0644);
3274 MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
3276 module_param(skip_txen_test, uint, 0644);
3277 MODULE_PARM_DESC(skip_txen_test, "Skip checking for the TXEN bug at init time");
3279 #ifdef CONFIG_SERIAL_8250_RSA
3280 module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
3281 MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
3283 MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);