drivers/serial/8250_pci.c

   1 /*
   2  *  linux/drivers/char/8250_pci.c
   3  *
   4  *  Probe module for 8250/16550-type PCI serial ports.
   5  *
   6  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
   7  *
   8  *  Copyright (C) 2001 Russell King, All Rights Reserved.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License.
  13  *
  14  *  $Id: 8250_pci.c,v 1.28 2002/11/02 11:14:18 rmk Exp $
  15  */
  16 #include <linux/module.h>
  17 #include <linux/init.h>
  18 #include <linux/pci.h>
  19 #include <linux/sched.h>
  20 #include <linux/string.h>
  21 #include <linux/kernel.h>
  22 #include <linux/slab.h>
  23 #include <linux/delay.h>
  24 #include <linux/tty.h>
  25 #include <linux/serial_core.h>
  26 #include <linux/8250_pci.h>
  27 #include <linux/bitops.h>
  28
  29 #include <asm/byteorder.h>
  30 #include <asm/io.h>
  31
  32 #include "8250.h"
  33
  34 #undef SERIAL_DEBUG_PCI
  35
  36 /*
  37  * Definitions for PCI support.
  38  */
  39 #define FL_BASE_MASK            0x0007
  40 #define FL_BASE0                0x0000
  41 #define FL_BASE1                0x0001
  42 #define FL_BASE2                0x0002
  43 #define FL_BASE3                0x0003
  44 #define FL_BASE4                0x0004
  45 #define FL_GET_BASE(x)          (x & FL_BASE_MASK)
  46
  47 /* Use successive BARs (PCI base address registers),
  48    else use offset into some specified BAR */
  49 #define FL_BASE_BARS            0x0008
  50
  51 /* do not assign an irq */
  52 #define FL_NOIRQ                0x0080
  53
  54 /* Use the Base address register size to cap number of ports */
  55 #define FL_REGION_SZ_CAP        0x0100
  56
  57 struct pciserial_board {
  58         unsigned int flags;
  59         unsigned int num_ports;
  60         unsigned int base_baud;
  61         unsigned int uart_offset;
  62         unsigned int reg_shift;
  63         unsigned int first_offset;
  64 };
  65
  66 /*
  67  * init function returns:
  68  *  > 0 - number of ports
  69  *  = 0 - use board->num_ports
  70  *  < 0 - error
  71  */
  72 struct pci_serial_quirk {
  73         u32     vendor;
  74         u32     device;
  75         u32     subvendor;
  76         u32     subdevice;
  77         int     (*init)(struct pci_dev *dev);
  78         int     (*setup)(struct pci_dev *dev, struct pciserial_board *,
  79                          struct uart_port *port, int idx);
  80         void    (*exit)(struct pci_dev *dev);
  81 };
  82
  83 #define PCI_NUM_BAR_RESOURCES   6
  84
  85 struct serial_private {
  86         unsigned int            nr;
  87         void __iomem            *remapped_bar[PCI_NUM_BAR_RESOURCES];
  88         struct pci_serial_quirk *quirk;
  89         int                     line[0];
  90 };
  91
  92 static void moan_device(const char *str, struct pci_dev *dev)
  93 {
  94         printk(KERN_WARNING "%s: %s\n"
  95                KERN_WARNING "Please send the output of lspci -vv, this\n"
  96                KERN_WARNING "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
  97                KERN_WARNING "manufacturer and name of serial board or\n"
  98                KERN_WARNING "modem board to rmk+serial@arm.linux.org.uk.\n",
  99                pci_name(dev), str, dev->vendor, dev->device,
 100                dev->subsystem_vendor, dev->subsystem_device);
 101 }
 102
 103 static int
 104 setup_port(struct pci_dev *dev, struct uart_port *port,
 105            int bar, int offset, int regshift)
 106 {
 107         struct serial_private *priv = pci_get_drvdata(dev);
 108         unsigned long base, len;
 109
 110         if (bar >= PCI_NUM_BAR_RESOURCES)
 111                 return -EINVAL;
 112
 113         if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
 114                 base = pci_resource_start(dev, bar);
 115                 len =  pci_resource_len(dev, bar);
 116
 117                 if (!priv->remapped_bar[bar])
 118                         priv->remapped_bar[bar] = ioremap(base, len);
 119                 if (!priv->remapped_bar[bar])
 120                         return -ENOMEM;
 121
 122                 port->iotype = UPIO_MEM;
 123                 port->mapbase = base + offset;
 124                 port->membase = priv->remapped_bar[bar] + offset;
 125                 port->regshift = regshift;
 126         } else {
 127                 base = pci_resource_start(dev, bar) + offset;
 128                 port->iotype = UPIO_PORT;
 129                 port->iobase = base;
 130         }
 131         return 0;
 132 }
 133
 134 /*
 135  * AFAVLAB uses a different mixture of BARs and offsets
 136  * Not that ugly ;) -- HW
 137  */
 138 static int
 139 afavlab_setup(struct pci_dev *dev, struct pciserial_board *board,
 140               struct uart_port *port, int idx)
 141 {
 142         unsigned int bar, offset = board->first_offset;
 143
 144         bar = FL_GET_BASE(board->flags);
 145         if (idx < 4)
 146                 bar += idx;
 147         else {
 148                 bar = 4;
 149                 offset += (idx - 4) * board->uart_offset;
 150         }
 151
 152         return setup_port(dev, port, bar, offset, board->reg_shift);
 153 }
 154
 155 /*
 156  * HP's Remote Management Console.  The Diva chip came in several
 157  * different versions.  N-class, L2000 and A500 have two Diva chips, each
 158  * with 3 UARTs (the third UART on the second chip is unused).  Superdome
 159  * and Keystone have one Diva chip with 3 UARTs.  Some later machines have
 160  * one Diva chip, but it has been expanded to 5 UARTs.
 161  */
 162 static int __devinit pci_hp_diva_init(struct pci_dev *dev)
 163 {
 164         int rc = 0;
 165
 166         switch (dev->subsystem_device) {
 167         case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
 168         case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
 169         case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
 170         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 171                 rc = 3;
 172                 break;
 173         case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
 174                 rc = 2;
 175                 break;
 176         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 177                 rc = 4;
 178                 break;
 179         case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
 180                 rc = 1;
 181                 break;
 182         }
 183
 184         return rc;
 185 }
 186
 187 /*
 188  * HP's Diva chip puts the 4th/5th serial port further out, and
 189  * some serial ports are supposed to be hidden on certain models.
 190  */
 191 static int
 192 pci_hp_diva_setup(struct pci_dev *dev, struct pciserial_board *board,
 193               struct uart_port *port, int idx)
 194 {
 195         unsigned int offset = board->first_offset;
 196         unsigned int bar = FL_GET_BASE(board->flags);
 197
 198         switch (dev->subsystem_device) {
 199         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 200                 if (idx == 3)
 201                         idx++;
 202                 break;
 203         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 204                 if (idx > 0)
 205                         idx++;
 206                 if (idx > 2)
 207                         idx++;
 208                 break;
 209         }
 210         if (idx > 2)
 211                 offset = 0x18;
 212
 213         offset += idx * board->uart_offset;
 214
 215         return setup_port(dev, port, bar, offset, board->reg_shift);
 216 }
 217
 218 /*
 219  * Added for EKF Intel i960 serial boards
 220  */
 221 static int __devinit pci_inteli960ni_init(struct pci_dev *dev)
 222 {
 223         unsigned long oldval;
 224
 225         if (!(dev->subsystem_device & 0x1000))
 226                 return -ENODEV;
 227
 228         /* is firmware started? */
 229         pci_read_config_dword(dev, 0x44, (void*) &oldval);
 230         if (oldval == 0x00001000L) { /* RESET value */
 231                 printk(KERN_DEBUG "Local i960 firmware missing");
 232                 return -ENODEV;
 233         }
 234         return 0;
 235 }
 236
 237 /*
 238  * Some PCI serial cards using the PLX 9050 PCI interface chip require
 239  * that the card interrupt be explicitly enabled or disabled.  This
 240  * seems to be mainly needed on card using the PLX which also use I/O
 241  * mapped memory.
 242  */
 243 static int __devinit pci_plx9050_init(struct pci_dev *dev)
 244 {
 245         u8 irq_config;
 246         void __iomem *p;
 247
 248         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
 249                 moan_device("no memory in bar 0", dev);
 250                 return 0;
 251         }
 252
 253         irq_config = 0x41;
 254         if (dev->vendor == PCI_VENDOR_ID_PANACOM)
 255                 irq_config = 0x43;
 256         if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
 257             (dev->device == PCI_DEVICE_ID_PLX_ROMULUS)) {
 258                 /*
 259                  * As the megawolf cards have the int pins active
 260                  * high, and have 2 UART chips, both ints must be
 261                  * enabled on the 9050. Also, the UARTS are set in
 262                  * 16450 mode by default, so we have to enable the
 263                  * 16C950 'enhanced' mode so that we can use the
 264                  * deep FIFOs
 265                  */
 266                 irq_config = 0x5b;
 267         }
 268
 269         /*
 270          * enable/disable interrupts
 271          */
 272         p = ioremap(pci_resource_start(dev, 0), 0x80);
 273         if (p == NULL)
 274                 return -ENOMEM;
 275         writel(irq_config, p + 0x4c);
 276
 277         /*
 278          * Read the register back to ensure that it took effect.
 279          */
 280         readl(p + 0x4c);
 281         iounmap(p);
 282
 283         return 0;
 284 }
 285
 286 static void __devexit pci_plx9050_exit(struct pci_dev *dev)
 287 {
 288         u8 __iomem *p;
 289
 290         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
 291                 return;
 292
 293         /*
 294          * disable interrupts
 295          */
 296         p = ioremap(pci_resource_start(dev, 0), 0x80);
 297         if (p != NULL) {
 298                 writel(0, p + 0x4c);
 299
 300                 /*
 301                  * Read the register back to ensure that it took effect.
 302                  */
 303                 readl(p + 0x4c);
 304                 iounmap(p);
 305         }
 306 }
 307
 308 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
 309 static int
 310 sbs_setup(struct pci_dev *dev, struct pciserial_board *board,
 311                 struct uart_port *port, int idx)
 312 {
 313         unsigned int bar, offset = board->first_offset;
 314
 315         bar = 0;
 316
 317         if (idx < 4) {
 318                 /* first four channels map to 0, 0x100, 0x200, 0x300 */
 319                 offset += idx * board->uart_offset;
 320         } else if (idx < 8) {
 321                 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
 322                 offset += idx * board->uart_offset + 0xC00;
 323         } else /* we have only 8 ports on PMC-OCTALPRO */
 324                 return 1;
 325
 326         return setup_port(dev, port, bar, offset, board->reg_shift);
 327 }
 328
 329 /*
 330 * This does initialization for PMC OCTALPRO cards:
 331 * maps the device memory, resets the UARTs (needed, bc
 332 * if the module is removed and inserted again, the card
 333 * is in the sleep mode) and enables global interrupt.
 334 */
 335
 336 /* global control register offset for SBS PMC-OctalPro */
 337 #define OCT_REG_CR_OFF          0x500
 338
 339 static int __devinit sbs_init(struct pci_dev *dev)
 340 {
 341         u8 __iomem *p;
 342
 343         p = ioremap(pci_resource_start(dev, 0),pci_resource_len(dev,0));
 344
 345         if (p == NULL)
 346                 return -ENOMEM;
 347         /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
 348         writeb(0x10,p + OCT_REG_CR_OFF);
 349         udelay(50);
 350         writeb(0x0,p + OCT_REG_CR_OFF);
 351
 352         /* Set bit-2 (INTENABLE) of Control Register */
 353         writeb(0x4, p + OCT_REG_CR_OFF);
 354         iounmap(p);
 355
 356         return 0;
 357 }
 358
 359 /*
 360  * Disables the global interrupt of PMC-OctalPro
 361  */
 362
 363 static void __devexit sbs_exit(struct pci_dev *dev)
 364 {
 365         u8 __iomem *p;
 366
 367         p = ioremap(pci_resource_start(dev, 0),pci_resource_len(dev,0));
 368         if (p != NULL) {
 369                 writeb(0, p + OCT_REG_CR_OFF);
 370         }
 371         iounmap(p);
 372 }
 373
 374 /*
 375  * SIIG serial cards have an PCI interface chip which also controls
 376  * the UART clocking frequency. Each UART can be clocked independently
 377  * (except cards equiped with 4 UARTs) and initial clocking settings
 378  * are stored in the EEPROM chip. It can cause problems because this
 379  * version of serial driver doesn't support differently clocked UART's
 380  * on single PCI card. To prevent this, initialization functions set
 381  * high frequency clocking for all UART's on given card. It is safe (I
 382  * hope) because it doesn't touch EEPROM settings to prevent conflicts
 383  * with other OSes (like M$ DOS).
 384  *
 385  *  SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
 386  *
 387  * There is two family of SIIG serial cards with different PCI
 388  * interface chip and different configuration methods:
 389  *     - 10x cards have control registers in IO and/or memory space;
 390  *     - 20x cards have control registers in standard PCI configuration space.
 391  *
 392  * There are also Quartet Serial cards which use Oxford Semiconductor
 393  * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
 394  *
 395  * Note: some SIIG cards are probed by the parport_serial object.
 396  */
 397
 398 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
 399 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
 400
 401 static int pci_siig10x_init(struct pci_dev *dev)
 402 {
 403         u16 data;
 404         void __iomem *p;
 405
 406         switch (dev->device & 0xfff8) {
 407         case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
 408                 data = 0xffdf;
 409                 break;
 410         case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
 411                 data = 0xf7ff;
 412                 break;
 413         default:                        /* 1S1P, 4S */
 414                 data = 0xfffb;
 415                 break;
 416         }
 417
 418         p = ioremap(pci_resource_start(dev, 0), 0x80);
 419         if (p == NULL)
 420                 return -ENOMEM;
 421
 422         writew(readw(p + 0x28) & data, p + 0x28);
 423         readw(p + 0x28);
 424         iounmap(p);
 425         return 0;
 426 }
 427
 428 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
 429 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
 430
 431 static int pci_siig20x_init(struct pci_dev *dev)
 432 {
 433         u8 data;
 434
 435         /* Change clock frequency for the first UART. */
 436         pci_read_config_byte(dev, 0x6f, &data);
 437         pci_write_config_byte(dev, 0x6f, data & 0xef);
 438
 439         /* If this card has 2 UART, we have to do the same with second UART. */
 440         if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
 441             ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
 442                 pci_read_config_byte(dev, 0x73, &data);
 443                 pci_write_config_byte(dev, 0x73, data & 0xef);
 444         }
 445         return 0;
 446 }
 447
 448 int pci_siig10x_fn(struct pci_dev *dev, int enable)
 449 {
 450         int ret = 0;
 451         if (enable)
 452                 ret = pci_siig10x_init(dev);
 453         return ret;
 454 }
 455
 456 int pci_siig20x_fn(struct pci_dev *dev, int enable)
 457 {
 458         int ret = 0;
 459         if (enable)
 460                 ret = pci_siig20x_init(dev);
 461         return ret;
 462 }
 463
 464 EXPORT_SYMBOL(pci_siig10x_fn);
 465 EXPORT_SYMBOL(pci_siig20x_fn);
 466
 467 /*
 468  * Timedia has an explosion of boards, and to avoid the PCI table from
 469  * growing *huge*, we use this function to collapse some 70 entries
 470  * in the PCI table into one, for sanity's and compactness's sake.
 471  */
 472 static unsigned short timedia_single_port[] = {
 473         0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
 474 };
 475
 476 static unsigned short timedia_dual_port[] = {
 477         0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
 478         0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
 479         0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
 480         0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
 481         0xD079, 0
 482 };
 483
 484 static unsigned short timedia_quad_port[] = {
 485         0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
 486         0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
 487         0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
 488         0xB157, 0
 489 };
 490
 491 static unsigned short timedia_eight_port[] = {
 492         0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
 493         0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
 494 };
 495
 496 static struct timedia_struct {
 497         int num;
 498         unsigned short *ids;
 499 } timedia_data[] = {
 500         { 1, timedia_single_port },
 501         { 2, timedia_dual_port },
 502         { 4, timedia_quad_port },
 503         { 8, timedia_eight_port },
 504         { 0, NULL }
 505 };
 506
 507 static int __devinit pci_timedia_init(struct pci_dev *dev)
 508 {
 509         unsigned short *ids;
 510         int i, j;
 511
 512         for (i = 0; timedia_data[i].num; i++) {
 513                 ids = timedia_data[i].ids;
 514                 for (j = 0; ids[j]; j++)
 515                         if (dev->subsystem_device == ids[j])
 516                                 return timedia_data[i].num;
 517         }
 518         return 0;
 519 }
 520
 521 /*
 522  * Timedia/SUNIX uses a mixture of BARs and offsets
 523  * Ugh, this is ugly as all hell --- TYT
 524  */
 525 static int
 526 pci_timedia_setup(struct pci_dev *dev, struct pciserial_board *board,
 527                   struct uart_port *port, int idx)
 528 {
 529         unsigned int bar = 0, offset = board->first_offset;
 530
 531         switch (idx) {
 532         case 0:
 533                 bar = 0;
 534                 break;
 535         case 1:
 536                 offset = board->uart_offset;
 537                 bar = 0;
 538                 break;
 539         case 2:
 540                 bar = 1;
 541                 break;
 542         case 3:
 543                 offset = board->uart_offset;
 544                 bar = 1;
 545         case 4: /* BAR 2 */
 546         case 5: /* BAR 3 */
 547         case 6: /* BAR 4 */
 548         case 7: /* BAR 5 */
 549                 bar = idx - 2;
 550         }
 551
 552         return setup_port(dev, port, bar, offset, board->reg_shift);
 553 }
 554
 555 /*
 556  * Some Titan cards are also a little weird
 557  */
 558 static int
 559 titan_400l_800l_setup(struct pci_dev *dev,
 560                       struct pciserial_board *board,
 561                       struct uart_port *port, int idx)
 562 {
 563         unsigned int bar, offset = board->first_offset;
 564
 565         switch (idx) {
 566         case 0:
 567                 bar = 1;
 568                 break;
 569         case 1:
 570                 bar = 2;
 571                 break;
 572         default:
 573                 bar = 4;
 574                 offset = (idx - 2) * board->uart_offset;
 575         }
 576
 577         return setup_port(dev, port, bar, offset, board->reg_shift);
 578 }
 579
 580 static int __devinit pci_xircom_init(struct pci_dev *dev)
 581 {
 582         msleep(100);
 583         return 0;
 584 }
 585
 586 static int __devinit pci_netmos_init(struct pci_dev *dev)
 587 {
 588         /* subdevice 0x00PS means <P> parallel, <S> serial */
 589         unsigned int num_serial = dev->subsystem_device & 0xf;
 590
 591         if (num_serial == 0)
 592                 return -ENODEV;
 593         return num_serial;
 594 }
 595
 596 static int
 597 pci_default_setup(struct pci_dev *dev, struct pciserial_board *board,
 598                   struct uart_port *port, int idx)
 599 {
 600         unsigned int bar, offset = board->first_offset, maxnr;
 601
 602         bar = FL_GET_BASE(board->flags);
 603         if (board->flags & FL_BASE_BARS)
 604                 bar += idx;
 605         else
 606                 offset += idx * board->uart_offset;
 607
 608         maxnr = (pci_resource_len(dev, bar) - board->first_offset) /
 609                 (8 << board->reg_shift);
 610
 611         if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
 612                 return 1;
 613
 614         return setup_port(dev, port, bar, offset, board->reg_shift);
 615 }
 616
 617 /* This should be in linux/pci_ids.h */
 618 #define PCI_VENDOR_ID_SBSMODULARIO      0x124B
 619 #define PCI_SUBVENDOR_ID_SBSMODULARIO   0x124B
 620 #define PCI_DEVICE_ID_OCTPRO            0x0001
 621 #define PCI_SUBDEVICE_ID_OCTPRO232      0x0108
 622 #define PCI_SUBDEVICE_ID_OCTPRO422      0x0208
 623 #define PCI_SUBDEVICE_ID_POCTAL232      0x0308
 624 #define PCI_SUBDEVICE_ID_POCTAL422      0x0408
 625
 626 /*
 627  * Master list of serial port init/setup/exit quirks.
 628  * This does not describe the general nature of the port.
 629  * (ie, baud base, number and location of ports, etc)
 630  *
 631  * This list is ordered alphabetically by vendor then device.
 632  * Specific entries must come before more generic entries.
 633  */
 634 static struct pci_serial_quirk pci_serial_quirks[] = {
 635         /*
 636          * AFAVLAB cards.
 637          *  It is not clear whether this applies to all products.
 638          */
 639         {
 640                 .vendor         = PCI_VENDOR_ID_AFAVLAB,
 641                 .device         = PCI_ANY_ID,
 642                 .subvendor      = PCI_ANY_ID,
 643                 .subdevice      = PCI_ANY_ID,
 644                 .setup          = afavlab_setup,
 645         },
 646         /*
 647          * HP Diva
 648          */
 649         {
 650                 .vendor         = PCI_VENDOR_ID_HP,
 651                 .device         = PCI_DEVICE_ID_HP_DIVA,
 652                 .subvendor      = PCI_ANY_ID,
 653                 .subdevice      = PCI_ANY_ID,
 654                 .init           = pci_hp_diva_init,
 655                 .setup          = pci_hp_diva_setup,
 656         },
 657         /*
 658          * Intel
 659          */
 660         {
 661                 .vendor         = PCI_VENDOR_ID_INTEL,
 662                 .device         = PCI_DEVICE_ID_INTEL_80960_RP,
 663                 .subvendor      = 0xe4bf,
 664                 .subdevice      = PCI_ANY_ID,
 665                 .init           = pci_inteli960ni_init,
 666                 .setup          = pci_default_setup,
 667         },
 668         /*
 669          * Panacom
 670          */
 671         {
 672                 .vendor         = PCI_VENDOR_ID_PANACOM,
 673                 .device         = PCI_DEVICE_ID_PANACOM_QUADMODEM,
 674                 .subvendor      = PCI_ANY_ID,
 675                 .subdevice      = PCI_ANY_ID,
 676                 .init           = pci_plx9050_init,
 677                 .setup          = pci_default_setup,
 678                 .exit           = __devexit_p(pci_plx9050_exit),
 679         },
 680         {
 681                 .vendor         = PCI_VENDOR_ID_PANACOM,
 682                 .device         = PCI_DEVICE_ID_PANACOM_DUALMODEM,
 683                 .subvendor      = PCI_ANY_ID,
 684                 .subdevice      = PCI_ANY_ID,
 685                 .init           = pci_plx9050_init,
 686                 .setup          = pci_default_setup,
 687                 .exit           = __devexit_p(pci_plx9050_exit),
 688         },
 689         /*
 690          * PLX
 691          */
 692         {
 693                 .vendor         = PCI_VENDOR_ID_PLX,
 694                 .device         = PCI_DEVICE_ID_PLX_9050,
 695                 .subvendor      = PCI_SUBVENDOR_ID_KEYSPAN,
 696                 .subdevice      = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
 697                 .init           = pci_plx9050_init,
 698                 .setup          = pci_default_setup,
 699                 .exit           = __devexit_p(pci_plx9050_exit),
 700         },
 701         {
 702                 .vendor         = PCI_VENDOR_ID_PLX,
 703                 .device         = PCI_DEVICE_ID_PLX_ROMULUS,
 704                 .subvendor      = PCI_VENDOR_ID_PLX,
 705                 .subdevice      = PCI_DEVICE_ID_PLX_ROMULUS,
 706                 .init           = pci_plx9050_init,
 707                 .setup          = pci_default_setup,
 708                 .exit           = __devexit_p(pci_plx9050_exit),
 709         },
 710         /*
 711          * SBS Technologies, Inc., PMC-OCTALPRO 232
 712          */
 713         {
 714                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
 715                 .device         = PCI_DEVICE_ID_OCTPRO,
 716                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
 717                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO232,
 718                 .init           = sbs_init,
 719                 .setup          = sbs_setup,
 720                 .exit           = __devexit_p(sbs_exit),
 721         },
 722         /*
 723          * SBS Technologies, Inc., PMC-OCTALPRO 422
 724          */
 725         {
 726                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
 727                 .device         = PCI_DEVICE_ID_OCTPRO,
 728                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
 729                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO422,
 730                 .init           = sbs_init,
 731                 .setup          = sbs_setup,
 732                 .exit           = __devexit_p(sbs_exit),
 733         },
 734         /*
 735          * SBS Technologies, Inc., P-Octal 232
 736          */
 737         {
 738                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
 739                 .device         = PCI_DEVICE_ID_OCTPRO,
 740                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
 741                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL232,
 742                 .init           = sbs_init,
 743                 .setup          = sbs_setup,
 744                 .exit           = __devexit_p(sbs_exit),
 745         },
 746         /*
 747          * SBS Technologies, Inc., P-Octal 422
 748          */
 749         {
 750                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
 751                 .device         = PCI_DEVICE_ID_OCTPRO,
 752                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
 753                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL422,
 754                 .init           = sbs_init,
 755                 .setup          = sbs_setup,
 756                 .exit           = __devexit_p(sbs_exit),
 757         },
 758
 759         /*
 760          * SIIG cards.
 761          *  It is not clear whether these could be collapsed.
 762          */
 763         {
 764                 .vendor         = PCI_VENDOR_ID_SIIG,
 765                 .device         = PCI_DEVICE_ID_SIIG_1S_10x_550,
 766                 .subvendor      = PCI_ANY_ID,
 767                 .subdevice      = PCI_ANY_ID,
 768                 .init           = pci_siig10x_init,
 769                 .setup          = pci_default_setup,
 770         },
 771         {
 772                 .vendor         = PCI_VENDOR_ID_SIIG,
 773                 .device         = PCI_DEVICE_ID_SIIG_1S_10x_650,
 774                 .subvendor      = PCI_ANY_ID,
 775                 .subdevice      = PCI_ANY_ID,
 776                 .init           = pci_siig10x_init,
 777                 .setup          = pci_default_setup,
 778         },
 779         {
 780                 .vendor         = PCI_VENDOR_ID_SIIG,
 781                 .device         = PCI_DEVICE_ID_SIIG_1S_10x_850,
 782                 .subvendor      = PCI_ANY_ID,
 783                 .subdevice      = PCI_ANY_ID,
 784                 .init           = pci_siig10x_init,
 785                 .setup          = pci_default_setup,
 786         },
 787         {
 788                 .vendor         = PCI_VENDOR_ID_SIIG,
 789                 .device         = PCI_DEVICE_ID_SIIG_2S_10x_550,
 790                 .subvendor      = PCI_ANY_ID,
 791                 .subdevice      = PCI_ANY_ID,
 792                 .init           = pci_siig10x_init,
 793                 .setup          = pci_default_setup,
 794         },
 795         {
 796                 .vendor         = PCI_VENDOR_ID_SIIG,
 797                 .device         = PCI_DEVICE_ID_SIIG_2S_10x_650,
 798                 .subvendor      = PCI_ANY_ID,
 799                 .subdevice      = PCI_ANY_ID,
 800                 .init           = pci_siig10x_init,
 801                 .setup          = pci_default_setup,
 802         },
 803         {
 804                 .vendor         = PCI_VENDOR_ID_SIIG,
 805                 .device         = PCI_DEVICE_ID_SIIG_2S_10x_850,
 806                 .subvendor      = PCI_ANY_ID,
 807                 .subdevice      = PCI_ANY_ID,
 808                 .init           = pci_siig10x_init,
 809                 .setup          = pci_default_setup,
 810         },
 811         {
 812                 .vendor         = PCI_VENDOR_ID_SIIG,
 813                 .device         = PCI_DEVICE_ID_SIIG_4S_10x_550,
 814                 .subvendor      = PCI_ANY_ID,
 815                 .subdevice      = PCI_ANY_ID,
 816                 .init           = pci_siig10x_init,
 817                 .setup          = pci_default_setup,
 818         },
 819         {
 820                 .vendor         = PCI_VENDOR_ID_SIIG,
 821                 .device         = PCI_DEVICE_ID_SIIG_4S_10x_650,
 822                 .subvendor      = PCI_ANY_ID,
 823                 .subdevice      = PCI_ANY_ID,
 824                 .init           = pci_siig10x_init,
 825                 .setup          = pci_default_setup,
 826         },
 827         {
 828                 .vendor         = PCI_VENDOR_ID_SIIG,
 829                 .device         = PCI_DEVICE_ID_SIIG_4S_10x_850,
 830                 .subvendor      = PCI_ANY_ID,
 831                 .subdevice      = PCI_ANY_ID,
 832                 .init           = pci_siig10x_init,
 833                 .setup          = pci_default_setup,
 834         },
 835         {
 836                 .vendor         = PCI_VENDOR_ID_SIIG,
 837                 .device         = PCI_DEVICE_ID_SIIG_1S_20x_550,
 838                 .subvendor      = PCI_ANY_ID,
 839                 .subdevice      = PCI_ANY_ID,
 840                 .init           = pci_siig20x_init,
 841                 .setup          = pci_default_setup,
 842         },
 843         {
 844                 .vendor         = PCI_VENDOR_ID_SIIG,
 845                 .device         = PCI_DEVICE_ID_SIIG_1S_20x_650,
 846                 .subvendor      = PCI_ANY_ID,
 847                 .subdevice      = PCI_ANY_ID,
 848                 .init           = pci_siig20x_init,
 849                 .setup          = pci_default_setup,
 850         },
 851         {
 852                 .vendor         = PCI_VENDOR_ID_SIIG,
 853                 .device         = PCI_DEVICE_ID_SIIG_1S_20x_850,
 854                 .subvendor      = PCI_ANY_ID,
 855                 .subdevice      = PCI_ANY_ID,
 856                 .init           = pci_siig20x_init,
 857                 .setup          = pci_default_setup,
 858         },
 859         {
 860                 .vendor         = PCI_VENDOR_ID_SIIG,
 861                 .device         = PCI_DEVICE_ID_SIIG_2S_20x_550,
 862                 .subvendor      = PCI_ANY_ID,
 863                 .subdevice      = PCI_ANY_ID,
 864                 .init           = pci_siig20x_init,
 865                 .setup          = pci_default_setup,
 866         },
 867         {       .vendor         = PCI_VENDOR_ID_SIIG,
 868                 .device         = PCI_DEVICE_ID_SIIG_2S_20x_650,
 869                 .subvendor      = PCI_ANY_ID,
 870                 .subdevice      = PCI_ANY_ID,
 871                 .init           = pci_siig20x_init,
 872                 .setup          = pci_default_setup,
 873         },
 874         {
 875                 .vendor         = PCI_VENDOR_ID_SIIG,
 876                 .device         = PCI_DEVICE_ID_SIIG_2S_20x_850,
 877                 .subvendor      = PCI_ANY_ID,
 878                 .subdevice      = PCI_ANY_ID,
 879                 .init           = pci_siig20x_init,
 880                 .setup          = pci_default_setup,
 881         },
 882         {
 883                 .vendor         = PCI_VENDOR_ID_SIIG,
 884                 .device         = PCI_DEVICE_ID_SIIG_4S_20x_550,
 885                 .subvendor      = PCI_ANY_ID,
 886                 .subdevice      = PCI_ANY_ID,
 887                 .init           = pci_siig20x_init,
 888                 .setup          = pci_default_setup,
 889         },
 890         {
 891                 .vendor         = PCI_VENDOR_ID_SIIG,
 892                 .device         = PCI_DEVICE_ID_SIIG_4S_20x_650,
 893                 .subvendor      = PCI_ANY_ID,
 894                 .subdevice      = PCI_ANY_ID,
 895                 .init           = pci_siig20x_init,
 896                 .setup          = pci_default_setup,
 897         },
 898         {
 899                 .vendor         = PCI_VENDOR_ID_SIIG,
 900                 .device         = PCI_DEVICE_ID_SIIG_4S_20x_850,
 901                 .subvendor      = PCI_ANY_ID,
 902                 .subdevice      = PCI_ANY_ID,
 903                 .init           = pci_siig20x_init,
 904                 .setup          = pci_default_setup,
 905         },
 906         /*
 907          * Titan cards
 908          */
 909         {
 910                 .vendor         = PCI_VENDOR_ID_TITAN,
 911                 .device         = PCI_DEVICE_ID_TITAN_400L,
 912                 .subvendor      = PCI_ANY_ID,
 913                 .subdevice      = PCI_ANY_ID,
 914                 .setup          = titan_400l_800l_setup,
 915         },
 916         {
 917                 .vendor         = PCI_VENDOR_ID_TITAN,
 918                 .device         = PCI_DEVICE_ID_TITAN_800L,
 919                 .subvendor      = PCI_ANY_ID,
 920                 .subdevice      = PCI_ANY_ID,
 921                 .setup          = titan_400l_800l_setup,
 922         },
 923         /*
 924          * Timedia cards
 925          */
 926         {
 927                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
 928                 .device         = PCI_DEVICE_ID_TIMEDIA_1889,
 929                 .subvendor      = PCI_VENDOR_ID_TIMEDIA,
 930                 .subdevice      = PCI_ANY_ID,
 931                 .init           = pci_timedia_init,
 932                 .setup          = pci_timedia_setup,
 933         },
 934         {
 935                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
 936                 .device         = PCI_ANY_ID,
 937                 .subvendor      = PCI_ANY_ID,
 938                 .subdevice      = PCI_ANY_ID,
 939                 .setup          = pci_timedia_setup,
 940         },
 941         /*
 942          * Xircom cards
 943          */
 944         {
 945                 .vendor         = PCI_VENDOR_ID_XIRCOM,
 946                 .device         = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
 947                 .subvendor      = PCI_ANY_ID,
 948                 .subdevice      = PCI_ANY_ID,
 949                 .init           = pci_xircom_init,
 950                 .setup          = pci_default_setup,
 951         },
 952         /*
 953          * Netmos cards
 954          */
 955         {
 956                 .vendor         = PCI_VENDOR_ID_NETMOS,
 957                 .device         = PCI_ANY_ID,
 958                 .subvendor      = PCI_ANY_ID,
 959                 .subdevice      = PCI_ANY_ID,
 960                 .init           = pci_netmos_init,
 961                 .setup          = pci_default_setup,
 962         },
 963         /*
 964          * Default "match everything" terminator entry
 965          */
 966         {
 967                 .vendor         = PCI_ANY_ID,
 968                 .device         = PCI_ANY_ID,
 969                 .subvendor      = PCI_ANY_ID,
 970                 .subdevice      = PCI_ANY_ID,
 971                 .setup          = pci_default_setup,
 972         }
 973 };
 974
 975 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
 976 {
 977         return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
 978 }
 979
 980 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
 981 {
 982         struct pci_serial_quirk *quirk;
 983
 984         for (quirk = pci_serial_quirks; ; quirk++)
 985                 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
 986                     quirk_id_matches(quirk->device, dev->device) &&
 987                     quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
 988                     quirk_id_matches(quirk->subdevice, dev->subsystem_device))
 989                         break;
 990         return quirk;
 991 }
 992
 993 static _INLINE_ int
 994 get_pci_irq(struct pci_dev *dev, struct pciserial_board *board, int idx)
 995 {
 996         if (board->flags & FL_NOIRQ)
 997                 return 0;
 998         else
 999                 return dev->irq;
1000 }
1001
1002 /*
1003  * This is the configuration table for all of the PCI serial boards
1004  * which we support.  It is directly indexed by the pci_board_num_t enum
1005  * value, which is encoded in the pci_device_id PCI probe table's
1006  * driver_data member.
1007  *
1008  * The makeup of these names are:
1009  *  pbn_bn{_bt}_n_baud
1010  *
1011  *  bn   = PCI BAR number
1012  *  bt   = Index using PCI BARs
1013  *  n    = number of serial ports
1014  *  baud = baud rate
1015  *
1016  * This table is sorted by (in order): baud, bt, bn, n.
1017  *
1018  * Please note: in theory if n = 1, _bt infix should make no difference.
1019  * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
1020  */
1021 enum pci_board_num_t {
1022         pbn_default = 0,
1023
1024         pbn_b0_1_115200,
1025         pbn_b0_2_115200,
1026         pbn_b0_4_115200,
1027         pbn_b0_5_115200,
1028
1029         pbn_b0_1_921600,
1030         pbn_b0_2_921600,
1031         pbn_b0_4_921600,
1032
1033         pbn_b0_4_1152000,
1034
1035         pbn_b0_bt_1_115200,
1036         pbn_b0_bt_2_115200,
1037         pbn_b0_bt_8_115200,
1038
1039         pbn_b0_bt_1_460800,
1040         pbn_b0_bt_2_460800,
1041         pbn_b0_bt_4_460800,
1042
1043         pbn_b0_bt_1_921600,
1044         pbn_b0_bt_2_921600,
1045         pbn_b0_bt_4_921600,
1046         pbn_b0_bt_8_921600,
1047
1048         pbn_b1_1_115200,
1049         pbn_b1_2_115200,
1050         pbn_b1_4_115200,
1051         pbn_b1_8_115200,
1052
1053         pbn_b1_1_921600,
1054         pbn_b1_2_921600,
1055         pbn_b1_4_921600,
1056         pbn_b1_8_921600,
1057
1058         pbn_b1_bt_2_921600,
1059
1060         pbn_b1_1_1382400,
1061         pbn_b1_2_1382400,
1062         pbn_b1_4_1382400,
1063         pbn_b1_8_1382400,
1064
1065         pbn_b2_1_115200,
1066         pbn_b2_8_115200,
1067
1068         pbn_b2_1_460800,
1069         pbn_b2_4_460800,
1070         pbn_b2_8_460800,
1071         pbn_b2_16_460800,
1072
1073         pbn_b2_1_921600,
1074         pbn_b2_4_921600,
1075         pbn_b2_8_921600,
1076
1077         pbn_b2_bt_1_115200,
1078         pbn_b2_bt_2_115200,
1079         pbn_b2_bt_4_115200,
1080
1081         pbn_b2_bt_2_921600,
1082         pbn_b2_bt_4_921600,
1083
1084         pbn_b3_4_115200,
1085         pbn_b3_8_115200,
1086
1087         /*
1088          * Board-specific versions.
1089          */
1090         pbn_panacom,
1091         pbn_panacom2,
1092         pbn_panacom4,
1093         pbn_plx_romulus,
1094         pbn_oxsemi,
1095         pbn_intel_i960,
1096         pbn_sgi_ioc3,
1097         pbn_nec_nile4,
1098         pbn_computone_4,
1099         pbn_computone_6,
1100         pbn_computone_8,
1101         pbn_sbsxrsio,
1102         pbn_exar_XR17C152,
1103         pbn_exar_XR17C154,
1104         pbn_exar_XR17C158,
1105 };
1106
1107 /*
1108  * uart_offset - the space between channels
1109  * reg_shift   - describes how the UART registers are mapped
1110  *               to PCI memory by the card.
1111  * For example IER register on SBS, Inc. PMC-OctPro is located at
1112  * offset 0x10 from the UART base, while UART_IER is defined as 1
1113  * in include/linux/serial_reg.h,
1114  * see first lines of serial_in() and serial_out() in 8250.c
1115 */
1116
1117 static struct pciserial_board pci_boards[] __devinitdata = {
1118         [pbn_default] = {
1119                 .flags          = FL_BASE0,
1120                 .num_ports      = 1,
1121                 .base_baud      = 115200,
1122                 .uart_offset    = 8,
1123         },
1124         [pbn_b0_1_115200] = {
1125                 .flags          = FL_BASE0,
1126                 .num_ports      = 1,
1127                 .base_baud      = 115200,
1128                 .uart_offset    = 8,
1129         },
1130         [pbn_b0_2_115200] = {
1131                 .flags          = FL_BASE0,
1132                 .num_ports      = 2,
1133                 .base_baud      = 115200,
1134                 .uart_offset    = 8,
1135         },
1136         [pbn_b0_4_115200] = {
1137                 .flags          = FL_BASE0,
1138                 .num_ports      = 4,
1139                 .base_baud      = 115200,
1140                 .uart_offset    = 8,
1141         },
1142         [pbn_b0_5_115200] = {
1143                 .flags          = FL_BASE0,
1144                 .num_ports      = 5,
1145                 .base_baud      = 115200,
1146                 .uart_offset    = 8,
1147         },
1148
1149         [pbn_b0_1_921600] = {
1150                 .flags          = FL_BASE0,
1151                 .num_ports      = 1,
1152                 .base_baud      = 921600,
1153                 .uart_offset    = 8,
1154         },
1155         [pbn_b0_2_921600] = {
1156                 .flags          = FL_BASE0,
1157                 .num_ports      = 2,
1158                 .base_baud      = 921600,
1159                 .uart_offset    = 8,
1160         },
1161         [pbn_b0_4_921600] = {
1162                 .flags          = FL_BASE0,
1163                 .num_ports      = 4,
1164                 .base_baud      = 921600,
1165                 .uart_offset    = 8,
1166         },
1167         [pbn_b0_4_1152000] = {
1168                 .flags          = FL_BASE0,
1169                 .num_ports      = 4,
1170                 .base_baud      = 1152000,
1171                 .uart_offset    = 8,
1172         },
1173
1174         [pbn_b0_bt_1_115200] = {
1175                 .flags          = FL_BASE0|FL_BASE_BARS,
1176                 .num_ports      = 1,
1177                 .base_baud      = 115200,
1178                 .uart_offset    = 8,
1179         },
1180         [pbn_b0_bt_2_115200] = {
1181                 .flags          = FL_BASE0|FL_BASE_BARS,
1182                 .num_ports      = 2,
1183                 .base_baud      = 115200,
1184                 .uart_offset    = 8,
1185         },
1186         [pbn_b0_bt_8_115200] = {
1187                 .flags          = FL_BASE0|FL_BASE_BARS,
1188                 .num_ports      = 8,
1189                 .base_baud      = 115200,
1190                 .uart_offset    = 8,
1191         },
1192
1193         [pbn_b0_bt_1_460800] = {
1194                 .flags          = FL_BASE0|FL_BASE_BARS,
1195                 .num_ports      = 1,
1196                 .base_baud      = 460800,
1197                 .uart_offset    = 8,
1198         },
1199         [pbn_b0_bt_2_460800] = {
1200                 .flags          = FL_BASE0|FL_BASE_BARS,
1201                 .num_ports      = 2,
1202                 .base_baud      = 460800,
1203                 .uart_offset    = 8,
1204         },
1205         [pbn_b0_bt_4_460800] = {
1206                 .flags          = FL_BASE0|FL_BASE_BARS,
1207                 .num_ports      = 4,
1208                 .base_baud      = 460800,
1209                 .uart_offset    = 8,
1210         },
1211
1212         [pbn_b0_bt_1_921600] = {
1213                 .flags          = FL_BASE0|FL_BASE_BARS,
1214                 .num_ports      = 1,
1215                 .base_baud      = 921600,
1216                 .uart_offset    = 8,
1217         },
1218         [pbn_b0_bt_2_921600] = {
1219                 .flags          = FL_BASE0|FL_BASE_BARS,
1220                 .num_ports      = 2,
1221                 .base_baud      = 921600,
1222                 .uart_offset    = 8,
1223         },
1224         [pbn_b0_bt_4_921600] = {
1225                 .flags          = FL_BASE0|FL_BASE_BARS,
1226                 .num_ports      = 4,
1227                 .base_baud      = 921600,
1228                 .uart_offset    = 8,
1229         },
1230         [pbn_b0_bt_8_921600] = {
1231                 .flags          = FL_BASE0|FL_BASE_BARS,
1232                 .num_ports      = 8,
1233                 .base_baud      = 921600,
1234                 .uart_offset    = 8,
1235         },
1236
1237         [pbn_b1_1_115200] = {
1238                 .flags          = FL_BASE1,
1239                 .num_ports      = 1,
1240                 .base_baud      = 115200,
1241                 .uart_offset    = 8,
1242         },
1243         [pbn_b1_2_115200] = {
1244                 .flags          = FL_BASE1,
1245                 .num_ports      = 2,
1246                 .base_baud      = 115200,
1247                 .uart_offset    = 8,
1248         },
1249         [pbn_b1_4_115200] = {
1250                 .flags          = FL_BASE1,
1251                 .num_ports      = 4,
1252                 .base_baud      = 115200,
1253                 .uart_offset    = 8,
1254         },
1255         [pbn_b1_8_115200] = {
1256                 .flags          = FL_BASE1,
1257                 .num_ports      = 8,
1258                 .base_baud      = 115200,
1259                 .uart_offset    = 8,
1260         },
1261
1262         [pbn_b1_1_921600] = {
1263                 .flags          = FL_BASE1,
1264                 .num_ports      = 1,
1265                 .base_baud      = 921600,
1266                 .uart_offset    = 8,
1267         },
1268         [pbn_b1_2_921600] = {
1269                 .flags          = FL_BASE1,
1270                 .num_ports      = 2,
1271                 .base_baud      = 921600,
1272                 .uart_offset    = 8,
1273         },
1274         [pbn_b1_4_921600] = {
1275                 .flags          = FL_BASE1,
1276                 .num_ports      = 4,
1277                 .base_baud      = 921600,
1278                 .uart_offset    = 8,
1279         },
1280         [pbn_b1_8_921600] = {
1281                 .flags          = FL_BASE1,
1282                 .num_ports      = 8,
1283                 .base_baud      = 921600,
1284                 .uart_offset    = 8,
1285         },
1286
1287         [pbn_b1_bt_2_921600] = {
1288                 .flags          = FL_BASE1|FL_BASE_BARS,
1289                 .num_ports      = 2,
1290                 .base_baud      = 921600,
1291                 .uart_offset    = 8,
1292         },
1293
1294         [pbn_b1_1_1382400] = {
1295                 .flags          = FL_BASE1,
1296                 .num_ports      = 1,
1297                 .base_baud      = 1382400,
1298                 .uart_offset    = 8,
1299         },
1300         [pbn_b1_2_1382400] = {
1301                 .flags          = FL_BASE1,
1302                 .num_ports      = 2,
1303                 .base_baud      = 1382400,
1304                 .uart_offset    = 8,
1305         },
1306         [pbn_b1_4_1382400] = {
1307                 .flags          = FL_BASE1,
1308                 .num_ports      = 4,
1309                 .base_baud      = 1382400,
1310                 .uart_offset    = 8,
1311         },
1312         [pbn_b1_8_1382400] = {
1313                 .flags          = FL_BASE1,
1314                 .num_ports      = 8,
1315                 .base_baud      = 1382400,
1316                 .uart_offset    = 8,
1317         },
1318
1319         [pbn_b2_1_115200] = {
1320                 .flags          = FL_BASE2,
1321                 .num_ports      = 1,
1322                 .base_baud      = 115200,
1323                 .uart_offset    = 8,
1324         },
1325         [pbn_b2_8_115200] = {
1326                 .flags          = FL_BASE2,
1327                 .num_ports      = 8,
1328                 .base_baud      = 115200,
1329                 .uart_offset    = 8,
1330         },
1331
1332         [pbn_b2_1_460800] = {
1333                 .flags          = FL_BASE2,
1334                 .num_ports      = 1,
1335                 .base_baud      = 460800,
1336                 .uart_offset    = 8,
1337         },
1338         [pbn_b2_4_460800] = {
1339                 .flags          = FL_BASE2,
1340                 .num_ports      = 4,
1341                 .base_baud      = 460800,
1342                 .uart_offset    = 8,
1343         },
1344         [pbn_b2_8_460800] = {
1345                 .flags          = FL_BASE2,
1346                 .num_ports      = 8,
1347                 .base_baud      = 460800,
1348                 .uart_offset    = 8,
1349         },
1350         [pbn_b2_16_460800] = {
1351                 .flags          = FL_BASE2,
1352                 .num_ports      = 16,
1353                 .base_baud      = 460800,
1354                 .uart_offset    = 8,
1355          },
1356
1357         [pbn_b2_1_921600] = {
1358                 .flags          = FL_BASE2,
1359                 .num_ports      = 1,
1360                 .base_baud      = 921600,
1361                 .uart_offset    = 8,
1362         },
1363         [pbn_b2_4_921600] = {
1364                 .flags          = FL_BASE2,
1365                 .num_ports      = 4,
1366                 .base_baud      = 921600,
1367                 .uart_offset    = 8,
1368         },
1369         [pbn_b2_8_921600] = {
1370                 .flags          = FL_BASE2,
1371                 .num_ports      = 8,
1372                 .base_baud      = 921600,
1373                 .uart_offset    = 8,
1374         },
1375
1376         [pbn_b2_bt_1_115200] = {
1377                 .flags          = FL_BASE2|FL_BASE_BARS,
1378                 .num_ports      = 1,
1379                 .base_baud      = 115200,
1380                 .uart_offset    = 8,
1381         },
1382         [pbn_b2_bt_2_115200] = {
1383                 .flags          = FL_BASE2|FL_BASE_BARS,
1384                 .num_ports      = 2,
1385                 .base_baud      = 115200,
1386                 .uart_offset    = 8,
1387         },
1388         [pbn_b2_bt_4_115200] = {
1389                 .flags          = FL_BASE2|FL_BASE_BARS,
1390                 .num_ports      = 4,
1391                 .base_baud      = 115200,
1392                 .uart_offset    = 8,
1393         },
1394
1395         [pbn_b2_bt_2_921600] = {
1396                 .flags          = FL_BASE2|FL_BASE_BARS,
1397                 .num_ports      = 2,
1398                 .base_baud      = 921600,
1399                 .uart_offset    = 8,
1400         },
1401         [pbn_b2_bt_4_921600] = {
1402                 .flags          = FL_BASE2|FL_BASE_BARS,
1403                 .num_ports      = 4,
1404                 .base_baud      = 921600,
1405                 .uart_offset    = 8,
1406         },
1407
1408         [pbn_b3_4_115200] = {
1409                 .flags          = FL_BASE3,
1410                 .num_ports      = 4,
1411                 .base_baud      = 115200,
1412                 .uart_offset    = 8,
1413         },
1414         [pbn_b3_8_115200] = {
1415                 .flags          = FL_BASE3,
1416                 .num_ports      = 8,
1417                 .base_baud      = 115200,
1418                 .uart_offset    = 8,
1419         },
1420
1421         /*
1422          * Entries following this are board-specific.
1423          */
1424
1425         /*
1426          * Panacom - IOMEM
1427          */
1428         [pbn_panacom] = {
1429                 .flags          = FL_BASE2,
1430                 .num_ports      = 2,
1431                 .base_baud      = 921600,
1432                 .uart_offset    = 0x400,
1433                 .reg_shift      = 7,
1434         },
1435         [pbn_panacom2] = {
1436                 .flags          = FL_BASE2|FL_BASE_BARS,
1437                 .num_ports      = 2,
1438                 .base_baud      = 921600,
1439                 .uart_offset    = 0x400,
1440                 .reg_shift      = 7,
1441         },
1442         [pbn_panacom4] = {
1443                 .flags          = FL_BASE2|FL_BASE_BARS,
1444                 .num_ports      = 4,
1445                 .base_baud      = 921600,
1446                 .uart_offset    = 0x400,
1447                 .reg_shift      = 7,
1448         },
1449
1450         /* I think this entry is broken - the first_offset looks wrong --rmk */
1451         [pbn_plx_romulus] = {
1452                 .flags          = FL_BASE2,
1453                 .num_ports      = 4,
1454                 .base_baud      = 921600,
1455                 .uart_offset    = 8 << 2,
1456                 .reg_shift      = 2,
1457                 .first_offset   = 0x03,
1458         },
1459
1460         /*
1461          * This board uses the size of PCI Base region 0 to
1462          * signal now many ports are available
1463          */
1464         [pbn_oxsemi] = {
1465                 .flags          = FL_BASE0|FL_REGION_SZ_CAP,
1466                 .num_ports      = 32,
1467                 .base_baud      = 115200,
1468                 .uart_offset    = 8,
1469         },
1470
1471         /*
1472          * EKF addition for i960 Boards form EKF with serial port.
1473          * Max 256 ports.
1474          */
1475         [pbn_intel_i960] = {
1476                 .flags          = FL_BASE0,
1477                 .num_ports      = 32,
1478                 .base_baud      = 921600,
1479                 .uart_offset    = 8 << 2,
1480                 .reg_shift      = 2,
1481                 .first_offset   = 0x10000,
1482         },
1483         [pbn_sgi_ioc3] = {
1484                 .flags          = FL_BASE0|FL_NOIRQ,
1485                 .num_ports      = 1,
1486                 .base_baud      = 458333,
1487                 .uart_offset    = 8,
1488                 .reg_shift      = 0,
1489                 .first_offset   = 0x20178,
1490         },
1491
1492         /*
1493          * NEC Vrc-5074 (Nile 4) builtin UART.
1494          */
1495         [pbn_nec_nile4] = {
1496                 .flags          = FL_BASE0,
1497                 .num_ports      = 1,
1498                 .base_baud      = 520833,
1499                 .uart_offset    = 8 << 3,
1500                 .reg_shift      = 3,
1501                 .first_offset   = 0x300,
1502         },
1503
1504         /*
1505          * Computone - uses IOMEM.
1506          */
1507         [pbn_computone_4] = {
1508                 .flags          = FL_BASE0,
1509                 .num_ports      = 4,
1510                 .base_baud      = 921600,
1511                 .uart_offset    = 0x40,
1512                 .reg_shift      = 2,
1513                 .first_offset   = 0x200,
1514         },
1515         [pbn_computone_6] = {
1516                 .flags          = FL_BASE0,
1517                 .num_ports      = 6,
1518                 .base_baud      = 921600,
1519                 .uart_offset    = 0x40,
1520                 .reg_shift      = 2,
1521                 .first_offset   = 0x200,
1522         },
1523         [pbn_computone_8] = {
1524                 .flags          = FL_BASE0,
1525                 .num_ports      = 8,
1526                 .base_baud      = 921600,
1527                 .uart_offset    = 0x40,
1528                 .reg_shift      = 2,
1529                 .first_offset   = 0x200,
1530         },
1531         [pbn_sbsxrsio] = {
1532                 .flags          = FL_BASE0,
1533                 .num_ports      = 8,
1534                 .base_baud      = 460800,
1535                 .uart_offset    = 256,
1536                 .reg_shift      = 4,
1537         },
1538         /*
1539          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
1540          *  Only basic 16550A support.
1541          *  XR17C15[24] are not tested, but they should work.
1542          */
1543         [pbn_exar_XR17C152] = {
1544                 .flags          = FL_BASE0,
1545                 .num_ports      = 2,
1546                 .base_baud      = 921600,
1547                 .uart_offset    = 0x200,
1548         },
1549         [pbn_exar_XR17C154] = {
1550                 .flags          = FL_BASE0,
1551                 .num_ports      = 4,
1552                 .base_baud      = 921600,
1553                 .uart_offset    = 0x200,
1554         },
1555         [pbn_exar_XR17C158] = {
1556                 .flags          = FL_BASE0,
1557                 .num_ports      = 8,
1558                 .base_baud      = 921600,
1559                 .uart_offset    = 0x200,
1560         },
1561 };
1562
1563 /*
1564  * Given a complete unknown PCI device, try to use some heuristics to
1565  * guess what the configuration might be, based on the pitiful PCI
1566  * serial specs.  Returns 0 on success, 1 on failure.
1567  */
1568 static int __devinit
1569 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
1570 {
1571         int num_iomem, num_port, first_port = -1, i;
1572
1573         /*
1574          * If it is not a communications device or the programming
1575          * interface is greater than 6, give up.
1576          *
1577          * (Should we try to make guesses for multiport serial devices
1578          * later?)
1579          */
1580         if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
1581              ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
1582             (dev->class & 0xff) > 6)
1583                 return -ENODEV;
1584
1585         num_iomem = num_port = 0;
1586         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1587                 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
1588                         num_port++;
1589                         if (first_port == -1)
1590                                 first_port = i;
1591                 }
1592                 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
1593                         num_iomem++;
1594         }
1595
1596         /*
1597          * If there is 1 or 0 iomem regions, and exactly one port,
1598          * use it.  We guess the number of ports based on the IO
1599          * region size.
1600          */
1601         if (num_iomem <= 1 && num_port == 1) {
1602                 board->flags = first_port;
1603                 board->num_ports = pci_resource_len(dev, first_port) / 8;
1604                 return 0;
1605         }
1606
1607         /*
1608          * Now guess if we've got a board which indexes by BARs.
1609          * Each IO BAR should be 8 bytes, and they should follow
1610          * consecutively.
1611          */
1612         first_port = -1;
1613         num_port = 0;
1614         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1615                 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
1616                     pci_resource_len(dev, i) == 8 &&
1617                     (first_port == -1 || (first_port + num_port) == i)) {
1618                         num_port++;
1619                         if (first_port == -1)
1620                                 first_port = i;
1621                 }
1622         }
1623
1624         if (num_port > 1) {
1625                 board->flags = first_port | FL_BASE_BARS;
1626                 board->num_ports = num_port;
1627                 return 0;
1628         }
1629
1630         return -ENODEV;
1631 }
1632
1633 static inline int
1634 serial_pci_matches(struct pciserial_board *board,
1635                    struct pciserial_board *guessed)
1636 {
1637         return
1638             board->num_ports == guessed->num_ports &&
1639             board->base_baud == guessed->base_baud &&
1640             board->uart_offset == guessed->uart_offset &&
1641             board->reg_shift == guessed->reg_shift &&
1642             board->first_offset == guessed->first_offset;
1643 }
1644
1645 /*
1646  * Probe one serial board.  Unfortunately, there is no rhyme nor reason
1647  * to the arrangement of serial ports on a PCI card.
1648  */
1649 static int __devinit
1650 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
1651 {
1652         struct serial_private *priv;
1653         struct pciserial_board *board, tmp;
1654         struct pci_serial_quirk *quirk;
1655         int rc, nr_ports, i;
1656
1657         if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
1658                 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
1659                         ent->driver_data);
1660                 return -EINVAL;
1661         }
1662
1663         board = &pci_boards[ent->driver_data];
1664
1665         rc = pci_enable_device(dev);
1666         if (rc)
1667                 return rc;
1668
1669         if (ent->driver_data == pbn_default) {
1670                 /*
1671                  * Use a copy of the pci_board entry for this;
1672                  * avoid changing entries in the table.
1673                  */
1674                 memcpy(&tmp, board, sizeof(struct pciserial_board));
1675                 board = &tmp;
1676
1677                 /*
1678                  * We matched one of our class entries.  Try to
1679                  * determine the parameters of this board.
1680                  */
1681                 rc = serial_pci_guess_board(dev, board);
1682                 if (rc)
1683                         goto disable;
1684         } else {
1685                 /*
1686                  * We matched an explicit entry.  If we are able to
1687                  * detect this boards settings with our heuristic,
1688                  * then we no longer need this entry.
1689                  */
1690                 memcpy(&tmp, &pci_boards[pbn_default],
1691                        sizeof(struct pciserial_board));
1692                 rc = serial_pci_guess_board(dev, &tmp);
1693                 if (rc == 0 && serial_pci_matches(board, &tmp))
1694                         moan_device("Redundant entry in serial pci_table.",
1695                                     dev);
1696         }
1697
1698         nr_ports = board->num_ports;
1699
1700         /*
1701          * Find an init and setup quirks.
1702          */
1703         quirk = find_quirk(dev);
1704
1705         /*
1706          * Run the new-style initialization function.
1707          * The initialization function returns:
1708          *  <0  - error
1709          *   0  - use board->num_ports
1710          *  >0  - number of ports
1711          */
1712         if (quirk->init) {
1713                 rc = quirk->init(dev);
1714                 if (rc < 0)
1715                         goto disable;
1716                 if (rc)
1717                         nr_ports = rc;
1718         }
1719
1720         priv = kmalloc(sizeof(struct serial_private) +
1721                        sizeof(unsigned int) * nr_ports,
1722                        GFP_KERNEL);
1723         if (!priv) {
1724                 rc = -ENOMEM;
1725                 goto deinit;
1726         }
1727
1728         memset(priv, 0, sizeof(struct serial_private) +
1729                         sizeof(unsigned int) * nr_ports);
1730
1731         priv->quirk = quirk;
1732         pci_set_drvdata(dev, priv);
1733
1734         for (i = 0; i < nr_ports; i++) {
1735                 struct uart_port serial_port;
1736                 memset(&serial_port, 0, sizeof(struct uart_port));
1737
1738                 serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF |
1739                                     UPF_SHARE_IRQ;
1740                 serial_port.uartclk = board->base_baud * 16;
1741                 serial_port.irq = get_pci_irq(dev, board, i);
1742                 serial_port.dev = &dev->dev;
1743                 if (quirk->setup(dev, board, &serial_port, i))
1744                         break;
1745 #ifdef SERIAL_DEBUG_PCI
1746                 printk("Setup PCI port: port %x, irq %d, type %d\n",
1747                        serial_port.iobase, serial_port.irq, serial_port.iotype);
1748 #endif
1749
1750                 priv->line[i] = serial8250_register_port(&serial_port);
1751                 if (priv->line[i] < 0) {
1752                         printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
1753                         break;
1754                 }
1755         }
1756
1757         priv->nr = i;
1758
1759         return 0;
1760
1761  deinit:
1762         if (quirk->exit)
1763                 quirk->exit(dev);
1764  disable:
1765         pci_disable_device(dev);
1766         return rc;
1767 }
1768
1769 static void __devexit pciserial_remove_one(struct pci_dev *dev)
1770 {
1771         struct serial_private *priv = pci_get_drvdata(dev);
1772         struct pci_serial_quirk *quirk;
1773         int i;
1774
1775         pci_set_drvdata(dev, NULL);
1776
1777         for (i = 0; i < priv->nr; i++)
1778                 serial8250_unregister_port(priv->line[i]);
1779
1780         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1781                 if (priv->remapped_bar[i])
1782                         iounmap(priv->remapped_bar[i]);
1783                 priv->remapped_bar[i] = NULL;
1784         }
1785
1786         /*
1787          * Find the exit quirks.
1788          */
1789         quirk = find_quirk(dev);
1790         if (quirk->exit)
1791                 quirk->exit(dev);
1792
1793         pci_disable_device(dev);
1794
1795         kfree(priv);
1796 }
1797
1798 static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
1799 {
1800         struct serial_private *priv = pci_get_drvdata(dev);
1801
1802         if (priv) {
1803                 int i;
1804
1805                 for (i = 0; i < priv->nr; i++)
1806                         serial8250_suspend_port(priv->line[i]);
1807         }
1808         pci_save_state(dev);
1809         pci_set_power_state(dev, pci_choose_state(dev, state));
1810         return 0;
1811 }
1812
1813 static int pciserial_resume_one(struct pci_dev *dev)
1814 {
1815         struct serial_private *priv = pci_get_drvdata(dev);
1816
1817         pci_set_power_state(dev, PCI_D0);
1818         pci_restore_state(dev);
1819
1820         if (priv) {
1821                 int i;
1822
1823                 /*
1824                  * The device may have been disabled.  Re-enable it.
1825                  */
1826                 pci_enable_device(dev);
1827
1828                 /*
1829                  * Ensure that the board is correctly configured.
1830                  */
1831                 if (priv->quirk->init)
1832                         priv->quirk->init(dev);
1833
1834                 for (i = 0; i < priv->nr; i++)
1835                         serial8250_resume_port(priv->line[i]);
1836         }
1837         return 0;
1838 }
1839
1840 static struct pci_device_id serial_pci_tbl[] = {
1841         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1842                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1843                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
1844                 pbn_b1_8_1382400 },
1845         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1846                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1847                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
1848                 pbn_b1_4_1382400 },
1849         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1850                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1851                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
1852                 pbn_b1_2_1382400 },
1853         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1854                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1855                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
1856                 pbn_b1_8_1382400 },
1857         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1858                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1859                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
1860                 pbn_b1_4_1382400 },
1861         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1862                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1863                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
1864                 pbn_b1_2_1382400 },
1865         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1866                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1867                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
1868                 pbn_b1_8_921600 },
1869         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1870                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1871                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
1872                 pbn_b1_8_921600 },
1873         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1874                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1875                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
1876                 pbn_b1_4_921600 },
1877         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1878                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1879                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
1880                 pbn_b1_4_921600 },
1881         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1882                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1883                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
1884                 pbn_b1_2_921600 },
1885         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1886                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1887                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
1888                 pbn_b1_8_921600 },
1889         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1890                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1891                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
1892                 pbn_b1_8_921600 },
1893         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1894                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1895                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
1896                 pbn_b1_4_921600 },
1897
1898         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
1899                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1900                 pbn_b2_bt_1_115200 },
1901         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
1902                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1903                 pbn_b2_bt_2_115200 },
1904         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
1905                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1906                 pbn_b2_bt_4_115200 },
1907         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
1908                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1909                 pbn_b2_bt_2_115200 },
1910         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
1911                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1912                 pbn_b2_bt_4_115200 },
1913         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
1914                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1915                 pbn_b2_8_115200 },
1916         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
1917                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1918                 pbn_b2_8_115200 },
1919
1920         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
1921                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1922                 pbn_b2_bt_2_115200 },
1923         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
1924                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1925                 pbn_b2_bt_2_921600 },
1926         /*
1927          * VScom SPCOM800, from sl@s.pl
1928          */
1929         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
1930                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1931                 pbn_b2_8_921600 },
1932         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
1933                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1934                 pbn_b2_4_921600 },
1935         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1936                 PCI_SUBVENDOR_ID_KEYSPAN,
1937                 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
1938                 pbn_panacom },
1939         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
1940                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1941                 pbn_panacom4 },
1942         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
1943                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1944                 pbn_panacom2 },
1945         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1946                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1947                 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
1948                 pbn_b2_4_460800 },
1949         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1950                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1951                 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
1952                 pbn_b2_8_460800 },
1953         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1954                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1955                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
1956                 pbn_b2_16_460800 },
1957         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1958                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1959                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
1960                 pbn_b2_16_460800 },
1961         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1962                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
1963                 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
1964                 pbn_b2_4_460800 },
1965         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1966                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
1967                 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
1968                 pbn_b2_8_460800 },
1969         /*
1970          * Megawolf Romulus PCI Serial Card, from Mike Hudson
1971          * (Exoray@isys.ca)
1972          */
1973         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
1974                 0x10b5, 0x106a, 0, 0,
1975                 pbn_plx_romulus },
1976         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
1977                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1978                 pbn_b1_4_115200 },
1979         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
1980                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1981                 pbn_b1_2_115200 },
1982         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
1983                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1984                 pbn_b1_8_115200 },
1985         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
1986                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1987                 pbn_b1_8_115200 },
1988         {       PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
1989                 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4, 0, 0,
1990                 pbn_b0_4_921600 },
1991         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
1992                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL, 0, 0,
1993                 pbn_b0_4_1152000 },
1994         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
1995                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1996                 pbn_b0_4_115200 },
1997         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
1998                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1999                 pbn_b0_bt_2_921600 },
2000
2001         /*
2002          * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
2003          * from skokodyn@yahoo.com
2004          */
2005         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2006                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
2007                 pbn_sbsxrsio },
2008         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2009                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
2010                 pbn_sbsxrsio },
2011         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2012                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
2013                 pbn_sbsxrsio },
2014         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2015                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
2016                 pbn_sbsxrsio },
2017
2018         /*
2019          * Digitan DS560-558, from jimd@esoft.com
2020          */
2021         {       PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
2022                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2023                 pbn_b1_1_115200 },
2024
2025         /*
2026          * Titan Electronic cards
2027          *  The 400L and 800L have a custom setup quirk.
2028          */
2029         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
2030                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2031                 pbn_b0_1_921600 },
2032         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
2033                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2034                 pbn_b0_2_921600 },
2035         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
2036                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2037                 pbn_b0_4_921600 },
2038         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
2039                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2040                 pbn_b0_4_921600 },
2041         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
2042                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2043                 pbn_b1_1_921600 },
2044         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
2045                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2046                 pbn_b1_bt_2_921600 },
2047         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
2048                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2049                 pbn_b0_bt_4_921600 },
2050         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
2051                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2052                 pbn_b0_bt_8_921600 },
2053
2054         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
2055                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2056                 pbn_b2_1_460800 },
2057         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
2058                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2059                 pbn_b2_1_460800 },
2060         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
2061                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2062                 pbn_b2_1_460800 },
2063         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
2064                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2065                 pbn_b2_bt_2_921600 },
2066         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
2067                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2068                 pbn_b2_bt_2_921600 },
2069         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
2070                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2071                 pbn_b2_bt_2_921600 },
2072         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
2073                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2074                 pbn_b2_bt_4_921600 },
2075         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
2076                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2077                 pbn_b2_bt_4_921600 },
2078         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
2079                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2080                 pbn_b2_bt_4_921600 },
2081         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
2082                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2083                 pbn_b0_1_921600 },
2084         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
2085                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2086                 pbn_b0_1_921600 },
2087         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
2088                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2089                 pbn_b0_1_921600 },
2090         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
2091                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2092                 pbn_b0_bt_2_921600 },
2093         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
2094                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2095                 pbn_b0_bt_2_921600 },
2096         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
2097                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2098                 pbn_b0_bt_2_921600 },
2099         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
2100                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2101                 pbn_b0_bt_4_921600 },
2102         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
2103                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2104                 pbn_b0_bt_4_921600 },
2105         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
2106                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2107                 pbn_b0_bt_4_921600 },
2108
2109         /*
2110          * Computone devices submitted by Doug McNash dmcnash@computone.com
2111          */
2112         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2113                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
2114                 0, 0, pbn_computone_4 },
2115         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2116                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
2117                 0, 0, pbn_computone_8 },
2118         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2119                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
2120                 0, 0, pbn_computone_6 },
2121
2122         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
2123                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2124                 pbn_oxsemi },
2125         {       PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
2126                 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
2127                 pbn_b0_bt_1_921600 },
2128
2129         /*
2130          * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
2131          */
2132         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
2133                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2134                 pbn_b0_bt_8_115200 },
2135         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
2136                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2137                 pbn_b0_bt_8_115200 },
2138
2139         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
2140                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2141                 pbn_b0_bt_2_115200 },
2142         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
2143                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2144                 pbn_b0_bt_2_115200 },
2145         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
2146                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2147                 pbn_b0_bt_2_115200 },
2148         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
2149                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2150                 pbn_b0_bt_4_460800 },
2151         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
2152                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2153                 pbn_b0_bt_4_460800 },
2154         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
2155                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2156                 pbn_b0_bt_2_460800 },
2157         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
2158                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2159                 pbn_b0_bt_2_460800 },
2160         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
2161                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2162                 pbn_b0_bt_2_460800 },
2163         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
2164                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2165                 pbn_b0_bt_1_115200 },
2166         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
2167                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2168                 pbn_b0_bt_1_460800 },
2169
2170         /*
2171          * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
2172          */
2173         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
2174                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2175                 pbn_b1_1_1382400 },
2176
2177         /*
2178          * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
2179          */
2180         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
2181                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2182                 pbn_b1_1_1382400 },
2183
2184         /*
2185          * RAStel 2 port modem, gerg@moreton.com.au
2186          */
2187         {       PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
2188                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2189                 pbn_b2_bt_2_115200 },
2190
2191         /*
2192          * EKF addition for i960 Boards form EKF with serial port
2193          */
2194         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
2195                 0xE4BF, PCI_ANY_ID, 0, 0,
2196                 pbn_intel_i960 },
2197
2198         /*
2199          * Xircom Cardbus/Ethernet combos
2200          */
2201         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2202                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2203                 pbn_b0_1_115200 },
2204         /*
2205          * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
2206          */
2207         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
2208                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2209                 pbn_b0_1_115200 },
2210
2211         /*
2212          * Untested PCI modems, sent in from various folks...
2213          */
2214
2215         /*
2216          * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
2217          */
2218         {       PCI_VENDOR_ID_ROCKWELL, 0x1004,
2219                 0x1048, 0x1500, 0, 0,
2220                 pbn_b1_1_115200 },
2221
2222         {       PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
2223                 0xFF00, 0, 0, 0,
2224                 pbn_sgi_ioc3 },
2225
2226         /*
2227          * HP Diva card
2228          */
2229         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
2230                 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
2231                 pbn_b1_1_115200 },
2232         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
2233                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2234                 pbn_b0_5_115200 },
2235         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
2236                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2237                 pbn_b2_1_115200 },
2238
2239         /*
2240          * NEC Vrc-5074 (Nile 4) builtin UART.
2241          */
2242         {       PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_NILE4,
2243                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2244                 pbn_nec_nile4 },
2245
2246         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
2247                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2248                 pbn_b3_4_115200 },
2249         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
2250                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2251                 pbn_b3_8_115200 },
2252
2253         /*
2254          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2255          */
2256         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2257                 PCI_ANY_ID, PCI_ANY_ID,
2258                 0,
2259                 0, pbn_exar_XR17C152 },
2260         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2261                 PCI_ANY_ID, PCI_ANY_ID,
2262                 0,
2263                 0, pbn_exar_XR17C154 },
2264         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2265                 PCI_ANY_ID, PCI_ANY_ID,
2266                 0,
2267                 0, pbn_exar_XR17C158 },
2268
2269         /*
2270          * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
2271          */
2272         {       PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
2273                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2274                 pbn_b0_1_115200 },
2275
2276         /*
2277          * These entries match devices with class COMMUNICATION_SERIAL,
2278          * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
2279          */
2280         {       PCI_ANY_ID, PCI_ANY_ID,
2281                 PCI_ANY_ID, PCI_ANY_ID,
2282                 PCI_CLASS_COMMUNICATION_SERIAL << 8,
2283                 0xffff00, pbn_default },
2284         {       PCI_ANY_ID, PCI_ANY_ID,
2285                 PCI_ANY_ID, PCI_ANY_ID,
2286                 PCI_CLASS_COMMUNICATION_MODEM << 8,
2287                 0xffff00, pbn_default },
2288         {       PCI_ANY_ID, PCI_ANY_ID,
2289                 PCI_ANY_ID, PCI_ANY_ID,
2290                 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
2291                 0xffff00, pbn_default },
2292         { 0, }
2293 };
2294
2295 static struct pci_driver serial_pci_driver = {
2296         .name           = "serial",
2297         .probe          = pciserial_init_one,
2298         .remove         = __devexit_p(pciserial_remove_one),
2299         .suspend        = pciserial_suspend_one,
2300         .resume         = pciserial_resume_one,
2301         .id_table       = serial_pci_tbl,
2302 };
2303
2304 static int __init serial8250_pci_init(void)
2305 {
2306         return pci_register_driver(&serial_pci_driver);
2307 }
2308
2309 static void __exit serial8250_pci_exit(void)
2310 {
2311         pci_unregister_driver(&serial_pci_driver);
2312 }
2313
2314 module_init(serial8250_pci_init);
2315 module_exit(serial8250_pci_exit);
2316
2317 MODULE_LICENSE("GPL");
2318 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
2319 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);