2 * linux/drivers/char/8250_pci.c
4 * Probe module for 8250/16550-type PCI serial ports.
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
8 * Copyright (C) 2001 Russell King, All Rights Reserved.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
14 #include <linux/module.h>
15 #include <linux/init.h>
16 #include <linux/pci.h>
17 #include <linux/string.h>
18 #include <linux/kernel.h>
19 #include <linux/slab.h>
20 #include <linux/delay.h>
21 #include <linux/tty.h>
22 #include <linux/serial_core.h>
23 #include <linux/8250_pci.h>
24 #include <linux/bitops.h>
26 #include <asm/byteorder.h>
31 #undef SERIAL_DEBUG_PCI
34 * init function returns:
35 * > 0 - number of ports
36 * = 0 - use board->num_ports
39 struct pci_serial_quirk {
44 int (*init)(struct pci_dev *dev);
45 int (*setup)(struct serial_private *, struct pciserial_board *,
46 struct uart_port *, int);
47 void (*exit)(struct pci_dev *dev);
50 #define PCI_NUM_BAR_RESOURCES 6
52 struct serial_private {
55 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
56 struct pci_serial_quirk *quirk;
60 static void moan_device(const char *str, struct pci_dev *dev)
62 printk(KERN_WARNING "%s: %s\n"
63 KERN_WARNING "Please send the output of lspci -vv, this\n"
64 KERN_WARNING "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
65 KERN_WARNING "manufacturer and name of serial board or\n"
66 KERN_WARNING "modem board to rmk+serial@arm.linux.org.uk.\n",
67 pci_name(dev), str, dev->vendor, dev->device,
68 dev->subsystem_vendor, dev->subsystem_device);
72 setup_port(struct serial_private *priv, struct uart_port *port,
73 int bar, int offset, int regshift)
75 struct pci_dev *dev = priv->dev;
76 unsigned long base, len;
78 if (bar >= PCI_NUM_BAR_RESOURCES)
81 base = pci_resource_start(dev, bar);
83 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
84 len = pci_resource_len(dev, bar);
86 if (!priv->remapped_bar[bar])
87 priv->remapped_bar[bar] = ioremap_nocache(base, len);
88 if (!priv->remapped_bar[bar])
91 port->iotype = UPIO_MEM;
93 port->mapbase = base + offset;
94 port->membase = priv->remapped_bar[bar] + offset;
95 port->regshift = regshift;
97 port->iotype = UPIO_PORT;
98 port->iobase = base + offset;
100 port->membase = NULL;
107 * ADDI-DATA GmbH communication cards <info@addi-data.com>
109 static int addidata_apci7800_setup(struct serial_private *priv,
110 struct pciserial_board *board,
111 struct uart_port *port, int idx)
113 unsigned int bar = 0, offset = board->first_offset;
114 bar = FL_GET_BASE(board->flags);
117 offset += idx * board->uart_offset;
118 } else if ((idx >= 2) && (idx < 4)) {
120 offset += ((idx - 2) * board->uart_offset);
121 } else if ((idx >= 4) && (idx < 6)) {
123 offset += ((idx - 4) * board->uart_offset);
124 } else if (idx >= 6) {
126 offset += ((idx - 6) * board->uart_offset);
129 return setup_port(priv, port, bar, offset, board->reg_shift);
133 * AFAVLAB uses a different mixture of BARs and offsets
134 * Not that ugly ;) -- HW
137 afavlab_setup(struct serial_private *priv, struct pciserial_board *board,
138 struct uart_port *port, int idx)
140 unsigned int bar, offset = board->first_offset;
142 bar = FL_GET_BASE(board->flags);
147 offset += (idx - 4) * board->uart_offset;
150 return setup_port(priv, port, bar, offset, board->reg_shift);
154 * HP's Remote Management Console. The Diva chip came in several
155 * different versions. N-class, L2000 and A500 have two Diva chips, each
156 * with 3 UARTs (the third UART on the second chip is unused). Superdome
157 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
158 * one Diva chip, but it has been expanded to 5 UARTs.
160 static int pci_hp_diva_init(struct pci_dev *dev)
164 switch (dev->subsystem_device) {
165 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
166 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
167 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
168 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
171 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
174 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
177 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
178 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
187 * HP's Diva chip puts the 4th/5th serial port further out, and
188 * some serial ports are supposed to be hidden on certain models.
191 pci_hp_diva_setup(struct serial_private *priv, struct pciserial_board *board,
192 struct uart_port *port, int idx)
194 unsigned int offset = board->first_offset;
195 unsigned int bar = FL_GET_BASE(board->flags);
197 switch (priv->dev->subsystem_device) {
198 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
202 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
212 offset += idx * board->uart_offset;
214 return setup_port(priv, port, bar, offset, board->reg_shift);
218 * Added for EKF Intel i960 serial boards
220 static int pci_inteli960ni_init(struct pci_dev *dev)
222 unsigned long oldval;
224 if (!(dev->subsystem_device & 0x1000))
227 /* is firmware started? */
228 pci_read_config_dword(dev, 0x44, (void *)&oldval);
229 if (oldval == 0x00001000L) { /* RESET value */
230 printk(KERN_DEBUG "Local i960 firmware missing");
237 * Some PCI serial cards using the PLX 9050 PCI interface chip require
238 * that the card interrupt be explicitly enabled or disabled. This
239 * seems to be mainly needed on card using the PLX which also use I/O
242 static int pci_plx9050_init(struct pci_dev *dev)
247 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
248 moan_device("no memory in bar 0", dev);
253 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
254 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
257 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
258 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
260 * As the megawolf cards have the int pins active
261 * high, and have 2 UART chips, both ints must be
262 * enabled on the 9050. Also, the UARTS are set in
263 * 16450 mode by default, so we have to enable the
264 * 16C950 'enhanced' mode so that we can use the
269 * enable/disable interrupts
271 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
274 writel(irq_config, p + 0x4c);
277 * Read the register back to ensure that it took effect.
285 static void __devexit pci_plx9050_exit(struct pci_dev *dev)
289 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
295 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
300 * Read the register back to ensure that it took effect.
307 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
309 sbs_setup(struct serial_private *priv, struct pciserial_board *board,
310 struct uart_port *port, int idx)
312 unsigned int bar, offset = board->first_offset;
317 /* first four channels map to 0, 0x100, 0x200, 0x300 */
318 offset += idx * board->uart_offset;
319 } else if (idx < 8) {
320 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
321 offset += idx * board->uart_offset + 0xC00;
322 } else /* we have only 8 ports on PMC-OCTALPRO */
325 return setup_port(priv, port, bar, offset, board->reg_shift);
329 * This does initialization for PMC OCTALPRO cards:
330 * maps the device memory, resets the UARTs (needed, bc
331 * if the module is removed and inserted again, the card
332 * is in the sleep mode) and enables global interrupt.
335 /* global control register offset for SBS PMC-OctalPro */
336 #define OCT_REG_CR_OFF 0x500
338 static int sbs_init(struct pci_dev *dev)
342 p = ioremap_nocache(pci_resource_start(dev, 0),
343 pci_resource_len(dev, 0));
347 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
348 writeb(0x10, p + OCT_REG_CR_OFF);
350 writeb(0x0, p + OCT_REG_CR_OFF);
352 /* Set bit-2 (INTENABLE) of Control Register */
353 writeb(0x4, p + OCT_REG_CR_OFF);
360 * Disables the global interrupt of PMC-OctalPro
363 static void __devexit sbs_exit(struct pci_dev *dev)
367 p = ioremap_nocache(pci_resource_start(dev, 0),
368 pci_resource_len(dev, 0));
369 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
371 writeb(0, p + OCT_REG_CR_OFF);
376 * SIIG serial cards have an PCI interface chip which also controls
377 * the UART clocking frequency. Each UART can be clocked independently
378 * (except cards equiped with 4 UARTs) and initial clocking settings
379 * are stored in the EEPROM chip. It can cause problems because this
380 * version of serial driver doesn't support differently clocked UART's
381 * on single PCI card. To prevent this, initialization functions set
382 * high frequency clocking for all UART's on given card. It is safe (I
383 * hope) because it doesn't touch EEPROM settings to prevent conflicts
384 * with other OSes (like M$ DOS).
386 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
388 * There is two family of SIIG serial cards with different PCI
389 * interface chip and different configuration methods:
390 * - 10x cards have control registers in IO and/or memory space;
391 * - 20x cards have control registers in standard PCI configuration space.
393 * Note: all 10x cards have PCI device ids 0x10..
394 * all 20x cards have PCI device ids 0x20..
396 * There are also Quartet Serial cards which use Oxford Semiconductor
397 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
399 * Note: some SIIG cards are probed by the parport_serial object.
402 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
403 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
405 static int pci_siig10x_init(struct pci_dev *dev)
410 switch (dev->device & 0xfff8) {
411 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
414 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
417 default: /* 1S1P, 4S */
422 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
426 writew(readw(p + 0x28) & data, p + 0x28);
432 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
433 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
435 static int pci_siig20x_init(struct pci_dev *dev)
439 /* Change clock frequency for the first UART. */
440 pci_read_config_byte(dev, 0x6f, &data);
441 pci_write_config_byte(dev, 0x6f, data & 0xef);
443 /* If this card has 2 UART, we have to do the same with second UART. */
444 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
445 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
446 pci_read_config_byte(dev, 0x73, &data);
447 pci_write_config_byte(dev, 0x73, data & 0xef);
452 static int pci_siig_init(struct pci_dev *dev)
454 unsigned int type = dev->device & 0xff00;
457 return pci_siig10x_init(dev);
458 else if (type == 0x2000)
459 return pci_siig20x_init(dev);
461 moan_device("Unknown SIIG card", dev);
465 static int pci_siig_setup(struct serial_private *priv,
466 struct pciserial_board *board,
467 struct uart_port *port, int idx)
469 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
473 offset = (idx - 4) * 8;
476 return setup_port(priv, port, bar, offset, 0);
480 * Timedia has an explosion of boards, and to avoid the PCI table from
481 * growing *huge*, we use this function to collapse some 70 entries
482 * in the PCI table into one, for sanity's and compactness's sake.
484 static const unsigned short timedia_single_port[] = {
485 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
488 static const unsigned short timedia_dual_port[] = {
489 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
490 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
491 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
492 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
496 static const unsigned short timedia_quad_port[] = {
497 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
498 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
499 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
503 static const unsigned short timedia_eight_port[] = {
504 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
505 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
508 static const struct timedia_struct {
510 const unsigned short *ids;
512 { 1, timedia_single_port },
513 { 2, timedia_dual_port },
514 { 4, timedia_quad_port },
515 { 8, timedia_eight_port }
518 static int pci_timedia_init(struct pci_dev *dev)
520 const unsigned short *ids;
523 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
524 ids = timedia_data[i].ids;
525 for (j = 0; ids[j]; j++)
526 if (dev->subsystem_device == ids[j])
527 return timedia_data[i].num;
533 * Timedia/SUNIX uses a mixture of BARs and offsets
534 * Ugh, this is ugly as all hell --- TYT
537 pci_timedia_setup(struct serial_private *priv, struct pciserial_board *board,
538 struct uart_port *port, int idx)
540 unsigned int bar = 0, offset = board->first_offset;
547 offset = board->uart_offset;
554 offset = board->uart_offset;
563 return setup_port(priv, port, bar, offset, board->reg_shift);
567 * Some Titan cards are also a little weird
570 titan_400l_800l_setup(struct serial_private *priv,
571 struct pciserial_board *board,
572 struct uart_port *port, int idx)
574 unsigned int bar, offset = board->first_offset;
585 offset = (idx - 2) * board->uart_offset;
588 return setup_port(priv, port, bar, offset, board->reg_shift);
591 static int pci_xircom_init(struct pci_dev *dev)
597 static int pci_netmos_init(struct pci_dev *dev)
599 /* subdevice 0x00PS means <P> parallel, <S> serial */
600 unsigned int num_serial = dev->subsystem_device & 0xf;
608 * ITE support by Niels de Vos <niels.devos@wincor-nixdorf.com>
610 * These chips are available with optionally one parallel port and up to
611 * two serial ports. Unfortunately they all have the same product id.
613 * Basic configuration is done over a region of 32 I/O ports. The base
614 * ioport is called INTA or INTC, depending on docs/other drivers.
616 * The region of the 32 I/O ports is configured in POSIO0R...
620 #define ITE_887x_MISCR 0x9c
621 #define ITE_887x_INTCBAR 0x78
622 #define ITE_887x_UARTBAR 0x7c
623 #define ITE_887x_PS0BAR 0x10
624 #define ITE_887x_POSIO0 0x60
627 #define ITE_887x_IOSIZE 32
628 /* I/O space size (bits 26-24; 8 bytes = 011b) */
629 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
630 /* I/O space size (bits 26-24; 32 bytes = 101b) */
631 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
632 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
633 #define ITE_887x_POSIO_SPEED (3 << 29)
634 /* enable IO_Space bit */
635 #define ITE_887x_POSIO_ENABLE (1 << 31)
637 static int pci_ite887x_init(struct pci_dev *dev)
639 /* inta_addr are the configuration addresses of the ITE */
640 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
643 struct resource *iobase = NULL;
644 u32 miscr, uartbar, ioport;
646 /* search for the base-ioport */
648 while (inta_addr[i] && iobase == NULL) {
649 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
651 if (iobase != NULL) {
652 /* write POSIO0R - speed | size | ioport */
653 pci_write_config_dword(dev, ITE_887x_POSIO0,
654 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
655 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
656 /* write INTCBAR - ioport */
657 pci_write_config_dword(dev, ITE_887x_INTCBAR,
659 ret = inb(inta_addr[i]);
661 /* ioport connected */
664 release_region(iobase->start, ITE_887x_IOSIZE);
671 printk(KERN_ERR "ite887x: could not find iobase\n");
675 /* start of undocumented type checking (see parport_pc.c) */
676 type = inb(iobase->start + 0x18) & 0x0f;
679 case 0x2: /* ITE8871 (1P) */
680 case 0xa: /* ITE8875 (1P) */
683 case 0xe: /* ITE8872 (2S1P) */
686 case 0x6: /* ITE8873 (1S) */
689 case 0x8: /* ITE8874 (2S) */
693 moan_device("Unknown ITE887x", dev);
697 /* configure all serial ports */
698 for (i = 0; i < ret; i++) {
699 /* read the I/O port from the device */
700 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
702 ioport &= 0x0000FF00; /* the actual base address */
703 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
704 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
705 ITE_887x_POSIO_IOSIZE_8 | ioport);
707 /* write the ioport to the UARTBAR */
708 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
709 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
710 uartbar |= (ioport << (16 * i)); /* set the ioport */
711 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
713 /* get current config */
714 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
715 /* disable interrupts (UARTx_Routing[3:0]) */
716 miscr &= ~(0xf << (12 - 4 * i));
717 /* activate the UART (UARTx_En) */
718 miscr |= 1 << (23 - i);
719 /* write new config with activated UART */
720 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
724 /* the device has no UARTs if we get here */
725 release_region(iobase->start, ITE_887x_IOSIZE);
731 static void __devexit pci_ite887x_exit(struct pci_dev *dev)
734 /* the ioport is bit 0-15 in POSIO0R */
735 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
737 release_region(ioport, ITE_887x_IOSIZE);
741 pci_default_setup(struct serial_private *priv, struct pciserial_board *board,
742 struct uart_port *port, int idx)
744 unsigned int bar, offset = board->first_offset, maxnr;
746 bar = FL_GET_BASE(board->flags);
747 if (board->flags & FL_BASE_BARS)
750 offset += idx * board->uart_offset;
752 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
753 (board->reg_shift + 3);
755 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
758 return setup_port(priv, port, bar, offset, board->reg_shift);
761 /* This should be in linux/pci_ids.h */
762 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
763 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
764 #define PCI_DEVICE_ID_OCTPRO 0x0001
765 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
766 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
767 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
768 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
770 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
771 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
774 * Master list of serial port init/setup/exit quirks.
775 * This does not describe the general nature of the port.
776 * (ie, baud base, number and location of ports, etc)
778 * This list is ordered alphabetically by vendor then device.
779 * Specific entries must come before more generic entries.
781 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
783 * ADDI-DATA GmbH communication cards <info@addi-data.com>
786 .vendor = PCI_VENDOR_ID_ADDIDATA_OLD,
787 .device = PCI_DEVICE_ID_ADDIDATA_APCI7800,
788 .subvendor = PCI_ANY_ID,
789 .subdevice = PCI_ANY_ID,
790 .setup = addidata_apci7800_setup,
793 * AFAVLAB cards - these may be called via parport_serial
794 * It is not clear whether this applies to all products.
797 .vendor = PCI_VENDOR_ID_AFAVLAB,
798 .device = PCI_ANY_ID,
799 .subvendor = PCI_ANY_ID,
800 .subdevice = PCI_ANY_ID,
801 .setup = afavlab_setup,
807 .vendor = PCI_VENDOR_ID_HP,
808 .device = PCI_DEVICE_ID_HP_DIVA,
809 .subvendor = PCI_ANY_ID,
810 .subdevice = PCI_ANY_ID,
811 .init = pci_hp_diva_init,
812 .setup = pci_hp_diva_setup,
818 .vendor = PCI_VENDOR_ID_INTEL,
819 .device = PCI_DEVICE_ID_INTEL_80960_RP,
821 .subdevice = PCI_ANY_ID,
822 .init = pci_inteli960ni_init,
823 .setup = pci_default_setup,
829 .vendor = PCI_VENDOR_ID_ITE,
830 .device = PCI_DEVICE_ID_ITE_8872,
831 .subvendor = PCI_ANY_ID,
832 .subdevice = PCI_ANY_ID,
833 .init = pci_ite887x_init,
834 .setup = pci_default_setup,
835 .exit = __devexit_p(pci_ite887x_exit),
841 .vendor = PCI_VENDOR_ID_PANACOM,
842 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
843 .subvendor = PCI_ANY_ID,
844 .subdevice = PCI_ANY_ID,
845 .init = pci_plx9050_init,
846 .setup = pci_default_setup,
847 .exit = __devexit_p(pci_plx9050_exit),
850 .vendor = PCI_VENDOR_ID_PANACOM,
851 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
852 .subvendor = PCI_ANY_ID,
853 .subdevice = PCI_ANY_ID,
854 .init = pci_plx9050_init,
855 .setup = pci_default_setup,
856 .exit = __devexit_p(pci_plx9050_exit),
862 .vendor = PCI_VENDOR_ID_PLX,
863 .device = PCI_DEVICE_ID_PLX_9030,
864 .subvendor = PCI_SUBVENDOR_ID_PERLE,
865 .subdevice = PCI_ANY_ID,
866 .setup = pci_default_setup,
869 .vendor = PCI_VENDOR_ID_PLX,
870 .device = PCI_DEVICE_ID_PLX_9050,
871 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
872 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
873 .init = pci_plx9050_init,
874 .setup = pci_default_setup,
875 .exit = __devexit_p(pci_plx9050_exit),
878 .vendor = PCI_VENDOR_ID_PLX,
879 .device = PCI_DEVICE_ID_PLX_9050,
880 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
881 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
882 .init = pci_plx9050_init,
883 .setup = pci_default_setup,
884 .exit = __devexit_p(pci_plx9050_exit),
887 .vendor = PCI_VENDOR_ID_PLX,
888 .device = PCI_DEVICE_ID_PLX_9050,
889 .subvendor = PCI_VENDOR_ID_PLX,
890 .subdevice = PCI_SUBDEVICE_ID_UNKNOWN_0x1584,
891 .init = pci_plx9050_init,
892 .setup = pci_default_setup,
893 .exit = __devexit_p(pci_plx9050_exit),
896 .vendor = PCI_VENDOR_ID_PLX,
897 .device = PCI_DEVICE_ID_PLX_ROMULUS,
898 .subvendor = PCI_VENDOR_ID_PLX,
899 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
900 .init = pci_plx9050_init,
901 .setup = pci_default_setup,
902 .exit = __devexit_p(pci_plx9050_exit),
905 * SBS Technologies, Inc., PMC-OCTALPRO 232
908 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
909 .device = PCI_DEVICE_ID_OCTPRO,
910 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
911 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
914 .exit = __devexit_p(sbs_exit),
917 * SBS Technologies, Inc., PMC-OCTALPRO 422
920 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
921 .device = PCI_DEVICE_ID_OCTPRO,
922 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
923 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
926 .exit = __devexit_p(sbs_exit),
929 * SBS Technologies, Inc., P-Octal 232
932 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
933 .device = PCI_DEVICE_ID_OCTPRO,
934 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
935 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
938 .exit = __devexit_p(sbs_exit),
941 * SBS Technologies, Inc., P-Octal 422
944 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
945 .device = PCI_DEVICE_ID_OCTPRO,
946 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
947 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
950 .exit = __devexit_p(sbs_exit),
953 * SIIG cards - these may be called via parport_serial
956 .vendor = PCI_VENDOR_ID_SIIG,
957 .device = PCI_ANY_ID,
958 .subvendor = PCI_ANY_ID,
959 .subdevice = PCI_ANY_ID,
960 .init = pci_siig_init,
961 .setup = pci_siig_setup,
967 .vendor = PCI_VENDOR_ID_TITAN,
968 .device = PCI_DEVICE_ID_TITAN_400L,
969 .subvendor = PCI_ANY_ID,
970 .subdevice = PCI_ANY_ID,
971 .setup = titan_400l_800l_setup,
974 .vendor = PCI_VENDOR_ID_TITAN,
975 .device = PCI_DEVICE_ID_TITAN_800L,
976 .subvendor = PCI_ANY_ID,
977 .subdevice = PCI_ANY_ID,
978 .setup = titan_400l_800l_setup,
984 .vendor = PCI_VENDOR_ID_TIMEDIA,
985 .device = PCI_DEVICE_ID_TIMEDIA_1889,
986 .subvendor = PCI_VENDOR_ID_TIMEDIA,
987 .subdevice = PCI_ANY_ID,
988 .init = pci_timedia_init,
989 .setup = pci_timedia_setup,
992 .vendor = PCI_VENDOR_ID_TIMEDIA,
993 .device = PCI_ANY_ID,
994 .subvendor = PCI_ANY_ID,
995 .subdevice = PCI_ANY_ID,
996 .setup = pci_timedia_setup,
1002 .vendor = PCI_VENDOR_ID_XIRCOM,
1003 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
1004 .subvendor = PCI_ANY_ID,
1005 .subdevice = PCI_ANY_ID,
1006 .init = pci_xircom_init,
1007 .setup = pci_default_setup,
1010 * Netmos cards - these may be called via parport_serial
1013 .vendor = PCI_VENDOR_ID_NETMOS,
1014 .device = PCI_ANY_ID,
1015 .subvendor = PCI_ANY_ID,
1016 .subdevice = PCI_ANY_ID,
1017 .init = pci_netmos_init,
1018 .setup = pci_default_setup,
1021 * Default "match everything" terminator entry
1024 .vendor = PCI_ANY_ID,
1025 .device = PCI_ANY_ID,
1026 .subvendor = PCI_ANY_ID,
1027 .subdevice = PCI_ANY_ID,
1028 .setup = pci_default_setup,
1032 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
1034 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
1037 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
1039 struct pci_serial_quirk *quirk;
1041 for (quirk = pci_serial_quirks; ; quirk++)
1042 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
1043 quirk_id_matches(quirk->device, dev->device) &&
1044 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
1045 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
1050 static inline int get_pci_irq(struct pci_dev *dev,
1051 struct pciserial_board *board)
1053 if (board->flags & FL_NOIRQ)
1060 * This is the configuration table for all of the PCI serial boards
1061 * which we support. It is directly indexed by the pci_board_num_t enum
1062 * value, which is encoded in the pci_device_id PCI probe table's
1063 * driver_data member.
1065 * The makeup of these names are:
1066 * pbn_bn{_bt}_n_baud{_offsetinhex}
1068 * bn = PCI BAR number
1069 * bt = Index using PCI BARs
1070 * n = number of serial ports
1072 * offsetinhex = offset for each sequential port (in hex)
1074 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
1076 * Please note: in theory if n = 1, _bt infix should make no difference.
1077 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
1079 enum pci_board_num_t {
1099 pbn_b0_2_1843200_200,
1100 pbn_b0_4_1843200_200,
1101 pbn_b0_8_1843200_200,
1164 * Board-specific versions.
1172 pbn_oxsemi_1_4000000,
1173 pbn_oxsemi_2_4000000,
1174 pbn_oxsemi_4_4000000,
1175 pbn_oxsemi_8_4000000,
1189 * uart_offset - the space between channels
1190 * reg_shift - describes how the UART registers are mapped
1191 * to PCI memory by the card.
1192 * For example IER register on SBS, Inc. PMC-OctPro is located at
1193 * offset 0x10 from the UART base, while UART_IER is defined as 1
1194 * in include/linux/serial_reg.h,
1195 * see first lines of serial_in() and serial_out() in 8250.c
1198 static struct pciserial_board pci_boards[] __devinitdata = {
1202 .base_baud = 115200,
1205 [pbn_b0_1_115200] = {
1208 .base_baud = 115200,
1211 [pbn_b0_2_115200] = {
1214 .base_baud = 115200,
1217 [pbn_b0_4_115200] = {
1220 .base_baud = 115200,
1223 [pbn_b0_5_115200] = {
1226 .base_baud = 115200,
1229 [pbn_b0_8_115200] = {
1232 .base_baud = 115200,
1235 [pbn_b0_1_921600] = {
1238 .base_baud = 921600,
1241 [pbn_b0_2_921600] = {
1244 .base_baud = 921600,
1247 [pbn_b0_4_921600] = {
1250 .base_baud = 921600,
1254 [pbn_b0_2_1130000] = {
1257 .base_baud = 1130000,
1261 [pbn_b0_4_1152000] = {
1264 .base_baud = 1152000,
1268 [pbn_b0_2_1843200] = {
1271 .base_baud = 1843200,
1274 [pbn_b0_4_1843200] = {
1277 .base_baud = 1843200,
1281 [pbn_b0_2_1843200_200] = {
1284 .base_baud = 1843200,
1285 .uart_offset = 0x200,
1287 [pbn_b0_4_1843200_200] = {
1290 .base_baud = 1843200,
1291 .uart_offset = 0x200,
1293 [pbn_b0_8_1843200_200] = {
1296 .base_baud = 1843200,
1297 .uart_offset = 0x200,
1299 [pbn_b0_1_4000000] = {
1302 .base_baud = 4000000,
1306 [pbn_b0_bt_1_115200] = {
1307 .flags = FL_BASE0|FL_BASE_BARS,
1309 .base_baud = 115200,
1312 [pbn_b0_bt_2_115200] = {
1313 .flags = FL_BASE0|FL_BASE_BARS,
1315 .base_baud = 115200,
1318 [pbn_b0_bt_8_115200] = {
1319 .flags = FL_BASE0|FL_BASE_BARS,
1321 .base_baud = 115200,
1325 [pbn_b0_bt_1_460800] = {
1326 .flags = FL_BASE0|FL_BASE_BARS,
1328 .base_baud = 460800,
1331 [pbn_b0_bt_2_460800] = {
1332 .flags = FL_BASE0|FL_BASE_BARS,
1334 .base_baud = 460800,
1337 [pbn_b0_bt_4_460800] = {
1338 .flags = FL_BASE0|FL_BASE_BARS,
1340 .base_baud = 460800,
1344 [pbn_b0_bt_1_921600] = {
1345 .flags = FL_BASE0|FL_BASE_BARS,
1347 .base_baud = 921600,
1350 [pbn_b0_bt_2_921600] = {
1351 .flags = FL_BASE0|FL_BASE_BARS,
1353 .base_baud = 921600,
1356 [pbn_b0_bt_4_921600] = {
1357 .flags = FL_BASE0|FL_BASE_BARS,
1359 .base_baud = 921600,
1362 [pbn_b0_bt_8_921600] = {
1363 .flags = FL_BASE0|FL_BASE_BARS,
1365 .base_baud = 921600,
1369 [pbn_b1_1_115200] = {
1372 .base_baud = 115200,
1375 [pbn_b1_2_115200] = {
1378 .base_baud = 115200,
1381 [pbn_b1_4_115200] = {
1384 .base_baud = 115200,
1387 [pbn_b1_8_115200] = {
1390 .base_baud = 115200,
1394 [pbn_b1_1_921600] = {
1397 .base_baud = 921600,
1400 [pbn_b1_2_921600] = {
1403 .base_baud = 921600,
1406 [pbn_b1_4_921600] = {
1409 .base_baud = 921600,
1412 [pbn_b1_8_921600] = {
1415 .base_baud = 921600,
1418 [pbn_b1_2_1250000] = {
1421 .base_baud = 1250000,
1425 [pbn_b1_bt_1_115200] = {
1426 .flags = FL_BASE1|FL_BASE_BARS,
1428 .base_baud = 115200,
1432 [pbn_b1_bt_2_921600] = {
1433 .flags = FL_BASE1|FL_BASE_BARS,
1435 .base_baud = 921600,
1439 [pbn_b1_1_1382400] = {
1442 .base_baud = 1382400,
1445 [pbn_b1_2_1382400] = {
1448 .base_baud = 1382400,
1451 [pbn_b1_4_1382400] = {
1454 .base_baud = 1382400,
1457 [pbn_b1_8_1382400] = {
1460 .base_baud = 1382400,
1464 [pbn_b2_1_115200] = {
1467 .base_baud = 115200,
1470 [pbn_b2_2_115200] = {
1473 .base_baud = 115200,
1476 [pbn_b2_4_115200] = {
1479 .base_baud = 115200,
1482 [pbn_b2_8_115200] = {
1485 .base_baud = 115200,
1489 [pbn_b2_1_460800] = {
1492 .base_baud = 460800,
1495 [pbn_b2_4_460800] = {
1498 .base_baud = 460800,
1501 [pbn_b2_8_460800] = {
1504 .base_baud = 460800,
1507 [pbn_b2_16_460800] = {
1510 .base_baud = 460800,
1514 [pbn_b2_1_921600] = {
1517 .base_baud = 921600,
1520 [pbn_b2_4_921600] = {
1523 .base_baud = 921600,
1526 [pbn_b2_8_921600] = {
1529 .base_baud = 921600,
1533 [pbn_b2_bt_1_115200] = {
1534 .flags = FL_BASE2|FL_BASE_BARS,
1536 .base_baud = 115200,
1539 [pbn_b2_bt_2_115200] = {
1540 .flags = FL_BASE2|FL_BASE_BARS,
1542 .base_baud = 115200,
1545 [pbn_b2_bt_4_115200] = {
1546 .flags = FL_BASE2|FL_BASE_BARS,
1548 .base_baud = 115200,
1552 [pbn_b2_bt_2_921600] = {
1553 .flags = FL_BASE2|FL_BASE_BARS,
1555 .base_baud = 921600,
1558 [pbn_b2_bt_4_921600] = {
1559 .flags = FL_BASE2|FL_BASE_BARS,
1561 .base_baud = 921600,
1565 [pbn_b3_2_115200] = {
1568 .base_baud = 115200,
1571 [pbn_b3_4_115200] = {
1574 .base_baud = 115200,
1577 [pbn_b3_8_115200] = {
1580 .base_baud = 115200,
1585 * Entries following this are board-specific.
1594 .base_baud = 921600,
1595 .uart_offset = 0x400,
1599 .flags = FL_BASE2|FL_BASE_BARS,
1601 .base_baud = 921600,
1602 .uart_offset = 0x400,
1606 .flags = FL_BASE2|FL_BASE_BARS,
1608 .base_baud = 921600,
1609 .uart_offset = 0x400,
1613 [pbn_exsys_4055] = {
1616 .base_baud = 115200,
1620 /* I think this entry is broken - the first_offset looks wrong --rmk */
1621 [pbn_plx_romulus] = {
1624 .base_baud = 921600,
1625 .uart_offset = 8 << 2,
1627 .first_offset = 0x03,
1631 * This board uses the size of PCI Base region 0 to
1632 * signal now many ports are available
1635 .flags = FL_BASE0|FL_REGION_SZ_CAP,
1637 .base_baud = 115200,
1640 [pbn_oxsemi_1_4000000] = {
1643 .base_baud = 4000000,
1644 .uart_offset = 0x200,
1645 .first_offset = 0x1000,
1647 [pbn_oxsemi_2_4000000] = {
1650 .base_baud = 4000000,
1651 .uart_offset = 0x200,
1652 .first_offset = 0x1000,
1654 [pbn_oxsemi_4_4000000] = {
1657 .base_baud = 4000000,
1658 .uart_offset = 0x200,
1659 .first_offset = 0x1000,
1661 [pbn_oxsemi_8_4000000] = {
1664 .base_baud = 4000000,
1665 .uart_offset = 0x200,
1666 .first_offset = 0x1000,
1671 * EKF addition for i960 Boards form EKF with serial port.
1674 [pbn_intel_i960] = {
1677 .base_baud = 921600,
1678 .uart_offset = 8 << 2,
1680 .first_offset = 0x10000,
1683 .flags = FL_BASE0|FL_NOIRQ,
1685 .base_baud = 458333,
1688 .first_offset = 0x20178,
1692 * Computone - uses IOMEM.
1694 [pbn_computone_4] = {
1697 .base_baud = 921600,
1698 .uart_offset = 0x40,
1700 .first_offset = 0x200,
1702 [pbn_computone_6] = {
1705 .base_baud = 921600,
1706 .uart_offset = 0x40,
1708 .first_offset = 0x200,
1710 [pbn_computone_8] = {
1713 .base_baud = 921600,
1714 .uart_offset = 0x40,
1716 .first_offset = 0x200,
1721 .base_baud = 460800,
1726 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
1727 * Only basic 16550A support.
1728 * XR17C15[24] are not tested, but they should work.
1730 [pbn_exar_XR17C152] = {
1733 .base_baud = 921600,
1734 .uart_offset = 0x200,
1736 [pbn_exar_XR17C154] = {
1739 .base_baud = 921600,
1740 .uart_offset = 0x200,
1742 [pbn_exar_XR17C158] = {
1745 .base_baud = 921600,
1746 .uart_offset = 0x200,
1749 * PA Semi PWRficient PA6T-1682M on-chip UART
1751 [pbn_pasemi_1682M] = {
1754 .base_baud = 8333333,
1758 static const struct pci_device_id softmodem_blacklist[] = {
1759 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
1763 * Given a complete unknown PCI device, try to use some heuristics to
1764 * guess what the configuration might be, based on the pitiful PCI
1765 * serial specs. Returns 0 on success, 1 on failure.
1767 static int __devinit
1768 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
1770 const struct pci_device_id *blacklist;
1771 int num_iomem, num_port, first_port = -1, i;
1774 * If it is not a communications device or the programming
1775 * interface is greater than 6, give up.
1777 * (Should we try to make guesses for multiport serial devices
1780 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
1781 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
1782 (dev->class & 0xff) > 6)
1786 * Do not access blacklisted devices that are known not to
1787 * feature serial ports.
1789 for (blacklist = softmodem_blacklist;
1790 blacklist < softmodem_blacklist + ARRAY_SIZE(softmodem_blacklist);
1792 if (dev->vendor == blacklist->vendor &&
1793 dev->device == blacklist->device)
1797 num_iomem = num_port = 0;
1798 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1799 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
1801 if (first_port == -1)
1804 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
1809 * If there is 1 or 0 iomem regions, and exactly one port,
1810 * use it. We guess the number of ports based on the IO
1813 if (num_iomem <= 1 && num_port == 1) {
1814 board->flags = first_port;
1815 board->num_ports = pci_resource_len(dev, first_port) / 8;
1820 * Now guess if we've got a board which indexes by BARs.
1821 * Each IO BAR should be 8 bytes, and they should follow
1826 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1827 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
1828 pci_resource_len(dev, i) == 8 &&
1829 (first_port == -1 || (first_port + num_port) == i)) {
1831 if (first_port == -1)
1837 board->flags = first_port | FL_BASE_BARS;
1838 board->num_ports = num_port;
1846 serial_pci_matches(struct pciserial_board *board,
1847 struct pciserial_board *guessed)
1850 board->num_ports == guessed->num_ports &&
1851 board->base_baud == guessed->base_baud &&
1852 board->uart_offset == guessed->uart_offset &&
1853 board->reg_shift == guessed->reg_shift &&
1854 board->first_offset == guessed->first_offset;
1858 * Oxford Semiconductor Inc.
1859 * Check that device is part of the Tornado range of devices, then determine
1860 * the number of ports available on the device.
1862 static int pci_oxsemi_tornado_init(struct pci_dev *dev, struct pciserial_board *board)
1865 unsigned long deviceID;
1866 unsigned int number_uarts;
1868 p = pci_iomap(dev, 0, 5);
1872 deviceID = ioread32(p);
1873 /* Tornado device */
1874 if (deviceID == 0x07000200) {
1875 number_uarts = ioread8(p + 4);
1876 board->num_ports = number_uarts;
1878 "%d ports detected on Oxford PCI Express device\n",
1881 pci_iounmap(dev, p);
1885 struct serial_private *
1886 pciserial_init_ports(struct pci_dev *dev, struct pciserial_board *board)
1888 struct uart_port serial_port;
1889 struct serial_private *priv;
1890 struct pci_serial_quirk *quirk;
1891 int rc, nr_ports, i;
1894 * Find number of ports on board
1896 if (dev->vendor == PCI_VENDOR_ID_OXSEMI)
1897 pci_oxsemi_tornado_init(dev, board);
1899 nr_ports = board->num_ports;
1902 * Find an init and setup quirks.
1904 quirk = find_quirk(dev);
1907 * Run the new-style initialization function.
1908 * The initialization function returns:
1910 * 0 - use board->num_ports
1911 * >0 - number of ports
1914 rc = quirk->init(dev);
1923 priv = kzalloc(sizeof(struct serial_private) +
1924 sizeof(unsigned int) * nr_ports,
1927 priv = ERR_PTR(-ENOMEM);
1932 priv->quirk = quirk;
1934 memset(&serial_port, 0, sizeof(struct uart_port));
1935 serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
1936 serial_port.uartclk = board->base_baud * 16;
1937 serial_port.irq = get_pci_irq(dev, board);
1938 serial_port.dev = &dev->dev;
1940 for (i = 0; i < nr_ports; i++) {
1941 if (quirk->setup(priv, board, &serial_port, i))
1944 #ifdef SERIAL_DEBUG_PCI
1945 printk(KERN_DEBUG "Setup PCI port: port %x, irq %d, type %d\n",
1946 serial_port.iobase, serial_port.irq, serial_port.iotype);
1949 priv->line[i] = serial8250_register_port(&serial_port);
1950 if (priv->line[i] < 0) {
1951 printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
1964 EXPORT_SYMBOL_GPL(pciserial_init_ports);
1966 void pciserial_remove_ports(struct serial_private *priv)
1968 struct pci_serial_quirk *quirk;
1971 for (i = 0; i < priv->nr; i++)
1972 serial8250_unregister_port(priv->line[i]);
1974 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1975 if (priv->remapped_bar[i])
1976 iounmap(priv->remapped_bar[i]);
1977 priv->remapped_bar[i] = NULL;
1981 * Find the exit quirks.
1983 quirk = find_quirk(priv->dev);
1985 quirk->exit(priv->dev);
1989 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
1991 void pciserial_suspend_ports(struct serial_private *priv)
1995 for (i = 0; i < priv->nr; i++)
1996 if (priv->line[i] >= 0)
1997 serial8250_suspend_port(priv->line[i]);
1999 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
2001 void pciserial_resume_ports(struct serial_private *priv)
2006 * Ensure that the board is correctly configured.
2008 if (priv->quirk->init)
2009 priv->quirk->init(priv->dev);
2011 for (i = 0; i < priv->nr; i++)
2012 if (priv->line[i] >= 0)
2013 serial8250_resume_port(priv->line[i]);
2015 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
2018 * Probe one serial board. Unfortunately, there is no rhyme nor reason
2019 * to the arrangement of serial ports on a PCI card.
2021 static int __devinit
2022 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
2024 struct serial_private *priv;
2025 struct pciserial_board *board, tmp;
2028 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
2029 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
2034 board = &pci_boards[ent->driver_data];
2036 rc = pci_enable_device(dev);
2040 if (ent->driver_data == pbn_default) {
2042 * Use a copy of the pci_board entry for this;
2043 * avoid changing entries in the table.
2045 memcpy(&tmp, board, sizeof(struct pciserial_board));
2049 * We matched one of our class entries. Try to
2050 * determine the parameters of this board.
2052 rc = serial_pci_guess_board(dev, board);
2057 * We matched an explicit entry. If we are able to
2058 * detect this boards settings with our heuristic,
2059 * then we no longer need this entry.
2061 memcpy(&tmp, &pci_boards[pbn_default],
2062 sizeof(struct pciserial_board));
2063 rc = serial_pci_guess_board(dev, &tmp);
2064 if (rc == 0 && serial_pci_matches(board, &tmp))
2065 moan_device("Redundant entry in serial pci_table.",
2069 priv = pciserial_init_ports(dev, board);
2070 if (!IS_ERR(priv)) {
2071 pci_set_drvdata(dev, priv);
2078 pci_disable_device(dev);
2082 static void __devexit pciserial_remove_one(struct pci_dev *dev)
2084 struct serial_private *priv = pci_get_drvdata(dev);
2086 pci_set_drvdata(dev, NULL);
2088 pciserial_remove_ports(priv);
2090 pci_disable_device(dev);
2094 static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
2096 struct serial_private *priv = pci_get_drvdata(dev);
2099 pciserial_suspend_ports(priv);
2101 pci_save_state(dev);
2102 pci_set_power_state(dev, pci_choose_state(dev, state));
2106 static int pciserial_resume_one(struct pci_dev *dev)
2109 struct serial_private *priv = pci_get_drvdata(dev);
2111 pci_set_power_state(dev, PCI_D0);
2112 pci_restore_state(dev);
2116 * The device may have been disabled. Re-enable it.
2118 err = pci_enable_device(dev);
2119 /* FIXME: We cannot simply error out here */
2121 printk(KERN_ERR "pciserial: Unable to re-enable ports, trying to continue.\n");
2122 pciserial_resume_ports(priv);
2128 static struct pci_device_id serial_pci_tbl[] = {
2129 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2130 PCI_SUBVENDOR_ID_CONNECT_TECH,
2131 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2133 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2134 PCI_SUBVENDOR_ID_CONNECT_TECH,
2135 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2137 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2138 PCI_SUBVENDOR_ID_CONNECT_TECH,
2139 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2141 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2142 PCI_SUBVENDOR_ID_CONNECT_TECH,
2143 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2145 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2146 PCI_SUBVENDOR_ID_CONNECT_TECH,
2147 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2149 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2150 PCI_SUBVENDOR_ID_CONNECT_TECH,
2151 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2153 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2154 PCI_SUBVENDOR_ID_CONNECT_TECH,
2155 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
2157 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2158 PCI_SUBVENDOR_ID_CONNECT_TECH,
2159 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
2161 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2162 PCI_SUBVENDOR_ID_CONNECT_TECH,
2163 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
2165 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2166 PCI_SUBVENDOR_ID_CONNECT_TECH,
2167 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
2169 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2170 PCI_SUBVENDOR_ID_CONNECT_TECH,
2171 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
2173 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2174 PCI_SUBVENDOR_ID_CONNECT_TECH,
2175 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
2177 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2178 PCI_SUBVENDOR_ID_CONNECT_TECH,
2179 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
2181 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2182 PCI_SUBVENDOR_ID_CONNECT_TECH,
2183 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
2185 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2186 PCI_SUBVENDOR_ID_CONNECT_TECH,
2187 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
2189 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2190 PCI_SUBVENDOR_ID_CONNECT_TECH,
2191 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
2193 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2194 PCI_SUBVENDOR_ID_CONNECT_TECH,
2195 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
2197 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2198 PCI_VENDOR_ID_AFAVLAB,
2199 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
2201 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2202 PCI_SUBVENDOR_ID_CONNECT_TECH,
2203 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
2204 pbn_b0_2_1843200_200 },
2205 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2206 PCI_SUBVENDOR_ID_CONNECT_TECH,
2207 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
2208 pbn_b0_4_1843200_200 },
2209 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2210 PCI_SUBVENDOR_ID_CONNECT_TECH,
2211 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
2212 pbn_b0_8_1843200_200 },
2213 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2214 PCI_SUBVENDOR_ID_CONNECT_TECH,
2215 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
2216 pbn_b0_2_1843200_200 },
2217 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2218 PCI_SUBVENDOR_ID_CONNECT_TECH,
2219 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
2220 pbn_b0_4_1843200_200 },
2221 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2222 PCI_SUBVENDOR_ID_CONNECT_TECH,
2223 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
2224 pbn_b0_8_1843200_200 },
2225 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2226 PCI_SUBVENDOR_ID_CONNECT_TECH,
2227 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
2228 pbn_b0_2_1843200_200 },
2229 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2230 PCI_SUBVENDOR_ID_CONNECT_TECH,
2231 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
2232 pbn_b0_4_1843200_200 },
2233 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2234 PCI_SUBVENDOR_ID_CONNECT_TECH,
2235 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
2236 pbn_b0_8_1843200_200 },
2237 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2238 PCI_SUBVENDOR_ID_CONNECT_TECH,
2239 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
2240 pbn_b0_2_1843200_200 },
2241 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2242 PCI_SUBVENDOR_ID_CONNECT_TECH,
2243 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
2244 pbn_b0_4_1843200_200 },
2245 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2246 PCI_SUBVENDOR_ID_CONNECT_TECH,
2247 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
2248 pbn_b0_8_1843200_200 },
2250 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
2251 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2252 pbn_b2_bt_1_115200 },
2253 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
2254 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2255 pbn_b2_bt_2_115200 },
2256 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
2257 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2258 pbn_b2_bt_4_115200 },
2259 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
2260 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2261 pbn_b2_bt_2_115200 },
2262 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
2263 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2264 pbn_b2_bt_4_115200 },
2265 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
2266 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2268 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
2269 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2272 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
2273 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2274 pbn_b2_bt_2_115200 },
2275 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
2276 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2277 pbn_b2_bt_2_921600 },
2279 * VScom SPCOM800, from sl@s.pl
2281 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
2282 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2284 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
2285 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2287 /* Unknown card - subdevice 0x1584 */
2288 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2290 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
2292 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2293 PCI_SUBVENDOR_ID_KEYSPAN,
2294 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
2296 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
2297 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2299 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
2300 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2302 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
2303 PCI_VENDOR_ID_ESDGMBH,
2304 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
2306 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2307 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2308 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
2310 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2311 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2312 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
2314 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2315 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2316 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
2318 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2319 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2320 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
2322 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2323 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
2324 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
2326 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2327 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
2328 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
2330 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2331 PCI_SUBVENDOR_ID_EXSYS,
2332 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
2335 * Megawolf Romulus PCI Serial Card, from Mike Hudson
2338 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
2339 0x10b5, 0x106a, 0, 0,
2341 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
2342 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2344 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
2345 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2347 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
2348 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2350 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
2351 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2353 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
2354 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
2357 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2358 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
2363 * The below card is a little controversial since it is the
2364 * subject of a PCI vendor/device ID clash. (See
2365 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
2366 * For now just used the hex ID 0x950a.
2368 { PCI_VENDOR_ID_OXSEMI, 0x950a,
2369 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2371 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2372 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2374 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
2375 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2376 pbn_b0_bt_2_921600 },
2379 * Oxford Semiconductor Inc. Tornado PCI express device range.
2381 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
2382 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2384 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
2385 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2387 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
2388 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2389 pbn_oxsemi_1_4000000 },
2390 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
2391 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2392 pbn_oxsemi_1_4000000 },
2393 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
2394 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2396 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
2397 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2399 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
2400 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2401 pbn_oxsemi_1_4000000 },
2402 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
2403 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2404 pbn_oxsemi_1_4000000 },
2405 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
2406 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2408 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
2409 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2411 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
2412 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2414 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
2415 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2417 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
2418 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2419 pbn_oxsemi_2_4000000 },
2420 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
2421 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2422 pbn_oxsemi_2_4000000 },
2423 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
2424 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2425 pbn_oxsemi_4_4000000 },
2426 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
2427 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2428 pbn_oxsemi_4_4000000 },
2429 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
2430 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2431 pbn_oxsemi_8_4000000 },
2432 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
2433 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2434 pbn_oxsemi_8_4000000 },
2435 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
2436 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2437 pbn_oxsemi_1_4000000 },
2438 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
2439 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2440 pbn_oxsemi_1_4000000 },
2441 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
2442 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2443 pbn_oxsemi_1_4000000 },
2444 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
2445 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2446 pbn_oxsemi_1_4000000 },
2447 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
2448 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2449 pbn_oxsemi_1_4000000 },
2450 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
2451 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2452 pbn_oxsemi_1_4000000 },
2453 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
2454 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2455 pbn_oxsemi_1_4000000 },
2456 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
2457 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2458 pbn_oxsemi_1_4000000 },
2459 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
2460 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2461 pbn_oxsemi_1_4000000 },
2462 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
2463 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2464 pbn_oxsemi_1_4000000 },
2465 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
2466 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2467 pbn_oxsemi_1_4000000 },
2468 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
2469 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2470 pbn_oxsemi_1_4000000 },
2471 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
2472 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2473 pbn_oxsemi_1_4000000 },
2474 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
2475 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2476 pbn_oxsemi_1_4000000 },
2477 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
2478 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2479 pbn_oxsemi_1_4000000 },
2480 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
2481 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2482 pbn_oxsemi_1_4000000 },
2483 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
2484 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2485 pbn_oxsemi_1_4000000 },
2486 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
2487 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2488 pbn_oxsemi_1_4000000 },
2489 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
2490 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2491 pbn_oxsemi_1_4000000 },
2492 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
2493 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2494 pbn_oxsemi_1_4000000 },
2495 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
2496 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2497 pbn_oxsemi_1_4000000 },
2498 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
2499 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2500 pbn_oxsemi_1_4000000 },
2501 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
2502 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2503 pbn_oxsemi_1_4000000 },
2504 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
2505 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2506 pbn_oxsemi_1_4000000 },
2507 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
2508 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2509 pbn_oxsemi_1_4000000 },
2510 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
2511 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2512 pbn_oxsemi_1_4000000 },
2515 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
2516 * from skokodyn@yahoo.com
2518 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2519 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
2521 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2522 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
2524 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2525 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
2527 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2528 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
2532 * Digitan DS560-558, from jimd@esoft.com
2534 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
2535 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2539 * Titan Electronic cards
2540 * The 400L and 800L have a custom setup quirk.
2542 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
2543 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2545 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
2546 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2548 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
2549 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2551 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
2552 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2554 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
2555 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2557 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
2558 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2559 pbn_b1_bt_2_921600 },
2560 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
2561 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2562 pbn_b0_bt_4_921600 },
2563 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
2564 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2565 pbn_b0_bt_8_921600 },
2567 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
2568 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2570 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
2571 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2573 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
2574 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2576 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
2577 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2578 pbn_b2_bt_2_921600 },
2579 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
2580 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2581 pbn_b2_bt_2_921600 },
2582 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
2583 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2584 pbn_b2_bt_2_921600 },
2585 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
2586 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2587 pbn_b2_bt_4_921600 },
2588 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
2589 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2590 pbn_b2_bt_4_921600 },
2591 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
2592 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2593 pbn_b2_bt_4_921600 },
2594 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
2595 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2597 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
2598 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2600 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
2601 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2603 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
2604 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2605 pbn_b0_bt_2_921600 },
2606 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
2607 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2608 pbn_b0_bt_2_921600 },
2609 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
2610 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2611 pbn_b0_bt_2_921600 },
2612 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
2613 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2614 pbn_b0_bt_4_921600 },
2615 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
2616 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2617 pbn_b0_bt_4_921600 },
2618 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
2619 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2620 pbn_b0_bt_4_921600 },
2621 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
2622 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2623 pbn_b0_bt_8_921600 },
2624 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
2625 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2626 pbn_b0_bt_8_921600 },
2627 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
2628 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2629 pbn_b0_bt_8_921600 },
2632 * Computone devices submitted by Doug McNash dmcnash@computone.com
2634 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2635 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
2636 0, 0, pbn_computone_4 },
2637 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2638 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
2639 0, 0, pbn_computone_8 },
2640 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2641 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
2642 0, 0, pbn_computone_6 },
2644 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
2645 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2647 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
2648 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
2649 pbn_b0_bt_1_921600 },
2652 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
2654 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
2655 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2656 pbn_b0_bt_8_115200 },
2657 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
2658 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2659 pbn_b0_bt_8_115200 },
2661 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
2662 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2663 pbn_b0_bt_2_115200 },
2664 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
2665 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2666 pbn_b0_bt_2_115200 },
2667 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
2668 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2669 pbn_b0_bt_2_115200 },
2670 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
2671 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2672 pbn_b0_bt_4_460800 },
2673 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
2674 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2675 pbn_b0_bt_4_460800 },
2676 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
2677 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2678 pbn_b0_bt_2_460800 },
2679 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
2680 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2681 pbn_b0_bt_2_460800 },
2682 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
2683 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2684 pbn_b0_bt_2_460800 },
2685 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
2686 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2687 pbn_b0_bt_1_115200 },
2688 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
2689 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2690 pbn_b0_bt_1_460800 },
2693 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
2694 * Cards are identified by their subsystem vendor IDs, which
2695 * (in hex) match the model number.
2697 * Note that JC140x are RS422/485 cards which require ox950
2698 * ACR = 0x10, and as such are not currently fully supported.
2700 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2701 0x1204, 0x0004, 0, 0,
2703 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2704 0x1208, 0x0004, 0, 0,
2706 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2707 0x1402, 0x0002, 0, 0,
2708 pbn_b0_2_921600 }, */
2709 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2710 0x1404, 0x0004, 0, 0,
2711 pbn_b0_4_921600 }, */
2712 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
2713 0x1208, 0x0004, 0, 0,
2717 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
2719 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
2720 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2724 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
2726 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
2727 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2731 * RAStel 2 port modem, gerg@moreton.com.au
2733 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
2734 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2735 pbn_b2_bt_2_115200 },
2738 * EKF addition for i960 Boards form EKF with serial port
2740 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
2741 0xE4BF, PCI_ANY_ID, 0, 0,
2745 * Xircom Cardbus/Ethernet combos
2747 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2748 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2751 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
2753 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
2754 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2758 * Untested PCI modems, sent in from various folks...
2762 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
2764 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
2765 0x1048, 0x1500, 0, 0,
2768 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
2775 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
2776 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
2778 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
2779 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2781 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
2782 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2785 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
2786 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2788 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
2789 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2791 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
2792 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2796 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2798 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2799 PCI_ANY_ID, PCI_ANY_ID,
2801 0, pbn_exar_XR17C152 },
2802 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2803 PCI_ANY_ID, PCI_ANY_ID,
2805 0, pbn_exar_XR17C154 },
2806 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2807 PCI_ANY_ID, PCI_ANY_ID,
2809 0, pbn_exar_XR17C158 },
2812 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
2814 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
2815 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2820 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
2821 PCI_ANY_ID, PCI_ANY_ID,
2823 pbn_b1_bt_1_115200 },
2828 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
2829 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
2834 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
2835 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
2838 * Perle PCI-RAS cards
2840 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
2841 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
2842 0, 0, pbn_b2_4_921600 },
2843 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
2844 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
2845 0, 0, pbn_b2_8_921600 },
2848 * Mainpine series cards: Fairly standard layout but fools
2849 * parts of the autodetect in some cases and uses otherwise
2850 * unmatched communications subclasses in the PCI Express case
2853 { /* RockForceDUO */
2854 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2855 PCI_VENDOR_ID_MAINPINE, 0x0200,
2856 0, 0, pbn_b0_2_115200 },
2857 { /* RockForceQUATRO */
2858 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2859 PCI_VENDOR_ID_MAINPINE, 0x0300,
2860 0, 0, pbn_b0_4_115200 },
2861 { /* RockForceDUO+ */
2862 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2863 PCI_VENDOR_ID_MAINPINE, 0x0400,
2864 0, 0, pbn_b0_2_115200 },
2865 { /* RockForceQUATRO+ */
2866 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2867 PCI_VENDOR_ID_MAINPINE, 0x0500,
2868 0, 0, pbn_b0_4_115200 },
2870 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2871 PCI_VENDOR_ID_MAINPINE, 0x0600,
2872 0, 0, pbn_b0_2_115200 },
2874 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2875 PCI_VENDOR_ID_MAINPINE, 0x0700,
2876 0, 0, pbn_b0_4_115200 },
2877 { /* RockForceOCTO+ */
2878 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2879 PCI_VENDOR_ID_MAINPINE, 0x0800,
2880 0, 0, pbn_b0_8_115200 },
2881 { /* RockForceDUO+ */
2882 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2883 PCI_VENDOR_ID_MAINPINE, 0x0C00,
2884 0, 0, pbn_b0_2_115200 },
2885 { /* RockForceQUARTRO+ */
2886 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2887 PCI_VENDOR_ID_MAINPINE, 0x0D00,
2888 0, 0, pbn_b0_4_115200 },
2889 { /* RockForceOCTO+ */
2890 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2891 PCI_VENDOR_ID_MAINPINE, 0x1D00,
2892 0, 0, pbn_b0_8_115200 },
2894 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2895 PCI_VENDOR_ID_MAINPINE, 0x2000,
2896 0, 0, pbn_b0_1_115200 },
2898 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2899 PCI_VENDOR_ID_MAINPINE, 0x2100,
2900 0, 0, pbn_b0_1_115200 },
2902 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2903 PCI_VENDOR_ID_MAINPINE, 0x2200,
2904 0, 0, pbn_b0_2_115200 },
2906 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2907 PCI_VENDOR_ID_MAINPINE, 0x2300,
2908 0, 0, pbn_b0_2_115200 },
2910 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2911 PCI_VENDOR_ID_MAINPINE, 0x2400,
2912 0, 0, pbn_b0_4_115200 },
2914 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2915 PCI_VENDOR_ID_MAINPINE, 0x2500,
2916 0, 0, pbn_b0_4_115200 },
2918 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2919 PCI_VENDOR_ID_MAINPINE, 0x2600,
2920 0, 0, pbn_b0_8_115200 },
2922 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2923 PCI_VENDOR_ID_MAINPINE, 0x2700,
2924 0, 0, pbn_b0_8_115200 },
2925 { /* IQ Express D1 */
2926 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2927 PCI_VENDOR_ID_MAINPINE, 0x3000,
2928 0, 0, pbn_b0_1_115200 },
2929 { /* IQ Express F1 */
2930 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2931 PCI_VENDOR_ID_MAINPINE, 0x3100,
2932 0, 0, pbn_b0_1_115200 },
2933 { /* IQ Express D2 */
2934 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2935 PCI_VENDOR_ID_MAINPINE, 0x3200,
2936 0, 0, pbn_b0_2_115200 },
2937 { /* IQ Express F2 */
2938 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2939 PCI_VENDOR_ID_MAINPINE, 0x3300,
2940 0, 0, pbn_b0_2_115200 },
2941 { /* IQ Express D4 */
2942 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2943 PCI_VENDOR_ID_MAINPINE, 0x3400,
2944 0, 0, pbn_b0_4_115200 },
2945 { /* IQ Express F4 */
2946 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2947 PCI_VENDOR_ID_MAINPINE, 0x3500,
2948 0, 0, pbn_b0_4_115200 },
2949 { /* IQ Express D8 */
2950 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2951 PCI_VENDOR_ID_MAINPINE, 0x3C00,
2952 0, 0, pbn_b0_8_115200 },
2953 { /* IQ Express F8 */
2954 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2955 PCI_VENDOR_ID_MAINPINE, 0x3D00,
2956 0, 0, pbn_b0_8_115200 },
2960 * PA Semi PA6T-1682M on-chip UART
2962 { PCI_VENDOR_ID_PASEMI, 0xa004,
2963 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2967 * ADDI-DATA GmbH communication cards <info@addi-data.com>
2969 { PCI_VENDOR_ID_ADDIDATA,
2970 PCI_DEVICE_ID_ADDIDATA_APCI7500,
2977 { PCI_VENDOR_ID_ADDIDATA,
2978 PCI_DEVICE_ID_ADDIDATA_APCI7420,
2985 { PCI_VENDOR_ID_ADDIDATA,
2986 PCI_DEVICE_ID_ADDIDATA_APCI7300,
2993 { PCI_VENDOR_ID_ADDIDATA_OLD,
2994 PCI_DEVICE_ID_ADDIDATA_APCI7800,
3001 { PCI_VENDOR_ID_ADDIDATA,
3002 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
3009 { PCI_VENDOR_ID_ADDIDATA,
3010 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
3017 { PCI_VENDOR_ID_ADDIDATA,
3018 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
3025 { PCI_VENDOR_ID_ADDIDATA,
3026 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
3033 { PCI_VENDOR_ID_ADDIDATA,
3034 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
3041 { PCI_VENDOR_ID_ADDIDATA,
3042 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
3049 { PCI_VENDOR_ID_ADDIDATA,
3050 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
3058 * These entries match devices with class COMMUNICATION_SERIAL,
3059 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
3061 { PCI_ANY_ID, PCI_ANY_ID,
3062 PCI_ANY_ID, PCI_ANY_ID,
3063 PCI_CLASS_COMMUNICATION_SERIAL << 8,
3064 0xffff00, pbn_default },
3065 { PCI_ANY_ID, PCI_ANY_ID,
3066 PCI_ANY_ID, PCI_ANY_ID,
3067 PCI_CLASS_COMMUNICATION_MODEM << 8,
3068 0xffff00, pbn_default },
3069 { PCI_ANY_ID, PCI_ANY_ID,
3070 PCI_ANY_ID, PCI_ANY_ID,
3071 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
3072 0xffff00, pbn_default },
3076 static struct pci_driver serial_pci_driver = {
3078 .probe = pciserial_init_one,
3079 .remove = __devexit_p(pciserial_remove_one),
3081 .suspend = pciserial_suspend_one,
3082 .resume = pciserial_resume_one,
3084 .id_table = serial_pci_tbl,
3087 static int __init serial8250_pci_init(void)
3089 return pci_register_driver(&serial_pci_driver);
3092 static void __exit serial8250_pci_exit(void)
3094 pci_unregister_driver(&serial_pci_driver);
3097 module_init(serial8250_pci_init);
3098 module_exit(serial8250_pci_exit);
3100 MODULE_LICENSE("GPL");
3101 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
3102 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);