2 * linux/drivers/char/8250_pci.c
4 * Probe module for 8250/16550-type PCI serial ports.
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
8 * Copyright (C) 2001 Russell King, All Rights Reserved.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
14 * $Id: 8250_pci.c,v 1.28 2002/11/02 11:14:18 rmk Exp $
16 #include <linux/module.h>
17 #include <linux/init.h>
18 #include <linux/pci.h>
19 #include <linux/sched.h>
20 #include <linux/string.h>
21 #include <linux/kernel.h>
22 #include <linux/slab.h>
23 #include <linux/delay.h>
24 #include <linux/tty.h>
25 #include <linux/serial_core.h>
26 #include <linux/8250_pci.h>
27 #include <linux/bitops.h>
29 #include <asm/byteorder.h>
34 #undef SERIAL_DEBUG_PCI
37 * init function returns:
38 * > 0 - number of ports
39 * = 0 - use board->num_ports
42 struct pci_serial_quirk {
47 int (*init)(struct pci_dev *dev);
48 int (*setup)(struct serial_private *, struct pciserial_board *,
49 struct uart_port *, int);
50 void (*exit)(struct pci_dev *dev);
53 #define PCI_NUM_BAR_RESOURCES 6
55 struct serial_private {
58 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
59 struct pci_serial_quirk *quirk;
63 static void moan_device(const char *str, struct pci_dev *dev)
65 printk(KERN_WARNING "%s: %s\n"
66 KERN_WARNING "Please send the output of lspci -vv, this\n"
67 KERN_WARNING "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
68 KERN_WARNING "manufacturer and name of serial board or\n"
69 KERN_WARNING "modem board to rmk+serial@arm.linux.org.uk.\n",
70 pci_name(dev), str, dev->vendor, dev->device,
71 dev->subsystem_vendor, dev->subsystem_device);
75 setup_port(struct serial_private *priv, struct uart_port *port,
76 int bar, int offset, int regshift)
78 struct pci_dev *dev = priv->dev;
79 unsigned long base, len;
81 if (bar >= PCI_NUM_BAR_RESOURCES)
84 base = pci_resource_start(dev, bar);
86 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
87 len = pci_resource_len(dev, bar);
89 if (!priv->remapped_bar[bar])
90 priv->remapped_bar[bar] = ioremap(base, len);
91 if (!priv->remapped_bar[bar])
94 port->iotype = UPIO_MEM;
96 port->mapbase = base + offset;
97 port->membase = priv->remapped_bar[bar] + offset;
98 port->regshift = regshift;
100 port->iotype = UPIO_PORT;
101 port->iobase = base + offset;
103 port->membase = NULL;
110 * AFAVLAB uses a different mixture of BARs and offsets
111 * Not that ugly ;) -- HW
114 afavlab_setup(struct serial_private *priv, struct pciserial_board *board,
115 struct uart_port *port, int idx)
117 unsigned int bar, offset = board->first_offset;
119 bar = FL_GET_BASE(board->flags);
124 offset += (idx - 4) * board->uart_offset;
127 return setup_port(priv, port, bar, offset, board->reg_shift);
131 * HP's Remote Management Console. The Diva chip came in several
132 * different versions. N-class, L2000 and A500 have two Diva chips, each
133 * with 3 UARTs (the third UART on the second chip is unused). Superdome
134 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
135 * one Diva chip, but it has been expanded to 5 UARTs.
137 static int pci_hp_diva_init(struct pci_dev *dev)
141 switch (dev->subsystem_device) {
142 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
143 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
144 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
145 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
148 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
151 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
154 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
155 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
164 * HP's Diva chip puts the 4th/5th serial port further out, and
165 * some serial ports are supposed to be hidden on certain models.
168 pci_hp_diva_setup(struct serial_private *priv, struct pciserial_board *board,
169 struct uart_port *port, int idx)
171 unsigned int offset = board->first_offset;
172 unsigned int bar = FL_GET_BASE(board->flags);
174 switch (priv->dev->subsystem_device) {
175 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
179 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
189 offset += idx * board->uart_offset;
191 return setup_port(priv, port, bar, offset, board->reg_shift);
195 * Added for EKF Intel i960 serial boards
197 static int pci_inteli960ni_init(struct pci_dev *dev)
199 unsigned long oldval;
201 if (!(dev->subsystem_device & 0x1000))
204 /* is firmware started? */
205 pci_read_config_dword(dev, 0x44, (void*) &oldval);
206 if (oldval == 0x00001000L) { /* RESET value */
207 printk(KERN_DEBUG "Local i960 firmware missing");
214 * Some PCI serial cards using the PLX 9050 PCI interface chip require
215 * that the card interrupt be explicitly enabled or disabled. This
216 * seems to be mainly needed on card using the PLX which also use I/O
219 static int pci_plx9050_init(struct pci_dev *dev)
224 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
225 moan_device("no memory in bar 0", dev);
230 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
231 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS) {
234 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
235 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS)) {
237 * As the megawolf cards have the int pins active
238 * high, and have 2 UART chips, both ints must be
239 * enabled on the 9050. Also, the UARTS are set in
240 * 16450 mode by default, so we have to enable the
241 * 16C950 'enhanced' mode so that we can use the
248 * enable/disable interrupts
250 p = ioremap(pci_resource_start(dev, 0), 0x80);
253 writel(irq_config, p + 0x4c);
256 * Read the register back to ensure that it took effect.
264 static void __devexit pci_plx9050_exit(struct pci_dev *dev)
268 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
274 p = ioremap(pci_resource_start(dev, 0), 0x80);
279 * Read the register back to ensure that it took effect.
286 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
288 sbs_setup(struct serial_private *priv, struct pciserial_board *board,
289 struct uart_port *port, int idx)
291 unsigned int bar, offset = board->first_offset;
296 /* first four channels map to 0, 0x100, 0x200, 0x300 */
297 offset += idx * board->uart_offset;
298 } else if (idx < 8) {
299 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
300 offset += idx * board->uart_offset + 0xC00;
301 } else /* we have only 8 ports on PMC-OCTALPRO */
304 return setup_port(priv, port, bar, offset, board->reg_shift);
308 * This does initialization for PMC OCTALPRO cards:
309 * maps the device memory, resets the UARTs (needed, bc
310 * if the module is removed and inserted again, the card
311 * is in the sleep mode) and enables global interrupt.
314 /* global control register offset for SBS PMC-OctalPro */
315 #define OCT_REG_CR_OFF 0x500
317 static int sbs_init(struct pci_dev *dev)
321 p = ioremap(pci_resource_start(dev, 0),pci_resource_len(dev,0));
325 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
326 writeb(0x10,p + OCT_REG_CR_OFF);
328 writeb(0x0,p + OCT_REG_CR_OFF);
330 /* Set bit-2 (INTENABLE) of Control Register */
331 writeb(0x4, p + OCT_REG_CR_OFF);
338 * Disables the global interrupt of PMC-OctalPro
341 static void __devexit sbs_exit(struct pci_dev *dev)
345 p = ioremap(pci_resource_start(dev, 0),pci_resource_len(dev,0));
347 writeb(0, p + OCT_REG_CR_OFF);
353 * SIIG serial cards have an PCI interface chip which also controls
354 * the UART clocking frequency. Each UART can be clocked independently
355 * (except cards equiped with 4 UARTs) and initial clocking settings
356 * are stored in the EEPROM chip. It can cause problems because this
357 * version of serial driver doesn't support differently clocked UART's
358 * on single PCI card. To prevent this, initialization functions set
359 * high frequency clocking for all UART's on given card. It is safe (I
360 * hope) because it doesn't touch EEPROM settings to prevent conflicts
361 * with other OSes (like M$ DOS).
363 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
365 * There is two family of SIIG serial cards with different PCI
366 * interface chip and different configuration methods:
367 * - 10x cards have control registers in IO and/or memory space;
368 * - 20x cards have control registers in standard PCI configuration space.
370 * Note: all 10x cards have PCI device ids 0x10..
371 * all 20x cards have PCI device ids 0x20..
373 * There are also Quartet Serial cards which use Oxford Semiconductor
374 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
376 * Note: some SIIG cards are probed by the parport_serial object.
379 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
380 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
382 static int pci_siig10x_init(struct pci_dev *dev)
387 switch (dev->device & 0xfff8) {
388 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
391 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
394 default: /* 1S1P, 4S */
399 p = ioremap(pci_resource_start(dev, 0), 0x80);
403 writew(readw(p + 0x28) & data, p + 0x28);
409 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
410 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
412 static int pci_siig20x_init(struct pci_dev *dev)
416 /* Change clock frequency for the first UART. */
417 pci_read_config_byte(dev, 0x6f, &data);
418 pci_write_config_byte(dev, 0x6f, data & 0xef);
420 /* If this card has 2 UART, we have to do the same with second UART. */
421 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
422 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
423 pci_read_config_byte(dev, 0x73, &data);
424 pci_write_config_byte(dev, 0x73, data & 0xef);
429 static int pci_siig_init(struct pci_dev *dev)
431 unsigned int type = dev->device & 0xff00;
434 return pci_siig10x_init(dev);
435 else if (type == 0x2000)
436 return pci_siig20x_init(dev);
438 moan_device("Unknown SIIG card", dev);
442 static int pci_siig_setup(struct serial_private *priv,
443 struct pciserial_board *board,
444 struct uart_port *port, int idx)
446 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
450 offset = (idx - 4) * 8;
453 return setup_port(priv, port, bar, offset, 0);
457 * Timedia has an explosion of boards, and to avoid the PCI table from
458 * growing *huge*, we use this function to collapse some 70 entries
459 * in the PCI table into one, for sanity's and compactness's sake.
461 static unsigned short timedia_single_port[] = {
462 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
465 static unsigned short timedia_dual_port[] = {
466 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
467 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
468 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
469 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
473 static unsigned short timedia_quad_port[] = {
474 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
475 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
476 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
480 static unsigned short timedia_eight_port[] = {
481 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
482 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
485 static const struct timedia_struct {
489 { 1, timedia_single_port },
490 { 2, timedia_dual_port },
491 { 4, timedia_quad_port },
492 { 8, timedia_eight_port },
496 static int pci_timedia_init(struct pci_dev *dev)
501 for (i = 0; timedia_data[i].num; i++) {
502 ids = timedia_data[i].ids;
503 for (j = 0; ids[j]; j++)
504 if (dev->subsystem_device == ids[j])
505 return timedia_data[i].num;
511 * Timedia/SUNIX uses a mixture of BARs and offsets
512 * Ugh, this is ugly as all hell --- TYT
515 pci_timedia_setup(struct serial_private *priv, struct pciserial_board *board,
516 struct uart_port *port, int idx)
518 unsigned int bar = 0, offset = board->first_offset;
525 offset = board->uart_offset;
532 offset = board->uart_offset;
541 return setup_port(priv, port, bar, offset, board->reg_shift);
545 * Some Titan cards are also a little weird
548 titan_400l_800l_setup(struct serial_private *priv,
549 struct pciserial_board *board,
550 struct uart_port *port, int idx)
552 unsigned int bar, offset = board->first_offset;
563 offset = (idx - 2) * board->uart_offset;
566 return setup_port(priv, port, bar, offset, board->reg_shift);
569 static int pci_xircom_init(struct pci_dev *dev)
575 static int pci_netmos_init(struct pci_dev *dev)
577 /* subdevice 0x00PS means <P> parallel, <S> serial */
578 unsigned int num_serial = dev->subsystem_device & 0xf;
586 pci_default_setup(struct serial_private *priv, struct pciserial_board *board,
587 struct uart_port *port, int idx)
589 unsigned int bar, offset = board->first_offset, maxnr;
591 bar = FL_GET_BASE(board->flags);
592 if (board->flags & FL_BASE_BARS)
595 offset += idx * board->uart_offset;
597 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
598 (board->reg_shift + 3);
600 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
603 return setup_port(priv, port, bar, offset, board->reg_shift);
606 /* This should be in linux/pci_ids.h */
607 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
608 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
609 #define PCI_DEVICE_ID_OCTPRO 0x0001
610 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
611 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
612 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
613 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
616 * Master list of serial port init/setup/exit quirks.
617 * This does not describe the general nature of the port.
618 * (ie, baud base, number and location of ports, etc)
620 * This list is ordered alphabetically by vendor then device.
621 * Specific entries must come before more generic entries.
623 static struct pci_serial_quirk pci_serial_quirks[] = {
625 * AFAVLAB cards - these may be called via parport_serial
626 * It is not clear whether this applies to all products.
629 .vendor = PCI_VENDOR_ID_AFAVLAB,
630 .device = PCI_ANY_ID,
631 .subvendor = PCI_ANY_ID,
632 .subdevice = PCI_ANY_ID,
633 .setup = afavlab_setup,
639 .vendor = PCI_VENDOR_ID_HP,
640 .device = PCI_DEVICE_ID_HP_DIVA,
641 .subvendor = PCI_ANY_ID,
642 .subdevice = PCI_ANY_ID,
643 .init = pci_hp_diva_init,
644 .setup = pci_hp_diva_setup,
650 .vendor = PCI_VENDOR_ID_INTEL,
651 .device = PCI_DEVICE_ID_INTEL_80960_RP,
653 .subdevice = PCI_ANY_ID,
654 .init = pci_inteli960ni_init,
655 .setup = pci_default_setup,
661 .vendor = PCI_VENDOR_ID_PANACOM,
662 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
663 .subvendor = PCI_ANY_ID,
664 .subdevice = PCI_ANY_ID,
665 .init = pci_plx9050_init,
666 .setup = pci_default_setup,
667 .exit = __devexit_p(pci_plx9050_exit),
670 .vendor = PCI_VENDOR_ID_PANACOM,
671 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
672 .subvendor = PCI_ANY_ID,
673 .subdevice = PCI_ANY_ID,
674 .init = pci_plx9050_init,
675 .setup = pci_default_setup,
676 .exit = __devexit_p(pci_plx9050_exit),
682 .vendor = PCI_VENDOR_ID_PLX,
683 .device = PCI_DEVICE_ID_PLX_9050,
684 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
685 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
686 .init = pci_plx9050_init,
687 .setup = pci_default_setup,
688 .exit = __devexit_p(pci_plx9050_exit),
691 .vendor = PCI_VENDOR_ID_PLX,
692 .device = PCI_DEVICE_ID_PLX_9050,
693 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
694 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
695 .init = pci_plx9050_init,
696 .setup = pci_default_setup,
697 .exit = __devexit_p(pci_plx9050_exit),
700 .vendor = PCI_VENDOR_ID_PLX,
701 .device = PCI_DEVICE_ID_PLX_ROMULUS,
702 .subvendor = PCI_VENDOR_ID_PLX,
703 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
704 .init = pci_plx9050_init,
705 .setup = pci_default_setup,
706 .exit = __devexit_p(pci_plx9050_exit),
709 * SBS Technologies, Inc., PMC-OCTALPRO 232
712 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
713 .device = PCI_DEVICE_ID_OCTPRO,
714 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
715 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
718 .exit = __devexit_p(sbs_exit),
721 * SBS Technologies, Inc., PMC-OCTALPRO 422
724 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
725 .device = PCI_DEVICE_ID_OCTPRO,
726 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
727 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
730 .exit = __devexit_p(sbs_exit),
733 * SBS Technologies, Inc., P-Octal 232
736 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
737 .device = PCI_DEVICE_ID_OCTPRO,
738 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
739 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
742 .exit = __devexit_p(sbs_exit),
745 * SBS Technologies, Inc., P-Octal 422
748 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
749 .device = PCI_DEVICE_ID_OCTPRO,
750 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
751 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
754 .exit = __devexit_p(sbs_exit),
757 * SIIG cards - these may be called via parport_serial
760 .vendor = PCI_VENDOR_ID_SIIG,
761 .device = PCI_ANY_ID,
762 .subvendor = PCI_ANY_ID,
763 .subdevice = PCI_ANY_ID,
764 .init = pci_siig_init,
765 .setup = pci_siig_setup,
771 .vendor = PCI_VENDOR_ID_TITAN,
772 .device = PCI_DEVICE_ID_TITAN_400L,
773 .subvendor = PCI_ANY_ID,
774 .subdevice = PCI_ANY_ID,
775 .setup = titan_400l_800l_setup,
778 .vendor = PCI_VENDOR_ID_TITAN,
779 .device = PCI_DEVICE_ID_TITAN_800L,
780 .subvendor = PCI_ANY_ID,
781 .subdevice = PCI_ANY_ID,
782 .setup = titan_400l_800l_setup,
788 .vendor = PCI_VENDOR_ID_TIMEDIA,
789 .device = PCI_DEVICE_ID_TIMEDIA_1889,
790 .subvendor = PCI_VENDOR_ID_TIMEDIA,
791 .subdevice = PCI_ANY_ID,
792 .init = pci_timedia_init,
793 .setup = pci_timedia_setup,
796 .vendor = PCI_VENDOR_ID_TIMEDIA,
797 .device = PCI_ANY_ID,
798 .subvendor = PCI_ANY_ID,
799 .subdevice = PCI_ANY_ID,
800 .setup = pci_timedia_setup,
806 .vendor = PCI_VENDOR_ID_XIRCOM,
807 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
808 .subvendor = PCI_ANY_ID,
809 .subdevice = PCI_ANY_ID,
810 .init = pci_xircom_init,
811 .setup = pci_default_setup,
814 * Netmos cards - these may be called via parport_serial
817 .vendor = PCI_VENDOR_ID_NETMOS,
818 .device = PCI_ANY_ID,
819 .subvendor = PCI_ANY_ID,
820 .subdevice = PCI_ANY_ID,
821 .init = pci_netmos_init,
822 .setup = pci_default_setup,
825 * Default "match everything" terminator entry
828 .vendor = PCI_ANY_ID,
829 .device = PCI_ANY_ID,
830 .subvendor = PCI_ANY_ID,
831 .subdevice = PCI_ANY_ID,
832 .setup = pci_default_setup,
836 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
838 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
841 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
843 struct pci_serial_quirk *quirk;
845 for (quirk = pci_serial_quirks; ; quirk++)
846 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
847 quirk_id_matches(quirk->device, dev->device) &&
848 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
849 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
854 static inline int get_pci_irq(struct pci_dev *dev,
855 struct pciserial_board *board)
857 if (board->flags & FL_NOIRQ)
864 * This is the configuration table for all of the PCI serial boards
865 * which we support. It is directly indexed by the pci_board_num_t enum
866 * value, which is encoded in the pci_device_id PCI probe table's
867 * driver_data member.
869 * The makeup of these names are:
870 * pbn_bn{_bt}_n_baud{_offsetinhex}
872 * bn = PCI BAR number
873 * bt = Index using PCI BARs
874 * n = number of serial ports
876 * offsetinhex = offset for each sequential port (in hex)
878 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
880 * Please note: in theory if n = 1, _bt infix should make no difference.
881 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
883 enum pci_board_num_t {
902 pbn_b0_2_1843200_200,
903 pbn_b0_4_1843200_200,
904 pbn_b0_8_1843200_200,
963 * Board-specific versions.
984 * uart_offset - the space between channels
985 * reg_shift - describes how the UART registers are mapped
986 * to PCI memory by the card.
987 * For example IER register on SBS, Inc. PMC-OctPro is located at
988 * offset 0x10 from the UART base, while UART_IER is defined as 1
989 * in include/linux/serial_reg.h,
990 * see first lines of serial_in() and serial_out() in 8250.c
993 static struct pciserial_board pci_boards[] __devinitdata = {
1000 [pbn_b0_1_115200] = {
1003 .base_baud = 115200,
1006 [pbn_b0_2_115200] = {
1009 .base_baud = 115200,
1012 [pbn_b0_4_115200] = {
1015 .base_baud = 115200,
1018 [pbn_b0_5_115200] = {
1021 .base_baud = 115200,
1025 [pbn_b0_1_921600] = {
1028 .base_baud = 921600,
1031 [pbn_b0_2_921600] = {
1034 .base_baud = 921600,
1037 [pbn_b0_4_921600] = {
1040 .base_baud = 921600,
1044 [pbn_b0_2_1130000] = {
1047 .base_baud = 1130000,
1051 [pbn_b0_4_1152000] = {
1054 .base_baud = 1152000,
1058 [pbn_b0_2_1843200] = {
1061 .base_baud = 1843200,
1064 [pbn_b0_4_1843200] = {
1067 .base_baud = 1843200,
1071 [pbn_b0_2_1843200_200] = {
1074 .base_baud = 1843200,
1075 .uart_offset = 0x200,
1077 [pbn_b0_4_1843200_200] = {
1080 .base_baud = 1843200,
1081 .uart_offset = 0x200,
1083 [pbn_b0_8_1843200_200] = {
1086 .base_baud = 1843200,
1087 .uart_offset = 0x200,
1090 [pbn_b0_bt_1_115200] = {
1091 .flags = FL_BASE0|FL_BASE_BARS,
1093 .base_baud = 115200,
1096 [pbn_b0_bt_2_115200] = {
1097 .flags = FL_BASE0|FL_BASE_BARS,
1099 .base_baud = 115200,
1102 [pbn_b0_bt_8_115200] = {
1103 .flags = FL_BASE0|FL_BASE_BARS,
1105 .base_baud = 115200,
1109 [pbn_b0_bt_1_460800] = {
1110 .flags = FL_BASE0|FL_BASE_BARS,
1112 .base_baud = 460800,
1115 [pbn_b0_bt_2_460800] = {
1116 .flags = FL_BASE0|FL_BASE_BARS,
1118 .base_baud = 460800,
1121 [pbn_b0_bt_4_460800] = {
1122 .flags = FL_BASE0|FL_BASE_BARS,
1124 .base_baud = 460800,
1128 [pbn_b0_bt_1_921600] = {
1129 .flags = FL_BASE0|FL_BASE_BARS,
1131 .base_baud = 921600,
1134 [pbn_b0_bt_2_921600] = {
1135 .flags = FL_BASE0|FL_BASE_BARS,
1137 .base_baud = 921600,
1140 [pbn_b0_bt_4_921600] = {
1141 .flags = FL_BASE0|FL_BASE_BARS,
1143 .base_baud = 921600,
1146 [pbn_b0_bt_8_921600] = {
1147 .flags = FL_BASE0|FL_BASE_BARS,
1149 .base_baud = 921600,
1153 [pbn_b1_1_115200] = {
1156 .base_baud = 115200,
1159 [pbn_b1_2_115200] = {
1162 .base_baud = 115200,
1165 [pbn_b1_4_115200] = {
1168 .base_baud = 115200,
1171 [pbn_b1_8_115200] = {
1174 .base_baud = 115200,
1178 [pbn_b1_1_921600] = {
1181 .base_baud = 921600,
1184 [pbn_b1_2_921600] = {
1187 .base_baud = 921600,
1190 [pbn_b1_4_921600] = {
1193 .base_baud = 921600,
1196 [pbn_b1_8_921600] = {
1199 .base_baud = 921600,
1202 [pbn_b1_2_1250000] = {
1205 .base_baud = 1250000,
1209 [pbn_b1_bt_2_921600] = {
1210 .flags = FL_BASE1|FL_BASE_BARS,
1212 .base_baud = 921600,
1216 [pbn_b1_1_1382400] = {
1219 .base_baud = 1382400,
1222 [pbn_b1_2_1382400] = {
1225 .base_baud = 1382400,
1228 [pbn_b1_4_1382400] = {
1231 .base_baud = 1382400,
1234 [pbn_b1_8_1382400] = {
1237 .base_baud = 1382400,
1241 [pbn_b2_1_115200] = {
1244 .base_baud = 115200,
1247 [pbn_b2_2_115200] = {
1250 .base_baud = 115200,
1253 [pbn_b2_8_115200] = {
1256 .base_baud = 115200,
1260 [pbn_b2_1_460800] = {
1263 .base_baud = 460800,
1266 [pbn_b2_4_460800] = {
1269 .base_baud = 460800,
1272 [pbn_b2_8_460800] = {
1275 .base_baud = 460800,
1278 [pbn_b2_16_460800] = {
1281 .base_baud = 460800,
1285 [pbn_b2_1_921600] = {
1288 .base_baud = 921600,
1291 [pbn_b2_4_921600] = {
1294 .base_baud = 921600,
1297 [pbn_b2_8_921600] = {
1300 .base_baud = 921600,
1304 [pbn_b2_bt_1_115200] = {
1305 .flags = FL_BASE2|FL_BASE_BARS,
1307 .base_baud = 115200,
1310 [pbn_b2_bt_2_115200] = {
1311 .flags = FL_BASE2|FL_BASE_BARS,
1313 .base_baud = 115200,
1316 [pbn_b2_bt_4_115200] = {
1317 .flags = FL_BASE2|FL_BASE_BARS,
1319 .base_baud = 115200,
1323 [pbn_b2_bt_2_921600] = {
1324 .flags = FL_BASE2|FL_BASE_BARS,
1326 .base_baud = 921600,
1329 [pbn_b2_bt_4_921600] = {
1330 .flags = FL_BASE2|FL_BASE_BARS,
1332 .base_baud = 921600,
1336 [pbn_b3_2_115200] = {
1339 .base_baud = 115200,
1342 [pbn_b3_4_115200] = {
1345 .base_baud = 115200,
1348 [pbn_b3_8_115200] = {
1351 .base_baud = 115200,
1356 * Entries following this are board-specific.
1365 .base_baud = 921600,
1366 .uart_offset = 0x400,
1370 .flags = FL_BASE2|FL_BASE_BARS,
1372 .base_baud = 921600,
1373 .uart_offset = 0x400,
1377 .flags = FL_BASE2|FL_BASE_BARS,
1379 .base_baud = 921600,
1380 .uart_offset = 0x400,
1384 [pbn_exsys_4055] = {
1387 .base_baud = 115200,
1391 /* I think this entry is broken - the first_offset looks wrong --rmk */
1392 [pbn_plx_romulus] = {
1395 .base_baud = 921600,
1396 .uart_offset = 8 << 2,
1398 .first_offset = 0x03,
1402 * This board uses the size of PCI Base region 0 to
1403 * signal now many ports are available
1406 .flags = FL_BASE0|FL_REGION_SZ_CAP,
1408 .base_baud = 115200,
1413 * EKF addition for i960 Boards form EKF with serial port.
1416 [pbn_intel_i960] = {
1419 .base_baud = 921600,
1420 .uart_offset = 8 << 2,
1422 .first_offset = 0x10000,
1425 .flags = FL_BASE0|FL_NOIRQ,
1427 .base_baud = 458333,
1430 .first_offset = 0x20178,
1434 * NEC Vrc-5074 (Nile 4) builtin UART.
1439 .base_baud = 520833,
1440 .uart_offset = 8 << 3,
1442 .first_offset = 0x300,
1446 * Computone - uses IOMEM.
1448 [pbn_computone_4] = {
1451 .base_baud = 921600,
1452 .uart_offset = 0x40,
1454 .first_offset = 0x200,
1456 [pbn_computone_6] = {
1459 .base_baud = 921600,
1460 .uart_offset = 0x40,
1462 .first_offset = 0x200,
1464 [pbn_computone_8] = {
1467 .base_baud = 921600,
1468 .uart_offset = 0x40,
1470 .first_offset = 0x200,
1475 .base_baud = 460800,
1480 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
1481 * Only basic 16550A support.
1482 * XR17C15[24] are not tested, but they should work.
1484 [pbn_exar_XR17C152] = {
1487 .base_baud = 921600,
1488 .uart_offset = 0x200,
1490 [pbn_exar_XR17C154] = {
1493 .base_baud = 921600,
1494 .uart_offset = 0x200,
1496 [pbn_exar_XR17C158] = {
1499 .base_baud = 921600,
1500 .uart_offset = 0x200,
1505 * Given a complete unknown PCI device, try to use some heuristics to
1506 * guess what the configuration might be, based on the pitiful PCI
1507 * serial specs. Returns 0 on success, 1 on failure.
1509 static int __devinit
1510 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
1512 int num_iomem, num_port, first_port = -1, i;
1515 * If it is not a communications device or the programming
1516 * interface is greater than 6, give up.
1518 * (Should we try to make guesses for multiport serial devices
1521 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
1522 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
1523 (dev->class & 0xff) > 6)
1526 num_iomem = num_port = 0;
1527 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1528 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
1530 if (first_port == -1)
1533 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
1538 * If there is 1 or 0 iomem regions, and exactly one port,
1539 * use it. We guess the number of ports based on the IO
1542 if (num_iomem <= 1 && num_port == 1) {
1543 board->flags = first_port;
1544 board->num_ports = pci_resource_len(dev, first_port) / 8;
1549 * Now guess if we've got a board which indexes by BARs.
1550 * Each IO BAR should be 8 bytes, and they should follow
1555 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1556 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
1557 pci_resource_len(dev, i) == 8 &&
1558 (first_port == -1 || (first_port + num_port) == i)) {
1560 if (first_port == -1)
1566 board->flags = first_port | FL_BASE_BARS;
1567 board->num_ports = num_port;
1575 serial_pci_matches(struct pciserial_board *board,
1576 struct pciserial_board *guessed)
1579 board->num_ports == guessed->num_ports &&
1580 board->base_baud == guessed->base_baud &&
1581 board->uart_offset == guessed->uart_offset &&
1582 board->reg_shift == guessed->reg_shift &&
1583 board->first_offset == guessed->first_offset;
1586 struct serial_private *
1587 pciserial_init_ports(struct pci_dev *dev, struct pciserial_board *board)
1589 struct uart_port serial_port;
1590 struct serial_private *priv;
1591 struct pci_serial_quirk *quirk;
1592 int rc, nr_ports, i;
1594 nr_ports = board->num_ports;
1597 * Find an init and setup quirks.
1599 quirk = find_quirk(dev);
1602 * Run the new-style initialization function.
1603 * The initialization function returns:
1605 * 0 - use board->num_ports
1606 * >0 - number of ports
1609 rc = quirk->init(dev);
1618 priv = kmalloc(sizeof(struct serial_private) +
1619 sizeof(unsigned int) * nr_ports,
1622 priv = ERR_PTR(-ENOMEM);
1626 memset(priv, 0, sizeof(struct serial_private) +
1627 sizeof(unsigned int) * nr_ports);
1630 priv->quirk = quirk;
1632 memset(&serial_port, 0, sizeof(struct uart_port));
1633 serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
1634 serial_port.uartclk = board->base_baud * 16;
1635 serial_port.irq = get_pci_irq(dev, board);
1636 serial_port.dev = &dev->dev;
1638 for (i = 0; i < nr_ports; i++) {
1639 if (quirk->setup(priv, board, &serial_port, i))
1642 #ifdef SERIAL_DEBUG_PCI
1643 printk("Setup PCI port: port %x, irq %d, type %d\n",
1644 serial_port.iobase, serial_port.irq, serial_port.iotype);
1647 priv->line[i] = serial8250_register_port(&serial_port);
1648 if (priv->line[i] < 0) {
1649 printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
1664 EXPORT_SYMBOL_GPL(pciserial_init_ports);
1666 void pciserial_remove_ports(struct serial_private *priv)
1668 struct pci_serial_quirk *quirk;
1671 for (i = 0; i < priv->nr; i++)
1672 serial8250_unregister_port(priv->line[i]);
1674 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1675 if (priv->remapped_bar[i])
1676 iounmap(priv->remapped_bar[i]);
1677 priv->remapped_bar[i] = NULL;
1681 * Find the exit quirks.
1683 quirk = find_quirk(priv->dev);
1685 quirk->exit(priv->dev);
1689 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
1691 void pciserial_suspend_ports(struct serial_private *priv)
1695 for (i = 0; i < priv->nr; i++)
1696 if (priv->line[i] >= 0)
1697 serial8250_suspend_port(priv->line[i]);
1699 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
1701 void pciserial_resume_ports(struct serial_private *priv)
1706 * Ensure that the board is correctly configured.
1708 if (priv->quirk->init)
1709 priv->quirk->init(priv->dev);
1711 for (i = 0; i < priv->nr; i++)
1712 if (priv->line[i] >= 0)
1713 serial8250_resume_port(priv->line[i]);
1715 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
1718 * Probe one serial board. Unfortunately, there is no rhyme nor reason
1719 * to the arrangement of serial ports on a PCI card.
1721 static int __devinit
1722 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
1724 struct serial_private *priv;
1725 struct pciserial_board *board, tmp;
1728 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
1729 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
1734 board = &pci_boards[ent->driver_data];
1736 rc = pci_enable_device(dev);
1740 if (ent->driver_data == pbn_default) {
1742 * Use a copy of the pci_board entry for this;
1743 * avoid changing entries in the table.
1745 memcpy(&tmp, board, sizeof(struct pciserial_board));
1749 * We matched one of our class entries. Try to
1750 * determine the parameters of this board.
1752 rc = serial_pci_guess_board(dev, board);
1757 * We matched an explicit entry. If we are able to
1758 * detect this boards settings with our heuristic,
1759 * then we no longer need this entry.
1761 memcpy(&tmp, &pci_boards[pbn_default],
1762 sizeof(struct pciserial_board));
1763 rc = serial_pci_guess_board(dev, &tmp);
1764 if (rc == 0 && serial_pci_matches(board, &tmp))
1765 moan_device("Redundant entry in serial pci_table.",
1769 priv = pciserial_init_ports(dev, board);
1770 if (!IS_ERR(priv)) {
1771 pci_set_drvdata(dev, priv);
1778 pci_disable_device(dev);
1782 static void __devexit pciserial_remove_one(struct pci_dev *dev)
1784 struct serial_private *priv = pci_get_drvdata(dev);
1786 pci_set_drvdata(dev, NULL);
1788 pciserial_remove_ports(priv);
1790 pci_disable_device(dev);
1793 static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
1795 struct serial_private *priv = pci_get_drvdata(dev);
1798 pciserial_suspend_ports(priv);
1800 pci_save_state(dev);
1801 pci_set_power_state(dev, pci_choose_state(dev, state));
1805 static int pciserial_resume_one(struct pci_dev *dev)
1807 struct serial_private *priv = pci_get_drvdata(dev);
1809 pci_set_power_state(dev, PCI_D0);
1810 pci_restore_state(dev);
1814 * The device may have been disabled. Re-enable it.
1816 pci_enable_device(dev);
1818 pciserial_resume_ports(priv);
1823 static struct pci_device_id serial_pci_tbl[] = {
1824 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1825 PCI_SUBVENDOR_ID_CONNECT_TECH,
1826 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
1828 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1829 PCI_SUBVENDOR_ID_CONNECT_TECH,
1830 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
1832 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1833 PCI_SUBVENDOR_ID_CONNECT_TECH,
1834 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
1836 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1837 PCI_SUBVENDOR_ID_CONNECT_TECH,
1838 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
1840 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1841 PCI_SUBVENDOR_ID_CONNECT_TECH,
1842 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
1844 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1845 PCI_SUBVENDOR_ID_CONNECT_TECH,
1846 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
1848 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1849 PCI_SUBVENDOR_ID_CONNECT_TECH,
1850 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
1852 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1853 PCI_SUBVENDOR_ID_CONNECT_TECH,
1854 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
1856 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1857 PCI_SUBVENDOR_ID_CONNECT_TECH,
1858 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
1860 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1861 PCI_SUBVENDOR_ID_CONNECT_TECH,
1862 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
1864 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1865 PCI_SUBVENDOR_ID_CONNECT_TECH,
1866 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
1868 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1869 PCI_SUBVENDOR_ID_CONNECT_TECH,
1870 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
1872 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1873 PCI_SUBVENDOR_ID_CONNECT_TECH,
1874 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
1876 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1877 PCI_SUBVENDOR_ID_CONNECT_TECH,
1878 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
1880 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1881 PCI_SUBVENDOR_ID_CONNECT_TECH,
1882 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
1884 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
1885 PCI_SUBVENDOR_ID_CONNECT_TECH,
1886 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
1888 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
1889 PCI_SUBVENDOR_ID_CONNECT_TECH,
1890 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
1892 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
1893 PCI_VENDOR_ID_AFAVLAB,
1894 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
1896 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
1897 PCI_SUBVENDOR_ID_CONNECT_TECH,
1898 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
1899 pbn_b0_2_1843200_200 },
1900 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
1901 PCI_SUBVENDOR_ID_CONNECT_TECH,
1902 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
1903 pbn_b0_4_1843200_200 },
1904 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
1905 PCI_SUBVENDOR_ID_CONNECT_TECH,
1906 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
1907 pbn_b0_8_1843200_200 },
1908 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
1909 PCI_SUBVENDOR_ID_CONNECT_TECH,
1910 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
1911 pbn_b0_2_1843200_200 },
1912 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
1913 PCI_SUBVENDOR_ID_CONNECT_TECH,
1914 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
1915 pbn_b0_4_1843200_200 },
1916 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
1917 PCI_SUBVENDOR_ID_CONNECT_TECH,
1918 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
1919 pbn_b0_8_1843200_200 },
1920 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
1921 PCI_SUBVENDOR_ID_CONNECT_TECH,
1922 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
1923 pbn_b0_2_1843200_200 },
1924 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
1925 PCI_SUBVENDOR_ID_CONNECT_TECH,
1926 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
1927 pbn_b0_4_1843200_200 },
1928 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
1929 PCI_SUBVENDOR_ID_CONNECT_TECH,
1930 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
1931 pbn_b0_8_1843200_200 },
1932 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
1933 PCI_SUBVENDOR_ID_CONNECT_TECH,
1934 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
1935 pbn_b0_2_1843200_200 },
1936 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
1937 PCI_SUBVENDOR_ID_CONNECT_TECH,
1938 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
1939 pbn_b0_4_1843200_200 },
1940 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
1941 PCI_SUBVENDOR_ID_CONNECT_TECH,
1942 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
1943 pbn_b0_8_1843200_200 },
1945 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
1946 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1947 pbn_b2_bt_1_115200 },
1948 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
1949 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1950 pbn_b2_bt_2_115200 },
1951 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
1952 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1953 pbn_b2_bt_4_115200 },
1954 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
1955 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1956 pbn_b2_bt_2_115200 },
1957 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
1958 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1959 pbn_b2_bt_4_115200 },
1960 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
1961 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1963 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
1964 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1967 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
1968 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1969 pbn_b2_bt_2_115200 },
1970 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
1971 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1972 pbn_b2_bt_2_921600 },
1974 * VScom SPCOM800, from sl@s.pl
1976 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
1977 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1979 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
1980 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1982 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1983 PCI_SUBVENDOR_ID_KEYSPAN,
1984 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
1986 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
1987 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1989 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
1990 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1992 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1993 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1994 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
1996 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1997 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1998 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
2000 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2001 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2002 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
2004 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2005 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2006 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
2008 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2009 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
2010 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
2012 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2013 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
2014 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
2016 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2017 PCI_SUBVENDOR_ID_EXSYS,
2018 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
2021 * Megawolf Romulus PCI Serial Card, from Mike Hudson
2024 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
2025 0x10b5, 0x106a, 0, 0,
2027 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
2028 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2030 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
2031 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2033 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
2034 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2036 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
2037 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2039 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
2040 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4, 0, 0,
2042 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2043 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL, 0, 0,
2047 * The below card is a little controversial since it is the
2048 * subject of a PCI vendor/device ID clash. (See
2049 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
2050 * For now just used the hex ID 0x950a.
2052 { PCI_VENDOR_ID_OXSEMI, 0x950a,
2053 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2055 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2056 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2058 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
2059 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2060 pbn_b0_bt_2_921600 },
2063 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
2064 * from skokodyn@yahoo.com
2066 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2067 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
2069 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2070 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
2072 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2073 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
2075 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2076 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
2080 * Digitan DS560-558, from jimd@esoft.com
2082 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
2083 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2087 * Titan Electronic cards
2088 * The 400L and 800L have a custom setup quirk.
2090 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
2091 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2093 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
2094 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2096 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
2097 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2099 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
2100 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2102 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
2103 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2105 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
2106 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2107 pbn_b1_bt_2_921600 },
2108 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
2109 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2110 pbn_b0_bt_4_921600 },
2111 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
2112 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2113 pbn_b0_bt_8_921600 },
2115 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
2116 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2118 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
2119 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2121 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
2122 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2124 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
2125 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2126 pbn_b2_bt_2_921600 },
2127 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
2128 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2129 pbn_b2_bt_2_921600 },
2130 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
2131 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2132 pbn_b2_bt_2_921600 },
2133 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
2134 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2135 pbn_b2_bt_4_921600 },
2136 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
2137 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2138 pbn_b2_bt_4_921600 },
2139 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
2140 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2141 pbn_b2_bt_4_921600 },
2142 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
2143 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2145 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
2146 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2148 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
2149 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2151 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
2152 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2153 pbn_b0_bt_2_921600 },
2154 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
2155 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2156 pbn_b0_bt_2_921600 },
2157 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
2158 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2159 pbn_b0_bt_2_921600 },
2160 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
2161 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2162 pbn_b0_bt_4_921600 },
2163 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
2164 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2165 pbn_b0_bt_4_921600 },
2166 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
2167 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2168 pbn_b0_bt_4_921600 },
2169 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
2170 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2171 pbn_b0_bt_8_921600 },
2172 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
2173 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2174 pbn_b0_bt_8_921600 },
2175 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
2176 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2177 pbn_b0_bt_8_921600 },
2180 * Computone devices submitted by Doug McNash dmcnash@computone.com
2182 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2183 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
2184 0, 0, pbn_computone_4 },
2185 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2186 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
2187 0, 0, pbn_computone_8 },
2188 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2189 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
2190 0, 0, pbn_computone_6 },
2192 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
2193 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2195 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
2196 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
2197 pbn_b0_bt_1_921600 },
2200 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
2202 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
2203 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2204 pbn_b0_bt_8_115200 },
2205 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
2206 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2207 pbn_b0_bt_8_115200 },
2209 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
2210 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2211 pbn_b0_bt_2_115200 },
2212 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
2213 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2214 pbn_b0_bt_2_115200 },
2215 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
2216 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2217 pbn_b0_bt_2_115200 },
2218 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
2219 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2220 pbn_b0_bt_4_460800 },
2221 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
2222 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2223 pbn_b0_bt_4_460800 },
2224 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
2225 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2226 pbn_b0_bt_2_460800 },
2227 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
2228 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2229 pbn_b0_bt_2_460800 },
2230 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
2231 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2232 pbn_b0_bt_2_460800 },
2233 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
2234 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2235 pbn_b0_bt_1_115200 },
2236 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
2237 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2238 pbn_b0_bt_1_460800 },
2241 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
2243 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
2244 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2248 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
2250 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
2251 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2255 * RAStel 2 port modem, gerg@moreton.com.au
2257 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
2258 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2259 pbn_b2_bt_2_115200 },
2262 * EKF addition for i960 Boards form EKF with serial port
2264 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
2265 0xE4BF, PCI_ANY_ID, 0, 0,
2269 * Xircom Cardbus/Ethernet combos
2271 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2272 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2275 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
2277 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
2278 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2282 * Untested PCI modems, sent in from various folks...
2286 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
2288 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
2289 0x1048, 0x1500, 0, 0,
2292 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
2299 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
2300 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
2302 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
2303 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2305 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
2306 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2310 * NEC Vrc-5074 (Nile 4) builtin UART.
2312 { PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_NILE4,
2313 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2316 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
2317 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2319 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
2320 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2322 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
2323 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2327 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2329 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2330 PCI_ANY_ID, PCI_ANY_ID,
2332 0, pbn_exar_XR17C152 },
2333 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2334 PCI_ANY_ID, PCI_ANY_ID,
2336 0, pbn_exar_XR17C154 },
2337 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2338 PCI_ANY_ID, PCI_ANY_ID,
2340 0, pbn_exar_XR17C158 },
2343 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
2345 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
2346 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2352 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
2353 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
2357 * These entries match devices with class COMMUNICATION_SERIAL,
2358 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
2360 { PCI_ANY_ID, PCI_ANY_ID,
2361 PCI_ANY_ID, PCI_ANY_ID,
2362 PCI_CLASS_COMMUNICATION_SERIAL << 8,
2363 0xffff00, pbn_default },
2364 { PCI_ANY_ID, PCI_ANY_ID,
2365 PCI_ANY_ID, PCI_ANY_ID,
2366 PCI_CLASS_COMMUNICATION_MODEM << 8,
2367 0xffff00, pbn_default },
2368 { PCI_ANY_ID, PCI_ANY_ID,
2369 PCI_ANY_ID, PCI_ANY_ID,
2370 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
2371 0xffff00, pbn_default },
2375 static struct pci_driver serial_pci_driver = {
2377 .probe = pciserial_init_one,
2378 .remove = __devexit_p(pciserial_remove_one),
2379 .suspend = pciserial_suspend_one,
2380 .resume = pciserial_resume_one,
2381 .id_table = serial_pci_tbl,
2384 static int __init serial8250_pci_init(void)
2386 return pci_register_driver(&serial_pci_driver);
2389 static void __exit serial8250_pci_exit(void)
2391 pci_unregister_driver(&serial_pci_driver);
2394 module_init(serial8250_pci_init);
2395 module_exit(serial8250_pci_exit);
2397 MODULE_LICENSE("GPL");
2398 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
2399 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);