2 * linux/drivers/char/8250_pci.c
4 * Probe module for 8250/16550-type PCI serial ports.
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
8 * Copyright (C) 2001 Russell King, All Rights Reserved.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
14 * $Id: 8250_pci.c,v 1.28 2002/11/02 11:14:18 rmk Exp $
16 #include <linux/module.h>
17 #include <linux/init.h>
18 #include <linux/pci.h>
19 #include <linux/sched.h>
20 #include <linux/string.h>
21 #include <linux/kernel.h>
22 #include <linux/slab.h>
23 #include <linux/delay.h>
24 #include <linux/tty.h>
25 #include <linux/serial_core.h>
26 #include <linux/8250_pci.h>
27 #include <linux/bitops.h>
29 #include <asm/byteorder.h>
34 #undef SERIAL_DEBUG_PCI
37 * init function returns:
38 * > 0 - number of ports
39 * = 0 - use board->num_ports
42 struct pci_serial_quirk {
47 int (*init)(struct pci_dev *dev);
48 int (*setup)(struct serial_private *, struct pciserial_board *,
49 struct uart_port *, int);
50 void (*exit)(struct pci_dev *dev);
53 #define PCI_NUM_BAR_RESOURCES 6
55 struct serial_private {
58 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
59 struct pci_serial_quirk *quirk;
63 static void moan_device(const char *str, struct pci_dev *dev)
65 printk(KERN_WARNING "%s: %s\n"
66 KERN_WARNING "Please send the output of lspci -vv, this\n"
67 KERN_WARNING "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
68 KERN_WARNING "manufacturer and name of serial board or\n"
69 KERN_WARNING "modem board to rmk+serial@arm.linux.org.uk.\n",
70 pci_name(dev), str, dev->vendor, dev->device,
71 dev->subsystem_vendor, dev->subsystem_device);
75 setup_port(struct serial_private *priv, struct uart_port *port,
76 int bar, int offset, int regshift)
78 struct pci_dev *dev = priv->dev;
79 unsigned long base, len;
81 if (bar >= PCI_NUM_BAR_RESOURCES)
84 base = pci_resource_start(dev, bar);
86 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
87 len = pci_resource_len(dev, bar);
89 if (!priv->remapped_bar[bar])
90 priv->remapped_bar[bar] = ioremap(base, len);
91 if (!priv->remapped_bar[bar])
94 port->iotype = UPIO_MEM;
96 port->mapbase = base + offset;
97 port->membase = priv->remapped_bar[bar] + offset;
98 port->regshift = regshift;
100 port->iotype = UPIO_PORT;
101 port->iobase = base + offset;
103 port->membase = NULL;
110 * AFAVLAB uses a different mixture of BARs and offsets
111 * Not that ugly ;) -- HW
114 afavlab_setup(struct serial_private *priv, struct pciserial_board *board,
115 struct uart_port *port, int idx)
117 unsigned int bar, offset = board->first_offset;
119 bar = FL_GET_BASE(board->flags);
124 offset += (idx - 4) * board->uart_offset;
127 return setup_port(priv, port, bar, offset, board->reg_shift);
131 * HP's Remote Management Console. The Diva chip came in several
132 * different versions. N-class, L2000 and A500 have two Diva chips, each
133 * with 3 UARTs (the third UART on the second chip is unused). Superdome
134 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
135 * one Diva chip, but it has been expanded to 5 UARTs.
137 static int __devinit pci_hp_diva_init(struct pci_dev *dev)
141 switch (dev->subsystem_device) {
142 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
143 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
144 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
145 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
148 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
151 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
154 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
155 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
164 * HP's Diva chip puts the 4th/5th serial port further out, and
165 * some serial ports are supposed to be hidden on certain models.
168 pci_hp_diva_setup(struct serial_private *priv, struct pciserial_board *board,
169 struct uart_port *port, int idx)
171 unsigned int offset = board->first_offset;
172 unsigned int bar = FL_GET_BASE(board->flags);
174 switch (priv->dev->subsystem_device) {
175 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
179 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
189 offset += idx * board->uart_offset;
191 return setup_port(priv, port, bar, offset, board->reg_shift);
195 * Added for EKF Intel i960 serial boards
197 static int __devinit pci_inteli960ni_init(struct pci_dev *dev)
199 unsigned long oldval;
201 if (!(dev->subsystem_device & 0x1000))
204 /* is firmware started? */
205 pci_read_config_dword(dev, 0x44, (void*) &oldval);
206 if (oldval == 0x00001000L) { /* RESET value */
207 printk(KERN_DEBUG "Local i960 firmware missing");
214 * Some PCI serial cards using the PLX 9050 PCI interface chip require
215 * that the card interrupt be explicitly enabled or disabled. This
216 * seems to be mainly needed on card using the PLX which also use I/O
219 static int __devinit pci_plx9050_init(struct pci_dev *dev)
224 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
225 moan_device("no memory in bar 0", dev);
230 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
231 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS) {
234 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
235 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS)) {
237 * As the megawolf cards have the int pins active
238 * high, and have 2 UART chips, both ints must be
239 * enabled on the 9050. Also, the UARTS are set in
240 * 16450 mode by default, so we have to enable the
241 * 16C950 'enhanced' mode so that we can use the
248 * enable/disable interrupts
250 p = ioremap(pci_resource_start(dev, 0), 0x80);
253 writel(irq_config, p + 0x4c);
256 * Read the register back to ensure that it took effect.
264 static void __devexit pci_plx9050_exit(struct pci_dev *dev)
268 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
274 p = ioremap(pci_resource_start(dev, 0), 0x80);
279 * Read the register back to ensure that it took effect.
286 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
288 sbs_setup(struct serial_private *priv, struct pciserial_board *board,
289 struct uart_port *port, int idx)
291 unsigned int bar, offset = board->first_offset;
296 /* first four channels map to 0, 0x100, 0x200, 0x300 */
297 offset += idx * board->uart_offset;
298 } else if (idx < 8) {
299 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
300 offset += idx * board->uart_offset + 0xC00;
301 } else /* we have only 8 ports on PMC-OCTALPRO */
304 return setup_port(priv, port, bar, offset, board->reg_shift);
308 * This does initialization for PMC OCTALPRO cards:
309 * maps the device memory, resets the UARTs (needed, bc
310 * if the module is removed and inserted again, the card
311 * is in the sleep mode) and enables global interrupt.
314 /* global control register offset for SBS PMC-OctalPro */
315 #define OCT_REG_CR_OFF 0x500
317 static int __devinit sbs_init(struct pci_dev *dev)
321 p = ioremap(pci_resource_start(dev, 0),pci_resource_len(dev,0));
325 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
326 writeb(0x10,p + OCT_REG_CR_OFF);
328 writeb(0x0,p + OCT_REG_CR_OFF);
330 /* Set bit-2 (INTENABLE) of Control Register */
331 writeb(0x4, p + OCT_REG_CR_OFF);
338 * Disables the global interrupt of PMC-OctalPro
341 static void __devexit sbs_exit(struct pci_dev *dev)
345 p = ioremap(pci_resource_start(dev, 0),pci_resource_len(dev,0));
347 writeb(0, p + OCT_REG_CR_OFF);
353 * SIIG serial cards have an PCI interface chip which also controls
354 * the UART clocking frequency. Each UART can be clocked independently
355 * (except cards equiped with 4 UARTs) and initial clocking settings
356 * are stored in the EEPROM chip. It can cause problems because this
357 * version of serial driver doesn't support differently clocked UART's
358 * on single PCI card. To prevent this, initialization functions set
359 * high frequency clocking for all UART's on given card. It is safe (I
360 * hope) because it doesn't touch EEPROM settings to prevent conflicts
361 * with other OSes (like M$ DOS).
363 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
365 * There is two family of SIIG serial cards with different PCI
366 * interface chip and different configuration methods:
367 * - 10x cards have control registers in IO and/or memory space;
368 * - 20x cards have control registers in standard PCI configuration space.
370 * Note: all 10x cards have PCI device ids 0x10..
371 * all 20x cards have PCI device ids 0x20..
373 * There are also Quartet Serial cards which use Oxford Semiconductor
374 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
376 * Note: some SIIG cards are probed by the parport_serial object.
379 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
380 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
382 static int pci_siig10x_init(struct pci_dev *dev)
387 switch (dev->device & 0xfff8) {
388 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
391 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
394 default: /* 1S1P, 4S */
399 p = ioremap(pci_resource_start(dev, 0), 0x80);
403 writew(readw(p + 0x28) & data, p + 0x28);
409 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
410 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
412 static int pci_siig20x_init(struct pci_dev *dev)
416 /* Change clock frequency for the first UART. */
417 pci_read_config_byte(dev, 0x6f, &data);
418 pci_write_config_byte(dev, 0x6f, data & 0xef);
420 /* If this card has 2 UART, we have to do the same with second UART. */
421 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
422 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
423 pci_read_config_byte(dev, 0x73, &data);
424 pci_write_config_byte(dev, 0x73, data & 0xef);
429 static int pci_siig_init(struct pci_dev *dev)
431 unsigned int type = dev->device & 0xff00;
434 return pci_siig10x_init(dev);
435 else if (type == 0x2000)
436 return pci_siig20x_init(dev);
438 moan_device("Unknown SIIG card", dev);
443 * Timedia has an explosion of boards, and to avoid the PCI table from
444 * growing *huge*, we use this function to collapse some 70 entries
445 * in the PCI table into one, for sanity's and compactness's sake.
447 static unsigned short timedia_single_port[] = {
448 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
451 static unsigned short timedia_dual_port[] = {
452 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
453 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
454 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
455 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
459 static unsigned short timedia_quad_port[] = {
460 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
461 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
462 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
466 static unsigned short timedia_eight_port[] = {
467 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
468 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
471 static const struct timedia_struct {
475 { 1, timedia_single_port },
476 { 2, timedia_dual_port },
477 { 4, timedia_quad_port },
478 { 8, timedia_eight_port },
482 static int __devinit pci_timedia_init(struct pci_dev *dev)
487 for (i = 0; timedia_data[i].num; i++) {
488 ids = timedia_data[i].ids;
489 for (j = 0; ids[j]; j++)
490 if (dev->subsystem_device == ids[j])
491 return timedia_data[i].num;
497 * Timedia/SUNIX uses a mixture of BARs and offsets
498 * Ugh, this is ugly as all hell --- TYT
501 pci_timedia_setup(struct serial_private *priv, struct pciserial_board *board,
502 struct uart_port *port, int idx)
504 unsigned int bar = 0, offset = board->first_offset;
511 offset = board->uart_offset;
518 offset = board->uart_offset;
527 return setup_port(priv, port, bar, offset, board->reg_shift);
531 * Some Titan cards are also a little weird
534 titan_400l_800l_setup(struct serial_private *priv,
535 struct pciserial_board *board,
536 struct uart_port *port, int idx)
538 unsigned int bar, offset = board->first_offset;
549 offset = (idx - 2) * board->uart_offset;
552 return setup_port(priv, port, bar, offset, board->reg_shift);
555 static int __devinit pci_xircom_init(struct pci_dev *dev)
561 static int __devinit pci_netmos_init(struct pci_dev *dev)
563 /* subdevice 0x00PS means <P> parallel, <S> serial */
564 unsigned int num_serial = dev->subsystem_device & 0xf;
572 pci_default_setup(struct serial_private *priv, struct pciserial_board *board,
573 struct uart_port *port, int idx)
575 unsigned int bar, offset = board->first_offset, maxnr;
577 bar = FL_GET_BASE(board->flags);
578 if (board->flags & FL_BASE_BARS)
581 offset += idx * board->uart_offset;
583 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) /
584 (8 << board->reg_shift);
586 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
589 return setup_port(priv, port, bar, offset, board->reg_shift);
592 /* This should be in linux/pci_ids.h */
593 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
594 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
595 #define PCI_DEVICE_ID_OCTPRO 0x0001
596 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
597 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
598 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
599 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
602 * Master list of serial port init/setup/exit quirks.
603 * This does not describe the general nature of the port.
604 * (ie, baud base, number and location of ports, etc)
606 * This list is ordered alphabetically by vendor then device.
607 * Specific entries must come before more generic entries.
609 static struct pci_serial_quirk pci_serial_quirks[] = {
612 * It is not clear whether this applies to all products.
615 .vendor = PCI_VENDOR_ID_AFAVLAB,
616 .device = PCI_ANY_ID,
617 .subvendor = PCI_ANY_ID,
618 .subdevice = PCI_ANY_ID,
619 .setup = afavlab_setup,
625 .vendor = PCI_VENDOR_ID_HP,
626 .device = PCI_DEVICE_ID_HP_DIVA,
627 .subvendor = PCI_ANY_ID,
628 .subdevice = PCI_ANY_ID,
629 .init = pci_hp_diva_init,
630 .setup = pci_hp_diva_setup,
636 .vendor = PCI_VENDOR_ID_INTEL,
637 .device = PCI_DEVICE_ID_INTEL_80960_RP,
639 .subdevice = PCI_ANY_ID,
640 .init = pci_inteli960ni_init,
641 .setup = pci_default_setup,
647 .vendor = PCI_VENDOR_ID_PANACOM,
648 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
649 .subvendor = PCI_ANY_ID,
650 .subdevice = PCI_ANY_ID,
651 .init = pci_plx9050_init,
652 .setup = pci_default_setup,
653 .exit = __devexit_p(pci_plx9050_exit),
656 .vendor = PCI_VENDOR_ID_PANACOM,
657 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
658 .subvendor = PCI_ANY_ID,
659 .subdevice = PCI_ANY_ID,
660 .init = pci_plx9050_init,
661 .setup = pci_default_setup,
662 .exit = __devexit_p(pci_plx9050_exit),
668 .vendor = PCI_VENDOR_ID_PLX,
669 .device = PCI_DEVICE_ID_PLX_9050,
670 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
671 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
672 .init = pci_plx9050_init,
673 .setup = pci_default_setup,
674 .exit = __devexit_p(pci_plx9050_exit),
677 .vendor = PCI_VENDOR_ID_PLX,
678 .device = PCI_DEVICE_ID_PLX_9050,
679 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
680 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
681 .init = pci_plx9050_init,
682 .setup = pci_default_setup,
683 .exit = __devexit_p(pci_plx9050_exit),
686 .vendor = PCI_VENDOR_ID_PLX,
687 .device = PCI_DEVICE_ID_PLX_ROMULUS,
688 .subvendor = PCI_VENDOR_ID_PLX,
689 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
690 .init = pci_plx9050_init,
691 .setup = pci_default_setup,
692 .exit = __devexit_p(pci_plx9050_exit),
695 * SBS Technologies, Inc., PMC-OCTALPRO 232
698 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
699 .device = PCI_DEVICE_ID_OCTPRO,
700 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
701 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
704 .exit = __devexit_p(sbs_exit),
707 * SBS Technologies, Inc., PMC-OCTALPRO 422
710 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
711 .device = PCI_DEVICE_ID_OCTPRO,
712 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
713 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
716 .exit = __devexit_p(sbs_exit),
719 * SBS Technologies, Inc., P-Octal 232
722 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
723 .device = PCI_DEVICE_ID_OCTPRO,
724 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
725 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
728 .exit = __devexit_p(sbs_exit),
731 * SBS Technologies, Inc., P-Octal 422
734 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
735 .device = PCI_DEVICE_ID_OCTPRO,
736 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
737 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
740 .exit = __devexit_p(sbs_exit),
746 .vendor = PCI_VENDOR_ID_SIIG,
747 .device = PCI_ANY_ID,
748 .subvendor = PCI_ANY_ID,
749 .subdevice = PCI_ANY_ID,
750 .init = pci_siig_init,
751 .setup = pci_default_setup,
757 .vendor = PCI_VENDOR_ID_TITAN,
758 .device = PCI_DEVICE_ID_TITAN_400L,
759 .subvendor = PCI_ANY_ID,
760 .subdevice = PCI_ANY_ID,
761 .setup = titan_400l_800l_setup,
764 .vendor = PCI_VENDOR_ID_TITAN,
765 .device = PCI_DEVICE_ID_TITAN_800L,
766 .subvendor = PCI_ANY_ID,
767 .subdevice = PCI_ANY_ID,
768 .setup = titan_400l_800l_setup,
774 .vendor = PCI_VENDOR_ID_TIMEDIA,
775 .device = PCI_DEVICE_ID_TIMEDIA_1889,
776 .subvendor = PCI_VENDOR_ID_TIMEDIA,
777 .subdevice = PCI_ANY_ID,
778 .init = pci_timedia_init,
779 .setup = pci_timedia_setup,
782 .vendor = PCI_VENDOR_ID_TIMEDIA,
783 .device = PCI_ANY_ID,
784 .subvendor = PCI_ANY_ID,
785 .subdevice = PCI_ANY_ID,
786 .setup = pci_timedia_setup,
792 .vendor = PCI_VENDOR_ID_XIRCOM,
793 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
794 .subvendor = PCI_ANY_ID,
795 .subdevice = PCI_ANY_ID,
796 .init = pci_xircom_init,
797 .setup = pci_default_setup,
803 .vendor = PCI_VENDOR_ID_NETMOS,
804 .device = PCI_ANY_ID,
805 .subvendor = PCI_ANY_ID,
806 .subdevice = PCI_ANY_ID,
807 .init = pci_netmos_init,
808 .setup = pci_default_setup,
811 * Default "match everything" terminator entry
814 .vendor = PCI_ANY_ID,
815 .device = PCI_ANY_ID,
816 .subvendor = PCI_ANY_ID,
817 .subdevice = PCI_ANY_ID,
818 .setup = pci_default_setup,
822 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
824 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
827 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
829 struct pci_serial_quirk *quirk;
831 for (quirk = pci_serial_quirks; ; quirk++)
832 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
833 quirk_id_matches(quirk->device, dev->device) &&
834 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
835 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
840 static inline int get_pci_irq(struct pci_dev *dev,
841 struct pciserial_board *board)
843 if (board->flags & FL_NOIRQ)
850 * This is the configuration table for all of the PCI serial boards
851 * which we support. It is directly indexed by the pci_board_num_t enum
852 * value, which is encoded in the pci_device_id PCI probe table's
853 * driver_data member.
855 * The makeup of these names are:
856 * pbn_bn{_bt}_n_baud{_offsetinhex}
858 * bn = PCI BAR number
859 * bt = Index using PCI BARs
860 * n = number of serial ports
862 * offsetinhex = offset for each sequential port (in hex)
864 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
866 * Please note: in theory if n = 1, _bt infix should make no difference.
867 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
869 enum pci_board_num_t {
888 pbn_b0_2_1843200_200,
889 pbn_b0_4_1843200_200,
890 pbn_b0_8_1843200_200,
948 * Board-specific versions.
969 * uart_offset - the space between channels
970 * reg_shift - describes how the UART registers are mapped
971 * to PCI memory by the card.
972 * For example IER register on SBS, Inc. PMC-OctPro is located at
973 * offset 0x10 from the UART base, while UART_IER is defined as 1
974 * in include/linux/serial_reg.h,
975 * see first lines of serial_in() and serial_out() in 8250.c
978 static struct pciserial_board pci_boards[] __devinitdata = {
985 [pbn_b0_1_115200] = {
991 [pbn_b0_2_115200] = {
997 [pbn_b0_4_115200] = {
1000 .base_baud = 115200,
1003 [pbn_b0_5_115200] = {
1006 .base_baud = 115200,
1010 [pbn_b0_1_921600] = {
1013 .base_baud = 921600,
1016 [pbn_b0_2_921600] = {
1019 .base_baud = 921600,
1022 [pbn_b0_4_921600] = {
1025 .base_baud = 921600,
1029 [pbn_b0_2_1130000] = {
1032 .base_baud = 1130000,
1036 [pbn_b0_4_1152000] = {
1039 .base_baud = 1152000,
1043 [pbn_b0_2_1843200] = {
1046 .base_baud = 1843200,
1049 [pbn_b0_4_1843200] = {
1052 .base_baud = 1843200,
1056 [pbn_b0_2_1843200_200] = {
1059 .base_baud = 1843200,
1060 .uart_offset = 0x200,
1062 [pbn_b0_4_1843200_200] = {
1065 .base_baud = 1843200,
1066 .uart_offset = 0x200,
1068 [pbn_b0_8_1843200_200] = {
1071 .base_baud = 1843200,
1072 .uart_offset = 0x200,
1075 [pbn_b0_bt_1_115200] = {
1076 .flags = FL_BASE0|FL_BASE_BARS,
1078 .base_baud = 115200,
1081 [pbn_b0_bt_2_115200] = {
1082 .flags = FL_BASE0|FL_BASE_BARS,
1084 .base_baud = 115200,
1087 [pbn_b0_bt_8_115200] = {
1088 .flags = FL_BASE0|FL_BASE_BARS,
1090 .base_baud = 115200,
1094 [pbn_b0_bt_1_460800] = {
1095 .flags = FL_BASE0|FL_BASE_BARS,
1097 .base_baud = 460800,
1100 [pbn_b0_bt_2_460800] = {
1101 .flags = FL_BASE0|FL_BASE_BARS,
1103 .base_baud = 460800,
1106 [pbn_b0_bt_4_460800] = {
1107 .flags = FL_BASE0|FL_BASE_BARS,
1109 .base_baud = 460800,
1113 [pbn_b0_bt_1_921600] = {
1114 .flags = FL_BASE0|FL_BASE_BARS,
1116 .base_baud = 921600,
1119 [pbn_b0_bt_2_921600] = {
1120 .flags = FL_BASE0|FL_BASE_BARS,
1122 .base_baud = 921600,
1125 [pbn_b0_bt_4_921600] = {
1126 .flags = FL_BASE0|FL_BASE_BARS,
1128 .base_baud = 921600,
1131 [pbn_b0_bt_8_921600] = {
1132 .flags = FL_BASE0|FL_BASE_BARS,
1134 .base_baud = 921600,
1138 [pbn_b1_1_115200] = {
1141 .base_baud = 115200,
1144 [pbn_b1_2_115200] = {
1147 .base_baud = 115200,
1150 [pbn_b1_4_115200] = {
1153 .base_baud = 115200,
1156 [pbn_b1_8_115200] = {
1159 .base_baud = 115200,
1163 [pbn_b1_1_921600] = {
1166 .base_baud = 921600,
1169 [pbn_b1_2_921600] = {
1172 .base_baud = 921600,
1175 [pbn_b1_4_921600] = {
1178 .base_baud = 921600,
1181 [pbn_b1_8_921600] = {
1184 .base_baud = 921600,
1187 [pbn_b1_2_1250000] = {
1190 .base_baud = 1250000,
1194 [pbn_b1_bt_2_921600] = {
1195 .flags = FL_BASE1|FL_BASE_BARS,
1197 .base_baud = 921600,
1201 [pbn_b1_1_1382400] = {
1204 .base_baud = 1382400,
1207 [pbn_b1_2_1382400] = {
1210 .base_baud = 1382400,
1213 [pbn_b1_4_1382400] = {
1216 .base_baud = 1382400,
1219 [pbn_b1_8_1382400] = {
1222 .base_baud = 1382400,
1226 [pbn_b2_1_115200] = {
1229 .base_baud = 115200,
1232 [pbn_b2_8_115200] = {
1235 .base_baud = 115200,
1239 [pbn_b2_1_460800] = {
1242 .base_baud = 460800,
1245 [pbn_b2_4_460800] = {
1248 .base_baud = 460800,
1251 [pbn_b2_8_460800] = {
1254 .base_baud = 460800,
1257 [pbn_b2_16_460800] = {
1260 .base_baud = 460800,
1264 [pbn_b2_1_921600] = {
1267 .base_baud = 921600,
1270 [pbn_b2_4_921600] = {
1273 .base_baud = 921600,
1276 [pbn_b2_8_921600] = {
1279 .base_baud = 921600,
1283 [pbn_b2_bt_1_115200] = {
1284 .flags = FL_BASE2|FL_BASE_BARS,
1286 .base_baud = 115200,
1289 [pbn_b2_bt_2_115200] = {
1290 .flags = FL_BASE2|FL_BASE_BARS,
1292 .base_baud = 115200,
1295 [pbn_b2_bt_4_115200] = {
1296 .flags = FL_BASE2|FL_BASE_BARS,
1298 .base_baud = 115200,
1302 [pbn_b2_bt_2_921600] = {
1303 .flags = FL_BASE2|FL_BASE_BARS,
1305 .base_baud = 921600,
1308 [pbn_b2_bt_4_921600] = {
1309 .flags = FL_BASE2|FL_BASE_BARS,
1311 .base_baud = 921600,
1315 [pbn_b3_2_115200] = {
1318 .base_baud = 115200,
1321 [pbn_b3_4_115200] = {
1324 .base_baud = 115200,
1327 [pbn_b3_8_115200] = {
1330 .base_baud = 115200,
1335 * Entries following this are board-specific.
1344 .base_baud = 921600,
1345 .uart_offset = 0x400,
1349 .flags = FL_BASE2|FL_BASE_BARS,
1351 .base_baud = 921600,
1352 .uart_offset = 0x400,
1356 .flags = FL_BASE2|FL_BASE_BARS,
1358 .base_baud = 921600,
1359 .uart_offset = 0x400,
1363 [pbn_exsys_4055] = {
1366 .base_baud = 115200,
1370 /* I think this entry is broken - the first_offset looks wrong --rmk */
1371 [pbn_plx_romulus] = {
1374 .base_baud = 921600,
1375 .uart_offset = 8 << 2,
1377 .first_offset = 0x03,
1381 * This board uses the size of PCI Base region 0 to
1382 * signal now many ports are available
1385 .flags = FL_BASE0|FL_REGION_SZ_CAP,
1387 .base_baud = 115200,
1392 * EKF addition for i960 Boards form EKF with serial port.
1395 [pbn_intel_i960] = {
1398 .base_baud = 921600,
1399 .uart_offset = 8 << 2,
1401 .first_offset = 0x10000,
1404 .flags = FL_BASE0|FL_NOIRQ,
1406 .base_baud = 458333,
1409 .first_offset = 0x20178,
1413 * NEC Vrc-5074 (Nile 4) builtin UART.
1418 .base_baud = 520833,
1419 .uart_offset = 8 << 3,
1421 .first_offset = 0x300,
1425 * Computone - uses IOMEM.
1427 [pbn_computone_4] = {
1430 .base_baud = 921600,
1431 .uart_offset = 0x40,
1433 .first_offset = 0x200,
1435 [pbn_computone_6] = {
1438 .base_baud = 921600,
1439 .uart_offset = 0x40,
1441 .first_offset = 0x200,
1443 [pbn_computone_8] = {
1446 .base_baud = 921600,
1447 .uart_offset = 0x40,
1449 .first_offset = 0x200,
1454 .base_baud = 460800,
1459 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
1460 * Only basic 16550A support.
1461 * XR17C15[24] are not tested, but they should work.
1463 [pbn_exar_XR17C152] = {
1466 .base_baud = 921600,
1467 .uart_offset = 0x200,
1469 [pbn_exar_XR17C154] = {
1472 .base_baud = 921600,
1473 .uart_offset = 0x200,
1475 [pbn_exar_XR17C158] = {
1478 .base_baud = 921600,
1479 .uart_offset = 0x200,
1484 * Given a complete unknown PCI device, try to use some heuristics to
1485 * guess what the configuration might be, based on the pitiful PCI
1486 * serial specs. Returns 0 on success, 1 on failure.
1488 static int __devinit
1489 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
1491 int num_iomem, num_port, first_port = -1, i;
1494 * If it is not a communications device or the programming
1495 * interface is greater than 6, give up.
1497 * (Should we try to make guesses for multiport serial devices
1500 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
1501 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
1502 (dev->class & 0xff) > 6)
1505 num_iomem = num_port = 0;
1506 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1507 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
1509 if (first_port == -1)
1512 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
1517 * If there is 1 or 0 iomem regions, and exactly one port,
1518 * use it. We guess the number of ports based on the IO
1521 if (num_iomem <= 1 && num_port == 1) {
1522 board->flags = first_port;
1523 board->num_ports = pci_resource_len(dev, first_port) / 8;
1528 * Now guess if we've got a board which indexes by BARs.
1529 * Each IO BAR should be 8 bytes, and they should follow
1534 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1535 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
1536 pci_resource_len(dev, i) == 8 &&
1537 (first_port == -1 || (first_port + num_port) == i)) {
1539 if (first_port == -1)
1545 board->flags = first_port | FL_BASE_BARS;
1546 board->num_ports = num_port;
1554 serial_pci_matches(struct pciserial_board *board,
1555 struct pciserial_board *guessed)
1558 board->num_ports == guessed->num_ports &&
1559 board->base_baud == guessed->base_baud &&
1560 board->uart_offset == guessed->uart_offset &&
1561 board->reg_shift == guessed->reg_shift &&
1562 board->first_offset == guessed->first_offset;
1565 struct serial_private *
1566 pciserial_init_ports(struct pci_dev *dev, struct pciserial_board *board)
1568 struct uart_port serial_port;
1569 struct serial_private *priv;
1570 struct pci_serial_quirk *quirk;
1571 int rc, nr_ports, i;
1573 nr_ports = board->num_ports;
1576 * Find an init and setup quirks.
1578 quirk = find_quirk(dev);
1581 * Run the new-style initialization function.
1582 * The initialization function returns:
1584 * 0 - use board->num_ports
1585 * >0 - number of ports
1588 rc = quirk->init(dev);
1597 priv = kmalloc(sizeof(struct serial_private) +
1598 sizeof(unsigned int) * nr_ports,
1601 priv = ERR_PTR(-ENOMEM);
1605 memset(priv, 0, sizeof(struct serial_private) +
1606 sizeof(unsigned int) * nr_ports);
1609 priv->quirk = quirk;
1611 memset(&serial_port, 0, sizeof(struct uart_port));
1612 serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
1613 serial_port.uartclk = board->base_baud * 16;
1614 serial_port.irq = get_pci_irq(dev, board);
1615 serial_port.dev = &dev->dev;
1617 for (i = 0; i < nr_ports; i++) {
1618 if (quirk->setup(priv, board, &serial_port, i))
1621 #ifdef SERIAL_DEBUG_PCI
1622 printk("Setup PCI port: port %x, irq %d, type %d\n",
1623 serial_port.iobase, serial_port.irq, serial_port.iotype);
1626 priv->line[i] = serial8250_register_port(&serial_port);
1627 if (priv->line[i] < 0) {
1628 printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
1643 EXPORT_SYMBOL_GPL(pciserial_init_ports);
1645 void pciserial_remove_ports(struct serial_private *priv)
1647 struct pci_serial_quirk *quirk;
1650 for (i = 0; i < priv->nr; i++)
1651 serial8250_unregister_port(priv->line[i]);
1653 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1654 if (priv->remapped_bar[i])
1655 iounmap(priv->remapped_bar[i]);
1656 priv->remapped_bar[i] = NULL;
1660 * Find the exit quirks.
1662 quirk = find_quirk(priv->dev);
1664 quirk->exit(priv->dev);
1668 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
1670 void pciserial_suspend_ports(struct serial_private *priv)
1674 for (i = 0; i < priv->nr; i++)
1675 if (priv->line[i] >= 0)
1676 serial8250_suspend_port(priv->line[i]);
1678 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
1680 void pciserial_resume_ports(struct serial_private *priv)
1685 * Ensure that the board is correctly configured.
1687 if (priv->quirk->init)
1688 priv->quirk->init(priv->dev);
1690 for (i = 0; i < priv->nr; i++)
1691 if (priv->line[i] >= 0)
1692 serial8250_resume_port(priv->line[i]);
1694 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
1697 * Probe one serial board. Unfortunately, there is no rhyme nor reason
1698 * to the arrangement of serial ports on a PCI card.
1700 static int __devinit
1701 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
1703 struct serial_private *priv;
1704 struct pciserial_board *board, tmp;
1707 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
1708 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
1713 board = &pci_boards[ent->driver_data];
1715 rc = pci_enable_device(dev);
1719 if (ent->driver_data == pbn_default) {
1721 * Use a copy of the pci_board entry for this;
1722 * avoid changing entries in the table.
1724 memcpy(&tmp, board, sizeof(struct pciserial_board));
1728 * We matched one of our class entries. Try to
1729 * determine the parameters of this board.
1731 rc = serial_pci_guess_board(dev, board);
1736 * We matched an explicit entry. If we are able to
1737 * detect this boards settings with our heuristic,
1738 * then we no longer need this entry.
1740 memcpy(&tmp, &pci_boards[pbn_default],
1741 sizeof(struct pciserial_board));
1742 rc = serial_pci_guess_board(dev, &tmp);
1743 if (rc == 0 && serial_pci_matches(board, &tmp))
1744 moan_device("Redundant entry in serial pci_table.",
1748 priv = pciserial_init_ports(dev, board);
1749 if (!IS_ERR(priv)) {
1750 pci_set_drvdata(dev, priv);
1757 pci_disable_device(dev);
1761 static void __devexit pciserial_remove_one(struct pci_dev *dev)
1763 struct serial_private *priv = pci_get_drvdata(dev);
1765 pci_set_drvdata(dev, NULL);
1767 pciserial_remove_ports(priv);
1769 pci_disable_device(dev);
1772 static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
1774 struct serial_private *priv = pci_get_drvdata(dev);
1777 pciserial_suspend_ports(priv);
1779 pci_save_state(dev);
1780 pci_set_power_state(dev, pci_choose_state(dev, state));
1784 static int pciserial_resume_one(struct pci_dev *dev)
1786 struct serial_private *priv = pci_get_drvdata(dev);
1788 pci_set_power_state(dev, PCI_D0);
1789 pci_restore_state(dev);
1793 * The device may have been disabled. Re-enable it.
1795 pci_enable_device(dev);
1797 pciserial_resume_ports(priv);
1802 static struct pci_device_id serial_pci_tbl[] = {
1803 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1804 PCI_SUBVENDOR_ID_CONNECT_TECH,
1805 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
1807 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1808 PCI_SUBVENDOR_ID_CONNECT_TECH,
1809 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
1811 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1812 PCI_SUBVENDOR_ID_CONNECT_TECH,
1813 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
1815 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1816 PCI_SUBVENDOR_ID_CONNECT_TECH,
1817 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
1819 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1820 PCI_SUBVENDOR_ID_CONNECT_TECH,
1821 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
1823 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1824 PCI_SUBVENDOR_ID_CONNECT_TECH,
1825 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
1827 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1828 PCI_SUBVENDOR_ID_CONNECT_TECH,
1829 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
1831 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1832 PCI_SUBVENDOR_ID_CONNECT_TECH,
1833 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
1835 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1836 PCI_SUBVENDOR_ID_CONNECT_TECH,
1837 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
1839 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1840 PCI_SUBVENDOR_ID_CONNECT_TECH,
1841 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
1843 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1844 PCI_SUBVENDOR_ID_CONNECT_TECH,
1845 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
1847 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1848 PCI_SUBVENDOR_ID_CONNECT_TECH,
1849 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
1851 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1852 PCI_SUBVENDOR_ID_CONNECT_TECH,
1853 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
1855 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1856 PCI_SUBVENDOR_ID_CONNECT_TECH,
1857 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
1859 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1860 PCI_SUBVENDOR_ID_CONNECT_TECH,
1861 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
1863 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
1864 PCI_SUBVENDOR_ID_CONNECT_TECH,
1865 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
1867 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
1868 PCI_SUBVENDOR_ID_CONNECT_TECH,
1869 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
1871 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
1872 PCI_SUBVENDOR_ID_CONNECT_TECH,
1873 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
1874 pbn_b0_2_1843200_200 },
1875 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
1876 PCI_SUBVENDOR_ID_CONNECT_TECH,
1877 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
1878 pbn_b0_4_1843200_200 },
1879 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
1880 PCI_SUBVENDOR_ID_CONNECT_TECH,
1881 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
1882 pbn_b0_8_1843200_200 },
1883 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
1884 PCI_SUBVENDOR_ID_CONNECT_TECH,
1885 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
1886 pbn_b0_2_1843200_200 },
1887 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
1888 PCI_SUBVENDOR_ID_CONNECT_TECH,
1889 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
1890 pbn_b0_4_1843200_200 },
1891 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
1892 PCI_SUBVENDOR_ID_CONNECT_TECH,
1893 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
1894 pbn_b0_8_1843200_200 },
1895 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
1896 PCI_SUBVENDOR_ID_CONNECT_TECH,
1897 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
1898 pbn_b0_2_1843200_200 },
1899 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
1900 PCI_SUBVENDOR_ID_CONNECT_TECH,
1901 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
1902 pbn_b0_4_1843200_200 },
1903 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
1904 PCI_SUBVENDOR_ID_CONNECT_TECH,
1905 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
1906 pbn_b0_8_1843200_200 },
1907 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
1908 PCI_SUBVENDOR_ID_CONNECT_TECH,
1909 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
1910 pbn_b0_2_1843200_200 },
1911 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
1912 PCI_SUBVENDOR_ID_CONNECT_TECH,
1913 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
1914 pbn_b0_4_1843200_200 },
1915 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
1916 PCI_SUBVENDOR_ID_CONNECT_TECH,
1917 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
1918 pbn_b0_8_1843200_200 },
1920 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
1921 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1922 pbn_b2_bt_1_115200 },
1923 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
1924 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1925 pbn_b2_bt_2_115200 },
1926 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
1927 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1928 pbn_b2_bt_4_115200 },
1929 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
1930 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1931 pbn_b2_bt_2_115200 },
1932 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
1933 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1934 pbn_b2_bt_4_115200 },
1935 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
1936 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1938 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
1939 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1942 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
1943 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1944 pbn_b2_bt_2_115200 },
1945 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
1946 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1947 pbn_b2_bt_2_921600 },
1949 * VScom SPCOM800, from sl@s.pl
1951 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
1952 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1954 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
1955 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1957 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1958 PCI_SUBVENDOR_ID_KEYSPAN,
1959 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
1961 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
1962 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1964 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
1965 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1967 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1968 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1969 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
1971 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1972 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1973 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
1975 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1976 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1977 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
1979 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1980 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1981 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
1983 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1984 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
1985 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
1987 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1988 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
1989 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
1991 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1992 PCI_SUBVENDOR_ID_EXSYS,
1993 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
1996 * Megawolf Romulus PCI Serial Card, from Mike Hudson
1999 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
2000 0x10b5, 0x106a, 0, 0,
2002 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
2003 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2005 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
2006 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2008 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
2009 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2011 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
2012 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2014 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
2015 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4, 0, 0,
2017 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2018 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL, 0, 0,
2022 * The below card is a little controversial since it is the
2023 * subject of a PCI vendor/device ID clash. (See
2024 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
2025 * For now just used the hex ID 0x950a.
2027 { PCI_VENDOR_ID_OXSEMI, 0x950a,
2028 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2030 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2031 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2033 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
2034 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2035 pbn_b0_bt_2_921600 },
2038 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
2039 * from skokodyn@yahoo.com
2041 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2042 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
2044 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2045 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
2047 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2048 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
2050 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2051 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
2055 * Digitan DS560-558, from jimd@esoft.com
2057 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
2058 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2062 * Titan Electronic cards
2063 * The 400L and 800L have a custom setup quirk.
2065 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
2066 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2068 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
2069 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2071 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
2072 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2074 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
2075 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2077 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
2078 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2080 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
2081 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2082 pbn_b1_bt_2_921600 },
2083 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
2084 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2085 pbn_b0_bt_4_921600 },
2086 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
2087 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2088 pbn_b0_bt_8_921600 },
2090 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
2091 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2093 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
2094 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2096 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
2097 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2099 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
2100 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2101 pbn_b2_bt_2_921600 },
2102 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
2103 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2104 pbn_b2_bt_2_921600 },
2105 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
2106 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2107 pbn_b2_bt_2_921600 },
2108 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
2109 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2110 pbn_b2_bt_4_921600 },
2111 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
2112 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2113 pbn_b2_bt_4_921600 },
2114 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
2115 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2116 pbn_b2_bt_4_921600 },
2117 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
2118 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2120 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
2121 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2123 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
2124 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2126 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
2127 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2128 pbn_b0_bt_2_921600 },
2129 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
2130 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2131 pbn_b0_bt_2_921600 },
2132 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
2133 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2134 pbn_b0_bt_2_921600 },
2135 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
2136 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2137 pbn_b0_bt_4_921600 },
2138 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
2139 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2140 pbn_b0_bt_4_921600 },
2141 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
2142 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2143 pbn_b0_bt_4_921600 },
2146 * Computone devices submitted by Doug McNash dmcnash@computone.com
2148 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2149 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
2150 0, 0, pbn_computone_4 },
2151 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2152 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
2153 0, 0, pbn_computone_8 },
2154 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2155 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
2156 0, 0, pbn_computone_6 },
2158 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
2159 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2161 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
2162 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
2163 pbn_b0_bt_1_921600 },
2166 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
2168 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
2169 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2170 pbn_b0_bt_8_115200 },
2171 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
2172 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2173 pbn_b0_bt_8_115200 },
2175 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
2176 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2177 pbn_b0_bt_2_115200 },
2178 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
2179 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2180 pbn_b0_bt_2_115200 },
2181 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
2182 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2183 pbn_b0_bt_2_115200 },
2184 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
2185 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2186 pbn_b0_bt_4_460800 },
2187 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
2188 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2189 pbn_b0_bt_4_460800 },
2190 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
2191 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2192 pbn_b0_bt_2_460800 },
2193 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
2194 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2195 pbn_b0_bt_2_460800 },
2196 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
2197 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2198 pbn_b0_bt_2_460800 },
2199 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
2200 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2201 pbn_b0_bt_1_115200 },
2202 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
2203 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2204 pbn_b0_bt_1_460800 },
2207 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
2209 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
2210 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2214 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
2216 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
2217 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2221 * RAStel 2 port modem, gerg@moreton.com.au
2223 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
2224 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2225 pbn_b2_bt_2_115200 },
2228 * EKF addition for i960 Boards form EKF with serial port
2230 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
2231 0xE4BF, PCI_ANY_ID, 0, 0,
2235 * Xircom Cardbus/Ethernet combos
2237 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2238 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2241 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
2243 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
2244 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2248 * Untested PCI modems, sent in from various folks...
2252 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
2254 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
2255 0x1048, 0x1500, 0, 0,
2258 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
2265 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
2266 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
2268 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
2269 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2271 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
2272 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2276 * NEC Vrc-5074 (Nile 4) builtin UART.
2278 { PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_NILE4,
2279 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2282 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
2283 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2285 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
2286 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2288 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
2289 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2293 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2295 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2296 PCI_ANY_ID, PCI_ANY_ID,
2298 0, pbn_exar_XR17C152 },
2299 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2300 PCI_ANY_ID, PCI_ANY_ID,
2302 0, pbn_exar_XR17C154 },
2303 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2304 PCI_ANY_ID, PCI_ANY_ID,
2306 0, pbn_exar_XR17C158 },
2309 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
2311 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
2312 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2316 * These entries match devices with class COMMUNICATION_SERIAL,
2317 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
2319 { PCI_ANY_ID, PCI_ANY_ID,
2320 PCI_ANY_ID, PCI_ANY_ID,
2321 PCI_CLASS_COMMUNICATION_SERIAL << 8,
2322 0xffff00, pbn_default },
2323 { PCI_ANY_ID, PCI_ANY_ID,
2324 PCI_ANY_ID, PCI_ANY_ID,
2325 PCI_CLASS_COMMUNICATION_MODEM << 8,
2326 0xffff00, pbn_default },
2327 { PCI_ANY_ID, PCI_ANY_ID,
2328 PCI_ANY_ID, PCI_ANY_ID,
2329 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
2330 0xffff00, pbn_default },
2334 static struct pci_driver serial_pci_driver = {
2336 .probe = pciserial_init_one,
2337 .remove = __devexit_p(pciserial_remove_one),
2338 .suspend = pciserial_suspend_one,
2339 .resume = pciserial_resume_one,
2340 .id_table = serial_pci_tbl,
2343 static int __init serial8250_pci_init(void)
2345 return pci_register_driver(&serial_pci_driver);
2348 static void __exit serial8250_pci_exit(void)
2350 pci_unregister_driver(&serial_pci_driver);
2353 module_init(serial8250_pci_init);
2354 module_exit(serial8250_pci_exit);
2356 MODULE_LICENSE("GPL");
2357 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
2358 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);