2 * linux/drivers/char/amba.c
4 * Driver for AMBA serial ports
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
8 * Copyright 1999 ARM Limited
9 * Copyright (C) 2000 Deep Blue Solutions Ltd.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 * This is a generic driver for ARM AMBA-type serial ports. They
26 * have a lot of 16550-like features, but are not register compatible.
27 * Note that although they do have CTS, DCD and DSR inputs, they do
28 * not have an RI input, nor do they have DTR or RTS outputs. If
29 * required, these have to be supplied via some other means (eg, GPIO)
30 * and hooked into this driver.
33 #if defined(CONFIG_SERIAL_AMBA_PL011_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
37 #include <linux/module.h>
38 #include <linux/ioport.h>
39 #include <linux/init.h>
40 #include <linux/console.h>
41 #include <linux/sysrq.h>
42 #include <linux/device.h>
43 #include <linux/tty.h>
44 #include <linux/tty_flip.h>
45 #include <linux/serial_core.h>
46 #include <linux/serial.h>
47 #include <linux/amba/bus.h>
48 #include <linux/amba/serial.h>
49 #include <linux/clk.h>
50 #include <linux/slab.h>
53 #include <asm/sizes.h>
57 #define SERIAL_AMBA_MAJOR 204
58 #define SERIAL_AMBA_MINOR 64
59 #define SERIAL_AMBA_NR UART_NR
61 #define AMBA_ISR_PASS_LIMIT 256
63 #define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE)
64 #define UART_DUMMY_DR_RX (1 << 16)
67 * We wrap our port structure around the generic uart_port.
69 struct uart_amba_port {
70 struct uart_port port;
72 unsigned int im; /* interrupt mask */
73 unsigned int old_status;
74 unsigned int ifls; /* vendor-specific */
75 unsigned int lcrh_tx; /* vendor-specific */
76 unsigned int lcrh_rx; /* vendor-specific */
77 bool oversampling; /* vendor-specific */
82 /* There is by now at least one vendor with differing details, so handle it */
85 unsigned int fifosize;
91 static struct vendor_data vendor_arm = {
92 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
94 .lcrh_tx = UART011_LCRH,
95 .lcrh_rx = UART011_LCRH,
96 .oversampling = false,
99 static struct vendor_data vendor_st = {
100 .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF,
102 .lcrh_tx = ST_UART011_LCRH_TX,
103 .lcrh_rx = ST_UART011_LCRH_RX,
104 .oversampling = true,
107 static void pl011_stop_tx(struct uart_port *port)
109 struct uart_amba_port *uap = (struct uart_amba_port *)port;
111 uap->im &= ~UART011_TXIM;
112 writew(uap->im, uap->port.membase + UART011_IMSC);
115 static void pl011_start_tx(struct uart_port *port)
117 struct uart_amba_port *uap = (struct uart_amba_port *)port;
119 uap->im |= UART011_TXIM;
120 writew(uap->im, uap->port.membase + UART011_IMSC);
123 static void pl011_stop_rx(struct uart_port *port)
125 struct uart_amba_port *uap = (struct uart_amba_port *)port;
127 uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM|
128 UART011_PEIM|UART011_BEIM|UART011_OEIM);
129 writew(uap->im, uap->port.membase + UART011_IMSC);
132 static void pl011_enable_ms(struct uart_port *port)
134 struct uart_amba_port *uap = (struct uart_amba_port *)port;
136 uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM;
137 writew(uap->im, uap->port.membase + UART011_IMSC);
140 static void pl011_rx_chars(struct uart_amba_port *uap)
142 struct tty_struct *tty = uap->port.state->port.tty;
143 unsigned int status, ch, flag, max_count = 256;
145 status = readw(uap->port.membase + UART01x_FR);
146 while ((status & UART01x_FR_RXFE) == 0 && max_count--) {
147 ch = readw(uap->port.membase + UART01x_DR) | UART_DUMMY_DR_RX;
149 uap->port.icount.rx++;
152 * Note that the error handling code is
153 * out of the main execution path
155 if (unlikely(ch & UART_DR_ERROR)) {
156 if (ch & UART011_DR_BE) {
157 ch &= ~(UART011_DR_FE | UART011_DR_PE);
158 uap->port.icount.brk++;
159 if (uart_handle_break(&uap->port))
161 } else if (ch & UART011_DR_PE)
162 uap->port.icount.parity++;
163 else if (ch & UART011_DR_FE)
164 uap->port.icount.frame++;
165 if (ch & UART011_DR_OE)
166 uap->port.icount.overrun++;
168 ch &= uap->port.read_status_mask;
170 if (ch & UART011_DR_BE)
172 else if (ch & UART011_DR_PE)
174 else if (ch & UART011_DR_FE)
178 if (uart_handle_sysrq_char(&uap->port, ch & 255))
181 uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag);
184 status = readw(uap->port.membase + UART01x_FR);
186 spin_unlock(&uap->port.lock);
187 tty_flip_buffer_push(tty);
188 spin_lock(&uap->port.lock);
191 static void pl011_tx_chars(struct uart_amba_port *uap)
193 struct circ_buf *xmit = &uap->port.state->xmit;
196 if (uap->port.x_char) {
197 writew(uap->port.x_char, uap->port.membase + UART01x_DR);
198 uap->port.icount.tx++;
199 uap->port.x_char = 0;
202 if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) {
203 pl011_stop_tx(&uap->port);
207 count = uap->port.fifosize >> 1;
209 writew(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR);
210 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
211 uap->port.icount.tx++;
212 if (uart_circ_empty(xmit))
214 } while (--count > 0);
216 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
217 uart_write_wakeup(&uap->port);
219 if (uart_circ_empty(xmit))
220 pl011_stop_tx(&uap->port);
223 static void pl011_modem_status(struct uart_amba_port *uap)
225 unsigned int status, delta;
227 status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
229 delta = status ^ uap->old_status;
230 uap->old_status = status;
235 if (delta & UART01x_FR_DCD)
236 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD);
238 if (delta & UART01x_FR_DSR)
239 uap->port.icount.dsr++;
241 if (delta & UART01x_FR_CTS)
242 uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS);
244 wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
247 static irqreturn_t pl011_int(int irq, void *dev_id)
249 struct uart_amba_port *uap = dev_id;
250 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
253 spin_lock(&uap->port.lock);
255 status = readw(uap->port.membase + UART011_MIS);
258 writew(status & ~(UART011_TXIS|UART011_RTIS|
260 uap->port.membase + UART011_ICR);
262 if (status & (UART011_RTIS|UART011_RXIS))
264 if (status & (UART011_DSRMIS|UART011_DCDMIS|
265 UART011_CTSMIS|UART011_RIMIS))
266 pl011_modem_status(uap);
267 if (status & UART011_TXIS)
270 if (pass_counter-- == 0)
273 status = readw(uap->port.membase + UART011_MIS);
274 } while (status != 0);
278 spin_unlock(&uap->port.lock);
280 return IRQ_RETVAL(handled);
283 static unsigned int pl01x_tx_empty(struct uart_port *port)
285 struct uart_amba_port *uap = (struct uart_amba_port *)port;
286 unsigned int status = readw(uap->port.membase + UART01x_FR);
287 return status & (UART01x_FR_BUSY|UART01x_FR_TXFF) ? 0 : TIOCSER_TEMT;
290 static unsigned int pl01x_get_mctrl(struct uart_port *port)
292 struct uart_amba_port *uap = (struct uart_amba_port *)port;
293 unsigned int result = 0;
294 unsigned int status = readw(uap->port.membase + UART01x_FR);
296 #define TIOCMBIT(uartbit, tiocmbit) \
297 if (status & uartbit) \
300 TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR);
301 TIOCMBIT(UART01x_FR_DSR, TIOCM_DSR);
302 TIOCMBIT(UART01x_FR_CTS, TIOCM_CTS);
303 TIOCMBIT(UART011_FR_RI, TIOCM_RNG);
308 static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl)
310 struct uart_amba_port *uap = (struct uart_amba_port *)port;
313 cr = readw(uap->port.membase + UART011_CR);
315 #define TIOCMBIT(tiocmbit, uartbit) \
316 if (mctrl & tiocmbit) \
321 TIOCMBIT(TIOCM_RTS, UART011_CR_RTS);
322 TIOCMBIT(TIOCM_DTR, UART011_CR_DTR);
323 TIOCMBIT(TIOCM_OUT1, UART011_CR_OUT1);
324 TIOCMBIT(TIOCM_OUT2, UART011_CR_OUT2);
325 TIOCMBIT(TIOCM_LOOP, UART011_CR_LBE);
328 /* We need to disable auto-RTS if we want to turn RTS off */
329 TIOCMBIT(TIOCM_RTS, UART011_CR_RTSEN);
333 writew(cr, uap->port.membase + UART011_CR);
336 static void pl011_break_ctl(struct uart_port *port, int break_state)
338 struct uart_amba_port *uap = (struct uart_amba_port *)port;
342 spin_lock_irqsave(&uap->port.lock, flags);
343 lcr_h = readw(uap->port.membase + uap->lcrh_tx);
344 if (break_state == -1)
345 lcr_h |= UART01x_LCRH_BRK;
347 lcr_h &= ~UART01x_LCRH_BRK;
348 writew(lcr_h, uap->port.membase + uap->lcrh_tx);
349 spin_unlock_irqrestore(&uap->port.lock, flags);
352 #ifdef CONFIG_CONSOLE_POLL
353 static int pl010_get_poll_char(struct uart_port *port)
355 struct uart_amba_port *uap = (struct uart_amba_port *)port;
358 status = readw(uap->port.membase + UART01x_FR);
359 if (status & UART01x_FR_RXFE)
362 return readw(uap->port.membase + UART01x_DR);
365 static void pl010_put_poll_char(struct uart_port *port,
368 struct uart_amba_port *uap = (struct uart_amba_port *)port;
370 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF)
373 writew(ch, uap->port.membase + UART01x_DR);
376 #endif /* CONFIG_CONSOLE_POLL */
378 static int pl011_startup(struct uart_port *port)
380 struct uart_amba_port *uap = (struct uart_amba_port *)port;
385 * Try to enable the clock producer.
387 retval = clk_enable(uap->clk);
391 uap->port.uartclk = clk_get_rate(uap->clk);
396 retval = request_irq(uap->port.irq, pl011_int, 0, "uart-pl011", uap);
400 writew(uap->ifls, uap->port.membase + UART011_IFLS);
403 * Provoke TX FIFO interrupt into asserting.
405 cr = UART01x_CR_UARTEN | UART011_CR_TXE | UART011_CR_LBE;
406 writew(cr, uap->port.membase + UART011_CR);
407 writew(0, uap->port.membase + UART011_FBRD);
408 writew(1, uap->port.membase + UART011_IBRD);
409 writew(0, uap->port.membase + uap->lcrh_rx);
410 if (uap->lcrh_tx != uap->lcrh_rx) {
413 * Wait 10 PCLKs before writing LCRH_TX register,
414 * to get this delay write read only register 10 times
416 for (i = 0; i < 10; ++i)
417 writew(0xff, uap->port.membase + UART011_MIS);
418 writew(0, uap->port.membase + uap->lcrh_tx);
420 writew(0, uap->port.membase + UART01x_DR);
421 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY)
424 cr = UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE;
425 writew(cr, uap->port.membase + UART011_CR);
428 * initialise the old status of the modem signals
430 uap->old_status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
433 * Finally, enable interrupts
435 spin_lock_irq(&uap->port.lock);
436 uap->im = UART011_RXIM | UART011_RTIM;
437 writew(uap->im, uap->port.membase + UART011_IMSC);
438 spin_unlock_irq(&uap->port.lock);
443 clk_disable(uap->clk);
448 static void pl011_shutdown_channel(struct uart_amba_port *uap,
453 val = readw(uap->port.membase + lcrh);
454 val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN);
455 writew(val, uap->port.membase + lcrh);
458 static void pl011_shutdown(struct uart_port *port)
460 struct uart_amba_port *uap = (struct uart_amba_port *)port;
463 * disable all interrupts
465 spin_lock_irq(&uap->port.lock);
467 writew(uap->im, uap->port.membase + UART011_IMSC);
468 writew(0xffff, uap->port.membase + UART011_ICR);
469 spin_unlock_irq(&uap->port.lock);
474 free_irq(uap->port.irq, uap);
479 uap->autorts = false;
480 writew(UART01x_CR_UARTEN | UART011_CR_TXE, uap->port.membase + UART011_CR);
483 * disable break condition and fifos
485 pl011_shutdown_channel(uap, uap->lcrh_rx);
486 if (uap->lcrh_rx != uap->lcrh_tx)
487 pl011_shutdown_channel(uap, uap->lcrh_tx);
490 * Shut down the clock producer
492 clk_disable(uap->clk);
496 pl011_set_termios(struct uart_port *port, struct ktermios *termios,
497 struct ktermios *old)
499 struct uart_amba_port *uap = (struct uart_amba_port *)port;
500 unsigned int lcr_h, old_cr;
502 unsigned int baud, quot;
505 * Ask the core to calculate the divisor for us.
507 baud = uart_get_baud_rate(port, termios, old, 0,
508 port->uartclk/(uap->oversampling ? 8 : 16));
510 if (baud > port->uartclk/16)
511 quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud);
513 quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud);
515 switch (termios->c_cflag & CSIZE) {
517 lcr_h = UART01x_LCRH_WLEN_5;
520 lcr_h = UART01x_LCRH_WLEN_6;
523 lcr_h = UART01x_LCRH_WLEN_7;
526 lcr_h = UART01x_LCRH_WLEN_8;
529 if (termios->c_cflag & CSTOPB)
530 lcr_h |= UART01x_LCRH_STP2;
531 if (termios->c_cflag & PARENB) {
532 lcr_h |= UART01x_LCRH_PEN;
533 if (!(termios->c_cflag & PARODD))
534 lcr_h |= UART01x_LCRH_EPS;
536 if (port->fifosize > 1)
537 lcr_h |= UART01x_LCRH_FEN;
539 spin_lock_irqsave(&port->lock, flags);
542 * Update the per-port timeout.
544 uart_update_timeout(port, termios->c_cflag, baud);
546 port->read_status_mask = UART011_DR_OE | 255;
547 if (termios->c_iflag & INPCK)
548 port->read_status_mask |= UART011_DR_FE | UART011_DR_PE;
549 if (termios->c_iflag & (BRKINT | PARMRK))
550 port->read_status_mask |= UART011_DR_BE;
553 * Characters to ignore
555 port->ignore_status_mask = 0;
556 if (termios->c_iflag & IGNPAR)
557 port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE;
558 if (termios->c_iflag & IGNBRK) {
559 port->ignore_status_mask |= UART011_DR_BE;
561 * If we're ignoring parity and break indicators,
562 * ignore overruns too (for real raw support).
564 if (termios->c_iflag & IGNPAR)
565 port->ignore_status_mask |= UART011_DR_OE;
569 * Ignore all characters if CREAD is not set.
571 if ((termios->c_cflag & CREAD) == 0)
572 port->ignore_status_mask |= UART_DUMMY_DR_RX;
574 if (UART_ENABLE_MS(port, termios->c_cflag))
575 pl011_enable_ms(port);
577 /* first, disable everything */
578 old_cr = readw(port->membase + UART011_CR);
579 writew(0, port->membase + UART011_CR);
581 if (termios->c_cflag & CRTSCTS) {
582 if (old_cr & UART011_CR_RTS)
583 old_cr |= UART011_CR_RTSEN;
585 old_cr |= UART011_CR_CTSEN;
588 old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN);
589 uap->autorts = false;
592 if (uap->oversampling) {
593 if (baud > port->uartclk/16)
594 old_cr |= ST_UART011_CR_OVSFACT;
596 old_cr &= ~ST_UART011_CR_OVSFACT;
600 writew(quot & 0x3f, port->membase + UART011_FBRD);
601 writew(quot >> 6, port->membase + UART011_IBRD);
604 * ----------v----------v----------v----------v-----
605 * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L
606 * ----------^----------^----------^----------^-----
608 writew(lcr_h, port->membase + uap->lcrh_rx);
609 if (uap->lcrh_rx != uap->lcrh_tx) {
612 * Wait 10 PCLKs before writing LCRH_TX register,
613 * to get this delay write read only register 10 times
615 for (i = 0; i < 10; ++i)
616 writew(0xff, uap->port.membase + UART011_MIS);
617 writew(lcr_h, port->membase + uap->lcrh_tx);
619 writew(old_cr, port->membase + UART011_CR);
621 spin_unlock_irqrestore(&port->lock, flags);
624 static const char *pl011_type(struct uart_port *port)
626 struct uart_amba_port *uap = (struct uart_amba_port *)port;
627 return uap->port.type == PORT_AMBA ? uap->type : NULL;
631 * Release the memory region(s) being used by 'port'
633 static void pl010_release_port(struct uart_port *port)
635 release_mem_region(port->mapbase, SZ_4K);
639 * Request the memory region(s) being used by 'port'
641 static int pl010_request_port(struct uart_port *port)
643 return request_mem_region(port->mapbase, SZ_4K, "uart-pl011")
644 != NULL ? 0 : -EBUSY;
648 * Configure/autoconfigure the port.
650 static void pl010_config_port(struct uart_port *port, int flags)
652 if (flags & UART_CONFIG_TYPE) {
653 port->type = PORT_AMBA;
654 pl010_request_port(port);
659 * verify the new serial_struct (for TIOCSSERIAL).
661 static int pl010_verify_port(struct uart_port *port, struct serial_struct *ser)
664 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA)
666 if (ser->irq < 0 || ser->irq >= nr_irqs)
668 if (ser->baud_base < 9600)
673 static struct uart_ops amba_pl011_pops = {
674 .tx_empty = pl01x_tx_empty,
675 .set_mctrl = pl011_set_mctrl,
676 .get_mctrl = pl01x_get_mctrl,
677 .stop_tx = pl011_stop_tx,
678 .start_tx = pl011_start_tx,
679 .stop_rx = pl011_stop_rx,
680 .enable_ms = pl011_enable_ms,
681 .break_ctl = pl011_break_ctl,
682 .startup = pl011_startup,
683 .shutdown = pl011_shutdown,
684 .set_termios = pl011_set_termios,
686 .release_port = pl010_release_port,
687 .request_port = pl010_request_port,
688 .config_port = pl010_config_port,
689 .verify_port = pl010_verify_port,
690 #ifdef CONFIG_CONSOLE_POLL
691 .poll_get_char = pl010_get_poll_char,
692 .poll_put_char = pl010_put_poll_char,
696 static struct uart_amba_port *amba_ports[UART_NR];
698 #ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE
700 static void pl011_console_putchar(struct uart_port *port, int ch)
702 struct uart_amba_port *uap = (struct uart_amba_port *)port;
704 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF)
706 writew(ch, uap->port.membase + UART01x_DR);
710 pl011_console_write(struct console *co, const char *s, unsigned int count)
712 struct uart_amba_port *uap = amba_ports[co->index];
713 unsigned int status, old_cr, new_cr;
715 clk_enable(uap->clk);
718 * First save the CR then disable the interrupts
720 old_cr = readw(uap->port.membase + UART011_CR);
721 new_cr = old_cr & ~UART011_CR_CTSEN;
722 new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
723 writew(new_cr, uap->port.membase + UART011_CR);
725 uart_console_write(&uap->port, s, count, pl011_console_putchar);
728 * Finally, wait for transmitter to become empty
729 * and restore the TCR
732 status = readw(uap->port.membase + UART01x_FR);
733 } while (status & UART01x_FR_BUSY);
734 writew(old_cr, uap->port.membase + UART011_CR);
736 clk_disable(uap->clk);
740 pl011_console_get_options(struct uart_amba_port *uap, int *baud,
741 int *parity, int *bits)
743 if (readw(uap->port.membase + UART011_CR) & UART01x_CR_UARTEN) {
744 unsigned int lcr_h, ibrd, fbrd;
746 lcr_h = readw(uap->port.membase + uap->lcrh_tx);
749 if (lcr_h & UART01x_LCRH_PEN) {
750 if (lcr_h & UART01x_LCRH_EPS)
756 if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7)
761 ibrd = readw(uap->port.membase + UART011_IBRD);
762 fbrd = readw(uap->port.membase + UART011_FBRD);
764 *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd);
766 if (uap->oversampling) {
767 if (readw(uap->port.membase + UART011_CR)
768 & ST_UART011_CR_OVSFACT)
774 static int __init pl011_console_setup(struct console *co, char *options)
776 struct uart_amba_port *uap;
783 * Check whether an invalid uart number has been specified, and
784 * if so, search for the first available port that does have
787 if (co->index >= UART_NR)
789 uap = amba_ports[co->index];
793 uap->port.uartclk = clk_get_rate(uap->clk);
796 uart_parse_options(options, &baud, &parity, &bits, &flow);
798 pl011_console_get_options(uap, &baud, &parity, &bits);
800 return uart_set_options(&uap->port, co, baud, parity, bits, flow);
803 static struct uart_driver amba_reg;
804 static struct console amba_console = {
806 .write = pl011_console_write,
807 .device = uart_console_device,
808 .setup = pl011_console_setup,
809 .flags = CON_PRINTBUFFER,
814 #define AMBA_CONSOLE (&amba_console)
816 #define AMBA_CONSOLE NULL
819 static struct uart_driver amba_reg = {
820 .owner = THIS_MODULE,
821 .driver_name = "ttyAMA",
822 .dev_name = "ttyAMA",
823 .major = SERIAL_AMBA_MAJOR,
824 .minor = SERIAL_AMBA_MINOR,
826 .cons = AMBA_CONSOLE,
829 static int pl011_probe(struct amba_device *dev, struct amba_id *id)
831 struct uart_amba_port *uap;
832 struct vendor_data *vendor = id->data;
836 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
837 if (amba_ports[i] == NULL)
840 if (i == ARRAY_SIZE(amba_ports)) {
845 uap = kzalloc(sizeof(struct uart_amba_port), GFP_KERNEL);
851 base = ioremap(dev->res.start, resource_size(&dev->res));
857 uap->clk = clk_get(&dev->dev, NULL);
858 if (IS_ERR(uap->clk)) {
859 ret = PTR_ERR(uap->clk);
863 uap->ifls = vendor->ifls;
864 uap->lcrh_rx = vendor->lcrh_rx;
865 uap->lcrh_tx = vendor->lcrh_tx;
866 uap->oversampling = vendor->oversampling;
867 uap->port.dev = &dev->dev;
868 uap->port.mapbase = dev->res.start;
869 uap->port.membase = base;
870 uap->port.iotype = UPIO_MEM;
871 uap->port.irq = dev->irq[0];
872 uap->port.fifosize = vendor->fifosize;
873 uap->port.ops = &amba_pl011_pops;
874 uap->port.flags = UPF_BOOT_AUTOCONF;
877 snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev));
881 amba_set_drvdata(dev, uap);
882 ret = uart_add_one_port(&amba_reg, &uap->port);
884 amba_set_drvdata(dev, NULL);
885 amba_ports[i] = NULL;
896 static int pl011_remove(struct amba_device *dev)
898 struct uart_amba_port *uap = amba_get_drvdata(dev);
901 amba_set_drvdata(dev, NULL);
903 uart_remove_one_port(&amba_reg, &uap->port);
905 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
906 if (amba_ports[i] == uap)
907 amba_ports[i] = NULL;
909 iounmap(uap->port.membase);
916 static int pl011_suspend(struct amba_device *dev, pm_message_t state)
918 struct uart_amba_port *uap = amba_get_drvdata(dev);
923 return uart_suspend_port(&amba_reg, &uap->port);
926 static int pl011_resume(struct amba_device *dev)
928 struct uart_amba_port *uap = amba_get_drvdata(dev);
933 return uart_resume_port(&amba_reg, &uap->port);
937 static struct amba_id pl011_ids[] = {
951 static struct amba_driver pl011_driver = {
953 .name = "uart-pl011",
955 .id_table = pl011_ids,
956 .probe = pl011_probe,
957 .remove = pl011_remove,
959 .suspend = pl011_suspend,
960 .resume = pl011_resume,
964 static int __init pl011_init(void)
967 printk(KERN_INFO "Serial: AMBA PL011 UART driver\n");
969 ret = uart_register_driver(&amba_reg);
971 ret = amba_driver_register(&pl011_driver);
973 uart_unregister_driver(&amba_reg);
978 static void __exit pl011_exit(void)
980 amba_driver_unregister(&pl011_driver);
981 uart_unregister_driver(&amba_reg);
985 * While this can be a module, if builtin it's most likely the console
986 * So let's leave module_exit but move module_init to an earlier place
988 arch_initcall(pl011_init);
989 module_exit(pl011_exit);
991 MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd");
992 MODULE_DESCRIPTION("ARM AMBA serial port driver");
993 MODULE_LICENSE("GPL");