2 * linux/drivers/char/amba.c
4 * Driver for AMBA serial ports
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
8 * Copyright 1999 ARM Limited
9 * Copyright (C) 2000 Deep Blue Solutions Ltd.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 * This is a generic driver for ARM AMBA-type serial ports. They
26 * have a lot of 16550-like features, but are not register compatible.
27 * Note that although they do have CTS, DCD and DSR inputs, they do
28 * not have an RI input, nor do they have DTR or RTS outputs. If
29 * required, these have to be supplied via some other means (eg, GPIO)
30 * and hooked into this driver.
33 #if defined(CONFIG_SERIAL_AMBA_PL011_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
37 #include <linux/module.h>
38 #include <linux/ioport.h>
39 #include <linux/init.h>
40 #include <linux/console.h>
41 #include <linux/sysrq.h>
42 #include <linux/device.h>
43 #include <linux/tty.h>
44 #include <linux/tty_flip.h>
45 #include <linux/serial_core.h>
46 #include <linux/serial.h>
47 #include <linux/amba/bus.h>
48 #include <linux/amba/serial.h>
49 #include <linux/clk.h>
50 #include <linux/slab.h>
53 #include <asm/sizes.h>
57 #define SERIAL_AMBA_MAJOR 204
58 #define SERIAL_AMBA_MINOR 64
59 #define SERIAL_AMBA_NR UART_NR
61 #define AMBA_ISR_PASS_LIMIT 256
63 #define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE)
64 #define UART_DUMMY_DR_RX (1 << 16)
67 * We wrap our port structure around the generic uart_port.
69 struct uart_amba_port {
70 struct uart_port port;
72 unsigned int im; /* interrupt mask */
73 unsigned int old_status;
74 unsigned int ifls; /* vendor-specific */
75 unsigned int lcrh_tx; /* vendor-specific */
76 unsigned int lcrh_rx; /* vendor-specific */
80 /* There is by now at least one vendor with differing details, so handle it */
83 unsigned int fifosize;
88 static struct vendor_data vendor_arm = {
89 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
91 .lcrh_tx = UART011_LCRH,
92 .lcrh_rx = UART011_LCRH,
95 static struct vendor_data vendor_st = {
96 .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF,
98 .lcrh_tx = ST_UART011_LCRH_TX,
99 .lcrh_rx = ST_UART011_LCRH_RX,
102 static void pl011_stop_tx(struct uart_port *port)
104 struct uart_amba_port *uap = (struct uart_amba_port *)port;
106 uap->im &= ~UART011_TXIM;
107 writew(uap->im, uap->port.membase + UART011_IMSC);
110 static void pl011_start_tx(struct uart_port *port)
112 struct uart_amba_port *uap = (struct uart_amba_port *)port;
114 uap->im |= UART011_TXIM;
115 writew(uap->im, uap->port.membase + UART011_IMSC);
118 static void pl011_stop_rx(struct uart_port *port)
120 struct uart_amba_port *uap = (struct uart_amba_port *)port;
122 uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM|
123 UART011_PEIM|UART011_BEIM|UART011_OEIM);
124 writew(uap->im, uap->port.membase + UART011_IMSC);
127 static void pl011_enable_ms(struct uart_port *port)
129 struct uart_amba_port *uap = (struct uart_amba_port *)port;
131 uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM;
132 writew(uap->im, uap->port.membase + UART011_IMSC);
135 static void pl011_rx_chars(struct uart_amba_port *uap)
137 struct tty_struct *tty = uap->port.state->port.tty;
138 unsigned int status, ch, flag, max_count = 256;
140 status = readw(uap->port.membase + UART01x_FR);
141 while ((status & UART01x_FR_RXFE) == 0 && max_count--) {
142 ch = readw(uap->port.membase + UART01x_DR) | UART_DUMMY_DR_RX;
144 uap->port.icount.rx++;
147 * Note that the error handling code is
148 * out of the main execution path
150 if (unlikely(ch & UART_DR_ERROR)) {
151 if (ch & UART011_DR_BE) {
152 ch &= ~(UART011_DR_FE | UART011_DR_PE);
153 uap->port.icount.brk++;
154 if (uart_handle_break(&uap->port))
156 } else if (ch & UART011_DR_PE)
157 uap->port.icount.parity++;
158 else if (ch & UART011_DR_FE)
159 uap->port.icount.frame++;
160 if (ch & UART011_DR_OE)
161 uap->port.icount.overrun++;
163 ch &= uap->port.read_status_mask;
165 if (ch & UART011_DR_BE)
167 else if (ch & UART011_DR_PE)
169 else if (ch & UART011_DR_FE)
173 if (uart_handle_sysrq_char(&uap->port, ch & 255))
176 uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag);
179 status = readw(uap->port.membase + UART01x_FR);
181 spin_unlock(&uap->port.lock);
182 tty_flip_buffer_push(tty);
183 spin_lock(&uap->port.lock);
186 static void pl011_tx_chars(struct uart_amba_port *uap)
188 struct circ_buf *xmit = &uap->port.state->xmit;
191 if (uap->port.x_char) {
192 writew(uap->port.x_char, uap->port.membase + UART01x_DR);
193 uap->port.icount.tx++;
194 uap->port.x_char = 0;
197 if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) {
198 pl011_stop_tx(&uap->port);
202 count = uap->port.fifosize >> 1;
204 writew(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR);
205 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
206 uap->port.icount.tx++;
207 if (uart_circ_empty(xmit))
209 } while (--count > 0);
211 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
212 uart_write_wakeup(&uap->port);
214 if (uart_circ_empty(xmit))
215 pl011_stop_tx(&uap->port);
218 static void pl011_modem_status(struct uart_amba_port *uap)
220 unsigned int status, delta;
222 status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
224 delta = status ^ uap->old_status;
225 uap->old_status = status;
230 if (delta & UART01x_FR_DCD)
231 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD);
233 if (delta & UART01x_FR_DSR)
234 uap->port.icount.dsr++;
236 if (delta & UART01x_FR_CTS)
237 uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS);
239 wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
242 static irqreturn_t pl011_int(int irq, void *dev_id)
244 struct uart_amba_port *uap = dev_id;
245 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
248 spin_lock(&uap->port.lock);
250 status = readw(uap->port.membase + UART011_MIS);
253 writew(status & ~(UART011_TXIS|UART011_RTIS|
255 uap->port.membase + UART011_ICR);
257 if (status & (UART011_RTIS|UART011_RXIS))
259 if (status & (UART011_DSRMIS|UART011_DCDMIS|
260 UART011_CTSMIS|UART011_RIMIS))
261 pl011_modem_status(uap);
262 if (status & UART011_TXIS)
265 if (pass_counter-- == 0)
268 status = readw(uap->port.membase + UART011_MIS);
269 } while (status != 0);
273 spin_unlock(&uap->port.lock);
275 return IRQ_RETVAL(handled);
278 static unsigned int pl01x_tx_empty(struct uart_port *port)
280 struct uart_amba_port *uap = (struct uart_amba_port *)port;
281 unsigned int status = readw(uap->port.membase + UART01x_FR);
282 return status & (UART01x_FR_BUSY|UART01x_FR_TXFF) ? 0 : TIOCSER_TEMT;
285 static unsigned int pl01x_get_mctrl(struct uart_port *port)
287 struct uart_amba_port *uap = (struct uart_amba_port *)port;
288 unsigned int result = 0;
289 unsigned int status = readw(uap->port.membase + UART01x_FR);
291 #define TIOCMBIT(uartbit, tiocmbit) \
292 if (status & uartbit) \
295 TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR);
296 TIOCMBIT(UART01x_FR_DSR, TIOCM_DSR);
297 TIOCMBIT(UART01x_FR_CTS, TIOCM_CTS);
298 TIOCMBIT(UART011_FR_RI, TIOCM_RNG);
303 static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl)
305 struct uart_amba_port *uap = (struct uart_amba_port *)port;
308 cr = readw(uap->port.membase + UART011_CR);
310 #define TIOCMBIT(tiocmbit, uartbit) \
311 if (mctrl & tiocmbit) \
316 TIOCMBIT(TIOCM_RTS, UART011_CR_RTS);
317 TIOCMBIT(TIOCM_DTR, UART011_CR_DTR);
318 TIOCMBIT(TIOCM_OUT1, UART011_CR_OUT1);
319 TIOCMBIT(TIOCM_OUT2, UART011_CR_OUT2);
320 TIOCMBIT(TIOCM_LOOP, UART011_CR_LBE);
323 /* We need to disable auto-RTS if we want to turn RTS off */
324 TIOCMBIT(TIOCM_RTS, UART011_CR_RTSEN);
328 writew(cr, uap->port.membase + UART011_CR);
331 static void pl011_break_ctl(struct uart_port *port, int break_state)
333 struct uart_amba_port *uap = (struct uart_amba_port *)port;
337 spin_lock_irqsave(&uap->port.lock, flags);
338 lcr_h = readw(uap->port.membase + uap->lcrh_tx);
339 if (break_state == -1)
340 lcr_h |= UART01x_LCRH_BRK;
342 lcr_h &= ~UART01x_LCRH_BRK;
343 writew(lcr_h, uap->port.membase + uap->lcrh_tx);
344 spin_unlock_irqrestore(&uap->port.lock, flags);
347 #ifdef CONFIG_CONSOLE_POLL
348 static int pl010_get_poll_char(struct uart_port *port)
350 struct uart_amba_port *uap = (struct uart_amba_port *)port;
353 status = readw(uap->port.membase + UART01x_FR);
354 if (status & UART01x_FR_RXFE)
357 return readw(uap->port.membase + UART01x_DR);
360 static void pl010_put_poll_char(struct uart_port *port,
363 struct uart_amba_port *uap = (struct uart_amba_port *)port;
365 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF)
368 writew(ch, uap->port.membase + UART01x_DR);
371 #endif /* CONFIG_CONSOLE_POLL */
373 static int pl011_startup(struct uart_port *port)
375 struct uart_amba_port *uap = (struct uart_amba_port *)port;
380 * Try to enable the clock producer.
382 retval = clk_enable(uap->clk);
386 uap->port.uartclk = clk_get_rate(uap->clk);
391 retval = request_irq(uap->port.irq, pl011_int, 0, "uart-pl011", uap);
395 writew(uap->ifls, uap->port.membase + UART011_IFLS);
398 * Provoke TX FIFO interrupt into asserting.
400 cr = UART01x_CR_UARTEN | UART011_CR_TXE | UART011_CR_LBE;
401 writew(cr, uap->port.membase + UART011_CR);
402 writew(0, uap->port.membase + UART011_FBRD);
403 writew(1, uap->port.membase + UART011_IBRD);
404 writew(0, uap->port.membase + uap->lcrh_rx);
405 if (uap->lcrh_tx != uap->lcrh_rx) {
408 * Wait 10 PCLKs before writing LCRH_TX register,
409 * to get this delay write read only register 10 times
411 for (i = 0; i < 10; ++i)
412 writew(0xff, uap->port.membase + UART011_MIS);
413 writew(0, uap->port.membase + uap->lcrh_tx);
415 writew(0, uap->port.membase + UART01x_DR);
416 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY)
419 cr = UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE;
420 writew(cr, uap->port.membase + UART011_CR);
423 * initialise the old status of the modem signals
425 uap->old_status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
428 * Finally, enable interrupts
430 spin_lock_irq(&uap->port.lock);
431 uap->im = UART011_RXIM | UART011_RTIM;
432 writew(uap->im, uap->port.membase + UART011_IMSC);
433 spin_unlock_irq(&uap->port.lock);
438 clk_disable(uap->clk);
443 static void pl011_shutdown_channel(struct uart_amba_port *uap,
448 val = readw(uap->port.membase + lcrh);
449 val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN);
450 writew(val, uap->port.membase + lcrh);
453 static void pl011_shutdown(struct uart_port *port)
455 struct uart_amba_port *uap = (struct uart_amba_port *)port;
458 * disable all interrupts
460 spin_lock_irq(&uap->port.lock);
462 writew(uap->im, uap->port.membase + UART011_IMSC);
463 writew(0xffff, uap->port.membase + UART011_ICR);
464 spin_unlock_irq(&uap->port.lock);
469 free_irq(uap->port.irq, uap);
474 uap->autorts = false;
475 writew(UART01x_CR_UARTEN | UART011_CR_TXE, uap->port.membase + UART011_CR);
478 * disable break condition and fifos
480 pl011_shutdown_channel(uap, uap->lcrh_rx);
481 if (uap->lcrh_rx != uap->lcrh_tx)
482 pl011_shutdown_channel(uap, uap->lcrh_tx);
485 * Shut down the clock producer
487 clk_disable(uap->clk);
491 pl011_set_termios(struct uart_port *port, struct ktermios *termios,
492 struct ktermios *old)
494 struct uart_amba_port *uap = (struct uart_amba_port *)port;
495 unsigned int lcr_h, old_cr;
497 unsigned int baud, quot;
500 * Ask the core to calculate the divisor for us.
502 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
503 quot = port->uartclk * 4 / baud;
505 switch (termios->c_cflag & CSIZE) {
507 lcr_h = UART01x_LCRH_WLEN_5;
510 lcr_h = UART01x_LCRH_WLEN_6;
513 lcr_h = UART01x_LCRH_WLEN_7;
516 lcr_h = UART01x_LCRH_WLEN_8;
519 if (termios->c_cflag & CSTOPB)
520 lcr_h |= UART01x_LCRH_STP2;
521 if (termios->c_cflag & PARENB) {
522 lcr_h |= UART01x_LCRH_PEN;
523 if (!(termios->c_cflag & PARODD))
524 lcr_h |= UART01x_LCRH_EPS;
526 if (port->fifosize > 1)
527 lcr_h |= UART01x_LCRH_FEN;
529 spin_lock_irqsave(&port->lock, flags);
532 * Update the per-port timeout.
534 uart_update_timeout(port, termios->c_cflag, baud);
536 port->read_status_mask = UART011_DR_OE | 255;
537 if (termios->c_iflag & INPCK)
538 port->read_status_mask |= UART011_DR_FE | UART011_DR_PE;
539 if (termios->c_iflag & (BRKINT | PARMRK))
540 port->read_status_mask |= UART011_DR_BE;
543 * Characters to ignore
545 port->ignore_status_mask = 0;
546 if (termios->c_iflag & IGNPAR)
547 port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE;
548 if (termios->c_iflag & IGNBRK) {
549 port->ignore_status_mask |= UART011_DR_BE;
551 * If we're ignoring parity and break indicators,
552 * ignore overruns too (for real raw support).
554 if (termios->c_iflag & IGNPAR)
555 port->ignore_status_mask |= UART011_DR_OE;
559 * Ignore all characters if CREAD is not set.
561 if ((termios->c_cflag & CREAD) == 0)
562 port->ignore_status_mask |= UART_DUMMY_DR_RX;
564 if (UART_ENABLE_MS(port, termios->c_cflag))
565 pl011_enable_ms(port);
567 /* first, disable everything */
568 old_cr = readw(port->membase + UART011_CR);
569 writew(0, port->membase + UART011_CR);
571 if (termios->c_cflag & CRTSCTS) {
572 if (old_cr & UART011_CR_RTS)
573 old_cr |= UART011_CR_RTSEN;
575 old_cr |= UART011_CR_CTSEN;
578 old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN);
579 uap->autorts = false;
583 writew(quot & 0x3f, port->membase + UART011_FBRD);
584 writew(quot >> 6, port->membase + UART011_IBRD);
587 * ----------v----------v----------v----------v-----
588 * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L
589 * ----------^----------^----------^----------^-----
591 writew(lcr_h, port->membase + uap->lcrh_rx);
592 if (uap->lcrh_rx != uap->lcrh_tx) {
595 * Wait 10 PCLKs before writing LCRH_TX register,
596 * to get this delay write read only register 10 times
598 for (i = 0; i < 10; ++i)
599 writew(0xff, uap->port.membase + UART011_MIS);
600 writew(lcr_h, port->membase + uap->lcrh_tx);
602 writew(old_cr, port->membase + UART011_CR);
604 spin_unlock_irqrestore(&port->lock, flags);
607 static const char *pl011_type(struct uart_port *port)
609 return port->type == PORT_AMBA ? "AMBA/PL011" : NULL;
613 * Release the memory region(s) being used by 'port'
615 static void pl010_release_port(struct uart_port *port)
617 release_mem_region(port->mapbase, SZ_4K);
621 * Request the memory region(s) being used by 'port'
623 static int pl010_request_port(struct uart_port *port)
625 return request_mem_region(port->mapbase, SZ_4K, "uart-pl011")
626 != NULL ? 0 : -EBUSY;
630 * Configure/autoconfigure the port.
632 static void pl010_config_port(struct uart_port *port, int flags)
634 if (flags & UART_CONFIG_TYPE) {
635 port->type = PORT_AMBA;
636 pl010_request_port(port);
641 * verify the new serial_struct (for TIOCSSERIAL).
643 static int pl010_verify_port(struct uart_port *port, struct serial_struct *ser)
646 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA)
648 if (ser->irq < 0 || ser->irq >= nr_irqs)
650 if (ser->baud_base < 9600)
655 static struct uart_ops amba_pl011_pops = {
656 .tx_empty = pl01x_tx_empty,
657 .set_mctrl = pl011_set_mctrl,
658 .get_mctrl = pl01x_get_mctrl,
659 .stop_tx = pl011_stop_tx,
660 .start_tx = pl011_start_tx,
661 .stop_rx = pl011_stop_rx,
662 .enable_ms = pl011_enable_ms,
663 .break_ctl = pl011_break_ctl,
664 .startup = pl011_startup,
665 .shutdown = pl011_shutdown,
666 .set_termios = pl011_set_termios,
668 .release_port = pl010_release_port,
669 .request_port = pl010_request_port,
670 .config_port = pl010_config_port,
671 .verify_port = pl010_verify_port,
672 #ifdef CONFIG_CONSOLE_POLL
673 .poll_get_char = pl010_get_poll_char,
674 .poll_put_char = pl010_put_poll_char,
678 static struct uart_amba_port *amba_ports[UART_NR];
680 #ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE
682 static void pl011_console_putchar(struct uart_port *port, int ch)
684 struct uart_amba_port *uap = (struct uart_amba_port *)port;
686 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF)
688 writew(ch, uap->port.membase + UART01x_DR);
692 pl011_console_write(struct console *co, const char *s, unsigned int count)
694 struct uart_amba_port *uap = amba_ports[co->index];
695 unsigned int status, old_cr, new_cr;
697 clk_enable(uap->clk);
700 * First save the CR then disable the interrupts
702 old_cr = readw(uap->port.membase + UART011_CR);
703 new_cr = old_cr & ~UART011_CR_CTSEN;
704 new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
705 writew(new_cr, uap->port.membase + UART011_CR);
707 uart_console_write(&uap->port, s, count, pl011_console_putchar);
710 * Finally, wait for transmitter to become empty
711 * and restore the TCR
714 status = readw(uap->port.membase + UART01x_FR);
715 } while (status & UART01x_FR_BUSY);
716 writew(old_cr, uap->port.membase + UART011_CR);
718 clk_disable(uap->clk);
722 pl011_console_get_options(struct uart_amba_port *uap, int *baud,
723 int *parity, int *bits)
725 if (readw(uap->port.membase + UART011_CR) & UART01x_CR_UARTEN) {
726 unsigned int lcr_h, ibrd, fbrd;
728 lcr_h = readw(uap->port.membase + uap->lcrh_tx);
731 if (lcr_h & UART01x_LCRH_PEN) {
732 if (lcr_h & UART01x_LCRH_EPS)
738 if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7)
743 ibrd = readw(uap->port.membase + UART011_IBRD);
744 fbrd = readw(uap->port.membase + UART011_FBRD);
746 *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd);
750 static int __init pl011_console_setup(struct console *co, char *options)
752 struct uart_amba_port *uap;
759 * Check whether an invalid uart number has been specified, and
760 * if so, search for the first available port that does have
763 if (co->index >= UART_NR)
765 uap = amba_ports[co->index];
769 uap->port.uartclk = clk_get_rate(uap->clk);
772 uart_parse_options(options, &baud, &parity, &bits, &flow);
774 pl011_console_get_options(uap, &baud, &parity, &bits);
776 return uart_set_options(&uap->port, co, baud, parity, bits, flow);
779 static struct uart_driver amba_reg;
780 static struct console amba_console = {
782 .write = pl011_console_write,
783 .device = uart_console_device,
784 .setup = pl011_console_setup,
785 .flags = CON_PRINTBUFFER,
790 #define AMBA_CONSOLE (&amba_console)
792 #define AMBA_CONSOLE NULL
795 static struct uart_driver amba_reg = {
796 .owner = THIS_MODULE,
797 .driver_name = "ttyAMA",
798 .dev_name = "ttyAMA",
799 .major = SERIAL_AMBA_MAJOR,
800 .minor = SERIAL_AMBA_MINOR,
802 .cons = AMBA_CONSOLE,
805 static int pl011_probe(struct amba_device *dev, struct amba_id *id)
807 struct uart_amba_port *uap;
808 struct vendor_data *vendor = id->data;
812 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
813 if (amba_ports[i] == NULL)
816 if (i == ARRAY_SIZE(amba_ports)) {
821 uap = kzalloc(sizeof(struct uart_amba_port), GFP_KERNEL);
827 base = ioremap(dev->res.start, resource_size(&dev->res));
833 uap->clk = clk_get(&dev->dev, NULL);
834 if (IS_ERR(uap->clk)) {
835 ret = PTR_ERR(uap->clk);
839 uap->ifls = vendor->ifls;
840 uap->lcrh_rx = vendor->lcrh_rx;
841 uap->lcrh_tx = vendor->lcrh_tx;
842 uap->port.dev = &dev->dev;
843 uap->port.mapbase = dev->res.start;
844 uap->port.membase = base;
845 uap->port.iotype = UPIO_MEM;
846 uap->port.irq = dev->irq[0];
847 uap->port.fifosize = vendor->fifosize;
848 uap->port.ops = &amba_pl011_pops;
849 uap->port.flags = UPF_BOOT_AUTOCONF;
854 amba_set_drvdata(dev, uap);
855 ret = uart_add_one_port(&amba_reg, &uap->port);
857 amba_set_drvdata(dev, NULL);
858 amba_ports[i] = NULL;
869 static int pl011_remove(struct amba_device *dev)
871 struct uart_amba_port *uap = amba_get_drvdata(dev);
874 amba_set_drvdata(dev, NULL);
876 uart_remove_one_port(&amba_reg, &uap->port);
878 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
879 if (amba_ports[i] == uap)
880 amba_ports[i] = NULL;
882 iounmap(uap->port.membase);
889 static int pl011_suspend(struct amba_device *dev, pm_message_t state)
891 struct uart_amba_port *uap = amba_get_drvdata(dev);
896 return uart_suspend_port(&amba_reg, &uap->port);
899 static int pl011_resume(struct amba_device *dev)
901 struct uart_amba_port *uap = amba_get_drvdata(dev);
906 return uart_resume_port(&amba_reg, &uap->port);
910 static struct amba_id pl011_ids[] __initdata = {
924 static struct amba_driver pl011_driver = {
926 .name = "uart-pl011",
928 .id_table = pl011_ids,
929 .probe = pl011_probe,
930 .remove = pl011_remove,
932 .suspend = pl011_suspend,
933 .resume = pl011_resume,
937 static int __init pl011_init(void)
940 printk(KERN_INFO "Serial: AMBA PL011 UART driver\n");
942 ret = uart_register_driver(&amba_reg);
944 ret = amba_driver_register(&pl011_driver);
946 uart_unregister_driver(&amba_reg);
951 static void __exit pl011_exit(void)
953 amba_driver_unregister(&pl011_driver);
954 uart_unregister_driver(&amba_reg);
958 * While this can be a module, if builtin it's most likely the console
959 * So let's leave module_exit but move module_init to an earlier place
961 arch_initcall(pl011_init);
962 module_exit(pl011_exit);
964 MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd");
965 MODULE_DESCRIPTION("ARM AMBA serial port driver");
966 MODULE_LICENSE("GPL");