2 * max3107.c - spi uart protocol driver for Maxim 3107
4 * by Christian Pellegrin <chripell@evolware.org>
6 * by Feng Tang <feng.tang@intel.com>
8 * Copyright (C) Aavamobile 2009
10 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
26 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
30 #include <linux/delay.h>
31 #include <linux/device.h>
32 #include <linux/serial_core.h>
33 #include <linux/serial.h>
34 #include <linux/spi/spi.h>
35 #include <linux/freezer.h>
36 #include <linux/platform_device.h>
37 #include <linux/gpio.h>
38 #include <linux/sfi.h>
48 /* UART port structure */
49 struct uart_port port;
51 /* SPI device structure */
52 struct spi_device *spi;
54 /* GPIO chip stucture */
55 struct gpio_chip chip;
57 /* Workqueue that does all the magic */
58 struct workqueue_struct *workqueue;
59 struct work_struct work;
61 /* Lock for shared data */
64 /* Device configuration */
65 int ext_clk; /* 1 if external clock used */
66 int loopback; /* Current loopback mode state */
67 int baud; /* Current baud rate */
70 int suspended; /* Indicates suspend mode */
71 int tx_fifo_empty; /* Flag for TX FIFO state */
72 int rx_enabled; /* Flag for receiver state */
73 int tx_enabled; /* Flag for transmitter state */
75 u16 irqen_reg; /* Current IRQ enable register value */
77 u16 mode1_reg; /* Current mode1 register value*/
78 int mode1_commit; /* Flag for setting new mode1 register value */
79 u16 lcr_reg; /* Current LCR register value */
80 int lcr_commit; /* Flag for setting new LCR register value */
81 u32 brg_cfg; /* Current Baud rate generator config */
82 int brg_commit; /* Flag for setting new baud rate generator
85 struct baud_table *baud_tbl;
86 int handle_irq; /* Indicates that IRQ should be handled */
88 /* Rx buffer and str*/
95 /* Platform data structure */
97 /* Loopback mode enable */
99 /* External clock enable */
101 /* HW suspend function */
102 void (*max3107_hw_suspend) (struct max3107_port *s, int suspend);
103 /* Polling mode enable */
105 /* Polling period if polling mode enabled */
109 static struct baud_table brg13_ext[] = {
110 { 300, MAX3107_BRG13_B300 },
111 { 600, MAX3107_BRG13_B600 },
112 { 1200, MAX3107_BRG13_B1200 },
113 { 2400, MAX3107_BRG13_B2400 },
114 { 4800, MAX3107_BRG13_B4800 },
115 { 9600, MAX3107_BRG13_B9600 },
116 { 19200, MAX3107_BRG13_B19200 },
117 { 57600, MAX3107_BRG13_B57600 },
118 { 115200, MAX3107_BRG13_B115200 },
119 { 230400, MAX3107_BRG13_B230400 },
120 { 460800, MAX3107_BRG13_B460800 },
121 { 921600, MAX3107_BRG13_B921600 },
125 static struct baud_table brg26_ext[] = {
126 { 300, MAX3107_BRG26_B300 },
127 { 600, MAX3107_BRG26_B600 },
128 { 1200, MAX3107_BRG26_B1200 },
129 { 2400, MAX3107_BRG26_B2400 },
130 { 4800, MAX3107_BRG26_B4800 },
131 { 9600, MAX3107_BRG26_B9600 },
132 { 19200, MAX3107_BRG26_B19200 },
133 { 57600, MAX3107_BRG26_B57600 },
134 { 115200, MAX3107_BRG26_B115200 },
135 { 230400, MAX3107_BRG26_B230400 },
136 { 460800, MAX3107_BRG26_B460800 },
137 { 921600, MAX3107_BRG26_B921600 },
141 static struct baud_table brg13_int[] = {
142 { 300, MAX3107_BRG13_IB300 },
143 { 600, MAX3107_BRG13_IB600 },
144 { 1200, MAX3107_BRG13_IB1200 },
145 { 2400, MAX3107_BRG13_IB2400 },
146 { 4800, MAX3107_BRG13_IB4800 },
147 { 9600, MAX3107_BRG13_IB9600 },
148 { 19200, MAX3107_BRG13_IB19200 },
149 { 57600, MAX3107_BRG13_IB57600 },
150 { 115200, MAX3107_BRG13_IB115200 },
151 { 230400, MAX3107_BRG13_IB230400 },
152 { 460800, MAX3107_BRG13_IB460800 },
153 { 921600, MAX3107_BRG13_IB921600 },
157 static u32 get_new_brg(int baud, struct max3107_port *s)
160 struct baud_table *baud_tbl = s->baud_tbl;
162 for (i = 0; i < 13; i++) {
163 if (baud == baud_tbl[i].baud)
164 return baud_tbl[i].new_brg;
170 /* Perform SPI transfer for write/read of device register(s) */
171 static int max3107_rw(struct max3107_port *s, u8 *tx, u8 *rx, int len)
173 struct spi_message spi_msg;
174 struct spi_transfer spi_xfer;
176 /* Initialize SPI ,message */
177 spi_message_init(&spi_msg);
179 /* Initialize SPI transfer */
180 memset(&spi_xfer, 0, sizeof spi_xfer);
182 spi_xfer.tx_buf = tx;
183 spi_xfer.rx_buf = rx;
184 spi_xfer.speed_hz = MAX3107_SPI_SPEED;
186 /* Add SPI transfer to SPI message */
187 spi_message_add_tail(&spi_xfer, &spi_msg);
189 #ifdef DBG_TRACE_SPI_DATA
192 pr_info("tx len %d:\n", spi_xfer.len);
193 for (i = 0 ; i < spi_xfer.len && i < 32 ; i++)
194 pr_info(" %x", ((u8 *)spi_xfer.tx_buf)[i]);
199 /* Perform synchronous SPI transfer */
200 if (spi_sync(s->spi, &spi_msg)) {
201 dev_err(&s->spi->dev, "spi_sync failure\n");
205 #ifdef DBG_TRACE_SPI_DATA
206 if (spi_xfer.rx_buf) {
208 pr_info("rx len %d:\n", spi_xfer.len);
209 for (i = 0 ; i < spi_xfer.len && i < 32 ; i++)
210 pr_info(" %x", ((u8 *)spi_xfer.rx_buf)[i]);
217 /* Puts received data to circular buffer */
218 static void put_data_to_circ_buf(struct max3107_port *s, unsigned char *data,
221 struct uart_port *port = &s->port;
222 struct tty_struct *tty;
227 tty = port->state->port.tty;
231 /* Insert received data */
232 tty_insert_flip_string(tty, data, len);
233 /* Update RX counter */
234 port->icount.rx += len;
237 /* Handle data receiving */
238 static void max3107_handlerx(struct max3107_port *s, u16 rxlvl)
242 int len; /* SPI transfer buffer length */
251 /* RX fifo is empty */
253 } else if (rxlvl >= MAX3107_RX_FIFO_SIZE) {
254 dev_warn(&s->spi->dev, "Possible RX FIFO overrun %d\n", rxlvl);
255 /* Ensure sanity of RX level */
256 rxlvl = MAX3107_RX_FIFO_SIZE;
258 if ((s->rxbuf == 0) || (s->rxstr == 0)) {
259 dev_warn(&s->spi->dev, "Rx buffer/str isn't ready\n");
263 valid_str = s->rxstr;
265 pr_debug("rxlvl %d\n", rxlvl);
267 memset(buf, 0, sizeof(u16) * (MAX3107_RX_FIFO_SIZE + 2));
269 if (s->irqen_reg & MAX3107_IRQ_RXFIFO_BIT) {
270 /* First disable RX FIFO interrupt */
271 pr_debug("Disabling RX INT\n");
272 buf[0] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG);
273 s->irqen_reg &= ~MAX3107_IRQ_RXFIFO_BIT;
274 buf[0] |= s->irqen_reg;
277 /* Just increase the length by amount of words in FIFO since
278 * buffer was zeroed and SPI transfer of 0x0000 means reading
282 /* Append RX level query */
283 buf[len] = MAX3107_RXFIFOLVL_REG;
286 /* Perform the SPI transfer */
287 if (max3107_rw(s, (u8 *)buf, (u8 *)buf, len * 2)) {
288 dev_err(&s->spi->dev, "SPI transfer for RX h failed\n");
292 /* Skip RX FIFO interrupt disabling word if it was added */
293 j = ((len - 1) - rxlvl);
294 /* Read received words */
295 for (i = 0; i < rxlvl; i++, j++)
296 valid_str[i] = (u8)buf[j];
297 put_data_to_circ_buf(s, valid_str, rxlvl);
298 /* Get new RX level */
299 rxlvl = (buf[len - 1] & MAX3107_SPI_RX_DATA_MASK);
303 /* RX still enabled, re-enable RX FIFO interrupt */
304 pr_debug("Enabling RX INT\n");
305 buf[0] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG);
306 s->irqen_reg |= MAX3107_IRQ_RXFIFO_BIT;
307 buf[0] |= s->irqen_reg;
308 if (max3107_rw(s, (u8 *)buf, NULL, 2))
309 dev_err(&s->spi->dev, "RX FIFO INT enabling failed\n");
312 /* Push the received data to receivers */
313 if (s->port.state->port.tty)
314 tty_flip_buffer_push(s->port.state->port.tty);
318 /* Handle data sending */
319 static void max3107_handletx(struct max3107_port *s)
321 struct circ_buf *xmit = &s->port.state->xmit;
324 int len; /* SPI transfer buffer length */
327 if (!s->tx_fifo_empty)
328 /* Don't send more data before previous data is sent */
331 if (uart_circ_empty(xmit) || uart_tx_stopped(&s->port))
332 /* No data to send or TX is stopped */
336 dev_warn(&s->spi->dev, "Txbuf isn't ready\n");
340 /* Get length of data pending in circular buffer */
341 len = uart_circ_chars_pending(xmit);
343 /* Limit to size of TX FIFO */
344 if (len > MAX3107_TX_FIFO_SIZE)
345 len = MAX3107_TX_FIFO_SIZE;
347 pr_debug("txlen %d\n", len);
349 /* Update TX counter */
350 s->port.icount.tx += len;
352 /* TX FIFO will no longer be empty */
353 s->tx_fifo_empty = 0;
356 if (s->irqen_reg & MAX3107_IRQ_TXEMPTY_BIT) {
357 /* First disable TX empty interrupt */
358 pr_debug("Disabling TE INT\n");
359 buf[i] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG);
360 s->irqen_reg &= ~MAX3107_IRQ_TXEMPTY_BIT;
361 buf[i] |= s->irqen_reg;
365 /* Add data to send */
366 spin_lock_irqsave(&s->port.lock, flags);
367 for ( ; i < len ; i++) {
368 buf[i] = (MAX3107_WRITE_BIT | MAX3107_THR_REG);
369 buf[i] |= ((u16)xmit->buf[xmit->tail] &
370 MAX3107_SPI_TX_DATA_MASK);
371 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
373 spin_unlock_irqrestore(&s->port.lock, flags);
374 if (!(s->irqen_reg & MAX3107_IRQ_TXEMPTY_BIT)) {
375 /* Enable TX empty interrupt */
376 pr_debug("Enabling TE INT\n");
377 buf[i] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG);
378 s->irqen_reg |= MAX3107_IRQ_TXEMPTY_BIT;
379 buf[i] |= s->irqen_reg;
383 if (!s->tx_enabled) {
385 pr_debug("Enable TX\n");
386 buf[i] = (MAX3107_WRITE_BIT | MAX3107_MODE1_REG);
387 spin_lock_irqsave(&s->data_lock, flags);
388 s->mode1_reg &= ~MAX3107_MODE1_TXDIS_BIT;
389 buf[i] |= s->mode1_reg;
390 spin_unlock_irqrestore(&s->data_lock, flags);
396 /* Perform the SPI transfer */
397 if (max3107_rw(s, (u8 *)buf, NULL, len*2)) {
398 dev_err(&s->spi->dev,
399 "SPI transfer TX handling failed\n");
404 /* Indicate wake up if circular buffer is getting low on data */
405 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
406 uart_write_wakeup(&s->port);
411 * Also reads and returns current RX FIFO level
413 static u16 handle_interrupt(struct max3107_port *s)
415 u16 buf[4]; /* Buffer for SPI transfers */
420 /* Read IRQ status register */
421 buf[0] = MAX3107_IRQSTS_REG;
422 /* Read status IRQ status register */
423 buf[1] = MAX3107_STS_IRQSTS_REG;
424 /* Read LSR IRQ status register */
425 buf[2] = MAX3107_LSR_IRQSTS_REG;
427 buf[3] = MAX3107_RXFIFOLVL_REG;
429 if (max3107_rw(s, (u8 *)buf, (u8 *)buf, 8)) {
430 dev_err(&s->spi->dev,
431 "SPI transfer for INTR handling failed\n");
435 irq_status = (u8)buf[0];
436 pr_debug("IRQSTS %x\n", irq_status);
437 rx_level = (buf[3] & MAX3107_SPI_RX_DATA_MASK);
439 if (irq_status & MAX3107_IRQ_LSR_BIT) {
441 if (buf[2] & MAX3107_LSR_RXTO_BIT)
442 /* RX timeout interrupt,
443 * handled by normal RX handling
445 pr_debug("RX TO INT\n");
448 if (irq_status & MAX3107_IRQ_TXEMPTY_BIT) {
449 /* Tx empty interrupt,
450 * disable TX and set tx_fifo_empty flag
452 pr_debug("TE INT, disabling TX\n");
453 buf[0] = (MAX3107_WRITE_BIT | MAX3107_MODE1_REG);
454 spin_lock_irqsave(&s->data_lock, flags);
455 s->mode1_reg |= MAX3107_MODE1_TXDIS_BIT;
456 buf[0] |= s->mode1_reg;
457 spin_unlock_irqrestore(&s->data_lock, flags);
458 if (max3107_rw(s, (u8 *)buf, NULL, 2))
459 dev_err(&s->spi->dev, "SPI transfer TX dis failed\n");
461 s->tx_fifo_empty = 1;
464 if (irq_status & MAX3107_IRQ_RXFIFO_BIT)
465 /* RX FIFO interrupt,
466 * handled by normal RX handling
468 pr_debug("RFIFO INT\n");
470 /* Return RX level */
474 /* Trigger work thread*/
475 static void max3107_dowork(struct max3107_port *s)
477 if (!work_pending(&s->work) && !freezing(current) && !s->suspended)
478 queue_work(s->workqueue, &s->work);
480 dev_warn(&s->spi->dev, "interrup isn't serviced normally!\n");
484 static void max3107_work(struct work_struct *w)
486 struct max3107_port *s = container_of(w, struct max3107_port, work);
488 int len; /* SPI transfer buffer length */
489 u16 buf[5]; /* Buffer for SPI transfers */
492 /* Start by reading current RX FIFO level */
493 buf[0] = MAX3107_RXFIFOLVL_REG;
494 if (max3107_rw(s, (u8 *)buf, (u8 *)buf, 2)) {
495 dev_err(&s->spi->dev, "SPI transfer RX lev failed\n");
498 rxlvl = (buf[0] & MAX3107_SPI_RX_DATA_MASK);
502 pr_debug("rxlvl %d\n", rxlvl);
505 max3107_handlerx(s, rxlvl);
509 /* Handle pending interrupts
510 * We also get new RX FIFO level since new data may
511 * have been received while pushing received data to
515 rxlvl = handle_interrupt(s);
521 /* Handle configuration changes */
523 spin_lock_irqsave(&s->data_lock, flags);
524 if (s->mode1_commit) {
525 pr_debug("mode1_commit\n");
526 buf[len] = (MAX3107_WRITE_BIT | MAX3107_MODE1_REG);
527 buf[len++] |= s->mode1_reg;
531 pr_debug("lcr_commit\n");
532 buf[len] = (MAX3107_WRITE_BIT | MAX3107_LCR_REG);
533 buf[len++] |= s->lcr_reg;
537 pr_debug("brg_commit\n");
538 buf[len] = (MAX3107_WRITE_BIT | MAX3107_BRGDIVMSB_REG);
539 buf[len++] |= ((s->brg_cfg >> 16) &
540 MAX3107_SPI_TX_DATA_MASK);
541 buf[len] = (MAX3107_WRITE_BIT | MAX3107_BRGDIVLSB_REG);
542 buf[len++] |= ((s->brg_cfg >> 8) &
543 MAX3107_SPI_TX_DATA_MASK);
544 buf[len] = (MAX3107_WRITE_BIT | MAX3107_BRGCFG_REG);
545 buf[len++] |= ((s->brg_cfg) & 0xff);
548 spin_unlock_irqrestore(&s->data_lock, flags);
551 if (max3107_rw(s, (u8 *)buf, NULL, len * 2))
552 dev_err(&s->spi->dev,
553 "SPI transfer config failed\n");
556 /* Reloop if interrupt handling indicated data in RX FIFO */
562 static void max3107_set_sleep(struct max3107_port *s, int mode)
564 u16 buf[1]; /* Buffer for SPI transfer */
566 pr_debug("enter, mode %d\n", mode);
568 buf[0] = (MAX3107_WRITE_BIT | MAX3107_MODE1_REG);
569 spin_lock_irqsave(&s->data_lock, flags);
571 case MAX3107_DISABLE_FORCED_SLEEP:
572 s->mode1_reg &= ~MAX3107_MODE1_FORCESLEEP_BIT;
574 case MAX3107_ENABLE_FORCED_SLEEP:
575 s->mode1_reg |= MAX3107_MODE1_FORCESLEEP_BIT;
577 case MAX3107_DISABLE_AUTOSLEEP:
578 s->mode1_reg &= ~MAX3107_MODE1_AUTOSLEEP_BIT;
580 case MAX3107_ENABLE_AUTOSLEEP:
581 s->mode1_reg |= MAX3107_MODE1_AUTOSLEEP_BIT;
584 spin_unlock_irqrestore(&s->data_lock, flags);
585 dev_warn(&s->spi->dev, "invalid sleep mode\n");
588 buf[0] |= s->mode1_reg;
589 spin_unlock_irqrestore(&s->data_lock, flags);
591 if (max3107_rw(s, (u8 *)buf, NULL, 2))
592 dev_err(&s->spi->dev, "SPI transfer sleep mode failed\n");
594 if (mode == MAX3107_DISABLE_AUTOSLEEP ||
595 mode == MAX3107_DISABLE_FORCED_SLEEP)
596 msleep(MAX3107_WAKEUP_DELAY);
599 /* Perform full register initialization */
600 static void max3107_register_init(struct max3107_port *s)
602 u16 buf[11]; /* Buffer for SPI transfers */
604 /* 1. Configure baud rate, 9600 as default */
606 /* the below is default*/
608 s->brg_cfg = MAX3107_BRG26_B9600;
609 s->baud_tbl = (struct baud_table *)brg26_ext;
611 s->brg_cfg = MAX3107_BRG13_IB9600;
612 s->baud_tbl = (struct baud_table *)brg13_int;
615 /*override for AAVA SC specific*/
616 if (mrst_platform_id() == MRST_PLATFORM_AAVA_SC) {
617 if (get_koski_build_id() <= KOSKI_EV2)
619 s->brg_cfg = MAX3107_BRG13_B9600;
620 s->baud_tbl = (struct baud_table *)brg13_ext;
624 buf[0] = (MAX3107_WRITE_BIT | MAX3107_BRGDIVMSB_REG)
625 | ((s->brg_cfg >> 16) & MAX3107_SPI_TX_DATA_MASK);
626 buf[1] = (MAX3107_WRITE_BIT | MAX3107_BRGDIVLSB_REG)
627 | ((s->brg_cfg >> 8) & MAX3107_SPI_TX_DATA_MASK);
628 buf[2] = (MAX3107_WRITE_BIT | MAX3107_BRGCFG_REG)
629 | ((s->brg_cfg) & 0xff);
631 /* 2. Configure LCR register, 8N1 mode by default */
632 s->lcr_reg = MAX3107_LCR_WORD_LEN_8;
633 buf[3] = (MAX3107_WRITE_BIT | MAX3107_LCR_REG)
636 /* 3. Configure MODE 1 register */
639 s->mode1_reg |= MAX3107_MODE1_IRQSEL_BIT;
641 s->mode1_reg |= MAX3107_MODE1_TXDIS_BIT;
645 buf[4] = (MAX3107_WRITE_BIT | MAX3107_MODE1_REG)
648 /* 4. Configure MODE 2 register */
649 buf[5] = (MAX3107_WRITE_BIT | MAX3107_MODE2_REG);
651 /* Enable loopback */
652 buf[5] |= MAX3107_MODE2_LOOPBACK_BIT;
655 buf[5] |= MAX3107_MODE2_FIFORST_BIT;
656 s->tx_fifo_empty = 1;
658 /* 5. Configure FIFO trigger level register */
659 buf[6] = (MAX3107_WRITE_BIT | MAX3107_FIFOTRIGLVL_REG);
660 /* RX FIFO trigger for 16 words, TX FIFO trigger not used */
661 buf[6] |= (MAX3107_FIFOTRIGLVL_RX(16) | MAX3107_FIFOTRIGLVL_TX(0));
663 /* 6. Configure flow control levels */
664 buf[7] = (MAX3107_WRITE_BIT | MAX3107_FLOWLVL_REG);
665 /* Flow control halt level 96, resume level 48 */
666 buf[7] |= (MAX3107_FLOWLVL_RES(48) | MAX3107_FLOWLVL_HALT(96));
668 /* 7. Configure flow control */
669 buf[8] = (MAX3107_WRITE_BIT | MAX3107_FLOWCTRL_REG);
670 /* Enable auto CTS and auto RTS flow control */
671 buf[8] |= (MAX3107_FLOWCTRL_AUTOCTS_BIT | MAX3107_FLOWCTRL_AUTORTS_BIT);
673 /* 8. Configure RX timeout register */
674 buf[9] = (MAX3107_WRITE_BIT | MAX3107_RXTO_REG);
675 /* Timeout after 48 character intervals */
678 /* 9. Configure LSR interrupt enable register */
679 buf[10] = (MAX3107_WRITE_BIT | MAX3107_LSR_IRQEN_REG);
680 /* Enable RX timeout interrupt */
681 buf[10] |= MAX3107_LSR_RXTO_BIT;
683 /* Perform SPI transfer */
684 if (max3107_rw(s, (u8 *)buf, NULL, 22))
685 dev_err(&s->spi->dev, "SPI transfer for init failed\n");
687 /* 10. Clear IRQ status register by reading it */
688 buf[0] = MAX3107_IRQSTS_REG;
690 /* 11. Configure interrupt enable register */
691 /* Enable LSR interrupt */
692 s->irqen_reg = MAX3107_IRQ_LSR_BIT;
693 /* Enable RX FIFO interrupt */
694 s->irqen_reg |= MAX3107_IRQ_RXFIFO_BIT;
695 buf[1] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG)
698 /* 12. Clear FIFO reset that was set in step 6 */
699 buf[2] = (MAX3107_WRITE_BIT | MAX3107_MODE2_REG);
701 /* Keep loopback enabled */
702 buf[2] |= MAX3107_MODE2_LOOPBACK_BIT;
705 /* Perform SPI transfer */
706 if (max3107_rw(s, (u8 *)buf, (u8 *)buf, 6))
707 dev_err(&s->spi->dev, "SPI transfer for init failed\n");
712 static irqreturn_t max3107_irq(int irqno, void *dev_id)
714 struct max3107_port *s = dev_id;
716 if (irqno != s->spi->irq) {
724 /* Trigger work thread */
730 /* HW suspension function
732 * Currently autosleep is used to decrease current consumption, alternative
733 * approach would be to set the chip to reset mode if UART is not being
734 * used but that would mess the GPIOs
737 static void max3107_hw_susp(struct max3107_port *s, int suspend)
739 pr_debug("enter, suspend %d\n", suspend);
742 /* Suspend requested,
743 * enable autosleep to decrease current consumption
746 max3107_set_sleep(s, MAX3107_ENABLE_AUTOSLEEP);
752 max3107_set_sleep(s, MAX3107_DISABLE_AUTOSLEEP);
756 /* Modem status IRQ enabling */
757 static void max3107_enable_ms(struct uart_port *port)
759 /* Modem status not supported */
762 /* Data send function */
763 static void max3107_start_tx(struct uart_port *port)
765 struct max3107_port *s = container_of(port, struct max3107_port, port);
767 /* Trigger work thread for sending data */
771 /* Function for checking that there is no pending transfers */
772 static unsigned int max3107_tx_empty(struct uart_port *port)
774 struct max3107_port *s = container_of(port, struct max3107_port, port);
776 pr_debug("returning %d\n",
777 (s->tx_fifo_empty && uart_circ_empty(&s->port.state->xmit)));
778 return s->tx_fifo_empty && uart_circ_empty(&s->port.state->xmit);
781 /* Function for stopping RX */
782 static void max3107_stop_rx(struct uart_port *port)
784 struct max3107_port *s = container_of(port, struct max3107_port, port);
787 /* Set RX disabled in MODE 1 register */
788 spin_lock_irqsave(&s->data_lock, flags);
789 s->mode1_reg |= MAX3107_MODE1_RXDIS_BIT;
791 spin_unlock_irqrestore(&s->data_lock, flags);
792 /* Set RX disabled */
794 /* Trigger work thread for doing the actual configuration change */
798 /* Function for returning control pin states */
799 static unsigned int max3107_get_mctrl(struct uart_port *port)
801 /* DCD and DSR are not wired and CTS/RTS is handled automatically
802 * so just indicate DSR and CAR asserted
804 return TIOCM_DSR | TIOCM_CAR;
807 /* Function for setting control pin states */
808 static void max3107_set_mctrl(struct uart_port *port, unsigned int mctrl)
810 /* DCD and DSR are not wired and CTS/RTS is hadnled automatically
815 /* Function for configuring UART parameters */
816 static void max3107_set_termios(struct uart_port *port,
817 struct ktermios *termios,
818 struct ktermios *old)
820 struct max3107_port *s = container_of(port, struct max3107_port, port);
821 struct tty_struct *tty;
830 tty = port->state->port.tty;
834 /* Get new LCR register values */
836 if ((termios->c_cflag & CSIZE) == CS7)
837 new_lcr |= MAX3107_LCR_WORD_LEN_7;
839 new_lcr |= MAX3107_LCR_WORD_LEN_8;
842 if (termios->c_cflag & PARENB) {
843 new_lcr |= MAX3107_LCR_PARITY_BIT;
844 if (!(termios->c_cflag & PARODD))
845 new_lcr |= MAX3107_LCR_EVENPARITY_BIT;
849 if (termios->c_cflag & CSTOPB) {
851 new_lcr |= MAX3107_LCR_STOPLEN_BIT;
854 /* Mask termios capabilities we don't support */
855 termios->c_cflag &= ~CMSPAR;
857 /* Set status ignore mask */
858 s->port.ignore_status_mask = 0;
859 if (termios->c_iflag & IGNPAR)
860 s->port.ignore_status_mask |= MAX3107_ALL_ERRORS;
862 /* Set low latency to immediately handle pushed data */
863 s->port.state->port.tty->low_latency = 1;
865 /* Get new baud rate generator configuration */
866 baud = tty_get_baud_rate(tty);
868 spin_lock_irqsave(&s->data_lock, flags);
869 new_brg = get_new_brg(baud, s);
870 /* if can't find the corrent config, use previous */
873 new_brg = s->brg_cfg;
875 spin_unlock_irqrestore(&s->data_lock, flags);
876 tty_termios_encode_baud_rate(termios, baud, baud);
879 /* Update timeout according to new baud rate */
880 uart_update_timeout(port, termios->c_cflag, baud);
882 spin_lock_irqsave(&s->data_lock, flags);
883 if (s->lcr_reg != new_lcr) {
884 s->lcr_reg = new_lcr;
887 if (s->brg_cfg != new_brg) {
888 s->brg_cfg = new_brg;
891 spin_unlock_irqrestore(&s->data_lock, flags);
893 /* Trigger work thread for doing the actual configuration change */
897 /* Port shutdown function */
898 static void max3107_shutdown(struct uart_port *port)
900 struct max3107_port *s = container_of(port, struct max3107_port, port);
904 max3107_hw_susp(s, 0);
907 /* Free the interrupt */
908 free_irq(s->spi->irq, s);
911 /* Flush and destroy work queue */
912 flush_workqueue(s->workqueue);
913 destroy_workqueue(s->workqueue);
918 max3107_hw_susp(s, 1);
921 /* Port startup function */
922 static int max3107_startup(struct uart_port *port)
924 struct max3107_port *s = container_of(port, struct max3107_port, port);
926 /* Initialize work queue */
927 s->workqueue = create_freezeable_workqueue("max3107");
929 dev_err(&s->spi->dev, "Workqueue creation failed\n");
932 INIT_WORK(&s->work, max3107_work);
935 if (request_irq(s->spi->irq, max3107_irq, IRQF_TRIGGER_FALLING,
937 dev_err(&s->spi->dev, "IRQ reguest failed\n");
938 destroy_workqueue(s->workqueue);
944 max3107_hw_susp(s, 0);
947 max3107_register_init(s);
952 /* Port type function */
953 static const char *max3107_type(struct uart_port *port)
955 struct max3107_port *s = container_of(port, struct max3107_port, port);
956 return s->spi->modalias;
959 /* Port release function */
960 static void max3107_release_port(struct uart_port *port)
965 /* Port request function */
966 static int max3107_request_port(struct uart_port *port)
972 /* Port config function */
973 static void max3107_config_port(struct uart_port *port, int flags)
975 struct max3107_port *s = container_of(port, struct max3107_port, port);
977 /* Use PORT_MAX3100 since we are at least int the same series */
978 s->port.type = PORT_MAX3100;
981 /* Port verify function */
982 static int max3107_verify_port(struct uart_port *port,
983 struct serial_struct *ser)
985 if (ser->type == PORT_UNKNOWN || ser->type == PORT_MAX3100)
991 /* Port stop TX function */
992 static void max3107_stop_tx(struct uart_port *port)
997 /* Port break control function */
998 static void max3107_break_ctl(struct uart_port *port, int break_state)
1000 /* We don't support break control, do nothing */
1003 /* GPIO direction to input function */
1004 static int max3107_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
1006 struct max3107_port *s = container_of(chip, struct max3107_port, chip);
1007 u16 buf[1]; /* Buffer for SPI transfer */
1009 if (offset >= MAX3107_GPIO_COUNT) {
1010 dev_err(&s->spi->dev, "Invalid GPIO\n");
1014 /* Read current GPIO configuration register */
1015 buf[0] = MAX3107_GPIOCFG_REG;
1016 /* Perform SPI transfer */
1017 if (max3107_rw(s, (u8 *)buf, (u8 *)buf, 2)) {
1018 dev_err(&s->spi->dev, "SPI transfer GPIO read failed\n");
1021 buf[0] &= MAX3107_SPI_RX_DATA_MASK;
1023 /* Set GPIO to input */
1024 buf[0] &= ~(0x0001 << offset);
1026 /* Write new GPIO configuration register value */
1027 buf[0] |= (MAX3107_WRITE_BIT | MAX3107_GPIOCFG_REG);
1028 /* Perform SPI transfer */
1029 if (max3107_rw(s, (u8 *)buf, NULL, 2)) {
1030 dev_err(&s->spi->dev, "SPI transfer GPIO write failed\n");
1036 /* GPIO direction to output function */
1037 static int max3107_gpio_direction_out(struct gpio_chip *chip, unsigned offset,
1040 struct max3107_port *s = container_of(chip, struct max3107_port, chip);
1041 u16 buf[2]; /* Buffer for SPI transfers */
1043 if (offset >= MAX3107_GPIO_COUNT) {
1044 dev_err(&s->spi->dev, "Invalid GPIO\n");
1048 /* Read current GPIO configuration and data registers */
1049 buf[0] = MAX3107_GPIOCFG_REG;
1050 buf[1] = MAX3107_GPIODATA_REG;
1051 /* Perform SPI transfer */
1052 if (max3107_rw(s, (u8 *)buf, (u8 *)buf, 4)) {
1053 dev_err(&s->spi->dev, "SPI transfer gpio failed\n");
1056 buf[0] &= MAX3107_SPI_RX_DATA_MASK;
1057 buf[1] &= MAX3107_SPI_RX_DATA_MASK;
1059 /* Set GPIO to output */
1060 buf[0] |= (0x0001 << offset);
1063 buf[1] |= (0x0001 << offset);
1065 buf[1] &= ~(0x0001 << offset);
1067 /* Write new GPIO configuration and data register values */
1068 buf[0] |= (MAX3107_WRITE_BIT | MAX3107_GPIOCFG_REG);
1069 buf[1] |= (MAX3107_WRITE_BIT | MAX3107_GPIODATA_REG);
1070 /* Perform SPI transfer */
1071 if (max3107_rw(s, (u8 *)buf, NULL, 4)) {
1072 dev_err(&s->spi->dev,
1073 "SPI transfer for GPIO conf data w failed\n");
1079 /* GPIO value query function */
1080 static int max3107_gpio_get(struct gpio_chip *chip, unsigned offset)
1082 struct max3107_port *s = container_of(chip, struct max3107_port, chip);
1083 u16 buf[1]; /* Buffer for SPI transfer */
1085 if (offset >= MAX3107_GPIO_COUNT) {
1086 dev_err(&s->spi->dev, "Invalid GPIO\n");
1090 /* Read current GPIO data register */
1091 buf[0] = MAX3107_GPIODATA_REG;
1092 /* Perform SPI transfer */
1093 if (max3107_rw(s, (u8 *)buf, (u8 *)buf, 2)) {
1094 dev_err(&s->spi->dev, "SPI transfer GPIO data r failed\n");
1097 buf[0] &= MAX3107_SPI_RX_DATA_MASK;
1100 return buf[0] & (0x0001 << offset);
1103 /* GPIO value set function */
1104 static void max3107_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1106 struct max3107_port *s = container_of(chip, struct max3107_port, chip);
1107 u16 buf[2]; /* Buffer for SPI transfers */
1109 if (offset >= MAX3107_GPIO_COUNT) {
1110 dev_err(&s->spi->dev, "Invalid GPIO\n");
1114 /* Read current GPIO configuration registers*/
1115 buf[0] = MAX3107_GPIODATA_REG;
1116 buf[1] = MAX3107_GPIOCFG_REG;
1117 /* Perform SPI transfer */
1118 if (max3107_rw(s, (u8 *)buf, (u8 *)buf, 4)) {
1119 dev_err(&s->spi->dev,
1120 "SPI transfer for GPIO data and config read failed\n");
1123 buf[0] &= MAX3107_SPI_RX_DATA_MASK;
1124 buf[1] &= MAX3107_SPI_RX_DATA_MASK;
1126 if (!(buf[1] & (0x0001 << offset))) {
1127 /* Configured as input, can't set value */
1128 dev_warn(&s->spi->dev,
1129 "Trying to set value for input GPIO\n");
1135 buf[0] |= (0x0001 << offset);
1137 buf[0] &= ~(0x0001 << offset);
1139 /* Write new GPIO data register value */
1140 buf[0] |= (MAX3107_WRITE_BIT | MAX3107_GPIODATA_REG);
1141 /* Perform SPI transfer */
1142 if (max3107_rw(s, (u8 *)buf, NULL, 2))
1143 dev_err(&s->spi->dev, "SPI transfer GPIO data w failed\n");
1147 static struct max3107_plat max3107_plat_data = {
1150 .max3107_hw_suspend = &max3107_hw_susp,
1155 /* Port functions */
1156 static struct uart_ops max3107_ops = {
1157 .tx_empty = max3107_tx_empty,
1158 .set_mctrl = max3107_set_mctrl,
1159 .get_mctrl = max3107_get_mctrl,
1160 .stop_tx = max3107_stop_tx,
1161 .start_tx = max3107_start_tx,
1162 .stop_rx = max3107_stop_rx,
1163 .enable_ms = max3107_enable_ms,
1164 .break_ctl = max3107_break_ctl,
1165 .startup = max3107_startup,
1166 .shutdown = max3107_shutdown,
1167 .set_termios = max3107_set_termios,
1168 .type = max3107_type,
1169 .release_port = max3107_release_port,
1170 .request_port = max3107_request_port,
1171 .config_port = max3107_config_port,
1172 .verify_port = max3107_verify_port,
1175 /* UART driver data */
1176 static struct uart_driver max3107_uart_driver = {
1177 .owner = THIS_MODULE,
1178 .driver_name = "ttyMAX",
1179 .dev_name = "ttyMAX",
1183 /* GPIO chip data */
1184 static struct gpio_chip max3107_gpio_chip = {
1185 .owner = THIS_MODULE,
1186 .direction_input = max3107_gpio_direction_in,
1187 .direction_output = max3107_gpio_direction_out,
1188 .get = max3107_gpio_get,
1189 .set = max3107_gpio_set,
1191 .base = MAX3107_GPIO_BASE,
1192 .ngpio = MAX3107_GPIO_COUNT,
1194 /* Device probe function */
1195 static int __devinit max3107_probe(struct spi_device *spi)
1197 struct max3107_port *s;
1198 struct max3107_plat *pdata = &max3107_plat_data;
1199 u16 buf[2]; /* Buffer for SPI transfers */
1202 pr_info("enter max3107 probe\n");
1204 /* Reset the chip */
1205 if (gpio_request(MAX3107_RESET_GPIO, "max3107")) {
1206 pr_err("Requesting RESET GPIO failed\n");
1209 if (gpio_direction_output(MAX3107_RESET_GPIO, 0)) {
1210 pr_err("Setting RESET GPIO to 0 failed\n");
1211 gpio_free(MAX3107_RESET_GPIO);
1214 msleep(MAX3107_RESET_DELAY);
1215 if (gpio_direction_output(MAX3107_RESET_GPIO, 1)) {
1216 pr_err("Setting RESET GPIO to 1 failed\n");
1217 gpio_free(MAX3107_RESET_GPIO);
1220 gpio_free(MAX3107_RESET_GPIO);
1221 msleep(MAX3107_WAKEUP_DELAY);
1223 /* Allocate port structure */
1224 s = kzalloc(sizeof(*s), GFP_KERNEL);
1226 pr_err("Allocating port structure failed\n");
1230 * +2 for RX FIFO interrupt
1231 * disabling and RX level query
1233 s->rxbuf = kzalloc(sizeof(u16) * (MAX3107_RX_FIFO_SIZE+2), GFP_KERNEL);
1235 pr_err("Allocating RX buffer failed\n");
1238 s->rxstr = kzalloc(sizeof(u8) * MAX3107_RX_FIFO_SIZE, GFP_KERNEL);
1240 pr_err("Allocating RX buffer failed\n");
1244 * SPI transfer buffer
1245 * +3 for TX FIFO empty
1246 * interrupt disabling and
1247 * enabling and TX enabling
1249 s->txbuf = kzalloc(sizeof(u16) * MAX3107_TX_FIFO_SIZE + 3, GFP_KERNEL);
1251 pr_err("Allocating TX buffer failed\n");
1254 /* Initialize shared data lock */
1255 spin_lock_init(&s->data_lock);
1257 /* SPI intializations */
1258 dev_set_drvdata(&spi->dev, s);
1259 spi->mode = SPI_MODE_0;
1260 spi->dev.platform_data = pdata;
1261 spi->bits_per_word = 16;
1262 s->ext_clk = pdata->ext_clk;
1263 s->loopback = pdata->loopback;
1267 /* Check REV ID to ensure we are talking to what we expect */
1268 buf[0] = MAX3107_REVID_REG;
1269 if (max3107_rw(s, (u8 *)buf, (u8 *)buf, 2)) {
1270 dev_err(&s->spi->dev, "SPI transfer for REVID read failed\n");
1273 if ((buf[0] & MAX3107_SPI_RX_DATA_MASK) != MAX3107_REVID1 &&
1274 (buf[0] & MAX3107_SPI_RX_DATA_MASK) != MAX3107_REVID2) {
1275 dev_err(&s->spi->dev, "REVID %x does not match\n",
1276 (buf[0] & MAX3107_SPI_RX_DATA_MASK));
1280 /* Disable all interrupts */
1281 buf[0] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG | 0x0000);
1284 /* Configure clock source */
1285 buf[1] = (MAX3107_WRITE_BIT | MAX3107_CLKSRC_REG);
1287 /* External clock */
1288 buf[1] |= MAX3107_CLKSRC_EXTCLK_BIT;
1292 buf[1] |= MAX3107_CLKSRC_PLLBYP_BIT;
1294 /* Perform SPI transfer */
1295 if (max3107_rw(s, (u8 *)buf, NULL, 4)) {
1296 dev_err(&s->spi->dev, "SPI transfer for init failed\n");
1300 /* Register UART driver */
1301 retval = uart_register_driver(&max3107_uart_driver);
1303 dev_err(&s->spi->dev, "Registering UART driver failed\n");
1307 /* Initialize UART port data */
1308 s->port.fifosize = 128;
1309 s->port.ops = &max3107_ops;
1311 s->port.dev = &spi->dev;
1312 s->port.uartclk = 9600;
1313 s->port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF;
1314 s->port.irq = s->spi->irq;
1315 /* Use PORT_MAX3100 since we are at least in the same series */
1316 s->port.type = PORT_MAX3100;
1319 retval = uart_add_one_port(&max3107_uart_driver, &s->port);
1321 dev_err(&s->spi->dev, "Adding UART port failed\n");
1325 /* Initialize GPIO chip data */
1326 s->chip = max3107_gpio_chip;
1327 s->chip.label = spi->modalias;
1328 s->chip.dev = &spi->dev;
1331 retval = gpiochip_add(&s->chip);
1333 dev_err(&s->spi->dev, "Adding GPIO chip failed\n");
1337 /* Temporary fix for EV2 boot problems, set modem reset to 0 */
1338 max3107_gpio_direction_out(&s->chip, 3, 0);
1340 /* Go to suspend mode */
1341 max3107_hw_susp(s, 1);
1346 /* Driver remove function */
1347 static int __devexit max3107_remove(struct spi_device *spi)
1349 struct max3107_port *s = dev_get_drvdata(&spi->dev);
1351 pr_info("enter max3107 remove\n");
1353 /* Remove GPIO chip */
1354 if (gpiochip_remove(&s->chip))
1355 dev_warn(&s->spi->dev, "Removing GPIO chip failed\n");
1358 if (uart_remove_one_port(&max3107_uart_driver, &s->port))
1359 dev_warn(&s->spi->dev, "Removing UART port failed\n");
1361 /* Unregister UART driver */
1362 uart_unregister_driver(&max3107_uart_driver);
1364 /* Free TxRx buffer */
1369 /* Free port structure */
1375 /* Driver suspend function */
1376 static int max3107_suspend(struct spi_device *spi, pm_message_t state)
1379 struct max3107_port *s = dev_get_drvdata(&spi->dev);
1381 pr_debug("enter suspend\n");
1383 /* Suspend UART port */
1384 uart_suspend_port(&max3107_uart_driver, &s->port);
1386 /* Go to suspend mode */
1387 max3107_hw_susp(s, 1);
1388 #endif /* CONFIG_PM */
1392 /* Driver resume function */
1393 static int max3107_resume(struct spi_device *spi)
1396 struct max3107_port *s = dev_get_drvdata(&spi->dev);
1398 pr_debug("enter resume\n");
1400 /* Resume from suspend */
1401 max3107_hw_susp(s, 0);
1403 /* Resume UART port */
1404 uart_resume_port(&max3107_uart_driver, &s->port);
1405 #endif /* CONFIG_PM */
1409 /* Spi driver data */
1410 static struct spi_driver max3107_driver = {
1413 .bus = &spi_bus_type,
1414 .owner = THIS_MODULE,
1416 .probe = max3107_probe,
1417 .remove = __devexit_p(max3107_remove),
1418 .suspend = max3107_suspend,
1419 .resume = max3107_resume,
1422 /* Driver init function */
1423 static int __init max3107_init(void)
1425 pr_info("enter max3107 init\n");
1426 return spi_register_driver(&max3107_driver);
1429 /* Driver exit function */
1430 static void __exit max3107_exit(void)
1432 pr_info("enter max3107 exit\n");
1433 spi_unregister_driver(&max3107_driver);
1436 module_init(max3107_init);
1437 module_exit(max3107_exit);
1439 MODULE_DESCRIPTION("MAX3107 driver");
1440 MODULE_AUTHOR("Aavamobile");
1441 MODULE_ALIAS("max3107-spi-uart");
1442 MODULE_LICENSE("GPLv2");