2 * Generic driver for the MPSC (UART mode) on Marvell parts (e.g., GT64240,
3 * GT64260, MV64340, MV64360, GT96100, ... ).
5 * Author: Mark A. Greer <mgreer@mvista.com>
7 * Based on an old MPSC driver that was in the linuxppc tree. It appears to
8 * have been created by Chris Zankel (formerly of MontaVista) but there
9 * is no proper Copyright so I'm not sure. Apparently, parts were also
10 * taken from PPCBoot (now U-Boot). Also based on drivers/serial/8250.c
13 * 2004 (c) MontaVista, Software, Inc. This file is licensed under
14 * the terms of the GNU General Public License version 2. This program
15 * is licensed "as is" without any warranty of any kind, whether express
19 * The MPSC interface is much like a typical network controller's interface.
20 * That is, you set up separate rings of descriptors for transmitting and
21 * receiving data. There is also a pool of buffers with (one buffer per
22 * descriptor) that incoming data are dma'd into or outgoing data are dma'd
25 * The MPSC requires two other controllers to be able to work. The Baud Rate
26 * Generator (BRG) provides a clock at programmable frequencies which determines
27 * the baud rate. The Serial DMA Controller (SDMA) takes incoming data from the
28 * MPSC and DMA's it into memory or DMA's outgoing data and passes it to the
29 * MPSC. It is actually the SDMA interrupt that the driver uses to keep the
30 * transmit and receive "engines" going (i.e., indicate data has been
31 * transmitted or received).
35 * 1) Some chips have an erratum where several regs cannot be
36 * read. To work around that, we keep a local copy of those regs in
39 * 2) Some chips have an erratum where the ctlr will hang when the SDMA ctlr
40 * accesses system mem with coherency enabled. For that reason, the driver
41 * assumes that coherency for that ctlr has been disabled. This means
42 * that when in a cache coherent system, the driver has to manually manage
43 * the data cache on the areas that it touches because the dma_* macro are
46 * 3) There is an erratum (on PPC) where you can't use the instruction to do
47 * a DMA_TO_DEVICE/cache clean so DMA_BIDIRECTIONAL/flushes are used in places
48 * where a DMA_TO_DEVICE/clean would have [otherwise] sufficed.
50 * 4) AFAICT, hardware flow control isn't supported by the controller --MAG.
54 #if defined(CONFIG_SERIAL_MPSC_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
58 #include <linux/module.h>
59 #include <linux/moduleparam.h>
60 #include <linux/tty.h>
61 #include <linux/tty_flip.h>
62 #include <linux/ioport.h>
63 #include <linux/init.h>
64 #include <linux/console.h>
65 #include <linux/sysrq.h>
66 #include <linux/serial.h>
67 #include <linux/serial_core.h>
68 #include <linux/delay.h>
69 #include <linux/device.h>
70 #include <linux/dma-mapping.h>
71 #include <linux/mv643xx.h>
72 #include <linux/platform_device.h>
77 #define MPSC_NUM_CTLRS 2
80 * Descriptors and buffers must be cache line aligned.
81 * Buffers lengths must be multiple of cache line size.
82 * Number of Tx & Rx descriptors must be powers of 2.
84 #define MPSC_RXR_ENTRIES 32
85 #define MPSC_RXRE_SIZE dma_get_cache_alignment()
86 #define MPSC_RXR_SIZE (MPSC_RXR_ENTRIES * MPSC_RXRE_SIZE)
87 #define MPSC_RXBE_SIZE dma_get_cache_alignment()
88 #define MPSC_RXB_SIZE (MPSC_RXR_ENTRIES * MPSC_RXBE_SIZE)
90 #define MPSC_TXR_ENTRIES 32
91 #define MPSC_TXRE_SIZE dma_get_cache_alignment()
92 #define MPSC_TXR_SIZE (MPSC_TXR_ENTRIES * MPSC_TXRE_SIZE)
93 #define MPSC_TXBE_SIZE dma_get_cache_alignment()
94 #define MPSC_TXB_SIZE (MPSC_TXR_ENTRIES * MPSC_TXBE_SIZE)
96 #define MPSC_DMA_ALLOC_SIZE (MPSC_RXR_SIZE + MPSC_RXB_SIZE + \
97 MPSC_TXR_SIZE + MPSC_TXB_SIZE + \
98 dma_get_cache_alignment() /* for alignment */)
100 /* Rx and Tx Ring entry descriptors -- assume entry size is <= cacheline size */
101 struct mpsc_rx_desc {
107 } __attribute((packed));
109 struct mpsc_tx_desc {
115 } __attribute((packed));
118 * Some regs that have the erratum that you can't read them are are shared
119 * between the two MPSC controllers. This struct contains those shared regs.
121 struct mpsc_shared_regs {
122 phys_addr_t mpsc_routing_base_p;
123 phys_addr_t sdma_intr_base_p;
125 void __iomem *mpsc_routing_base;
126 void __iomem *sdma_intr_base;
131 u32 SDMA_INTR_CAUSE_m;
132 u32 SDMA_INTR_MASK_m;
135 /* The main driver data structure */
136 struct mpsc_port_info {
137 struct uart_port port; /* Overlay uart_port structure */
139 /* Internal driver state for this ctlr */
142 tcflag_t c_iflag; /* save termios->c_iflag */
143 tcflag_t c_cflag; /* save termios->c_cflag */
145 /* Info passed in from platform */
146 u8 mirror_regs; /* Need to mirror regs? */
147 u8 cache_mgmt; /* Need manual cache mgmt? */
148 u8 brg_can_tune; /* BRG has baud tuning? */
156 /* Physical addresses of various blocks of registers (from platform) */
157 phys_addr_t mpsc_base_p;
158 phys_addr_t sdma_base_p;
159 phys_addr_t brg_base_p;
161 /* Virtual addresses of various blocks of registers (from platform) */
162 void __iomem *mpsc_base;
163 void __iomem *sdma_base;
164 void __iomem *brg_base;
166 /* Descriptor ring and buffer allocations */
168 dma_addr_t dma_region_p;
170 dma_addr_t rxr; /* Rx descriptor ring */
171 dma_addr_t rxr_p; /* Phys addr of rxr */
172 u8 *rxb; /* Rx Ring I/O buf */
173 u8 *rxb_p; /* Phys addr of rxb */
174 u32 rxr_posn; /* First desc w/ Rx data */
176 dma_addr_t txr; /* Tx descriptor ring */
177 dma_addr_t txr_p; /* Phys addr of txr */
178 u8 *txb; /* Tx Ring I/O buf */
179 u8 *txb_p; /* Phys addr of txb */
180 int txr_head; /* Where new data goes */
181 int txr_tail; /* Where sent data comes off */
182 spinlock_t tx_lock; /* transmit lock */
184 /* Mirrored values of regs we can't read (if 'mirror_regs' set) */
190 struct mpsc_shared_regs *shared_regs;
193 /* Hooks to platform-specific code */
194 int mpsc_platform_register_driver(void);
195 void mpsc_platform_unregister_driver(void);
197 /* Hooks back in to mpsc common to be called by platform-specific code */
198 struct mpsc_port_info *mpsc_device_probe(int index);
199 struct mpsc_port_info *mpsc_device_remove(int index);
201 /* Main MPSC Configuration Register Offsets */
202 #define MPSC_MMCRL 0x0000
203 #define MPSC_MMCRH 0x0004
204 #define MPSC_MPCR 0x0008
205 #define MPSC_CHR_1 0x000c
206 #define MPSC_CHR_2 0x0010
207 #define MPSC_CHR_3 0x0014
208 #define MPSC_CHR_4 0x0018
209 #define MPSC_CHR_5 0x001c
210 #define MPSC_CHR_6 0x0020
211 #define MPSC_CHR_7 0x0024
212 #define MPSC_CHR_8 0x0028
213 #define MPSC_CHR_9 0x002c
214 #define MPSC_CHR_10 0x0030
215 #define MPSC_CHR_11 0x0034
217 #define MPSC_MPCR_FRZ (1 << 9)
218 #define MPSC_MPCR_CL_5 0
219 #define MPSC_MPCR_CL_6 1
220 #define MPSC_MPCR_CL_7 2
221 #define MPSC_MPCR_CL_8 3
222 #define MPSC_MPCR_SBL_1 0
223 #define MPSC_MPCR_SBL_2 1
225 #define MPSC_CHR_2_TEV (1<<1)
226 #define MPSC_CHR_2_TA (1<<7)
227 #define MPSC_CHR_2_TTCS (1<<9)
228 #define MPSC_CHR_2_REV (1<<17)
229 #define MPSC_CHR_2_RA (1<<23)
230 #define MPSC_CHR_2_CRD (1<<25)
231 #define MPSC_CHR_2_EH (1<<31)
232 #define MPSC_CHR_2_PAR_ODD 0
233 #define MPSC_CHR_2_PAR_SPACE 1
234 #define MPSC_CHR_2_PAR_EVEN 2
235 #define MPSC_CHR_2_PAR_MARK 3
237 /* MPSC Signal Routing */
238 #define MPSC_MRR 0x0000
239 #define MPSC_RCRR 0x0004
240 #define MPSC_TCRR 0x0008
242 /* Serial DMA Controller Interface Registers */
243 #define SDMA_SDC 0x0000
244 #define SDMA_SDCM 0x0008
245 #define SDMA_RX_DESC 0x0800
246 #define SDMA_RX_BUF_PTR 0x0808
247 #define SDMA_SCRDP 0x0810
248 #define SDMA_TX_DESC 0x0c00
249 #define SDMA_SCTDP 0x0c10
250 #define SDMA_SFTDP 0x0c14
252 #define SDMA_DESC_CMDSTAT_PE (1<<0)
253 #define SDMA_DESC_CMDSTAT_CDL (1<<1)
254 #define SDMA_DESC_CMDSTAT_FR (1<<3)
255 #define SDMA_DESC_CMDSTAT_OR (1<<6)
256 #define SDMA_DESC_CMDSTAT_BR (1<<9)
257 #define SDMA_DESC_CMDSTAT_MI (1<<10)
258 #define SDMA_DESC_CMDSTAT_A (1<<11)
259 #define SDMA_DESC_CMDSTAT_AM (1<<12)
260 #define SDMA_DESC_CMDSTAT_CT (1<<13)
261 #define SDMA_DESC_CMDSTAT_C (1<<14)
262 #define SDMA_DESC_CMDSTAT_ES (1<<15)
263 #define SDMA_DESC_CMDSTAT_L (1<<16)
264 #define SDMA_DESC_CMDSTAT_F (1<<17)
265 #define SDMA_DESC_CMDSTAT_P (1<<18)
266 #define SDMA_DESC_CMDSTAT_EI (1<<23)
267 #define SDMA_DESC_CMDSTAT_O (1<<31)
269 #define SDMA_DESC_DFLT (SDMA_DESC_CMDSTAT_O | \
270 SDMA_DESC_CMDSTAT_EI)
272 #define SDMA_SDC_RFT (1<<0)
273 #define SDMA_SDC_SFM (1<<1)
274 #define SDMA_SDC_BLMR (1<<6)
275 #define SDMA_SDC_BLMT (1<<7)
276 #define SDMA_SDC_POVR (1<<8)
277 #define SDMA_SDC_RIFB (1<<9)
279 #define SDMA_SDCM_ERD (1<<7)
280 #define SDMA_SDCM_AR (1<<15)
281 #define SDMA_SDCM_STD (1<<16)
282 #define SDMA_SDCM_TXD (1<<23)
283 #define SDMA_SDCM_AT (1<<31)
285 #define SDMA_0_CAUSE_RXBUF (1<<0)
286 #define SDMA_0_CAUSE_RXERR (1<<1)
287 #define SDMA_0_CAUSE_TXBUF (1<<2)
288 #define SDMA_0_CAUSE_TXEND (1<<3)
289 #define SDMA_1_CAUSE_RXBUF (1<<8)
290 #define SDMA_1_CAUSE_RXERR (1<<9)
291 #define SDMA_1_CAUSE_TXBUF (1<<10)
292 #define SDMA_1_CAUSE_TXEND (1<<11)
294 #define SDMA_CAUSE_RX_MASK (SDMA_0_CAUSE_RXBUF | SDMA_0_CAUSE_RXERR | \
295 SDMA_1_CAUSE_RXBUF | SDMA_1_CAUSE_RXERR)
296 #define SDMA_CAUSE_TX_MASK (SDMA_0_CAUSE_TXBUF | SDMA_0_CAUSE_TXEND | \
297 SDMA_1_CAUSE_TXBUF | SDMA_1_CAUSE_TXEND)
299 /* SDMA Interrupt registers */
300 #define SDMA_INTR_CAUSE 0x0000
301 #define SDMA_INTR_MASK 0x0080
303 /* Baud Rate Generator Interface Registers */
304 #define BRG_BCR 0x0000
305 #define BRG_BTR 0x0004
308 * Define how this driver is known to the outside (we've been assigned a
309 * range on the "Low-density serial ports" major).
311 #define MPSC_MAJOR 204
312 #define MPSC_MINOR_START 44
313 #define MPSC_DRIVER_NAME "MPSC"
314 #define MPSC_DEV_NAME "ttyMM"
315 #define MPSC_VERSION "1.00"
317 static struct mpsc_port_info mpsc_ports[MPSC_NUM_CTLRS];
318 static struct mpsc_shared_regs mpsc_shared_regs;
319 static struct uart_driver mpsc_reg;
321 static void mpsc_start_rx(struct mpsc_port_info *pi);
322 static void mpsc_free_ring_mem(struct mpsc_port_info *pi);
323 static void mpsc_release_port(struct uart_port *port);
325 ******************************************************************************
327 * Baud Rate Generator Routines (BRG)
329 ******************************************************************************
332 mpsc_brg_init(struct mpsc_port_info *pi, u32 clk_src)
336 v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR);
337 v = (v & ~(0xf << 18)) | ((clk_src & 0xf) << 18);
339 if (pi->brg_can_tune)
344 writel(v, pi->brg_base + BRG_BCR);
346 writel(readl(pi->brg_base + BRG_BTR) & 0xffff0000,
347 pi->brg_base + BRG_BTR);
352 mpsc_brg_enable(struct mpsc_port_info *pi)
356 v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR);
361 writel(v, pi->brg_base + BRG_BCR);
366 mpsc_brg_disable(struct mpsc_port_info *pi)
370 v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR);
375 writel(v, pi->brg_base + BRG_BCR);
380 mpsc_set_baudrate(struct mpsc_port_info *pi, u32 baud)
383 * To set the baud, we adjust the CDV field in the BRG_BCR reg.
384 * From manual: Baud = clk / ((CDV+1)*2) ==> CDV = (clk / (baud*2)) - 1.
385 * However, the input clock is divided by 16 in the MPSC b/c of how
386 * 'MPSC_MMCRH' was set up so we have to divide the 'clk' used in our
387 * calculation by 16 to account for that. So the real calculation
388 * that accounts for the way the mpsc is set up is:
389 * CDV = (clk / (baud*2*16)) - 1 ==> CDV = (clk / (baud << 5)) - 1.
391 u32 cdv = (pi->port.uartclk / (baud << 5)) - 1;
394 mpsc_brg_disable(pi);
395 v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR);
396 v = (v & 0xffff0000) | (cdv & 0xffff);
400 writel(v, pi->brg_base + BRG_BCR);
407 ******************************************************************************
409 * Serial DMA Routines (SDMA)
411 ******************************************************************************
415 mpsc_sdma_burstsize(struct mpsc_port_info *pi, u32 burst_size)
419 pr_debug("mpsc_sdma_burstsize[%d]: burst_size: %d\n",
420 pi->port.line, burst_size);
422 burst_size >>= 3; /* Divide by 8 b/c reg values are 8-byte chunks */
425 v = 0x0; /* 1 64-bit word */
426 else if (burst_size < 4)
427 v = 0x1; /* 2 64-bit words */
428 else if (burst_size < 8)
429 v = 0x2; /* 4 64-bit words */
431 v = 0x3; /* 8 64-bit words */
433 writel((readl(pi->sdma_base + SDMA_SDC) & (0x3 << 12)) | (v << 12),
434 pi->sdma_base + SDMA_SDC);
439 mpsc_sdma_init(struct mpsc_port_info *pi, u32 burst_size)
441 pr_debug("mpsc_sdma_init[%d]: burst_size: %d\n", pi->port.line,
444 writel((readl(pi->sdma_base + SDMA_SDC) & 0x3ff) | 0x03f,
445 pi->sdma_base + SDMA_SDC);
446 mpsc_sdma_burstsize(pi, burst_size);
451 mpsc_sdma_intr_mask(struct mpsc_port_info *pi, u32 mask)
455 pr_debug("mpsc_sdma_intr_mask[%d]: mask: 0x%x\n", pi->port.line, mask);
457 old = v = (pi->mirror_regs) ? pi->shared_regs->SDMA_INTR_MASK_m :
458 readl(pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK);
466 pi->shared_regs->SDMA_INTR_MASK_m = v;
467 writel(v, pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK);
475 mpsc_sdma_intr_unmask(struct mpsc_port_info *pi, u32 mask)
479 pr_debug("mpsc_sdma_intr_unmask[%d]: mask: 0x%x\n", pi->port.line,mask);
481 v = (pi->mirror_regs) ? pi->shared_regs->SDMA_INTR_MASK_m :
482 readl(pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK);
490 pi->shared_regs->SDMA_INTR_MASK_m = v;
491 writel(v, pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK);
496 mpsc_sdma_intr_ack(struct mpsc_port_info *pi)
498 pr_debug("mpsc_sdma_intr_ack[%d]: Acknowledging IRQ\n", pi->port.line);
501 pi->shared_regs->SDMA_INTR_CAUSE_m = 0;
502 writeb(0x00, pi->shared_regs->sdma_intr_base + SDMA_INTR_CAUSE +
508 mpsc_sdma_set_rx_ring(struct mpsc_port_info *pi, struct mpsc_rx_desc *rxre_p)
510 pr_debug("mpsc_sdma_set_rx_ring[%d]: rxre_p: 0x%x\n",
511 pi->port.line, (u32) rxre_p);
513 writel((u32)rxre_p, pi->sdma_base + SDMA_SCRDP);
518 mpsc_sdma_set_tx_ring(struct mpsc_port_info *pi, struct mpsc_tx_desc *txre_p)
520 writel((u32)txre_p, pi->sdma_base + SDMA_SFTDP);
521 writel((u32)txre_p, pi->sdma_base + SDMA_SCTDP);
526 mpsc_sdma_cmd(struct mpsc_port_info *pi, u32 val)
530 v = readl(pi->sdma_base + SDMA_SDCM);
536 writel(v, pi->sdma_base + SDMA_SDCM);
542 mpsc_sdma_tx_active(struct mpsc_port_info *pi)
544 return readl(pi->sdma_base + SDMA_SDCM) & SDMA_SDCM_TXD;
548 mpsc_sdma_start_tx(struct mpsc_port_info *pi)
550 struct mpsc_tx_desc *txre, *txre_p;
552 /* If tx isn't running & there's a desc ready to go, start it */
553 if (!mpsc_sdma_tx_active(pi)) {
554 txre = (struct mpsc_tx_desc *)(pi->txr +
555 (pi->txr_tail * MPSC_TXRE_SIZE));
556 dma_cache_sync(pi->port.dev, (void *) txre, MPSC_TXRE_SIZE, DMA_FROM_DEVICE);
557 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
558 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
559 invalidate_dcache_range((ulong)txre,
560 (ulong)txre + MPSC_TXRE_SIZE);
563 if (be32_to_cpu(txre->cmdstat) & SDMA_DESC_CMDSTAT_O) {
564 txre_p = (struct mpsc_tx_desc *)(pi->txr_p +
568 mpsc_sdma_set_tx_ring(pi, txre_p);
569 mpsc_sdma_cmd(pi, SDMA_SDCM_STD | SDMA_SDCM_TXD);
577 mpsc_sdma_stop(struct mpsc_port_info *pi)
579 pr_debug("mpsc_sdma_stop[%d]: Stopping SDMA\n", pi->port.line);
581 /* Abort any SDMA transfers */
582 mpsc_sdma_cmd(pi, 0);
583 mpsc_sdma_cmd(pi, SDMA_SDCM_AR | SDMA_SDCM_AT);
585 /* Clear the SDMA current and first TX and RX pointers */
586 mpsc_sdma_set_tx_ring(pi, NULL);
587 mpsc_sdma_set_rx_ring(pi, NULL);
589 /* Disable interrupts */
590 mpsc_sdma_intr_mask(pi, 0xf);
591 mpsc_sdma_intr_ack(pi);
597 ******************************************************************************
599 * Multi-Protocol Serial Controller Routines (MPSC)
601 ******************************************************************************
605 mpsc_hw_init(struct mpsc_port_info *pi)
609 pr_debug("mpsc_hw_init[%d]: Initializing hardware\n", pi->port.line);
611 /* Set up clock routing */
612 if (pi->mirror_regs) {
613 v = pi->shared_regs->MPSC_MRR_m;
615 pi->shared_regs->MPSC_MRR_m = v;
616 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_MRR);
618 v = pi->shared_regs->MPSC_RCRR_m;
619 v = (v & ~0xf0f) | 0x100;
620 pi->shared_regs->MPSC_RCRR_m = v;
621 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_RCRR);
623 v = pi->shared_regs->MPSC_TCRR_m;
624 v = (v & ~0xf0f) | 0x100;
625 pi->shared_regs->MPSC_TCRR_m = v;
626 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_TCRR);
629 v = readl(pi->shared_regs->mpsc_routing_base + MPSC_MRR);
631 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_MRR);
633 v = readl(pi->shared_regs->mpsc_routing_base + MPSC_RCRR);
634 v = (v & ~0xf0f) | 0x100;
635 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_RCRR);
637 v = readl(pi->shared_regs->mpsc_routing_base + MPSC_TCRR);
638 v = (v & ~0xf0f) | 0x100;
639 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_TCRR);
642 /* Put MPSC in UART mode & enabel Tx/Rx egines */
643 writel(0x000004c4, pi->mpsc_base + MPSC_MMCRL);
645 /* No preamble, 16x divider, low-latency, */
646 writel(0x04400400, pi->mpsc_base + MPSC_MMCRH);
648 if (pi->mirror_regs) {
649 pi->MPSC_CHR_1_m = 0;
650 pi->MPSC_CHR_2_m = 0;
652 writel(0, pi->mpsc_base + MPSC_CHR_1);
653 writel(0, pi->mpsc_base + MPSC_CHR_2);
654 writel(pi->mpsc_max_idle, pi->mpsc_base + MPSC_CHR_3);
655 writel(0, pi->mpsc_base + MPSC_CHR_4);
656 writel(0, pi->mpsc_base + MPSC_CHR_5);
657 writel(0, pi->mpsc_base + MPSC_CHR_6);
658 writel(0, pi->mpsc_base + MPSC_CHR_7);
659 writel(0, pi->mpsc_base + MPSC_CHR_8);
660 writel(0, pi->mpsc_base + MPSC_CHR_9);
661 writel(0, pi->mpsc_base + MPSC_CHR_10);
667 mpsc_enter_hunt(struct mpsc_port_info *pi)
669 pr_debug("mpsc_enter_hunt[%d]: Hunting...\n", pi->port.line);
671 if (pi->mirror_regs) {
672 writel(pi->MPSC_CHR_2_m | MPSC_CHR_2_EH,
673 pi->mpsc_base + MPSC_CHR_2);
674 /* Erratum prevents reading CHR_2 so just delay for a while */
678 writel(readl(pi->mpsc_base + MPSC_CHR_2) | MPSC_CHR_2_EH,
679 pi->mpsc_base + MPSC_CHR_2);
681 while (readl(pi->mpsc_base + MPSC_CHR_2) & MPSC_CHR_2_EH)
689 mpsc_freeze(struct mpsc_port_info *pi)
693 pr_debug("mpsc_freeze[%d]: Freezing\n", pi->port.line);
695 v = (pi->mirror_regs) ? pi->MPSC_MPCR_m :
696 readl(pi->mpsc_base + MPSC_MPCR);
701 writel(v, pi->mpsc_base + MPSC_MPCR);
706 mpsc_unfreeze(struct mpsc_port_info *pi)
710 v = (pi->mirror_regs) ? pi->MPSC_MPCR_m :
711 readl(pi->mpsc_base + MPSC_MPCR);
716 writel(v, pi->mpsc_base + MPSC_MPCR);
718 pr_debug("mpsc_unfreeze[%d]: Unfrozen\n", pi->port.line);
723 mpsc_set_char_length(struct mpsc_port_info *pi, u32 len)
727 pr_debug("mpsc_set_char_length[%d]: char len: %d\n", pi->port.line,len);
729 v = (pi->mirror_regs) ? pi->MPSC_MPCR_m :
730 readl(pi->mpsc_base + MPSC_MPCR);
731 v = (v & ~(0x3 << 12)) | ((len & 0x3) << 12);
735 writel(v, pi->mpsc_base + MPSC_MPCR);
740 mpsc_set_stop_bit_length(struct mpsc_port_info *pi, u32 len)
744 pr_debug("mpsc_set_stop_bit_length[%d]: stop bits: %d\n",
747 v = (pi->mirror_regs) ? pi->MPSC_MPCR_m :
748 readl(pi->mpsc_base + MPSC_MPCR);
750 v = (v & ~(1 << 14)) | ((len & 0x1) << 14);
754 writel(v, pi->mpsc_base + MPSC_MPCR);
759 mpsc_set_parity(struct mpsc_port_info *pi, u32 p)
763 pr_debug("mpsc_set_parity[%d]: parity bits: 0x%x\n", pi->port.line, p);
765 v = (pi->mirror_regs) ? pi->MPSC_CHR_2_m :
766 readl(pi->mpsc_base + MPSC_CHR_2);
769 v = (v & ~0xc000c) | (p << 18) | (p << 2);
772 pi->MPSC_CHR_2_m = v;
773 writel(v, pi->mpsc_base + MPSC_CHR_2);
778 ******************************************************************************
780 * Driver Init Routines
782 ******************************************************************************
786 mpsc_init_hw(struct mpsc_port_info *pi)
788 pr_debug("mpsc_init_hw[%d]: Initializing\n", pi->port.line);
790 mpsc_brg_init(pi, pi->brg_clk_src);
792 mpsc_sdma_init(pi, dma_get_cache_alignment()); /* burst a cacheline */
800 mpsc_alloc_ring_mem(struct mpsc_port_info *pi)
804 pr_debug("mpsc_alloc_ring_mem[%d]: Allocating ring mem\n",
807 if (!pi->dma_region) {
808 if (!dma_supported(pi->port.dev, 0xffffffff)) {
809 printk(KERN_ERR "MPSC: Inadequate DMA support\n");
812 else if ((pi->dma_region = dma_alloc_noncoherent(pi->port.dev,
813 MPSC_DMA_ALLOC_SIZE, &pi->dma_region_p, GFP_KERNEL))
816 printk(KERN_ERR "MPSC: Can't alloc Desc region\n");
825 mpsc_free_ring_mem(struct mpsc_port_info *pi)
827 pr_debug("mpsc_free_ring_mem[%d]: Freeing ring mem\n", pi->port.line);
829 if (pi->dma_region) {
830 dma_free_noncoherent(pi->port.dev, MPSC_DMA_ALLOC_SIZE,
831 pi->dma_region, pi->dma_region_p);
832 pi->dma_region = NULL;
833 pi->dma_region_p = (dma_addr_t) NULL;
840 mpsc_init_rings(struct mpsc_port_info *pi)
842 struct mpsc_rx_desc *rxre;
843 struct mpsc_tx_desc *txre;
848 pr_debug("mpsc_init_rings[%d]: Initializing rings\n", pi->port.line);
850 BUG_ON(pi->dma_region == NULL);
852 memset(pi->dma_region, 0, MPSC_DMA_ALLOC_SIZE);
855 * Descriptors & buffers are multiples of cacheline size and must be
858 dp = ALIGN((u32) pi->dma_region, dma_get_cache_alignment());
859 dp_p = ALIGN((u32) pi->dma_region_p, dma_get_cache_alignment());
862 * Partition dma region into rx ring descriptor, rx buffers,
863 * tx ring descriptors, and tx buffers.
868 dp_p += MPSC_RXR_SIZE;
871 pi->rxb_p = (u8 *) dp_p;
873 dp_p += MPSC_RXB_SIZE;
880 dp_p += MPSC_TXR_SIZE;
883 pi->txb_p = (u8 *) dp_p;
888 /* Init rx ring descriptors */
894 for (i = 0; i < MPSC_RXR_ENTRIES; i++) {
895 rxre = (struct mpsc_rx_desc *)dp;
897 rxre->bufsize = cpu_to_be16(MPSC_RXBE_SIZE);
898 rxre->bytecnt = cpu_to_be16(0);
899 rxre->cmdstat = cpu_to_be32(SDMA_DESC_CMDSTAT_O |
900 SDMA_DESC_CMDSTAT_EI |
901 SDMA_DESC_CMDSTAT_F |
902 SDMA_DESC_CMDSTAT_L);
903 rxre->link = cpu_to_be32(dp_p + MPSC_RXRE_SIZE);
904 rxre->buf_ptr = cpu_to_be32(bp_p);
906 dp += MPSC_RXRE_SIZE;
907 dp_p += MPSC_RXRE_SIZE;
908 bp += MPSC_RXBE_SIZE;
909 bp_p += MPSC_RXBE_SIZE;
911 rxre->link = cpu_to_be32(pi->rxr_p); /* Wrap last back to first */
913 /* Init tx ring descriptors */
919 for (i = 0; i < MPSC_TXR_ENTRIES; i++) {
920 txre = (struct mpsc_tx_desc *)dp;
922 txre->link = cpu_to_be32(dp_p + MPSC_TXRE_SIZE);
923 txre->buf_ptr = cpu_to_be32(bp_p);
925 dp += MPSC_TXRE_SIZE;
926 dp_p += MPSC_TXRE_SIZE;
927 bp += MPSC_TXBE_SIZE;
928 bp_p += MPSC_TXBE_SIZE;
930 txre->link = cpu_to_be32(pi->txr_p); /* Wrap last back to first */
932 dma_cache_sync(pi->port.dev, (void *) pi->dma_region, MPSC_DMA_ALLOC_SIZE,
934 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
935 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
936 flush_dcache_range((ulong)pi->dma_region,
937 (ulong)pi->dma_region + MPSC_DMA_ALLOC_SIZE);
944 mpsc_uninit_rings(struct mpsc_port_info *pi)
946 pr_debug("mpsc_uninit_rings[%d]: Uninitializing rings\n",pi->port.line);
948 BUG_ON(pi->dma_region == NULL);
967 mpsc_make_ready(struct mpsc_port_info *pi)
971 pr_debug("mpsc_make_ready[%d]: Making cltr ready\n", pi->port.line);
975 if ((rc = mpsc_alloc_ring_mem(pi)))
985 ******************************************************************************
987 * Interrupt Handling Routines
989 ******************************************************************************
993 mpsc_rx_intr(struct mpsc_port_info *pi)
995 struct mpsc_rx_desc *rxre;
996 struct tty_struct *tty = pi->port.info->tty;
997 u32 cmdstat, bytes_in, i;
1000 char flag = TTY_NORMAL;
1002 pr_debug("mpsc_rx_intr[%d]: Handling Rx intr\n", pi->port.line);
1004 rxre = (struct mpsc_rx_desc *)(pi->rxr + (pi->rxr_posn*MPSC_RXRE_SIZE));
1006 dma_cache_sync(pi->port.dev, (void *)rxre, MPSC_RXRE_SIZE, DMA_FROM_DEVICE);
1007 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1008 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1009 invalidate_dcache_range((ulong)rxre,
1010 (ulong)rxre + MPSC_RXRE_SIZE);
1014 * Loop through Rx descriptors handling ones that have been completed.
1016 while (!((cmdstat = be32_to_cpu(rxre->cmdstat)) & SDMA_DESC_CMDSTAT_O)){
1017 bytes_in = be16_to_cpu(rxre->bytecnt);
1019 /* Following use of tty struct directly is deprecated */
1020 if (unlikely(tty_buffer_request_room(tty, bytes_in) < bytes_in)) {
1021 if (tty->low_latency)
1022 tty_flip_buffer_push(tty);
1024 * If this failed then we will throw away the bytes
1025 * but must do so to clear interrupts.
1029 bp = pi->rxb + (pi->rxr_posn * MPSC_RXBE_SIZE);
1030 dma_cache_sync(pi->port.dev, (void *) bp, MPSC_RXBE_SIZE, DMA_FROM_DEVICE);
1031 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1032 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1033 invalidate_dcache_range((ulong)bp,
1034 (ulong)bp + MPSC_RXBE_SIZE);
1038 * Other than for parity error, the manual provides little
1039 * info on what data will be in a frame flagged by any of
1040 * these errors. For parity error, it is the last byte in
1041 * the buffer that had the error. As for the rest, I guess
1042 * we'll assume there is no data in the buffer.
1043 * If there is...it gets lost.
1045 if (unlikely(cmdstat & (SDMA_DESC_CMDSTAT_BR |
1046 SDMA_DESC_CMDSTAT_FR | SDMA_DESC_CMDSTAT_OR))) {
1048 pi->port.icount.rx++;
1050 if (cmdstat & SDMA_DESC_CMDSTAT_BR) { /* Break */
1051 pi->port.icount.brk++;
1053 if (uart_handle_break(&pi->port))
1056 else if (cmdstat & SDMA_DESC_CMDSTAT_FR)/* Framing */
1057 pi->port.icount.frame++;
1058 else if (cmdstat & SDMA_DESC_CMDSTAT_OR) /* Overrun */
1059 pi->port.icount.overrun++;
1061 cmdstat &= pi->port.read_status_mask;
1063 if (cmdstat & SDMA_DESC_CMDSTAT_BR)
1065 else if (cmdstat & SDMA_DESC_CMDSTAT_FR)
1067 else if (cmdstat & SDMA_DESC_CMDSTAT_OR)
1069 else if (cmdstat & SDMA_DESC_CMDSTAT_PE)
1073 if (uart_handle_sysrq_char(&pi->port, *bp)) {
1079 if ((unlikely(cmdstat & (SDMA_DESC_CMDSTAT_BR |
1080 SDMA_DESC_CMDSTAT_FR | SDMA_DESC_CMDSTAT_OR))) &&
1081 !(cmdstat & pi->port.ignore_status_mask))
1083 tty_insert_flip_char(tty, *bp, flag);
1085 for (i=0; i<bytes_in; i++)
1086 tty_insert_flip_char(tty, *bp++, TTY_NORMAL);
1088 pi->port.icount.rx += bytes_in;
1092 rxre->bytecnt = cpu_to_be16(0);
1094 rxre->cmdstat = cpu_to_be32(SDMA_DESC_CMDSTAT_O |
1095 SDMA_DESC_CMDSTAT_EI |
1096 SDMA_DESC_CMDSTAT_F |
1097 SDMA_DESC_CMDSTAT_L);
1099 dma_cache_sync(pi->port.dev, (void *)rxre, MPSC_RXRE_SIZE, DMA_BIDIRECTIONAL);
1100 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1101 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1102 flush_dcache_range((ulong)rxre,
1103 (ulong)rxre + MPSC_RXRE_SIZE);
1106 /* Advance to next descriptor */
1107 pi->rxr_posn = (pi->rxr_posn + 1) & (MPSC_RXR_ENTRIES - 1);
1108 rxre = (struct mpsc_rx_desc *)(pi->rxr +
1109 (pi->rxr_posn * MPSC_RXRE_SIZE));
1110 dma_cache_sync(pi->port.dev, (void *)rxre, MPSC_RXRE_SIZE, DMA_FROM_DEVICE);
1111 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1112 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1113 invalidate_dcache_range((ulong)rxre,
1114 (ulong)rxre + MPSC_RXRE_SIZE);
1120 /* Restart rx engine, if its stopped */
1121 if ((readl(pi->sdma_base + SDMA_SDCM) & SDMA_SDCM_ERD) == 0)
1124 tty_flip_buffer_push(tty);
1129 mpsc_setup_tx_desc(struct mpsc_port_info *pi, u32 count, u32 intr)
1131 struct mpsc_tx_desc *txre;
1133 txre = (struct mpsc_tx_desc *)(pi->txr +
1134 (pi->txr_head * MPSC_TXRE_SIZE));
1136 txre->bytecnt = cpu_to_be16(count);
1137 txre->shadow = txre->bytecnt;
1138 wmb(); /* ensure cmdstat is last field updated */
1139 txre->cmdstat = cpu_to_be32(SDMA_DESC_CMDSTAT_O | SDMA_DESC_CMDSTAT_F |
1140 SDMA_DESC_CMDSTAT_L | ((intr) ?
1141 SDMA_DESC_CMDSTAT_EI
1144 dma_cache_sync(pi->port.dev, (void *) txre, MPSC_TXRE_SIZE, DMA_BIDIRECTIONAL);
1145 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1146 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1147 flush_dcache_range((ulong)txre,
1148 (ulong)txre + MPSC_TXRE_SIZE);
1155 mpsc_copy_tx_data(struct mpsc_port_info *pi)
1157 struct circ_buf *xmit = &pi->port.info->xmit;
1161 /* Make sure the desc ring isn't full */
1162 while (CIRC_CNT(pi->txr_head, pi->txr_tail, MPSC_TXR_ENTRIES) <
1163 (MPSC_TXR_ENTRIES - 1)) {
1164 if (pi->port.x_char) {
1166 * Ideally, we should use the TCS field in
1167 * CHR_1 to put the x_char out immediately but
1168 * errata prevents us from being able to read
1169 * CHR_2 to know that its safe to write to
1170 * CHR_1. Instead, just put it in-band with
1171 * all the other Tx data.
1173 bp = pi->txb + (pi->txr_head * MPSC_TXBE_SIZE);
1174 *bp = pi->port.x_char;
1175 pi->port.x_char = 0;
1178 else if (!uart_circ_empty(xmit) && !uart_tx_stopped(&pi->port)){
1179 i = min((u32) MPSC_TXBE_SIZE,
1180 (u32) uart_circ_chars_pending(xmit));
1181 i = min(i, (u32) CIRC_CNT_TO_END(xmit->head, xmit->tail,
1183 bp = pi->txb + (pi->txr_head * MPSC_TXBE_SIZE);
1184 memcpy(bp, &xmit->buf[xmit->tail], i);
1185 xmit->tail = (xmit->tail + i) & (UART_XMIT_SIZE - 1);
1187 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1188 uart_write_wakeup(&pi->port);
1190 else /* All tx data copied into ring bufs */
1193 dma_cache_sync(pi->port.dev, (void *) bp, MPSC_TXBE_SIZE, DMA_BIDIRECTIONAL);
1194 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1195 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1196 flush_dcache_range((ulong)bp,
1197 (ulong)bp + MPSC_TXBE_SIZE);
1199 mpsc_setup_tx_desc(pi, i, 1);
1201 /* Advance to next descriptor */
1202 pi->txr_head = (pi->txr_head + 1) & (MPSC_TXR_ENTRIES - 1);
1209 mpsc_tx_intr(struct mpsc_port_info *pi)
1211 struct mpsc_tx_desc *txre;
1213 unsigned long iflags;
1215 spin_lock_irqsave(&pi->tx_lock, iflags);
1217 if (!mpsc_sdma_tx_active(pi)) {
1218 txre = (struct mpsc_tx_desc *)(pi->txr +
1219 (pi->txr_tail * MPSC_TXRE_SIZE));
1221 dma_cache_sync(pi->port.dev, (void *) txre, MPSC_TXRE_SIZE, DMA_FROM_DEVICE);
1222 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1223 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1224 invalidate_dcache_range((ulong)txre,
1225 (ulong)txre + MPSC_TXRE_SIZE);
1228 while (!(be32_to_cpu(txre->cmdstat) & SDMA_DESC_CMDSTAT_O)) {
1230 pi->port.icount.tx += be16_to_cpu(txre->bytecnt);
1231 pi->txr_tail = (pi->txr_tail+1) & (MPSC_TXR_ENTRIES-1);
1233 /* If no more data to tx, fall out of loop */
1234 if (pi->txr_head == pi->txr_tail)
1237 txre = (struct mpsc_tx_desc *)(pi->txr +
1238 (pi->txr_tail * MPSC_TXRE_SIZE));
1239 dma_cache_sync(pi->port.dev, (void *) txre, MPSC_TXRE_SIZE,
1241 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1242 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1243 invalidate_dcache_range((ulong)txre,
1244 (ulong)txre + MPSC_TXRE_SIZE);
1248 mpsc_copy_tx_data(pi);
1249 mpsc_sdma_start_tx(pi); /* start next desc if ready */
1252 spin_unlock_irqrestore(&pi->tx_lock, iflags);
1257 * This is the driver's interrupt handler. To avoid a race, we first clear
1258 * the interrupt, then handle any completed Rx/Tx descriptors. When done
1259 * handling those descriptors, we restart the Rx/Tx engines if they're stopped.
1262 mpsc_sdma_intr(int irq, void *dev_id)
1264 struct mpsc_port_info *pi = dev_id;
1268 pr_debug("mpsc_sdma_intr[%d]: SDMA Interrupt Received\n",pi->port.line);
1270 spin_lock_irqsave(&pi->port.lock, iflags);
1271 mpsc_sdma_intr_ack(pi);
1272 if (mpsc_rx_intr(pi))
1274 if (mpsc_tx_intr(pi))
1276 spin_unlock_irqrestore(&pi->port.lock, iflags);
1278 pr_debug("mpsc_sdma_intr[%d]: SDMA Interrupt Handled\n", pi->port.line);
1283 ******************************************************************************
1285 * serial_core.c Interface routines
1287 ******************************************************************************
1290 mpsc_tx_empty(struct uart_port *port)
1292 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1296 spin_lock_irqsave(&pi->port.lock, iflags);
1297 rc = mpsc_sdma_tx_active(pi) ? 0 : TIOCSER_TEMT;
1298 spin_unlock_irqrestore(&pi->port.lock, iflags);
1304 mpsc_set_mctrl(struct uart_port *port, uint mctrl)
1306 /* Have no way to set modem control lines AFAICT */
1311 mpsc_get_mctrl(struct uart_port *port)
1313 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1316 status = (pi->mirror_regs) ? pi->MPSC_CHR_10_m :
1317 readl(pi->mpsc_base + MPSC_CHR_10);
1321 mflags |= TIOCM_CTS;
1323 mflags |= TIOCM_CAR;
1325 return mflags | TIOCM_DSR; /* No way to tell if DSR asserted */
1329 mpsc_stop_tx(struct uart_port *port)
1331 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1333 pr_debug("mpsc_stop_tx[%d]\n", port->line);
1340 mpsc_start_tx(struct uart_port *port)
1342 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1343 unsigned long iflags;
1345 spin_lock_irqsave(&pi->tx_lock, iflags);
1348 mpsc_copy_tx_data(pi);
1349 mpsc_sdma_start_tx(pi);
1351 spin_unlock_irqrestore(&pi->tx_lock, iflags);
1353 pr_debug("mpsc_start_tx[%d]\n", port->line);
1358 mpsc_start_rx(struct mpsc_port_info *pi)
1360 pr_debug("mpsc_start_rx[%d]: Starting...\n", pi->port.line);
1363 mpsc_enter_hunt(pi);
1364 mpsc_sdma_cmd(pi, SDMA_SDCM_ERD);
1370 mpsc_stop_rx(struct uart_port *port)
1372 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1374 pr_debug("mpsc_stop_rx[%d]: Stopping...\n", port->line);
1376 if (pi->mirror_regs) {
1377 writel(pi->MPSC_CHR_2_m | MPSC_CHR_2_RA,
1378 pi->mpsc_base + MPSC_CHR_2);
1379 /* Erratum prevents reading CHR_2 so just delay for a while */
1383 writel(readl(pi->mpsc_base + MPSC_CHR_2) | MPSC_CHR_2_RA,
1384 pi->mpsc_base + MPSC_CHR_2);
1386 while (readl(pi->mpsc_base + MPSC_CHR_2) & MPSC_CHR_2_RA)
1390 mpsc_sdma_cmd(pi, SDMA_SDCM_AR);
1395 mpsc_enable_ms(struct uart_port *port)
1397 return; /* Not supported */
1401 mpsc_break_ctl(struct uart_port *port, int ctl)
1403 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1407 v = ctl ? 0x00ff0000 : 0;
1409 spin_lock_irqsave(&pi->port.lock, flags);
1410 if (pi->mirror_regs)
1411 pi->MPSC_CHR_1_m = v;
1412 writel(v, pi->mpsc_base + MPSC_CHR_1);
1413 spin_unlock_irqrestore(&pi->port.lock, flags);
1419 mpsc_startup(struct uart_port *port)
1421 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1425 pr_debug("mpsc_startup[%d]: Starting up MPSC, irq: %d\n",
1426 port->line, pi->port.irq);
1428 if ((rc = mpsc_make_ready(pi)) == 0) {
1429 /* Setup IRQ handler */
1430 mpsc_sdma_intr_ack(pi);
1432 /* If irq's are shared, need to set flag */
1433 if (mpsc_ports[0].port.irq == mpsc_ports[1].port.irq)
1436 if (request_irq(pi->port.irq, mpsc_sdma_intr, flag,
1438 printk(KERN_ERR "MPSC: Can't get SDMA IRQ %d\n",
1441 mpsc_sdma_intr_unmask(pi, 0xf);
1442 mpsc_sdma_set_rx_ring(pi, (struct mpsc_rx_desc *)(pi->rxr_p +
1443 (pi->rxr_posn * MPSC_RXRE_SIZE)));
1450 mpsc_shutdown(struct uart_port *port)
1452 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1454 pr_debug("mpsc_shutdown[%d]: Shutting down MPSC\n", port->line);
1457 free_irq(pi->port.irq, pi);
1462 mpsc_set_termios(struct uart_port *port, struct ktermios *termios,
1463 struct ktermios *old)
1465 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1468 u32 chr_bits, stop_bits, par;
1470 pi->c_iflag = termios->c_iflag;
1471 pi->c_cflag = termios->c_cflag;
1473 switch (termios->c_cflag & CSIZE) {
1475 chr_bits = MPSC_MPCR_CL_5;
1478 chr_bits = MPSC_MPCR_CL_6;
1481 chr_bits = MPSC_MPCR_CL_7;
1485 chr_bits = MPSC_MPCR_CL_8;
1489 if (termios->c_cflag & CSTOPB)
1490 stop_bits = MPSC_MPCR_SBL_2;
1492 stop_bits = MPSC_MPCR_SBL_1;
1494 par = MPSC_CHR_2_PAR_EVEN;
1495 if (termios->c_cflag & PARENB)
1496 if (termios->c_cflag & PARODD)
1497 par = MPSC_CHR_2_PAR_ODD;
1499 if (termios->c_cflag & CMSPAR) {
1500 if (termios->c_cflag & PARODD)
1501 par = MPSC_CHR_2_PAR_MARK;
1503 par = MPSC_CHR_2_PAR_SPACE;
1507 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk);
1509 spin_lock_irqsave(&pi->port.lock, flags);
1511 uart_update_timeout(port, termios->c_cflag, baud);
1513 mpsc_set_char_length(pi, chr_bits);
1514 mpsc_set_stop_bit_length(pi, stop_bits);
1515 mpsc_set_parity(pi, par);
1516 mpsc_set_baudrate(pi, baud);
1518 /* Characters/events to read */
1519 pi->port.read_status_mask = SDMA_DESC_CMDSTAT_OR;
1521 if (termios->c_iflag & INPCK)
1522 pi->port.read_status_mask |= SDMA_DESC_CMDSTAT_PE |
1523 SDMA_DESC_CMDSTAT_FR;
1525 if (termios->c_iflag & (BRKINT | PARMRK))
1526 pi->port.read_status_mask |= SDMA_DESC_CMDSTAT_BR;
1528 /* Characters/events to ignore */
1529 pi->port.ignore_status_mask = 0;
1531 if (termios->c_iflag & IGNPAR)
1532 pi->port.ignore_status_mask |= SDMA_DESC_CMDSTAT_PE |
1533 SDMA_DESC_CMDSTAT_FR;
1535 if (termios->c_iflag & IGNBRK) {
1536 pi->port.ignore_status_mask |= SDMA_DESC_CMDSTAT_BR;
1538 if (termios->c_iflag & IGNPAR)
1539 pi->port.ignore_status_mask |= SDMA_DESC_CMDSTAT_OR;
1542 if ((termios->c_cflag & CREAD)) {
1543 if (!pi->rcv_data) {
1547 } else if (pi->rcv_data) {
1552 spin_unlock_irqrestore(&pi->port.lock, flags);
1557 mpsc_type(struct uart_port *port)
1559 pr_debug("mpsc_type[%d]: port type: %s\n", port->line,MPSC_DRIVER_NAME);
1560 return MPSC_DRIVER_NAME;
1564 mpsc_request_port(struct uart_port *port)
1566 /* Should make chip/platform specific call */
1571 mpsc_release_port(struct uart_port *port)
1573 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1576 mpsc_uninit_rings(pi);
1577 mpsc_free_ring_mem(pi);
1585 mpsc_config_port(struct uart_port *port, int flags)
1591 mpsc_verify_port(struct uart_port *port, struct serial_struct *ser)
1593 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1596 pr_debug("mpsc_verify_port[%d]: Verifying port data\n", pi->port.line);
1598 if (ser->type != PORT_UNKNOWN && ser->type != PORT_MPSC)
1600 else if (pi->port.irq != ser->irq)
1602 else if (ser->io_type != SERIAL_IO_MEM)
1604 else if (pi->port.uartclk / 16 != ser->baud_base) /* Not sure */
1606 else if ((void *)pi->port.mapbase != ser->iomem_base)
1608 else if (pi->port.iobase != ser->port)
1610 else if (ser->hub6 != 0)
1616 static struct uart_ops mpsc_pops = {
1617 .tx_empty = mpsc_tx_empty,
1618 .set_mctrl = mpsc_set_mctrl,
1619 .get_mctrl = mpsc_get_mctrl,
1620 .stop_tx = mpsc_stop_tx,
1621 .start_tx = mpsc_start_tx,
1622 .stop_rx = mpsc_stop_rx,
1623 .enable_ms = mpsc_enable_ms,
1624 .break_ctl = mpsc_break_ctl,
1625 .startup = mpsc_startup,
1626 .shutdown = mpsc_shutdown,
1627 .set_termios = mpsc_set_termios,
1629 .release_port = mpsc_release_port,
1630 .request_port = mpsc_request_port,
1631 .config_port = mpsc_config_port,
1632 .verify_port = mpsc_verify_port,
1636 ******************************************************************************
1638 * Console Interface Routines
1640 ******************************************************************************
1643 #ifdef CONFIG_SERIAL_MPSC_CONSOLE
1645 mpsc_console_write(struct console *co, const char *s, uint count)
1647 struct mpsc_port_info *pi = &mpsc_ports[co->index];
1648 u8 *bp, *dp, add_cr = 0;
1650 unsigned long iflags;
1652 spin_lock_irqsave(&pi->tx_lock, iflags);
1654 while (pi->txr_head != pi->txr_tail) {
1655 while (mpsc_sdma_tx_active(pi))
1657 mpsc_sdma_intr_ack(pi);
1661 while (mpsc_sdma_tx_active(pi))
1665 bp = dp = pi->txb + (pi->txr_head * MPSC_TXBE_SIZE);
1667 for (i = 0; i < MPSC_TXBE_SIZE; i++) {
1678 if (*(s++) == '\n') { /* add '\r' after '\n' */
1687 dma_cache_sync(pi->port.dev, (void *) bp, MPSC_TXBE_SIZE, DMA_BIDIRECTIONAL);
1688 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1689 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1690 flush_dcache_range((ulong)bp,
1691 (ulong)bp + MPSC_TXBE_SIZE);
1693 mpsc_setup_tx_desc(pi, i, 0);
1694 pi->txr_head = (pi->txr_head + 1) & (MPSC_TXR_ENTRIES - 1);
1695 mpsc_sdma_start_tx(pi);
1697 while (mpsc_sdma_tx_active(pi))
1700 pi->txr_tail = (pi->txr_tail + 1) & (MPSC_TXR_ENTRIES - 1);
1703 spin_unlock_irqrestore(&pi->tx_lock, iflags);
1708 mpsc_console_setup(struct console *co, char *options)
1710 struct mpsc_port_info *pi;
1711 int baud, bits, parity, flow;
1713 pr_debug("mpsc_console_setup[%d]: options: %s\n", co->index, options);
1715 if (co->index >= MPSC_NUM_CTLRS)
1718 pi = &mpsc_ports[co->index];
1720 baud = pi->default_baud;
1721 bits = pi->default_bits;
1722 parity = pi->default_parity;
1723 flow = pi->default_flow;
1728 spin_lock_init(&pi->port.lock); /* Temporary fix--copied from 8250.c */
1731 uart_parse_options(options, &baud, &parity, &bits, &flow);
1733 return uart_set_options(&pi->port, co, baud, parity, bits, flow);
1736 static struct console mpsc_console = {
1737 .name = MPSC_DEV_NAME,
1738 .write = mpsc_console_write,
1739 .device = uart_console_device,
1740 .setup = mpsc_console_setup,
1741 .flags = CON_PRINTBUFFER,
1747 mpsc_late_console_init(void)
1749 pr_debug("mpsc_late_console_init: Enter\n");
1751 if (!(mpsc_console.flags & CON_ENABLED))
1752 register_console(&mpsc_console);
1756 late_initcall(mpsc_late_console_init);
1758 #define MPSC_CONSOLE &mpsc_console
1760 #define MPSC_CONSOLE NULL
1763 ******************************************************************************
1765 * Dummy Platform Driver to extract & map shared register regions
1767 ******************************************************************************
1770 mpsc_resource_err(char *s)
1772 printk(KERN_WARNING "MPSC: Platform device resource error in %s\n", s);
1777 mpsc_shared_map_regs(struct platform_device *pd)
1781 if ((r = platform_get_resource(pd, IORESOURCE_MEM,
1782 MPSC_ROUTING_BASE_ORDER)) && request_mem_region(r->start,
1783 MPSC_ROUTING_REG_BLOCK_SIZE, "mpsc_routing_regs")) {
1785 mpsc_shared_regs.mpsc_routing_base = ioremap(r->start,
1786 MPSC_ROUTING_REG_BLOCK_SIZE);
1787 mpsc_shared_regs.mpsc_routing_base_p = r->start;
1790 mpsc_resource_err("MPSC routing base");
1794 if ((r = platform_get_resource(pd, IORESOURCE_MEM,
1795 MPSC_SDMA_INTR_BASE_ORDER)) && request_mem_region(r->start,
1796 MPSC_SDMA_INTR_REG_BLOCK_SIZE, "sdma_intr_regs")) {
1798 mpsc_shared_regs.sdma_intr_base = ioremap(r->start,
1799 MPSC_SDMA_INTR_REG_BLOCK_SIZE);
1800 mpsc_shared_regs.sdma_intr_base_p = r->start;
1803 iounmap(mpsc_shared_regs.mpsc_routing_base);
1804 release_mem_region(mpsc_shared_regs.mpsc_routing_base_p,
1805 MPSC_ROUTING_REG_BLOCK_SIZE);
1806 mpsc_resource_err("SDMA intr base");
1814 mpsc_shared_unmap_regs(void)
1816 if (!mpsc_shared_regs.mpsc_routing_base) {
1817 iounmap(mpsc_shared_regs.mpsc_routing_base);
1818 release_mem_region(mpsc_shared_regs.mpsc_routing_base_p,
1819 MPSC_ROUTING_REG_BLOCK_SIZE);
1821 if (!mpsc_shared_regs.sdma_intr_base) {
1822 iounmap(mpsc_shared_regs.sdma_intr_base);
1823 release_mem_region(mpsc_shared_regs.sdma_intr_base_p,
1824 MPSC_SDMA_INTR_REG_BLOCK_SIZE);
1827 mpsc_shared_regs.mpsc_routing_base = NULL;
1828 mpsc_shared_regs.sdma_intr_base = NULL;
1830 mpsc_shared_regs.mpsc_routing_base_p = 0;
1831 mpsc_shared_regs.sdma_intr_base_p = 0;
1837 mpsc_shared_drv_probe(struct platform_device *dev)
1839 struct mpsc_shared_pdata *pdata;
1843 if (!(rc = mpsc_shared_map_regs(dev))) {
1844 pdata = (struct mpsc_shared_pdata *)dev->dev.platform_data;
1846 mpsc_shared_regs.MPSC_MRR_m = pdata->mrr_val;
1847 mpsc_shared_regs.MPSC_RCRR_m= pdata->rcrr_val;
1848 mpsc_shared_regs.MPSC_TCRR_m= pdata->tcrr_val;
1849 mpsc_shared_regs.SDMA_INTR_CAUSE_m =
1850 pdata->intr_cause_val;
1851 mpsc_shared_regs.SDMA_INTR_MASK_m =
1852 pdata->intr_mask_val;
1862 mpsc_shared_drv_remove(struct platform_device *dev)
1867 mpsc_shared_unmap_regs();
1868 mpsc_shared_regs.MPSC_MRR_m = 0;
1869 mpsc_shared_regs.MPSC_RCRR_m = 0;
1870 mpsc_shared_regs.MPSC_TCRR_m = 0;
1871 mpsc_shared_regs.SDMA_INTR_CAUSE_m = 0;
1872 mpsc_shared_regs.SDMA_INTR_MASK_m = 0;
1879 static struct platform_driver mpsc_shared_driver = {
1880 .probe = mpsc_shared_drv_probe,
1881 .remove = mpsc_shared_drv_remove,
1883 .name = MPSC_SHARED_NAME,
1888 ******************************************************************************
1890 * Driver Interface Routines
1892 ******************************************************************************
1894 static struct uart_driver mpsc_reg = {
1895 .owner = THIS_MODULE,
1896 .driver_name = MPSC_DRIVER_NAME,
1897 .dev_name = MPSC_DEV_NAME,
1898 .major = MPSC_MAJOR,
1899 .minor = MPSC_MINOR_START,
1900 .nr = MPSC_NUM_CTLRS,
1901 .cons = MPSC_CONSOLE,
1905 mpsc_drv_map_regs(struct mpsc_port_info *pi, struct platform_device *pd)
1909 if ((r = platform_get_resource(pd, IORESOURCE_MEM, MPSC_BASE_ORDER)) &&
1910 request_mem_region(r->start, MPSC_REG_BLOCK_SIZE, "mpsc_regs")){
1912 pi->mpsc_base = ioremap(r->start, MPSC_REG_BLOCK_SIZE);
1913 pi->mpsc_base_p = r->start;
1916 mpsc_resource_err("MPSC base");
1920 if ((r = platform_get_resource(pd, IORESOURCE_MEM,
1921 MPSC_SDMA_BASE_ORDER)) && request_mem_region(r->start,
1922 MPSC_SDMA_REG_BLOCK_SIZE, "sdma_regs")) {
1924 pi->sdma_base = ioremap(r->start,MPSC_SDMA_REG_BLOCK_SIZE);
1925 pi->sdma_base_p = r->start;
1928 mpsc_resource_err("SDMA base");
1929 if (pi->mpsc_base) {
1930 iounmap(pi->mpsc_base);
1931 pi->mpsc_base = NULL;
1936 if ((r = platform_get_resource(pd,IORESOURCE_MEM,MPSC_BRG_BASE_ORDER))
1937 && request_mem_region(r->start, MPSC_BRG_REG_BLOCK_SIZE,
1940 pi->brg_base = ioremap(r->start, MPSC_BRG_REG_BLOCK_SIZE);
1941 pi->brg_base_p = r->start;
1944 mpsc_resource_err("BRG base");
1945 if (pi->mpsc_base) {
1946 iounmap(pi->mpsc_base);
1947 pi->mpsc_base = NULL;
1949 if (pi->sdma_base) {
1950 iounmap(pi->sdma_base);
1951 pi->sdma_base = NULL;
1960 mpsc_drv_unmap_regs(struct mpsc_port_info *pi)
1962 if (!pi->mpsc_base) {
1963 iounmap(pi->mpsc_base);
1964 release_mem_region(pi->mpsc_base_p, MPSC_REG_BLOCK_SIZE);
1966 if (!pi->sdma_base) {
1967 iounmap(pi->sdma_base);
1968 release_mem_region(pi->sdma_base_p, MPSC_SDMA_REG_BLOCK_SIZE);
1970 if (!pi->brg_base) {
1971 iounmap(pi->brg_base);
1972 release_mem_region(pi->brg_base_p, MPSC_BRG_REG_BLOCK_SIZE);
1975 pi->mpsc_base = NULL;
1976 pi->sdma_base = NULL;
1977 pi->brg_base = NULL;
1979 pi->mpsc_base_p = 0;
1980 pi->sdma_base_p = 0;
1987 mpsc_drv_get_platform_data(struct mpsc_port_info *pi,
1988 struct platform_device *pd, int num)
1990 struct mpsc_pdata *pdata;
1992 pdata = (struct mpsc_pdata *)pd->dev.platform_data;
1994 pi->port.uartclk = pdata->brg_clk_freq;
1995 pi->port.iotype = UPIO_MEM;
1996 pi->port.line = num;
1997 pi->port.type = PORT_MPSC;
1998 pi->port.fifosize = MPSC_TXBE_SIZE;
1999 pi->port.membase = pi->mpsc_base;
2000 pi->port.mapbase = (ulong)pi->mpsc_base;
2001 pi->port.ops = &mpsc_pops;
2003 pi->mirror_regs = pdata->mirror_regs;
2004 pi->cache_mgmt = pdata->cache_mgmt;
2005 pi->brg_can_tune = pdata->brg_can_tune;
2006 pi->brg_clk_src = pdata->brg_clk_src;
2007 pi->mpsc_max_idle = pdata->max_idle;
2008 pi->default_baud = pdata->default_baud;
2009 pi->default_bits = pdata->default_bits;
2010 pi->default_parity = pdata->default_parity;
2011 pi->default_flow = pdata->default_flow;
2013 /* Initial values of mirrored regs */
2014 pi->MPSC_CHR_1_m = pdata->chr_1_val;
2015 pi->MPSC_CHR_2_m = pdata->chr_2_val;
2016 pi->MPSC_CHR_10_m = pdata->chr_10_val;
2017 pi->MPSC_MPCR_m = pdata->mpcr_val;
2018 pi->BRG_BCR_m = pdata->bcr_val;
2020 pi->shared_regs = &mpsc_shared_regs;
2022 pi->port.irq = platform_get_irq(pd, 0);
2028 mpsc_drv_probe(struct platform_device *dev)
2030 struct mpsc_port_info *pi;
2033 pr_debug("mpsc_drv_probe: Adding MPSC %d\n", dev->id);
2035 if (dev->id < MPSC_NUM_CTLRS) {
2036 pi = &mpsc_ports[dev->id];
2038 if (!(rc = mpsc_drv_map_regs(pi, dev))) {
2039 mpsc_drv_get_platform_data(pi, dev, dev->id);
2041 if (!(rc = mpsc_make_ready(pi))) {
2042 spin_lock_init(&pi->tx_lock);
2043 if (!(rc = uart_add_one_port(&mpsc_reg,
2048 (struct uart_port *)pi);
2049 mpsc_drv_unmap_regs(pi);
2053 mpsc_drv_unmap_regs(pi);
2061 mpsc_drv_remove(struct platform_device *dev)
2063 pr_debug("mpsc_drv_exit: Removing MPSC %d\n", dev->id);
2065 if (dev->id < MPSC_NUM_CTLRS) {
2066 uart_remove_one_port(&mpsc_reg, &mpsc_ports[dev->id].port);
2067 mpsc_release_port((struct uart_port *)&mpsc_ports[dev->id].port);
2068 mpsc_drv_unmap_regs(&mpsc_ports[dev->id]);
2075 static struct platform_driver mpsc_driver = {
2076 .probe = mpsc_drv_probe,
2077 .remove = mpsc_drv_remove,
2079 .name = MPSC_CTLR_NAME,
2088 printk(KERN_INFO "Serial: MPSC driver $Revision: 1.00 $\n");
2090 memset(mpsc_ports, 0, sizeof(mpsc_ports));
2091 memset(&mpsc_shared_regs, 0, sizeof(mpsc_shared_regs));
2093 if (!(rc = uart_register_driver(&mpsc_reg))) {
2094 if (!(rc = platform_driver_register(&mpsc_shared_driver))) {
2095 if ((rc = platform_driver_register(&mpsc_driver))) {
2096 platform_driver_unregister(&mpsc_shared_driver);
2097 uart_unregister_driver(&mpsc_reg);
2101 uart_unregister_driver(&mpsc_reg);
2111 platform_driver_unregister(&mpsc_driver);
2112 platform_driver_unregister(&mpsc_shared_driver);
2113 uart_unregister_driver(&mpsc_reg);
2114 memset(mpsc_ports, 0, sizeof(mpsc_ports));
2115 memset(&mpsc_shared_regs, 0, sizeof(mpsc_shared_regs));
2119 module_init(mpsc_drv_init);
2120 module_exit(mpsc_drv_exit);
2122 MODULE_AUTHOR("Mark A. Greer <mgreer@mvista.com>");
2123 MODULE_DESCRIPTION("Generic Marvell MPSC serial/UART driver $Revision: 1.00 $");
2124 MODULE_VERSION(MPSC_VERSION);
2125 MODULE_LICENSE("GPL");
2126 MODULE_ALIAS_CHARDEV_MAJOR(MPSC_MAJOR);